1 files changed, 159 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/mach-stm32mp/spl.c b/roms/u-boot/arch/arm/mach-stm32mp/spl.c
new file mode 100644
index 000000000..b53659a69
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-stm32mp/spl.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/libfdt.h>
+
+u32 spl_boot_device(void)
+{
+	u32 boot_mode;
+
+	boot_mode = get_bootmode();
+
+	switch (boot_mode) {
+	case BOOT_FLASH_SD_1:
+	case BOOT_FLASH_EMMC_1:
+		return BOOT_DEVICE_MMC1;
+	case BOOT_FLASH_SD_2:
+	case BOOT_FLASH_EMMC_2:
+		return BOOT_DEVICE_MMC2;
+	case BOOT_SERIAL_UART_1:
+	case BOOT_SERIAL_UART_2:
+	case BOOT_SERIAL_UART_3:
+	case BOOT_SERIAL_UART_4:
+	case BOOT_SERIAL_UART_5:
+	case BOOT_SERIAL_UART_6:
+	case BOOT_SERIAL_UART_7:
+	case BOOT_SERIAL_UART_8:
+		return BOOT_DEVICE_UART;
+	case BOOT_SERIAL_USB_OTG:
+		return BOOT_DEVICE_USB;
+	case BOOT_FLASH_NAND_FMC:
+		return BOOT_DEVICE_NAND;
+	case BOOT_FLASH_NOR_QSPI:
+		return BOOT_DEVICE_SPI;
+	case BOOT_FLASH_SPINAND_1:
+		return BOOT_DEVICE_NONE; /* SPINAND not supported in SPL */
+	}
+
+	return BOOT_DEVICE_MMC1;
+}
+
+u32 spl_mmc_boot_mode(const u32 boot_device)
+{
+	return MMCSD_MODE_RAW;
+}
+
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+int spl_mmc_boot_partition(const u32 boot_device)
+{
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+		return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION;
+	case BOOT_DEVICE_MMC2:
+		return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2;
+	default:
+		return -EINVAL;
+	}
+}
+#endif
+
+#ifdef CONFIG_SPL_DISPLAY_PRINT
+void spl_display_print(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	const char *model;
+
+	/* same code than show_board_info() but not compiled for SPL
+	 * see CONFIG_DISPLAY_BOARDINFO & common/board_info.c
+	 */
+	model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+	if (model)
+		log_info("Model: %s\n", model);
+}
+#endif
+
+__weak int board_early_init_f(void)
+{
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+	arch_cpu_init();
+
+	ret = spl_early_init();
+	if (ret) {
+		log_debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	if (ret) {
+		log_debug("Clock init failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+	if (ret) {
+		log_debug("Reset init failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
+	if (ret) {
+		log_debug("%s: Cannot find pinctrl device\n", __func__);
+		hang();
+	}
+
+	/* enable console uart printing */
+	preloader_console_init();
+
+	ret = board_early_init_f();
+	if (ret) {
+		log_debug("board_early_init_f() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		log_err("DRAM init failed: %d\n", ret);
+		hang();
+	}
+
+	/*
+	 * activate cache on DDR only when DDR is fully initialized
+	 * to avoid speculative access and issue in get_ram_size()
+	 */
+	if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+		mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
+						CONFIG_DDR_CACHEABLE_SIZE,
+						DCACHE_DEFAULT_OPTION);
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	dcache_disable();
+}
+
+void spl_board_prepare_for_linux(void)
+{
+	dcache_disable();
+}