diff options
Diffstat (limited to 'roms/u-boot/arch/mips/mach-pic32')
| -rw-r--r-- | roms/u-boot/arch/mips/mach-pic32/Kconfig | 36 | ||||
| -rw-r--r-- | roms/u-boot/arch/mips/mach-pic32/Makefile | 7 | ||||
| -rw-r--r-- | roms/u-boot/arch/mips/mach-pic32/cpu.c | 171 | ||||
| -rw-r--r-- | roms/u-boot/arch/mips/mach-pic32/include/mach/ddr.h | 31 | ||||
| -rw-r--r-- | roms/u-boot/arch/mips/mach-pic32/include/mach/pic32.h | 78 | ||||
| -rw-r--r-- | roms/u-boot/arch/mips/mach-pic32/lowlevel_init.S | 26 | ||||
| -rw-r--r-- | roms/u-boot/arch/mips/mach-pic32/reset.c | 35 |
7 files changed, 384 insertions, 0 deletions
diff --git a/roms/u-boot/arch/mips/mach-pic32/Kconfig b/roms/u-boot/arch/mips/mach-pic32/Kconfig new file mode 100644 index 000000000..5f13bf14e --- /dev/null +++ b/roms/u-boot/arch/mips/mach-pic32/Kconfig @@ -0,0 +1,36 @@ +menu "Microchip PIC32 platforms" + depends on MACH_PIC32 + +config SYS_SOC + default "pic32mzda" if SOC_PIC32MZDA + +choice + prompt "PIC32 SoC select" + +config SOC_PIC32MZDA + bool "Microchip PIC32MZ[DA] family" + select MIPS_L1_CACHE_SHIFT_4 + select ROM_EXCEPTION_VECTORS + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + select SYS_MIPS_CACHE_INIT_RAM_LOAD + help + This supports Microchip PIC32MZ[DA] family of microcontrollers. + +endchoice + +choice + prompt "Board select" + +config TARGET_PIC32MZDASK + bool "Microchip PIC32MZ[DA] Starter Kit" + depends on SOC_PIC32MZDA + help + This supports Microchip PIC32MZ[DA] Starter Kit. + +endchoice + +source "board/microchip/pic32mzda/Kconfig" + +endmenu diff --git a/roms/u-boot/arch/mips/mach-pic32/Makefile b/roms/u-boot/arch/mips/mach-pic32/Makefile new file mode 100644 index 000000000..e321e65fd --- /dev/null +++ b/roms/u-boot/arch/mips/mach-pic32/Makefile @@ -0,0 +1,7 @@ +# (C) Copyright 2015 +# Purna Chandra Mandal, purna.mandal@microchip.com. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = cpu.o lowlevel_init.o reset.o
\ No newline at end of file diff --git a/roms/u-boot/arch/mips/mach-pic32/cpu.c b/roms/u-boot/arch/mips/mach-pic32/cpu.c new file mode 100644 index 000000000..eac2fe5f8 --- /dev/null +++ b/roms/u-boot/arch/mips/mach-pic32/cpu.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 + * Purna Chandra Mandal <purna.mandal@microchip.com> + * + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <init.h> +#include <malloc.h> +#include <asm/global_data.h> +#include <mach/pic32.h> +#include <mach/ddr.h> +#include <dt-bindings/clock/microchip,clock.h> + +/* Flash prefetch */ +#define PRECON 0x00 + +/* Flash ECCCON */ +#define ECC_MASK 0x03 +#define ECC_SHIFT 4 + +#define CLK_MHZ(x) ((x) / 1000000) + +DECLARE_GLOBAL_DATA_PTR; + +static ulong rate(int id) +{ + int ret; + struct udevice *dev; + struct clk clk; + ulong rate; + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + printf("clk-uclass not found\n"); + return 0; + } + + clk.id = id; + ret = clk_request(dev, &clk); + if (ret < 0) + return ret; + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + return rate; +} + +static ulong clk_get_cpu_rate(void) +{ + return rate(PB7CLK); +} + +/* initialize prefetch module related to cpu_clk */ +static void prefetch_init(void) +{ + struct pic32_reg_atomic *regs; + const void __iomem *base; + int v, nr_waits; + ulong rate; + + /* cpu frequency in MHZ */ + rate = clk_get_cpu_rate() / 1000000; + + /* get flash ECC type */ + base = pic32_get_syscfg_base(); + v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK; + + if (v < 2) { + if (rate < 66) + nr_waits = 0; + else if (rate < 133) + nr_waits = 1; + else + nr_waits = 2; + } else { + if (rate <= 83) + nr_waits = 0; + else if (rate <= 166) + nr_waits = 1; + else + nr_waits = 2; + } + + regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs)); + writel(nr_waits, ®s->raw); + + /* Enable prefetch for all */ + writel(0x30, ®s->set); + iounmap(regs); +} + +/* arch specific CPU init after DM */ +int arch_cpu_init_dm(void) +{ + /* flash prefetch */ + prefetch_init(); + return 0; +} + +/* Un-gate DDR2 modules (gated by default) */ +static void ddr2_pmd_ungate(void) +{ + void __iomem *regs; + + regs = pic32_get_syscfg_base(); + writel(0, regs + PMD7); +} + +/* initialize the DDR2 Controller and DDR2 PHY */ +int dram_init(void) +{ + ddr2_pmd_ungate(); + ddr2_phy_init(); + ddr2_ctrl_init(); + gd->ram_size = ddr2_calculate_size(); + + return 0; +} + +int misc_init_r(void) +{ + set_io_port_base(0); + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +const char *get_core_name(void) +{ + u32 proc_id; + const char *str; + + proc_id = read_c0_prid(); + switch (proc_id) { + case 0x19e28: + str = "PIC32MZ[DA]"; + break; + default: + str = "UNKNOWN"; + } + + return str; +} +#endif +#ifdef CONFIG_CMD_CLK + +int soc_clk_dump(void) +{ + int i; + + printf("PLL Speed: %lu MHz\n", + CLK_MHZ(rate(PLLCLK))); + + printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK))); + + printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL))); + + for (i = PB1CLK; i <= PB7CLK; i++) + printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1, + CLK_MHZ(rate(i))); + + for (i = REF1CLK; i <= REF5CLK; i++) + printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1, + CLK_MHZ(rate(i))); + return 0; +} +#endif diff --git a/roms/u-boot/arch/mips/mach-pic32/include/mach/ddr.h b/roms/u-boot/arch/mips/mach-pic32/include/mach/ddr.h new file mode 100644 index 000000000..1b2391e01 --- /dev/null +++ b/roms/u-boot/arch/mips/mach-pic32/include/mach/ddr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + */ + +#ifndef __MICROCHIP_PIC32_DDR_H +#define __MICROCHIP_PIC32_DDR_H + +/* called by dram_init() function */ +void ddr2_phy_init(void); +void ddr2_ctrl_init(void); +phys_size_t ddr2_calculate_size(void); + +/* Maximum number of agents */ +#define NUM_AGENTS 5 + +/* Board can provide agent specific parameters for arbitration by + * filling struct ddr2_arbiter_params for all the agents and + * implementing board_get_ddr_arbiter_params() to return the filled + * structure. + */ +struct ddr2_arbiter_params { + u32 min_limit; /* min bursts to execute per arbitration */ + u32 req_period; /* request period threshold for accepted cmds */ + u32 min_cmd_acpt; /* min number of accepted cmds */ +}; + +const struct ddr2_arbiter_params *board_get_ddr_arbiter_params(void); + +#endif /* __MICROCHIP_PIC32_DDR_H */ diff --git a/roms/u-boot/arch/mips/mach-pic32/include/mach/pic32.h b/roms/u-boot/arch/mips/mach-pic32/include/mach/pic32.h new file mode 100644 index 000000000..69015334b --- /dev/null +++ b/roms/u-boot/arch/mips/mach-pic32/include/mach/pic32.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2015 Paul Thacker <paul.thacker@microchip.com> + * + */ + +#ifndef __PIC32_REGS_H__ +#define __PIC32_REGS_H__ + +#include <asm/io.h> + +/* System Configuration */ +#define PIC32_CFG_BASE 0x1f800000 + +/* System config register offsets */ +#define CFGCON 0x0000 +#define DEVID 0x0020 +#define SYSKEY 0x0030 +#define PMD1 0x0040 +#define PMD7 0x00a0 +#define CFGEBIA 0x00c0 +#define CFGEBIC 0x00d0 +#define CFGPG 0x00e0 +#define CFGMPLL 0x0100 + +/* Non Volatile Memory (NOR flash) */ +#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600) +/* Oscillator Configuration */ +#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200) +/* Peripheral Pin Select Input */ +#define PPS_IN_BASE 0x1f801400 +/* Peripheral Pin Select Output */ +#define PPS_OUT_BASE 0x1f801500 +/* Pin Config */ +#define PINCTRL_BASE 0x1f860000 + +/* USB Core */ +#define PIC32_USB_CORE_BASE 0x1f8e3000 +#define PIC32_USB_CTRL_BASE 0x1f884000 + +/* SPI1-SPI6 */ +#define PIC32_SPI1_BASE 0x1f821000 + +/* Prefetch Module */ +#define PREFETCH_BASE 0x1f8e0000 + +/* DDR2 Controller */ +#define PIC32_DDR2C_BASE 0x1f8e8000 + +/* DDR2 PHY */ +#define PIC32_DDR2P_BASE 0x1f8e9100 + +/* EBI */ +#define PIC32_EBI_BASE 0x1f8e1000 + +/* SQI */ +#define PIC32_SQI_BASE 0x1f8e2000 + +struct pic32_reg_atomic { + u32 raw; + u32 clr; + u32 set; + u32 inv; +}; + +#define _CLR_OFFSET 0x04 +#define _SET_OFFSET 0x08 +#define _INV_OFFSET 0x0c + +static inline void __iomem *pic32_get_syscfg_base(void) +{ + return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE); +} + +/* Core */ +const char *get_core_name(void); + +#endif /* __PIC32_REGS_H__ */ diff --git a/roms/u-boot/arch/mips/mach-pic32/lowlevel_init.S b/roms/u-boot/arch/mips/mach-pic32/lowlevel_init.S new file mode 100644 index 000000000..6ecea5ca9 --- /dev/null +++ b/roms/u-boot/arch/mips/mach-pic32/lowlevel_init.S @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * +*/ + +#include <config.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/asm.h> + +LEAF(lowlevel_init) + /* + * Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + + jr ra + nop + END(lowlevel_init) diff --git a/roms/u-boot/arch/mips/mach-pic32/reset.c b/roms/u-boot/arch/mips/mach-pic32/reset.c new file mode 100644 index 000000000..8071b13f7 --- /dev/null +++ b/roms/u-boot/arch/mips/mach-pic32/reset.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/pic32.h> + +/* SYSKEY */ +#define UNLOCK_KEY1 0xaa996655 +#define UNLOCK_KEY2 0x556699aa +#define LOCK_KEY 0 + +#define RSWRST 0x1250 + +void _machine_restart(void) +{ + void __iomem *base; + + base = pic32_get_syscfg_base(); + + /* unlock sequence */ + writel(LOCK_KEY, base + SYSKEY); + writel(UNLOCK_KEY1, base + SYSKEY); + writel(UNLOCK_KEY2, base + SYSKEY); + + /* soft reset */ + writel(0x1, base + RSWRST); + (void) readl(base + RSWRST); + + while (1) + ; +} |