diff options
Diffstat (limited to 'roms/u-boot/arch/riscv/dts')
20 files changed, 6322 insertions, 0 deletions
diff --git a/roms/u-boot/arch/riscv/dts/Makefile b/roms/u-boot/arch/riscv/dts/Makefile new file mode 100644 index 000000000..777887483 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/Makefile @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0+ + +dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb +dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb +dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb +dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb +dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/roms/u-boot/arch/riscv/dts/ae350-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/ae350-u-boot.dtsi new file mode 100644 index 000000000..0d4201cfa --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/ae350-u-boot.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + cpus { + u-boot,dm-spl; + CPU0: cpu@0 { + u-boot,dm-spl; + CPU0_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + CPU1: cpu@1 { + u-boot,dm-spl; + CPU1_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + CPU2: cpu@2 { + u-boot,dm-spl; + CPU2_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + CPU3: cpu@3 { + u-boot,dm-spl; + CPU3_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + }; + + memory@0 { + u-boot,dm-spl; + }; + + soc { + u-boot,dm-spl; + + plic1: interrupt-controller@e6400000 { + u-boot,dm-spl; + }; + + plmt0@e6000000 { + u-boot,dm-spl; + }; + }; + + serial0: serial@f0300000 { + u-boot,dm-spl; + }; + +}; diff --git a/roms/u-boot/arch/riscv/dts/ae350_32.dts b/roms/u-boot/arch/riscv/dts/ae350_32.dts new file mode 100644 index 000000000..083f67633 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/ae350_32.dts @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "binman.dtsi" +#include "ae350-u-boot.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "andestech,a25"; + model = "andestech,a25"; + + aliases { + uart0 = &serial0; + spi0 = &spi; + }; + + chosen { + bootargs = "console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <60000000>; + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv32"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + CPU1: cpu@1 { + device_type = "cpu"; + reg = <1>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv32"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU1_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + CPU2: cpu@2 { + device_type = "cpu"; + reg = <2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv32"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU2_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + CPU3: cpu@3 { + device_type = "cpu"; + reg = <3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv32"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU3_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + L2: l2-cache@e0500000 { + compatible = "v5l2cache"; + cache-level = <2>; + cache-size = <0x40000>; + reg = <0xe0500000 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is <XRAMOCTL XRAMICTL> */ + andes,tag-ram-ctl = <0 0>; + andes,data-ram-ctl = <0 0>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + plic0: interrupt-controller@e4000000 { + compatible = "riscv,plic0"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0xe4000000 0x2000000>; + riscv,ndev=<71>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 + &CPU1_intc 11 &CPU1_intc 9 + &CPU2_intc 11 &CPU2_intc 9 + &CPU3_intc 11 &CPU3_intc 9>; + }; + + plic1: interrupt-controller@e6400000 { + compatible = "riscv,plic1"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xe6400000 0x400000>; + riscv,ndev=<2>; + interrupts-extended = <&CPU0_intc 3 + &CPU1_intc 3 + &CPU2_intc 3 + &CPU3_intc 3>; + }; + + plmt0@e6000000 { + compatible = "riscv,plmt0"; + interrupts-extended = <&CPU0_intc 7 + &CPU1_intc 7 + &CPU2_intc 7 + &CPU3_intc 7>; + reg = <0xe6000000 0x100000>; + }; + }; + + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + clock-frequency = <60000000>; + interrupts = <3 4>; + interrupt-parent = <&plic0>; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <9 4>; + clock-frequency = <19660800>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + interrupt-parent = <&plic0>; + }; + + mac0: mac@e0100000 { + compatible = "andestech,atmac100"; + reg = <0xe0100000 0x1000>; + interrupts = <19 4>; + interrupt-parent = <&plic0>; + }; + + mmc0: mmc@f0e00000 { + compatible = "andestech,atfsdc010"; + max-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; + fifo-depth = <0x10>; + reg = <0xf0e00000 0x1000>; + interrupts = <18 4>; + cap-sd-highspeed; + interrupt-parent = <&plic0>; + }; + + dma0: dma@f0c00000 { + compatible = "andestech,atcdmac300"; + reg = <0xf0c00000 0x1000>; + interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; + dma-channels = <8>; + interrupt-parent = <&plic0>; + }; + + lcd0: lcd@e0200000 { + compatible = "andestech,atflcdc100"; + reg = <0xe0200000 0x1000>; + interrupts = <20 4>; + interrupt-parent = <&plic0>; + }; + + smc0: smc@e0400000 { + compatible = "andestech,atfsmc020"; + reg = <0xe0400000 0x1000>; + }; + + snd0: snd@f0d00000 { + compatible = "andestech,atfac97"; + reg = <0xf0d00000 0x1000>; + interrupts = <17 4>; + interrupt-parent = <&plic0>; + }; + + pmu { + compatible = "riscv,base-pmu"; + }; + + virtio_mmio@fe007000 { + interrupts = <0x17 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe007000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe006000 { + interrupts = <0x16 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe006000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe005000 { + interrupts = <0x15 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe005000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe004000 { + interrupts = <0x14 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe004000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe003000 { + interrupts = <0x13 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe003000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe002000 { + interrupts = <0x12 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe002000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe001000 { + interrupts = <0x11 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe001000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe000000 { + interrupts = <0x10 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe000000 0x1000>; + compatible = "virtio,mmio"; + }; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x88000000 0x4000000>; + bank-width = <2>; + device-width = <1>; + }; + + spi: spi@f0b00000 { + compatible = "andestech,atcspi200"; + reg = <0xf0b00000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + clocks = <&spiclk>; + interrupts = <4 4>; + interrupt-parent = <&plic0>; + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-cpol; + spi-cpha; + }; + }; +}; diff --git a/roms/u-boot/arch/riscv/dts/ae350_64.dts b/roms/u-boot/arch/riscv/dts/ae350_64.dts new file mode 100644 index 000000000..74cff9122 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/ae350_64.dts @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "binman.dtsi" +#include "ae350-u-boot.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,ax25"; + model = "andestech,ax25"; + + aliases { + uart0 = &serial0; + spi0 = &spi; + }; + + chosen { + bootargs = "console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <60000000>; + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + CPU1: cpu@1 { + device_type = "cpu"; + reg = <1>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU1_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + CPU2: cpu@2 { + device_type = "cpu"; + reg = <2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU2_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + CPU3: cpu@3 { + device_type = "cpu"; + reg = <3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <1>; + riscv,priv-minor = <10>; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; + CPU3_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + L2: l2-cache@e0500000 { + compatible = "v5l2cache"; + cache-level = <2>; + cache-size = <0x40000>; + reg = <0x0 0xe0500000 0x0 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is <XRAMOCTL XRAMICTL> */ + andes,tag-ram-ctl = <0 0>; + andes,data-ram-ctl = <0 0>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x40000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + plic0: interrupt-controller@e4000000 { + compatible = "riscv,plic0"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x0 0xe4000000 0x0 0x2000000>; + riscv,ndev=<71>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 + &CPU1_intc 11 &CPU1_intc 9 + &CPU2_intc 11 &CPU2_intc 9 + &CPU3_intc 11 &CPU3_intc 9>; + }; + + plic1: interrupt-controller@e6400000 { + compatible = "riscv,plic1"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x0 0xe6400000 0x0 0x400000>; + riscv,ndev=<2>; + interrupts-extended = <&CPU0_intc 3 + &CPU1_intc 3 + &CPU2_intc 3 + &CPU3_intc 3>; + }; + + plmt0@e6000000 { + compatible = "riscv,plmt0"; + interrupts-extended = <&CPU0_intc 7 + &CPU1_intc 7 + &CPU2_intc 7 + &CPU3_intc 7>; + reg = <0x0 0xe6000000 0x0 0x100000>; + }; + }; + + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0x0 0xf0400000 0x0 0x1000>; + clock-frequency = <60000000>; + interrupts = <3 4>; + interrupt-parent = <&plic0>; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x0 0xf0300000 0x0 0x1000>; + interrupts = <9 4>; + clock-frequency = <19660800>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + interrupt-parent = <&plic0>; + }; + + mac0: mac@e0100000 { + compatible = "andestech,atmac100"; + reg = <0x0 0xe0100000 0x0 0x1000>; + interrupts = <19 4>; + interrupt-parent = <&plic0>; + }; + + mmc0: mmc@f0e00000 { + compatible = "andestech,atfsdc010"; + max-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; + fifo-depth = <0x10>; + reg = <0x0 0xf0e00000 0x0 0x1000>; + interrupts = <18 4>; + cap-sd-highspeed; + interrupt-parent = <&plic0>; + }; + + dma0: dma@f0c00000 { + compatible = "andestech,atcdmac300"; + reg = <0x0 0xf0c00000 0x0 0x1000>; + interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; + dma-channels = <8>; + interrupt-parent = <&plic0>; + }; + + lcd0: lcd@e0200000 { + compatible = "andestech,atflcdc100"; + reg = <0x0 0xe0200000 0x0 0x1000>; + interrupts = <20 4>; + interrupt-parent = <&plic0>; + }; + + smc0: smc@e0400000 { + compatible = "andestech,atfsmc020"; + reg = <0x0 0xe0400000 0x0 0x1000>; + }; + + snd0: snd@f0d00000 { + compatible = "andestech,atfac97"; + reg = <0x0 0xf0d00000 0x0 0x1000>; + interrupts = <17 4>; + interrupt-parent = <&plic0>; + }; + + pmu { + compatible = "riscv,base-pmu"; + }; + + virtio_mmio@fe007000 { + interrupts = <0x17 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe007000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe006000 { + interrupts = <0x16 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe006000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe005000 { + interrupts = <0x15 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe005000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe004000 { + interrupts = <0x14 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe004000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe003000 { + interrupts = <0x13 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe003000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe002000 { + interrupts = <0x12 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe002000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe001000 { + interrupts = <0x11 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe001000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe000000 { + interrupts = <0x10 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe000000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + nor@0,0 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "cfi-flash"; + reg = <0x0 0x88000000 0x0 0x4000000>; + bank-width = <2>; + device-width = <1>; + }; + + spi: spi@f0b00000 { + compatible = "andestech,atcspi200"; + reg = <0x0 0xf0b00000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + clocks = <&spiclk>; + interrupts = <4 4>; + interrupt-parent = <&plic0>; + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-cpol; + spi-cpha; + }; + }; +}; diff --git a/roms/u-boot/arch/riscv/dts/binman.dtsi b/roms/u-boot/arch/riscv/dts/binman.dtsi new file mode 100644 index 000000000..d26cfdb78 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/binman.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <config.h> + +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load OpenSBI before U-Boot"; + #address-cells = <1>; + fit,fdt-list = "of-list"; + + images { + uboot { + description = "U-Boot"; + type = "standalone"; + os = "U-Boot"; + arch = "riscv"; + compression = "none"; + load = <CONFIG_SYS_TEXT_BASE>; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + opensbi { + description = "OpenSBI fw_dynamic Firmware"; + type = "firmware"; + os = "opensbi"; + arch = "riscv"; + compression = "none"; + load = <CONFIG_SPL_OPENSBI_LOAD_ADDR>; + entry = <CONFIG_SPL_OPENSBI_LOAD_ADDR>; + + opensbi_blob: opensbi { + filename = "fw_dynamic.bin"; + }; + }; + +#ifndef CONFIG_OF_PRIOR_STAGE + @fdt-SEQ { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + }; +#endif + }; + + configurations { + default = "conf-1"; + +#ifndef CONFIG_OF_PRIOR_STAGE + @conf-SEQ { +#else + conf-1 { +#endif + description = "NAME"; + firmware = "opensbi"; + loadables = "uboot"; +#ifndef CONFIG_OF_PRIOR_STAGE + fdt = "fdt-SEQ"; +#endif + }; + }; + }; + }; +}; diff --git a/roms/u-boot/arch/riscv/dts/fu540-c000-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/fu540-c000-u-boot.dtsi new file mode 100644 index 000000000..b7cd600b8 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) Copyright 2019 SiFive, Inc + */ + +#include <dt-bindings/reset/sifive-fu540-prci.h> + +/ { + cpus { + assigned-clocks = <&prci PRCI_CLK_COREPLL>; + assigned-clock-rates = <1000000000>; + u-boot,dm-spl; + cpu0: cpu@0 { + clocks = <&prci PRCI_CLK_COREPLL>; + u-boot,dm-spl; + status = "okay"; + cpu0_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + cpu1: cpu@1 { + clocks = <&prci PRCI_CLK_COREPLL>; + u-boot,dm-spl; + cpu1_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + cpu2: cpu@2 { + clocks = <&prci PRCI_CLK_COREPLL>; + u-boot,dm-spl; + cpu2_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + cpu3: cpu@3 { + clocks = <&prci PRCI_CLK_COREPLL>; + u-boot,dm-spl; + cpu3_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + cpu4: cpu@4 { + clocks = <&prci PRCI_CLK_COREPLL>; + u-boot,dm-spl; + cpu4_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + }; + + soc { + u-boot,dm-spl; + otp: otp@10070000 { + compatible = "sifive,fu540-c000-otp"; + reg = <0x0 0x10070000 0x0 0x1000>; + fuse-count = <0x1000>; + }; + clint: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + u-boot,dm-spl; + }; + prci: clock-controller@10000000 { + #reset-cells = <1>; + resets = <&prci PRCI_RST_DDR_CTRL_N>, + <&prci PRCI_RST_DDR_AXI_N>, + <&prci PRCI_RST_DDR_AHB_N>, + <&prci PRCI_RST_DDR_PHY_N>, + <&prci PRCI_RST_GEMGXL_N>; + reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", + "ddr_phy", "gemgxl_reset"; + }; + dmc: dmc@100b0000 { + compatible = "sifive,fu540-c000-ddr"; + reg = <0x0 0x100b0000 0x0 0x0800 + 0x0 0x100b2000 0x0 0x2000 + 0x0 0x100b8000 0x0 0x1000>; + clocks = <&prci PRCI_CLK_DDRPLL>; + clock-frequency = <933333324>; + u-boot,dm-spl; + }; + }; +}; + +&prci { + u-boot,dm-spl; +}; + +&uart0 { + u-boot,dm-spl; +}; + +&qspi2 { + u-boot,dm-spl; +}; + +ð0 { + assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clock-rates = <125000000>; +}; + +&l2cache { + status = "okay"; +}; diff --git a/roms/u-boot/arch/riscv/dts/fu540-c000.dtsi b/roms/u-boot/arch/riscv/dts/fu540-c000.dtsi new file mode 100644 index 000000000..7db861053 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/fu540-c000.dtsi @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include <dt-bindings/clock/sifive-fu540-prci.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = ð0; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + next-level-cache = <&l2cache>; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + next-level-cache = <&l2cache>; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + next-level-cache = <&l2cache>; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + next-level-cache = <&l2cache>; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + dma: dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic0>; + interrupts = <23 24 25 26 27 28 29 30>; + #dma-cells = <1>; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci PRCI_CLK_TLCLK>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci PRCI_CLK_TLCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm0: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <42 43 44 45>; + clocks = <&prci PRCI_CLK_TLCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm1: pwm@10021000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10021000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <46 47 48 49>; + clocks = <&prci PRCI_CLK_TLCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + l2cache: cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic0>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; + interrupt-parent = <&plic0>; + interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, + <14>, <15>, <16>, <17>, <18>, <19>, <20>, + <21>, <22>; + reg = <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&prci PRCI_CLK_TLCLK>; + status = "disabled"; + }; + }; +}; diff --git a/roms/u-boot/arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi b/roms/u-boot/arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi new file mode 100644 index 000000000..6ed5ccdbc --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi @@ -0,0 +1,1489 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) Copyright 2020 SiFive, Inc + */ + +&dmc { + sifive,ddr-params = < + 0x00000a00 /* DENALI_CTL_00_DATA */ + 0x00000000 /* DENALI_CTL_01_DATA */ + 0x00000000 /* DENALI_CTL_02_DATA */ + 0x00000000 /* DENALI_CTL_03_DATA */ + 0x00000000 /* DENALI_CTL_04_DATA */ + 0x00000000 /* DENALI_CTL_05_DATA */ + 0x0000000a /* DENALI_CTL_06_DATA */ + 0x0002d362 /* DENALI_CTL_07_DATA */ + 0x00071073 /* DENALI_CTL_08_DATA */ + 0x0a1c0255 /* DENALI_CTL_09_DATA */ + 0x1c1c0400 /* DENALI_CTL_10_DATA */ + 0x0404990b /* DENALI_CTL_11_DATA */ + 0x2b050405 /* DENALI_CTL_12_DATA */ + 0x0e0c081e /* DENALI_CTL_13_DATA */ + 0x08090914 /* DENALI_CTL_14_DATA */ + 0x00fde718 /* DENALI_CTL_15_DATA */ + 0x00180a05 /* DENALI_CTL_16_DATA */ + 0x008b130e /* DENALI_CTL_17_DATA */ + 0x01000118 /* DENALI_CTL_18_DATA */ + 0x0e032101 /* DENALI_CTL_19_DATA */ + 0x00000000 /* DENALI_CTL_20_DATA */ + 0x00000101 /* DENALI_CTL_21_DATA */ + 0x00000000 /* DENALI_CTL_22_DATA */ + 0x0a000000 /* DENALI_CTL_23_DATA */ + 0x00000000 /* DENALI_CTL_24_DATA */ + 0x01450100 /* DENALI_CTL_25_DATA */ + 0x00001c36 /* DENALI_CTL_26_DATA */ + 0x00000005 /* DENALI_CTL_27_DATA */ + 0x00170006 /* DENALI_CTL_28_DATA */ + 0x014e0300 /* DENALI_CTL_29_DATA */ + 0x03010000 /* DENALI_CTL_30_DATA */ + 0x000a0e00 /* DENALI_CTL_31_DATA */ + 0x04030200 /* DENALI_CTL_32_DATA */ + 0x0000031f /* DENALI_CTL_33_DATA */ + 0x00070004 /* DENALI_CTL_34_DATA */ + 0x00000000 /* DENALI_CTL_35_DATA */ + 0x00000000 /* DENALI_CTL_36_DATA */ + 0x00000000 /* DENALI_CTL_37_DATA */ + 0x00000000 /* DENALI_CTL_38_DATA */ + 0x00000000 /* DENALI_CTL_39_DATA */ + 0x00000000 /* DENALI_CTL_40_DATA */ + 0x00000000 /* DENALI_CTL_41_DATA */ + 0x00000000 /* DENALI_CTL_42_DATA */ + 0x00000000 /* DENALI_CTL_43_DATA */ + 0x00000000 /* DENALI_CTL_44_DATA */ + 0x00000000 /* DENALI_CTL_45_DATA */ + 0x00000000 /* DENALI_CTL_46_DATA */ + 0x00000000 /* DENALI_CTL_47_DATA */ + 0x00000000 /* DENALI_CTL_48_DATA */ + 0x00000000 /* DENALI_CTL_49_DATA */ + 0x00000000 /* DENALI_CTL_50_DATA */ + 0x00000000 /* DENALI_CTL_51_DATA */ + 0x00000000 /* DENALI_CTL_52_DATA */ + 0x00000000 /* DENALI_CTL_53_DATA */ + 0x00000000 /* DENALI_CTL_54_DATA */ + 0x00000000 /* DENALI_CTL_55_DATA */ + 0x00000000 /* DENALI_CTL_56_DATA */ + 0x00000000 /* DENALI_CTL_57_DATA */ + 0x00000000 /* DENALI_CTL_58_DATA */ + 0x00000000 /* DENALI_CTL_59_DATA */ + 0x00000424 /* DENALI_CTL_60_DATA */ + 0x00000201 /* DENALI_CTL_61_DATA */ + 0x00001008 /* DENALI_CTL_62_DATA */ + 0x00000000 /* DENALI_CTL_63_DATA */ + 0x00000200 /* DENALI_CTL_64_DATA */ + 0x00000000 /* DENALI_CTL_65_DATA */ + 0x00000481 /* DENALI_CTL_66_DATA */ + 0x00000400 /* DENALI_CTL_67_DATA */ + 0x00000424 /* DENALI_CTL_68_DATA */ + 0x00000201 /* DENALI_CTL_69_DATA */ + 0x00001008 /* DENALI_CTL_70_DATA */ + 0x00000000 /* DENALI_CTL_71_DATA */ + 0x00000200 /* DENALI_CTL_72_DATA */ + 0x00000000 /* DENALI_CTL_73_DATA */ + 0x00000481 /* DENALI_CTL_74_DATA */ + 0x00000400 /* DENALI_CTL_75_DATA */ + 0x01010000 /* DENALI_CTL_76_DATA */ + 0x00000000 /* DENALI_CTL_77_DATA */ + 0x00000000 /* DENALI_CTL_78_DATA */ + 0x00000000 /* DENALI_CTL_79_DATA */ + 0x00000000 /* DENALI_CTL_80_DATA */ + 0x00000000 /* DENALI_CTL_81_DATA */ + 0x00000000 /* DENALI_CTL_82_DATA */ + 0x00000000 /* DENALI_CTL_83_DATA */ + 0x00000000 /* DENALI_CTL_84_DATA */ + 0x00000000 /* DENALI_CTL_85_DATA */ + 0x00000000 /* DENALI_CTL_86_DATA */ + 0x00000000 /* DENALI_CTL_87_DATA */ + 0x00000000 /* DENALI_CTL_88_DATA */ + 0x00000000 /* DENALI_CTL_89_DATA */ + 0x00000000 /* DENALI_CTL_90_DATA */ + 0x00000000 /* DENALI_CTL_91_DATA */ + 0x00000000 /* DENALI_CTL_92_DATA */ + 0x00000000 /* DENALI_CTL_93_DATA */ + 0x00000000 /* DENALI_CTL_94_DATA */ + 0x00000000 /* DENALI_CTL_95_DATA */ + 0x00000000 /* DENALI_CTL_96_DATA */ + 0x00000000 /* DENALI_CTL_97_DATA */ + 0x00000000 /* DENALI_CTL_98_DATA */ + 0x00000000 /* DENALI_CTL_99_DATA */ + 0x00000000 /* DENALI_CTL_100_DATA */ + 0x00000000 /* DENALI_CTL_101_DATA */ + 0x00000000 /* DENALI_CTL_102_DATA */ + 0x00000000 /* DENALI_CTL_103_DATA */ + 0x00000000 /* DENALI_CTL_104_DATA */ + 0x00000003 /* DENALI_CTL_105_DATA */ + 0x00000000 /* DENALI_CTL_106_DATA */ + 0x00000000 /* DENALI_CTL_107_DATA */ + 0x00000000 /* DENALI_CTL_108_DATA */ + 0x00000000 /* DENALI_CTL_109_DATA */ + 0x01000000 /* DENALI_CTL_110_DATA */ + 0x00040000 /* DENALI_CTL_111_DATA */ + 0x00800200 /* DENALI_CTL_112_DATA */ + 0x00000200 /* DENALI_CTL_113_DATA */ + 0x00000040 /* DENALI_CTL_114_DATA */ + 0x01000100 /* DENALI_CTL_115_DATA */ + 0x0a000002 /* DENALI_CTL_116_DATA */ + 0x0101ffff /* DENALI_CTL_117_DATA */ + 0x01010101 /* DENALI_CTL_118_DATA */ + 0x01010101 /* DENALI_CTL_119_DATA */ + 0x0000010b /* DENALI_CTL_120_DATA */ + 0x00000c01 /* DENALI_CTL_121_DATA */ + 0x00000000 /* DENALI_CTL_122_DATA */ + 0x00000000 /* DENALI_CTL_123_DATA */ + 0x00000000 /* DENALI_CTL_124_DATA */ + 0x00000000 /* DENALI_CTL_125_DATA */ + 0x00030300 /* DENALI_CTL_126_DATA */ + 0x00000000 /* DENALI_CTL_127_DATA */ + 0x00010001 /* DENALI_CTL_128_DATA */ + 0x00000000 /* DENALI_CTL_129_DATA */ + 0x00000000 /* DENALI_CTL_130_DATA */ + 0x00000000 /* DENALI_CTL_131_DATA */ + 0x00000000 /* DENALI_CTL_132_DATA */ + 0x00000000 /* DENALI_CTL_133_DATA */ + 0x00000000 /* DENALI_CTL_134_DATA */ + 0x00000000 /* DENALI_CTL_135_DATA */ + 0x00000000 /* DENALI_CTL_136_DATA */ + 0x00000000 /* DENALI_CTL_137_DATA */ + 0x00000000 /* DENALI_CTL_138_DATA */ + 0x00000000 /* DENALI_CTL_139_DATA */ + 0x00000000 /* DENALI_CTL_140_DATA */ + 0x00000000 /* DENALI_CTL_141_DATA */ + 0x00000000 /* DENALI_CTL_142_DATA */ + 0x00000000 /* DENALI_CTL_143_DATA */ + 0x00000000 /* DENALI_CTL_144_DATA */ + 0x00000000 /* DENALI_CTL_145_DATA */ + 0x00000000 /* DENALI_CTL_146_DATA */ + 0x00000000 /* DENALI_CTL_147_DATA */ + 0x00000000 /* DENALI_CTL_148_DATA */ + 0x00000000 /* DENALI_CTL_149_DATA */ + 0x00000000 /* DENALI_CTL_150_DATA */ + 0x00000000 /* DENALI_CTL_151_DATA */ + 0x00000000 /* DENALI_CTL_152_DATA */ + 0x00000000 /* DENALI_CTL_153_DATA */ + 0x00000000 /* DENALI_CTL_154_DATA */ + 0x00000000 /* DENALI_CTL_155_DATA */ + 0x00000000 /* DENALI_CTL_156_DATA */ + 0x00000000 /* DENALI_CTL_157_DATA */ + 0x00000000 /* DENALI_CTL_158_DATA */ + 0x00000000 /* DENALI_CTL_159_DATA */ + 0x00000000 /* DENALI_CTL_160_DATA */ + 0x02010102 /* DENALI_CTL_161_DATA */ + 0x0107070d /* DENALI_CTL_162_DATA */ + 0x04040400 /* DENALI_CTL_163_DATA */ + 0x03000503 /* DENALI_CTL_164_DATA */ + 0x00000000 /* DENALI_CTL_165_DATA */ + 0x00000000 /* DENALI_CTL_166_DATA */ + 0x00000000 /* DENALI_CTL_167_DATA */ + 0x00000000 /* DENALI_CTL_168_DATA */ + 0x280d0000 /* DENALI_CTL_169_DATA */ + 0x01000000 /* DENALI_CTL_170_DATA */ + 0x00000000 /* DENALI_CTL_171_DATA */ + 0x00010001 /* DENALI_CTL_172_DATA */ + 0x00000000 /* DENALI_CTL_173_DATA */ + 0x00000000 /* DENALI_CTL_174_DATA */ + 0x00000000 /* DENALI_CTL_175_DATA */ + 0x00000000 /* DENALI_CTL_176_DATA */ + 0x00000000 /* DENALI_CTL_177_DATA */ + 0x00000000 /* DENALI_CTL_178_DATA */ + 0x00000000 /* DENALI_CTL_179_DATA */ + 0x00000000 /* DENALI_CTL_180_DATA */ + 0x01000000 /* DENALI_CTL_181_DATA */ + 0x00000001 /* DENALI_CTL_182_DATA */ + 0x00000100 /* DENALI_CTL_183_DATA */ + 0x00000101 /* DENALI_CTL_184_DATA */ + 0x67676701 /* DENALI_CTL_185_DATA */ + 0x67676767 /* DENALI_CTL_186_DATA */ + 0x67676767 /* DENALI_CTL_187_DATA */ + 0x67676767 /* DENALI_CTL_188_DATA */ + 0x67676767 /* DENALI_CTL_189_DATA */ + 0x67676767 /* DENALI_CTL_190_DATA */ + 0x67676767 /* DENALI_CTL_191_DATA */ + 0x67676767 /* DENALI_CTL_192_DATA */ + 0x67676767 /* DENALI_CTL_193_DATA */ + 0x01000067 /* DENALI_CTL_194_DATA */ + 0x00000001 /* DENALI_CTL_195_DATA */ + 0x00000101 /* DENALI_CTL_196_DATA */ + 0x00000000 /* DENALI_CTL_197_DATA */ + 0x00000000 /* DENALI_CTL_198_DATA */ + 0x00000000 /* DENALI_CTL_199_DATA */ + 0x00000000 /* DENALI_CTL_200_DATA */ + 0x00000000 /* DENALI_CTL_201_DATA */ + 0x00000000 /* DENALI_CTL_202_DATA */ + 0x00000000 /* DENALI_CTL_203_DATA */ + 0x00000000 /* DENALI_CTL_204_DATA */ + 0x00000000 /* DENALI_CTL_205_DATA */ + 0x00000000 /* DENALI_CTL_206_DATA */ + 0x00000000 /* DENALI_CTL_207_DATA */ + 0x00000001 /* DENALI_CTL_208_DATA */ + 0x00000000 /* DENALI_CTL_209_DATA */ + 0x007fffff /* DENALI_CTL_210_DATA */ + 0x00000000 /* DENALI_CTL_211_DATA */ + 0x007fffff /* DENALI_CTL_212_DATA */ + 0x00000000 /* DENALI_CTL_213_DATA */ + 0x007fffff /* DENALI_CTL_214_DATA */ + 0x00000000 /* DENALI_CTL_215_DATA */ + 0x007fffff /* DENALI_CTL_216_DATA */ + 0x00000000 /* DENALI_CTL_217_DATA */ + 0x007fffff /* DENALI_CTL_218_DATA */ + 0x00000000 /* DENALI_CTL_219_DATA */ + 0x007fffff /* DENALI_CTL_220_DATA */ + 0x00000000 /* DENALI_CTL_221_DATA */ + 0x007fffff /* DENALI_CTL_222_DATA */ + 0x00000000 /* DENALI_CTL_223_DATA */ + 0x037fffff /* DENALI_CTL_224_DATA */ + 0xffffffff /* DENALI_CTL_225_DATA */ + 0x000f000f /* DENALI_CTL_226_DATA */ + 0x00ffff03 /* DENALI_CTL_227_DATA */ + 0x000fffff /* DENALI_CTL_228_DATA */ + 0x0003000f /* DENALI_CTL_229_DATA */ + 0xffffffff /* DENALI_CTL_230_DATA */ + 0x000f000f /* DENALI_CTL_231_DATA */ + 0x00ffff03 /* DENALI_CTL_232_DATA */ + 0x000fffff /* DENALI_CTL_233_DATA */ + 0x0003000f /* DENALI_CTL_234_DATA */ + 0xffffffff /* DENALI_CTL_235_DATA */ + 0x000f000f /* DENALI_CTL_236_DATA */ + 0x00ffff03 /* DENALI_CTL_237_DATA */ + 0x000fffff /* DENALI_CTL_238_DATA */ + 0x0003000f /* DENALI_CTL_239_DATA */ + 0xffffffff /* DENALI_CTL_240_DATA */ + 0x000f000f /* DENALI_CTL_241_DATA */ + 0x00ffff03 /* DENALI_CTL_242_DATA */ + 0x000fffff /* DENALI_CTL_243_DATA */ + 0x6407000f /* DENALI_CTL_244_DATA */ + 0x01640001 /* DENALI_CTL_245_DATA */ + 0x00000000 /* DENALI_CTL_246_DATA */ + 0x00000000 /* DENALI_CTL_247_DATA */ + 0x00001700 /* DENALI_CTL_248_DATA */ + 0x00386c05 /* DENALI_CTL_249_DATA */ + 0x02000200 /* DENALI_CTL_250_DATA */ + 0x02000200 /* DENALI_CTL_251_DATA */ + 0x0000386c /* DENALI_CTL_252_DATA */ + 0x00023438 /* DENALI_CTL_253_DATA */ + 0x02020d10 /* DENALI_CTL_254_DATA */ + 0x00140303 /* DENALI_CTL_255_DATA */ + 0x00000000 /* DENALI_CTL_256_DATA */ + 0x00000000 /* DENALI_CTL_257_DATA */ + 0x00001403 /* DENALI_CTL_258_DATA */ + 0x00000000 /* DENALI_CTL_259_DATA */ + 0x00000000 /* DENALI_CTL_260_DATA */ + 0x00000000 /* DENALI_CTL_261_DATA */ + 0x00000000 /* DENALI_CTL_262_DATA */ + 0x0d010000 /* DENALI_CTL_263_DATA */ + 0x00000008 /* DENALI_CTL_264_DATA */ + 0x31706542 /* DENALI_PHY_00_DATA */ + 0x0004c008 /* DENALI_PHY_01_DATA */ + 0x000000da /* DENALI_PHY_02_DATA */ + 0x00000000 /* DENALI_PHY_03_DATA */ + 0x00000000 /* DENALI_PHY_04_DATA */ + 0x00010000 /* DENALI_PHY_05_DATA */ + 0x01DDDD90 /* DENALI_PHY_06_DATA */ + 0x01DDDD90 /* DENALI_PHY_07_DATA */ + 0x01030000 /* DENALI_PHY_08_DATA */ + 0x01000000 /* DENALI_PHY_09_DATA */ + 0x00c00000 /* DENALI_PHY_10_DATA */ + 0x00000007 /* DENALI_PHY_11_DATA */ + 0x00000000 /* DENALI_PHY_12_DATA */ + 0x00000000 /* DENALI_PHY_13_DATA */ + 0x04000408 /* DENALI_PHY_14_DATA */ + 0x00000408 /* DENALI_PHY_15_DATA */ + 0x00e4e400 /* DENALI_PHY_16_DATA */ + 0x00000000 /* DENALI_PHY_17_DATA */ + 0x00000000 /* DENALI_PHY_18_DATA */ + 0x00000000 /* DENALI_PHY_19_DATA */ + 0x00000000 /* DENALI_PHY_20_DATA */ + 0x00000000 /* DENALI_PHY_21_DATA */ + 0x00000000 /* DENALI_PHY_22_DATA */ + 0x00000000 /* DENALI_PHY_23_DATA */ + 0x00000000 /* DENALI_PHY_24_DATA */ + 0x00000000 /* DENALI_PHY_25_DATA */ + 0x00000000 /* DENALI_PHY_26_DATA */ + 0x00000000 /* DENALI_PHY_27_DATA */ + 0x00000000 /* DENALI_PHY_28_DATA */ + 0x00000000 /* DENALI_PHY_29_DATA */ + 0x00000000 /* DENALI_PHY_30_DATA */ + 0x00000000 /* DENALI_PHY_31_DATA */ + 0x00000000 /* DENALI_PHY_32_DATA */ + 0x00200000 /* DENALI_PHY_33_DATA */ + 0x00000000 /* DENALI_PHY_34_DATA */ + 0x00000000 /* DENALI_PHY_35_DATA */ + 0x00000000 /* DENALI_PHY_36_DATA */ + 0x00000000 /* DENALI_PHY_37_DATA */ + 0x00000000 /* DENALI_PHY_38_DATA */ + 0x00000000 /* DENALI_PHY_39_DATA */ + 0x02800280 /* DENALI_PHY_40_DATA */ + 0x02800280 /* DENALI_PHY_41_DATA */ + 0x02800280 /* DENALI_PHY_42_DATA */ + 0x02800280 /* DENALI_PHY_43_DATA */ + 0x00000280 /* DENALI_PHY_44_DATA */ + 0x00000000 /* DENALI_PHY_45_DATA */ + 0x00000000 /* DENALI_PHY_46_DATA */ + 0x00000000 /* DENALI_PHY_47_DATA */ + 0x00000000 /* DENALI_PHY_48_DATA */ + 0x00000000 /* DENALI_PHY_49_DATA */ + 0x00800080 /* DENALI_PHY_50_DATA */ + 0x00800080 /* DENALI_PHY_51_DATA */ + 0x00800080 /* DENALI_PHY_52_DATA */ + 0x00800080 /* DENALI_PHY_53_DATA */ + 0x00800080 /* DENALI_PHY_54_DATA */ + 0x00800080 /* DENALI_PHY_55_DATA */ + 0x00800080 /* DENALI_PHY_56_DATA */ + 0x00800080 /* DENALI_PHY_57_DATA */ + 0x00800080 /* DENALI_PHY_58_DATA */ + 0x000100da /* DENALI_PHY_59_DATA */ + 0x01000200 /* DENALI_PHY_60_DATA */ + 0x00000000 /* DENALI_PHY_61_DATA */ + 0x00000000 /* DENALI_PHY_62_DATA */ + 0x00000002 /* DENALI_PHY_63_DATA */ + 0x51313152 /* DENALI_PHY_64_DATA */ + 0x80013130 /* DENALI_PHY_65_DATA */ + 0x02000080 /* DENALI_PHY_66_DATA */ + 0x00100001 /* DENALI_PHY_67_DATA */ + 0x0c064208 /* DENALI_PHY_68_DATA */ + 0x000f0c0f /* DENALI_PHY_69_DATA */ + 0x01000140 /* DENALI_PHY_70_DATA */ + 0x0000000c /* DENALI_PHY_71_DATA */ + 0x00000000 /* DENALI_PHY_72_DATA */ + 0x00000000 /* DENALI_PHY_73_DATA */ + 0x00000000 /* DENALI_PHY_74_DATA */ + 0x00000000 /* DENALI_PHY_75_DATA */ + 0x00000000 /* DENALI_PHY_76_DATA */ + 0x00000000 /* DENALI_PHY_77_DATA */ + 0x00000000 /* DENALI_PHY_78_DATA */ + 0x00000000 /* DENALI_PHY_79_DATA */ + 0x00000000 /* DENALI_PHY_80_DATA */ + 0x00000000 /* DENALI_PHY_81_DATA */ + 0x00000000 /* DENALI_PHY_82_DATA */ + 0x00000000 /* DENALI_PHY_83_DATA */ + 0x00000000 /* DENALI_PHY_84_DATA */ + 0x00000000 /* DENALI_PHY_85_DATA */ + 0x00000000 /* DENALI_PHY_86_DATA */ + 0x00000000 /* DENALI_PHY_87_DATA */ + 0x00000000 /* DENALI_PHY_88_DATA */ + 0x00000000 /* DENALI_PHY_89_DATA */ + 0x00000000 /* DENALI_PHY_90_DATA */ + 0x00000000 /* DENALI_PHY_91_DATA */ + 0x00000000 /* DENALI_PHY_92_DATA */ + 0x00000000 /* DENALI_PHY_93_DATA */ + 0x00000000 /* DENALI_PHY_94_DATA */ + 0x00000000 /* DENALI_PHY_95_DATA */ + 0x00000000 /* DENALI_PHY_96_DATA */ + 0x00000000 /* DENALI_PHY_97_DATA */ + 0x00000000 /* DENALI_PHY_98_DATA */ + 0x00000000 /* DENALI_PHY_99_DATA */ + 0x00000000 /* DENALI_PHY_100_DATA */ + 0x00000000 /* DENALI_PHY_101_DATA */ + 0x00000000 /* DENALI_PHY_102_DATA */ + 0x00000000 /* DENALI_PHY_103_DATA */ + 0x00000000 /* DENALI_PHY_104_DATA */ + 0x00000000 /* DENALI_PHY_105_DATA */ + 0x00000000 /* DENALI_PHY_106_DATA */ + 0x00000000 /* DENALI_PHY_107_DATA */ + 0x00000000 /* DENALI_PHY_108_DATA */ + 0x00000000 /* DENALI_PHY_109_DATA */ + 0x00000000 /* DENALI_PHY_110_DATA */ + 0x00000000 /* DENALI_PHY_111_DATA */ + 0x00000000 /* DENALI_PHY_112_DATA */ + 0x00000000 /* DENALI_PHY_113_DATA */ + 0x00000000 /* DENALI_PHY_114_DATA */ + 0x00000000 /* DENALI_PHY_115_DATA */ + 0x00000000 /* DENALI_PHY_116_DATA */ + 0x00000000 /* DENALI_PHY_117_DATA */ + 0x00000000 /* DENALI_PHY_118_DATA */ + 0x00000000 /* DENALI_PHY_119_DATA */ + 0x00000000 /* DENALI_PHY_120_DATA */ + 0x00000000 /* DENALI_PHY_121_DATA */ + 0x00000000 /* DENALI_PHY_122_DATA */ + 0x00000000 /* DENALI_PHY_123_DATA */ + 0x00000000 /* DENALI_PHY_124_DATA */ + 0x00000000 /* DENALI_PHY_125_DATA */ + 0x00000000 /* DENALI_PHY_126_DATA */ + 0x00000000 /* DENALI_PHY_127_DATA */ + 0x40263571 /* DENALI_PHY_128_DATA */ + 0x0004c008 /* DENALI_PHY_129_DATA */ + 0x000000da /* DENALI_PHY_130_DATA */ + 0x00000000 /* DENALI_PHY_131_DATA */ + 0x00000000 /* DENALI_PHY_132_DATA */ + 0x00010000 /* DENALI_PHY_133_DATA */ + 0x01DDDD90 /* DENALI_PHY_134_DATA */ + 0x01DDDD90 /* DENALI_PHY_135_DATA */ + 0x01030000 /* DENALI_PHY_136_DATA */ + 0x01000000 /* DENALI_PHY_137_DATA */ + 0x00c00000 /* DENALI_PHY_138_DATA */ + 0x00000007 /* DENALI_PHY_139_DATA */ + 0x00000000 /* DENALI_PHY_140_DATA */ + 0x00000000 /* DENALI_PHY_141_DATA */ + 0x04000408 /* DENALI_PHY_142_DATA */ + 0x00000408 /* DENALI_PHY_143_DATA */ + 0x00e4e400 /* DENALI_PHY_144_DATA */ + 0x00000000 /* DENALI_PHY_145_DATA */ + 0x00000000 /* DENALI_PHY_146_DATA */ + 0x00000000 /* DENALI_PHY_147_DATA */ + 0x00000000 /* DENALI_PHY_148_DATA */ + 0x00000000 /* DENALI_PHY_149_DATA */ + 0x00000000 /* DENALI_PHY_150_DATA */ + 0x00000000 /* DENALI_PHY_151_DATA */ + 0x00000000 /* DENALI_PHY_152_DATA */ + 0x00000000 /* DENALI_PHY_153_DATA */ + 0x00000000 /* DENALI_PHY_154_DATA */ + 0x00000000 /* DENALI_PHY_155_DATA */ + 0x00000000 /* DENALI_PHY_156_DATA */ + 0x00000000 /* DENALI_PHY_157_DATA */ + 0x00000000 /* DENALI_PHY_158_DATA */ + 0x00000000 /* DENALI_PHY_159_DATA */ + 0x00000000 /* DENALI_PHY_160_DATA */ + 0x00200000 /* DENALI_PHY_161_DATA */ + 0x00000000 /* DENALI_PHY_162_DATA */ + 0x00000000 /* DENALI_PHY_163_DATA */ + 0x00000000 /* DENALI_PHY_164_DATA */ + 0x00000000 /* DENALI_PHY_165_DATA */ + 0x00000000 /* DENALI_PHY_166_DATA */ + 0x00000000 /* DENALI_PHY_167_DATA */ + 0x02800280 /* DENALI_PHY_168_DATA */ + 0x02800280 /* DENALI_PHY_169_DATA */ + 0x02800280 /* DENALI_PHY_170_DATA */ + 0x02800280 /* DENALI_PHY_171_DATA */ + 0x00000280 /* DENALI_PHY_172_DATA */ + 0x00000000 /* DENALI_PHY_173_DATA */ + 0x00000000 /* DENALI_PHY_174_DATA */ + 0x00000000 /* DENALI_PHY_175_DATA */ + 0x00000000 /* DENALI_PHY_176_DATA */ + 0x00000000 /* DENALI_PHY_177_DATA */ + 0x00800080 /* DENALI_PHY_178_DATA */ + 0x00800080 /* DENALI_PHY_179_DATA */ + 0x00800080 /* DENALI_PHY_180_DATA */ + 0x00800080 /* DENALI_PHY_181_DATA */ + 0x00800080 /* DENALI_PHY_182_DATA */ + 0x00800080 /* DENALI_PHY_183_DATA */ + 0x00800080 /* DENALI_PHY_184_DATA */ + 0x00800080 /* DENALI_PHY_185_DATA */ + 0x00800080 /* DENALI_PHY_186_DATA */ + 0x000100da /* DENALI_PHY_187_DATA */ + 0x01000200 /* DENALI_PHY_188_DATA */ + 0x00000000 /* DENALI_PHY_189_DATA */ + 0x00000000 /* DENALI_PHY_190_DATA */ + 0x00000002 /* DENALI_PHY_191_DATA */ + 0x51313152 /* DENALI_PHY_192_DATA */ + 0x80013130 /* DENALI_PHY_193_DATA */ + 0x02000080 /* DENALI_PHY_194_DATA */ + 0x00100001 /* DENALI_PHY_195_DATA */ + 0x0c064208 /* DENALI_PHY_196_DATA */ + 0x000f0c0f /* DENALI_PHY_197_DATA */ + 0x01000140 /* DENALI_PHY_198_DATA */ + 0x0000000c /* DENALI_PHY_199_DATA */ + 0x00000000 /* DENALI_PHY_200_DATA */ + 0x00000000 /* DENALI_PHY_201_DATA */ + 0x00000000 /* DENALI_PHY_202_DATA */ + 0x00000000 /* DENALI_PHY_203_DATA */ + 0x00000000 /* DENALI_PHY_204_DATA */ + 0x00000000 /* DENALI_PHY_205_DATA */ + 0x00000000 /* DENALI_PHY_206_DATA */ + 0x00000000 /* DENALI_PHY_207_DATA */ + 0x00000000 /* DENALI_PHY_208_DATA */ + 0x00000000 /* DENALI_PHY_209_DATA */ + 0x00000000 /* DENALI_PHY_210_DATA */ + 0x00000000 /* DENALI_PHY_211_DATA */ + 0x00000000 /* DENALI_PHY_212_DATA */ + 0x00000000 /* DENALI_PHY_213_DATA */ + 0x00000000 /* DENALI_PHY_214_DATA */ + 0x00000000 /* DENALI_PHY_215_DATA */ + 0x00000000 /* DENALI_PHY_216_DATA */ + 0x00000000 /* DENALI_PHY_217_DATA */ + 0x00000000 /* DENALI_PHY_218_DATA */ + 0x00000000 /* DENALI_PHY_219_DATA */ + 0x00000000 /* DENALI_PHY_220_DATA */ + 0x00000000 /* DENALI_PHY_221_DATA */ + 0x00000000 /* DENALI_PHY_222_DATA */ + 0x00000000 /* DENALI_PHY_223_DATA */ + 0x00000000 /* DENALI_PHY_224_DATA */ + 0x00000000 /* DENALI_PHY_225_DATA */ + 0x00000000 /* DENALI_PHY_226_DATA */ + 0x00000000 /* DENALI_PHY_227_DATA */ + 0x00000000 /* DENALI_PHY_228_DATA */ + 0x00000000 /* DENALI_PHY_229_DATA */ + 0x00000000 /* DENALI_PHY_230_DATA */ + 0x00000000 /* DENALI_PHY_231_DATA */ + 0x00000000 /* DENALI_PHY_232_DATA */ + 0x00000000 /* DENALI_PHY_233_DATA */ + 0x00000000 /* DENALI_PHY_234_DATA */ + 0x00000000 /* DENALI_PHY_235_DATA */ + 0x00000000 /* DENALI_PHY_236_DATA */ + 0x00000000 /* DENALI_PHY_237_DATA */ + 0x00000000 /* DENALI_PHY_238_DATA */ + 0x00000000 /* DENALI_PHY_239_DATA */ + 0x00000000 /* DENALI_PHY_240_DATA */ + 0x00000000 /* DENALI_PHY_241_DATA */ + 0x00000000 /* DENALI_PHY_242_DATA */ + 0x00000000 /* DENALI_PHY_243_DATA */ + 0x00000000 /* DENALI_PHY_244_DATA */ + 0x00000000 /* DENALI_PHY_245_DATA */ + 0x00000000 /* DENALI_PHY_246_DATA */ + 0x00000000 /* DENALI_PHY_247_DATA */ + 0x00000000 /* DENALI_PHY_248_DATA */ + 0x00000000 /* DENALI_PHY_249_DATA */ + 0x00000000 /* DENALI_PHY_250_DATA */ + 0x00000000 /* DENALI_PHY_251_DATA */ + 0x00000000 /* DENALI_PHY_252_DATA */ + 0x00000000 /* DENALI_PHY_253_DATA */ + 0x00000000 /* DENALI_PHY_254_DATA */ + 0x00000000 /* DENALI_PHY_255_DATA */ + 0x46052371 /* DENALI_PHY_256_DATA */ + 0x0004c008 /* DENALI_PHY_257_DATA */ + 0x000000da /* DENALI_PHY_258_DATA */ + 0x00000000 /* DENALI_PHY_259_DATA */ + 0x00000000 /* DENALI_PHY_260_DATA */ + 0x00010000 /* DENALI_PHY_261_DATA */ + 0x01DDDD90 /* DENALI_PHY_262_DATA */ + 0x01DDDD90 /* DENALI_PHY_263_DATA */ + 0x01030000 /* DENALI_PHY_264_DATA */ + 0x01000000 /* DENALI_PHY_265_DATA */ + 0x00c00000 /* DENALI_PHY_266_DATA */ + 0x00000007 /* DENALI_PHY_267_DATA */ + 0x00000000 /* DENALI_PHY_268_DATA */ + 0x00000000 /* DENALI_PHY_269_DATA */ + 0x04000408 /* DENALI_PHY_270_DATA */ + 0x00000408 /* DENALI_PHY_271_DATA */ + 0x00e4e400 /* DENALI_PHY_272_DATA */ + 0x00000000 /* DENALI_PHY_273_DATA */ + 0x00000000 /* DENALI_PHY_274_DATA */ + 0x00000000 /* DENALI_PHY_275_DATA */ + 0x00000000 /* DENALI_PHY_276_DATA */ + 0x00000000 /* DENALI_PHY_277_DATA */ + 0x00000000 /* DENALI_PHY_278_DATA */ + 0x00000000 /* DENALI_PHY_279_DATA */ + 0x00000000 /* DENALI_PHY_280_DATA */ + 0x00000000 /* DENALI_PHY_281_DATA */ + 0x00000000 /* DENALI_PHY_282_DATA */ + 0x00000000 /* DENALI_PHY_283_DATA */ + 0x00000000 /* DENALI_PHY_284_DATA */ + 0x00000000 /* DENALI_PHY_285_DATA */ + 0x00000000 /* DENALI_PHY_286_DATA */ + 0x00000000 /* DENALI_PHY_287_DATA */ + 0x00000000 /* DENALI_PHY_288_DATA */ + 0x00200000 /* DENALI_PHY_289_DATA */ + 0x00000000 /* DENALI_PHY_290_DATA */ + 0x00000000 /* DENALI_PHY_291_DATA */ + 0x00000000 /* DENALI_PHY_292_DATA */ + 0x00000000 /* DENALI_PHY_293_DATA */ + 0x00000000 /* DENALI_PHY_294_DATA */ + 0x00000000 /* DENALI_PHY_295_DATA */ + 0x02800280 /* DENALI_PHY_296_DATA */ + 0x02800280 /* DENALI_PHY_297_DATA */ + 0x02800280 /* DENALI_PHY_298_DATA */ + 0x02800280 /* DENALI_PHY_299_DATA */ + 0x00000280 /* DENALI_PHY_300_DATA */ + 0x00000000 /* DENALI_PHY_301_DATA */ + 0x00000000 /* DENALI_PHY_302_DATA */ + 0x00000000 /* DENALI_PHY_303_DATA */ + 0x00000000 /* DENALI_PHY_304_DATA */ + 0x00000000 /* DENALI_PHY_305_DATA */ + 0x00800080 /* DENALI_PHY_306_DATA */ + 0x00800080 /* DENALI_PHY_307_DATA */ + 0x00800080 /* DENALI_PHY_308_DATA */ + 0x00800080 /* DENALI_PHY_309_DATA */ + 0x00800080 /* DENALI_PHY_310_DATA */ + 0x00800080 /* DENALI_PHY_311_DATA */ + 0x00800080 /* DENALI_PHY_312_DATA */ + 0x00800080 /* DENALI_PHY_313_DATA */ + 0x00800080 /* DENALI_PHY_314_DATA */ + 0x000100da /* DENALI_PHY_315_DATA */ + 0x00000200 /* DENALI_PHY_316_DATA */ + 0x00000000 /* DENALI_PHY_317_DATA */ + 0x00000000 /* DENALI_PHY_318_DATA */ + 0x00000002 /* DENALI_PHY_319_DATA */ + 0x51313152 /* DENALI_PHY_320_DATA */ + 0x80013130 /* DENALI_PHY_321_DATA */ + 0x02000080 /* DENALI_PHY_322_DATA */ + 0x00100001 /* DENALI_PHY_323_DATA */ + 0x0c064208 /* DENALI_PHY_324_DATA */ + 0x000f0c0f /* DENALI_PHY_325_DATA */ + 0x01000140 /* DENALI_PHY_326_DATA */ + 0x0000000c /* DENALI_PHY_327_DATA */ + 0x00000000 /* DENALI_PHY_328_DATA */ + 0x00000000 /* DENALI_PHY_329_DATA */ + 0x00000000 /* DENALI_PHY_330_DATA */ + 0x00000000 /* DENALI_PHY_331_DATA */ + 0x00000000 /* DENALI_PHY_332_DATA */ + 0x00000000 /* DENALI_PHY_333_DATA */ + 0x00000000 /* DENALI_PHY_334_DATA */ + 0x00000000 /* DENALI_PHY_335_DATA */ + 0x00000000 /* DENALI_PHY_336_DATA */ + 0x00000000 /* DENALI_PHY_337_DATA */ + 0x00000000 /* DENALI_PHY_338_DATA */ + 0x00000000 /* DENALI_PHY_339_DATA */ + 0x00000000 /* DENALI_PHY_340_DATA */ + 0x00000000 /* DENALI_PHY_341_DATA */ + 0x00000000 /* DENALI_PHY_342_DATA */ + 0x00000000 /* DENALI_PHY_343_DATA */ + 0x00000000 /* DENALI_PHY_344_DATA */ + 0x00000000 /* DENALI_PHY_345_DATA */ + 0x00000000 /* DENALI_PHY_346_DATA */ + 0x00000000 /* DENALI_PHY_347_DATA */ + 0x00000000 /* DENALI_PHY_348_DATA */ + 0x00000000 /* DENALI_PHY_349_DATA */ + 0x00000000 /* DENALI_PHY_350_DATA */ + 0x00000000 /* DENALI_PHY_351_DATA */ + 0x00000000 /* DENALI_PHY_352_DATA */ + 0x00000000 /* DENALI_PHY_353_DATA */ + 0x00000000 /* DENALI_PHY_354_DATA */ + 0x00000000 /* DENALI_PHY_355_DATA */ + 0x00000000 /* DENALI_PHY_356_DATA */ + 0x00000000 /* DENALI_PHY_357_DATA */ + 0x00000000 /* DENALI_PHY_358_DATA */ + 0x00000000 /* DENALI_PHY_359_DATA */ + 0x00000000 /* DENALI_PHY_360_DATA */ + 0x00000000 /* DENALI_PHY_361_DATA */ + 0x00000000 /* DENALI_PHY_362_DATA */ + 0x00000000 /* DENALI_PHY_363_DATA */ + 0x00000000 /* DENALI_PHY_364_DATA */ + 0x00000000 /* DENALI_PHY_365_DATA */ + 0x00000000 /* DENALI_PHY_366_DATA */ + 0x00000000 /* DENALI_PHY_367_DATA */ + 0x00000000 /* DENALI_PHY_368_DATA */ + 0x00000000 /* DENALI_PHY_369_DATA */ + 0x00000000 /* DENALI_PHY_370_DATA */ + 0x00000000 /* DENALI_PHY_371_DATA */ + 0x00000000 /* DENALI_PHY_372_DATA */ + 0x00000000 /* DENALI_PHY_373_DATA */ + 0x00000000 /* DENALI_PHY_374_DATA */ + 0x00000000 /* DENALI_PHY_375_DATA */ + 0x00000000 /* DENALI_PHY_376_DATA */ + 0x00000000 /* DENALI_PHY_377_DATA */ + 0x00000000 /* DENALI_PHY_378_DATA */ + 0x00000000 /* DENALI_PHY_379_DATA */ + 0x00000000 /* DENALI_PHY_380_DATA */ + 0x00000000 /* DENALI_PHY_381_DATA */ + 0x00000000 /* DENALI_PHY_382_DATA */ + 0x00000000 /* DENALI_PHY_383_DATA */ + 0x37654120 /* DENALI_PHY_384_DATA */ + 0x0004c008 /* DENALI_PHY_385_DATA */ + 0x000000da /* DENALI_PHY_386_DATA */ + 0x00000000 /* DENALI_PHY_387_DATA */ + 0x00000000 /* DENALI_PHY_388_DATA */ + 0x00010000 /* DENALI_PHY_389_DATA */ + 0x01DDDD90 /* DENALI_PHY_390_DATA */ + 0x01DDDD90 /* DENALI_PHY_391_DATA */ + 0x01030000 /* DENALI_PHY_392_DATA */ + 0x01000000 /* DENALI_PHY_393_DATA */ + 0x00c00000 /* DENALI_PHY_394_DATA */ + 0x00000007 /* DENALI_PHY_395_DATA */ + 0x00000000 /* DENALI_PHY_396_DATA */ + 0x00000000 /* DENALI_PHY_397_DATA */ + 0x04000408 /* DENALI_PHY_398_DATA */ + 0x00000408 /* DENALI_PHY_399_DATA */ + 0x00e4e400 /* DENALI_PHY_400_DATA */ + 0x00000000 /* DENALI_PHY_401_DATA */ + 0x00000000 /* DENALI_PHY_402_DATA */ + 0x00000000 /* DENALI_PHY_403_DATA */ + 0x00000000 /* DENALI_PHY_404_DATA */ + 0x00000000 /* DENALI_PHY_405_DATA */ + 0x00000000 /* DENALI_PHY_406_DATA */ + 0x00000000 /* DENALI_PHY_407_DATA */ + 0x00000000 /* DENALI_PHY_408_DATA */ + 0x00000000 /* DENALI_PHY_409_DATA */ + 0x00000000 /* DENALI_PHY_410_DATA */ + 0x00000000 /* DENALI_PHY_411_DATA */ + 0x00000000 /* DENALI_PHY_412_DATA */ + 0x00000000 /* DENALI_PHY_413_DATA */ + 0x00000000 /* DENALI_PHY_414_DATA */ + 0x00000000 /* DENALI_PHY_415_DATA */ + 0x00000000 /* DENALI_PHY_416_DATA */ + 0x00200000 /* DENALI_PHY_417_DATA */ + 0x00000000 /* DENALI_PHY_418_DATA */ + 0x00000000 /* DENALI_PHY_419_DATA */ + 0x00000000 /* DENALI_PHY_420_DATA */ + 0x00000000 /* DENALI_PHY_421_DATA */ + 0x00000000 /* DENALI_PHY_422_DATA */ + 0x00000000 /* DENALI_PHY_423_DATA */ + 0x02800280 /* DENALI_PHY_424_DATA */ + 0x02800280 /* DENALI_PHY_425_DATA */ + 0x02800280 /* DENALI_PHY_426_DATA */ + 0x02800280 /* DENALI_PHY_427_DATA */ + 0x00000280 /* DENALI_PHY_428_DATA */ + 0x00000000 /* DENALI_PHY_429_DATA */ + 0x00000000 /* DENALI_PHY_430_DATA */ + 0x00000000 /* DENALI_PHY_431_DATA */ + 0x00000000 /* DENALI_PHY_432_DATA */ + 0x00000000 /* DENALI_PHY_433_DATA */ + 0x00800080 /* DENALI_PHY_434_DATA */ + 0x00800080 /* DENALI_PHY_435_DATA */ + 0x00800080 /* DENALI_PHY_436_DATA */ + 0x00800080 /* DENALI_PHY_437_DATA */ + 0x00800080 /* DENALI_PHY_438_DATA */ + 0x00800080 /* DENALI_PHY_439_DATA */ + 0x00800080 /* DENALI_PHY_440_DATA */ + 0x00800080 /* DENALI_PHY_441_DATA */ + 0x00800080 /* DENALI_PHY_442_DATA */ + 0x000100da /* DENALI_PHY_443_DATA */ + 0x00000200 /* DENALI_PHY_444_DATA */ + 0x00000000 /* DENALI_PHY_445_DATA */ + 0x00000000 /* DENALI_PHY_446_DATA */ + 0x00000002 /* DENALI_PHY_447_DATA */ + 0x51313152 /* DENALI_PHY_448_DATA */ + 0x80013130 /* DENALI_PHY_449_DATA */ + 0x02000080 /* DENALI_PHY_450_DATA */ + 0x00100001 /* DENALI_PHY_451_DATA */ + 0x0c064208 /* DENALI_PHY_452_DATA */ + 0x000f0c0f /* DENALI_PHY_453_DATA */ + 0x01000140 /* DENALI_PHY_454_DATA */ + 0x0000000c /* DENALI_PHY_455_DATA */ + 0x00000000 /* DENALI_PHY_456_DATA */ + 0x00000000 /* DENALI_PHY_457_DATA */ + 0x00000000 /* DENALI_PHY_458_DATA */ + 0x00000000 /* DENALI_PHY_459_DATA */ + 0x00000000 /* DENALI_PHY_460_DATA */ + 0x00000000 /* DENALI_PHY_461_DATA */ + 0x00000000 /* DENALI_PHY_462_DATA */ + 0x00000000 /* DENALI_PHY_463_DATA */ + 0x00000000 /* DENALI_PHY_464_DATA */ + 0x00000000 /* DENALI_PHY_465_DATA */ + 0x00000000 /* DENALI_PHY_466_DATA */ + 0x00000000 /* DENALI_PHY_467_DATA */ + 0x00000000 /* DENALI_PHY_468_DATA */ + 0x00000000 /* DENALI_PHY_469_DATA */ + 0x00000000 /* DENALI_PHY_470_DATA */ + 0x00000000 /* DENALI_PHY_471_DATA */ + 0x00000000 /* DENALI_PHY_472_DATA */ + 0x00000000 /* DENALI_PHY_473_DATA */ + 0x00000000 /* DENALI_PHY_474_DATA */ + 0x00000000 /* DENALI_PHY_475_DATA */ + 0x00000000 /* DENALI_PHY_476_DATA */ + 0x00000000 /* DENALI_PHY_477_DATA */ + 0x00000000 /* DENALI_PHY_478_DATA */ + 0x00000000 /* DENALI_PHY_479_DATA */ + 0x00000000 /* DENALI_PHY_480_DATA */ + 0x00000000 /* DENALI_PHY_481_DATA */ + 0x00000000 /* DENALI_PHY_482_DATA */ + 0x00000000 /* DENALI_PHY_483_DATA */ + 0x00000000 /* DENALI_PHY_484_DATA */ + 0x00000000 /* DENALI_PHY_485_DATA */ + 0x00000000 /* DENALI_PHY_486_DATA */ + 0x00000000 /* DENALI_PHY_487_DATA */ + 0x00000000 /* DENALI_PHY_488_DATA */ + 0x00000000 /* DENALI_PHY_489_DATA */ + 0x00000000 /* DENALI_PHY_490_DATA */ + 0x00000000 /* DENALI_PHY_491_DATA */ + 0x00000000 /* DENALI_PHY_492_DATA */ + 0x00000000 /* DENALI_PHY_493_DATA */ + 0x00000000 /* DENALI_PHY_494_DATA */ + 0x00000000 /* DENALI_PHY_495_DATA */ + 0x00000000 /* DENALI_PHY_496_DATA */ + 0x00000000 /* DENALI_PHY_497_DATA */ + 0x00000000 /* DENALI_PHY_498_DATA */ + 0x00000000 /* DENALI_PHY_499_DATA */ + 0x00000000 /* DENALI_PHY_500_DATA */ + 0x00000000 /* DENALI_PHY_501_DATA */ + 0x00000000 /* DENALI_PHY_502_DATA */ + 0x00000000 /* DENALI_PHY_503_DATA */ + 0x00000000 /* DENALI_PHY_504_DATA */ + 0x00000000 /* DENALI_PHY_505_DATA */ + 0x00000000 /* DENALI_PHY_506_DATA */ + 0x00000000 /* DENALI_PHY_507_DATA */ + 0x00000000 /* DENALI_PHY_508_DATA */ + 0x00000000 /* DENALI_PHY_509_DATA */ + 0x00000000 /* DENALI_PHY_510_DATA */ + 0x00000000 /* DENALI_PHY_511_DATA */ + 0x24316750 /* DENALI_PHY_512_DATA */ + 0x0004c008 /* DENALI_PHY_513_DATA */ + 0x000000da /* DENALI_PHY_514_DATA */ + 0x00000000 /* DENALI_PHY_515_DATA */ + 0x00000000 /* DENALI_PHY_516_DATA */ + 0x00010000 /* DENALI_PHY_517_DATA */ + 0x01DDDD90 /* DENALI_PHY_518_DATA */ + 0x01DDDD90 /* DENALI_PHY_519_DATA */ + 0x01030000 /* DENALI_PHY_520_DATA */ + 0x01000000 /* DENALI_PHY_521_DATA */ + 0x00c00000 /* DENALI_PHY_522_DATA */ + 0x00000007 /* DENALI_PHY_523_DATA */ + 0x00000000 /* DENALI_PHY_524_DATA */ + 0x00000000 /* DENALI_PHY_525_DATA */ + 0x04000408 /* DENALI_PHY_526_DATA */ + 0x00000408 /* DENALI_PHY_527_DATA */ + 0x00e4e400 /* DENALI_PHY_528_DATA */ + 0x00000000 /* DENALI_PHY_529_DATA */ + 0x00000000 /* DENALI_PHY_530_DATA */ + 0x00000000 /* DENALI_PHY_531_DATA */ + 0x00000000 /* DENALI_PHY_532_DATA */ + 0x00000000 /* DENALI_PHY_533_DATA */ + 0x00000000 /* DENALI_PHY_534_DATA */ + 0x00000000 /* DENALI_PHY_535_DATA */ + 0x00000000 /* DENALI_PHY_536_DATA */ + 0x00000000 /* DENALI_PHY_537_DATA */ + 0x00000000 /* DENALI_PHY_538_DATA */ + 0x00000000 /* DENALI_PHY_539_DATA */ + 0x00000000 /* DENALI_PHY_540_DATA */ + 0x00000000 /* DENALI_PHY_541_DATA */ + 0x00000000 /* DENALI_PHY_542_DATA */ + 0x00000000 /* DENALI_PHY_543_DATA */ + 0x00000000 /* DENALI_PHY_544_DATA */ + 0x00200000 /* DENALI_PHY_545_DATA */ + 0x00000000 /* DENALI_PHY_546_DATA */ + 0x00000000 /* DENALI_PHY_547_DATA */ + 0x00000000 /* DENALI_PHY_548_DATA */ + 0x00000000 /* DENALI_PHY_549_DATA */ + 0x00000000 /* DENALI_PHY_550_DATA */ + 0x00000000 /* DENALI_PHY_551_DATA */ + 0x02800280 /* DENALI_PHY_552_DATA */ + 0x02800280 /* DENALI_PHY_553_DATA */ + 0x02800280 /* DENALI_PHY_554_DATA */ + 0x02800280 /* DENALI_PHY_555_DATA */ + 0x00000280 /* DENALI_PHY_556_DATA */ + 0x00000000 /* DENALI_PHY_557_DATA */ + 0x00000000 /* DENALI_PHY_558_DATA */ + 0x00000000 /* DENALI_PHY_559_DATA */ + 0x00000000 /* DENALI_PHY_560_DATA */ + 0x00000000 /* DENALI_PHY_561_DATA */ + 0x00800080 /* DENALI_PHY_562_DATA */ + 0x00800080 /* DENALI_PHY_563_DATA */ + 0x00800080 /* DENALI_PHY_564_DATA */ + 0x00800080 /* DENALI_PHY_565_DATA */ + 0x00800080 /* DENALI_PHY_566_DATA */ + 0x00800080 /* DENALI_PHY_567_DATA */ + 0x00800080 /* DENALI_PHY_568_DATA */ + 0x00800080 /* DENALI_PHY_569_DATA */ + 0x00800080 /* DENALI_PHY_570_DATA */ + 0x000100da /* DENALI_PHY_571_DATA */ + 0x00000200 /* DENALI_PHY_572_DATA */ + 0x00000000 /* DENALI_PHY_573_DATA */ + 0x00000000 /* DENALI_PHY_574_DATA */ + 0x00000002 /* DENALI_PHY_575_DATA */ + 0x51313152 /* DENALI_PHY_576_DATA */ + 0x80013130 /* DENALI_PHY_577_DATA */ + 0x02000080 /* DENALI_PHY_578_DATA */ + 0x00100001 /* DENALI_PHY_579_DATA */ + 0x0c064208 /* DENALI_PHY_580_DATA */ + 0x000f0c0f /* DENALI_PHY_581_DATA */ + 0x01000140 /* DENALI_PHY_582_DATA */ + 0x0000000c /* DENALI_PHY_583_DATA */ + 0x00000000 /* DENALI_PHY_584_DATA */ + 0x00000000 /* DENALI_PHY_585_DATA */ + 0x00000000 /* DENALI_PHY_586_DATA */ + 0x00000000 /* DENALI_PHY_587_DATA */ + 0x00000000 /* DENALI_PHY_588_DATA */ + 0x00000000 /* DENALI_PHY_589_DATA */ + 0x00000000 /* DENALI_PHY_590_DATA */ + 0x00000000 /* DENALI_PHY_591_DATA */ + 0x00000000 /* DENALI_PHY_592_DATA */ + 0x00000000 /* DENALI_PHY_593_DATA */ + 0x00000000 /* DENALI_PHY_594_DATA */ + 0x00000000 /* DENALI_PHY_595_DATA */ + 0x00000000 /* DENALI_PHY_596_DATA */ + 0x00000000 /* DENALI_PHY_597_DATA */ + 0x00000000 /* DENALI_PHY_598_DATA */ + 0x00000000 /* DENALI_PHY_599_DATA */ + 0x00000000 /* DENALI_PHY_600_DATA */ + 0x00000000 /* DENALI_PHY_601_DATA */ + 0x00000000 /* DENALI_PHY_602_DATA */ + 0x00000000 /* DENALI_PHY_603_DATA */ + 0x00000000 /* DENALI_PHY_604_DATA */ + 0x00000000 /* DENALI_PHY_605_DATA */ + 0x00000000 /* DENALI_PHY_606_DATA */ + 0x00000000 /* DENALI_PHY_607_DATA */ + 0x00000000 /* DENALI_PHY_608_DATA */ + 0x00000000 /* DENALI_PHY_609_DATA */ + 0x00000000 /* DENALI_PHY_610_DATA */ + 0x00000000 /* DENALI_PHY_611_DATA */ + 0x00000000 /* DENALI_PHY_612_DATA */ + 0x00000000 /* DENALI_PHY_613_DATA */ + 0x00000000 /* DENALI_PHY_614_DATA */ + 0x00000000 /* DENALI_PHY_615_DATA */ + 0x00000000 /* DENALI_PHY_616_DATA */ + 0x00000000 /* DENALI_PHY_617_DATA */ + 0x00000000 /* DENALI_PHY_618_DATA */ + 0x00000000 /* DENALI_PHY_619_DATA */ + 0x00000000 /* DENALI_PHY_620_DATA */ + 0x00000000 /* DENALI_PHY_621_DATA */ + 0x00000000 /* DENALI_PHY_622_DATA */ + 0x00000000 /* DENALI_PHY_623_DATA */ + 0x00000000 /* DENALI_PHY_624_DATA */ + 0x00000000 /* DENALI_PHY_625_DATA */ + 0x00000000 /* DENALI_PHY_626_DATA */ + 0x00000000 /* DENALI_PHY_627_DATA */ + 0x00000000 /* DENALI_PHY_628_DATA */ + 0x00000000 /* DENALI_PHY_629_DATA */ + 0x00000000 /* DENALI_PHY_630_DATA */ + 0x00000000 /* DENALI_PHY_631_DATA */ + 0x00000000 /* DENALI_PHY_632_DATA */ + 0x00000000 /* DENALI_PHY_633_DATA */ + 0x00000000 /* DENALI_PHY_634_DATA */ + 0x00000000 /* DENALI_PHY_635_DATA */ + 0x00000000 /* DENALI_PHY_636_DATA */ + 0x00000000 /* DENALI_PHY_637_DATA */ + 0x00000000 /* DENALI_PHY_638_DATA */ + 0x00000000 /* DENALI_PHY_639_DATA */ + 0x35174620 /* DENALI_PHY_640_DATA */ + 0x0004c008 /* DENALI_PHY_641_DATA */ + 0x000000da /* DENALI_PHY_642_DATA */ + 0x00000000 /* DENALI_PHY_643_DATA */ + 0x00000000 /* DENALI_PHY_644_DATA */ + 0x00010000 /* DENALI_PHY_645_DATA */ + 0x01DDDD90 /* DENALI_PHY_646_DATA */ + 0x01DDDD90 /* DENALI_PHY_647_DATA */ + 0x01030000 /* DENALI_PHY_648_DATA */ + 0x01000000 /* DENALI_PHY_649_DATA */ + 0x00c00000 /* DENALI_PHY_650_DATA */ + 0x00000007 /* DENALI_PHY_651_DATA */ + 0x00000000 /* DENALI_PHY_652_DATA */ + 0x00000000 /* DENALI_PHY_653_DATA */ + 0x04000408 /* DENALI_PHY_654_DATA */ + 0x00000408 /* DENALI_PHY_655_DATA */ + 0x00e4e400 /* DENALI_PHY_656_DATA */ + 0x00000000 /* DENALI_PHY_657_DATA */ + 0x00000000 /* DENALI_PHY_658_DATA */ + 0x00000000 /* DENALI_PHY_659_DATA */ + 0x00000000 /* DENALI_PHY_660_DATA */ + 0x00000000 /* DENALI_PHY_661_DATA */ + 0x00000000 /* DENALI_PHY_662_DATA */ + 0x00000000 /* DENALI_PHY_663_DATA */ + 0x00000000 /* DENALI_PHY_664_DATA */ + 0x00000000 /* DENALI_PHY_665_DATA */ + 0x00000000 /* DENALI_PHY_666_DATA */ + 0x00000000 /* DENALI_PHY_667_DATA */ + 0x00000000 /* DENALI_PHY_668_DATA */ + 0x00000000 /* DENALI_PHY_669_DATA */ + 0x00000000 /* DENALI_PHY_670_DATA */ + 0x00000000 /* DENALI_PHY_671_DATA */ + 0x00000000 /* DENALI_PHY_672_DATA */ + 0x00200000 /* DENALI_PHY_673_DATA */ + 0x00000000 /* DENALI_PHY_674_DATA */ + 0x00000000 /* DENALI_PHY_675_DATA */ + 0x00000000 /* DENALI_PHY_676_DATA */ + 0x00000000 /* DENALI_PHY_677_DATA */ + 0x00000000 /* DENALI_PHY_678_DATA */ + 0x00000000 /* DENALI_PHY_679_DATA */ + 0x02800280 /* DENALI_PHY_680_DATA */ + 0x02800280 /* DENALI_PHY_681_DATA */ + 0x02800280 /* DENALI_PHY_682_DATA */ + 0x02800280 /* DENALI_PHY_683_DATA */ + 0x00000280 /* DENALI_PHY_684_DATA */ + 0x00000000 /* DENALI_PHY_685_DATA */ + 0x00000000 /* DENALI_PHY_686_DATA */ + 0x00000000 /* DENALI_PHY_687_DATA */ + 0x00000000 /* DENALI_PHY_688_DATA */ + 0x00000000 /* DENALI_PHY_689_DATA */ + 0x00800080 /* DENALI_PHY_690_DATA */ + 0x00800080 /* DENALI_PHY_691_DATA */ + 0x00800080 /* DENALI_PHY_692_DATA */ + 0x00800080 /* DENALI_PHY_693_DATA */ + 0x00800080 /* DENALI_PHY_694_DATA */ + 0x00800080 /* DENALI_PHY_695_DATA */ + 0x00800080 /* DENALI_PHY_696_DATA */ + 0x00800080 /* DENALI_PHY_697_DATA */ + 0x00800080 /* DENALI_PHY_698_DATA */ + 0x000100da /* DENALI_PHY_699_DATA */ + 0x00000200 /* DENALI_PHY_700_DATA */ + 0x00000000 /* DENALI_PHY_701_DATA */ + 0x00000000 /* DENALI_PHY_702_DATA */ + 0x00000002 /* DENALI_PHY_703_DATA */ + 0x51313152 /* DENALI_PHY_704_DATA */ + 0x80013130 /* DENALI_PHY_705_DATA */ + 0x02000080 /* DENALI_PHY_706_DATA */ + 0x00100001 /* DENALI_PHY_707_DATA */ + 0x0c064208 /* DENALI_PHY_708_DATA */ + 0x000f0c0f /* DENALI_PHY_709_DATA */ + 0x01000140 /* DENALI_PHY_710_DATA */ + 0x0000000c /* DENALI_PHY_711_DATA */ + 0x00000000 /* DENALI_PHY_712_DATA */ + 0x00000000 /* DENALI_PHY_713_DATA */ + 0x00000000 /* DENALI_PHY_714_DATA */ + 0x00000000 /* DENALI_PHY_715_DATA */ + 0x00000000 /* DENALI_PHY_716_DATA */ + 0x00000000 /* DENALI_PHY_717_DATA */ + 0x00000000 /* DENALI_PHY_718_DATA */ + 0x00000000 /* DENALI_PHY_719_DATA */ + 0x00000000 /* DENALI_PHY_720_DATA */ + 0x00000000 /* DENALI_PHY_721_DATA */ + 0x00000000 /* DENALI_PHY_722_DATA */ + 0x00000000 /* DENALI_PHY_723_DATA */ + 0x00000000 /* DENALI_PHY_724_DATA */ + 0x00000000 /* DENALI_PHY_725_DATA */ + 0x00000000 /* DENALI_PHY_726_DATA */ + 0x00000000 /* DENALI_PHY_727_DATA */ + 0x00000000 /* DENALI_PHY_728_DATA */ + 0x00000000 /* DENALI_PHY_729_DATA */ + 0x00000000 /* DENALI_PHY_730_DATA */ + 0x00000000 /* DENALI_PHY_731_DATA */ + 0x00000000 /* DENALI_PHY_732_DATA */ + 0x00000000 /* DENALI_PHY_733_DATA */ + 0x00000000 /* DENALI_PHY_734_DATA */ + 0x00000000 /* DENALI_PHY_735_DATA */ + 0x00000000 /* DENALI_PHY_736_DATA */ + 0x00000000 /* DENALI_PHY_737_DATA */ + 0x00000000 /* DENALI_PHY_738_DATA */ + 0x00000000 /* DENALI_PHY_739_DATA */ + 0x00000000 /* DENALI_PHY_740_DATA */ + 0x00000000 /* DENALI_PHY_741_DATA */ + 0x00000000 /* DENALI_PHY_742_DATA */ + 0x00000000 /* DENALI_PHY_743_DATA */ + 0x00000000 /* DENALI_PHY_744_DATA */ + 0x00000000 /* DENALI_PHY_745_DATA */ + 0x00000000 /* DENALI_PHY_746_DATA */ + 0x00000000 /* DENALI_PHY_747_DATA */ + 0x00000000 /* DENALI_PHY_748_DATA */ + 0x00000000 /* DENALI_PHY_749_DATA */ + 0x00000000 /* DENALI_PHY_750_DATA */ + 0x00000000 /* DENALI_PHY_751_DATA */ + 0x00000000 /* DENALI_PHY_752_DATA */ + 0x00000000 /* DENALI_PHY_753_DATA */ + 0x00000000 /* DENALI_PHY_754_DATA */ + 0x00000000 /* DENALI_PHY_755_DATA */ + 0x00000000 /* DENALI_PHY_756_DATA */ + 0x00000000 /* DENALI_PHY_757_DATA */ + 0x00000000 /* DENALI_PHY_758_DATA */ + 0x00000000 /* DENALI_PHY_759_DATA */ + 0x00000000 /* DENALI_PHY_760_DATA */ + 0x00000000 /* DENALI_PHY_761_DATA */ + 0x00000000 /* DENALI_PHY_762_DATA */ + 0x00000000 /* DENALI_PHY_763_DATA */ + 0x00000000 /* DENALI_PHY_764_DATA */ + 0x00000000 /* DENALI_PHY_765_DATA */ + 0x00000000 /* DENALI_PHY_766_DATA */ + 0x00000000 /* DENALI_PHY_767_DATA */ + 0x15203476 /* DENALI_PHY_768_DATA */ + 0x0004c008 /* DENALI_PHY_769_DATA */ + 0x000000da /* DENALI_PHY_770_DATA */ + 0x00000000 /* DENALI_PHY_771_DATA */ + 0x00000000 /* DENALI_PHY_772_DATA */ + 0x00010000 /* DENALI_PHY_773_DATA */ + 0x01DDDD90 /* DENALI_PHY_774_DATA */ + 0x01DDDD90 /* DENALI_PHY_775_DATA */ + 0x01030000 /* DENALI_PHY_776_DATA */ + 0x01000000 /* DENALI_PHY_777_DATA */ + 0x00c00000 /* DENALI_PHY_778_DATA */ + 0x00000007 /* DENALI_PHY_779_DATA */ + 0x00000000 /* DENALI_PHY_780_DATA */ + 0x00000000 /* DENALI_PHY_781_DATA */ + 0x04000408 /* DENALI_PHY_782_DATA */ + 0x00000408 /* DENALI_PHY_783_DATA */ + 0x00e4e400 /* DENALI_PHY_784_DATA */ + 0x00000000 /* DENALI_PHY_785_DATA */ + 0x00000000 /* DENALI_PHY_786_DATA */ + 0x00000000 /* DENALI_PHY_787_DATA */ + 0x00000000 /* DENALI_PHY_788_DATA */ + 0x00000000 /* DENALI_PHY_789_DATA */ + 0x00000000 /* DENALI_PHY_790_DATA */ + 0x00000000 /* DENALI_PHY_791_DATA */ + 0x00000000 /* DENALI_PHY_792_DATA */ + 0x00000000 /* DENALI_PHY_793_DATA */ + 0x00000000 /* DENALI_PHY_794_DATA */ + 0x00000000 /* DENALI_PHY_795_DATA */ + 0x00000000 /* DENALI_PHY_796_DATA */ + 0x00000000 /* DENALI_PHY_797_DATA */ + 0x00000000 /* DENALI_PHY_798_DATA */ + 0x00000000 /* DENALI_PHY_799_DATA */ + 0x00000000 /* DENALI_PHY_800_DATA */ + 0x00200000 /* DENALI_PHY_801_DATA */ + 0x00000000 /* DENALI_PHY_802_DATA */ + 0x00000000 /* DENALI_PHY_803_DATA */ + 0x00000000 /* DENALI_PHY_804_DATA */ + 0x00000000 /* DENALI_PHY_805_DATA */ + 0x00000000 /* DENALI_PHY_806_DATA */ + 0x00000000 /* DENALI_PHY_807_DATA */ + 0x02800280 /* DENALI_PHY_808_DATA */ + 0x02800280 /* DENALI_PHY_809_DATA */ + 0x02800280 /* DENALI_PHY_810_DATA */ + 0x02800280 /* DENALI_PHY_811_DATA */ + 0x00000280 /* DENALI_PHY_812_DATA */ + 0x00000000 /* DENALI_PHY_813_DATA */ + 0x00000000 /* DENALI_PHY_814_DATA */ + 0x00000000 /* DENALI_PHY_815_DATA */ + 0x00000000 /* DENALI_PHY_816_DATA */ + 0x00000000 /* DENALI_PHY_817_DATA */ + 0x00800080 /* DENALI_PHY_818_DATA */ + 0x00800080 /* DENALI_PHY_819_DATA */ + 0x00800080 /* DENALI_PHY_820_DATA */ + 0x00800080 /* DENALI_PHY_821_DATA */ + 0x00800080 /* DENALI_PHY_822_DATA */ + 0x00800080 /* DENALI_PHY_823_DATA */ + 0x00800080 /* DENALI_PHY_824_DATA */ + 0x00800080 /* DENALI_PHY_825_DATA */ + 0x00800080 /* DENALI_PHY_826_DATA */ + 0x000100da /* DENALI_PHY_827_DATA */ + 0x00000200 /* DENALI_PHY_828_DATA */ + 0x00000000 /* DENALI_PHY_829_DATA */ + 0x00000000 /* DENALI_PHY_830_DATA */ + 0x00000002 /* DENALI_PHY_831_DATA */ + 0x51313152 /* DENALI_PHY_832_DATA */ + 0x80013130 /* DENALI_PHY_833_DATA */ + 0x02000080 /* DENALI_PHY_834_DATA */ + 0x00100001 /* DENALI_PHY_835_DATA */ + 0x0c064208 /* DENALI_PHY_836_DATA */ + 0x000f0c0f /* DENALI_PHY_837_DATA */ + 0x01000140 /* DENALI_PHY_838_DATA */ + 0x0000000c /* DENALI_PHY_839_DATA */ + 0x00000000 /* DENALI_PHY_840_DATA */ + 0x00000000 /* DENALI_PHY_841_DATA */ + 0x00000000 /* DENALI_PHY_842_DATA */ + 0x00000000 /* DENALI_PHY_843_DATA */ + 0x00000000 /* DENALI_PHY_844_DATA */ + 0x00000000 /* DENALI_PHY_845_DATA */ + 0x00000000 /* DENALI_PHY_846_DATA */ + 0x00000000 /* DENALI_PHY_847_DATA */ + 0x00000000 /* DENALI_PHY_848_DATA */ + 0x00000000 /* DENALI_PHY_849_DATA */ + 0x00000000 /* DENALI_PHY_850_DATA */ + 0x00000000 /* DENALI_PHY_851_DATA */ + 0x00000000 /* DENALI_PHY_852_DATA */ + 0x00000000 /* DENALI_PHY_853_DATA */ + 0x00000000 /* DENALI_PHY_854_DATA */ + 0x00000000 /* DENALI_PHY_855_DATA */ + 0x00000000 /* DENALI_PHY_856_DATA */ + 0x00000000 /* DENALI_PHY_857_DATA */ + 0x00000000 /* DENALI_PHY_858_DATA */ + 0x00000000 /* DENALI_PHY_859_DATA */ + 0x00000000 /* DENALI_PHY_860_DATA */ + 0x00000000 /* DENALI_PHY_861_DATA */ + 0x00000000 /* DENALI_PHY_862_DATA */ + 0x00000000 /* DENALI_PHY_863_DATA */ + 0x00000000 /* DENALI_PHY_864_DATA */ + 0x00000000 /* DENALI_PHY_865_DATA */ + 0x00000000 /* DENALI_PHY_866_DATA */ + 0x00000000 /* DENALI_PHY_867_DATA */ + 0x00000000 /* DENALI_PHY_868_DATA */ + 0x00000000 /* DENALI_PHY_869_DATA */ + 0x00000000 /* DENALI_PHY_870_DATA */ + 0x00000000 /* DENALI_PHY_871_DATA */ + 0x00000000 /* DENALI_PHY_872_DATA */ + 0x00000000 /* DENALI_PHY_873_DATA */ + 0x00000000 /* DENALI_PHY_874_DATA */ + 0x00000000 /* DENALI_PHY_875_DATA */ + 0x00000000 /* DENALI_PHY_876_DATA */ + 0x00000000 /* DENALI_PHY_877_DATA */ + 0x00000000 /* DENALI_PHY_878_DATA */ + 0x00000000 /* DENALI_PHY_879_DATA */ + 0x00000000 /* DENALI_PHY_880_DATA */ + 0x00000000 /* DENALI_PHY_881_DATA */ + 0x00000000 /* DENALI_PHY_882_DATA */ + 0x00000000 /* DENALI_PHY_883_DATA */ + 0x00000000 /* DENALI_PHY_884_DATA */ + 0x00000000 /* DENALI_PHY_885_DATA */ + 0x00000000 /* DENALI_PHY_886_DATA */ + 0x00000000 /* DENALI_PHY_887_DATA */ + 0x00000000 /* DENALI_PHY_888_DATA */ + 0x00000000 /* DENALI_PHY_889_DATA */ + 0x00000000 /* DENALI_PHY_890_DATA */ + 0x00000000 /* DENALI_PHY_891_DATA */ + 0x00000000 /* DENALI_PHY_892_DATA */ + 0x00000000 /* DENALI_PHY_893_DATA */ + 0x00000000 /* DENALI_PHY_894_DATA */ + 0x00000000 /* DENALI_PHY_895_DATA */ + 0x41753206 /* DENALI_PHY_896_DATA */ + 0x0004c008 /* DENALI_PHY_897_DATA */ + 0x000000da /* DENALI_PHY_898_DATA */ + 0x00000000 /* DENALI_PHY_899_DATA */ + 0x00000000 /* DENALI_PHY_900_DATA */ + 0x00010000 /* DENALI_PHY_901_DATA */ + 0x01DDDD90 /* DENALI_PHY_902_DATA */ + 0x01DDDD90 /* DENALI_PHY_903_DATA */ + 0x01030000 /* DENALI_PHY_904_DATA */ + 0x01000000 /* DENALI_PHY_905_DATA */ + 0x00c00000 /* DENALI_PHY_906_DATA */ + 0x00000007 /* DENALI_PHY_907_DATA */ + 0x00000000 /* DENALI_PHY_908_DATA */ + 0x00000000 /* DENALI_PHY_909_DATA */ + 0x04000408 /* DENALI_PHY_910_DATA */ + 0x00000408 /* DENALI_PHY_911_DATA */ + 0x00e4e400 /* DENALI_PHY_912_DATA */ + 0x00000000 /* DENALI_PHY_913_DATA */ + 0x00000000 /* DENALI_PHY_914_DATA */ + 0x00000000 /* DENALI_PHY_915_DATA */ + 0x00000000 /* DENALI_PHY_916_DATA */ + 0x00000000 /* DENALI_PHY_917_DATA */ + 0x00000000 /* DENALI_PHY_918_DATA */ + 0x00000000 /* DENALI_PHY_919_DATA */ + 0x00000000 /* DENALI_PHY_920_DATA */ + 0x00000000 /* DENALI_PHY_921_DATA */ + 0x00000000 /* DENALI_PHY_922_DATA */ + 0x00000000 /* DENALI_PHY_923_DATA */ + 0x00000000 /* DENALI_PHY_924_DATA */ + 0x00000000 /* DENALI_PHY_925_DATA */ + 0x00000000 /* DENALI_PHY_926_DATA */ + 0x00000000 /* DENALI_PHY_927_DATA */ + 0x00000000 /* DENALI_PHY_928_DATA */ + 0x00200000 /* DENALI_PHY_929_DATA */ + 0x00000000 /* DENALI_PHY_930_DATA */ + 0x00000000 /* DENALI_PHY_931_DATA */ + 0x00000000 /* DENALI_PHY_932_DATA */ + 0x00000000 /* DENALI_PHY_933_DATA */ + 0x00000000 /* DENALI_PHY_934_DATA */ + 0x00000000 /* DENALI_PHY_935_DATA */ + 0x02800280 /* DENALI_PHY_936_DATA */ + 0x02800280 /* DENALI_PHY_937_DATA */ + 0x02800280 /* DENALI_PHY_938_DATA */ + 0x02800280 /* DENALI_PHY_939_DATA */ + 0x00000280 /* DENALI_PHY_940_DATA */ + 0x00000000 /* DENALI_PHY_941_DATA */ + 0x00000000 /* DENALI_PHY_942_DATA */ + 0x00000000 /* DENALI_PHY_943_DATA */ + 0x00000000 /* DENALI_PHY_944_DATA */ + 0x00000000 /* DENALI_PHY_945_DATA */ + 0x00800080 /* DENALI_PHY_946_DATA */ + 0x00800080 /* DENALI_PHY_947_DATA */ + 0x00800080 /* DENALI_PHY_948_DATA */ + 0x00800080 /* DENALI_PHY_949_DATA */ + 0x00800080 /* DENALI_PHY_950_DATA */ + 0x00800080 /* DENALI_PHY_951_DATA */ + 0x00800080 /* DENALI_PHY_952_DATA */ + 0x00800080 /* DENALI_PHY_953_DATA */ + 0x00800080 /* DENALI_PHY_954_DATA */ + 0x000100da /* DENALI_PHY_955_DATA */ + 0x00000200 /* DENALI_PHY_956_DATA */ + 0x00000000 /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + 0x00000002 /* DENALI_PHY_959_DATA */ + 0x51313152 /* DENALI_PHY_960_DATA */ + 0x80013130 /* DENALI_PHY_961_DATA */ + 0x02000080 /* DENALI_PHY_962_DATA */ + 0x00100001 /* DENALI_PHY_963_DATA */ + 0x0c064208 /* DENALI_PHY_964_DATA */ + 0x000f0c0f /* DENALI_PHY_965_DATA */ + 0x01000140 /* DENALI_PHY_966_DATA */ + 0x0000000c /* DENALI_PHY_967_DATA */ + 0x00000000 /* DENALI_PHY_968_DATA */ + 0x00000000 /* DENALI_PHY_969_DATA */ + 0x00000000 /* DENALI_PHY_970_DATA */ + 0x00000000 /* DENALI_PHY_971_DATA */ + 0x00000000 /* DENALI_PHY_972_DATA */ + 0x00000000 /* DENALI_PHY_973_DATA */ + 0x00000000 /* DENALI_PHY_974_DATA */ + 0x00000000 /* DENALI_PHY_975_DATA */ + 0x00000000 /* DENALI_PHY_976_DATA */ + 0x00000000 /* DENALI_PHY_977_DATA */ + 0x00000000 /* DENALI_PHY_978_DATA */ + 0x00000000 /* DENALI_PHY_979_DATA */ + 0x00000000 /* DENALI_PHY_980_DATA */ + 0x00000000 /* DENALI_PHY_981_DATA */ + 0x00000000 /* DENALI_PHY_982_DATA */ + 0x00000000 /* DENALI_PHY_983_DATA */ + 0x00000000 /* DENALI_PHY_984_DATA */ + 0x00000000 /* DENALI_PHY_985_DATA */ + 0x00000000 /* DENALI_PHY_986_DATA */ + 0x00000000 /* DENALI_PHY_987_DATA */ + 0x00000000 /* DENALI_PHY_988_DATA */ + 0x00000000 /* DENALI_PHY_989_DATA */ + 0x00000000 /* DENALI_PHY_990_DATA */ + 0x00000000 /* DENALI_PHY_991_DATA */ + 0x00000000 /* DENALI_PHY_992_DATA */ + 0x00000000 /* DENALI_PHY_993_DATA */ + 0x00000000 /* DENALI_PHY_994_DATA */ + 0x00000000 /* DENALI_PHY_995_DATA */ + 0x00000000 /* DENALI_PHY_996_DATA */ + 0x00000000 /* DENALI_PHY_997_DATA */ + 0x00000000 /* DENALI_PHY_998_DATA */ + 0x00000000 /* DENALI_PHY_999_DATA */ + 0x00000000 /* DENALI_PHY_1000_DATA */ + 0x00000000 /* DENALI_PHY_1001_DATA */ + 0x00000000 /* DENALI_PHY_1002_DATA */ + 0x00000000 /* DENALI_PHY_1003_DATA */ + 0x00000000 /* DENALI_PHY_1004_DATA */ + 0x00000000 /* DENALI_PHY_1005_DATA */ + 0x00000000 /* DENALI_PHY_1006_DATA */ + 0x00000000 /* DENALI_PHY_1007_DATA */ + 0x00000000 /* DENALI_PHY_1008_DATA */ + 0x00000000 /* DENALI_PHY_1009_DATA */ + 0x00000000 /* DENALI_PHY_1010_DATA */ + 0x00000000 /* DENALI_PHY_1011_DATA */ + 0x00000000 /* DENALI_PHY_1012_DATA */ + 0x00000000 /* DENALI_PHY_1013_DATA */ + 0x00000000 /* DENALI_PHY_1014_DATA */ + 0x00000000 /* DENALI_PHY_1015_DATA */ + 0x00000000 /* DENALI_PHY_1016_DATA */ + 0x00000000 /* DENALI_PHY_1017_DATA */ + 0x00000000 /* DENALI_PHY_1018_DATA */ + 0x00000000 /* DENALI_PHY_1019_DATA */ + 0x00000000 /* DENALI_PHY_1020_DATA */ + 0x00000000 /* DENALI_PHY_1021_DATA */ + 0x00000000 /* DENALI_PHY_1022_DATA */ + 0x00000000 /* DENALI_PHY_1023_DATA */ + 0x36025174 /* DENALI_PHY_1024_DATA */ + 0x0004c008 /* DENALI_PHY_1025_DATA */ + 0x000000da /* DENALI_PHY_1026_DATA */ + 0x00000000 /* DENALI_PHY_1027_DATA */ + 0x00000000 /* DENALI_PHY_1028_DATA */ + 0x00010000 /* DENALI_PHY_1029_DATA */ + 0x01DDDD90 /* DENALI_PHY_1030_DATA */ + 0x01DDDD90 /* DENALI_PHY_1031_DATA */ + 0x01030000 /* DENALI_PHY_1032_DATA */ + 0x01000000 /* DENALI_PHY_1033_DATA */ + 0x00c00000 /* DENALI_PHY_1034_DATA */ + 0x00000007 /* DENALI_PHY_1035_DATA */ + 0x00000000 /* DENALI_PHY_1036_DATA */ + 0x00000000 /* DENALI_PHY_1037_DATA */ + 0x04000408 /* DENALI_PHY_1038_DATA */ + 0x00000408 /* DENALI_PHY_1039_DATA */ + 0x00e4e400 /* DENALI_PHY_1040_DATA */ + 0x00000000 /* DENALI_PHY_1041_DATA */ + 0x00000000 /* DENALI_PHY_1042_DATA */ + 0x00000000 /* DENALI_PHY_1043_DATA */ + 0x00000000 /* DENALI_PHY_1044_DATA */ + 0x00000000 /* DENALI_PHY_1045_DATA */ + 0x00000000 /* DENALI_PHY_1046_DATA */ + 0x00000000 /* DENALI_PHY_1047_DATA */ + 0x00000000 /* DENALI_PHY_1048_DATA */ + 0x00000000 /* DENALI_PHY_1049_DATA */ + 0x00000000 /* DENALI_PHY_1050_DATA */ + 0x00000000 /* DENALI_PHY_1051_DATA */ + 0x00000000 /* DENALI_PHY_1052_DATA */ + 0x00000000 /* DENALI_PHY_1053_DATA */ + 0x00000000 /* DENALI_PHY_1054_DATA */ + 0x00000000 /* DENALI_PHY_1055_DATA */ + 0x00000000 /* DENALI_PHY_1056_DATA */ + 0x00200000 /* DENALI_PHY_1057_DATA */ + 0x00000000 /* DENALI_PHY_1058_DATA */ + 0x00000000 /* DENALI_PHY_1059_DATA */ + 0x00000000 /* DENALI_PHY_1060_DATA */ + 0x00000000 /* DENALI_PHY_1061_DATA */ + 0x00000000 /* DENALI_PHY_1062_DATA */ + 0x00000000 /* DENALI_PHY_1063_DATA */ + 0x02800280 /* DENALI_PHY_1064_DATA */ + 0x02800280 /* DENALI_PHY_1065_DATA */ + 0x02800280 /* DENALI_PHY_1066_DATA */ + 0x02800280 /* DENALI_PHY_1067_DATA */ + 0x00000280 /* DENALI_PHY_1068_DATA */ + 0x00000000 /* DENALI_PHY_1069_DATA */ + 0x00000000 /* DENALI_PHY_1070_DATA */ + 0x00000000 /* DENALI_PHY_1071_DATA */ + 0x00000000 /* DENALI_PHY_1072_DATA */ + 0x00000000 /* DENALI_PHY_1073_DATA */ + 0x00800080 /* DENALI_PHY_1074_DATA */ + 0x00800080 /* DENALI_PHY_1075_DATA */ + 0x00800080 /* DENALI_PHY_1076_DATA */ + 0x00800080 /* DENALI_PHY_1077_DATA */ + 0x00800080 /* DENALI_PHY_1078_DATA */ + 0x00800080 /* DENALI_PHY_1079_DATA */ + 0x00800080 /* DENALI_PHY_1080_DATA */ + 0x00800080 /* DENALI_PHY_1081_DATA */ + 0x00800080 /* DENALI_PHY_1082_DATA */ + 0x000100da /* DENALI_PHY_1083_DATA */ + 0x00000200 /* DENALI_PHY_1084_DATA */ + 0x00000000 /* DENALI_PHY_1085_DATA */ + 0x00000000 /* DENALI_PHY_1086_DATA */ + 0x00000002 /* DENALI_PHY_1087_DATA */ + 0x51313152 /* DENALI_PHY_1088_DATA */ + 0x80013130 /* DENALI_PHY_1089_DATA */ + 0x02000080 /* DENALI_PHY_1090_DATA */ + 0x00100001 /* DENALI_PHY_1091_DATA */ + 0x0c064208 /* DENALI_PHY_1092_DATA */ + 0x000f0c0f /* DENALI_PHY_1093_DATA */ + 0x01000140 /* DENALI_PHY_1094_DATA */ + 0x0000000c /* DENALI_PHY_1095_DATA */ + 0x00000000 /* DENALI_PHY_1096_DATA */ + 0x00000000 /* DENALI_PHY_1097_DATA */ + 0x00000000 /* DENALI_PHY_1098_DATA */ + 0x00000000 /* DENALI_PHY_1099_DATA */ + 0x00000000 /* DENALI_PHY_1100_DATA */ + 0x00000000 /* DENALI_PHY_1101_DATA */ + 0x00000000 /* DENALI_PHY_1102_DATA */ + 0x00000000 /* DENALI_PHY_1103_DATA */ + 0x00000000 /* DENALI_PHY_1104_DATA */ + 0x00000000 /* DENALI_PHY_1105_DATA */ + 0x00000000 /* DENALI_PHY_1106_DATA */ + 0x00000000 /* DENALI_PHY_1107_DATA */ + 0x00000000 /* DENALI_PHY_1108_DATA */ + 0x00000000 /* DENALI_PHY_1109_DATA */ + 0x00000000 /* DENALI_PHY_1110_DATA */ + 0x00000000 /* DENALI_PHY_1111_DATA */ + 0x00000000 /* DENALI_PHY_1112_DATA */ + 0x00000000 /* DENALI_PHY_1113_DATA */ + 0x00000000 /* DENALI_PHY_1114_DATA */ + 0x00000000 /* DENALI_PHY_1115_DATA */ + 0x00000000 /* DENALI_PHY_1116_DATA */ + 0x00000000 /* DENALI_PHY_1117_DATA */ + 0x00000000 /* DENALI_PHY_1118_DATA */ + 0x00000000 /* DENALI_PHY_1119_DATA */ + 0x00000000 /* DENALI_PHY_1120_DATA */ + 0x00000000 /* DENALI_PHY_1121_DATA */ + 0x00000000 /* DENALI_PHY_1122_DATA */ + 0x00000000 /* DENALI_PHY_1123_DATA */ + 0x00000000 /* DENALI_PHY_1124_DATA */ + 0x00000000 /* DENALI_PHY_1125_DATA */ + 0x00000000 /* DENALI_PHY_1126_DATA */ + 0x00000000 /* DENALI_PHY_1127_DATA */ + 0x00000000 /* DENALI_PHY_1128_DATA */ + 0x00000000 /* DENALI_PHY_1129_DATA */ + 0x00000000 /* DENALI_PHY_1130_DATA */ + 0x00000000 /* DENALI_PHY_1131_DATA */ + 0x00000000 /* DENALI_PHY_1132_DATA */ + 0x00000000 /* DENALI_PHY_1133_DATA */ + 0x00000000 /* DENALI_PHY_1134_DATA */ + 0x00000000 /* DENALI_PHY_1135_DATA */ + 0x00000000 /* DENALI_PHY_1136_DATA */ + 0x00000000 /* DENALI_PHY_1137_DATA */ + 0x00000000 /* DENALI_PHY_1138_DATA */ + 0x00000000 /* DENALI_PHY_1139_DATA */ + 0x00000000 /* DENALI_PHY_1140_DATA */ + 0x00000000 /* DENALI_PHY_1141_DATA */ + 0x00000000 /* DENALI_PHY_1142_DATA */ + 0x00000000 /* DENALI_PHY_1143_DATA */ + 0x00000000 /* DENALI_PHY_1144_DATA */ + 0x00000000 /* DENALI_PHY_1145_DATA */ + 0x00000000 /* DENALI_PHY_1146_DATA */ + 0x00000000 /* DENALI_PHY_1147_DATA */ + 0x00000000 /* DENALI_PHY_1148_DATA */ + 0x00000000 /* DENALI_PHY_1149_DATA */ + 0x00000000 /* DENALI_PHY_1150_DATA */ + 0x00000000 /* DENALI_PHY_1151_DATA */ + 0x00000000 /* DENALI_PHY_1152_DATA */ + 0x00000000 /* DENALI_PHY_1153_DATA */ + 0x00050000 /* DENALI_PHY_1154_DATA */ + 0x00000000 /* DENALI_PHY_1155_DATA */ + 0x00000000 /* DENALI_PHY_1156_DATA */ + 0x00000000 /* DENALI_PHY_1157_DATA */ + 0x00000100 /* DENALI_PHY_1158_DATA */ + 0x00000000 /* DENALI_PHY_1159_DATA */ + 0x00000000 /* DENALI_PHY_1160_DATA */ + 0x00506401 /* DENALI_PHY_1161_DATA */ + 0x01221102 /* DENALI_PHY_1162_DATA */ + 0x00000122 /* DENALI_PHY_1163_DATA */ + 0x00000000 /* DENALI_PHY_1164_DATA */ + 0x000B1F00 /* DENALI_PHY_1165_DATA */ + 0x0B1F0B1F /* DENALI_PHY_1166_DATA */ + 0x0B1F0B1B /* DENALI_PHY_1167_DATA */ + 0x0B1F0B1F /* DENALI_PHY_1168_DATA */ + 0x0B1F0B1F /* DENALI_PHY_1169_DATA */ + 0x00000B00 /* DENALI_PHY_1170_DATA */ + 0x42080010 /* DENALI_PHY_1171_DATA */ + 0x01000100 /* DENALI_PHY_1172_DATA */ + 0x01000100 /* DENALI_PHY_1173_DATA */ + 0x01000100 /* DENALI_PHY_1174_DATA */ + 0x01000100 /* DENALI_PHY_1175_DATA */ + 0x00000000 /* DENALI_PHY_1176_DATA */ + 0x00000000 /* DENALI_PHY_1177_DATA */ + 0x00000000 /* DENALI_PHY_1178_DATA */ + 0x00000000 /* DENALI_PHY_1179_DATA */ + 0x00000000 /* DENALI_PHY_1180_DATA */ + 0x00000803 /* DENALI_PHY_1181_DATA */ + 0x223FFF00 /* DENALI_PHY_1182_DATA */ + 0x000008FF /* DENALI_PHY_1183_DATA */ + 0x0000057F /* DENALI_PHY_1184_DATA */ + 0x0000057F /* DENALI_PHY_1185_DATA */ + 0x00037FFF /* DENALI_PHY_1186_DATA */ + 0x00037FFF /* DENALI_PHY_1187_DATA */ + 0x00004410 /* DENALI_PHY_1188_DATA */ + 0x00004410 /* DENALI_PHY_1189_DATA */ + 0x00004410 /* DENALI_PHY_1190_DATA */ + 0x00004410 /* DENALI_PHY_1191_DATA */ + 0x00004410 /* DENALI_PHY_1192_DATA */ + 0x00037FFF /* DENALI_PHY_1193_DATA */ + 0x00037FFF /* DENALI_PHY_1194_DATA */ + 0x00000000 /* DENALI_PHY_1195_DATA */ + 0x00000000 /* DENALI_PHY_1196_DATA */ + 0x00000000 /* DENALI_PHY_1197_DATA */ + 0x04000000 /* DENALI_PHY_1198_DATA */ + 0x00000000 /* DENALI_PHY_1199_DATA */ + 0x00000000 /* DENALI_PHY_1200_DATA */ + 0x00000108 /* DENALI_PHY_1201_DATA */ + 0x00000000 /* DENALI_PHY_1202_DATA */ + 0x00000000 /* DENALI_PHY_1203_DATA */ + 0x00000000 /* DENALI_PHY_1204_DATA */ + 0x00000001 /* DENALI_PHY_1205_DATA */ + 0x00000000 /* DENALI_PHY_1206_DATA */ + 0x00000000 /* DENALI_PHY_1207_DATA */ + 0x00000000 /* DENALI_PHY_1208_DATA */ + 0x00000000 /* DENALI_PHY_1209_DATA */ + 0x00000000 /* DENALI_PHY_1210_DATA */ + 0x00000000 /* DENALI_PHY_1211_DATA */ + 0x00020100 /* DENALI_PHY_1212_DATA */ + 0x00000000 /* DENALI_PHY_1213_DATA */ + 0x00000000 /* DENALI_PHY_1214_DATA */ + >; +}; diff --git a/roms/u-boot/arch/riscv/dts/fu740-c000-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/fu740-c000-u-boot.dtsi new file mode 100644 index 000000000..a5d0688b0 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/fu740-c000-u-boot.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) Copyright 2020-2021 SiFive, Inc + */ + +#include <dt-bindings/reset/sifive-fu740-prci.h> + +/ { + cpus { + assigned-clocks = <&prci PRCI_CLK_COREPLL>; + assigned-clock-rates = <1200000000>; + u-boot,dm-spl; + cpu0: cpu@0 { + clocks = <&prci PRCI_CLK_COREPLL>; + u-boot,dm-spl; + status = "okay"; + cpu0_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + cpu1: cpu@1 { + clocks = <&prci PRCI_CLK_COREPLL>; + u-boot,dm-spl; + cpu1_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + cpu2: cpu@2 { + clocks = <&prci PRCI_CLK_COREPLL>; + u-boot,dm-spl; + cpu2_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + cpu3: cpu@3 { + clocks = <&prci PRCI_CLK_COREPLL>; + u-boot,dm-spl; + cpu3_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + cpu4: cpu@4 { + clocks = <&prci PRCI_CLK_COREPLL>; + u-boot,dm-spl; + cpu4_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + }; + + soc { + u-boot,dm-spl; + clint: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + u-boot,dm-spl; + }; + prci: clock-controller@10000000 { + #reset-cells = <1>; + resets = <&prci PRCI_RST_DDR_CTRL_N>, + <&prci PRCI_RST_DDR_AXI_N>, + <&prci PRCI_RST_DDR_AHB_N>, + <&prci PRCI_RST_DDR_PHY_N>, + <&prci PRCI_RST_GEMGXL_N>, + <&prci PRCI_RST_CLTX_N>; + reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", + "ddr_phy", "gemgxl_reset", "cltx_reset"; + }; + dmc: dmc@100b0000 { + compatible = "sifive,fu740-c000-ddr"; + reg = <0x0 0x100b0000 0x0 0x0800 + 0x0 0x100b2000 0x0 0x2000 + 0x0 0x100b8000 0x0 0x1000>; + clocks = <&prci PRCI_CLK_DDRPLL>; + clock-frequency = <933333324>; + u-boot,dm-spl; + }; + }; +}; + +&prci { + u-boot,dm-spl; +}; + +&uart0 { + u-boot,dm-spl; +}; + +&spi0 { + u-boot,dm-spl; +}; + +ð0 { + assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clock-rates = <125125000>; +}; + +&ccache { + status = "okay"; +}; diff --git a/roms/u-boot/arch/riscv/dts/fu740-c000.dtsi b/roms/u-boot/arch/riscv/dts/fu740-c000.dtsi new file mode 100644 index 000000000..649efe400 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/fu740-c000.dtsi @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 SiFive, Inc */ + +/dts-v1/; + +#include <dt-bindings/clock/sifive-fu740-prci.h> +#include <dt-bindings/reset/sifive-fu740-prci.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu740-c000", "sifive,fu740"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = ð0; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + compatible = "sifive,bullet0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&ccache>; + reg = <0x0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible = "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0x4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <69>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu740-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu740-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <39>; + clocks = <&prci PRCI_CLK_PCLK>; + status = "disabled"; + }; + uart1: serial@10011000 { + compatible = "sifive,fu740-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <40>; + clocks = <&prci PRCI_CLK_PCLK>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci PRCI_CLK_PCLK>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c1: i2c@10031000 { + compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10031000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <53>; + clocks = <&prci PRCI_CLK_PCLK>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <41>; + clocks = <&prci PRCI_CLK_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <42>; + clocks = <&prci PRCI_CLK_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi0: spi@10050000 { + compatible = "sifive,fu740-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <43>; + clocks = <&prci PRCI_CLK_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <55>; + reg = <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm0: pwm@10020000 { + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <44 45 46 47>; + clocks = <&prci PRCI_CLK_PCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm1: pwm@10021000 { + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10021000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <48 49 50 51>; + clocks = <&prci PRCI_CLK_PCLK>; + #pwm-cells = <3>; + status = "disabled"; + }; + ccache: cache-controller@2010000 { + compatible = "sifive,fu740-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic0>; + interrupts = <19 21 22 20>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; + interrupt-parent = <&plic0>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>, <31>, <32>, <33>, <34>, <35>, <36>, + <37>, <38>; + reg = <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&prci PRCI_CLK_PCLK>; + status = "disabled"; + }; + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #num-lanes = <8>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0 + 0xd 0xf0000000 0x0 0x10000000 + 0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 + 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 + 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 + 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; + num-lanes = <0x8>; + interrupts = <56 57 58 59 60 61 62 63 64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>, + <0x0 0x0 0x0 0x4 &plic0 60>; + pwren-gpios = <&gpio 5 0>; + reset-gpios = <&gpio 8 0>; + clocks = <&prci PRCI_CLK_PCIEAUX>; + clock-names = "pcieaux"; + resets = <&prci PRCI_RST_PCIE_POWER_UP_N>; + reset-names = "rst_n"; + + status = "okay"; + }; + }; +}; diff --git a/roms/u-boot/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi b/roms/u-boot/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi new file mode 100644 index 000000000..fc3dfd195 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi @@ -0,0 +1,1489 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) Copyright 2020-2021 SiFive, Inc + */ + +&dmc { + sifive,ddr-params = < + 0x00000a00 /* DENALI_CTL_00_DATA */ + 0x00000000 /* DENALI_CTL_01_DATA */ + 0x00000000 /* DENALI_CTL_02_DATA */ + 0x00000000 /* DENALI_CTL_03_DATA */ + 0x00000000 /* DENALI_CTL_04_DATA */ + 0x00000000 /* DENALI_CTL_05_DATA */ + 0x0000000a /* DENALI_CTL_06_DATA */ + 0x0002d362 /* DENALI_CTL_07_DATA */ + 0x00071073 /* DENALI_CTL_08_DATA */ + 0x0a1c0255 /* DENALI_CTL_09_DATA */ + 0x1c1c0400 /* DENALI_CTL_10_DATA */ + 0x0404c90b /* DENALI_CTL_11_DATA */ + 0x2b050405 /* DENALI_CTL_12_DATA */ + 0x0d0c081e /* DENALI_CTL_13_DATA */ + 0x08090914 /* DENALI_CTL_14_DATA */ + 0x00fde718 /* DENALI_CTL_15_DATA */ + 0x00180a05 /* DENALI_CTL_16_DATA */ + 0x008b130d /* DENALI_CTL_17_DATA */ + 0x01000118 /* DENALI_CTL_18_DATA */ + 0x0d032001 /* DENALI_CTL_19_DATA */ + 0x00000000 /* DENALI_CTL_20_DATA */ + 0x00000101 /* DENALI_CTL_21_DATA */ + 0x00000000 /* DENALI_CTL_22_DATA */ + 0x0a000000 /* DENALI_CTL_23_DATA */ + 0x00000000 /* DENALI_CTL_24_DATA */ + 0x01450100 /* DENALI_CTL_25_DATA */ + 0x00001c36 /* DENALI_CTL_26_DATA */ + 0x00000005 /* DENALI_CTL_27_DATA */ + 0x00170006 /* DENALI_CTL_28_DATA */ + 0x014e0400 /* DENALI_CTL_29_DATA */ + 0x03010000 /* DENALI_CTL_30_DATA */ + 0x000a0e00 /* DENALI_CTL_31_DATA */ + 0x04030200 /* DENALI_CTL_32_DATA */ + 0x0000031f /* DENALI_CTL_33_DATA */ + 0x00070004 /* DENALI_CTL_34_DATA */ + 0x00000000 /* DENALI_CTL_35_DATA */ + 0x00000000 /* DENALI_CTL_36_DATA */ + 0x00000000 /* DENALI_CTL_37_DATA */ + 0x00000000 /* DENALI_CTL_38_DATA */ + 0x00000000 /* DENALI_CTL_39_DATA */ + 0x00000000 /* DENALI_CTL_40_DATA */ + 0x00000000 /* DENALI_CTL_41_DATA */ + 0x00000000 /* DENALI_CTL_42_DATA */ + 0x00000000 /* DENALI_CTL_43_DATA */ + 0x00000000 /* DENALI_CTL_44_DATA */ + 0x00000000 /* DENALI_CTL_45_DATA */ + 0x00000000 /* DENALI_CTL_46_DATA */ + 0x00000000 /* DENALI_CTL_47_DATA */ + 0x00000000 /* DENALI_CTL_48_DATA */ + 0x00000000 /* DENALI_CTL_49_DATA */ + 0x00000000 /* DENALI_CTL_50_DATA */ + 0x00000000 /* DENALI_CTL_51_DATA */ + 0x00000000 /* DENALI_CTL_52_DATA */ + 0x00000000 /* DENALI_CTL_53_DATA */ + 0x00000000 /* DENALI_CTL_54_DATA */ + 0x00000000 /* DENALI_CTL_55_DATA */ + 0x00000000 /* DENALI_CTL_56_DATA */ + 0x00000000 /* DENALI_CTL_57_DATA */ + 0x00000000 /* DENALI_CTL_58_DATA */ + 0x00000000 /* DENALI_CTL_59_DATA */ + 0x00000424 /* DENALI_CTL_60_DATA */ + 0x00000201 /* DENALI_CTL_61_DATA */ + 0x00001008 /* DENALI_CTL_62_DATA */ + 0x00000000 /* DENALI_CTL_63_DATA */ + 0x00000200 /* DENALI_CTL_64_DATA */ + 0x00000800 /* DENALI_CTL_65_DATA */ + 0x00000481 /* DENALI_CTL_66_DATA */ + 0x00000400 /* DENALI_CTL_67_DATA */ + 0x00000424 /* DENALI_CTL_68_DATA */ + 0x00000201 /* DENALI_CTL_69_DATA */ + 0x00001008 /* DENALI_CTL_70_DATA */ + 0x00000000 /* DENALI_CTL_71_DATA */ + 0x00000200 /* DENALI_CTL_72_DATA */ + 0x00000800 /* DENALI_CTL_73_DATA */ + 0x00000481 /* DENALI_CTL_74_DATA */ + 0x00000400 /* DENALI_CTL_75_DATA */ + 0x01010000 /* DENALI_CTL_76_DATA */ + 0x00000000 /* DENALI_CTL_77_DATA */ + 0x00000000 /* DENALI_CTL_78_DATA */ + 0x00000000 /* DENALI_CTL_79_DATA */ + 0x00000000 /* DENALI_CTL_80_DATA */ + 0x00000000 /* DENALI_CTL_81_DATA */ + 0x00000000 /* DENALI_CTL_82_DATA */ + 0x00000000 /* DENALI_CTL_83_DATA */ + 0x00000000 /* DENALI_CTL_84_DATA */ + 0x00000000 /* DENALI_CTL_85_DATA */ + 0x00000000 /* DENALI_CTL_86_DATA */ + 0x00000000 /* DENALI_CTL_87_DATA */ + 0x00000000 /* DENALI_CTL_88_DATA */ + 0x00000000 /* DENALI_CTL_89_DATA */ + 0x00000000 /* DENALI_CTL_90_DATA */ + 0x00000000 /* DENALI_CTL_91_DATA */ + 0x00000000 /* DENALI_CTL_92_DATA */ + 0x00000000 /* DENALI_CTL_93_DATA */ + 0x00000000 /* DENALI_CTL_94_DATA */ + 0x00000000 /* DENALI_CTL_95_DATA */ + 0x00000000 /* DENALI_CTL_96_DATA */ + 0x00000000 /* DENALI_CTL_97_DATA */ + 0x00000000 /* DENALI_CTL_98_DATA */ + 0x00000000 /* DENALI_CTL_99_DATA */ + 0x00000000 /* DENALI_CTL_100_DATA */ + 0x00000000 /* DENALI_CTL_101_DATA */ + 0x00000000 /* DENALI_CTL_102_DATA */ + 0x00000000 /* DENALI_CTL_103_DATA */ + 0x00000000 /* DENALI_CTL_104_DATA */ + 0x00000003 /* DENALI_CTL_105_DATA */ + 0x00000000 /* DENALI_CTL_106_DATA */ + 0x00000000 /* DENALI_CTL_107_DATA */ + 0x00000000 /* DENALI_CTL_108_DATA */ + 0x00000000 /* DENALI_CTL_109_DATA */ + 0x01000000 /* DENALI_CTL_110_DATA */ + 0x00040000 /* DENALI_CTL_111_DATA */ + 0x00800200 /* DENALI_CTL_112_DATA */ + 0x00000200 /* DENALI_CTL_113_DATA */ + 0x00000040 /* DENALI_CTL_114_DATA */ + 0x01000100 /* DENALI_CTL_115_DATA */ + 0x0a000002 /* DENALI_CTL_116_DATA */ + 0x0101ffff /* DENALI_CTL_117_DATA */ + 0x01010101 /* DENALI_CTL_118_DATA */ + 0x01010101 /* DENALI_CTL_119_DATA */ + 0x0000010b /* DENALI_CTL_120_DATA */ + 0x00000c03 /* DENALI_CTL_121_DATA */ + 0x00000000 /* DENALI_CTL_122_DATA */ + 0x00000000 /* DENALI_CTL_123_DATA */ + 0x00000000 /* DENALI_CTL_124_DATA */ + 0x00000000 /* DENALI_CTL_125_DATA */ + 0x00030300 /* DENALI_CTL_126_DATA */ + 0x00000000 /* DENALI_CTL_127_DATA */ + 0x00010101 /* DENALI_CTL_128_DATA */ + 0x00000000 /* DENALI_CTL_129_DATA */ + 0x00000000 /* DENALI_CTL_130_DATA */ + 0x00000000 /* DENALI_CTL_131_DATA */ + 0x00000000 /* DENALI_CTL_132_DATA */ + 0x00000000 /* DENALI_CTL_133_DATA */ + 0x00000000 /* DENALI_CTL_134_DATA */ + 0x00000000 /* DENALI_CTL_135_DATA */ + 0x00000000 /* DENALI_CTL_136_DATA */ + 0x00000000 /* DENALI_CTL_137_DATA */ + 0x00000000 /* DENALI_CTL_138_DATA */ + 0x00000000 /* DENALI_CTL_139_DATA */ + 0x00000000 /* DENALI_CTL_140_DATA */ + 0x00000000 /* DENALI_CTL_141_DATA */ + 0x00000000 /* DENALI_CTL_142_DATA */ + 0x00000000 /* DENALI_CTL_143_DATA */ + 0x00000000 /* DENALI_CTL_144_DATA */ + 0x00000000 /* DENALI_CTL_145_DATA */ + 0x00000000 /* DENALI_CTL_146_DATA */ + 0x00000000 /* DENALI_CTL_147_DATA */ + 0x00000000 /* DENALI_CTL_148_DATA */ + 0x00000000 /* DENALI_CTL_149_DATA */ + 0x00000000 /* DENALI_CTL_150_DATA */ + 0x00000000 /* DENALI_CTL_151_DATA */ + 0x00000000 /* DENALI_CTL_152_DATA */ + 0x00000000 /* DENALI_CTL_153_DATA */ + 0x00000000 /* DENALI_CTL_154_DATA */ + 0x00000000 /* DENALI_CTL_155_DATA */ + 0x00000000 /* DENALI_CTL_156_DATA */ + 0x00000000 /* DENALI_CTL_157_DATA */ + 0x00000000 /* DENALI_CTL_158_DATA */ + 0x00000000 /* DENALI_CTL_159_DATA */ + 0x00000000 /* DENALI_CTL_160_DATA */ + 0x02010102 /* DENALI_CTL_161_DATA */ + 0x0108070d /* DENALI_CTL_162_DATA */ + 0x05050300 /* DENALI_CTL_163_DATA */ + 0x04000503 /* DENALI_CTL_164_DATA */ + 0x00000000 /* DENALI_CTL_165_DATA */ + 0x00000000 /* DENALI_CTL_166_DATA */ + 0x00000000 /* DENALI_CTL_167_DATA */ + 0x00000000 /* DENALI_CTL_168_DATA */ + 0x280d0000 /* DENALI_CTL_169_DATA */ + 0x01000000 /* DENALI_CTL_170_DATA */ + 0x00000000 /* DENALI_CTL_171_DATA */ + 0x00030001 /* DENALI_CTL_172_DATA */ + 0x00000000 /* DENALI_CTL_173_DATA */ + 0x00000000 /* DENALI_CTL_174_DATA */ + 0x00000000 /* DENALI_CTL_175_DATA */ + 0x00000000 /* DENALI_CTL_176_DATA */ + 0x00000000 /* DENALI_CTL_177_DATA */ + 0x00000000 /* DENALI_CTL_178_DATA */ + 0x00000000 /* DENALI_CTL_179_DATA */ + 0x00000000 /* DENALI_CTL_180_DATA */ + 0x01000000 /* DENALI_CTL_181_DATA */ + 0x00000001 /* DENALI_CTL_182_DATA */ + 0x00000100 /* DENALI_CTL_183_DATA */ + 0x00010303 /* DENALI_CTL_184_DATA */ + 0x67676701 /* DENALI_CTL_185_DATA */ + 0x67676767 /* DENALI_CTL_186_DATA */ + 0x67676767 /* DENALI_CTL_187_DATA */ + 0x67676767 /* DENALI_CTL_188_DATA */ + 0x67676767 /* DENALI_CTL_189_DATA */ + 0x67676767 /* DENALI_CTL_190_DATA */ + 0x67676767 /* DENALI_CTL_191_DATA */ + 0x67676767 /* DENALI_CTL_192_DATA */ + 0x67676767 /* DENALI_CTL_193_DATA */ + 0x01000067 /* DENALI_CTL_194_DATA */ + 0x00000001 /* DENALI_CTL_195_DATA */ + 0x00000101 /* DENALI_CTL_196_DATA */ + 0x00000000 /* DENALI_CTL_197_DATA */ + 0x00000000 /* DENALI_CTL_198_DATA */ + 0x00000000 /* DENALI_CTL_199_DATA */ + 0x00000000 /* DENALI_CTL_200_DATA */ + 0x00000000 /* DENALI_CTL_201_DATA */ + 0x00000000 /* DENALI_CTL_202_DATA */ + 0x00000000 /* DENALI_CTL_203_DATA */ + 0x00000000 /* DENALI_CTL_204_DATA */ + 0x00000000 /* DENALI_CTL_205_DATA */ + 0x00000000 /* DENALI_CTL_206_DATA */ + 0x00000000 /* DENALI_CTL_207_DATA */ + 0x00000001 /* DENALI_CTL_208_DATA */ + 0x00000000 /* DENALI_CTL_209_DATA */ + 0x007fffff /* DENALI_CTL_210_DATA */ + 0x00000000 /* DENALI_CTL_211_DATA */ + 0x007fffff /* DENALI_CTL_212_DATA */ + 0x00000000 /* DENALI_CTL_213_DATA */ + 0x007fffff /* DENALI_CTL_214_DATA */ + 0x00000000 /* DENALI_CTL_215_DATA */ + 0x007fffff /* DENALI_CTL_216_DATA */ + 0x00000000 /* DENALI_CTL_217_DATA */ + 0x007fffff /* DENALI_CTL_218_DATA */ + 0x00000000 /* DENALI_CTL_219_DATA */ + 0x007fffff /* DENALI_CTL_220_DATA */ + 0x00000000 /* DENALI_CTL_221_DATA */ + 0x007fffff /* DENALI_CTL_222_DATA */ + 0x00000000 /* DENALI_CTL_223_DATA */ + 0x037fffff /* DENALI_CTL_224_DATA */ + 0xffffffff /* DENALI_CTL_225_DATA */ + 0x000f000f /* DENALI_CTL_226_DATA */ + 0x00ffff03 /* DENALI_CTL_227_DATA */ + 0x000fffff /* DENALI_CTL_228_DATA */ + 0x0003000f /* DENALI_CTL_229_DATA */ + 0xffffffff /* DENALI_CTL_230_DATA */ + 0x000f000f /* DENALI_CTL_231_DATA */ + 0x00ffff03 /* DENALI_CTL_232_DATA */ + 0x000fffff /* DENALI_CTL_233_DATA */ + 0x0003000f /* DENALI_CTL_234_DATA */ + 0xffffffff /* DENALI_CTL_235_DATA */ + 0x000f000f /* DENALI_CTL_236_DATA */ + 0x00ffff03 /* DENALI_CTL_237_DATA */ + 0x000fffff /* DENALI_CTL_238_DATA */ + 0x0003000f /* DENALI_CTL_239_DATA */ + 0xffffffff /* DENALI_CTL_240_DATA */ + 0x000f000f /* DENALI_CTL_241_DATA */ + 0x00ffff03 /* DENALI_CTL_242_DATA */ + 0x000fffff /* DENALI_CTL_243_DATA */ + 0x6407000f /* DENALI_CTL_244_DATA */ + 0x01640001 /* DENALI_CTL_245_DATA */ + 0x00000000 /* DENALI_CTL_246_DATA */ + 0x00000000 /* DENALI_CTL_247_DATA */ + 0x00001800 /* DENALI_CTL_248_DATA */ + 0x00386c05 /* DENALI_CTL_249_DATA */ + 0x02000200 /* DENALI_CTL_250_DATA */ + 0x02000200 /* DENALI_CTL_251_DATA */ + 0x0000386c /* DENALI_CTL_252_DATA */ + 0x00023438 /* DENALI_CTL_253_DATA */ + 0x02020d0f /* DENALI_CTL_254_DATA */ + 0x00140303 /* DENALI_CTL_255_DATA */ + 0x00000000 /* DENALI_CTL_256_DATA */ + 0x00000000 /* DENALI_CTL_257_DATA */ + 0x00001403 /* DENALI_CTL_258_DATA */ + 0x00000000 /* DENALI_CTL_259_DATA */ + 0x00000000 /* DENALI_CTL_260_DATA */ + 0x00000000 /* DENALI_CTL_261_DATA */ + 0x00000000 /* DENALI_CTL_262_DATA */ + 0x0c010000 /* DENALI_CTL_263_DATA */ + 0x00000008 /* DENALI_CTL_264_DATA */ + 0x01375642 /* DENALI_PHY_00_DATA */ + 0x0004c008 /* DENALI_PHY_01_DATA */ + 0x000000da /* DENALI_PHY_02_DATA */ + 0x00000000 /* DENALI_PHY_03_DATA */ + 0x00000000 /* DENALI_PHY_04_DATA */ + 0x00010000 /* DENALI_PHY_05_DATA */ + 0x01DDDD90 /* DENALI_PHY_06_DATA */ + 0x01DDDD90 /* DENALI_PHY_07_DATA */ + 0x01030001 /* DENALI_PHY_08_DATA */ + 0x01000000 /* DENALI_PHY_09_DATA */ + 0x00c00000 /* DENALI_PHY_10_DATA */ + 0x00000007 /* DENALI_PHY_11_DATA */ + 0x00000000 /* DENALI_PHY_12_DATA */ + 0x00000000 /* DENALI_PHY_13_DATA */ + 0x04000408 /* DENALI_PHY_14_DATA */ + 0x00000408 /* DENALI_PHY_15_DATA */ + 0x00e4e400 /* DENALI_PHY_16_DATA */ + 0x00000000 /* DENALI_PHY_17_DATA */ + 0x00000000 /* DENALI_PHY_18_DATA */ + 0x00000000 /* DENALI_PHY_19_DATA */ + 0x00000000 /* DENALI_PHY_20_DATA */ + 0x00000000 /* DENALI_PHY_21_DATA */ + 0x00000000 /* DENALI_PHY_22_DATA */ + 0x00000000 /* DENALI_PHY_23_DATA */ + 0x00000000 /* DENALI_PHY_24_DATA */ + 0x00000000 /* DENALI_PHY_25_DATA */ + 0x00000000 /* DENALI_PHY_26_DATA */ + 0x00000000 /* DENALI_PHY_27_DATA */ + 0x00000000 /* DENALI_PHY_28_DATA */ + 0x00000000 /* DENALI_PHY_29_DATA */ + 0x00000000 /* DENALI_PHY_30_DATA */ + 0x00000000 /* DENALI_PHY_31_DATA */ + 0x00000000 /* DENALI_PHY_32_DATA */ + 0x00200000 /* DENALI_PHY_33_DATA */ + 0x00000000 /* DENALI_PHY_34_DATA */ + 0x00000000 /* DENALI_PHY_35_DATA */ + 0x00000000 /* DENALI_PHY_36_DATA */ + 0x00000000 /* DENALI_PHY_37_DATA */ + 0x00000000 /* DENALI_PHY_38_DATA */ + 0x00000000 /* DENALI_PHY_39_DATA */ + 0x02800280 /* DENALI_PHY_40_DATA */ + 0x02800280 /* DENALI_PHY_41_DATA */ + 0x02800280 /* DENALI_PHY_42_DATA */ + 0x02800280 /* DENALI_PHY_43_DATA */ + 0x00000280 /* DENALI_PHY_44_DATA */ + 0x00000000 /* DENALI_PHY_45_DATA */ + 0x00000000 /* DENALI_PHY_46_DATA */ + 0x00000000 /* DENALI_PHY_47_DATA */ + 0x00000000 /* DENALI_PHY_48_DATA */ + 0x00000000 /* DENALI_PHY_49_DATA */ + 0x00800080 /* DENALI_PHY_50_DATA */ + 0x00800080 /* DENALI_PHY_51_DATA */ + 0x00800080 /* DENALI_PHY_52_DATA */ + 0x00800080 /* DENALI_PHY_53_DATA */ + 0x00800080 /* DENALI_PHY_54_DATA */ + 0x00800080 /* DENALI_PHY_55_DATA */ + 0x00800080 /* DENALI_PHY_56_DATA */ + 0x00800080 /* DENALI_PHY_57_DATA */ + 0x00800080 /* DENALI_PHY_58_DATA */ + 0x000100da /* DENALI_PHY_59_DATA */ + 0x01ff0010 /* DENALI_PHY_60_DATA */ + 0x00000000 /* DENALI_PHY_61_DATA */ + 0x00000000 /* DENALI_PHY_62_DATA */ + 0x00000002 /* DENALI_PHY_63_DATA */ + 0x51313152 /* DENALI_PHY_64_DATA */ + 0x80013130 /* DENALI_PHY_65_DATA */ + 0x02000080 /* DENALI_PHY_66_DATA */ + 0x00100001 /* DENALI_PHY_67_DATA */ + 0x0c064208 /* DENALI_PHY_68_DATA */ + 0x000f0c0f /* DENALI_PHY_69_DATA */ + 0x01000140 /* DENALI_PHY_70_DATA */ + 0x0000000c /* DENALI_PHY_71_DATA */ + 0x00000000 /* DENALI_PHY_72_DATA */ + 0x00000000 /* DENALI_PHY_73_DATA */ + 0x00000000 /* DENALI_PHY_74_DATA */ + 0x00000000 /* DENALI_PHY_75_DATA */ + 0x00000000 /* DENALI_PHY_76_DATA */ + 0x00000000 /* DENALI_PHY_77_DATA */ + 0x00000000 /* DENALI_PHY_78_DATA */ + 0x00000000 /* DENALI_PHY_79_DATA */ + 0x00000000 /* DENALI_PHY_80_DATA */ + 0x00000000 /* DENALI_PHY_81_DATA */ + 0x00000000 /* DENALI_PHY_82_DATA */ + 0x00000000 /* DENALI_PHY_83_DATA */ + 0x00000000 /* DENALI_PHY_84_DATA */ + 0x00000000 /* DENALI_PHY_85_DATA */ + 0x00000000 /* DENALI_PHY_86_DATA */ + 0x00000000 /* DENALI_PHY_87_DATA */ + 0x00000000 /* DENALI_PHY_88_DATA */ + 0x00000000 /* DENALI_PHY_89_DATA */ + 0x00000000 /* DENALI_PHY_90_DATA */ + 0x00000000 /* DENALI_PHY_91_DATA */ + 0x00000000 /* DENALI_PHY_92_DATA */ + 0x00000000 /* DENALI_PHY_93_DATA */ + 0x00000000 /* DENALI_PHY_94_DATA */ + 0x00000000 /* DENALI_PHY_95_DATA */ + 0x00000000 /* DENALI_PHY_96_DATA */ + 0x00000000 /* DENALI_PHY_97_DATA */ + 0x00000000 /* DENALI_PHY_98_DATA */ + 0x00000000 /* DENALI_PHY_99_DATA */ + 0x00000000 /* DENALI_PHY_100_DATA */ + 0x00000000 /* DENALI_PHY_101_DATA */ + 0x00000000 /* DENALI_PHY_102_DATA */ + 0x00000000 /* DENALI_PHY_103_DATA */ + 0x00000000 /* DENALI_PHY_104_DATA */ + 0x00000000 /* DENALI_PHY_105_DATA */ + 0x00000000 /* DENALI_PHY_106_DATA */ + 0x00000000 /* DENALI_PHY_107_DATA */ + 0x00000000 /* DENALI_PHY_108_DATA */ + 0x00000000 /* DENALI_PHY_109_DATA */ + 0x00000000 /* DENALI_PHY_110_DATA */ + 0x00000000 /* DENALI_PHY_111_DATA */ + 0x00000000 /* DENALI_PHY_112_DATA */ + 0x00000000 /* DENALI_PHY_113_DATA */ + 0x00000000 /* DENALI_PHY_114_DATA */ + 0x00000000 /* DENALI_PHY_115_DATA */ + 0x00000000 /* DENALI_PHY_116_DATA */ + 0x00000000 /* DENALI_PHY_117_DATA */ + 0x00000000 /* DENALI_PHY_118_DATA */ + 0x00000000 /* DENALI_PHY_119_DATA */ + 0x00000000 /* DENALI_PHY_120_DATA */ + 0x00000000 /* DENALI_PHY_121_DATA */ + 0x00000000 /* DENALI_PHY_122_DATA */ + 0x00000000 /* DENALI_PHY_123_DATA */ + 0x00000000 /* DENALI_PHY_124_DATA */ + 0x00000000 /* DENALI_PHY_125_DATA */ + 0x00000000 /* DENALI_PHY_126_DATA */ + 0x00000000 /* DENALI_PHY_127_DATA */ + 0x40263571 /* DENALI_PHY_128_DATA */ + 0x0004c008 /* DENALI_PHY_129_DATA */ + 0x000000da /* DENALI_PHY_130_DATA */ + 0x00000000 /* DENALI_PHY_131_DATA */ + 0x00000000 /* DENALI_PHY_132_DATA */ + 0x00010000 /* DENALI_PHY_133_DATA */ + 0x01DDDD90 /* DENALI_PHY_134_DATA */ + 0x01DDDD90 /* DENALI_PHY_135_DATA */ + 0x01030001 /* DENALI_PHY_136_DATA */ + 0x01000000 /* DENALI_PHY_137_DATA */ + 0x00c00000 /* DENALI_PHY_138_DATA */ + 0x00000007 /* DENALI_PHY_139_DATA */ + 0x00000000 /* DENALI_PHY_140_DATA */ + 0x00000000 /* DENALI_PHY_141_DATA */ + 0x04000408 /* DENALI_PHY_142_DATA */ + 0x00000408 /* DENALI_PHY_143_DATA */ + 0x00e4e400 /* DENALI_PHY_144_DATA */ + 0x00000000 /* DENALI_PHY_145_DATA */ + 0x00000000 /* DENALI_PHY_146_DATA */ + 0x00000000 /* DENALI_PHY_147_DATA */ + 0x00000000 /* DENALI_PHY_148_DATA */ + 0x00000000 /* DENALI_PHY_149_DATA */ + 0x00000000 /* DENALI_PHY_150_DATA */ + 0x00000000 /* DENALI_PHY_151_DATA */ + 0x00000000 /* DENALI_PHY_152_DATA */ + 0x00000000 /* DENALI_PHY_153_DATA */ + 0x00000000 /* DENALI_PHY_154_DATA */ + 0x00000000 /* DENALI_PHY_155_DATA */ + 0x00000000 /* DENALI_PHY_156_DATA */ + 0x00000000 /* DENALI_PHY_157_DATA */ + 0x00000000 /* DENALI_PHY_158_DATA */ + 0x00000000 /* DENALI_PHY_159_DATA */ + 0x00000000 /* DENALI_PHY_160_DATA */ + 0x00200000 /* DENALI_PHY_161_DATA */ + 0x00000000 /* DENALI_PHY_162_DATA */ + 0x00000000 /* DENALI_PHY_163_DATA */ + 0x00000000 /* DENALI_PHY_164_DATA */ + 0x00000000 /* DENALI_PHY_165_DATA */ + 0x00000000 /* DENALI_PHY_166_DATA */ + 0x00000000 /* DENALI_PHY_167_DATA */ + 0x02800280 /* DENALI_PHY_168_DATA */ + 0x02800280 /* DENALI_PHY_169_DATA */ + 0x02800280 /* DENALI_PHY_170_DATA */ + 0x02800280 /* DENALI_PHY_171_DATA */ + 0x00000280 /* DENALI_PHY_172_DATA */ + 0x00000000 /* DENALI_PHY_173_DATA */ + 0x00000000 /* DENALI_PHY_174_DATA */ + 0x00000000 /* DENALI_PHY_175_DATA */ + 0x00000000 /* DENALI_PHY_176_DATA */ + 0x00000000 /* DENALI_PHY_177_DATA */ + 0x00800080 /* DENALI_PHY_178_DATA */ + 0x00800080 /* DENALI_PHY_179_DATA */ + 0x00800080 /* DENALI_PHY_180_DATA */ + 0x00800080 /* DENALI_PHY_181_DATA */ + 0x00800080 /* DENALI_PHY_182_DATA */ + 0x00800080 /* DENALI_PHY_183_DATA */ + 0x00800080 /* DENALI_PHY_184_DATA */ + 0x00800080 /* DENALI_PHY_185_DATA */ + 0x00800080 /* DENALI_PHY_186_DATA */ + 0x000100da /* DENALI_PHY_187_DATA */ + 0x01ff0010 /* DENALI_PHY_188_DATA */ + 0x00000000 /* DENALI_PHY_189_DATA */ + 0x00000000 /* DENALI_PHY_190_DATA */ + 0x00000002 /* DENALI_PHY_191_DATA */ + 0x51313152 /* DENALI_PHY_192_DATA */ + 0x80013130 /* DENALI_PHY_193_DATA */ + 0x02000080 /* DENALI_PHY_194_DATA */ + 0x00100001 /* DENALI_PHY_195_DATA */ + 0x0c064208 /* DENALI_PHY_196_DATA */ + 0x000f0c0f /* DENALI_PHY_197_DATA */ + 0x01000140 /* DENALI_PHY_198_DATA */ + 0x0000000c /* DENALI_PHY_199_DATA */ + 0x00000000 /* DENALI_PHY_200_DATA */ + 0x00000000 /* DENALI_PHY_201_DATA */ + 0x00000000 /* DENALI_PHY_202_DATA */ + 0x00000000 /* DENALI_PHY_203_DATA */ + 0x00000000 /* DENALI_PHY_204_DATA */ + 0x00000000 /* DENALI_PHY_205_DATA */ + 0x00000000 /* DENALI_PHY_206_DATA */ + 0x00000000 /* DENALI_PHY_207_DATA */ + 0x00000000 /* DENALI_PHY_208_DATA */ + 0x00000000 /* DENALI_PHY_209_DATA */ + 0x00000000 /* DENALI_PHY_210_DATA */ + 0x00000000 /* DENALI_PHY_211_DATA */ + 0x00000000 /* DENALI_PHY_212_DATA */ + 0x00000000 /* DENALI_PHY_213_DATA */ + 0x00000000 /* DENALI_PHY_214_DATA */ + 0x00000000 /* DENALI_PHY_215_DATA */ + 0x00000000 /* DENALI_PHY_216_DATA */ + 0x00000000 /* DENALI_PHY_217_DATA */ + 0x00000000 /* DENALI_PHY_218_DATA */ + 0x00000000 /* DENALI_PHY_219_DATA */ + 0x00000000 /* DENALI_PHY_220_DATA */ + 0x00000000 /* DENALI_PHY_221_DATA */ + 0x00000000 /* DENALI_PHY_222_DATA */ + 0x00000000 /* DENALI_PHY_223_DATA */ + 0x00000000 /* DENALI_PHY_224_DATA */ + 0x00000000 /* DENALI_PHY_225_DATA */ + 0x00000000 /* DENALI_PHY_226_DATA */ + 0x00000000 /* DENALI_PHY_227_DATA */ + 0x00000000 /* DENALI_PHY_228_DATA */ + 0x00000000 /* DENALI_PHY_229_DATA */ + 0x00000000 /* DENALI_PHY_230_DATA */ + 0x00000000 /* DENALI_PHY_231_DATA */ + 0x00000000 /* DENALI_PHY_232_DATA */ + 0x00000000 /* DENALI_PHY_233_DATA */ + 0x00000000 /* DENALI_PHY_234_DATA */ + 0x00000000 /* DENALI_PHY_235_DATA */ + 0x00000000 /* DENALI_PHY_236_DATA */ + 0x00000000 /* DENALI_PHY_237_DATA */ + 0x00000000 /* DENALI_PHY_238_DATA */ + 0x00000000 /* DENALI_PHY_239_DATA */ + 0x00000000 /* DENALI_PHY_240_DATA */ + 0x00000000 /* DENALI_PHY_241_DATA */ + 0x00000000 /* DENALI_PHY_242_DATA */ + 0x00000000 /* DENALI_PHY_243_DATA */ + 0x00000000 /* DENALI_PHY_244_DATA */ + 0x00000000 /* DENALI_PHY_245_DATA */ + 0x00000000 /* DENALI_PHY_246_DATA */ + 0x00000000 /* DENALI_PHY_247_DATA */ + 0x00000000 /* DENALI_PHY_248_DATA */ + 0x00000000 /* DENALI_PHY_249_DATA */ + 0x00000000 /* DENALI_PHY_250_DATA */ + 0x00000000 /* DENALI_PHY_251_DATA */ + 0x00000000 /* DENALI_PHY_252_DATA */ + 0x00000000 /* DENALI_PHY_253_DATA */ + 0x00000000 /* DENALI_PHY_254_DATA */ + 0x00000000 /* DENALI_PHY_255_DATA */ + 0x46052371 /* DENALI_PHY_256_DATA */ + 0x0004c008 /* DENALI_PHY_257_DATA */ + 0x000000da /* DENALI_PHY_258_DATA */ + 0x00000000 /* DENALI_PHY_259_DATA */ + 0x00000000 /* DENALI_PHY_260_DATA */ + 0x00010000 /* DENALI_PHY_261_DATA */ + 0x01DDDD90 /* DENALI_PHY_262_DATA */ + 0x01DDDD90 /* DENALI_PHY_263_DATA */ + 0x01030001 /* DENALI_PHY_264_DATA */ + 0x01000000 /* DENALI_PHY_265_DATA */ + 0x00c00000 /* DENALI_PHY_266_DATA */ + 0x00000007 /* DENALI_PHY_267_DATA */ + 0x00000000 /* DENALI_PHY_268_DATA */ + 0x00000000 /* DENALI_PHY_269_DATA */ + 0x04000408 /* DENALI_PHY_270_DATA */ + 0x00000408 /* DENALI_PHY_271_DATA */ + 0x00e4e400 /* DENALI_PHY_272_DATA */ + 0x00000000 /* DENALI_PHY_273_DATA */ + 0x00000000 /* DENALI_PHY_274_DATA */ + 0x00000000 /* DENALI_PHY_275_DATA */ + 0x00000000 /* DENALI_PHY_276_DATA */ + 0x00000000 /* DENALI_PHY_277_DATA */ + 0x00000000 /* DENALI_PHY_278_DATA */ + 0x00000000 /* DENALI_PHY_279_DATA */ + 0x00000000 /* DENALI_PHY_280_DATA */ + 0x00000000 /* DENALI_PHY_281_DATA */ + 0x00000000 /* DENALI_PHY_282_DATA */ + 0x00000000 /* DENALI_PHY_283_DATA */ + 0x00000000 /* DENALI_PHY_284_DATA */ + 0x00000000 /* DENALI_PHY_285_DATA */ + 0x00000000 /* DENALI_PHY_286_DATA */ + 0x00000000 /* DENALI_PHY_287_DATA */ + 0x00000000 /* DENALI_PHY_288_DATA */ + 0x00200000 /* DENALI_PHY_289_DATA */ + 0x00000000 /* DENALI_PHY_290_DATA */ + 0x00000000 /* DENALI_PHY_291_DATA */ + 0x00000000 /* DENALI_PHY_292_DATA */ + 0x00000000 /* DENALI_PHY_293_DATA */ + 0x00000000 /* DENALI_PHY_294_DATA */ + 0x00000000 /* DENALI_PHY_295_DATA */ + 0x02800280 /* DENALI_PHY_296_DATA */ + 0x02800280 /* DENALI_PHY_297_DATA */ + 0x02800280 /* DENALI_PHY_298_DATA */ + 0x02800280 /* DENALI_PHY_299_DATA */ + 0x00000280 /* DENALI_PHY_300_DATA */ + 0x00000000 /* DENALI_PHY_301_DATA */ + 0x00000000 /* DENALI_PHY_302_DATA */ + 0x00000000 /* DENALI_PHY_303_DATA */ + 0x00000000 /* DENALI_PHY_304_DATA */ + 0x00000000 /* DENALI_PHY_305_DATA */ + 0x00800080 /* DENALI_PHY_306_DATA */ + 0x00800080 /* DENALI_PHY_307_DATA */ + 0x00800080 /* DENALI_PHY_308_DATA */ + 0x00800080 /* DENALI_PHY_309_DATA */ + 0x00800080 /* DENALI_PHY_310_DATA */ + 0x00800080 /* DENALI_PHY_311_DATA */ + 0x00800080 /* DENALI_PHY_312_DATA */ + 0x00800080 /* DENALI_PHY_313_DATA */ + 0x00800080 /* DENALI_PHY_314_DATA */ + 0x000100da /* DENALI_PHY_315_DATA */ + 0x01ff0010 /* DENALI_PHY_316_DATA */ + 0x00000000 /* DENALI_PHY_317_DATA */ + 0x00000000 /* DENALI_PHY_318_DATA */ + 0x00000002 /* DENALI_PHY_319_DATA */ + 0x51313152 /* DENALI_PHY_320_DATA */ + 0x80013130 /* DENALI_PHY_321_DATA */ + 0x02000080 /* DENALI_PHY_322_DATA */ + 0x00100001 /* DENALI_PHY_323_DATA */ + 0x0c064208 /* DENALI_PHY_324_DATA */ + 0x000f0c0f /* DENALI_PHY_325_DATA */ + 0x01000140 /* DENALI_PHY_326_DATA */ + 0x0000000c /* DENALI_PHY_327_DATA */ + 0x00000000 /* DENALI_PHY_328_DATA */ + 0x00000000 /* DENALI_PHY_329_DATA */ + 0x00000000 /* DENALI_PHY_330_DATA */ + 0x00000000 /* DENALI_PHY_331_DATA */ + 0x00000000 /* DENALI_PHY_332_DATA */ + 0x00000000 /* DENALI_PHY_333_DATA */ + 0x00000000 /* DENALI_PHY_334_DATA */ + 0x00000000 /* DENALI_PHY_335_DATA */ + 0x00000000 /* DENALI_PHY_336_DATA */ + 0x00000000 /* DENALI_PHY_337_DATA */ + 0x00000000 /* DENALI_PHY_338_DATA */ + 0x00000000 /* DENALI_PHY_339_DATA */ + 0x00000000 /* DENALI_PHY_340_DATA */ + 0x00000000 /* DENALI_PHY_341_DATA */ + 0x00000000 /* DENALI_PHY_342_DATA */ + 0x00000000 /* DENALI_PHY_343_DATA */ + 0x00000000 /* DENALI_PHY_344_DATA */ + 0x00000000 /* DENALI_PHY_345_DATA */ + 0x00000000 /* DENALI_PHY_346_DATA */ + 0x00000000 /* DENALI_PHY_347_DATA */ + 0x00000000 /* DENALI_PHY_348_DATA */ + 0x00000000 /* DENALI_PHY_349_DATA */ + 0x00000000 /* DENALI_PHY_350_DATA */ + 0x00000000 /* DENALI_PHY_351_DATA */ + 0x00000000 /* DENALI_PHY_352_DATA */ + 0x00000000 /* DENALI_PHY_353_DATA */ + 0x00000000 /* DENALI_PHY_354_DATA */ + 0x00000000 /* DENALI_PHY_355_DATA */ + 0x00000000 /* DENALI_PHY_356_DATA */ + 0x00000000 /* DENALI_PHY_357_DATA */ + 0x00000000 /* DENALI_PHY_358_DATA */ + 0x00000000 /* DENALI_PHY_359_DATA */ + 0x00000000 /* DENALI_PHY_360_DATA */ + 0x00000000 /* DENALI_PHY_361_DATA */ + 0x00000000 /* DENALI_PHY_362_DATA */ + 0x00000000 /* DENALI_PHY_363_DATA */ + 0x00000000 /* DENALI_PHY_364_DATA */ + 0x00000000 /* DENALI_PHY_365_DATA */ + 0x00000000 /* DENALI_PHY_366_DATA */ + 0x00000000 /* DENALI_PHY_367_DATA */ + 0x00000000 /* DENALI_PHY_368_DATA */ + 0x00000000 /* DENALI_PHY_369_DATA */ + 0x00000000 /* DENALI_PHY_370_DATA */ + 0x00000000 /* DENALI_PHY_371_DATA */ + 0x00000000 /* DENALI_PHY_372_DATA */ + 0x00000000 /* DENALI_PHY_373_DATA */ + 0x00000000 /* DENALI_PHY_374_DATA */ + 0x00000000 /* DENALI_PHY_375_DATA */ + 0x00000000 /* DENALI_PHY_376_DATA */ + 0x00000000 /* DENALI_PHY_377_DATA */ + 0x00000000 /* DENALI_PHY_378_DATA */ + 0x00000000 /* DENALI_PHY_379_DATA */ + 0x00000000 /* DENALI_PHY_380_DATA */ + 0x00000000 /* DENALI_PHY_381_DATA */ + 0x00000000 /* DENALI_PHY_382_DATA */ + 0x00000000 /* DENALI_PHY_383_DATA */ + 0x37651240 /* DENALI_PHY_384_DATA */ + 0x0004c008 /* DENALI_PHY_385_DATA */ + 0x000000da /* DENALI_PHY_386_DATA */ + 0x00000000 /* DENALI_PHY_387_DATA */ + 0x00000000 /* DENALI_PHY_388_DATA */ + 0x00010000 /* DENALI_PHY_389_DATA */ + 0x01DDDD90 /* DENALI_PHY_390_DATA */ + 0x01DDDD90 /* DENALI_PHY_391_DATA */ + 0x01030001 /* DENALI_PHY_392_DATA */ + 0x01000000 /* DENALI_PHY_393_DATA */ + 0x00c00000 /* DENALI_PHY_394_DATA */ + 0x00000007 /* DENALI_PHY_395_DATA */ + 0x00000000 /* DENALI_PHY_396_DATA */ + 0x00000000 /* DENALI_PHY_397_DATA */ + 0x04000408 /* DENALI_PHY_398_DATA */ + 0x00000408 /* DENALI_PHY_399_DATA */ + 0x00e4e400 /* DENALI_PHY_400_DATA */ + 0x00000000 /* DENALI_PHY_401_DATA */ + 0x00000000 /* DENALI_PHY_402_DATA */ + 0x00000000 /* DENALI_PHY_403_DATA */ + 0x00000000 /* DENALI_PHY_404_DATA */ + 0x00000000 /* DENALI_PHY_405_DATA */ + 0x00000000 /* DENALI_PHY_406_DATA */ + 0x00000000 /* DENALI_PHY_407_DATA */ + 0x00000000 /* DENALI_PHY_408_DATA */ + 0x00000000 /* DENALI_PHY_409_DATA */ + 0x00000000 /* DENALI_PHY_410_DATA */ + 0x00000000 /* DENALI_PHY_411_DATA */ + 0x00000000 /* DENALI_PHY_412_DATA */ + 0x00000000 /* DENALI_PHY_413_DATA */ + 0x00000000 /* DENALI_PHY_414_DATA */ + 0x00000000 /* DENALI_PHY_415_DATA */ + 0x00000000 /* DENALI_PHY_416_DATA */ + 0x00200000 /* DENALI_PHY_417_DATA */ + 0x00000000 /* DENALI_PHY_418_DATA */ + 0x00000000 /* DENALI_PHY_419_DATA */ + 0x00000000 /* DENALI_PHY_420_DATA */ + 0x00000000 /* DENALI_PHY_421_DATA */ + 0x00000000 /* DENALI_PHY_422_DATA */ + 0x00000000 /* DENALI_PHY_423_DATA */ + 0x02800280 /* DENALI_PHY_424_DATA */ + 0x02800280 /* DENALI_PHY_425_DATA */ + 0x02800280 /* DENALI_PHY_426_DATA */ + 0x02800280 /* DENALI_PHY_427_DATA */ + 0x00000280 /* DENALI_PHY_428_DATA */ + 0x00000000 /* DENALI_PHY_429_DATA */ + 0x00000000 /* DENALI_PHY_430_DATA */ + 0x00000000 /* DENALI_PHY_431_DATA */ + 0x00000000 /* DENALI_PHY_432_DATA */ + 0x00000000 /* DENALI_PHY_433_DATA */ + 0x00800080 /* DENALI_PHY_434_DATA */ + 0x00800080 /* DENALI_PHY_435_DATA */ + 0x00800080 /* DENALI_PHY_436_DATA */ + 0x00800080 /* DENALI_PHY_437_DATA */ + 0x00800080 /* DENALI_PHY_438_DATA */ + 0x00800080 /* DENALI_PHY_439_DATA */ + 0x00800080 /* DENALI_PHY_440_DATA */ + 0x00800080 /* DENALI_PHY_441_DATA */ + 0x00800080 /* DENALI_PHY_442_DATA */ + 0x000100da /* DENALI_PHY_443_DATA */ + 0x01ff0010 /* DENALI_PHY_444_DATA */ + 0x00000000 /* DENALI_PHY_445_DATA */ + 0x00000000 /* DENALI_PHY_446_DATA */ + 0x00000002 /* DENALI_PHY_447_DATA */ + 0x51313152 /* DENALI_PHY_448_DATA */ + 0x80013130 /* DENALI_PHY_449_DATA */ + 0x02000080 /* DENALI_PHY_450_DATA */ + 0x00100001 /* DENALI_PHY_451_DATA */ + 0x0c064208 /* DENALI_PHY_452_DATA */ + 0x000f0c0f /* DENALI_PHY_453_DATA */ + 0x01000140 /* DENALI_PHY_454_DATA */ + 0x0000000c /* DENALI_PHY_455_DATA */ + 0x00000000 /* DENALI_PHY_456_DATA */ + 0x00000000 /* DENALI_PHY_457_DATA */ + 0x00000000 /* DENALI_PHY_458_DATA */ + 0x00000000 /* DENALI_PHY_459_DATA */ + 0x00000000 /* DENALI_PHY_460_DATA */ + 0x00000000 /* DENALI_PHY_461_DATA */ + 0x00000000 /* DENALI_PHY_462_DATA */ + 0x00000000 /* DENALI_PHY_463_DATA */ + 0x00000000 /* DENALI_PHY_464_DATA */ + 0x00000000 /* DENALI_PHY_465_DATA */ + 0x00000000 /* DENALI_PHY_466_DATA */ + 0x00000000 /* DENALI_PHY_467_DATA */ + 0x00000000 /* DENALI_PHY_468_DATA */ + 0x00000000 /* DENALI_PHY_469_DATA */ + 0x00000000 /* DENALI_PHY_470_DATA */ + 0x00000000 /* DENALI_PHY_471_DATA */ + 0x00000000 /* DENALI_PHY_472_DATA */ + 0x00000000 /* DENALI_PHY_473_DATA */ + 0x00000000 /* DENALI_PHY_474_DATA */ + 0x00000000 /* DENALI_PHY_475_DATA */ + 0x00000000 /* DENALI_PHY_476_DATA */ + 0x00000000 /* DENALI_PHY_477_DATA */ + 0x00000000 /* DENALI_PHY_478_DATA */ + 0x00000000 /* DENALI_PHY_479_DATA */ + 0x00000000 /* DENALI_PHY_480_DATA */ + 0x00000000 /* DENALI_PHY_481_DATA */ + 0x00000000 /* DENALI_PHY_482_DATA */ + 0x00000000 /* DENALI_PHY_483_DATA */ + 0x00000000 /* DENALI_PHY_484_DATA */ + 0x00000000 /* DENALI_PHY_485_DATA */ + 0x00000000 /* DENALI_PHY_486_DATA */ + 0x00000000 /* DENALI_PHY_487_DATA */ + 0x00000000 /* DENALI_PHY_488_DATA */ + 0x00000000 /* DENALI_PHY_489_DATA */ + 0x00000000 /* DENALI_PHY_490_DATA */ + 0x00000000 /* DENALI_PHY_491_DATA */ + 0x00000000 /* DENALI_PHY_492_DATA */ + 0x00000000 /* DENALI_PHY_493_DATA */ + 0x00000000 /* DENALI_PHY_494_DATA */ + 0x00000000 /* DENALI_PHY_495_DATA */ + 0x00000000 /* DENALI_PHY_496_DATA */ + 0x00000000 /* DENALI_PHY_497_DATA */ + 0x00000000 /* DENALI_PHY_498_DATA */ + 0x00000000 /* DENALI_PHY_499_DATA */ + 0x00000000 /* DENALI_PHY_500_DATA */ + 0x00000000 /* DENALI_PHY_501_DATA */ + 0x00000000 /* DENALI_PHY_502_DATA */ + 0x00000000 /* DENALI_PHY_503_DATA */ + 0x00000000 /* DENALI_PHY_504_DATA */ + 0x00000000 /* DENALI_PHY_505_DATA */ + 0x00000000 /* DENALI_PHY_506_DATA */ + 0x00000000 /* DENALI_PHY_507_DATA */ + 0x00000000 /* DENALI_PHY_508_DATA */ + 0x00000000 /* DENALI_PHY_509_DATA */ + 0x00000000 /* DENALI_PHY_510_DATA */ + 0x00000000 /* DENALI_PHY_511_DATA */ + 0x34216750 /* DENALI_PHY_512_DATA */ + 0x0004c008 /* DENALI_PHY_513_DATA */ + 0x000000da /* DENALI_PHY_514_DATA */ + 0x00000000 /* DENALI_PHY_515_DATA */ + 0x00000000 /* DENALI_PHY_516_DATA */ + 0x00010000 /* DENALI_PHY_517_DATA */ + 0x01DDDD90 /* DENALI_PHY_518_DATA */ + 0x01DDDD90 /* DENALI_PHY_519_DATA */ + 0x01030001 /* DENALI_PHY_520_DATA */ + 0x01000000 /* DENALI_PHY_521_DATA */ + 0x00c00000 /* DENALI_PHY_522_DATA */ + 0x00000007 /* DENALI_PHY_523_DATA */ + 0x00000000 /* DENALI_PHY_524_DATA */ + 0x00000000 /* DENALI_PHY_525_DATA */ + 0x04000408 /* DENALI_PHY_526_DATA */ + 0x00000408 /* DENALI_PHY_527_DATA */ + 0x00e4e400 /* DENALI_PHY_528_DATA */ + 0x00000000 /* DENALI_PHY_529_DATA */ + 0x00000000 /* DENALI_PHY_530_DATA */ + 0x00000000 /* DENALI_PHY_531_DATA */ + 0x00000000 /* DENALI_PHY_532_DATA */ + 0x00000000 /* DENALI_PHY_533_DATA */ + 0x00000000 /* DENALI_PHY_534_DATA */ + 0x00000000 /* DENALI_PHY_535_DATA */ + 0x00000000 /* DENALI_PHY_536_DATA */ + 0x00000000 /* DENALI_PHY_537_DATA */ + 0x00000000 /* DENALI_PHY_538_DATA */ + 0x00000000 /* DENALI_PHY_539_DATA */ + 0x00000000 /* DENALI_PHY_540_DATA */ + 0x00000000 /* DENALI_PHY_541_DATA */ + 0x00000000 /* DENALI_PHY_542_DATA */ + 0x00000000 /* DENALI_PHY_543_DATA */ + 0x00000000 /* DENALI_PHY_544_DATA */ + 0x00200000 /* DENALI_PHY_545_DATA */ + 0x00000000 /* DENALI_PHY_546_DATA */ + 0x00000000 /* DENALI_PHY_547_DATA */ + 0x00000000 /* DENALI_PHY_548_DATA */ + 0x00000000 /* DENALI_PHY_549_DATA */ + 0x00000000 /* DENALI_PHY_550_DATA */ + 0x00000000 /* DENALI_PHY_551_DATA */ + 0x02800280 /* DENALI_PHY_552_DATA */ + 0x02800280 /* DENALI_PHY_553_DATA */ + 0x02800280 /* DENALI_PHY_554_DATA */ + 0x02800280 /* DENALI_PHY_555_DATA */ + 0x00000280 /* DENALI_PHY_556_DATA */ + 0x00000000 /* DENALI_PHY_557_DATA */ + 0x00000000 /* DENALI_PHY_558_DATA */ + 0x00000000 /* DENALI_PHY_559_DATA */ + 0x00000000 /* DENALI_PHY_560_DATA */ + 0x00000000 /* DENALI_PHY_561_DATA */ + 0x00800080 /* DENALI_PHY_562_DATA */ + 0x00800080 /* DENALI_PHY_563_DATA */ + 0x00800080 /* DENALI_PHY_564_DATA */ + 0x00800080 /* DENALI_PHY_565_DATA */ + 0x00800080 /* DENALI_PHY_566_DATA */ + 0x00800080 /* DENALI_PHY_567_DATA */ + 0x00800080 /* DENALI_PHY_568_DATA */ + 0x00800080 /* DENALI_PHY_569_DATA */ + 0x00800080 /* DENALI_PHY_570_DATA */ + 0x000100da /* DENALI_PHY_571_DATA */ + 0x01ff0010 /* DENALI_PHY_572_DATA */ + 0x00000000 /* DENALI_PHY_573_DATA */ + 0x00000000 /* DENALI_PHY_574_DATA */ + 0x00000002 /* DENALI_PHY_575_DATA */ + 0x51313152 /* DENALI_PHY_576_DATA */ + 0x80013130 /* DENALI_PHY_577_DATA */ + 0x02000080 /* DENALI_PHY_578_DATA */ + 0x00100001 /* DENALI_PHY_579_DATA */ + 0x0c064208 /* DENALI_PHY_580_DATA */ + 0x000f0c0f /* DENALI_PHY_581_DATA */ + 0x01000140 /* DENALI_PHY_582_DATA */ + 0x0000000c /* DENALI_PHY_583_DATA */ + 0x00000000 /* DENALI_PHY_584_DATA */ + 0x00000000 /* DENALI_PHY_585_DATA */ + 0x00000000 /* DENALI_PHY_586_DATA */ + 0x00000000 /* DENALI_PHY_587_DATA */ + 0x00000000 /* DENALI_PHY_588_DATA */ + 0x00000000 /* DENALI_PHY_589_DATA */ + 0x00000000 /* DENALI_PHY_590_DATA */ + 0x00000000 /* DENALI_PHY_591_DATA */ + 0x00000000 /* DENALI_PHY_592_DATA */ + 0x00000000 /* DENALI_PHY_593_DATA */ + 0x00000000 /* DENALI_PHY_594_DATA */ + 0x00000000 /* DENALI_PHY_595_DATA */ + 0x00000000 /* DENALI_PHY_596_DATA */ + 0x00000000 /* DENALI_PHY_597_DATA */ + 0x00000000 /* DENALI_PHY_598_DATA */ + 0x00000000 /* DENALI_PHY_599_DATA */ + 0x00000000 /* DENALI_PHY_600_DATA */ + 0x00000000 /* DENALI_PHY_601_DATA */ + 0x00000000 /* DENALI_PHY_602_DATA */ + 0x00000000 /* DENALI_PHY_603_DATA */ + 0x00000000 /* DENALI_PHY_604_DATA */ + 0x00000000 /* DENALI_PHY_605_DATA */ + 0x00000000 /* DENALI_PHY_606_DATA */ + 0x00000000 /* DENALI_PHY_607_DATA */ + 0x00000000 /* DENALI_PHY_608_DATA */ + 0x00000000 /* DENALI_PHY_609_DATA */ + 0x00000000 /* DENALI_PHY_610_DATA */ + 0x00000000 /* DENALI_PHY_611_DATA */ + 0x00000000 /* DENALI_PHY_612_DATA */ + 0x00000000 /* DENALI_PHY_613_DATA */ + 0x00000000 /* DENALI_PHY_614_DATA */ + 0x00000000 /* DENALI_PHY_615_DATA */ + 0x00000000 /* DENALI_PHY_616_DATA */ + 0x00000000 /* DENALI_PHY_617_DATA */ + 0x00000000 /* DENALI_PHY_618_DATA */ + 0x00000000 /* DENALI_PHY_619_DATA */ + 0x00000000 /* DENALI_PHY_620_DATA */ + 0x00000000 /* DENALI_PHY_621_DATA */ + 0x00000000 /* DENALI_PHY_622_DATA */ + 0x00000000 /* DENALI_PHY_623_DATA */ + 0x00000000 /* DENALI_PHY_624_DATA */ + 0x00000000 /* DENALI_PHY_625_DATA */ + 0x00000000 /* DENALI_PHY_626_DATA */ + 0x00000000 /* DENALI_PHY_627_DATA */ + 0x00000000 /* DENALI_PHY_628_DATA */ + 0x00000000 /* DENALI_PHY_629_DATA */ + 0x00000000 /* DENALI_PHY_630_DATA */ + 0x00000000 /* DENALI_PHY_631_DATA */ + 0x00000000 /* DENALI_PHY_632_DATA */ + 0x00000000 /* DENALI_PHY_633_DATA */ + 0x00000000 /* DENALI_PHY_634_DATA */ + 0x00000000 /* DENALI_PHY_635_DATA */ + 0x00000000 /* DENALI_PHY_636_DATA */ + 0x00000000 /* DENALI_PHY_637_DATA */ + 0x00000000 /* DENALI_PHY_638_DATA */ + 0x00000000 /* DENALI_PHY_639_DATA */ + 0x35176402 /* DENALI_PHY_640_DATA */ + 0x0004c008 /* DENALI_PHY_641_DATA */ + 0x000000da /* DENALI_PHY_642_DATA */ + 0x00000000 /* DENALI_PHY_643_DATA */ + 0x00000000 /* DENALI_PHY_644_DATA */ + 0x00010000 /* DENALI_PHY_645_DATA */ + 0x01DDDD90 /* DENALI_PHY_646_DATA */ + 0x01DDDD90 /* DENALI_PHY_647_DATA */ + 0x01030001 /* DENALI_PHY_648_DATA */ + 0x01000000 /* DENALI_PHY_649_DATA */ + 0x00c00000 /* DENALI_PHY_650_DATA */ + 0x00000007 /* DENALI_PHY_651_DATA */ + 0x00000000 /* DENALI_PHY_652_DATA */ + 0x00000000 /* DENALI_PHY_653_DATA */ + 0x04000408 /* DENALI_PHY_654_DATA */ + 0x00000408 /* DENALI_PHY_655_DATA */ + 0x00e4e400 /* DENALI_PHY_656_DATA */ + 0x00000000 /* DENALI_PHY_657_DATA */ + 0x00000000 /* DENALI_PHY_658_DATA */ + 0x00000000 /* DENALI_PHY_659_DATA */ + 0x00000000 /* DENALI_PHY_660_DATA */ + 0x00000000 /* DENALI_PHY_661_DATA */ + 0x00000000 /* DENALI_PHY_662_DATA */ + 0x00000000 /* DENALI_PHY_663_DATA */ + 0x00000000 /* DENALI_PHY_664_DATA */ + 0x00000000 /* DENALI_PHY_665_DATA */ + 0x00000000 /* DENALI_PHY_666_DATA */ + 0x00000000 /* DENALI_PHY_667_DATA */ + 0x00000000 /* DENALI_PHY_668_DATA */ + 0x00000000 /* DENALI_PHY_669_DATA */ + 0x00000000 /* DENALI_PHY_670_DATA */ + 0x00000000 /* DENALI_PHY_671_DATA */ + 0x00000000 /* DENALI_PHY_672_DATA */ + 0x00200000 /* DENALI_PHY_673_DATA */ + 0x00000000 /* DENALI_PHY_674_DATA */ + 0x00000000 /* DENALI_PHY_675_DATA */ + 0x00000000 /* DENALI_PHY_676_DATA */ + 0x00000000 /* DENALI_PHY_677_DATA */ + 0x00000000 /* DENALI_PHY_678_DATA */ + 0x00000000 /* DENALI_PHY_679_DATA */ + 0x02800280 /* DENALI_PHY_680_DATA */ + 0x02800280 /* DENALI_PHY_681_DATA */ + 0x02800280 /* DENALI_PHY_682_DATA */ + 0x02800280 /* DENALI_PHY_683_DATA */ + 0x00000280 /* DENALI_PHY_684_DATA */ + 0x00000000 /* DENALI_PHY_685_DATA */ + 0x00000000 /* DENALI_PHY_686_DATA */ + 0x00000000 /* DENALI_PHY_687_DATA */ + 0x00000000 /* DENALI_PHY_688_DATA */ + 0x00000000 /* DENALI_PHY_689_DATA */ + 0x00800080 /* DENALI_PHY_690_DATA */ + 0x00800080 /* DENALI_PHY_691_DATA */ + 0x00800080 /* DENALI_PHY_692_DATA */ + 0x00800080 /* DENALI_PHY_693_DATA */ + 0x00800080 /* DENALI_PHY_694_DATA */ + 0x00800080 /* DENALI_PHY_695_DATA */ + 0x00800080 /* DENALI_PHY_696_DATA */ + 0x00800080 /* DENALI_PHY_697_DATA */ + 0x00800080 /* DENALI_PHY_698_DATA */ + 0x000100da /* DENALI_PHY_699_DATA */ + 0x01ff0010 /* DENALI_PHY_700_DATA */ + 0x00000000 /* DENALI_PHY_701_DATA */ + 0x00000000 /* DENALI_PHY_702_DATA */ + 0x00000002 /* DENALI_PHY_703_DATA */ + 0x51313152 /* DENALI_PHY_704_DATA */ + 0x80013130 /* DENALI_PHY_705_DATA */ + 0x02000080 /* DENALI_PHY_706_DATA */ + 0x00100001 /* DENALI_PHY_707_DATA */ + 0x0c064208 /* DENALI_PHY_708_DATA */ + 0x000f0c0f /* DENALI_PHY_709_DATA */ + 0x01000140 /* DENALI_PHY_710_DATA */ + 0x0000000c /* DENALI_PHY_711_DATA */ + 0x00000000 /* DENALI_PHY_712_DATA */ + 0x00000000 /* DENALI_PHY_713_DATA */ + 0x00000000 /* DENALI_PHY_714_DATA */ + 0x00000000 /* DENALI_PHY_715_DATA */ + 0x00000000 /* DENALI_PHY_716_DATA */ + 0x00000000 /* DENALI_PHY_717_DATA */ + 0x00000000 /* DENALI_PHY_718_DATA */ + 0x00000000 /* DENALI_PHY_719_DATA */ + 0x00000000 /* DENALI_PHY_720_DATA */ + 0x00000000 /* DENALI_PHY_721_DATA */ + 0x00000000 /* DENALI_PHY_722_DATA */ + 0x00000000 /* DENALI_PHY_723_DATA */ + 0x00000000 /* DENALI_PHY_724_DATA */ + 0x00000000 /* DENALI_PHY_725_DATA */ + 0x00000000 /* DENALI_PHY_726_DATA */ + 0x00000000 /* DENALI_PHY_727_DATA */ + 0x00000000 /* DENALI_PHY_728_DATA */ + 0x00000000 /* DENALI_PHY_729_DATA */ + 0x00000000 /* DENALI_PHY_730_DATA */ + 0x00000000 /* DENALI_PHY_731_DATA */ + 0x00000000 /* DENALI_PHY_732_DATA */ + 0x00000000 /* DENALI_PHY_733_DATA */ + 0x00000000 /* DENALI_PHY_734_DATA */ + 0x00000000 /* DENALI_PHY_735_DATA */ + 0x00000000 /* DENALI_PHY_736_DATA */ + 0x00000000 /* DENALI_PHY_737_DATA */ + 0x00000000 /* DENALI_PHY_738_DATA */ + 0x00000000 /* DENALI_PHY_739_DATA */ + 0x00000000 /* DENALI_PHY_740_DATA */ + 0x00000000 /* DENALI_PHY_741_DATA */ + 0x00000000 /* DENALI_PHY_742_DATA */ + 0x00000000 /* DENALI_PHY_743_DATA */ + 0x00000000 /* DENALI_PHY_744_DATA */ + 0x00000000 /* DENALI_PHY_745_DATA */ + 0x00000000 /* DENALI_PHY_746_DATA */ + 0x00000000 /* DENALI_PHY_747_DATA */ + 0x00000000 /* DENALI_PHY_748_DATA */ + 0x00000000 /* DENALI_PHY_749_DATA */ + 0x00000000 /* DENALI_PHY_750_DATA */ + 0x00000000 /* DENALI_PHY_751_DATA */ + 0x00000000 /* DENALI_PHY_752_DATA */ + 0x00000000 /* DENALI_PHY_753_DATA */ + 0x00000000 /* DENALI_PHY_754_DATA */ + 0x00000000 /* DENALI_PHY_755_DATA */ + 0x00000000 /* DENALI_PHY_756_DATA */ + 0x00000000 /* DENALI_PHY_757_DATA */ + 0x00000000 /* DENALI_PHY_758_DATA */ + 0x00000000 /* DENALI_PHY_759_DATA */ + 0x00000000 /* DENALI_PHY_760_DATA */ + 0x00000000 /* DENALI_PHY_761_DATA */ + 0x00000000 /* DENALI_PHY_762_DATA */ + 0x00000000 /* DENALI_PHY_763_DATA */ + 0x00000000 /* DENALI_PHY_764_DATA */ + 0x00000000 /* DENALI_PHY_765_DATA */ + 0x00000000 /* DENALI_PHY_766_DATA */ + 0x00000000 /* DENALI_PHY_767_DATA */ + 0x10526347 /* DENALI_PHY_768_DATA */ + 0x0004c008 /* DENALI_PHY_769_DATA */ + 0x000000da /* DENALI_PHY_770_DATA */ + 0x00000000 /* DENALI_PHY_771_DATA */ + 0x00000000 /* DENALI_PHY_772_DATA */ + 0x00010000 /* DENALI_PHY_773_DATA */ + 0x01DDDD90 /* DENALI_PHY_774_DATA */ + 0x01DDDD90 /* DENALI_PHY_775_DATA */ + 0x01030001 /* DENALI_PHY_776_DATA */ + 0x01000000 /* DENALI_PHY_777_DATA */ + 0x00c00000 /* DENALI_PHY_778_DATA */ + 0x00000007 /* DENALI_PHY_779_DATA */ + 0x00000000 /* DENALI_PHY_780_DATA */ + 0x00000000 /* DENALI_PHY_781_DATA */ + 0x04000408 /* DENALI_PHY_782_DATA */ + 0x00000408 /* DENALI_PHY_783_DATA */ + 0x00e4e400 /* DENALI_PHY_784_DATA */ + 0x00000000 /* DENALI_PHY_785_DATA */ + 0x00000000 /* DENALI_PHY_786_DATA */ + 0x00000000 /* DENALI_PHY_787_DATA */ + 0x00000000 /* DENALI_PHY_788_DATA */ + 0x00000000 /* DENALI_PHY_789_DATA */ + 0x00000000 /* DENALI_PHY_790_DATA */ + 0x00000000 /* DENALI_PHY_791_DATA */ + 0x00000000 /* DENALI_PHY_792_DATA */ + 0x00000000 /* DENALI_PHY_793_DATA */ + 0x00000000 /* DENALI_PHY_794_DATA */ + 0x00000000 /* DENALI_PHY_795_DATA */ + 0x00000000 /* DENALI_PHY_796_DATA */ + 0x00000000 /* DENALI_PHY_797_DATA */ + 0x00000000 /* DENALI_PHY_798_DATA */ + 0x00000000 /* DENALI_PHY_799_DATA */ + 0x00000000 /* DENALI_PHY_800_DATA */ + 0x00200000 /* DENALI_PHY_801_DATA */ + 0x00000000 /* DENALI_PHY_802_DATA */ + 0x00000000 /* DENALI_PHY_803_DATA */ + 0x00000000 /* DENALI_PHY_804_DATA */ + 0x00000000 /* DENALI_PHY_805_DATA */ + 0x00000000 /* DENALI_PHY_806_DATA */ + 0x00000000 /* DENALI_PHY_807_DATA */ + 0x02800280 /* DENALI_PHY_808_DATA */ + 0x02800280 /* DENALI_PHY_809_DATA */ + 0x02800280 /* DENALI_PHY_810_DATA */ + 0x02800280 /* DENALI_PHY_811_DATA */ + 0x00000280 /* DENALI_PHY_812_DATA */ + 0x00000000 /* DENALI_PHY_813_DATA */ + 0x00000000 /* DENALI_PHY_814_DATA */ + 0x00000000 /* DENALI_PHY_815_DATA */ + 0x00000000 /* DENALI_PHY_816_DATA */ + 0x00000000 /* DENALI_PHY_817_DATA */ + 0x00800080 /* DENALI_PHY_818_DATA */ + 0x00800080 /* DENALI_PHY_819_DATA */ + 0x00800080 /* DENALI_PHY_820_DATA */ + 0x00800080 /* DENALI_PHY_821_DATA */ + 0x00800080 /* DENALI_PHY_822_DATA */ + 0x00800080 /* DENALI_PHY_823_DATA */ + 0x00800080 /* DENALI_PHY_824_DATA */ + 0x00800080 /* DENALI_PHY_825_DATA */ + 0x00800080 /* DENALI_PHY_826_DATA */ + 0x000100da /* DENALI_PHY_827_DATA */ + 0x01ff0010 /* DENALI_PHY_828_DATA */ + 0x00000000 /* DENALI_PHY_829_DATA */ + 0x00000000 /* DENALI_PHY_830_DATA */ + 0x00000002 /* DENALI_PHY_831_DATA */ + 0x51313152 /* DENALI_PHY_832_DATA */ + 0x80013130 /* DENALI_PHY_833_DATA */ + 0x02000080 /* DENALI_PHY_834_DATA */ + 0x00100001 /* DENALI_PHY_835_DATA */ + 0x0c064208 /* DENALI_PHY_836_DATA */ + 0x000f0c0f /* DENALI_PHY_837_DATA */ + 0x01000140 /* DENALI_PHY_838_DATA */ + 0x0000000c /* DENALI_PHY_839_DATA */ + 0x00000000 /* DENALI_PHY_840_DATA */ + 0x00000000 /* DENALI_PHY_841_DATA */ + 0x00000000 /* DENALI_PHY_842_DATA */ + 0x00000000 /* DENALI_PHY_843_DATA */ + 0x00000000 /* DENALI_PHY_844_DATA */ + 0x00000000 /* DENALI_PHY_845_DATA */ + 0x00000000 /* DENALI_PHY_846_DATA */ + 0x00000000 /* DENALI_PHY_847_DATA */ + 0x00000000 /* DENALI_PHY_848_DATA */ + 0x00000000 /* DENALI_PHY_849_DATA */ + 0x00000000 /* DENALI_PHY_850_DATA */ + 0x00000000 /* DENALI_PHY_851_DATA */ + 0x00000000 /* DENALI_PHY_852_DATA */ + 0x00000000 /* DENALI_PHY_853_DATA */ + 0x00000000 /* DENALI_PHY_854_DATA */ + 0x00000000 /* DENALI_PHY_855_DATA */ + 0x00000000 /* DENALI_PHY_856_DATA */ + 0x00000000 /* DENALI_PHY_857_DATA */ + 0x00000000 /* DENALI_PHY_858_DATA */ + 0x00000000 /* DENALI_PHY_859_DATA */ + 0x00000000 /* DENALI_PHY_860_DATA */ + 0x00000000 /* DENALI_PHY_861_DATA */ + 0x00000000 /* DENALI_PHY_862_DATA */ + 0x00000000 /* DENALI_PHY_863_DATA */ + 0x00000000 /* DENALI_PHY_864_DATA */ + 0x00000000 /* DENALI_PHY_865_DATA */ + 0x00000000 /* DENALI_PHY_866_DATA */ + 0x00000000 /* DENALI_PHY_867_DATA */ + 0x00000000 /* DENALI_PHY_868_DATA */ + 0x00000000 /* DENALI_PHY_869_DATA */ + 0x00000000 /* DENALI_PHY_870_DATA */ + 0x00000000 /* DENALI_PHY_871_DATA */ + 0x00000000 /* DENALI_PHY_872_DATA */ + 0x00000000 /* DENALI_PHY_873_DATA */ + 0x00000000 /* DENALI_PHY_874_DATA */ + 0x00000000 /* DENALI_PHY_875_DATA */ + 0x00000000 /* DENALI_PHY_876_DATA */ + 0x00000000 /* DENALI_PHY_877_DATA */ + 0x00000000 /* DENALI_PHY_878_DATA */ + 0x00000000 /* DENALI_PHY_879_DATA */ + 0x00000000 /* DENALI_PHY_880_DATA */ + 0x00000000 /* DENALI_PHY_881_DATA */ + 0x00000000 /* DENALI_PHY_882_DATA */ + 0x00000000 /* DENALI_PHY_883_DATA */ + 0x00000000 /* DENALI_PHY_884_DATA */ + 0x00000000 /* DENALI_PHY_885_DATA */ + 0x00000000 /* DENALI_PHY_886_DATA */ + 0x00000000 /* DENALI_PHY_887_DATA */ + 0x00000000 /* DENALI_PHY_888_DATA */ + 0x00000000 /* DENALI_PHY_889_DATA */ + 0x00000000 /* DENALI_PHY_890_DATA */ + 0x00000000 /* DENALI_PHY_891_DATA */ + 0x00000000 /* DENALI_PHY_892_DATA */ + 0x00000000 /* DENALI_PHY_893_DATA */ + 0x00000000 /* DENALI_PHY_894_DATA */ + 0x00000000 /* DENALI_PHY_895_DATA */ + 0x41753260 /* DENALI_PHY_896_DATA */ + 0x0004c008 /* DENALI_PHY_897_DATA */ + 0x000000da /* DENALI_PHY_898_DATA */ + 0x00000000 /* DENALI_PHY_899_DATA */ + 0x00000000 /* DENALI_PHY_900_DATA */ + 0x00010000 /* DENALI_PHY_901_DATA */ + 0x01DDDD90 /* DENALI_PHY_902_DATA */ + 0x01DDDD90 /* DENALI_PHY_903_DATA */ + 0x01030001 /* DENALI_PHY_904_DATA */ + 0x01000000 /* DENALI_PHY_905_DATA */ + 0x00c00000 /* DENALI_PHY_906_DATA */ + 0x00000007 /* DENALI_PHY_907_DATA */ + 0x00000000 /* DENALI_PHY_908_DATA */ + 0x00000000 /* DENALI_PHY_909_DATA */ + 0x04000408 /* DENALI_PHY_910_DATA */ + 0x00000408 /* DENALI_PHY_911_DATA */ + 0x00e4e400 /* DENALI_PHY_912_DATA */ + 0x00000000 /* DENALI_PHY_913_DATA */ + 0x00000000 /* DENALI_PHY_914_DATA */ + 0x00000000 /* DENALI_PHY_915_DATA */ + 0x00000000 /* DENALI_PHY_916_DATA */ + 0x00000000 /* DENALI_PHY_917_DATA */ + 0x00000000 /* DENALI_PHY_918_DATA */ + 0x00000000 /* DENALI_PHY_919_DATA */ + 0x00000000 /* DENALI_PHY_920_DATA */ + 0x00000000 /* DENALI_PHY_921_DATA */ + 0x00000000 /* DENALI_PHY_922_DATA */ + 0x00000000 /* DENALI_PHY_923_DATA */ + 0x00000000 /* DENALI_PHY_924_DATA */ + 0x00000000 /* DENALI_PHY_925_DATA */ + 0x00000000 /* DENALI_PHY_926_DATA */ + 0x00000000 /* DENALI_PHY_927_DATA */ + 0x00000000 /* DENALI_PHY_928_DATA */ + 0x00200000 /* DENALI_PHY_929_DATA */ + 0x00000000 /* DENALI_PHY_930_DATA */ + 0x00000000 /* DENALI_PHY_931_DATA */ + 0x00000000 /* DENALI_PHY_932_DATA */ + 0x00000000 /* DENALI_PHY_933_DATA */ + 0x00000000 /* DENALI_PHY_934_DATA */ + 0x00000000 /* DENALI_PHY_935_DATA */ + 0x02800280 /* DENALI_PHY_936_DATA */ + 0x02800280 /* DENALI_PHY_937_DATA */ + 0x02800280 /* DENALI_PHY_938_DATA */ + 0x02800280 /* DENALI_PHY_939_DATA */ + 0x00000280 /* DENALI_PHY_940_DATA */ + 0x00000000 /* DENALI_PHY_941_DATA */ + 0x00000000 /* DENALI_PHY_942_DATA */ + 0x00000000 /* DENALI_PHY_943_DATA */ + 0x00000000 /* DENALI_PHY_944_DATA */ + 0x00000000 /* DENALI_PHY_945_DATA */ + 0x00800080 /* DENALI_PHY_946_DATA */ + 0x00800080 /* DENALI_PHY_947_DATA */ + 0x00800080 /* DENALI_PHY_948_DATA */ + 0x00800080 /* DENALI_PHY_949_DATA */ + 0x00800080 /* DENALI_PHY_950_DATA */ + 0x00800080 /* DENALI_PHY_951_DATA */ + 0x00800080 /* DENALI_PHY_952_DATA */ + 0x00800080 /* DENALI_PHY_953_DATA */ + 0x00800080 /* DENALI_PHY_954_DATA */ + 0x000100da /* DENALI_PHY_955_DATA */ + 0x01ff0010 /* DENALI_PHY_956_DATA */ + 0x00000000 /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + 0x00000002 /* DENALI_PHY_959_DATA */ + 0x51313152 /* DENALI_PHY_960_DATA */ + 0x80013130 /* DENALI_PHY_961_DATA */ + 0x02000080 /* DENALI_PHY_962_DATA */ + 0x00100001 /* DENALI_PHY_963_DATA */ + 0x0c064208 /* DENALI_PHY_964_DATA */ + 0x000f0c0f /* DENALI_PHY_965_DATA */ + 0x01000140 /* DENALI_PHY_966_DATA */ + 0x0000000c /* DENALI_PHY_967_DATA */ + 0x00000000 /* DENALI_PHY_968_DATA */ + 0x00000000 /* DENALI_PHY_969_DATA */ + 0x00000000 /* DENALI_PHY_970_DATA */ + 0x00000000 /* DENALI_PHY_971_DATA */ + 0x00000000 /* DENALI_PHY_972_DATA */ + 0x00000000 /* DENALI_PHY_973_DATA */ + 0x00000000 /* DENALI_PHY_974_DATA */ + 0x00000000 /* DENALI_PHY_975_DATA */ + 0x00000000 /* DENALI_PHY_976_DATA */ + 0x00000000 /* DENALI_PHY_977_DATA */ + 0x00000000 /* DENALI_PHY_978_DATA */ + 0x00000000 /* DENALI_PHY_979_DATA */ + 0x00000000 /* DENALI_PHY_980_DATA */ + 0x00000000 /* DENALI_PHY_981_DATA */ + 0x00000000 /* DENALI_PHY_982_DATA */ + 0x00000000 /* DENALI_PHY_983_DATA */ + 0x00000000 /* DENALI_PHY_984_DATA */ + 0x00000000 /* DENALI_PHY_985_DATA */ + 0x00000000 /* DENALI_PHY_986_DATA */ + 0x00000000 /* DENALI_PHY_987_DATA */ + 0x00000000 /* DENALI_PHY_988_DATA */ + 0x00000000 /* DENALI_PHY_989_DATA */ + 0x00000000 /* DENALI_PHY_990_DATA */ + 0x00000000 /* DENALI_PHY_991_DATA */ + 0x00000000 /* DENALI_PHY_992_DATA */ + 0x00000000 /* DENALI_PHY_993_DATA */ + 0x00000000 /* DENALI_PHY_994_DATA */ + 0x00000000 /* DENALI_PHY_995_DATA */ + 0x00000000 /* DENALI_PHY_996_DATA */ + 0x00000000 /* DENALI_PHY_997_DATA */ + 0x00000000 /* DENALI_PHY_998_DATA */ + 0x00000000 /* DENALI_PHY_999_DATA */ + 0x00000000 /* DENALI_PHY_1000_DATA */ + 0x00000000 /* DENALI_PHY_1001_DATA */ + 0x00000000 /* DENALI_PHY_1002_DATA */ + 0x00000000 /* DENALI_PHY_1003_DATA */ + 0x00000000 /* DENALI_PHY_1004_DATA */ + 0x00000000 /* DENALI_PHY_1005_DATA */ + 0x00000000 /* DENALI_PHY_1006_DATA */ + 0x00000000 /* DENALI_PHY_1007_DATA */ + 0x00000000 /* DENALI_PHY_1008_DATA */ + 0x00000000 /* DENALI_PHY_1009_DATA */ + 0x00000000 /* DENALI_PHY_1010_DATA */ + 0x00000000 /* DENALI_PHY_1011_DATA */ + 0x00000000 /* DENALI_PHY_1012_DATA */ + 0x00000000 /* DENALI_PHY_1013_DATA */ + 0x00000000 /* DENALI_PHY_1014_DATA */ + 0x00000000 /* DENALI_PHY_1015_DATA */ + 0x00000000 /* DENALI_PHY_1016_DATA */ + 0x00000000 /* DENALI_PHY_1017_DATA */ + 0x00000000 /* DENALI_PHY_1018_DATA */ + 0x00000000 /* DENALI_PHY_1019_DATA */ + 0x00000000 /* DENALI_PHY_1020_DATA */ + 0x00000000 /* DENALI_PHY_1021_DATA */ + 0x00000000 /* DENALI_PHY_1022_DATA */ + 0x00000000 /* DENALI_PHY_1023_DATA */ + 0x76543210 /* DENALI_PHY_1024_DATA */ + 0x0004c008 /* DENALI_PHY_1025_DATA */ + 0x000000da /* DENALI_PHY_1026_DATA */ + 0x00000000 /* DENALI_PHY_1027_DATA */ + 0x00000000 /* DENALI_PHY_1028_DATA */ + 0x00010000 /* DENALI_PHY_1029_DATA */ + 0x01665555 /* DENALI_PHY_1030_DATA */ + 0x01665555 /* DENALI_PHY_1031_DATA */ + 0x01030001 /* DENALI_PHY_1032_DATA */ + 0x01000000 /* DENALI_PHY_1033_DATA */ + 0x00c00000 /* DENALI_PHY_1034_DATA */ + 0x00000007 /* DENALI_PHY_1035_DATA */ + 0x00000000 /* DENALI_PHY_1036_DATA */ + 0x00000000 /* DENALI_PHY_1037_DATA */ + 0x04000408 /* DENALI_PHY_1038_DATA */ + 0x00000408 /* DENALI_PHY_1039_DATA */ + 0x00e4e400 /* DENALI_PHY_1040_DATA */ + 0x00000000 /* DENALI_PHY_1041_DATA */ + 0x00000000 /* DENALI_PHY_1042_DATA */ + 0x00000000 /* DENALI_PHY_1043_DATA */ + 0x00000000 /* DENALI_PHY_1044_DATA */ + 0x00000000 /* DENALI_PHY_1045_DATA */ + 0x00000000 /* DENALI_PHY_1046_DATA */ + 0x00000000 /* DENALI_PHY_1047_DATA */ + 0x00000000 /* DENALI_PHY_1048_DATA */ + 0x00000000 /* DENALI_PHY_1049_DATA */ + 0x00000000 /* DENALI_PHY_1050_DATA */ + 0x00000000 /* DENALI_PHY_1051_DATA */ + 0x00000000 /* DENALI_PHY_1052_DATA */ + 0x00000000 /* DENALI_PHY_1053_DATA */ + 0x00000000 /* DENALI_PHY_1054_DATA */ + 0x00000000 /* DENALI_PHY_1055_DATA */ + 0x00000000 /* DENALI_PHY_1056_DATA */ + 0x00200000 /* DENALI_PHY_1057_DATA */ + 0x00000000 /* DENALI_PHY_1058_DATA */ + 0x00000000 /* DENALI_PHY_1059_DATA */ + 0x00000000 /* DENALI_PHY_1060_DATA */ + 0x00000000 /* DENALI_PHY_1061_DATA */ + 0x00000000 /* DENALI_PHY_1062_DATA */ + 0x00000000 /* DENALI_PHY_1063_DATA */ + 0x02800280 /* DENALI_PHY_1064_DATA */ + 0x02800280 /* DENALI_PHY_1065_DATA */ + 0x02800280 /* DENALI_PHY_1066_DATA */ + 0x02800280 /* DENALI_PHY_1067_DATA */ + 0x00000280 /* DENALI_PHY_1068_DATA */ + 0x00000000 /* DENALI_PHY_1069_DATA */ + 0x00000000 /* DENALI_PHY_1070_DATA */ + 0x00000000 /* DENALI_PHY_1071_DATA */ + 0x00000000 /* DENALI_PHY_1072_DATA */ + 0x00000000 /* DENALI_PHY_1073_DATA */ + 0x00800080 /* DENALI_PHY_1074_DATA */ + 0x00800080 /* DENALI_PHY_1075_DATA */ + 0x00800080 /* DENALI_PHY_1076_DATA */ + 0x00800080 /* DENALI_PHY_1077_DATA */ + 0x00800080 /* DENALI_PHY_1078_DATA */ + 0x00800080 /* DENALI_PHY_1079_DATA */ + 0x00800080 /* DENALI_PHY_1080_DATA */ + 0x00800080 /* DENALI_PHY_1081_DATA */ + 0x00800080 /* DENALI_PHY_1082_DATA */ + 0x000100da /* DENALI_PHY_1083_DATA */ + 0x01ff0010 /* DENALI_PHY_1084_DATA */ + 0x00000000 /* DENALI_PHY_1085_DATA */ + 0x00000000 /* DENALI_PHY_1086_DATA */ + 0x00000002 /* DENALI_PHY_1087_DATA */ + 0x51313152 /* DENALI_PHY_1088_DATA */ + 0x80013130 /* DENALI_PHY_1089_DATA */ + 0x02000080 /* DENALI_PHY_1090_DATA */ + 0x00100001 /* DENALI_PHY_1091_DATA */ + 0x0c064208 /* DENALI_PHY_1092_DATA */ + 0x000f0c0f /* DENALI_PHY_1093_DATA */ + 0x01000140 /* DENALI_PHY_1094_DATA */ + 0x0000000c /* DENALI_PHY_1095_DATA */ + 0x00000000 /* DENALI_PHY_1096_DATA */ + 0x00000000 /* DENALI_PHY_1097_DATA */ + 0x00000000 /* DENALI_PHY_1098_DATA */ + 0x00000000 /* DENALI_PHY_1099_DATA */ + 0x00000000 /* DENALI_PHY_1100_DATA */ + 0x00000000 /* DENALI_PHY_1101_DATA */ + 0x00000000 /* DENALI_PHY_1102_DATA */ + 0x00000000 /* DENALI_PHY_1103_DATA */ + 0x00000000 /* DENALI_PHY_1104_DATA */ + 0x00000000 /* DENALI_PHY_1105_DATA */ + 0x00000000 /* DENALI_PHY_1106_DATA */ + 0x00000000 /* DENALI_PHY_1107_DATA */ + 0x00000000 /* DENALI_PHY_1108_DATA */ + 0x00000000 /* DENALI_PHY_1109_DATA */ + 0x00000000 /* DENALI_PHY_1110_DATA */ + 0x00000000 /* DENALI_PHY_1111_DATA */ + 0x00000000 /* DENALI_PHY_1112_DATA */ + 0x00000000 /* DENALI_PHY_1113_DATA */ + 0x00000000 /* DENALI_PHY_1114_DATA */ + 0x00000000 /* DENALI_PHY_1115_DATA */ + 0x00000000 /* DENALI_PHY_1116_DATA */ + 0x00000000 /* DENALI_PHY_1117_DATA */ + 0x00000000 /* DENALI_PHY_1118_DATA */ + 0x00000000 /* DENALI_PHY_1119_DATA */ + 0x00000000 /* DENALI_PHY_1120_DATA */ + 0x00000000 /* DENALI_PHY_1121_DATA */ + 0x00000000 /* DENALI_PHY_1122_DATA */ + 0x00000000 /* DENALI_PHY_1123_DATA */ + 0x00000000 /* DENALI_PHY_1124_DATA */ + 0x00000000 /* DENALI_PHY_1125_DATA */ + 0x00000000 /* DENALI_PHY_1126_DATA */ + 0x00000000 /* DENALI_PHY_1127_DATA */ + 0x00000000 /* DENALI_PHY_1128_DATA */ + 0x00000000 /* DENALI_PHY_1129_DATA */ + 0x00000000 /* DENALI_PHY_1130_DATA */ + 0x00000000 /* DENALI_PHY_1131_DATA */ + 0x00000000 /* DENALI_PHY_1132_DATA */ + 0x00000000 /* DENALI_PHY_1133_DATA */ + 0x00000000 /* DENALI_PHY_1134_DATA */ + 0x00000000 /* DENALI_PHY_1135_DATA */ + 0x00000000 /* DENALI_PHY_1136_DATA */ + 0x00000000 /* DENALI_PHY_1137_DATA */ + 0x00000000 /* DENALI_PHY_1138_DATA */ + 0x00000000 /* DENALI_PHY_1139_DATA */ + 0x00000000 /* DENALI_PHY_1140_DATA */ + 0x00000000 /* DENALI_PHY_1141_DATA */ + 0x00000000 /* DENALI_PHY_1142_DATA */ + 0x00000000 /* DENALI_PHY_1143_DATA */ + 0x00000000 /* DENALI_PHY_1144_DATA */ + 0x00000000 /* DENALI_PHY_1145_DATA */ + 0x00000000 /* DENALI_PHY_1146_DATA */ + 0x00000000 /* DENALI_PHY_1147_DATA */ + 0x00000000 /* DENALI_PHY_1148_DATA */ + 0x00000000 /* DENALI_PHY_1149_DATA */ + 0x00000000 /* DENALI_PHY_1150_DATA */ + 0x00000000 /* DENALI_PHY_1151_DATA */ + 0x00000000 /* DENALI_PHY_1152_DATA */ + 0x00000000 /* DENALI_PHY_1153_DATA */ + 0x00050000 /* DENALI_PHY_1154_DATA */ + 0x00000000 /* DENALI_PHY_1155_DATA */ + 0x00000000 /* DENALI_PHY_1156_DATA */ + 0x00000000 /* DENALI_PHY_1157_DATA */ + 0x00000100 /* DENALI_PHY_1158_DATA */ + 0x00000000 /* DENALI_PHY_1159_DATA */ + 0x00000000 /* DENALI_PHY_1160_DATA */ + 0x00506401 /* DENALI_PHY_1161_DATA */ + 0x01221102 /* DENALI_PHY_1162_DATA */ + 0x00000122 /* DENALI_PHY_1163_DATA */ + 0x00000000 /* DENALI_PHY_1164_DATA */ + 0x000B1F00 /* DENALI_PHY_1165_DATA */ + 0x0B1F0B1F /* DENALI_PHY_1166_DATA */ + 0x0B1F0B1F /* DENALI_PHY_1167_DATA */ + 0x0B1F0B1F /* DENALI_PHY_1168_DATA */ + 0x0B1F0B1F /* DENALI_PHY_1169_DATA */ + 0x00000B00 /* DENALI_PHY_1170_DATA */ + 0x42080010 /* DENALI_PHY_1171_DATA */ + 0x01000100 /* DENALI_PHY_1172_DATA */ + 0x01000100 /* DENALI_PHY_1173_DATA */ + 0x01000100 /* DENALI_PHY_1174_DATA */ + 0x01000100 /* DENALI_PHY_1175_DATA */ + 0x00000000 /* DENALI_PHY_1176_DATA */ + 0x00000000 /* DENALI_PHY_1177_DATA */ + 0x00000000 /* DENALI_PHY_1178_DATA */ + 0x00000000 /* DENALI_PHY_1179_DATA */ + 0x00000000 /* DENALI_PHY_1180_DATA */ + 0x00000803 /* DENALI_PHY_1181_DATA */ + 0x223FFF00 /* DENALI_PHY_1182_DATA */ + 0x000008FF /* DENALI_PHY_1183_DATA */ + 0x0000057F /* DENALI_PHY_1184_DATA */ + 0x0000057F /* DENALI_PHY_1185_DATA */ + 0x00037FFF /* DENALI_PHY_1186_DATA */ + 0x00037FFF /* DENALI_PHY_1187_DATA */ + 0x00004410 /* DENALI_PHY_1188_DATA */ + 0x00004410 /* DENALI_PHY_1189_DATA */ + 0x00004410 /* DENALI_PHY_1190_DATA */ + 0x00004410 /* DENALI_PHY_1191_DATA */ + 0x00004410 /* DENALI_PHY_1192_DATA */ + 0x00000111 /* DENALI_PHY_1193_DATA */ + 0x00000111 /* DENALI_PHY_1194_DATA */ + 0x00000000 /* DENALI_PHY_1195_DATA */ + 0x00000000 /* DENALI_PHY_1196_DATA */ + 0x00000000 /* DENALI_PHY_1197_DATA */ + 0x04000000 /* DENALI_PHY_1198_DATA */ + 0x00000000 /* DENALI_PHY_1199_DATA */ + 0x00000000 /* DENALI_PHY_1200_DATA */ + 0x00000108 /* DENALI_PHY_1201_DATA */ + 0x00000000 /* DENALI_PHY_1202_DATA */ + 0x00000000 /* DENALI_PHY_1203_DATA */ + 0x00000000 /* DENALI_PHY_1204_DATA */ + 0x00000001 /* DENALI_PHY_1205_DATA */ + 0x00000000 /* DENALI_PHY_1206_DATA */ + 0x00000000 /* DENALI_PHY_1207_DATA */ + 0x00000000 /* DENALI_PHY_1208_DATA */ + 0x00000000 /* DENALI_PHY_1209_DATA */ + 0x00000000 /* DENALI_PHY_1210_DATA */ + 0x00000000 /* DENALI_PHY_1211_DATA */ + 0x00020100 /* DENALI_PHY_1212_DATA */ + 0x00000000 /* DENALI_PHY_1213_DATA */ + 0x00000000 /* DENALI_PHY_1214_DATA */ + >; +}; diff --git a/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi new file mode 100644 index 000000000..51b566116 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "binman.dtsi" +#include "fu540-c000-u-boot.dtsi" +#include "fu540-hifive-unleashed-a00-ddr.dtsi" + +/ { + aliases { + cpu1 = &cpu1; + cpu2 = &cpu2; + cpu3 = &cpu3; + cpu4 = &cpu4; + spi0 = &qspi0; + spi2 = &qspi2; + }; + + config { + u-boot,spl-payload-offset = <0x105000>; /* loader2 @1044KB */ + }; + + memory@80000000 { + u-boot,dm-spl; + }; + + hfclk { + u-boot,dm-spl; + }; + + rtcclk { + u-boot,dm-spl; + }; + +}; + +&clint { + clocks = <&rtcclk>; +}; + +&qspi0 { + u-boot,dm-spl; + + flash@0 { + u-boot,dm-spl; + }; +}; + +&qspi2 { + mmc@0 { + u-boot,dm-spl; + }; +}; + +&gpio { + u-boot,dm-spl; +}; diff --git a/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00.dts b/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00.dts new file mode 100644 index 000000000..4a2729f5c --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +#include "fu540-c000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <RTCCLK_FREQ>; + clock-output-names = "rtcclk"; + }; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; diff --git a/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi new file mode 100644 index 000000000..c5475aa14 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020-2021 SiFive, Inc + */ + +#include "binman.dtsi" +#include "fu740-c000-u-boot.dtsi" +#include "fu740-hifive-unmatched-a00-ddr.dtsi" + +/ { + aliases { + spi0 = &spi0; + }; + + memory@80000000 { + u-boot,dm-spl; + }; + + hfclk { + u-boot,dm-spl; + }; + + rtcclk { + u-boot,dm-spl; + }; + +}; + +&clint { + clocks = <&rtcclk>; +}; + +&spi0 { + mmc@0 { + u-boot,dm-spl; + }; +}; + +&gpio { + u-boot,dm-spl; +}; diff --git a/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00.dts b/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00.dts new file mode 100644 index 000000000..b44e8c160 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00.dts @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2019-2021 SiFive, Inc */ + +#include "fu740-c000.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unmatched A00"; + compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", + "sifive,fu740"; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x4 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <RTCCLK_FREQ>; + clock-output-names = "rtcclk"; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + }; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + regulators { + vdd_bcore1: bcore1 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-min-microamp = <5000000>; + regulator-max-microamp = <5000000>; + regulator-always-on; + }; + + vdd_bcore2: bcore2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-min-microamp = <5000000>; + regulator-max-microamp = <5000000>; + regulator-always-on; + }; + + vdd_bpro: bpro { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <2500000>; + regulator-always-on; + }; + + vdd_bperi: bperi { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-min-microamp = <1500000>; + regulator-max-microamp = <1500000>; + regulator-always-on; + }; + + vdd_bmem: bmem { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3000000>; + regulator-max-microamp = <3000000>; + regulator-always-on; + }; + + vdd_bio: bio { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3000000>; + regulator-max-microamp = <3000000>; + regulator-always-on; + }; + + vdd_ldo1: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-min-microamp = <100000>; + regulator-max-microamp = <100000>; + regulator-always-on; + }; + + vdd_ldo2: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo3: ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo4: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo5: ldo5 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-min-microamp = <100000>; + regulator-max-microamp = <100000>; + regulator-always-on; + }; + + vdd_ldo6: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo7: ldo7 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo8: ldo8 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ld09: ldo9 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + }; + + vdd_ldo10: ldo10 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-min-microamp = <300000>; + regulator-max-microamp = <300000>; + }; + + vdd_ldo11: ldo11 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-min-microamp = <300000>; + regulator-max-microamp = <300000>; + regulator-always-on; + }; + }; + }; +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&spi0 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; diff --git a/roms/u-boot/arch/riscv/dts/k210-maix-bit.dts b/roms/u-boot/arch/riscv/dts/k210-maix-bit.dts new file mode 100644 index 000000000..902dcfd08 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/k210-maix-bit.dts @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Sipeed Maix Bit 2.0"; + compatible = "sipeed,maix-bitm", "sipeed,maix-bit", "kendryte,k210"; + + chosen { + stdout-path = "serial0:115200"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + green { + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + red { + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + blue { + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = <BTN_0>; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm61s4030h0"; + status = "disabled"; + }; +}; + +&uarths0 { + pinctrl-0 = <&fpioa_uarths>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&fpioa_gpiohs>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&fpioa_gpio>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&fpioa_i2s0>; + pinctrl-names = "default"; +}; + +&fpioa { + status = "okay"; + + fpioa_uarths: uarths { + pinmux = <K210_FPIOA(4, K210_PCF_UARTHS_RX)>, + <K210_FPIOA(5, K210_PCF_UARTHS_TX)>; + }; + + fpioa_gpio: gpio { + pinmux = <K210_FPIOA(8, K210_PCF_GPIO0)>, + <K210_FPIOA(9, K210_PCF_GPIO1)>, + <K210_FPIOA(10, K210_PCF_GPIO2)>, + <K210_FPIOA(11, K210_PCF_GPIO3)>, + <K210_FPIOA(12, K210_PCF_GPIO4)>, + <K210_FPIOA(13, K210_PCF_GPIO5)>, + <K210_FPIOA(14, K210_PCF_GPIO6)>, + <K210_FPIOA(15, K210_PCF_GPIO7)>; + }; + + fpioa_gpiohs: gpiohs { + pinmux = <K210_FPIOA(16, K210_PCF_GPIOHS0)>, + <K210_FPIOA(17, K210_PCF_GPIOHS1)>, + <K210_FPIOA(21, K210_PCF_GPIOHS5)>, + <K210_FPIOA(22, K210_PCF_GPIOHS6)>, + <K210_FPIOA(23, K210_PCF_GPIOHS7)>, + <K210_FPIOA(24, K210_PCF_GPIOHS8)>, + <K210_FPIOA(25, K210_PCF_GPIOHS9)>, + <K210_FPIOA(30, K210_PCF_GPIOHS14)>, + <K210_FPIOA(31, K210_PCF_GPIOHS15)>, + <K210_FPIOA(32, K210_PCF_GPIOHS16)>, + <K210_FPIOA(33, K210_PCF_GPIOHS17)>, + <K210_FPIOA(34, K210_PCF_GPIOHS18)>, + <K210_FPIOA(35, K210_PCF_GPIOHS19)>; + }; + + fpioa_i2s0: i2s0 { + pinmux = <K210_FPIOA(18, K210_PCF_I2S0_SCLK)>, + <K210_FPIOA(19, K210_PCF_I2S0_WS)>, + <K210_FPIOA(20, K210_PCF_I2S0_IN_D0)>; + }; + + fpioa_dvp: dvp { + pinmux = <K210_FPIOA(40, K210_PCF_SCCB_SDA)>, + <K210_FPIOA(41, K210_PCF_SCCB_SCLK)>, + <K210_FPIOA(42, K210_PCF_DVP_RST)>, + <K210_FPIOA(43, K210_PCF_DVP_VSYNC)>, + <K210_FPIOA(44, K210_PCF_DVP_PWDN)>, + <K210_FPIOA(45, K210_PCF_DVP_HSYNC)>, + <K210_FPIOA(46, K210_PCF_DVP_XCLK)>, + <K210_FPIOA(47, K210_PCF_DVP_PCLK)>; + }; + + fpioa_spi0: spi0 { + pinmux = <K210_FPIOA(36, K210_PCF_GPIOHS20)>, /* cs */ + <K210_FPIOA(37, K210_PCF_GPIOHS21)>, /* rst */ + <K210_FPIOA(38, K210_PCF_GPIOHS22)>, /* dc */ + <K210_FPIOA(39, K210_PCF_SPI0_SCLK)>; /* wr */ + }; + + fpioa_spi1: spi1 { + pinmux = <K210_FPIOA(26, K210_PCF_SPI1_D1)>, + <K210_FPIOA(27, K210_PCF_SPI1_SCLK)>, + <K210_FPIOA(28, K210_PCF_SPI1_D0)>, + <K210_FPIOA(29, K210_PCF_GPIOHS13)>; /* cs */ + }; +}; + +&dvp0 { + pinctrl-0 = <&fpioa_dvp>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&fpioa_spi0>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 0>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&fpioa_spi1>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 13 0>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <25000000>; + voltage-ranges = <3300 3300>; + broken-cd; + }; +}; + +&spi3 { + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + broken-flash-reset; + }; +}; diff --git a/roms/u-boot/arch/riscv/dts/k210.dtsi b/roms/u-boot/arch/riscv/dts/k210.dtsi new file mode 100644 index 000000000..2492af803 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/k210.dtsi @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> + */ + +#include <dt-bindings/clock/k210-sysctl.h> +#include <dt-bindings/mfd/k210-sysctl.h> +#include <dt-bindings/pinctrl/k210-pinctrl.h> +#include <dt-bindings/reset/k210-sysctl.h> + +/ { + /* + * Although the K210 is a 64-bit CPU, the address bus is only 32-bits + * wide, and the upper half of all addresses is ignored. + */ + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210"; + + aliases { + cpu0 = &cpu0; + cpu1 = &cpu1; + dma0 = &dmac0; + gpio0 = &gpio0; + gpio1 = &gpio1_0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + pinctrl0 = &fpioa; + serial0 = &uarths0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <7800000>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "kendryte,k210", "sifive,rocket0", "riscv"; + reg = <0>; + riscv,isa = "rv64imafdgc"; + mmu-type = "sv39"; + i-cache-block-size = <64>; + i-cache-size = <0x8000>; + d-cache-block-size = <64>; + d-cache-size = <0x8000>; + clocks = <&sysclk K210_CLK_CPU>; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "kendryte,k210", "sifive,rocket0", "riscv"; + reg = <1>; + riscv,isa = "rv64imafdgc"; + mmu-type = "sv39"; + i-cache-block-size = <64>; + i-cache-size = <0x8000>; + d-cache-block-size = <64>; + d-cache-size = <0x8000>; + clocks = <&sysclk K210_CLK_CPU>; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + sram: memory@80000000 { + device_type = "memory"; + compatible = "kendryte,k210-sram"; + reg = <0x80000000 0x400000>, + <0x80400000 0x200000>, + <0x80600000 0x200000>; + reg-names = "sram0", "sram1", "aisram"; + clocks = <&sysclk K210_CLK_SRAM0>, + <&sysclk K210_CLK_SRAM1>, + <&sysclk K210_CLK_AI>; + clock-names = "sram0", "sram1", "aisram"; + u-boot,dm-pre-reloc; + }; + + clocks { + in0: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + u-boot,dm-pre-reloc; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-soc", "simple-bus"; + ranges; + interrupt-parent = <&plic0>; + + debug0: debug@0 { + compatible = "kendryte,k210-debug", "riscv,debug"; + reg = <0x0 0x1000>; + }; + + rom0: nvmem@1000 { + reg = <0x1000 0x1000>; + read-only; + }; + + clint0: clint@2000000 { + #interrupt-cells = <1>; + compatible = "kendryte,k210-clint", "riscv,clint0"; + reg = <0x2000000 0xC000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>; + clocks = <&sysclk K210_CLK_CLINT>; + }; + + plic0: interrupt-controller@C000000 { + #interrupt-cells = <1>; + compatible = "kendryte,k210-plic", "riscv,plic0"; + reg = <0xC000000 0x4000000>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>, + <&cpu1_intc 9>, <&cpu1_intc 11>; + riscv,ndev = <65>; + riscv,max-priority = <7>; + }; + + uarths0: serial@38000000 { + compatible = "kendryte,k210-uarths", "sifive,uart0"; + reg = <0x38000000 0x1000>; + interrupts = <33>; + clocks = <&sysclk K210_CLK_CPU>; + status = "disabled"; + }; + + gpio0: gpio-controller@38001000 { + #interrupt-cells = <2>; + #gpio-cells = <2>; + compatible = "kendryte,k210-gpiohs", "sifive,gpio0"; + reg = <0x38001000 0x1000>; + interrupt-controller; + interrupts = <34 35 36 37 38 39 40 41 + 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 + 58 59 60 61 62 63 64 65>; + gpio-controller; + ngpios = <32>; + status = "disabled"; + }; + + kpu0: kpu@40800000 { + compatible = "kendryte,k210-kpu"; + reg = <0x40800000 0xc00000>; + interrupts = <25>; + clocks = <&sysclk K210_CLK_AI>; + status = "disabled"; + }; + + fft0: fft@42000000 { + compatible = "kendryte,k210-fft"; + reg = <0x42000000 0x400000>; + interrupts = <26>; + clocks = <&sysclk K210_CLK_FFT>; + resets = <&sysrst K210_RST_FFT>; + status = "disabled"; + }; + + dmac0: dma-controller@50000000 { + compatible = "kendryte,k210-dmac", "snps,axi-dma-1.01a"; + reg = <0x50000000 0x1000>; + interrupts = <27 28 29 30 31 32>; + clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&sysrst K210_RST_DMA>; + dma-channels = <6>; + snps,dma-masters = <2>; + snps,data-width = <5>; + snps,block-size = <0x200000 0x200000 0x200000 + 0x200000 0x200000 0x200000>; + snps,axi-max-burst-len = <256>; + status = "disabled"; + }; + + apb0: bus@50200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-apb", "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB0>; + + gpio1: gpio-controller@50200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "kendryte,k210-gpio", + "snps,dw-apb-gpio"; + reg = <0x50200000 0x80>; + clocks = <&sysclk K210_CLK_GPIO>; + resets = <&sysrst K210_RST_GPIO>; + status = "disabled"; + + gpio1_0: gpio1@0 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + interrupt-controller; + interrupts = <23>; + gpio-controller; + snps,nr-gpios = <8>; + }; + }; + + uart1: serial@50210000 { + compatible = "kendryte,k210-uart", + "snps,dw-apb-uart"; + reg = <0x50210000 0x100>; + interrupts = <11>; + clocks = <&sysclk K210_CLK_UART1>; + resets = <&sysrst K210_RST_UART1>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart2: serial@50220000 { + compatible = "kendryte,k210-uart", + "snps,dw-apb-uart"; + reg = <0x50220000 0x100>; + interrupts = <12>; + clocks = <&sysclk K210_CLK_UART2>; + resets = <&sysrst K210_RST_UART2>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart3: serial@50230000 { + compatible = "kendryte,k210-uart", + "snps,dw-apb-uart"; + reg = <0x50230000 0x100>; + interrupts = <13>; + clocks = <&sysclk K210_CLK_UART3>; + resets = <&sysrst K210_RST_UART3>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + spi2: spi@50240000 { + compatible = "canaan,kendryte-k210-spi", + "snps,dw-apb-ssi-4.01", + "snps,dw-apb-ssi"; + spi-slave; + reg = <0x50240000 0x100>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI2>; + resets = <&sysrst K210_RST_SPI2>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + i2s0: i2s@50250000 { + compatible = "kendryte,k210-i2s", + "snps,designware-i2s"; + reg = <0x50250000 0x200>; + interrupts = <5>; + clocks = <&sysclk K210_CLK_I2S0>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S0>; + status = "disabled"; + }; + + apu0: sound@520250200 { + compatible = "kendryte,k210-apu"; + reg = <0x50250200 0x200>; + status = "disabled"; + }; + + i2s1: i2s@50260000 { + compatible = "kendryte,k210-i2s", + "snps,designware-i2s"; + reg = <0x50260000 0x200>; + interrupts = <6>; + clocks = <&sysclk K210_CLK_I2S1>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@50270000 { + compatible = "kendryte,k210-i2s", + "snps,designware-i2s"; + reg = <0x50270000 0x200>; + interrupts = <7>; + clocks = <&sysclk K210_CLK_I2S2>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S2>; + status = "disabled"; + }; + + i2c0: i2c@50280000 { + compatible = "kendryte,k210-i2c", + "snps,designware-i2c"; + reg = <0x50280000 0x100>; + interrupts = <8>; + clocks = <&sysclk K210_CLK_I2C0>; + resets = <&sysrst K210_RST_I2C0>; + status = "disabled"; + }; + + i2c1: i2c@50290000 { + compatible = "kendryte,k210-i2c", + "snps,designware-i2c"; + reg = <0x50290000 0x100>; + interrupts = <9>; + clocks = <&sysclk K210_CLK_I2C1>; + resets = <&sysrst K210_RST_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@502A0000 { + compatible = "kendryte,k210-i2c", + "snps,designware-i2c"; + reg = <0x502A0000 0x100>; + interrupts = <10>; + clocks = <&sysclk K210_CLK_I2C2>; + resets = <&sysrst K210_RST_I2C2>; + status = "disabled"; + }; + + fpioa: pinmux@502B0000 { + compatible = "kendryte,k210-fpioa"; + reg = <0x502B0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>; + resets = <&sysrst K210_RST_FPIOA>; + kendryte,sysctl = <&sysctl>; + kendryte,power-offset = <K210_SYSCTL_POWER_SEL>; + pinctrl-0 = <&fpioa_jtag>; + pinctrl-names = "default"; + status = "disabled"; + + fpioa_jtag: jtag { + pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>, + <K210_FPIOA(1, K210_PCF_JTAG_TDI)>, + <K210_FPIOA(2, K210_PCF_JTAG_TMS)>, + <K210_FPIOA(3, K210_PCF_JTAG_TDO)>; + }; + }; + + sha256: sha256@502C0000 { + compatible = "kendryte,k210-sha256"; + reg = <0x502C0000 0x100>; + clocks = <&sysclk K210_CLK_SHA>; + resets = <&sysrst K210_RST_SHA>; + status = "disabled"; + }; + + timer0: timer@502D0000 { + compatible = "kendryte,k210-timer", + "snps,dw-apb-timer"; + reg = <0x502D0000 0x100>; + interrupts = <14 15>; + clocks = <&sysclk K210_CLK_TIMER0>; + clock-names = "timer"; + resets = <&sysrst K210_RST_TIMER0>; + status = "disabled"; + }; + + timer1: timer@502E0000 { + compatible = "kendryte,k210-timer", + "snps,dw-apb-timer"; + reg = <0x502E0000 0x100>; + interrupts = <16 17>; + clocks = <&sysclk K210_CLK_TIMER1>; + clock-names = "timer"; + resets = <&sysrst K210_RST_TIMER1>; + status = "disabled"; + }; + + timer2: timer@502F0000 { + compatible = "kendryte,k210-timer", + "snps,dw-apb-timer"; + reg = <0x502F0000 0x100>; + interrupts = <18 19>; + clocks = <&sysclk K210_CLK_TIMER2>; + clock-names = "timer"; + resets = <&sysrst K210_RST_TIMER2>; + status = "disabled"; + }; + }; + + apb1: bus@50400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-apb", "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB1>; + + wdt0: watchdog@50400000 { + compatible = "kendryte,k210-wdt", "snps,dw-wdt"; + reg = <0x50400000 0x100>; + interrupts = <21>; + clocks = <&sysclk K210_CLK_WDT0>; + resets = <&sysrst K210_RST_WDT0>; + }; + + wdt1: watchdog@50410000 { + compatible = "kendryte,k210-wdt", "snps,dw-wdt"; + reg = <0x50410000 0x100>; + interrupts = <22>; + clocks = <&sysclk K210_CLK_WDT1>; + resets = <&sysrst K210_RST_WDT1>; + status = "disabled"; + }; + + otp0: nvmem@50420000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-otp"; + reg = <0x50420000 0x100>, + <0x88000000 0x20000>; + reg-names = "reg", "mem"; + clocks = <&sysclk K210_CLK_ROM>; + resets = <&sysrst K210_RST_ROM>; + read-only; + status = "disabled"; + + /* Bootloader */ + firmware@00000 { + reg = <0x00000 0xC200>; + }; + + /* + * config string as described in RISC-V + * privileged spec 1.9 + */ + config-1-9@1c000 { + reg = <0x1C000 0x1000>; + }; + + /* + * Device tree containing only registers, + * interrupts, and cpus + */ + fdt@1d000 { + reg = <0x1D000 0x2000>; + }; + + /* CPU/ROM credits */ + credits@1f000 { + reg = <0x1F000 0x1000>; + }; + }; + + dvp0: camera@50430000 { + compatible = "kendryte,k210-dvp"; + reg = <0x50430000 0x100>; + interrupts = <24>; + clocks = <&sysclk K210_CLK_DVP>; + resets = <&sysrst K210_RST_DVP>; + kendryte,sysctl = <&sysctl>; + kendryte,misc-offset = <K210_SYSCTL_MISC>; + status = "disabled"; + }; + + sysctl: syscon@50440000 { + compatible = "kendryte,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x100>; + reg-io-width = <4>; + u-boot,dm-pre-reloc; + + sysclk: clock-controller { + #clock-cells = <1>; + compatible = "kendryte,k210-clk"; + clocks = <&in0>; + u-boot,dm-pre-reloc; + }; + + sysrst: reset-controller { + compatible = "kendryte,k210-rst", + "syscon-reset"; + #reset-cells = <1>; + regmap = <&sysctl>; + offset = <K210_SYSCTL_PERI_RESET>; + mask = <0x27FFFFFF>; + assert-high = <1>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctl>; + offset = <K210_SYSCTL_SOFT_RESET>; + mask = <1>; + value = <1>; + }; + }; + + aes0: aes@50450000 { + compatible = "kendryte,k210-aes"; + reg = <0x50450000 0x100>; + clocks = <&sysclk K210_CLK_AES>; + resets = <&sysrst K210_RST_AES>; + status = "disabled"; + }; + + rtc: rtc@50460000 { + compatible = "kendryte,k210-rtc"; + reg = <0x50460000 0x100>; + clocks = <&in0>; + resets = <&sysrst K210_RST_RTC>; + interrupts = <20>; + status = "disabled"; + }; + }; + + apb2: bus@52000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-apb", "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB2>; + + spi0: spi@52000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,kendryte-k210-spi", + "snps,dw-apb-ssi-4.01", + "snps,dw-apb-ssi"; + reg = <0x52000000 0x100>; + interrupts = <1>; + clocks = <&sysclk K210_CLK_SPI0>; + clock-names = "ssi_clk"; + resets = <&sysrst K210_RST_SPI0>; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi1: spi@53000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,kendryte-k210-spi", + "snps,dw-apb-ssi-4.01", + "snps,dw-apb-ssi"; + reg = <0x53000000 0x100>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI1>; + clock-names = "ssi_clk"; + resets = <&sysrst K210_RST_SPI1>; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi3: spi@54000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,kendryte-k210-ssi", + "snps,dwc-ssi-1.01a"; + reg = <0x54000000 0x200>; + interrupts = <4>; + clocks = <&sysclk K210_CLK_SPI3>; + clock-names = "ssi_clk"; + resets = <&sysrst K210_RST_SPI3>; + /* Could possibly go up to 200 MHz */ + spi-max-frequency = <100000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + }; + }; +}; diff --git a/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi new file mode 100644 index 000000000..f60283fb6 --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ + +/ { + aliases { + cpu1 = &cpu1; + cpu2 = &cpu2; + cpu3 = &cpu3; + cpu4 = &cpu4; + }; +}; diff --git a/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit.dts new file mode 100644 index 000000000..89c4cf5fb --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit.dts @@ -0,0 +1,417 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 Microchip Technology Inc */ + +/dts-v1/; +#include "dt-bindings/clock/microchip-mpfs-clock.h" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip MPFS Icicle Kit"; + compatible = "microchip,mpfs-icicle-kit"; + + aliases { + serial0 = &uart0; + ethernet0 = &emac1; + }; + + chosen { + stdout-path = "serial0"; + }; + + cpucomplex: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <RTCCLK_FREQ>; + cpu0: cpu@0 { + clocks = <&clkcfg CLK_CPU>; + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu0intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + clocks = <&clkcfg CLK_CPU>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu1intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clocks = <&clkcfg CLK_CPU>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu2intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clocks = <&clkcfg CLK_CPU>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu3intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clocks = <&clkcfg CLK_CPU>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu4intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "msspllclk"; + }; + ddr: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + clocks = <&clkcfg CLK_DDRC>; + }; + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "microchip,mpfs-icicle-kit", "simple-bus"; + ranges; + clint0: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0intc 3 &cpu0intc 7 + &cpu1intc 3 &cpu1intc 7 + &cpu2intc 3 &cpu2intc 7 + &cpu3intc 3 &cpu3intc 7 + &cpu4intc 3 &cpu4intc 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + reg-names = "control"; + clock-frequency = <RTCCLK_FREQ>; + }; + cachecontroller: cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,max-priority = <7>; + riscv,ndev = <186>; + interrupt-controller; + interrupts-extended = < + &cpu0intc 11 + &cpu1intc 11 &cpu1intc 9 + &cpu2intc 11 &cpu2intc 9 + &cpu3intc 11 &cpu3intc 9 + &cpu4intc 11 &cpu4intc 9>; + }; + uart0: serial@20000000 { + compatible = "ns16550a"; + reg = <0x0 0x20000000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <90>; + clocks = <&clkcfg CLK_MMUART0>; + status = "okay"; + }; + clkcfg: clkcfg@20002000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>; + reg-names = "mss_sysreg"; + clocks = <&refclk>; + #clock-cells = <1>; + clock-output-names = "cpu", "axi", "ahb", "envm", + "mac0", "mac1", "mmc", "timer", + "mmuart0", "mmuart1", "mmuart2", + "mmuart3", "mmuart4", "spi0", "spi1", + "i2c0", "i2c1", "can0", "can1", "usb", + "reserved", "rtc", "qspi", "gpio0", + "gpio1", "gpio2", "ddrc", "fic0", + "fic1", "fic2", "fic3", "athena", + "cfm"; + }; + emmc: mmc@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88 89>; + pinctrl-names = "default"; + clocks = <&clkcfg CLK_MMC>; + bus-width = <4>; + cap-mmc-highspeed; + mmc-ddr-3_3v; + max-frequency = <200000000>; + non-removable; + no-sd; + no-sdio; + voltage-ranges = <3300 3300>; + status = "okay"; + }; + sdcard: sd@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88>; + pinctrl-names = "default"; + clocks = <&clkcfg CLK_MMC>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + card-detect-delay = <200>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + status = "disabled"; + }; + uart1: serial@20100000 { + compatible = "ns16550a"; + reg = <0x0 0x20100000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <91>; + clocks = <&clkcfg CLK_MMUART1>; + status = "okay"; + }; + uart2: serial@20102000 { + compatible = "ns16550a"; + reg = <0x0 0x20102000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <92>; + clocks = <&clkcfg CLK_MMUART2>; + status = "okay"; + }; + uart3: serial@20104000 { + compatible = "ns16550a"; + reg = <0x0 0x20104000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <93>; + clocks = <&clkcfg CLK_MMUART3>; + status = "okay"; + }; + i2c0: i2c@2010a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,mpfs-mss-i2c"; + reg = <0x0 0x2010a000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clkcfg CLK_I2C0>; + status = "disabled"; + }; + i2c1: i2c@2010b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,mpfs-mss-i2c"; + reg = <0x0 0x2010b000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <61>; + clocks = <&clkcfg CLK_I2C1>; + status = "disabled"; + pac193x@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + samp-rate = <64>; + status = "disabled"; + ch1: channel0 { + uohms-shunt-res = <10000>; + rail-name = "VDD"; + channel_enabled; + }; + ch2: channel1 { + uohms-shunt-res = <10000>; + rail-name = "VDDA25"; + channel_enabled; + }; + ch3: channel2 { + uohms-shunt-res = <10000>; + rail-name = "VDD25"; + channel_enabled; + }; + ch4: channel3 { + uohms-shunt-res = <10000>; + rail-name = "VDDA"; + channel_enabled; + }; + }; + }; + emac0: ethernet@20110000 { + compatible = "microchip,mpfs-mss-gem"; + reg = <0x0 0x20110000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <64 65 66 67>; + local-mac-address = [56 34 00 FC 00 02]; + phy-mode = "sgmii"; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy0>; + phy0: ethernet-phy@8 { + reg = <8>; + ti,fifo-depth = <0x01>; + }; + }; + emac1: ethernet@20112000 { + compatible = "microchip,mpfs-mss-gem"; + reg = <0x0 0x20112000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <70 71 72 73>; + local-mac-address = [00 00 00 00 00 00]; + phy-mode = "sgmii"; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy1>; + phy1: ethernet-phy@9 { + reg = <9>; + ti,fifo-depth = <0x01>; + }; + }; + gpio: gpio@20122000 { + compatible = "microchip,mpfs-mss-gpio"; + interrupt-parent = <&plic>; + interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26 + 27 28 29 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44>; + gpio-controller; + clocks = <&clkcfg CLK_GPIO2>; + reg = <0x00 0x20122000 0x0 0x1000>; + reg-names = "control"; + #gpio-cells = <2>; + status = "disabled"; + }; + }; +}; diff --git a/roms/u-boot/arch/riscv/dts/qemu-virt.dts b/roms/u-boot/arch/riscv/dts/qemu-virt.dts new file mode 100644 index 000000000..fecff542b --- /dev/null +++ b/roms/u-boot/arch/riscv/dts/qemu-virt.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com> + */ + +/dts-v1/; + +#include "binman.dtsi" |