diff options
Diffstat (limited to 'roms/u-boot/arch/x86/cpu/baytrail')
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/baytrail/Kconfig | 42 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/baytrail/Makefile | 9 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/baytrail/acpi.c | 207 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/baytrail/cpu.c | 209 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/baytrail/early_uart.c | 86 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/baytrail/fsp_configs.c | 171 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/baytrail/valleyview.c | 59 |
7 files changed, 783 insertions, 0 deletions
diff --git a/roms/u-boot/arch/x86/cpu/baytrail/Kconfig b/roms/u-boot/arch/x86/cpu/baytrail/Kconfig new file mode 100644 index 000000000..d2c3473d6 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/baytrail/Kconfig @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Google, Inc + +config INTEL_BAYTRAIL + bool + select HAVE_FSP + select ARCH_MISC_INIT + select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED + imply HAVE_INTEL_ME + imply ENABLE_MRC_CACHE + imply AHCI_PCI + imply ICH_SPI + imply INTEL_ICH6_GPIO + imply PINCTRL_ICH6 + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply SCSI + imply SCSI_AHCI + imply SPI_FLASH + imply SYS_NS16550 + imply USB + imply USB_EHCI_HCD + imply USB_XHCI_HCD + imply VIDEO_VESA + +if INTEL_BAYTRAIL +config INTERNAL_UART + bool "Enable the SoC integrated legacy UART" + help + There is a legacy UART integrated into the Bay Trail SoC. + A maximum baud rate of 115200 bps is supported. For this + reason, it is recommended that the UART port be used for + debug purposes only, eg: U-Boot console. + +config DEBUG_UART + bool + select DEBUG_UART_BOARD_INIT + +endif diff --git a/roms/u-boot/arch/x86/cpu/baytrail/Makefile b/roms/u-boot/arch/x86/cpu/baytrail/Makefile new file mode 100644 index 000000000..ce5d6178c --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/baytrail/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Google, Inc + +obj-y += cpu.o +obj-y += early_uart.o +obj-y += fsp_configs.o +obj-y += valleyview.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o diff --git a/roms/u-boot/arch/x86/cpu/baytrail/acpi.c b/roms/u-boot/arch/x86/cpu/baytrail/acpi.c new file mode 100644 index 000000000..07757b88a --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/baytrail/acpi.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <log.h> +#include <acpi/acpi_s3.h> +#include <acpi/acpi_table.h> +#include <asm/io.h> +#include <asm/tables.h> +#include <asm/arch/global_nvs.h> +#include <asm/arch/iomap.h> +#include <dm/uclass-internal.h> + +void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt) +{ + struct acpi_table_header *header = &(fadt->header); + u16 pmbase = ACPI_BASE_ADDRESS; + + memset((void *)fadt, 0, sizeof(struct acpi_fadt)); + + acpi_fill_header(header, "FACP"); + header->length = sizeof(struct acpi_fadt); + header->revision = 4; + + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + fadt->preferred_pm_profile = ACPI_PM_MOBILE; + fadt->sci_int = 9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0; + fadt->pstate_cnt = 0; + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0x0d; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = IO_PORT_RESET; + fadt->reset_reg.addrh = 0; + fadt->reset_value = SYS_RST | RST_CPU | FULL_RST; + + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = table_compute_checksum(fadt, header->length); +} + +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + struct udevice *dev; + int ret; + + /* at least we have one processor */ + gnvs->pcnt = 1; + /* override the processor count with actual number */ + ret = uclass_find_first_device(UCLASS_CPU, &dev); + if (ret == 0 && dev != NULL) { + ret = cpu_get_count(dev); + if (ret > 0) + gnvs->pcnt = ret; + } + + /* determine whether internal uart is on */ + if (IS_ENABLED(CONFIG_INTERNAL_UART)) + gnvs->iuart_en = 1; + else + gnvs->iuart_en = 0; + + return 0; +} + +/* + * The following two routines are called at a very early stage, even before + * FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS + * and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses + * of these two blocks are programmed by either U-Boot or FSP. + * + * It has been verified that 1st phase API (see arch/x86/lib/fsp1/fsp_car.S) + * on Intel BayTrail SoC already initializes these two base addresses so + * we are safe to access these registers here. + */ + +enum acpi_sleep_state chipset_prev_sleep_state(void) +{ + u32 pm1_sts; + u32 pm1_cnt; + u32 gen_pmcon1; + enum acpi_sleep_state prev_sleep_state = ACPI_S0; + + /* Read Power State */ + pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1); + + debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", + pm1_sts, pm1_cnt, gen_pmcon1); + + if (pm1_sts & WAK_STS) + prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt); + + if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + return prev_sleep_state; +} + +void chipset_clear_sleep_state(void) +{ + u32 pm1_cnt; + + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); +} diff --git a/roms/u-boot/arch/x86/cpu/baytrail/cpu.c b/roms/u-boot/arch/x86/cpu/baytrail/cpu.c new file mode 100644 index 000000000..309a50a11 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/baytrail/cpu.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Google, Inc + * + * Based on code from coreboot + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <init.h> +#include <log.h> +#include <pci.h> +#include <asm/cpu.h> +#include <asm/cpu_x86.h> +#include <asm/io.h> +#include <asm/lapic.h> +#include <asm/msr.h> +#include <asm/turbo.h> + +#define BYT_PRV_CLK 0x800 +#define BYT_PRV_CLK_EN (1 << 0) +#define BYT_PRV_CLK_M_VAL_SHIFT 1 +#define BYT_PRV_CLK_N_VAL_SHIFT 16 +#define BYT_PRV_CLK_UPDATE (1 << 31) + +static void hsuart_clock_set(void *base) +{ + u32 m, n, reg; + + /* + * Configure the BayTrail UART clock for the internal HS UARTs + * (PCI devices) to 58982400 Hz + */ + m = 0x2400; + n = 0x3d09; + reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); + writel(reg, base + BYT_PRV_CLK); + reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; + writel(reg, base + BYT_PRV_CLK); +} + +/* + * Configure the internal clock of both SIO HS-UARTs, if they are enabled + * via FSP + */ +int arch_cpu_init_dm(void) +{ + struct udevice *dev; + void *base; + int ret; + int i; + + /* Loop over the 2 HS-UARTs */ + for (i = 0; i < 2; i++) { + ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1e, 3 + i), &dev); + if (!ret) { + base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + hsuart_clock_set(base); + } + } + + return 0; +} + +static void set_max_freq(void) +{ + msr_t perf_ctl; + msr_t msr; + + /* Enable speed step */ + msr = msr_read(MSR_IA32_MISC_ENABLE); + msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP; + msr_write(MSR_IA32_MISC_ENABLE, msr); + + /* + * Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of + * the PERF_CTL + */ + msr = msr_read(MSR_IACORE_RATIOS); + perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; + + /* + * Set guaranteed vid [22:16] from IACORE_VIDS to bits [7:0] of + * the PERF_CTL + */ + msr = msr_read(MSR_IACORE_VIDS); + perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; + perf_ctl.hi = 0; + + msr_write(MSR_IA32_PERF_CTL, perf_ctl); +} + +static int cpu_x86_baytrail_probe(struct udevice *dev) +{ + if (!ll_boot_init()) + return 0; + debug("Init BayTrail core\n"); + + /* + * On BayTrail the turbo disable bit is actually scoped at the + * building-block level, not package. For non-BSP cores that are + * within a building block, enable turbo. The cores within the BSP's + * building block will just see it already enabled and move on. + */ + if (lapicid()) + turbo_enable(); + + /* Dynamic L2 shrink enable and threshold */ + msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f000f, 0xe0008), + + /* Disable C1E */ + msr_clrsetbits_64(MSR_POWER_CTL, 2, 0); + msr_setbits_64(MSR_POWER_MISC, 0x44); + + /* Set this core to max frequency ratio */ + set_max_freq(); + + return 0; +} + +static unsigned bus_freq(void) +{ + msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL); + switch (clk_info.lo & 0x3) { + case 0: + return 83333333; + case 1: + return 100000000; + case 2: + return 133333333; + case 3: + return 116666666; + default: + return 0; + } +} + +static unsigned long tsc_freq(void) +{ + msr_t platform_info; + ulong bclk = bus_freq(); + + if (!bclk) + return 0; + + platform_info = msr_read(MSR_PLATFORM_INFO); + + return bclk * ((platform_info.lo >> 8) & 0xff); +} + +static int baytrail_get_info(const struct udevice *dev, struct cpu_info *info) +{ + info->cpu_freq = tsc_freq(); + info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU; + + return 0; +} + +static int baytrail_get_count(const struct udevice *dev) +{ + int ecx = 0; + + /* + * Use the algorithm described in Intel 64 and IA-32 Architectures + * Software Developer's Manual Volume 3 (3A, 3B & 3C): System + * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping + * of CPUID Extended Topology Leaf. + */ + while (1) { + struct cpuid_result leaf_b; + + leaf_b = cpuid_ext(0xb, ecx); + + /* + * Bay Trail doesn't have hyperthreading so just determine the + * number of cores by from level type (ecx[15:8] == * 2) + */ + if ((leaf_b.ecx & 0xff00) == 0x0200) + return leaf_b.ebx & 0xffff; + + ecx++; + } + + return 0; +} + +static const struct cpu_ops cpu_x86_baytrail_ops = { + .get_desc = cpu_x86_get_desc, + .get_info = baytrail_get_info, + .get_count = baytrail_get_count, + .get_vendor = cpu_x86_get_vendor, +}; + +static const struct udevice_id cpu_x86_baytrail_ids[] = { + { .compatible = "intel,baytrail-cpu" }, + { } +}; + +U_BOOT_DRIVER(cpu_x86_baytrail_drv) = { + .name = "cpu_x86_baytrail", + .id = UCLASS_CPU, + .of_match = cpu_x86_baytrail_ids, + .bind = cpu_x86_bind, + .probe = cpu_x86_baytrail_probe, + .ops = &cpu_x86_baytrail_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/roms/u-boot/arch/x86/cpu/baytrail/early_uart.c b/roms/u-boot/arch/x86/cpu/baytrail/early_uart.c new file mode 100644 index 000000000..08dbd5538 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/baytrail/early_uart.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Google, Inc + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> + +#define PCI_DEV_CONFIG(segbus, dev, fn) ( \ + (((segbus) & 0xfff) << 20) | \ + (((dev) & 0x1f) << 15) | \ + (((fn) & 0x07) << 12)) + +/* Platform Controller Unit */ +#define LPC_DEV 0x1f +#define LPC_FUNC 0 + +/* Enable UART */ +#define UART_CONT 0x80 + +/* SCORE Pad definitions */ +#define UART_RXD_PAD 82 +#define UART_TXD_PAD 83 + +/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */ +#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed0c000 +#define IO_BASE_OFFSET_GPSCORE 0x0000 +#define IO_BASE_OFFSET_GPNCORE 0x1000 +#define IO_BASE_OFFSET_GPSSUS 0x2000 +#define IO_BASE_SIZE 0x4000 + +static inline unsigned int score_pconf0(int pad_num) +{ + return GPSCORE_PAD_BASE + pad_num * 16; +} + +static void score_select_func(int pad, int func) +{ + uint32_t reg; + uint32_t pconf0_addr = score_pconf0(pad); + + reg = readl(pconf0_addr); + reg &= ~0x7; + reg |= func & 0x7; + writel(reg, pconf0_addr); +} + +static void x86_pci_write_config32(int dev, unsigned int where, u32 value) +{ + unsigned long addr; + + addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3); + writel(value, addr); +} + +/* This can be called after memory-mapped PCI is working */ +int setup_internal_uart(int enable) +{ + /* Enable or disable the legacy UART hardware */ + x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, + enable); + + /* All done for the disable part, so just return */ + if (!enable) + return 0; + + /* + * Set up the pads to the UART function. This allows the signals to + * leave the chip + */ + score_select_func(UART_RXD_PAD, 1); + score_select_func(UART_TXD_PAD, 1); + + /* TODO(sjg@chromium.org): Call debug_uart_init() */ + + return 0; +} + +void board_debug_uart_init(void) +{ + setup_internal_uart(1); +} diff --git a/roms/u-boot/arch/x86/cpu/baytrail/fsp_configs.c b/roms/u-boot/arch/x86/cpu/baytrail/fsp_configs.c new file mode 100644 index 000000000..fb3f946c4 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/baytrail/fsp_configs.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: Intel +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + * Copyright (C) 2015, Kodak Alaris, Inc + */ + +#include <common.h> +#include <fdtdec.h> +#include <log.h> +#include <asm/fsp1/fsp_support.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * Override the FSP's Azalia configuration data + * + * @azalia: pointer to be updated to point to a ROM address where Azalia + * configuration data is stored + */ +__weak void update_fsp_azalia_configs(struct azalia_config **azalia) +{ + *azalia = NULL; +} + +/** + * Override the FSP's configuration data. + * If the device tree does not specify an integer setting, use the default + * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. + */ +void fsp_update_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) +{ + struct upd_region *fsp_upd = &config->fsp_upd; + struct memory_down_data *mem; + const void *blob = gd->fdt_blob; + int node; + + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-tseg-size", + MRC_INIT_TSEG_SIZE_1MB); + fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-mmio-size", + MRC_INIT_MMIO_SIZE_2048MB); + fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr1", + 0xa0); + fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr2", + 0xa2); + fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node, + "fsp,emmc-boot-mode", + EMMC_BOOT_MODE_EMMC41); + fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio"); + fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node, + "fsp,enable-sdcard"); + fsp_upd->enable_hsuart0 = fdtdec_get_bool(blob, node, + "fsp,enable-hsuart0"); + fsp_upd->enable_hsuart1 = fdtdec_get_bool(blob, node, + "fsp,enable-hsuart1"); + fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi"); + fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata"); + fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", + SATA_MODE_AHCI); + fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, + "fsp,enable-azalia"); + if (fsp_upd->enable_azalia) + update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr); + fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); + fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode", + LPE_MODE_PCI); + fsp_upd->lpss_sio_mode = fdtdec_get_int(blob, node, "fsp,lpss-sio-mode", + LPSS_SIO_MODE_PCI); + fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0"); + fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1"); + fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0"); + fsp_upd->enable_i2_c1 = fdtdec_get_bool(blob, node, "fsp,enable-i2c1"); + fsp_upd->enable_i2_c2 = fdtdec_get_bool(blob, node, "fsp,enable-i2c2"); + fsp_upd->enable_i2_c3 = fdtdec_get_bool(blob, node, "fsp,enable-i2c3"); + fsp_upd->enable_i2_c4 = fdtdec_get_bool(blob, node, "fsp,enable-i2c4"); + fsp_upd->enable_i2_c5 = fdtdec_get_bool(blob, node, "fsp,enable-i2c5"); + fsp_upd->enable_i2_c6 = fdtdec_get_bool(blob, node, "fsp,enable-i2c6"); + fsp_upd->enable_pwm0 = fdtdec_get_bool(blob, node, "fsp,enable-pwm0"); + fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1"); + fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi"); + fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node, + "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_64MB); + fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size", + APERTURE_SIZE_256MB); + fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", + GTT_SIZE_2MB); + fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node, + "fsp,mrc-debug-msg"); + fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable"); + fsp_upd->scc_mode = fdtdec_get_int(blob, node, "fsp,scc-mode", + SCC_MODE_PCI); + fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node, + "fsp,igd-render-standby"); + fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node, + "fsp,txe-uma-enable"); + fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection", + OS_SELECTION_LINUX); + fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node, + "fsp,emmc45-ddr50-enabled"); + fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node, + "fsp,emmc45-hs200-enabled"); + fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node, + "fsp,emmc45-retune-timer-value", 8); + fsp_upd->enable_igd = fdtdec_get_bool(blob, node, "fsp,enable-igd"); + + mem = &fsp_upd->memory_params; + mem->enable_memory_down = fdtdec_get_bool(blob, node, + "fsp,enable-memory-down"); + if (mem->enable_memory_down) { + node = fdtdec_next_compatible(blob, node, + COMPAT_INTEL_BAYTRAIL_FSP_MDP); + if (node < 0) { + debug("%s: Cannot find FSP memory-down-params node\n", + __func__); + } else { + mem->dram_speed = fdtdec_get_int(blob, node, + "fsp,dram-speed", + DRAM_SPEED_1333MTS); + mem->dram_type = fdtdec_get_int(blob, node, + "fsp,dram-type", + DRAM_TYPE_DDR3L); + mem->dimm_0_enable = fdtdec_get_bool(blob, node, + "fsp,dimm-0-enable"); + mem->dimm_1_enable = fdtdec_get_bool(blob, node, + "fsp,dimm-1-enable"); + mem->dimm_width = fdtdec_get_int(blob, node, + "fsp,dimm-width", + DIMM_WIDTH_X8); + mem->dimm_density = fdtdec_get_int(blob, node, + "fsp,dimm-density", + DIMM_DENSITY_2GBIT); + mem->dimm_bus_width = fdtdec_get_int(blob, node, + "fsp,dimm-bus-width", + DIMM_BUS_WIDTH_64BITS); + mem->dimm_sides = fdtdec_get_int(blob, node, + "fsp,dimm-sides", + DIMM_SIDES_1RANKS); + mem->dimm_tcl = fdtdec_get_int(blob, node, + "fsp,dimm-tcl", 0x09); + mem->dimm_trpt_rcd = fdtdec_get_int(blob, node, + "fsp,dimm-trpt-rcd", 0x09); + mem->dimm_twr = fdtdec_get_int(blob, node, + "fsp,dimm-twr", 0x0a); + mem->dimm_twtr = fdtdec_get_int(blob, node, + "fsp,dimm-twtr", 0x05); + mem->dimm_trrd = fdtdec_get_int(blob, node, + "fsp,dimm-trrd", 0x04); + mem->dimm_trtp = fdtdec_get_int(blob, node, + "fsp,dimm-trtp", 0x05); + mem->dimm_tfaw = fdtdec_get_int(blob, node, + "fsp,dimm-tfaw", 0x14); + } + } +} diff --git a/roms/u-boot/arch/x86/cpu/baytrail/valleyview.c b/roms/u-boot/arch/x86/cpu/baytrail/valleyview.c new file mode 100644 index 000000000..f73738ce5 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/baytrail/valleyview.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <init.h> +#include <mmc.h> +#include <pci_ids.h> +#include <asm/irq.h> +#include <asm/mrccache.h> +#include <asm/post.h> +#include <asm/arch/iomap.h> +#include <linux/bitops.h> + +/* GPIO SUS */ +#define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) +#define GPIO_SUS_DFX5_CONF0 0x150 +#define BYT_TRIG_LVL BIT(24) +#define BYT_TRIG_POS BIT(25) + +int arch_cpu_init(void) +{ + post_code(POST_CPU_INIT); + + return x86_cpu_init_f(); +} + +int arch_misc_init(void) +{ + if (!ll_boot_init()) + return 0; + +#ifdef CONFIG_ENABLE_MRC_CACHE + /* + * We intend not to check any return value here, as even MRC cache + * is not saved successfully, it is not a severe error that will + * prevent system from continuing to boot. + */ + mrccache_save(); +#endif + + /* + * For some unknown reason, FSP (gold4) for BayTrail configures + * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25). + * This does not cause any issue when Linux kernel runs w/ or w/o + * the pinctrl driver for BayTrail. However this causes unstable + * S3 resume if the pinctrl driver is included in the kernel build. + * As this pin keeps generating interrupts during an S3 resume, + * and there is no IRQ requester in the kernel to handle it, the + * kernel seems to hang and does not continue resuming. + * + * Clear the mysterious interrupt bits for this pin. + */ + clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0, + BYT_TRIG_LVL | BYT_TRIG_POS); + + return 0; +} |