diff options
Diffstat (limited to 'roms/u-boot/arch/x86/cpu/braswell')
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/braswell/Kconfig | 33 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/braswell/Makefile | 5 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/braswell/braswell.c | 30 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/braswell/early_uart.c | 81 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/braswell/fsp_configs.c | 165 |
5 files changed, 314 insertions, 0 deletions
diff --git a/roms/u-boot/arch/x86/cpu/braswell/Kconfig b/roms/u-boot/arch/x86/cpu/braswell/Kconfig new file mode 100644 index 000000000..2676fe6e1 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/braswell/Kconfig @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + +config INTEL_BRASWELL + bool + select HAVE_FSP + select ARCH_MISC_INIT + select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED + imply HAVE_INTEL_ME + imply HAVE_VBT + imply ENABLE_MRC_CACHE + imply AHCI_PCI + imply ICH_SPI + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply SCSI + imply SCSI_AHCI + imply SPI_FLASH + imply SYS_NS16550 + imply USB + imply USB_XHCI_HCD + imply VIDEO_FSP + +if INTEL_BRASWELL + +config FSP_ADDR + hex + default 0xfff20000 + +endif diff --git a/roms/u-boot/arch/x86/cpu/braswell/Makefile b/roms/u-boot/arch/x86/cpu/braswell/Makefile new file mode 100644 index 000000000..277f81e6d --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/braswell/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + +obj-y += braswell.o early_uart.o fsp_configs.o diff --git a/roms/u-boot/arch/x86/cpu/braswell/braswell.c b/roms/u-boot/arch/x86/cpu/braswell/braswell.c new file mode 100644 index 000000000..334504999 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/braswell/braswell.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/mrccache.h> +#include <asm/post.h> + +int arch_cpu_init(void) +{ + post_code(POST_CPU_INIT); + + return x86_cpu_init_f(); +} + +int arch_misc_init(void) +{ +#ifdef CONFIG_ENABLE_MRC_CACHE + /* + * We intend not to check any return value here, as even MRC cache + * is not saved successfully, it is not a severe error that will + * prevent system from continuing to boot. + */ + mrccache_save(); +#endif + + return 0; +} diff --git a/roms/u-boot/arch/x86/cpu/braswell/early_uart.c b/roms/u-boot/arch/x86/cpu/braswell/early_uart.c new file mode 100644 index 000000000..d78c6b0fe --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/braswell/early_uart.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <asm/io.h> + +#define PCI_DEV_CONFIG(segbus, dev, fn) ( \ + (((segbus) & 0xfff) << 20) | \ + (((dev) & 0x1f) << 15) | \ + (((fn) & 0x07) << 12)) + +/* Platform Controller Unit */ +#define LPC_DEV 0x1f +#define LPC_FUNC 0 + +/* Enable UART */ +#define UART_CONT 0x80 + +/* UART PAD definitions */ +#define UART_RXD_COMMUITY 1 +#define UART_TXD_COMMUITY 1 +#define UART_RXD_FAMILY 4 +#define UART_TXD_FAMILY 4 +#define UART_RXD_PAD 2 +#define UART_TXD_PAD 7 +#define UART_RXD_FUNC 3 +#define UART_TXD_FUNC 3 + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed80000 + +static inline uint32_t gpio_pconf0(int community, int family, int pad) +{ + return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 + + family * 0x400 + pad * 8; +} + +static void gpio_select_func(int community, int family, int pad, int func) +{ + uint32_t pconf0_addr = gpio_pconf0(community, family, pad); + + clrsetbits_le32(pconf0_addr, 0xf << 16, func << 16); +} + +static void x86_pci_write_config32(int dev, unsigned int where, u32 value) +{ + unsigned long addr; + + addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3); + writel(value, addr); +} + +/* This can be called after memory-mapped PCI is working */ +int setup_internal_uart(int enable) +{ + /* Enable or disable the legacy UART hardware */ + x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, + enable); + + /* All done for the disable part, so just return */ + if (!enable) + return 0; + + /* + * Set up the pads to the UART function. This allows the signals to + * leave the chip + */ + gpio_select_func(UART_RXD_COMMUITY, UART_RXD_FAMILY, + UART_RXD_PAD, UART_RXD_FUNC); + gpio_select_func(UART_TXD_COMMUITY, UART_TXD_FAMILY, + UART_TXD_PAD, UART_TXD_FUNC); + + return 0; +} + +void board_debug_uart_init(void) +{ + setup_internal_uart(1); +} diff --git a/roms/u-boot/arch/x86/cpu/braswell/fsp_configs.c b/roms/u-boot/arch/x86/cpu/braswell/fsp_configs.c new file mode 100644 index 000000000..243298fd5 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/braswell/fsp_configs.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <fdtdec.h> +#include <log.h> +#include <asm/fsp1/fsp_support.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * Override the FSP's Azalia configuration data + * + * @azalia: pointer to be updated to point to a ROM address where Azalia + * configuration data is stored + */ +__weak void update_fsp_azalia_configs(struct azalia_config **azalia) +{ + *azalia = NULL; +} + +/** + * Override the FSP's GPIO configuration data + * + * @family: pointer to be updated to point to a ROM address where GPIO + * family configuration data is stored + * @pad: pointer to be updated to point to a ROM address where GPIO + * pad configuration data is stored + */ +__weak void update_fsp_gpio_configs(struct gpio_family **family, + struct gpio_pad **pad) +{ + *family = NULL; + *pad = NULL; +} + +/** + * Override the FSP's configuration data. + * If the device tree does not specify an integer setting, use the default + * provided in Intel's Braswell release FSP/BraswellFsp.bsf file. + */ +void fsp_update_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) +{ + struct upd_region *fsp_upd = &config->fsp_upd; + struct memory_upd *memory_upd = &fsp_upd->memory_upd; + struct silicon_upd *silicon_upd = &fsp_upd->silicon_upd; + const void *blob = gd->fdt_blob; + int node; + + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; + + node = fdt_node_offset_by_compatible(blob, 0, "intel,braswell-fsp"); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + node = fdt_node_offset_by_compatible(blob, node, + "intel,braswell-fsp-memory"); + if (node < 0) { + debug("%s: Cannot find FSP memory node\n", __func__); + return; + } + + /* Override memory UPD contents */ + memory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-tseg-size", MRC_INIT_TSEG_SIZE_4MB); + memory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-mmio-size", MRC_INIT_MMIO_SIZE_2048MB); + memory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr1", 0xa0); + memory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr2", 0xa2); + memory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node, + "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_32MB); + memory_upd->aperture_size = fdtdec_get_int(blob, node, + "fsp,aperture-size", APERTURE_SIZE_256MB); + memory_upd->gtt_size = fdtdec_get_int(blob, node, + "fsp,gtt-size", GTT_SIZE_1MB); + memory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node, + "fsp,legacy-seg-decode"); + memory_upd->enable_dvfs = fdtdec_get_bool(blob, node, + "fsp,enable-dvfs"); + memory_upd->memory_type = fdtdec_get_int(blob, node, + "fsp,memory-type", DRAM_TYPE_DDR3); + memory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node, + "fsp,enable-ca-mirror"); + + node = fdt_node_offset_by_compatible(blob, node, + "intel,braswell-fsp-silicon"); + if (node < 0) { + debug("%s: Cannot find FSP silicon node\n", __func__); + return; + } + + /* Override silicon UPD contents */ + silicon_upd->sdcard_mode = fdtdec_get_int(blob, node, + "fsp,sdcard-mode", SDCARD_MODE_PCI); + silicon_upd->enable_hsuart0 = fdtdec_get_bool(blob, node, + "fsp,enable-hsuart0"); + silicon_upd->enable_hsuart1 = fdtdec_get_bool(blob, node, + "fsp,enable-hsuart1"); + silicon_upd->enable_azalia = fdtdec_get_bool(blob, node, + "fsp,enable-azalia"); + if (silicon_upd->enable_azalia) + update_fsp_azalia_configs(&silicon_upd->azalia_cfg_ptr); + silicon_upd->enable_sata = fdtdec_get_bool(blob, node, + "fsp,enable-sata"); + silicon_upd->enable_xhci = fdtdec_get_bool(blob, node, + "fsp,enable-xhci"); + silicon_upd->lpe_mode = fdtdec_get_int(blob, node, + "fsp,lpe-mode", LPE_MODE_PCI); + silicon_upd->enable_dma0 = fdtdec_get_bool(blob, node, + "fsp,enable-dma0"); + silicon_upd->enable_dma1 = fdtdec_get_bool(blob, node, + "fsp,enable-dma1"); + silicon_upd->enable_i2c0 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c0"); + silicon_upd->enable_i2c1 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c1"); + silicon_upd->enable_i2c2 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c2"); + silicon_upd->enable_i2c3 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c3"); + silicon_upd->enable_i2c4 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c4"); + silicon_upd->enable_i2c5 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c5"); + silicon_upd->enable_i2c6 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c6"); +#ifdef CONFIG_HAVE_VBT + silicon_upd->graphics_config_ptr = CONFIG_VBT_ADDR; +#endif + update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr, + &silicon_upd->gpio_pad_ptr); + /* + * For Braswell B0 stepping, disable_punit_pwr_config must be set to 1 + * otherwise it just hangs in fsp_init(). + */ + if (gd->arch.x86_mask == 2) + silicon_upd->disable_punit_pwr_config = 1; + silicon_upd->emmc_mode = fdtdec_get_int(blob, node, + "fsp,emmc-mode", EMMC_MODE_PCI); + silicon_upd->sata_speed = fdtdec_get_int(blob, node, + "fsp,sata-speed", SATA_SPEED_GEN3); + silicon_upd->pmic_i2c_bus = fdtdec_get_int(blob, node, + "fsp,pmic-i2c-bus", 0); + silicon_upd->enable_isp = fdtdec_get_bool(blob, node, + "fsp,enable-isp"); + silicon_upd->isp_pci_dev_config = fdtdec_get_int(blob, node, + "fsp,isp-pci-dev-config", ISP_PCI_DEV_CONFIG_2); + silicon_upd->turbo_mode = fdtdec_get_bool(blob, node, + "fsp,turbo-mode"); + silicon_upd->pnp_settings = fdtdec_get_int(blob, node, + "fsp,pnp-settings", PNP_SETTING_POWER_AND_PERF); + silicon_upd->sd_detect_chk = fdtdec_get_bool(blob, node, + "fsp,sd-detect-chk"); +} |