diff options
Diffstat (limited to 'roms/u-boot/arch/x86/cpu/coreboot')
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/coreboot/Kconfig | 30 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/coreboot/Makefile | 23 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/coreboot/car.S | 12 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/coreboot/coreboot.c | 87 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/coreboot/coreboot_spl.c | 12 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/coreboot/sdram.c | 103 | ||||
| -rw-r--r-- | roms/u-boot/arch/x86/cpu/coreboot/timestamp.c | 74 |
7 files changed, 341 insertions, 0 deletions
diff --git a/roms/u-boot/arch/x86/cpu/coreboot/Kconfig b/roms/u-boot/arch/x86/cpu/coreboot/Kconfig new file mode 100644 index 000000000..497d6284a --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/coreboot/Kconfig @@ -0,0 +1,30 @@ +if TARGET_COREBOOT + +config SYS_COREBOOT + bool + default y + imply SYS_NS16550 + imply SCSI + imply SCSI_AHCI + imply AHCI_PCI + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply USB + imply USB_EHCI_HCD + imply USB_XHCI_HCD + imply USB_STORAGE + imply USB_KEYBOARD + imply VIDEO_COREBOOT + imply E1000 + imply ETH_DESIGNWARE + imply PCH_GBE + imply RTL8169 + imply CMD_CBFS + imply FS_CBFS + imply CBMEM_CONSOLE + imply X86_TSC_READ_BASE + select BINMAN if X86_64 + +endif diff --git a/roms/u-boot/arch/x86/cpu/coreboot/Makefile b/roms/u-boot/arch/x86/cpu/coreboot/Makefile new file mode 100644 index 000000000..a6cdb9a14 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/coreboot/Makefile @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2011 The Chromium OS Authors. +# +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + +ifndef CONFIG_SPL +obj-y += car.o +endif +ifdef CONFIG_SPL_BUILD +obj-y += coreboot_spl.o +else +obj-y += sdram.o +endif +obj-y += coreboot.o +obj-y += timestamp.o diff --git a/roms/u-boot/arch/x86/cpu/coreboot/car.S b/roms/u-boot/arch/x86/cpu/coreboot/car.S new file mode 100644 index 000000000..7163b69a4 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/coreboot/car.S @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010-2011 + * Graeme Russ, <graeme.russ@gmail.com> + */ + +.section .text + +.globl car_init +car_init: + jmp car_init_ret diff --git a/roms/u-boot/arch/x86/cpu/coreboot/coreboot.c b/roms/u-boot/arch/x86/cpu/coreboot/coreboot.c new file mode 100644 index 000000000..69cf8f417 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/coreboot/coreboot.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + */ + +#include <common.h> +#include <cpu_func.h> +#include <fdtdec.h> +#include <init.h> +#include <usb.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/msr.h> +#include <asm/mtrr.h> +#include <asm/cb_sysinfo.h> +#include <asm/arch/timestamp.h> + +DECLARE_GLOBAL_DATA_PTR; + +int arch_cpu_init(void) +{ + int ret = get_coreboot_info(&lib_sysinfo); + if (ret != 0) { + printf("Failed to parse coreboot tables.\n"); + return ret; + } + + timestamp_init(); + + return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() : + x86_cpu_init_f(); +} + +int checkcpu(void) +{ + return 0; +} + +int print_cpuinfo(void) +{ + return default_print_cpuinfo(); +} + +static void board_final_init(void) +{ + /* + * Un-cache the ROM so the kernel has one + * more MTRR available. + * + * Coreboot should have assigned this to the + * top available variable MTRR. + */ + u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1; + u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff; + + /* Make sure this MTRR is the correct Write-Protected type */ + if (top_type == MTRR_TYPE_WRPROT) { + struct mtrr_state state; + + mtrr_open(&state, true); + wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0); + wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0); + mtrr_close(&state, true); + } + + if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) { + /* + * Issue SMI to coreboot to lock down ME and registers + * when allowed via device tree + */ + printf("Finalizing coreboot\n"); + outb(0xcb, 0xb2); + } +} + +int last_stage_init(void) +{ + /* start usb so that usb keyboard can be used as input device */ + if (CONFIG_IS_ENABLED(USB_KEYBOARD)) + usb_init(); + + board_final_init(); + + return 0; +} diff --git a/roms/u-boot/arch/x86/cpu/coreboot/coreboot_spl.c b/roms/u-boot/arch/x86/cpu/coreboot/coreboot_spl.c new file mode 100644 index 000000000..36661871e --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/coreboot/coreboot_spl.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Google LLC + */ + +#include <common.h> +#include <init.h> + +int dram_init(void) +{ + return 0; +} diff --git a/roms/u-boot/arch/x86/cpu/coreboot/sdram.c b/roms/u-boot/arch/x86/cpu/coreboot/sdram.c new file mode 100644 index 000000000..4a256bad4 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/coreboot/sdram.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 + * Graeme Russ, <graeme.russ@gmail.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/e820.h> +#include <asm/cb_sysinfo.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int install_e820_map(unsigned int max_entries, + struct e820_entry *entries) +{ + return cb_install_e820_map(max_entries, entries); +} + +/* + * This function looks for the highest region of memory lower than 4GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. It + * overrides the default implementation found elsewhere which simply picks the + * end of ram, wherever that may be. The location of the stack, the relocation + * address, and how far U-Boot is moved by relocation are set in the global + * data structure. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + uintptr_t dest_addr = 0; + int i; + + for (i = 0; i < lib_sysinfo.n_memranges; i++) { + struct memrange *memrange = &lib_sysinfo.memrange[i]; + /* Force U-Boot to relocate to a page aligned address. */ + uint64_t start = roundup(memrange->base, 1 << 12); + uint64_t end = memrange->base + memrange->size; + + /* Ignore non-memory regions. */ + if (memrange->type != CB_MEM_RAM) + continue; + + /* Filter memory over 4GB. */ + if (end > 0xffffffffULL) + end = 0x100000000ULL; + /* Skip this region if it's too small. */ + if (end - start < total_size) + continue; + + /* Use this address if it's the largest so far. */ + if (end > dest_addr) + dest_addr = end; + } + + /* If no suitable area was found, return an error. */ + if (!dest_addr) + panic("No available memory found for relocation"); + + return (ulong)dest_addr; +} + +int dram_init(void) +{ + int i; + phys_size_t ram_size = 0; + + for (i = 0; i < lib_sysinfo.n_memranges; i++) { + struct memrange *memrange = &lib_sysinfo.memrange[i]; + unsigned long long end = memrange->base + memrange->size; + + if (memrange->type == CB_MEM_RAM && end > ram_size) + ram_size += memrange->size; + } + + gd->ram_size = ram_size; + if (ram_size == 0) + return -1; + + return 0; +} + +int dram_init_banksize(void) +{ + int i, j; + + if (CONFIG_NR_DRAM_BANKS) { + for (i = 0, j = 0; i < lib_sysinfo.n_memranges; i++) { + struct memrange *memrange = &lib_sysinfo.memrange[i]; + + if (memrange->type == CB_MEM_RAM) { + gd->bd->bi_dram[j].start = memrange->base; + gd->bd->bi_dram[j].size = memrange->size; + j++; + if (j >= CONFIG_NR_DRAM_BANKS) + break; + } + } + } + + return 0; +} diff --git a/roms/u-boot/arch/x86/cpu/coreboot/timestamp.c b/roms/u-boot/arch/x86/cpu/coreboot/timestamp.c new file mode 100644 index 000000000..3ad611a53 --- /dev/null +++ b/roms/u-boot/arch/x86/cpu/coreboot/timestamp.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * Modified from the coreboot version + */ + +#include <common.h> +#include <bootstage.h> +#include <asm/arch/timestamp.h> +#include <asm/cb_sysinfo.h> +#include <linux/compiler.h> + +static struct timestamp_table *ts_table __section(".data"); + +void timestamp_init(void) +{ + timestamp_add_now(TS_U_BOOT_INITTED); +} + +void timestamp_add(enum timestamp_id id, uint64_t ts_time) +{ + struct timestamp_entry *tse; + + if (!ts_table || (ts_table->num_entries == ts_table->max_entries)) + return; + + tse = &ts_table->entries[ts_table->num_entries++]; + tse->entry_id = id; + tse->entry_stamp = ts_time - ts_table->base_time; +} + +void timestamp_add_now(enum timestamp_id id) +{ + timestamp_add(id, rdtsc()); +} + +int timestamp_add_to_bootstage(void) +{ + uint i; + + if (!ts_table) + return -1; + + for (i = 0; i < ts_table->num_entries; i++) { + struct timestamp_entry *tse = &ts_table->entries[i]; + const char *name = NULL; + + switch (tse->entry_id) { + case TS_START_ROMSTAGE: + name = "start-romstage"; + break; + case TS_BEFORE_INITRAM: + name = "before-initram"; + break; + case TS_DEVICE_INITIALIZE: + name = "device-initialize"; + break; + case TS_DEVICE_DONE: + name = "device-done"; + break; + case TS_SELFBOOT_JUMP: + name = "selfboot-jump"; + break; + } + if (name) { + bootstage_add_record(0, name, BOOTSTAGEF_ALLOC, + tse->entry_stamp / + get_tbclk_mhz()); + } + } + + return 0; +} |