diff options
Diffstat (limited to 'roms/u-boot/board/engicam/imx8mm/icore_mx8mm.c')
-rw-r--r-- | roms/u-boot/board/engicam/imx8mm/icore_mx8mm.c | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/roms/u-boot/board/engicam/imx8mm/icore_mx8mm.c b/roms/u-boot/board/engicam/imx8mm/icore_mx8mm.c new file mode 100644 index 000000000..4f7c699d7 --- /dev/null +++ b/roms/u-boot/board/engicam/imx8mm/icore_mx8mm.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#include <common.h> +#include <miiphy.h> +#include <netdev.h> + +#include <asm/io.h> +#include <asm-generic/gpio.h> + +#include <linux/delay.h> + +#include <asm/arch/clock.h> +#include <asm/arch/imx8mm_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/iomux-v3.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if IS_ENABLED(CONFIG_FEC_MXC) + +#define FEC_RST_PAD IMX_GPIO_NR(3, 7) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(FEC_RST_PAD, "fec1_rst"); + gpio_direction_output(FEC_RST_PAD, 0); + udelay(500); + gpio_direction_output(FEC_RST_PAD, 1); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 13, 0); + + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} |