diff options
Diffstat (limited to 'roms/u-boot/board/freescale/ls1012afrdm')
-rw-r--r-- | roms/u-boot/board/freescale/ls1012afrdm/Kconfig | 95 | ||||
-rw-r--r-- | roms/u-boot/board/freescale/ls1012afrdm/MAINTAINERS | 17 | ||||
-rw-r--r-- | roms/u-boot/board/freescale/ls1012afrdm/Makefile | 8 | ||||
-rw-r--r-- | roms/u-boot/board/freescale/ls1012afrdm/README | 58 | ||||
-rw-r--r-- | roms/u-boot/board/freescale/ls1012afrdm/eth.c | 125 | ||||
-rw-r--r-- | roms/u-boot/board/freescale/ls1012afrdm/ls1012afrdm.c | 203 |
6 files changed, 506 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/ls1012afrdm/Kconfig b/roms/u-boot/board/freescale/ls1012afrdm/Kconfig new file mode 100644 index 000000000..4ac69d711 --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012afrdm/Kconfig @@ -0,0 +1,95 @@ +if TARGET_LS1012AFRDM + +config SYS_BOARD + default "ls1012afrdm" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012afrdm" + +config SYS_LS_PFE_FW_ADDR + hex "Flash address of PFE firmware" + default 0x40a00000 + +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x40000 + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40400000 +endif + +if FSL_PFE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select PHYLIB + imply PHY_REALTEK + imply PHY_ATHEROS + +config DDR_PFE_PHYS_BASEADDR + hex "PFE DDR physical base address" + default 0x03800000 + +config DDR_PFE_BASEADDR + hex "PFE DDR base address" + default 0x83800000 + +config PFE_EMAC1_PHY_ADDR + hex "PFE DDR base address" + default 0x2 + +config PFE_EMAC2_PHY_ADDR + hex "PFE DDR base address" + default 0x1 + +endif + +if TARGET_LS1012AFRWY + +config SYS_BOARD + default "ls1012afrdm" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012afrwy" + +config SYS_LS_PFE_FW_ADDR + hex "Flash address of PFE firmware" + default 0x40020000 + +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x40000 + +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x40060000 + +config SYS_LS_PPA_ESBC_ADDR + hex "PPA Firmware HDR Addr" + default 0x401f4000 + +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x401f8000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 +endif + +if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY +source "board/freescale/common/Kconfig" +endif diff --git a/roms/u-boot/board/freescale/ls1012afrdm/MAINTAINERS b/roms/u-boot/board/freescale/ls1012afrdm/MAINTAINERS new file mode 100644 index 000000000..5fc7e9385 --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012afrdm/MAINTAINERS @@ -0,0 +1,17 @@ +LS1012AFRDM BOARD +M: Rajesh Bhagat <rajesh.bhagat@nxp.com> +S: Maintained +F: board/freescale/ls1012afrdm/ +F: include/configs/ls1012afrdm.h +F: configs/ls1012afrdm_qspi_defconfig +F: configs/ls1012afrdm_tfa_defconfig +F: configs/ls1012afrwy_tfa_defconfig +F: configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig + +LS1012AFRWY BOARD +M: Pramod Kumar <pramod.kumar_1@nxp.com> +S: Maintained +F: board/freescale/ls1012afrwy/ +F: include/configs/ls1012afrwy.h +F: configs/ls1012afrwy_qspi_defconfig +F: configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig diff --git a/roms/u-boot/board/freescale/ls1012afrdm/Makefile b/roms/u-boot/board/freescale/ls1012afrdm/Makefile new file mode 100644 index 000000000..1e53c9673 --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012afrdm/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012afrdm.o +obj-$(CONFIG_FSL_PFE) += eth.o diff --git a/roms/u-boot/board/freescale/ls1012afrdm/README b/roms/u-boot/board/freescale/ls1012afrdm/README new file mode 100644 index 000000000..181c4615a --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012afrdm/README @@ -0,0 +1,58 @@ +Overview +-------- +QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development +platform, with a complete debugging environment. The LS1012AFRDM board +supports the QorIQ LS1012A processor and is optimized to support the +high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + + LS1012AFRDM board Overview + ----------------------- + - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s + - 2 SGMII 1G PHYs + - DDR Controller + - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s + operating at 1.35 V + - QSPI + - Onboard 512 Mbit QSPI flash memory running at speed up + to 108/54 MHz + - One high-speed USB 2.0/3.0 port, one USB 2.0 port + - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a + Micro-AB connector. + - USB 2.0 port is a debug port (CMSIS DAP) and is configured + as a Micro-AB device. + - I2C controller + - One I2C bus with connectivity to Arduino headers + - UART + - UART (Console): UART1 (Without flow control) for console + - ARM JTAG support + - ARM Cortex® 10-pin JTAG connector for LS1012A + - CMSIS DAP through K20 microcontroller + - SAI Audio interface + - One SAI port, SAI 2 with full duplex support + - Clocks + - 25 MHz crystal for LS1012A + - 8 MHz Crystal for K20 + - 24 MHz for SC16IS740IPW SPI to Dual UART bridge + - Power Supplies + - 5 V input supply from USB + - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and + other board interfaces + +Booting Options +--------------- +QSPI Flash 1 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/roms/u-boot/board/freescale/ls1012afrdm/eth.c b/roms/u-boot/board/freescale/ls1012afrdm/eth.c new file mode 100644 index 000000000..d2df9351e --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012afrdm/eth.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#include <common.h> +#include <dm.h> +#include <net.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <asm/types.h> +#include <fsl_dtsec.h> +#include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/config.h> +#include <asm/arch-fsl-layerscape/immap_lsch2.h> +#include <asm/arch/fsl_serdes.h> +#include <linux/delay.h> +#include <net/pfe_eth/pfe_eth.h> +#include <dm/platform_data/pfe_dm_eth.h> + +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" +#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" + +#define MASK_ETH_PHY_RST 0x00000100 + +static inline void ls1012afrdm_reset_phy(void) +{ + unsigned int val; + struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR); + + setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST); + + val = in_be32(&pgpio->gpdat); + setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST); + mdelay(10); + + val = in_be32(&pgpio->gpdat); + setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST); + mdelay(50); +} + +int pfe_eth_board_init(struct udevice *dev) +{ + static int init_done; + struct mii_dev *bus; + struct pfe_mdio_info mac_mdio_info; + struct pfe_eth_dev *priv = dev_get_priv(dev); + + if (!init_done) { + ls1012afrdm_reset_phy(); + + mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; + mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; + + bus = pfe_mdio_init(&mac_mdio_info); + if (!bus) { + printf("Failed to register mdio\n"); + return -1; + } + + init_done = 1; + } + + if (priv->gemac_port) { + mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; + mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; + bus = pfe_mdio_init(&mac_mdio_info); + if (!bus) { + printf("Failed to register mdio\n"); + return -1; + } + } + + pfe_set_mdio(priv->gemac_port, + miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + if (!priv->gemac_port) + /* MAC1 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII); + else + /* MAC2 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII); + return 0; +} + +static struct pfe_eth_pdata pfe_pdata0 = { + .pfe_eth_pdata_mac = { + .iobase = (phys_addr_t)EMAC1_BASE_ADDR, + .phy_interface = 0, + }, + + .pfe_ddr_addr = { + .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, + .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, + }, +}; + +static struct pfe_eth_pdata pfe_pdata1 = { + .pfe_eth_pdata_mac = { + .iobase = (phys_addr_t)EMAC2_BASE_ADDR, + .phy_interface = 1, + }, + + .pfe_ddr_addr = { + .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, + .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, + }, +}; + +U_BOOT_DRVINFO(ls1012a_pfe0) = { + .name = "pfe_eth", + .plat = &pfe_pdata0, +}; + +U_BOOT_DRVINFO(ls1012a_pfe1) = { + .name = "pfe_eth", + .plat = &pfe_pdata1, +}; diff --git a/roms/u-boot/board/freescale/ls1012afrdm/ls1012afrdm.c b/roms/u-boot/board/freescale/ls1012afrdm/ls1012afrdm.c new file mode 100644 index 000000000..6473ee057 --- /dev/null +++ b/roms/u-boot/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ + +#include <common.h> +#include <fdt_support.h> +#include <i2c.h> +#include <asm/cache.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif +#include <asm/arch/mmu.h> +#include <asm/arch/soc.h> +#include <fsl_esdhc.h> +#include <hwconfig.h> +#include <env_internal.h> +#include <fsl_mmdc.h> +#include <netdev.h> +#include <fsl_sec.h> +#include <net/pfe_eth/pfe/pfe_hw.h> + +DECLARE_GLOBAL_DATA_PTR; + +static inline int get_board_version(void) +{ + uint32_t val; +#ifdef CONFIG_TARGET_LS1012AFRDM + val = 0; +#else + struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); + + val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/ + +#endif + return val; +} + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_LS1012AFRDM + puts("Board: LS1012AFRDM "); +#else + int rev; + + rev = get_board_version(); + + puts("Board: FRWY-LS1012A "); + + puts("Version"); + + switch (rev) { + case BOARD_REV_A_B: + puts(": RevA/B "); + break; + case BOARD_REV_C: + puts(": RevC "); + break; + default: + puts(": unknown"); + break; + } +#endif + + return 0; +} + +#ifdef CONFIG_TARGET_LS1012AFRWY +int esdhc_status_fixup(void *blob, const char *compat) +{ + char esdhc0_path[] = "/soc/esdhc@1560000"; + char esdhc1_path[] = "/soc/esdhc@1580000"; + + do_fixup_by_path(blob, esdhc0_path, "status", "okay", + sizeof("okay"), 1); + + do_fixup_by_path(blob, esdhc1_path, "status", "disabled", + sizeof("disabled"), 1); + return 0; +} +#endif + +#ifdef CONFIG_TFABOOT +int dram_init(void) +{ +#ifdef CONFIG_TARGET_LS1012AFRWY + int board_rev; +#endif + + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) { +#ifdef CONFIG_TARGET_LS1012AFRWY + board_rev = get_board_version(); + + if (board_rev & BOARD_REV_C) + gd->ram_size = SYS_SDRAM_SIZE_1024; + else + gd->ram_size = SYS_SDRAM_SIZE_512; +#else + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#endif + } + return 0; +} +#else +int dram_init(void) +{ +#ifdef CONFIG_TARGET_LS1012AFRWY + int board_rev; +#endif + struct fsl_mmdc_info mparam = { + 0x04180000, /* mdctl */ + 0x00030035, /* mdpdc */ + 0x12554000, /* mdotc */ + 0xbabf7954, /* mdcfg0 */ + 0xdb328f64, /* mdcfg1 */ + 0x01ff00db, /* mdcfg2 */ + 0x00001680, /* mdmisc */ + 0x0f3c8000, /* mdref */ + 0x00002000, /* mdrwd */ + 0x00bf1023, /* mdor */ + 0x0000003f, /* mdasp */ + 0x0000022a, /* mpodtctrl */ + 0xa1390003, /* mpzqhwctrl */ + }; + +#ifdef CONFIG_TARGET_LS1012AFRWY + board_rev = get_board_version(); + + if (board_rev == BOARD_REV_C) { + mparam.mdctl = 0x05180000; + gd->ram_size = SYS_SDRAM_SIZE_1024; + } else { + gd->ram_size = SYS_SDRAM_SIZE_512; + } +#else + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#endif + mmdc_init(&mparam); + +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; +} +#endif + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + if (current_el() == 3) + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + return 0; +} + +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} |