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-rw-r--r--roms/u-boot/board/freescale/t208xrdb/Kconfig18
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/MAINTAINERS19
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/Makefile16
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/README288
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/cpld.c70
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/cpld.h44
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/ddr.c119
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/ddr.h46
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c101
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/law.c33
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/pci.c25
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/spl.c111
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/t2080_nand_rcw.cfg19
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg40
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/t2080_sd_rcw.cfg19
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/t2080_spi_rcw.cfg19
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/t208xrdb.c160
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/t208xrdb.h15
-rw-r--r--roms/u-boot/board/freescale/t208xrdb/tlb.c152
19 files changed, 1314 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/t208xrdb/Kconfig b/roms/u-boot/board/freescale/t208xrdb/Kconfig
new file mode 100644
index 000000000..8249c5df9
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_T2080RDB
+
+config SYS_BOARD
+ default "t208xrdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T208xRDB"
+
+config T2080RDB_REV_D
+ bool "Support for T2080RDB revisions D and up"
+ default n
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/roms/u-boot/board/freescale/t208xrdb/MAINTAINERS b/roms/u-boot/board/freescale/t208xrdb/MAINTAINERS
new file mode 100644
index 000000000..6e9b25fa0
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/MAINTAINERS
@@ -0,0 +1,19 @@
+T208XRDB BOARD
+M: Shengzhou Liu <Shengzhou.Liu@nxp.com>
+S: Maintained
+F: board/freescale/t208xrdb/
+F: include/configs/T208xRDB.h
+F: configs/T2080RDB_defconfig
+F: configs/T2080RDB_NAND_defconfig
+F: configs/T2080RDB_SDCARD_defconfig
+F: configs/T2080RDB_SPIFLASH_defconfig
+F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+F: configs/T2080RDB_revD_defconfig
+F: configs/T2080RDB_revD_NAND_defconfig
+F: configs/T2080RDB_revD_SDCARD_defconfig
+F: configs/T2080RDB_revD_SPIFLASH_defconfig
+
+T2080RDB_SECURE_BOOT BOARD
+M: Ruchika Gupta <ruchika.gupta@nxp.com>
+S: Maintained
+F: configs/T2080RDB_SECURE_BOOT_defconfig
diff --git a/roms/u-boot/board/freescale/t208xrdb/Makefile b/roms/u-boot/board/freescale/t208xrdb/Makefile
new file mode 100644
index 000000000..25ea66a02
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
+obj-$(CONFIG_PCI) += pci.o
+endif
+
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/roms/u-boot/board/freescale/t208xrdb/README b/roms/u-boot/board/freescale/t208xrdb/README
new file mode 100644
index 000000000..ec47c96f2
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/README
@@ -0,0 +1,288 @@
+T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
+It can work in two mode: standalone mode and PCIe endpoint mode.
+
+T2080 SoC Overview
+------------------
+The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
+Architecture processor cores with high-performance datapath acceleration
+logic and network and peripheral bus interfaces required for networking,
+telecom/datacom, wireless infrastructure, and mil/aerospace applications.
+
+T2080 includes the following functions and features:
+ - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
+ - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
+ - Hierarchical interconnect fabric
+ - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ - 16 SerDes lanes up to 10.3125 GHz
+ - 8 Ethernet interfaces, supporting combinations of the following:
+ - Up to four 10 Gbps Ethernet MACs
+ - Up to eight 1 Gbps Ethernet MACs
+ - Up to four 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+ - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 2.0) controllers
+ - Two high-speed USB 2.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
+ - Enhanced serial peripheral interface (eSPI)
+ - Four I2C controllers
+ - Four 2-pin UARTs or two 4-pin UARTs
+ - Integrated Flash Controller supporting NAND and NOR flash
+ - Three eight-channel DMA engines
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ Platform's Trust Architecture 2.0
+
+User Guide
+----------
+The T2080RDB User Guide is available on the web at
+https://www.nxp.com/docs/en/user-guide/T2080RDBPCUG.pdf
+
+Differences between T2080 and T2081
+-----------------------------------
+ Feature T2080 T2081
+ 1G Ethernet numbers: 8 6
+ 10G Ethernet numbers: 4 2
+ SerDes lanes: 16 8
+ Serial RapidIO,RMan: 2 no
+ SATA Controller: 2 no
+ Aurora: yes no
+ SoC Package: 896-pins 780-pins
+
+
+T2080PCIe-RDB board Overview
+----------------------------
+ - SERDES Configuration
+ - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
+ - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
+ - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
+ - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
+ - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
+ - SerDes-2 Lane G-H: to SATA1 & SATA2
+ - Ethernet
+ - Two on-board 10M/100M/1G RGMII ethernet ports
+ - Two on-board 10Gbps XFI fiber ports
+ - Two on-board 10Gbps Base-T copper ports
+ - DDR Memory
+ - Supports 72bit 4GB DDR3-LP SODIMM
+ - PCIe
+ - One PCIe x4 gold-finger
+ - One PCIe x4 connector
+ - One PCIe x2 end-point device (C293 Crypto co-processor)
+ - IFC/Local Bus
+ - NOR: 128MB 16-bit NOR Flash
+ - NAND: 1GB 8-bit NAND flash
+ - CPLD: for system controlling with programable header on-board
+ - SATA
+ - Two SATA 2.0 onnectors on-board
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - one TF-card connector on-board
+ - SPI
+ - On-board 64MB SPI flash
+ - Other
+ - Two Serial ports
+ - Four I2C ports
+
+
+System Memory map
+-----------------
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
+0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
+0x0_0000_0000 0x0_ffff_ffff DDR 4GB
+
+
+128M NOR Flash memory Map
+-------------------------
+Start Address End Address Definition Max size
+0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+T2080PCIe-RDB Ethernet Port Map
+-------------------------------
+Label In Uboot In Linux FMan Address Comments PHY
+ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
+ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
+ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
+ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
+ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E)
+ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E)
+
+
+T2080PCIe-RDB Default DIP-Switch setting
+----------------------------------------
+SW1[1:8] = '00010011'
+SW2[1:8] = '10111111'
+SW3[1:8] = '11100001'
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+ a. build NOR boot image
+ $ make T2080RDB_config
+ $ make
+ b. program u-boot.bin image to NOR flash
+ => tftp 1000000 u-boot.bin
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+
+ Switching between default bank and alternate bank on NOR flash
+ To change boot source to vbank4:
+ via software: run command 'cpld reset altbank' in U-Boot.
+ via DIP-switch: set SW3[5:7] = '100'
+
+ To change boot source to vbank0:
+ via software: run command 'cpld reset' in U-Boot.
+ via DIP-Switch: set SW3[5:7] = '000'
+
+2. NAND Boot:
+ a. build PBL image for NAND boot
+ $ make T2080RDB_NAND_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => nand erase 0 d0000
+ => nand write 1000000 0 $filesize
+ set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
+
+3. SPI Boot:
+ a. build PBL image for SPI boot
+ $ make T2080RDB_SPIFLASH_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SPI flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => sf probe 0
+ => sf erase 0 d0000
+ => sf write 1000000 0 $filesize
+ set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+ a. build PBL image for SD boot
+ $ make T2080RDB_SDCARD_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => mmc write 1000000 8 0x800
+ set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to U-Boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (50KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-Boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T2080RDB
+--------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF U-Boot img 1MB (2 blocks)
+0x100000 0x17FFFF U-Boot env 512KB (1 block)
+0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
+0x200000 0x27FFFF CS4315 ucode 512KB (1 block)
+
+
+Micro SD Card memory Map on T2080RDB
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 U-Boot img 1MB
+0x800 0016 U-Boot env 8KB
+0x820 0128 FMAN ucode 64KB
+0x8a0 0512 CS4315 ucode 256KB
+
+
+SPI Flash memory Map on T2080RDB
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF U-Boot img 1MB
+0x100000 0x101FFF U-Boot env 8KB
+0x110000 0x11FFFF FMAN ucode 64KB
+0x120000 0x15FFFF CS4315 ucode 256KB
+
+
+How to update the ucode of Cortina CS4315/CS4340 10G PHY
+--------------------------------------------------------
+=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
+=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
+
+
+How to update the ucode of Freescale FMAN
+-----------------------------------------
+=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
+=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
+
+
+For more details, please refer to T2080PCIe-RDB User Guide and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for t2080rdb for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+ CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/roms/u-boot/board/freescale/t208xrdb/cpld.c b/roms/u-boot/board/freescale/t208xrdb/cpld.c
new file mode 100644
index 000000000..b9ba62adf
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/cpld.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * Freescale T2080RDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+ u8 reg = CPLD_READ(flash_csr);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+ CPLD_WRITE(flash_csr, reg);
+ CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+ u8 reg = CPLD_READ(flash_csr);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+ CPLD_WRITE(flash_csr, reg);
+ CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+ } else {
+ rc = cmd_usage(cmdtp);
+ }
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset: reset to default bank\n"
+ "cpld reset altbank: reset to alternate bank\n"
+);
diff --git a/roms/u-boot/board/freescale/t208xrdb/cpld.h b/roms/u-boot/board/freescale/t208xrdb/cpld.h
new file mode 100644
index 000000000..bd6c20374
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/cpld.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor
+ */
+
+/*
+ * CPLD register set of T2080RDB board-specific.
+ */
+struct cpld_data {
+ u8 chip_id1; /* 0x00 - Chip ID1 register */
+ u8 chip_id2; /* 0x01 - Chip ID2 register */
+ u8 hw_ver; /* 0x02 - Hardware Revision Register */
+ u8 sw_ver; /* 0x03 - Software Revision register */
+ u8 res0[12]; /* 0x04 - 0x0F - not used */
+ u8 reset_ctl; /* 0x10 - Reset control Register */
+ u8 flash_csr; /* 0x11 - Flash control and status register */
+ u8 thermal_csr; /* 0x12 - Thermal control and status register */
+ u8 led_csr; /* 0x13 - LED control and status register */
+ u8 sfp_csr; /* 0x14 - SFP+ control and status register */
+ u8 misc_csr; /* 0x15 - Misc control and status register */
+ u8 boot_or; /* 0x16 - Boot config override register */
+ u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
+ u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
+} cpld_data_t;
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value) \
+ cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK 0x3F
+#define CPLD_BANK_SEL_MASK 0x07
+#define CPLD_BANK_OVERRIDE 0x40
+#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_RESET 0xFF
+#define CPLD_LBMAP_SHIFT 0x03
+#define CPLD_BOOT_SEL 0x80
+
+/* RSTCON Register */
+#define CPLD_RSTCON_EDC_RST 0x04
diff --git a/roms/u-boot/board/freescale/t208xrdb/ddr.c b/roms/u-boot/board/freescale/t208xrdb/ddr.c
new file mode 100644
index 000000000..1fbab36e1
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/ddr.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x54;
+}
+
+int dram_init(void)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ puts("Initializing....using SPD\n");
+ dram_size = fsl_ddr_sdram();
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ gd->ram_size = dram_size;
+
+ return 0;
+}
diff --git a/roms/u-boot/board/freescale/t208xrdb/ddr.h b/roms/u-boot/board/freescale/t208xrdb/ddr.h
new file mode 100644
index 000000000..c00f17816
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/ddr.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+ {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
+ {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
+ {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
+ {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
+ {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
+ {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+#endif
diff --git a/roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c b/roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c
new file mode 100644
index 000000000..e4592eac1
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdt_support.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+
+extern u8 get_hw_revision(void);
+
+/* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two
+ * "fsl,dpa-ethernet" nodes that reference them.
+ */
+void fdt_fixup_board_fman_ethernet(void *fdt)
+{
+ int mac_off, eth_off, i;
+ char mac_path[2][42] = {
+ "/soc@ffe000000/fman@400000/ethernet@e8000",
+ "/soc@ffe000000/fman@400000/ethernet@ea000",
+ };
+ u32 eth_ph;
+
+ for (i = 0; i < 2; i++) {
+ /* Disable the MAC node */
+ mac_off = fdt_path_offset(fdt, mac_path[i]);
+ if (mac_off < 0)
+ continue;
+ fdt_status_disabled(fdt, mac_off);
+
+ /* Disable the fsl,dpa-ethernet node that points to the MAC.
+ * The fsl,fman-mac property refers to the MAC's phandle.
+ */
+ eth_ph = fdt_get_phandle(fdt, mac_off);
+ if (eth_ph <= 0)
+ continue;
+
+ eth_off = fdt_node_offset_by_prop_value(fdt, -1, "fsl,fman-mac",
+ &eth_ph,
+ sizeof(eth_ph));
+ if (eth_off >= 0)
+ fdt_status_disabled(fdt, eth_off);
+ }
+}
+
+/* Update the address of the second Aquantia PHY on boards revision D and up.
+ * Also rename the PHY node to align with the address change.
+ */
+void fdt_fixup_board_phy(void *fdt)
+{
+ const char phy_path[] =
+ "/soc@ffe000000/fman@400000/mdio@fd000/ethernet-phy@1";
+ int ret, offset, new_addr = AQR113C_PHY_ADDR2;
+ char new_name[] = "ethernet-phy@00";
+
+ if (get_hw_revision() == 'C')
+ return;
+
+ offset = fdt_path_offset(fdt, phy_path);
+ if (offset < 0) {
+ printf("ethernet-phy@1 node not found in the dts\n");
+ return;
+ }
+
+ ret = fdt_setprop(fdt, offset, "reg", &new_addr, sizeof(new_addr));
+ if (ret < 0) {
+ printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
+ fdt_strerror(ret));
+ return;
+ }
+
+ sprintf(new_name, "ethernet-phy@%x", new_addr);
+ ret = fdt_set_name(fdt, offset, new_name);
+ if (ret < 0)
+ printf("Unable to rename node ethernet-phy@1: %s\n",
+ fdt_strerror(ret));
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}
diff --git a/roms/u-boot/board/freescale/t208xrdb/law.c b/roms/u-boot/board/freescale/t208xrdb/law.c
new file mode 100644
index 000000000..d3b263f59
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/law.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/roms/u-boot/board/freescale/t208xrdb/pci.c b/roms/u-boot/board/freescale/t208xrdb/pci.c
new file mode 100644
index 000000000..45ab9223a
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/pci.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007-2014 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+#if !defined(CONFIG_DM_PCI)
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, struct bd_info *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/roms/u-boot/board/freescale/t208xrdb/spl.c b/roms/u-boot/board/freescale/t208xrdb/spl.c
new file mode 100644
index 000000000..b0ce9af00
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/spl.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <console.h>
+#include <env_internal.h>
+#include <init.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include <asm/global_data.h>
+#include "../common/spl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ struct bd_info *bd;
+
+ bd = (struct bd_info *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(struct bd_info));
+ gd->bd = bd;
+
+ arch_cpu_init();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)SPL_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)SPL_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)SPL_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(SPL_ENV_ADDR);
+ gd->env_valid = ENV_VALID;
+
+ i2c_init_all();
+
+ dram_init();
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ fsl_spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/roms/u-boot/board/freescale/t208xrdb/t2080_nand_rcw.cfg b/roms/u-boot/board/freescale/t208xrdb/t2080_nand_rcw.cfg
new file mode 100644
index 000000000..8096ff9f3
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t2080_nand_rcw.cfg
@@ -0,0 +1,19 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
+66150002 00000000 e8104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg b/roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg
new file mode 100644
index 000000000..43be8a864
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg
@@ -0,0 +1,40 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+091380c0 00100000
diff --git a/roms/u-boot/board/freescale/t208xrdb/t2080_sd_rcw.cfg b/roms/u-boot/board/freescale/t208xrdb/t2080_sd_rcw.cfg
new file mode 100644
index 000000000..6309b1d22
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t2080_sd_rcw.cfg
@@ -0,0 +1,19 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
+66150002 00000000 68104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xrdb/t2080_spi_rcw.cfg b/roms/u-boot/board/freescale/t208xrdb/t2080_spi_rcw.cfg
new file mode 100644
index 000000000..f16749588
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t2080_spi_rcw.cfg
@@ -0,0 +1,19 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
+66150002 00000000 58104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/roms/u-boot/board/freescale/t208xrdb/t208xrdb.c b/roms/u-boot/board/freescale/t208xrdb/t208xrdb.c
new file mode 100644
index 000000000..1f0cdee0b
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t208xrdb.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <image.h>
+#include <init.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include "t208xrdb.h"
+#include "cpld.h"
+#include "../common/vid.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u8 get_hw_revision(void)
+{
+ u8 ver = CPLD_READ(hw_ver);
+
+ switch (ver) {
+ default:
+ case 0x1:
+ return 'C';
+ case 0x0:
+ return 'D';
+ case 0x2:
+ return 'E';
+ }
+}
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+
+ printf("Board: %sRDB, ", cpu->name);
+ printf("Board rev: %c CPLD ver: 0x%02x, boot from ",
+ get_hw_revision(), CPLD_READ(sw_ver));
+
+#ifdef CONFIG_SDCARD
+ puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+ puts("SPI\n");
+#else
+ u8 reg;
+
+ reg = CPLD_READ(flash_csr);
+
+ if (reg & CPLD_BOOT_SEL) {
+ puts("NAND\n");
+ } else {
+ reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+ printf("NOR vBank%d\n", reg);
+ }
+#endif
+
+ puts("SERDES Reference Clocks:\n");
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+ printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+int misc_init_r(void)
+{
+ u8 reg;
+
+ /* Reset CS4315 PHY */
+ reg = CPLD_READ(reset_ctl);
+ reg |= CPLD_RSTCON_EDC_RST;
+ CPLD_WRITE(reset_ctl, reg);
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = env_get_bootm_low();
+ size = env_get_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fsl_fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_board_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+ fdt_fixup_board_phy(blob);
+#endif
+
+ return 0;
+}
diff --git a/roms/u-boot/board/freescale/t208xrdb/t208xrdb.h b/roms/u-boot/board/freescale/t208xrdb/t208xrdb.h
new file mode 100644
index 000000000..edbc860c9
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/t208xrdb.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, struct bd_info *bd);
+void fdt_fixup_board_fman_ethernet(void *blob);
+void fdt_fixup_board_phy(void *blob);
+
+#endif
diff --git a/roms/u-boot/board/freescale/t208xrdb/tlb.c b/roms/u-boot/board/freescale/t208xrdb/tlb.c
new file mode 100644
index 000000000..542ab1e03
--- /dev/null
+++ b/roms/u-boot/board/freescale/t208xrdb/tlb.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* *I*G* - PCIe 1, 0x80000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_512M, 1),
+
+ /* *I*G* - PCIe 2, 0xa0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 3, 0xb0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+ /* *I*G* - PCIe 4, 0xc0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+ 0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);