diff options
Diffstat (limited to 'roms/u-boot/board/ge')
23 files changed, 3024 insertions, 0 deletions
diff --git a/roms/u-boot/board/ge/b1x5v2/Kconfig b/roms/u-boot/board/ge/b1x5v2/Kconfig new file mode 100644 index 000000000..80a5bcae7 --- /dev/null +++ b/roms/u-boot/board/ge/b1x5v2/Kconfig @@ -0,0 +1,14 @@ +if TARGET_GE_B1X5V2 + +config SYS_BOARD + default "b1x5v2" + +config SYS_VENDOR + default "ge" + +config SYS_CONFIG_NAME + default "ge_b1x5v2" + +source "board/ge/common/Kconfig" + +endif diff --git a/roms/u-boot/board/ge/b1x5v2/MAINTAINERS b/roms/u-boot/board/ge/b1x5v2/MAINTAINERS new file mode 100644 index 000000000..f22d49283 --- /dev/null +++ b/roms/u-boot/board/ge/b1x5v2/MAINTAINERS @@ -0,0 +1,9 @@ +GE B1X5V2 BOARD +M: Huan 'Kitty' Wang <HuanWang@ge.com> +M: Ian Ray <ian.ray@ge.com> +M: Sebastian Reichel <sebastian.reichel@collabora.com> +S: Maintained +F: arch/arm/dts/imx6dl-b1x5v2.dts +F: board/ge/b1x5v2/ +F: configs/ge_b1x5v2_defconfig +F: include/configs/ge_b1x5v2.h diff --git a/roms/u-boot/board/ge/b1x5v2/Makefile b/roms/u-boot/board/ge/b1x5v2/Makefile new file mode 100644 index 000000000..8a27af52e --- /dev/null +++ b/roms/u-boot/board/ge/b1x5v2/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2018-2020 Collabora +# Copyright 2018-2020 GE + +obj-y := b1x5v2.o spl.o diff --git a/roms/u-boot/board/ge/b1x5v2/b1x5v2.c b/roms/u-boot/board/ge/b1x5v2/b1x5v2.c new file mode 100644 index 000000000..de4cb0d5a --- /dev/null +++ b/roms/u-boot/board/ge/b1x5v2/b1x5v2.c @@ -0,0 +1,699 @@ +/* + * GE B105v2, B125v2, B155v2 + * + * Copyright 2018-2020 GE Inc. + * Copyright 2018-2020 Collabora Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/mach-imx/video.h> +#include <command.h> +#include <common.h> +#include <i2c.h> +#include <input.h> +#include <ipu_pixfmt.h> +#include <linux/delay.h> +#include <linux/fb.h> +#include <malloc.h> +#include <miiphy.h> +#include <micrel.h> +#include <netdev.h> +#include <panel.h> +#include <rtc.h> +#include <spi_flash.h> +#include <version.h> + +#include "../common/vpd_reader.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SPL_BUILD + +#define B1X5V2_GE_VPD_OFFSET 0x0100000 +#define B1X5V2_GE_VPD_SIZE 1022 + +#define VPD_TYPE_INVALID 0x00 +#define VPD_BLOCK_NETWORK 0x20 +#define VPD_BLOCK_HWID 0x44 +#define VPD_MAC_ADDRESS_LENGTH 6 + +#define VPD_FLAG_VALID_MAC BIT(1) + +#define AR8035_PHY_ID 0x004dd072 +#define AR8035_PHY_DEBUG_ADDR_REG 0x1d +#define AR8035_PHY_DEBUG_DATA_REG 0x1e +#define AR8035_HIB_CTRL_REG 0xb +#define AR8035_HIBERNATE_EN (1 << 15) + +static struct vpd_cache { + bool is_read; + u8 product_id; + unsigned char mac[VPD_MAC_ADDRESS_LENGTH]; + u32 flags; +} vpd; + +enum product_type { + PRODUCT_TYPE_B105V2 = 6, + PRODUCT_TYPE_B105PV2 = 7, + PRODUCT_TYPE_B125V2 = 8, + PRODUCT_TYPE_B125PV2 = 9, + PRODUCT_TYPE_B155V2 = 10, + + PRODUCT_TYPE_INVALID = 0, +}; + +int dram_init(void) { + gd->ram_size = imx_ddr_size(); + return 0; +} + +int power_init_board(void) +{ + /* all required PMIC configuration happens via DT */ + return 0; +} + +static int disable_phy_hibernation(struct phy_device *phydev) +{ + unsigned short val; + + if (phydev->drv->uid == AR8035_PHY_ID) { + /* Disable hibernation, other configuration has been done by PHY driver */ + phy_write(phydev, MDIO_DEVAD_NONE, AR8035_PHY_DEBUG_ADDR_REG, AR8035_HIB_CTRL_REG); + val = phy_read(phydev, MDIO_DEVAD_NONE, AR8035_PHY_DEBUG_DATA_REG); + val &= ~AR8035_HIBERNATE_EN; + phy_write(phydev, MDIO_DEVAD_NONE, AR8035_PHY_DEBUG_DATA_REG, val); + } else { + printf("Unknown PHY: %08x\n", phydev->drv->uid); + } + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + disable_phy_hibernation(phydev); + + return 0; +} + +static int auo_g101evn01_detect(const struct display_info_t *info) +{ + char *dev = env_get("devicetype"); + return !strcmp(dev, "B105v2") || !strcmp(dev, "B105Pv2"); +} + +static int auo_g121ean01_detect(const struct display_info_t *info) +{ + char *dev = env_get("devicetype"); + return !strcmp(dev, "B125v2") || !strcmp(dev, "B125Pv2");; +} + +static int auo_g156xtn01_detect(const struct display_info_t *info) +{ + char *dev = env_get("devicetype"); + return !strcmp(dev, "B155v2"); +} + +static void b1x5v2_backlight_enable(int percent) +{ + struct udevice *panel; + int ret; + + ret = uclass_get_device(UCLASS_PANEL, 0, &panel); + if (ret) { + printf("Could not find panel: %d\n", ret); + return; + } + + panel_set_backlight(panel, percent); + panel_enable_backlight(panel); + +} + +static void lcd_enable(const struct display_info_t *info) +{ + printf("Enable backlight...\n"); + b1x5v2_backlight_enable(100); +} + +struct display_info_t const displays[] = { +{ + .di = 0, + .bus = -1, + .addr = -1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = auo_g156xtn01_detect, + .enable = lcd_enable, + .mode = { + .name = "AUO G156XTN01", + .refresh = 60, + .xres = 1368, /* because of i.MX6 limitation, actually 1366 */ + .yres = 768, + .pixclock = 13158, /* 76 MHz in ps */ + .left_margin = 33, + .right_margin = 67, + .upper_margin = 4, + .lower_margin = 4, + .hsync_len = 94, + .vsync_len = 30, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } +}, +{ + .di = 0, + .bus = -1, + .addr = -1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = auo_g121ean01_detect, + .enable = lcd_enable, + .mode = { + .name = "AUO G121EAN01.4", + .refresh = 60, + .xres = 1280, + .yres = 800, + .pixclock = 14992, /* 66.7 MHz in ps */ + .left_margin = 8, + .right_margin = 58, + .upper_margin = 6, + .lower_margin = 4, + .hsync_len = 70, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } +}, +{ + .di = 0, + .bus = -1, + .addr = -1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = auo_g101evn01_detect, + .enable = lcd_enable, + .mode = { + .name = "AUO G101EVN01.3", + .refresh = 60, + .xres = 1280, + .yres = 800, + .pixclock = 14992, /* 66.7 MHz in ps */ + .left_margin = 8, + .right_margin = 58, + .upper_margin = 6, + .lower_margin = 4, + .hsync_len = 70, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } +} +}; +size_t display_count = ARRAY_SIZE(displays); + +static void enable_videopll(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + s32 timeout = 100000; + + setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2) + * | + * PLL5 + * | + * CS2CDR[LDB_DI0_CLK_SEL] + * | + * +----> LDB_DI0_SERIAL_CLK_ROOT + * | + * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz + */ + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_DIV_SELECT | + BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, + BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | + BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1)); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); + + clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_BYPASS, + BM_ANADIG_PLL_VIDEO_ENABLE); +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + enable_videopll(); + + /* When a reset/reboot is performed the display power needs to be turned + * off for atleast 500ms. The boot time is ~300ms, we need to wait for + * an additional 200ms here. Unfortunately we use external PMIC for + * doing the reset, so can not differentiate between POR vs soft reset + */ + mdelay(200); + + /* CCM_CSCMR2 -> ldb_di0_ipu_div [IMX6SDLRM page 839] */ + /* divide IPU clock by 7 */ + setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + /* CCM_CHSCCDR -> ipu1_di0_clk_sel [IMX6SDLRM page 849] */ + /* Set LDB_DI0 as clock source for IPU_DI0 */ + clrsetbits_le32(&mxc_ccm->chsccdr, + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, + (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); + + /* Turn on IPU LDB DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + enable_ipu_clock(); + + /* IOMUXC_GPR2 [IMX6SDLRM page 2049] */ + /* Set LDB Channel 0 in SPWG 24 Bit mode */ + writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + /* IOMUXC_GPR3 [IMX6SDLRM page 2051] */ + /* LVDS0 is connected to IPU DI0 */ + clrsetbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)); +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_early_init_f(void) +{ + select_ldb_di_clock_source(MXC_PLL5_CLK); + + return 0; +} + +static int eeti_touch_get_model(struct udevice *dev, char *result) { + u8 query[68] = {0x67, 0x00, 0x42, 0x00, 0x03, 0x01, 'E', 0x00, 0x00, 0x00}; + struct i2c_msg qmsg = { + .addr = 0x2a, + .flags = 0, + .len = sizeof(query), + .buf = query, + }; + u8 reply[66] = {0}; + struct i2c_msg rmsg = { + .addr = 0x2a, + .flags = I2C_M_RD, + .len = sizeof(reply), + .buf = reply, + }; + int err; + + err = dm_i2c_xfer(dev, &qmsg, 1); + if (err) + return err; + + /* + * device sends IRQ when its ok to read. To keep the code + * simple we just wait an arbitrary, long enough time period. + */ + mdelay(10); + + err = dm_i2c_xfer(dev, &rmsg, 1); + if (err) + return err; + + if (reply[0] != 0x42 || reply[1] != 0x00 || + reply[2] != 0x03 || reply[4] != 'E') + return -EPROTO; + + memcpy(result, reply+5, 10); + return 0; +} + +static bool b1x5v2_board_is_p_model(void) +{ + struct udevice *bus = NULL; + struct udevice *dev = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_I2C, "i2c@21a0000", &bus); + if (err || !bus) { + printf("Could not get I2C bus: %d\n", err); + return true; + } + + /* The P models do not have this port expander */ + err = dm_i2c_probe(bus, 0x21, 0, &dev); + if (err || !dev) { + return true; + } + + return false; +} + +static enum product_type b1x5v2_board_type(void) +{ + struct udevice *bus = NULL; + struct udevice *dev = NULL; + char model[11] = {0}; + int err; + int retry; + + err = uclass_get_device_by_name(UCLASS_I2C, "i2c@21a8000", &bus); + if (err) { + printf("Could not get I2C bus: %d\n", err); + return PRODUCT_TYPE_INVALID; + } + + err = dm_i2c_probe(bus, 0x41, 0, &dev); + if (!err && dev) { /* Ilitek Touchscreen */ + if (b1x5v2_board_is_p_model()) { + return PRODUCT_TYPE_B105PV2; + } else { + return PRODUCT_TYPE_B105V2; + } + } + + err = dm_i2c_probe(bus, 0x2a, 0, &dev); + if (err || !dev) { + printf("Could not find touchscreen: %d\n", err); + return PRODUCT_TYPE_INVALID; + } + + for (retry = 0; retry < 3; ++retry) { + err = eeti_touch_get_model(dev, model); + if (!err) + break; + printf("Retry %d read EETI touchscreen model: %d\n", retry + 1, err); + } + if (err) { + printf("Could not read EETI touchscreen model: %d\n", err); + return PRODUCT_TYPE_INVALID; + } + + if (!strcmp(model, "Orion_1320")) { /* EETI EXC80H60 */ + if (b1x5v2_board_is_p_model()) { + return PRODUCT_TYPE_B125PV2; + } else { + return PRODUCT_TYPE_B125V2; + } + } else if (!strcmp(model, "Orion_1343")) { /* EETI EXC80H84 */ + return PRODUCT_TYPE_B155V2; + } + + printf("Unknown EETI touchscreen model: %s\n", model); + return PRODUCT_TYPE_INVALID; +} + +static void set_env_per_board_type(enum product_type type) +{ + switch (type) { + case PRODUCT_TYPE_B105V2: + env_set("resolution", "1280x800"); + env_set("devicetype", "B105v2"); + env_set("fdtfile", "imx6dl-b105v2.dtb"); + break; + case PRODUCT_TYPE_B105PV2: + env_set("resolution", "1280x800"); + env_set("devicetype", "B105Pv2"); + env_set("fdtfile", "imx6dl-b105pv2.dtb"); + break; + case PRODUCT_TYPE_B125V2: + env_set("resolution", "1280x800"); + env_set("devicetype", "B125v2"); + env_set("fdtfile", "imx6dl-b125v2.dtb"); + break; + case PRODUCT_TYPE_B125PV2: + env_set("resolution", "1280x800"); + env_set("devicetype", "B125Pv2"); + env_set("fdtfile", "imx6dl-b125pv2.dtb"); + break; + case PRODUCT_TYPE_B155V2: + env_set("resolution", "1366x768"); + env_set("devicetype", "B155v2"); + env_set("fdtfile", "imx6dl-b155v2.dtb"); + break; + default: + break; + } +} + +static int b1x5v2_board_type_autodetect(void) +{ + enum product_type product = b1x5v2_board_type(); + if (product != PRODUCT_TYPE_INVALID) { + set_env_per_board_type(product); + return 0; + } + return -1; +} + +/* + * Extracts MAC and product information from the VPD. + */ +static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type, + size_t size, u8 const *data) +{ + if (type == VPD_TYPE_INVALID) + return 0; + + if (id == VPD_BLOCK_HWID && version == 1 && size >= 1) { + vpd->product_id = data[0]; + } else if (id == VPD_BLOCK_NETWORK && version == 1) { + if (size >= VPD_MAC_ADDRESS_LENGTH) { + memcpy(vpd->mac, data, VPD_MAC_ADDRESS_LENGTH); + vpd->flags |= VPD_FLAG_VALID_MAC; + } + } + + return 0; +} + +static int read_spi_vpd(struct vpd_cache *cache, + int (*process_block)(struct vpd_cache *, u8 id, u8 version, + u8 type, size_t size, u8 const *data)) +{ + static const int size = B1X5V2_GE_VPD_SIZE; + struct udevice *dev; + int ret; + u8 *data; + + ret = uclass_get_device_by_name(UCLASS_SPI_FLASH, "m25p80@0", &dev); + if (ret) + return ret; + + data = malloc(size); + if (!data) + return -ENOMEM; + + ret = spi_flash_read_dm(dev, B1X5V2_GE_VPD_OFFSET, size, data); + if (ret) { + free(data); + return ret; + } + + ret = vpd_reader(size, data, cache, process_block); + + free(data); + + return ret; +} + +int board_init(void) +{ + if (!read_spi_vpd(&vpd, vpd_callback)) { + vpd.is_read = true; + } + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + setup_display(); + + return 0; +} + +static void init_bootcause(void) +{ + const char *cause; + + /* We care about WDOG only, treating everything else as + * a power-on-reset. + */ + if (get_imx_reset_cause() & 0x0010) + cause = "WDOG"; + else + cause = "POR"; + + env_set("bootcause", cause); +} + +int misc_init_r(void) +{ + init_bootcause(); + + return 0; +} + +#define M41T62_REG_FLAGS 0xf +#define M41T62_FLAGS_OF (1 << 2) +static void check_time(void) +{ + struct udevice *rtc = NULL; + struct rtc_time tm; + u8 val; + int ret; + + ret = uclass_get_device_by_name(UCLASS_RTC, "m41t62@68", &rtc); + if (ret) { + printf("Could not get RTC: %d\n", ret); + env_set("rtc_status", "FAIL"); + return; + } + + ret = dm_i2c_read(rtc, M41T62_REG_FLAGS, &val, sizeof(val)); + if (ret) { + printf("Could not read RTC register: %d\n", ret); + env_set("rtc_status", "FAIL"); + return; + } + + ret = dm_rtc_reset(rtc); + if (ret) { + printf("Could not reset RTC: %d\n", ret); + env_set("rtc_status", "FAIL"); + return; + } + + if (val & M41T62_FLAGS_OF) { + env_set("rtc_status", "STOP"); + return; + } + + ret = dm_rtc_get(rtc, &tm); + if (ret) { + printf("Could not read RTC: %d\n", ret); + env_set("rtc_status", "FAIL"); + return; + } + + if (tm.tm_year > 2037) { + tm.tm_sec = 0; + tm.tm_min = 0; + tm.tm_hour = 0; + tm.tm_mday = 1; + tm.tm_wday = 2; + tm.tm_mon = 1; + tm.tm_year = 2036; + + ret = dm_rtc_set(rtc, &tm); + if (ret) { + printf("Could not update RTC: %d\n", ret); + env_set("rtc_status", "FAIL"); + return; + } + + printf("RTC behind 2037, capped to 2036 for userspace handling\n"); + env_set("rtc_status", "2038"); + return; + } + + env_set("rtc_status", "OK"); +} + +static void process_vpd(struct vpd_cache *vpd) +{ + if (!vpd->is_read) { + printf("VPD wasn't read\n"); + return; + } + + if (vpd->flags & VPD_FLAG_VALID_MAC) { + eth_env_set_enetaddr_by_index("eth", 0, vpd->mac); + env_set("ethact", "eth0"); + } +} + +int board_late_init(void) +{ + process_vpd(&vpd); + + if (vpd.product_id >= PRODUCT_TYPE_B105V2 && + vpd.product_id <= PRODUCT_TYPE_B155V2) { + set_env_per_board_type((enum product_type)vpd.product_id); + } else { + b1x5v2_board_type_autodetect(); + } + + printf("Board: GE %s\n", env_get("devicetype")); + + check_time(); + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + char *rtc_status = env_get("rtc_status"); + + fdt_setprop(blob, 0, "ge,boot-ver", version_string, + strlen(version_string) + 1); + fdt_setprop(blob, 0, "ge,rtc-status", rtc_status, + strlen(rtc_status) + 1); + + return 0; +} +#endif + +static int do_b1x5v2_autodetect(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + int err; + + err = b1x5v2_board_type_autodetect(); + if (!err) + printf("Identified %s\n", env_get("devicetype")); + + return 0; +} + +U_BOOT_CMD( + autodetect_devtype, 1, 1, do_b1x5v2_autodetect, + "autodetect b1x5v2 device type", + "" +); + +#endif // CONFIG_SPL_BUILD diff --git a/roms/u-boot/board/ge/b1x5v2/spl.c b/roms/u-boot/board/ge/b1x5v2/spl.c new file mode 100644 index 000000000..52c80f792 --- /dev/null +++ b/roms/u-boot/board/ge/b1x5v2/spl.c @@ -0,0 +1,587 @@ +/* + * GE b1x5v2 - QMX6 SPL + * + * Copyright 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Copyright 2018-2020 GE Inc. + * Copyright 2018-2020 Collabora Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <init.h> +#include <spi.h> +#include <spi_flash.h> +#include <spl.h> + +#if defined(CONFIG_SPL_BUILD) + +#include <asm/arch/mx6-ddr.h> + +#define IMX6DQ_DRIVE_STRENGTH_40_OHM 0x30 +#define IMX6DQ_DRIVE_STRENGTH_48_OHM 0x28 +#define IMX6DQ_DRIVE_STRENGTH IMX6DQ_DRIVE_STRENGTH_40_OHM + +#define QMX6_DDR_PKE_DISABLED 0x00000000 +#define QMX6_DDR_ODT_60_OHM (2 << 16) +#define QMX6_DDR_TYPE_DDR3 0x000c0000 + +#define QMX6_DRAM_SDCKE_PULLUP_100K 0x00003000 +#define QMX6_DRAM_SDBA2_PULLUP_NONE 0x00000000 + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define SPI1_CS0 IMX_GPIO_NR(3, 19) +#define POWEROFF IMX_GPIO_NR(4, 25) + +static iomux_v3_cfg_t const poweroff_pads[] = { + IOMUX_PADS(PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const uart2_pads[] = { + IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const uart3_pads[] = { + IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const ecspi1_pads[] = { + IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { + .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, + .dram_cas = IMX6DQ_DRIVE_STRENGTH, + .dram_ras = IMX6DQ_DRIVE_STRENGTH, + .dram_reset = IMX6DQ_DRIVE_STRENGTH, + .dram_sdcke0 = QMX6_DRAM_SDCKE_PULLUP_100K, + .dram_sdcke1 = QMX6_DRAM_SDCKE_PULLUP_100K, + .dram_sdba2 = QMX6_DRAM_SDBA2_PULLUP_NONE, + .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, +}; + +static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = { + .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, + .dram_cas = IMX6DQ_DRIVE_STRENGTH, + .dram_ras = IMX6DQ_DRIVE_STRENGTH, + .dram_reset = IMX6DQ_DRIVE_STRENGTH, + .dram_sdcke0 = QMX6_DRAM_SDCKE_PULLUP_100K, + .dram_sdcke1 = QMX6_DRAM_SDCKE_PULLUP_100K, + .dram_sdba2 = QMX6_DRAM_SDBA2_PULLUP_NONE, + .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, +}; + +static struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = { + .grp_ddr_type = QMX6_DDR_TYPE_DDR3, + .grp_ddrmode_ctl = QMX6_DDR_ODT_60_OHM, + .grp_ddrpke = QMX6_DDR_PKE_DISABLED, + .grp_addds = IMX6DQ_DRIVE_STRENGTH, + .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, + .grp_ddrmode = QMX6_DDR_ODT_60_OHM, + .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, +}; + +static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + .grp_ddr_type = QMX6_DDR_TYPE_DDR3, + .grp_ddrmode_ctl = QMX6_DDR_ODT_60_OHM, + .grp_ddrpke = QMX6_DDR_PKE_DISABLED, + .grp_addds = IMX6DQ_DRIVE_STRENGTH, + .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, + .grp_ddrmode = QMX6_DDR_ODT_60_OHM, + .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, +}; + +const struct mx6_mmdc_calibration mx6q_mmcd_calib = { + .p0_mpwldectrl0 = 0x0016001A, + .p0_mpwldectrl1 = 0x0023001C, + .p1_mpwldectrl0 = 0x0028003A, + .p1_mpwldectrl1 = 0x001F002C, + .p0_mpdgctrl0 = 0x43440354, + .p0_mpdgctrl1 = 0x033C033C, + .p1_mpdgctrl0 = 0x43300368, + .p1_mpdgctrl1 = 0x03500330, + .p0_mprddlctl = 0x3228242E, + .p1_mprddlctl = 0x2C2C2636, + .p0_mpwrdlctl = 0x36323A38, + .p1_mpwrdlctl = 0x42324440, +}; + +const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = { + .p0_mpwldectrl0 = 0x00080016, + .p0_mpwldectrl1 = 0x001D0016, + .p1_mpwldectrl0 = 0x0018002C, + .p1_mpwldectrl1 = 0x000D001D, + .p0_mpdgctrl0 = 0x43200334, + .p0_mpdgctrl1 = 0x0320031C, + .p1_mpdgctrl0 = 0x0344034C, + .p1_mpdgctrl1 = 0x03380314, + .p0_mprddlctl = 0x3E36383A, + .p1_mprddlctl = 0x38363240, + .p0_mpwrdlctl = 0x36364238, + .p1_mpwrdlctl = 0x4230423E, +}; + +const struct mx6_mmdc_calibration mx6q_4g_mmcd_calib = { + .p0_mpwldectrl0 = 0x00180018, + .p0_mpwldectrl1 = 0x00220018, + .p1_mpwldectrl0 = 0x00330046, + .p1_mpwldectrl1 = 0x002B003D, + .p0_mpdgctrl0 = 0x4344034C, + .p0_mpdgctrl1 = 0x033C033C, + .p1_mpdgctrl0 = 0x03700374, + .p1_mpdgctrl1 = 0x03600338, + .p0_mprddlctl = 0x443E3E40, + .p1_mprddlctl = 0x423E3E48, + .p0_mpwrdlctl = 0x3C3C4442, + .p1_mpwrdlctl = 0x46384C46, +}; + +static const struct mx6_mmdc_calibration mx6s_mmcd_calib = { + .p0_mpwldectrl0 = 0x00480049, + .p0_mpwldectrl1 = 0x00410044, + .p0_mpdgctrl0 = 0x42480248, + .p0_mpdgctrl1 = 0x023C023C, + .p0_mprddlctl = 0x40424644, + .p0_mpwrdlctl = 0x34323034, +}; + +static const struct mx6_mmdc_calibration mx6s_2g_mmcd_calib = { + .p0_mpwldectrl0 = 0x00450048, + .p0_mpwldectrl1 = 0x003B003F, + .p0_mpdgctrl0 = 0x424C0248, + .p0_mpdgctrl1 = 0x0234023C, + .p0_mprddlctl = 0x40444848, + .p0_mpwrdlctl = 0x38363232, +}; + +static const struct mx6_mmdc_calibration mx6dl_mmcd_calib = { + .p0_mpwldectrl0 = 0x0043004B, + .p0_mpwldectrl1 = 0x003A003E, + .p1_mpwldectrl0 = 0x0047004F, + .p1_mpwldectrl1 = 0x004E0061, + .p0_mpdgctrl0 = 0x42500250, + .p0_mpdgctrl1 = 0x0238023C, + .p1_mpdgctrl0 = 0x42640264, + .p1_mpdgctrl1 = 0x02500258, + .p0_mprddlctl = 0x40424846, + .p1_mprddlctl = 0x46484842, + .p0_mpwrdlctl = 0x38382C30, + .p1_mpwrdlctl = 0x34343430, +}; + +static const struct mx6_mmdc_calibration mx6dl_2g_mmcd_calib = { + .p0_mpwldectrl0 = 0x00450045, + .p0_mpwldectrl1 = 0x00390043, + .p1_mpwldectrl0 = 0x0049004D, + .p1_mpwldectrl1 = 0x004E0061, + .p0_mpdgctrl0 = 0x4240023C, + .p0_mpdgctrl1 = 0x0228022C, + .p1_mpdgctrl0 = 0x02400244, + .p1_mpdgctrl1 = 0x02340238, + .p0_mprddlctl = 0x42464648, + .p1_mprddlctl = 0x4446463C, + .p0_mpwrdlctl = 0x3C38323A, + .p1_mpwrdlctl = 0x34323430, +}; + +static struct mx6_ddr3_cfg mem_ddr_2g = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1310, + .trcmin = 4875, + .trasmin = 3500, +}; + +static struct mx6_ddr3_cfg mem_ddr_4g = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1310, + .trcmin = 4875, + .trasmin = 3500, +}; + +static struct mx6_ddr3_cfg mem_ddr_8g = { + .mem_speed = 1600, + .density = 8, + .width = 16, + .banks = 8, + .rowaddr = 16, + .coladdr = 10, + .pagesz = 2, + .trcd = 1310, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void spl_dram_init(u8 width, u32 memsize) { + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus: 0=16, 1=32, 2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 2, + .walat = 0, + .ralat = 5, + .mif3_mode = 3, + .bi_on = 1, + .sde_to_rst = 0x0d, + .rst_to_cke = 0x20, + }; + + if (is_cpu_type(MXC_CPU_MX6SOLO)) { + sysinfo.walat = 1; + mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); + + switch(memsize) { + case 512: + mx6_dram_cfg(&sysinfo, &mx6s_2g_mmcd_calib, &mem_ddr_2g); + break; + default: + mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g); + break; + } + } else if (is_cpu_type(MXC_CPU_MX6DL)) { + sysinfo.walat = 1; + mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); + + switch(memsize) { + case 2048: + mx6_dram_cfg(&sysinfo, &mx6dl_2g_mmcd_calib, &mem_ddr_4g); + break; + default: + mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g); + break; + } + } else if (is_cpu_type(MXC_CPU_MX6Q)) { + mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); + + switch(memsize) { + case 4096: + sysinfo.cs_density = 16; + sysinfo.ncs = 2; + mx6_dram_cfg(&sysinfo, &mx6q_4g_mmcd_calib, &mem_ddr_8g); + break; + case 2048: + mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g); + break; + default: + mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g); + break; + } + } +} + +/* Define a minimal structure so that the part number can be read via SPL */ +#define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K) +struct mfgdata { + unsigned char tsize; + /* size of checksummed part in bytes */ + unsigned char ckcnt; + /* checksum corrected byte */ + unsigned char cksum; + /* decimal serial number, packed BCD */ + unsigned char serial[6]; + /* part number, right justified, ASCII */ + unsigned char pn[16]; +}; + +static void conv_ascii(unsigned char *dst, unsigned char *src, int len) +{ + int remain = len; + unsigned char *sptr = src; + unsigned char *dptr = dst; + + while (remain) { + if (*sptr) { + *dptr = *sptr; + dptr++; + } + sptr++; + remain--; + } + *dptr = 0x0; +} + +/* + * Returns the total size of the memory [in MB] the board is equipped with + * + * This is determined via the partnumber which is stored in the + * congatec manufacturing area + */ +static int get_boardmem_size(struct spi_flash *spi) +{ + int ret; + int i; + int arraysize; + char buf[sizeof(struct mfgdata)]; + struct mfgdata *data = (struct mfgdata *)buf; + unsigned char outbuf[32]; + char partnumbers_2g[4][7] = { "016104", "016105", "016304", "016305" }; + char partnumbers_4g[2][7] = { "016308", "016318" }; + char partnumbers_512m[2][7] = { "016203", "616300" }; + + ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata), + buf); + if (ret) + return 1024; /* default to 1GByte in case of error */ + + conv_ascii(outbuf, data->pn, sizeof(data->pn)); + + printf("Detected Congatec QMX6 SOM: %s\n", outbuf); + + /* congatec PN 016104, 016105, 016304, 016305 have 2GiB of RAM */ + arraysize = sizeof(partnumbers_2g) / sizeof(partnumbers_2g[0]); + for (i=0; i < arraysize; i++) { + if (!memcmp(outbuf,partnumbers_2g[i],6)) + return 2048; + } + + /* congatec PN 016308, 016318 have 4GiB of RAM */ + arraysize = sizeof(partnumbers_4g) / sizeof(partnumbers_4g[0]); + for (i=0; i < arraysize; i++) { + if (!memcmp(outbuf,partnumbers_4g[i],6)) + return 4096; + } + + /* congatec PN 016203, 616300 has 512MiB of RAM */ + arraysize = sizeof(partnumbers_512m) / sizeof(partnumbers_512m[0]); + for (i=0; i < arraysize; i++) { + if (!memcmp(outbuf,partnumbers_512m[i],6)) + return 512; + } + + /* default to 1GByte */ + return 1024; +} + +void reset_cpu(void) +{ +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + if (bus == 0 && cs == 0) + return (SPI1_CS0); + else + return -1; +} + +static void memory_init(void) { + struct spi_flash *spi; + u8 width; + u32 size; + + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_direction_output(SPI1_CS0, 0); + + spi = spi_flash_probe(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!spi) + panic("Cannot identify board type: SPI-NOR flash module not detected\n"); + + /* lock manufacturer area */ + spi_flash_protect(spi, CFG_MFG_ADDR_OFFSET, SZ_16K, true); + + width = is_cpu_type(MXC_CPU_MX6SOLO) ? 32 : 64; + size = get_boardmem_size(spi); + printf("Detected Memory Size: %u\n", size); + + spl_dram_init(width, size); +} + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + static const uint32_t ccgr0 = + MXC_CCM_CCGR0_AIPS_TZ1_MASK | + MXC_CCM_CCGR0_AIPS_TZ2_MASK | + MXC_CCM_CCGR0_APBHDMA_MASK | + MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | + MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK; + + static const uint32_t ccgr1 = + MXC_CCM_CCGR1_ECSPI1S_MASK | + MXC_CCM_CCGR1_ENET_MASK | + MXC_CCM_CCGR1_EPIT1S_MASK | + MXC_CCM_CCGR1_EPIT2S_MASK | + MXC_CCM_CCGR1_GPT_BUS_MASK; + + static const uint32_t ccgr2 = + MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK | + MXC_CCM_CCGR2_IPMUX1_MASK | + MXC_CCM_CCGR2_IPMUX2_MASK | + MXC_CCM_CCGR2_IPMUX3_MASK | + MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK | + MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK | + MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK; + + static const uint32_t ccgr3 = + MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK | + MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK | + MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK | + MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK | + MXC_CCM_CCGR3_OCRAM_MASK; + + static const uint32_t ccgr4 = + MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK | + MXC_CCM_CCGR4_PWM1_MASK | + MXC_CCM_CCGR4_PWM2_MASK | + MXC_CCM_CCGR4_PWM3_MASK | + MXC_CCM_CCGR4_PWM4_MASK; + + static const uint32_t ccgr5 = + MXC_CCM_CCGR5_ROM_MASK | + MXC_CCM_CCGR5_SDMA_MASK | + MXC_CCM_CCGR5_UART_MASK | + MXC_CCM_CCGR5_UART_SERIAL_MASK; + + static const uint32_t ccgr6 = + MXC_CCM_CCGR6_USBOH3_MASK | + MXC_CCM_CCGR6_USDHC1_MASK | + MXC_CCM_CCGR6_USDHC2_MASK | + MXC_CCM_CCGR6_SIM1_CLK_MASK | + MXC_CCM_CCGR6_SIM2_CLK_MASK; + + writel(ccgr0, &ccm->CCGR0); + writel(ccgr1, &ccm->CCGR1); + writel(ccgr2, &ccm->CCGR2); + writel(ccgr3, &ccm->CCGR3); + writel(ccgr4, &ccm->CCGR4); + writel(ccgr5, &ccm->CCGR5); + writel(ccgr6, &ccm->CCGR6); +} + +void board_init_f(ulong dummy) +{ + /* setup clock gating */ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* setup AXI */ + gpr_init(); + + /* + * setup poweroff GPIO. This controls system power regulator. Once + * the power button is released this must be enabled to keep system + * running. Not enabling it (or disabling it later) will turn off + * the main system regulator and instantly poweroff the system. We + * do this very early, to reduce the time users have to press the + * power button. + */ + SETUP_IOMUX_PADS(poweroff_pads); + gpio_direction_output(POWEROFF, 1); + + /* setup GP timer */ + timer_init(); + + /* iomux */ + if (CONFIG_MXC_UART_BASE == UART2_BASE) + SETUP_IOMUX_PADS(uart2_pads); + else if (CONFIG_MXC_UART_BASE == UART3_BASE) + SETUP_IOMUX_PADS(uart3_pads); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Needed for malloc() [used by SPI] to work in SPL prior to board_init_r() */ + spl_init(); + + /* DDR initialization */ + memory_init(); +} + +void spl_board_prepare_for_boot(void) +{ + printf("Load normal U-Boot...\n"); +} +#endif diff --git a/roms/u-boot/board/ge/bx50v3/Kconfig b/roms/u-boot/board/ge/bx50v3/Kconfig new file mode 100644 index 000000000..05938560a --- /dev/null +++ b/roms/u-boot/board/ge/bx50v3/Kconfig @@ -0,0 +1,20 @@ +if TARGET_GE_BX50V3 + +config IMX_CONFIG + default "board/ge/bx50v3/bx50v3.cfg" + +config SYS_BOARD + default "bx50v3" + +config SYS_VENDOR + default "ge" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "ge_bx50v3" + +source "board/ge/common/Kconfig" + +endif diff --git a/roms/u-boot/board/ge/bx50v3/MAINTAINERS b/roms/u-boot/board/ge/bx50v3/MAINTAINERS new file mode 100644 index 000000000..fafbd78c2 --- /dev/null +++ b/roms/u-boot/board/ge/bx50v3/MAINTAINERS @@ -0,0 +1,14 @@ +GE BX50V3 BOARD +M: Ian Ray <ian.ray@ge.com> +M: Sebastian Reichel <sebastian.reichel@collabora.com> +S: Maintained +F: arch/arm/dts/imx6q-b450v3.dts +F: arch/arm/dts/imx6q-b650v3.dts +F: arch/arm/dts/imx6q-b850v3.dts +F: arch/arm/dts/imx6q-bx50v3* +F: board/ge/bx50v3/ +F: configs/ge_b450v3_defconfig +F: configs/ge_b650v3_defconfig +F: configs/ge_b850v3_defconfig +F: configs/ge_bx50v3_defconfig +F: include/configs/ge_bx50v3.h diff --git a/roms/u-boot/board/ge/bx50v3/Makefile b/roms/u-boot/board/ge/bx50v3/Makefile new file mode 100644 index 000000000..9b80e7c24 --- /dev/null +++ b/roms/u-boot/board/ge/bx50v3/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2015 Timesys Corporation +# Copyright 2015 General Electric Company + +obj-y := bx50v3.o diff --git a/roms/u-boot/board/ge/bx50v3/bx50v3.c b/roms/u-boot/board/ge/bx50v3/bx50v3.c new file mode 100644 index 000000000..7fcebba02 --- /dev/null +++ b/roms/u-boot/board/ge/bx50v3/bx50v3.c @@ -0,0 +1,596 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Timesys Corporation + * Copyright 2015 General Electric Company + * Copyright 2012 Freescale Semiconductor, Inc. + */ + +#include <image.h> +#include <init.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <env.h> +#include <asm/global_data.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/libfdt.h> +#include <asm/gpio.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/video.h> +#include <mmc.h> +#include <fsl_esdhc_imx.h> +#include <miiphy.h> +#include <net.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <power/regulator.h> +#include <power/da9063_pmic.h> +#include <power/pmic.h> +#include <input.h> +#include <pwm.h> +#include <version.h> +#include <stdlib.h> +#include <dm/root.h> +#include "../common/ge_rtc.h" +#include "../common/vpd_reader.h" +#include "../../../drivers/net/e1000.h" +#include <pci.h> +#include <panel.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define VPD_PRODUCT_B850 1 +#define VPD_PRODUCT_B650 2 +#define VPD_PRODUCT_B450 3 + +#define AR8033_DBG_REG_ADDR 0x1d +#define AR8033_DBG_REG_DATA 0x1e +#define AR8033_SERDES_REG 0x5 + +static int productid; /* Default to generic. */ +static struct vpd_cache vpd; + +#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Set reserved bits to avoid board specific voltage peak issue. The + * value is a magic number provided directly by Qualcomm. Note, that + * PHY driver will take control of BIT(8) in this register to control + * TX clock delay, so we do not initialize that bit here. + */ + phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG); + phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +#if defined(CONFIG_VIDEO_IPUV3) +static void do_enable_backlight(struct display_info_t const *dev) +{ + struct udevice *panel; + int ret; + + ret = uclass_get_device(UCLASS_PANEL, 0, &panel); + if (ret) { + printf("Could not find panel: %d\n", ret); + return; + } + + panel_set_backlight(panel, 100); + panel_enable_backlight(panel); +} + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static int is_b850v3(void) +{ + return productid == VPD_PRODUCT_B850; +} + +static int detect_lcd(struct display_info_t const *dev) +{ + return !is_b850v3(); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = -1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_lcd, + .enable = do_enable_backlight, + .mode = { + .name = "G121X1-L03", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 20, + .right_margin = 300, + .upper_margin = 30, + .lower_margin = 8, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 3, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void enable_videopll(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + s32 timeout = 100000; + + setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2) + * | + * PLL5 + * | + * CS2CDR[LDB_DI0_CLK_SEL] + * | + * +----> LDB_DI0_SERIAL_CLK_ROOT + * | + * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz + */ + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_DIV_SELECT | + BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, + BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | + BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1)); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); + + clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_BYPASS, + BM_ANADIG_PLL_VIDEO_ENABLE); +} + +static void setup_display_b850v3(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + enable_videopll(); + + /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */ + setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + imx_setup_hdmi(); + + /* Set LDB_DI0 as clock source for IPU_DI0 */ + clrsetbits_le32(&mxc_ccm->chsccdr, + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, + (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); + + /* Turn on IPU LDB DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + enable_ipu_clock(); + + writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_SPLIT_MODE_EN_MASK | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | + IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + clrbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | + IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | + IOMUXC_GPR3_HDMI_MUX_CTL_MASK); +} + +static void setup_display_bx50v3(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + enable_videopll(); + + /* When a reset/reboot is performed the display power needs to be turned + * off for atleast 500ms. The boot time is ~300ms, we need to wait for + * an additional 200ms here. Unfortunately we use external PMIC for + * doing the reset, so can not differentiate between POR vs soft reset + */ + mdelay(200); + + /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */ + setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + /* Set LDB_DI0 as clock source for IPU_DI0 */ + clrsetbits_le32(&mxc_ccm->chsccdr, + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, + (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); + + /* Turn on IPU LDB DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + enable_ipu_clock(); + + writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + clrsetbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#define VPD_TYPE_INVALID 0x00 +#define VPD_BLOCK_NETWORK 0x20 +#define VPD_BLOCK_HWID 0x44 +#define VPD_HAS_MAC1 0x1 +#define VPD_HAS_MAC2 0x2 +#define VPD_MAC_ADDRESS_LENGTH 6 + +struct vpd_cache { + bool is_read; + u8 product_id; + u8 has; + unsigned char mac1[VPD_MAC_ADDRESS_LENGTH]; + unsigned char mac2[VPD_MAC_ADDRESS_LENGTH]; +}; + +/* + * Extracts MAC and product information from the VPD. + */ +static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type, + size_t size, u8 const *data) +{ + if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID && + size >= 1) { + vpd->product_id = data[0]; + } else if (id == VPD_BLOCK_NETWORK && version == 1 && + type != VPD_TYPE_INVALID) { + if (size >= 6) { + vpd->has |= VPD_HAS_MAC1; + memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH); + } + if (size >= 12) { + vpd->has |= VPD_HAS_MAC2; + memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH); + } + } + + return 0; +} + +static void process_vpd(struct vpd_cache *vpd) +{ + int fec_index = 0; + int i210_index = -1; + + if (!vpd->is_read) { + printf("VPD wasn't read"); + return; + } + + if (vpd->has & VPD_HAS_MAC1) + eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1); + + env_set("ethact", "eth0"); + + switch (vpd->product_id) { + case VPD_PRODUCT_B450: + i210_index = 1; + break; + case VPD_PRODUCT_B650: + i210_index = 1; + break; + case VPD_PRODUCT_B850: + i210_index = 2; + break; + } + + if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2)) + eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2); +} + +static iomux_v3_cfg_t const misc_pads[] = { + MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL), +}; +#define SUS_S3_OUT IMX_GPIO_NR(4, 11) +#define PWGIN_IN IMX_GPIO_NR(4, 14) +#define WIFI_EN IMX_GPIO_NR(6, 14) + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(misc_pads, + ARRAY_SIZE(misc_pads)); + +#if defined(CONFIG_VIDEO_IPUV3) + /* Set LDB clock to Video PLL */ + select_ldb_di_clock_source(MXC_PLL5_CLK); +#endif + return 0; +} + +int board_init(void) +{ + if (!read_i2c_vpd(&vpd, vpd_callback)) { + int ret, rescan; + + vpd.is_read = true; + productid = vpd.product_id; + + ret = fdtdec_resetup(&rescan); + if (!ret && rescan) { + dm_uninit(); + dm_init_and_scan(false); + } + } + + gpio_request(SUS_S3_OUT, "sus_s3_out"); + gpio_direction_output(SUS_S3_OUT, 1); + + gpio_request(PWGIN_IN, "pwgin_in"); + gpio_direction_input(PWGIN_IN); + + gpio_request(WIFI_EN, "wifi_en"); + gpio_direction_output(WIFI_EN, 1); + +#if defined(CONFIG_VIDEO_IPUV3) + if (is_b850v3()) + setup_display_b850v3(); + else + setup_display_bx50v3(); +#endif + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + + +/* + * The SoM used by these boards has XTAL not connected despite datasheet + * suggesting connecting unused XTAL pins to ground. Without explicitly + * clearing the CRYSTAL bit the system runs unstable and sometimes reboots + * unexpectedly. + */ +static void pmic_crystal_fix(void) +{ + struct udevice *pmic; + static const uint EN_32K_CRYSTAL = (1 << 3); + + if (pmic_get("pmic@58", &pmic)) { + puts("failed to get device for PMIC\n"); + return; + } + + if (pmic_clrsetbits(pmic, DA9063_REG_EN_32K, EN_32K_CRYSTAL, 0) < 0) { + puts("failed to clear CRYSTAL bit\n"); + return; + } +} + +void pmic_init(void) +{ + struct udevice *reg; + int ret, i; + static const char * const bucks[] = { + "bcore1", + "bcore2", + "bpro", + "bmem", + "bio", + "bperi", + }; + + pmic_crystal_fix(); + + for (i = 0; i < ARRAY_SIZE(bucks); i++) { + ret = regulator_get_by_devname(bucks[i], ®); + if (reg < 0) { + printf("%s(): Unable to get regulator %s: %d\n", + __func__, bucks[i], ret); + continue; + } + regulator_set_mode(reg, DA9063_BUCKMODE_SYNC); + } +} + +static void detect_boot_cause(void) +{ + const char *cause = "POR"; + + if (is_b850v3()) + if (!gpio_get_value(PWGIN_IN)) + cause = "PM_WDOG"; + + env_set("bootcause", cause); +} + +int board_late_init(void) +{ + process_vpd(&vpd); + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + if (is_b850v3()) + env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60"); + else + env_set("videoargs", "video=LVDS-1:1024x768@65"); + + detect_boot_cause(); + + /* board specific pmic init */ + pmic_init(); + + check_time(); + + pci_init(); + + return 0; +} + +/* + * Removes the 'eth[0-9]*addr' environment variable with the given index + * + * @param index [in] the index of the eth_device whose variable is to be removed + */ +static void remove_ethaddr_env_var(int index) +{ + char env_var_name[9]; + + sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index); + env_set(env_var_name, NULL); +} + +int last_stage_init(void) +{ + int i; + + /* + * Remove first three ethaddr which may have been created by + * function process_vpd(). + */ + for (i = 0; i < 3; ++i) + remove_ethaddr_env_var(i); + + return 0; +} + +int checkboard(void) +{ + printf("BOARD: %s\n", CONFIG_BOARD_NAME); + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + char *rtc_status = env_get("rtc_status"); + + fdt_setprop(blob, 0, "ge,boot-ver", version_string, + strlen(version_string) + 1); + + fdt_setprop(blob, 0, "ge,rtc-status", rtc_status, + strlen(rtc_status) + 1); + return 0; +} +#endif + +int board_fit_config_name_match(const char *name) +{ + const char *machine = name; + + if (!vpd.is_read) + return strcmp(name, "imx6q-bx50v3"); + + if (!strncmp(machine, "Boot ", 5)) + machine += 5; + if (!strncmp(machine, "imx6q-", 6)) + machine += 6; + + switch (vpd.product_id) { + case VPD_PRODUCT_B450: + return strcasecmp(machine, "b450v3"); + case VPD_PRODUCT_B650: + return strcasecmp(machine, "b650v3"); + case VPD_PRODUCT_B850: + return strcasecmp(machine, "b850v3"); + default: + return -1; + } +} + +int embedded_dtb_select(void) +{ + vpd.is_read = false; + return fdtdec_setup(); +} diff --git a/roms/u-boot/board/ge/bx50v3/bx50v3.cfg b/roms/u-boot/board/ge/bx50v3/bx50v3.cfg new file mode 100644 index 000000000..de3955a94 --- /dev/null +++ b/roms/u-boot/board/ge/bx50v3/bx50v3.cfg @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +IMAGE_VERSION 2 +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* DDR IO */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 + +/* Calibrations */ +/* ZQ */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +/* write leveling */ +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F +/* Read DQS Gating calibration */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C +/* Read calibration */ +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042 +/* Write calibration */ +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E +/* read data bit delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* MMDC init */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 +DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000 + +/* Initialize Micron MT41J128M */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en 1 --> CKO1 enabled + * cko1_div 111 --> divide by 8 + * cko1_sel 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/roms/u-boot/board/ge/common/Kconfig b/roms/u-boot/board/ge/common/Kconfig new file mode 100644 index 000000000..323ed1f99 --- /dev/null +++ b/roms/u-boot/board/ge/common/Kconfig @@ -0,0 +1,7 @@ +config GE_VPD + bool "Enable GE VPD Support" + default y + +config GE_RTC + bool "Enable GE RTC Support" + default y diff --git a/roms/u-boot/board/ge/common/Makefile b/roms/u-boot/board/ge/common/Makefile new file mode 100644 index 000000000..8bd44e3c8 --- /dev/null +++ b/roms/u-boot/board/ge/common/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2017 General Electric Company + +obj-$(CONFIG_GE_VPD) += vpd_reader.o +obj-$(CONFIG_GE_RTC) += ge_rtc.o diff --git a/roms/u-boot/board/ge/common/ge_rtc.c b/roms/u-boot/board/ge/common/ge_rtc.c new file mode 100644 index 000000000..48c377804 --- /dev/null +++ b/roms/u-boot/board/ge/common/ge_rtc.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 General Electric Company + */ + +#include <common.h> +#include <env.h> +#include <dm/uclass.h> +#include <rtc.h> + +void check_time(void) +{ + struct udevice *dev; + int ret, i; + struct rtc_time tm; + u8 retry = 3; + + ret = uclass_get_device(UCLASS_RTC, 0, &dev); + if (ret) { + env_set("rtc_status", "FAIL"); + return; + } + + for (i = 0; i < retry; i++) { + ret = dm_rtc_get(dev, &tm); + if (!ret || ret == -EINVAL) + break; + } + + if (!ret && tm.tm_year > 2037) { + tm.tm_sec = 0; + tm.tm_min = 0; + tm.tm_hour = 0; + tm.tm_mday = 1; + tm.tm_wday = 2; + tm.tm_mon = 1; + tm.tm_year = 2036; + + for (i = 0; i < retry; i++) { + ret = dm_rtc_set(dev, &tm); + if (!ret) + break; + } + + if (ret >= 0) + ret = 2038; + } + + if (ret < 0) + env_set("rtc_status", "FAIL"); + else if (ret == 2038) + env_set("rtc_status", "2038"); + else + env_set("rtc_status", "OK"); +} + diff --git a/roms/u-boot/board/ge/common/ge_rtc.h b/roms/u-boot/board/ge/common/ge_rtc.h new file mode 100644 index 000000000..d33486d08 --- /dev/null +++ b/roms/u-boot/board/ge/common/ge_rtc.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 General Electric Company + */ + +void check_time(void); diff --git a/roms/u-boot/board/ge/common/vpd_reader.c b/roms/u-boot/board/ge/common/vpd_reader.c new file mode 100644 index 000000000..c28d2c03c --- /dev/null +++ b/roms/u-boot/board/ge/common/vpd_reader.c @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 General Electric Company + */ + +#include "vpd_reader.h" +#include <malloc.h> + +#include <i2c.h> +#include <linux/bch.h> +#include <stdlib.h> +#include <dm/uclass.h> +#include <i2c_eeprom.h> +#include <hexdump.h> + +/* BCH configuration */ + +const struct { + int header_ecc_capability_bits; + int data_ecc_capability_bits; + unsigned int prim_poly; + struct { + int min; + int max; + } galois_field_order; +} bch_configuration = { + .header_ecc_capability_bits = 4, + .data_ecc_capability_bits = 16, + .prim_poly = 0, + .galois_field_order = { + .min = 5, + .max = 15, + }, +}; + +static int calculate_galois_field_order(size_t source_length) +{ + int gfo = bch_configuration.galois_field_order.min; + + for (; gfo < bch_configuration.galois_field_order.max && + ((((1 << gfo) - 1) - ((int)source_length * 8)) < 0); + gfo++) { + } + + if (gfo == bch_configuration.galois_field_order.max) + return -1; + + return gfo + 1; +} + +static int verify_bch(int ecc_bits, unsigned int prim_poly, u8 *data, + size_t data_length, const u8 *ecc, size_t ecc_length) +{ + int gfo = calculate_galois_field_order(data_length); + + if (gfo < 0) + return -1; + + struct bch_control *bch = init_bch(gfo, ecc_bits, prim_poly); + + if (!bch) + return -1; + + if (bch->ecc_bytes != ecc_length) { + free_bch(bch); + return -1; + } + + unsigned int *errloc = (unsigned int *)calloc(data_length, + sizeof(unsigned int)); + int errors = decode_bch(bch, data, data_length, ecc, NULL, NULL, + errloc); + + free_bch(bch); + if (errors < 0) { + free(errloc); + return -1; + } + + if (errors > 0) { + for (int n = 0; n < errors; n++) { + if (errloc[n] >= 8 * data_length) { + /* + * n-th error located in ecc (no need for data + * correction) + */ + } else { + /* n-th error located in data */ + data[errloc[n] / 8] ^= 1 << (errloc[n] % 8); + } + } + } + + free(errloc); + return 0; +} + +static const int ID; +static const int LEN = 1; +static const int VER = 2; +static const int TYP = 3; +static const int BLOCK_SIZE = 4; + +static const u8 HEADER_BLOCK_ID; +static const u8 HEADER_BLOCK_LEN = 18; +static const u32 HEADER_BLOCK_MAGIC = 0xca53ca53; +static const size_t HEADER_BLOCK_VERIFY_LEN = 14; +static const size_t HEADER_BLOCK_ECC_OFF = 14; +static const size_t HEADER_BLOCK_ECC_LEN = 4; + +static const u8 ECC_BLOCK_ID = 0xFF; + +int vpd_reader(size_t size, u8 *data, struct vpd_cache *userdata, + int (*fn)(struct vpd_cache *, u8 id, u8 version, u8 type, + size_t size, u8 const *data)) +{ + if (size < HEADER_BLOCK_LEN || !data || !fn) + return -EINVAL; + + /* + * +--------------------+----------------+--//--+--------------------+ + * | header block | data block | ... | ecc block | + * +--------------------+----------------+--//--+--------------------+ + * : : : + * +------+-------+-----+ +------+-------------+ + * | id | magic | ecc | | ... | ecc | + * | len | off | | +------+-------------+ + * | ver | size | | : + * | type | | | : + * +------+-------+-----+ : + * : : : : + * <----- [1] ----> <--------- [2] ---------> + * + * Repair (if necessary) the contents of header block [1] by using a + * 4 byte ECC located at the end of the header block. A successful + * return value means that we can trust the header. + */ + int ret = verify_bch(bch_configuration.header_ecc_capability_bits, + bch_configuration.prim_poly, data, + HEADER_BLOCK_VERIFY_LEN, + &data[HEADER_BLOCK_ECC_OFF], HEADER_BLOCK_ECC_LEN); + if (ret < 0) + return ret; + + /* Validate header block { id, length, version, type }. */ + if (data[ID] != HEADER_BLOCK_ID || data[LEN] != HEADER_BLOCK_LEN || + data[VER] != 0 || data[TYP] != 0 || + ntohl(*(u32 *)(&data[4])) != HEADER_BLOCK_MAGIC) + return -EINVAL; + + u32 offset = ntohl(*(u32 *)(&data[8])); + u16 size_bits = ntohs(*(u16 *)(&data[12])); + + /* Check that ECC header fits. */ + if (offset + 3 >= size) + return -EINVAL; + + /* Validate ECC block. */ + u8 *ecc = &data[offset]; + + if (ecc[ID] != ECC_BLOCK_ID || ecc[LEN] < BLOCK_SIZE || + ecc[LEN] + offset > size || + ecc[LEN] - BLOCK_SIZE != size_bits / 8 || ecc[VER] != 1 || + ecc[TYP] != 1) + return -EINVAL; + + /* + * Use the header block to locate the ECC block and verify the data + * blocks [2] against the ecc block ECC. + */ + ret = verify_bch(bch_configuration.data_ecc_capability_bits, + bch_configuration.prim_poly, &data[data[LEN]], + offset - data[LEN], &data[offset + BLOCK_SIZE], + ecc[LEN] - BLOCK_SIZE); + if (ret < 0) + return ret; + + /* Stop after ECC. Ignore possible zero padding. */ + size = offset; + + for (;;) { + /* Move to next block. */ + size -= data[LEN]; + data += data[LEN]; + + if (size == 0) { + /* Finished iterating through blocks. */ + return 0; + } + + if (size < BLOCK_SIZE || data[LEN] < BLOCK_SIZE) { + /* Not enough data for a header, or short header. */ + return -EINVAL; + } + + ret = fn(userdata, data[ID], data[VER], data[TYP], + data[LEN] - BLOCK_SIZE, &data[BLOCK_SIZE]); + if (ret) + return ret; + } +} + +int read_i2c_vpd(struct vpd_cache *cache, + int (*process_block)(struct vpd_cache *, u8 id, u8 version, + u8 type, size_t size, u8 const *data)) +{ + struct udevice *dev; + int ret; + u8 *data; + int size; + + ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd@0", &dev); + if (ret) + return ret; + + size = i2c_eeprom_size(dev); + if (size < 0) { + printf("Unable to get size of eeprom: %d\n", ret); + return ret; + } + + data = malloc(size); + if (!data) + return -ENOMEM; + + ret = i2c_eeprom_read(dev, 0, data, size); + if (ret) { + free(data); + return ret; + } + + ret = vpd_reader(size, data, cache, process_block); + + free(data); + + return ret; +} diff --git a/roms/u-boot/board/ge/common/vpd_reader.h b/roms/u-boot/board/ge/common/vpd_reader.h new file mode 100644 index 000000000..0c51dc57e --- /dev/null +++ b/roms/u-boot/board/ge/common/vpd_reader.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 General Electric Company + */ + +#include "common.h" + +struct vpd_cache; + +/* + * Read VPD from given data, verify content, call callback for each vital + * product data block. + * + * cache: structure used by process block to store VPD information + * process_block: callback called for each VPD data block + * + * Returns Non-zero on error. Negative numbers encode errno. + */ +int read_i2c_vpd(struct vpd_cache *cache, + int (*process_block)(struct vpd_cache *, u8 id, u8 version, + u8 type, size_t size, u8 const *data)); + +/* + * Read VPD from given data, verify content, call callback for each vital + * product data block. + * + * size: size of the raw VPD data in bytes + * data: raw VPD data read from device + * cache: structure used by process block to store VPD information + * process_block: callback called for each VPD data block + * + * Returns Non-zero on error. Negative numbers encode errno. + */ + +int vpd_reader(size_t size, u8 *data, struct vpd_cache *cache, + int (*process_block)(struct vpd_cache *, u8 id, u8 version, u8 type, + size_t size, u8 const *data)); diff --git a/roms/u-boot/board/ge/mx53ppd/Kconfig b/roms/u-boot/board/ge/mx53ppd/Kconfig new file mode 100644 index 000000000..bebb2fab0 --- /dev/null +++ b/roms/u-boot/board/ge/mx53ppd/Kconfig @@ -0,0 +1,18 @@ + +if TARGET_MX53PPD + +config SYS_BOARD + default "mx53ppd" + +config SYS_VENDOR + default "ge" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "mx53ppd" + +source "board/ge/common/Kconfig" + +endif diff --git a/roms/u-boot/board/ge/mx53ppd/MAINTAINERS b/roms/u-boot/board/ge/mx53ppd/MAINTAINERS new file mode 100644 index 000000000..2c06c8ee8 --- /dev/null +++ b/roms/u-boot/board/ge/mx53ppd/MAINTAINERS @@ -0,0 +1,9 @@ +GE PPD BOARD +M: Antti Mäentausta <antti.maentausta@ge.com> +M: Ian Ray <ian.ray@ge.com> +M: Sebastian Reichel <sebastian.reichel@collabora.com> +S: Maintained +F: arch/arm/dts/imx53-ppd* +F: board/ge/mx53ppd/ +F: configs/mx53ppd_defconfig +F: include/configs/mx53ppd.h diff --git a/roms/u-boot/board/ge/mx53ppd/Makefile b/roms/u-boot/board/ge/mx53ppd/Makefile new file mode 100644 index 000000000..f423e80ca --- /dev/null +++ b/roms/u-boot/board/ge/mx53ppd/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2017 General Electric Company +# +# Based on board/freescale/mx53loco/Makefile: +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# Jason Liu <r64343@freescale.com> + +obj-y += mx53ppd.o +obj-$(CONFIG_DM_VIDEO) += mx53ppd_video.o diff --git a/roms/u-boot/board/ge/mx53ppd/imximage.cfg b/roms/u-boot/board/ge/mx53ppd/imximage.cfg new file mode 100644 index 000000000..1ee819839 --- /dev/null +++ b/roms/u-boot/board/ge/mx53ppd/imximage.cfg @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 General Electric Company + * + * Based on board/freescale/mx53loco/imximage.cfg: + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu <r64343@freescale.com> + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x53fa8004 0x00194005 +DATA 4 0x53fa8554 0x00300000 +DATA 4 0x53fa8558 0x00300040 +DATA 4 0x53fa8560 0x00300000 +DATA 4 0x53fa8564 0x00300040 +DATA 4 0x53fa8568 0x00300040 +DATA 4 0x53fa8570 0x00300000 +DATA 4 0x53fa8574 0x00300000 +DATA 4 0x53fa8578 0x00300000 +DATA 4 0x53fa857c 0x00300040 +DATA 4 0x53fa8580 0x00300040 +DATA 4 0x53fa8584 0x00300000 +DATA 4 0x53fa8588 0x00300000 +DATA 4 0x53fa8590 0x00300040 +DATA 4 0x53fa8594 0x00300000 +DATA 4 0x53fa86f0 0x00300000 +DATA 4 0x53fa86f4 0x00000000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8718 0x00300000 +DATA 4 0x53fa871c 0x00300000 +DATA 4 0x53fa8720 0x00300000 +DATA 4 0x53fa8728 0x00300000 +DATA 4 0x53fa872c 0x00300000 +DATA 4 0x63fd9088 0x35343535 +DATA 4 0x63fd9090 0x4d444c44 +DATA 4 0x63fd907c 0x01370138 +DATA 4 0x63fd9080 0x013b013c +DATA 4 0x63fd9018 0x00111740 +DATA 4 0x63fd9000 0x85190000 +DATA 4 0x63fd900c 0x8b8f52e3 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x008f0e21 +DATA 4 0x63fd9008 0x09333030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00468031 +DATA 4 0x63fd901c 0x052080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x05208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00005800 +DATA 4 0x63fd9040 0x05380003 +DATA 4 0x63fd9058 0x00011110 +DATA 4 0x63fd901c 0x00000000 diff --git a/roms/u-boot/board/ge/mx53ppd/mx53ppd.c b/roms/u-boot/board/ge/mx53ppd/mx53ppd.c new file mode 100644 index 000000000..6174125e7 --- /dev/null +++ b/roms/u-boot/board/ge/mx53ppd/mx53ppd.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 General Electric Company + * + * Based on board/freescale/mx53loco/mx53loco.c: + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu <r64343@freescale.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux-mx53.h> +#include <asm/arch/clock.h> +#include <env.h> +#include <linux/errno.h> +#include <linux/libfdt.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/mach-imx/mx5_video.h> +#include <netdev.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc_imx.h> +#include <asm/gpio.h> +#include <power/pmic.h> +#include <dialog_pmic.h> +#include <fsl_pmic.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <version.h> +#include <watchdog.h> +#include "ppd_gpio.h" +#include <stdlib.h> +#include "../../ge/common/ge_rtc.h" +#include "../../ge/common/vpd_reader.h" + +DECLARE_GLOBAL_DATA_PTR; + +static u32 mx53_dram_size[2]; + +phys_size_t get_effective_memsize(void) +{ + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return mx53_dram_size[0]; +} + +int dram_init(void) +{ + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); + + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev() & ~(0xF << 8); +} + +#ifdef CONFIG_USB_EHCI_MX5 +int board_ehci_hcd_init(int port) +{ + /* request VBUS power enable pin, GPIO7_8 */ + imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8); + gpio_direction_output(IMX_GPIO_NR(7, 8), 1); + return 0; +} +#endif + +static int clock_1GHz(void) +{ + int ret; + u32 ref_clk = MXC_HCLK; + /* + * After increasing voltage to 1.25V, we can switch + * CPU clock to 1GHz and DDR to 400MHz safely + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (ret) { + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + return -1; + } + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) { + printf("CPU: Switch DDR clock to 400MHz failed\n"); + return -1; + } + + return 0; +} + +void ppd_gpio_init(void) +{ + int i; + + imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads)); + for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i) { + gpio_request(ppd_gpios[i].gpio, "request"); + gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value); + } +} + +int board_early_init_f(void) +{ + ppd_gpio_init(); + + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#define VPD_TYPE_INVALID 0x00 +#define VPD_BLOCK_NETWORK 0x20 +#define VPD_BLOCK_HWID 0x44 +#define VPD_PRODUCT_PPD 4 +#define VPD_HAS_MAC1 0x1 +#define VPD_MAC_ADDRESS_LENGTH 6 + +struct vpd_cache { + u8 product_id; + u8 has; + unsigned char mac1[VPD_MAC_ADDRESS_LENGTH]; +}; + +/* + * Extracts MAC and product information from the VPD. + */ +static int vpd_callback(struct vpd_cache *userdata, u8 id, u8 version, + u8 type, size_t size, u8 const *data) +{ + struct vpd_cache *vpd = userdata; + + if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID && + size >= 1) { + vpd->product_id = data[0]; + + } else if (id == VPD_BLOCK_NETWORK && version == 1 && + type != VPD_TYPE_INVALID) { + if (size >= 6) { + vpd->has |= VPD_HAS_MAC1; + memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH); + } + } + + return 0; +} + +static void process_vpd(struct vpd_cache *vpd) +{ + int fec_index = -1; + + if (vpd->product_id == VPD_PRODUCT_PPD) + fec_index = 0; + + if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1)) + eth_env_set_enetaddr("ethaddr", vpd->mac1); +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + mxc_set_sata_internal_clock(); + + return 0; +} + +int misc_init_r(void) +{ + const char *cause; + + /* We care about WDOG only, treating everything else as + * a power-on-reset. + */ + if (get_imx_reset_cause() & 0x0010) + cause = "WDOG"; + else + cause = "POR"; + + env_set("bootcause", cause); + + return 0; +} + +int board_late_init(void) +{ + int res; + struct vpd_cache vpd; + + memset(&vpd, 0, sizeof(vpd)); + res = read_i2c_vpd(&vpd, vpd_callback); + if (!res) + process_vpd(&vpd); + else + printf("Can't read VPD"); + + res = clock_1GHz(); + if (res != 0) + return res; + + print_cpuinfo(); + + check_time(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: GE PPD\n"); + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + char *rtc_status = env_get("rtc_status"); + + fdt_setprop(blob, 0, "ge,boot-ver", version_string, + strlen(version_string) + 1); + + fdt_setprop(blob, 0, "ge,rtc-status", rtc_status, + strlen(rtc_status) + 1); + return 0; +} +#endif diff --git a/roms/u-boot/board/ge/mx53ppd/mx53ppd_video.c b/roms/u-boot/board/ge/mx53ppd/mx53ppd_video.c new file mode 100644 index 000000000..3240ed62a --- /dev/null +++ b/roms/u-boot/board/ge/mx53ppd/mx53ppd_video.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 General Electric Company + * + * Based on board/freescale/mx53loco/mx53loco_video.c: + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Fabio Estevam <fabio.estevam@freescale.com> + */ + +#include <common.h> +#include <dm.h> +#include <linux/list.h> +#include <asm/arch/iomux-mx53.h> +#include <asm/mach-imx/video.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/io.h> +#include <panel.h> + +static int detect_lcd(struct display_info_t const *dev) +{ + return 1; +} + +static void lcd_enable(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* Set LDB_DI0 as clock source for IPU_DI0 */ + clrsetbits_le32(&mxc_ccm->cscmr2, + MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK, + MXC_CCM_CSCMR2_DI0_CLK_SEL( + MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK)); + + /* Turn on IPU LDB DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3)); + + /* Turn on IPU DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3)); + + /* Configure LDB */ + writel(IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, + &iomux->gpr[2]); +} + +static void do_enable_backlight(struct display_info_t const *dev) +{ + struct udevice *panel; + int ret; + + lcd_enable(); + + ret = uclass_get_device(UCLASS_PANEL, 0, &panel); + if (ret) { + printf("Could not find panel: %d\n", ret); + return; + } + + panel_set_backlight(panel, 100); + panel_enable_backlight(panel); +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = -1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_lcd, + .enable = do_enable_backlight, + .mode = { + .name = "NV-SPWGRGB888", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 15384, + .left_margin = 16, + .right_margin = 210, + .upper_margin = 10, + .lower_margin = 22, + .hsync_len = 30, + .vsync_len = 13, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } + } +}; + +size_t display_count = ARRAY_SIZE(displays); + diff --git a/roms/u-boot/board/ge/mx53ppd/ppd_gpio.h b/roms/u-boot/board/ge/mx53ppd/ppd_gpio.h new file mode 100644 index 000000000..98c41d4d6 --- /dev/null +++ b/roms/u-boot/board/ge/mx53ppd/ppd_gpio.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 General Electric Company + */ + +#ifndef __PPD_GPIO_H_ +#define __PPD_GPIO_H_ + +#include <asm/arch/iomux-mx53.h> +#include <asm/gpio.h> + +static const iomux_v3_cfg_t ppd_pads[] = { + /* FEC */ + MX53_PAD_EIM_A22__GPIO2_16, + /* Video */ + MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */ + MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */ + MX53_PAD_CSI0_DAT10__GPIO5_28, /* DATA_WIDTH_CTRL */ + MX53_PAD_CSI0_PIXCLK__GPIO5_18, /* HOST_CONTROLLED_RESET_TO_LCD_N */ + MX53_PAD_EIM_DA2__GPIO3_2, /* LVDS1_MUX_CTRL */ + MX53_PAD_EIM_DA3__GPIO3_3, /* LVDS0_MUX_CTRL */ + MX53_PAD_EIM_A21__GPIO2_17, /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ + MX53_PAD_CSI0_DAT11__GPIO5_29, /* BACKLIGHT_ENABLE */ + MX53_PAD_DISP0_DAT9__PWM2_PWMO, /* IMX535_PWM2_TO_LCD_CONNECTOR */ + /* I2C */ + MX53_PAD_EIM_A20__GPIO2_18, /* RESET_I2C1_BUS_SEGMENT_MUX_N */ + + /* SPI */ + MX53_PAD_DISP0_DAT23__GPIO5_17, + MX53_PAD_KEY_COL2__GPIO4_10, + MX53_PAD_KEY_ROW2__GPIO4_11, + MX53_PAD_KEY_COL3__GPIO4_12, + + MX53_PAD_PATA_DATA7__GPIO2_7, /* BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */ +}; + +struct gpio_cfg { + unsigned int gpio; + int value; +}; + +#define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16) +#define UD_SCAN_CTRL IMX_GPIO_NR(5, 21) +#define LR_SCAN_CTRL IMX_GPIO_NR(5, 20) +#define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3) +#define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2) +#define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18) +#define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28) +#define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28) +#define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29) +#define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22) +#define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27) +#define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17) +#define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18) +#define ECSPI1_CS0 IMX_GPIO_NR(5, 17) +#define ECSPI1_CS1 IMX_GPIO_NR(4, 10) +#define ECSPI1_CS2 IMX_GPIO_NR(4, 11) +#define ECSPI1_CS3 IMX_GPIO_NR(4, 12) +#define BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N IMX_GPIO_NR(2, 7) + +static const struct gpio_cfg ppd_gpios[] = { + /* FEC */ + /* Drive Low as GPIO output for 25ms per Eth Phy IX spec */ + /* Then Drive High as GPIO output to bring Eth Phy IC out of reset */ + { RESET_IMX535_ETHERNET_PHY_N, 0 }, + { RESET_IMX535_ETHERNET_PHY_N, 1 }, + /* Video */ + { UD_SCAN_CTRL, 0 }, + { LR_SCAN_CTRL, 1 }, +#ifdef PROPRIETARY_CHANGES + { LVDS0_MUX_CTRL, 1 }, +#else + { LVDS0_MUX_CTRL, 0 }, +#endif + { LVDS1_MUX_CTRL, 1 }, + { HOST_CONTROLLED_RESET_TO_LCD_N, 1 }, + { DATA_WIDTH_CTRL, 0 }, + { RESET_DP0_TRANSMITTER_N, 1 }, + { RESET_DP1_TRANSMITTER_N, 1 }, + { POWER_DOWN_LVDS0_DESERIALIZER_N, 1 }, + { POWER_DOWN_LVDS1_DESERIALIZER_N, 1 }, + { ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 }, + { RESET_I2C1_BUS_SEGMENT_MUX_N, 1 }, + { ECSPI1_CS0, 1 }, + { ECSPI1_CS1, 1 }, + { ECSPI1_CS2, 1 }, + { ECSPI1_CS3, 1 }, + { BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N, 1 }, +}; + +#endif /* __PPD_GPIO_H_ */ |