diff options
Diffstat (limited to 'roms/u-boot/board/google')
44 files changed, 3285 insertions, 0 deletions
diff --git a/roms/u-boot/board/google/Kconfig b/roms/u-boot/board/google/Kconfig new file mode 100644 index 000000000..22c4be392 --- /dev/null +++ b/roms/u-boot/board/google/Kconfig @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + +if VENDOR_GOOGLE + +choice + prompt "Mainboard model" + optional + +config TARGET_CHROMEBOOK_CORAL + bool "Chromebook coral" + help + This is a range of Intel-based laptops released in 2018. They use an + Intel Apollo Lake SoC. The design supports WiFi, 4GB to 16GB of + LPDDR4 1600MHz SDRAM, PCIe WiFi and Bluetooth, eMMC (typically 32GB), + up two cameras (front-facing 720p and another 5MP option), USB SD + reader, microphone and speakers. It also includes two USB 3 Type A and + two Type C ports. The latter are used as power input and can also + charge external devices as well as a 4K external display. There is a + Chrome OS EC connected on LPC, a Cr50 secure chip from Google and + various display options. OEMs products include Acer Chromebook 11 + (e.g. C732, CB11, CP311) and Lenovo Chromebook (100e, 300e, 500e). + +config TARGET_CHROMEBOOK_LINK + bool "Chromebook link" + help + This is the Chromebook Pixel released in 2013. It uses an Intel + i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of + SDRAM. It has a Panther Point platform controller hub, PCIe + WiFi and Bluetooth. It also includes a 720p webcam, USB SD + reader, microphone and speakers, display port and 32GB SATA + solid state drive. There is a Chrome OS EC connected on LPC, + and it provides a 2560x1700 high resolution touch-enabled LCD + display. + +config TARGET_CHROMEBOOK_LINK64 + bool "Chromebook link 64-bit" + help + This is the Chromebook Pixel released in 2013. With this config + U-Boot is built as a 64-bit binary. This allows testing while this + feature is being completed. + +config TARGET_CHROMEBOX_PANTHER + bool "Chromebox panther (not available)" + help + Note: At present this must be used with coreboot. See README.x86 + for instructions. + + This is the Asus Chromebox CN60 released in 2014. It uses an Intel + Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a + Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also + includes a USB SD reader, four USB3 ports, display port and HDMI + video output and a 16GB SATA solid state drive. There is no Chrome + OS EC on this model. + +config TARGET_CHROMEBOOK_SAMUS + bool "Chromebook samus" + help + This is the Chromebook Pixel released in 2015. It uses an Intel + Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of + LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a + 720p webcam, USB SD reader, microphone and speakers, 2 USB 3 Type + C ports which can support charging and up to a 4K external display. + There is a solid state drive, either 32GB or 64GB. There is a + Chrome OS EC connected on LPC, and it provides a 2560x1700 high + resolution touch-enabled LCD display. + +config TARGET_CHROMEBOOK_SAMUS_TPL + bool "Chromebook samus booting from TPL" + help + This is a version of Samus which boots into TPL, then to SPL and + U-Boot proper. This is useful where verified boot must select + between different A/B versions of SPL/U-Boot, to allow upgrading of + almost all U-Boot code in the field. + +endchoice + +source "board/google/chromebook_coral/Kconfig" +source "board/google/chromebook_link/Kconfig" +source "board/google/chromebox_panther/Kconfig" +source "board/google/chromebook_samus/Kconfig" + +endif diff --git a/roms/u-boot/board/google/chromebook_coral/Kconfig b/roms/u-boot/board/google/chromebook_coral/Kconfig new file mode 100644 index 000000000..53c651c3f --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/Kconfig @@ -0,0 +1,44 @@ +if TARGET_CHROMEBOOK_CORAL + +config SYS_BOARD + default "chromebook_coral" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "apollolake" + +config SYS_CONFIG_NAME + default "chromebook_coral" + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select USE_EARLY_BOARD_INIT + select INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + +config PCIE_ECAM_BASE + default 0xe0000000 + +config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + help + Allow post codes to be sent to the Chroem OS EC early during boot, + to enable monitoring of the boot and debugging when things go wrong. + With this option enabled, the EC console can be used to watch post + codes the first part of boot. + +config SYS_CAR_ADDR + hex + default 0xfef00000 + +config SYS_CAR_SIZE + hex + default 0xc0000 + +endif diff --git a/roms/u-boot/board/google/chromebook_coral/MAINTAINERS b/roms/u-boot/board/google/chromebook_coral/MAINTAINERS new file mode 100644 index 000000000..904227e2e --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK_CORAL_BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/chromebook_coral/ +F: include/configs/chromebook_coral.h +F: configs/chromebook_coral_defconfig diff --git a/roms/u-boot/board/google/chromebook_coral/Makefile b/roms/u-boot/board/google/chromebook_coral/Makefile new file mode 100644 index 000000000..f7a0ca6cc --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += coral.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/roms/u-boot/board/google/chromebook_coral/baseboard_dptf.asl b/roms/u-boot/board/google/chromebook_coral/baseboard_dptf.asl new file mode 100644 index 000000000..5da963a67 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/baseboard_dptf.asl @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 120 +#define DPTF_TSR0_CRITICAL 125 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 46 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 58 +#define DPTF_TSR2_CRITICAL 90 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/roms/u-boot/board/google/chromebook_coral/coral.c b/roms/u-boot/board/google/chromebook_coral/coral.c new file mode 100644 index 000000000..3f9235c90 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/coral.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + */ + +#define LOG_CATEGORY UCLASS_SYSINFO + +#include <common.h> +#include <bloblist.h> +#include <command.h> +#include <cros_ec.h> +#include <dm.h> +#include <log.h> +#include <sysinfo.h> +#include <acpi/acpigen.h> +#include <asm-generic/gpio.h> +#include <asm/acpi_nhlt.h> +#include <asm/intel_gnvs.h> +#include <asm/intel_pinctrl.h> +#include <dm/acpi.h> +#include <linux/delay.h> +#include "variant_gpio.h" + +struct cros_gpio_info { + const char *linux_name; + enum cros_gpio_t type; + int gpio_num; + int flags; +}; + +int arch_misc_init(void) +{ + return 0; +} + +static int get_memconfig(struct udevice *dev) +{ + struct gpio_desc gpios[4]; + int cfg; + int ret; + + ret = gpio_request_list_by_name(dev, "memconfig-gpios", gpios, + ARRAY_SIZE(gpios), + GPIOD_IS_IN | GPIOD_PULL_UP); + if (ret < 0) { + log_debug("Cannot get GPIO list '%s' (%d)\n", dev->name, ret); + return ret; + } + + /* Give the lines time to settle */ + udelay(10); + + ret = dm_gpio_get_values_as_int(gpios, ARRAY_SIZE(gpios)); + if (ret < 0) + return log_msg_ret("get", ret); + cfg = ret; + + ret = gpio_free_list(dev, gpios, ARRAY_SIZE(gpios)); + if (ret) + return log_msg_ret("free", ret); + + return cfg; +} + +/** + * get_skuconfig() - Get the SKU number either from pins or the EC + * + * Two options are supported: + * skuconfig-gpios - two pins in the device tree (tried first) + * EC - reading from the EC (backup) + * + * @dev: sysinfo device to use + * @return SKU ID, or -ve error if not found + */ +static int get_skuconfig(struct udevice *dev) +{ + struct gpio_desc gpios[2]; + int cfg; + int ret; + + ret = gpio_request_list_by_name(dev, "skuconfig-gpios", gpios, + ARRAY_SIZE(gpios), + GPIOD_IS_IN); + if (ret != ARRAY_SIZE(gpios)) { + struct udevice *cros_ec; + + log_debug("Cannot get GPIO list '%s' (%d)\n", dev->name, ret); + + /* Try the EC */ + ret = uclass_first_device_err(UCLASS_CROS_EC, &cros_ec); + if (ret < 0) { + log_err("Cannot find EC for SKU details\n"); + return log_msg_ret("sku", ret); + } + ret = cros_ec_get_sku_id(cros_ec); + if (ret < 0) { + log_err("Cannot read SKU details\n"); + return log_msg_ret("sku", ret); + } + + return ret; + } + + ret = dm_gpio_get_values_as_int_base3(gpios, ARRAY_SIZE(gpios)); + if (ret < 0) + return log_msg_ret("get", ret); + cfg = ret; + + ret = gpio_free_list(dev, gpios, ARRAY_SIZE(gpios)); + if (ret) + return log_msg_ret("free", ret); + + return cfg; +} + +static int coral_get_str(struct udevice *dev, int id, size_t size, char *val) +{ + int ret; + + if (IS_ENABLED(CONFIG_SPL_BUILD)) + return -ENOSYS; + + switch (id) { + case SYSINFO_ID_SMBIOS_SYSTEM_VERSION: + case SYSINFO_ID_SMBIOS_BASEBOARD_VERSION: { + ret = get_skuconfig(dev); + + if (ret < 0) + return ret; + if (size < 15) + return -ENOSPC; + sprintf(val, "rev%d", ret); + break; + } + case SYSINFO_ID_BOARD_MODEL: { + int mem_config, sku_config; + const char *model; + + ret = get_memconfig(dev); + if (ret < 0) + log_warning("Unable to read memconfig (err=%d)\n", ret); + mem_config = ret; + ret = get_skuconfig(dev); + if (ret < 0) + log_warning("Unable to read skuconfig (err=%d)\n", ret); + sku_config = ret; + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + snprintf(val, size, "%s (memconfig %d, SKU %d)", model, + mem_config, sku_config); + break; + } + default: + return -ENOENT; + } + + return 0; +} + +int chromeos_get_gpio(const struct udevice *dev, const char *prop, + enum cros_gpio_t type, struct cros_gpio_info *info) +{ + struct udevice *pinctrl; + struct gpio_desc desc; + int ret; + + ret = gpio_request_by_name((struct udevice *)dev, prop, 0, &desc, 0); + if (ret == -ENOTBLK) { + info->gpio_num = CROS_GPIO_VIRTUAL; + log_debug("GPIO '%s' is virtual\n", prop); + } else if (ret) { + return log_msg_ret("gpio", ret); + } else { + info->gpio_num = desc.offset; + dm_gpio_free((struct udevice *)dev, &desc); + } + info->linux_name = dev_read_string(desc.dev, "linux-name"); + if (!info->linux_name) + return log_msg_ret("linux-name", -ENOENT); + info->type = type; + /* Get ACPI pin from GPIO library if available */ + if (info->gpio_num != CROS_GPIO_VIRTUAL) { + pinctrl = dev_get_parent(desc.dev); + info->gpio_num = intel_pinctrl_get_acpi_pin(pinctrl, + info->gpio_num); + } + info->flags = desc.flags & GPIOD_ACTIVE_LOW ? CROS_GPIO_ACTIVE_LOW : + CROS_GPIO_ACTIVE_HIGH; + if (!ret) + dm_gpio_free(desc.dev, &desc); + + return 0; +} + +static int chromeos_acpi_gpio_generate(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct cros_gpio_info info[3]; + int count, i; + int ret; + + count = 3; + ret = chromeos_get_gpio(dev, "recovery-gpios", CROS_GPIO_REC, &info[0]); + if (ret) + return log_msg_ret("rec", ret); + ret = chromeos_get_gpio(dev, "write-protect-gpios", CROS_GPIO_WP, + &info[1]); + if (ret) + return log_msg_ret("wp", ret); + ret = chromeos_get_gpio(dev, "phase-enforce-gpios", CROS_GPIO_PE, + &info[2]); + if (ret) + return log_msg_ret("phase", ret); + acpigen_write_scope(ctx, "\\"); + acpigen_write_name(ctx, "OIPG"); + acpigen_write_package(ctx, count); + for (i = 0; i < count; i++) { + acpigen_write_package(ctx, 4); + acpigen_write_integer(ctx, info[i].type); + acpigen_write_integer(ctx, info[i].flags); + acpigen_write_integer(ctx, info[i].gpio_num); + acpigen_write_string(ctx, info[i].linux_name); + acpigen_pop_len(ctx); + } + + acpigen_pop_len(ctx); + acpigen_pop_len(ctx); + + return 0; +} + +static int coral_write_acpi_tables(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct acpi_global_nvs *gnvs; + struct nhlt *nhlt; + const char *oem_id = "coral"; + const char *oem_table_id = "coral"; + u32 oem_revision = 3; + int ret; + + gnvs = bloblist_find(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs)); + if (!gnvs) + return log_msg_ret("bloblist", -ENOENT); + + nhlt = nhlt_init(); + if (!nhlt) + return -ENOMEM; + + log_debug("Setting up NHLT\n"); + ret = acpi_setup_nhlt(ctx, nhlt); + if (ret) + return log_msg_ret("setup", ret); + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)ctx->current; + gnvs->nhll = nhlt_current_size(nhlt); + + ret = nhlt_serialise_oem_overrides(ctx, nhlt, oem_id, oem_table_id, + oem_revision); + if (ret) + return log_msg_ret("serialise", ret); + + return 0; +} + +struct acpi_ops coral_acpi_ops = { + .write_tables = coral_write_acpi_tables, + .inject_dsdt = chromeos_acpi_gpio_generate, +}; + +struct sysinfo_ops coral_sysinfo_ops = { + .get_str = coral_get_str, +}; + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) +static const struct udevice_id coral_ids[] = { + { .compatible = "google,coral" }, + { } +}; +#endif + +U_BOOT_DRIVER(coral_drv) = { + .name = "coral", + .id = UCLASS_SYSINFO, + .of_match = of_match_ptr(coral_ids), + .ops = &coral_sysinfo_ops, + ACPI_OPS_PTR(&coral_acpi_ops) +}; diff --git a/roms/u-boot/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat b/roms/u-boot/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat Binary files differnew file mode 100644 index 000000000..46c0efbd0 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat diff --git a/roms/u-boot/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat b/roms/u-boot/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat Binary files differnew file mode 100644 index 000000000..6a7f2cef4 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat diff --git a/roms/u-boot/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat b/roms/u-boot/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat Binary files differnew file mode 100644 index 000000000..71d764820 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat diff --git a/roms/u-boot/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat b/roms/u-boot/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat Binary files differnew file mode 100644 index 000000000..142ab353f --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat diff --git a/roms/u-boot/board/google/chromebook_coral/dsdt.asl b/roms/u-boot/board/google/chromebook_coral/dsdt.asl new file mode 100644 index 000000000..b51e0b050 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/dsdt.asl @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Google Inc. + */ + +#include "variant_ec.h" +#include "variant_gpio.h" +#include <acpi/acpi_table.h> +#include <asm/acpi/global_nvs.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + OEM_TABLE_ID, + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include <asm/arch/acpi/globalnvs.asl> + + /* CPU */ + #include <asm/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <asm/arch/acpi/northbridge.asl> + #include <asm/arch/acpi/southbridge.asl> + #include <asm/arch/acpi/pch_hda.asl> + } + } + + /* Chrome OS specific */ + #include <asm/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <asm/acpi/sleepstates.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <asm/acpi/cros_ec/superio.asl> + /* ACPI code for EC functions */ + #include <asm/acpi/cros_ec/ec.asl> + } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include "variant_dptf.asl" + /* Include soc specific DPTF changes */ + #include <asm/arch/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <asm/acpi/dptf/dptf.asl> + } +} diff --git a/roms/u-boot/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat b/roms/u-boot/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat Binary files differnew file mode 100644 index 000000000..b0b5b9ba6 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat diff --git a/roms/u-boot/board/google/chromebook_coral/variant_dptf.asl b/roms/u-boot/board/google/chromebook_coral/variant_dptf.asl new file mode 100644 index 000000000..943ebeaac --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/variant_dptf.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Google Inc. + */ + +#include "baseboard_dptf.asl" diff --git a/roms/u-boot/board/google/chromebook_coral/variant_ec.h b/roms/u-boot/board/google/chromebook_coral/variant_ec.h new file mode 100644 index 000000000..7d5e1a674 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/variant_ec.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC +/* + * Taken from coreboot file of the same name + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include "variant_gpio.h" +#include <ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define EC_ENABLE_TBMC_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/roms/u-boot/board/google/chromebook_coral/variant_gpio.h b/roms/u-boot/board/google/chromebook_coral/variant_gpio.h new file mode 100644 index 000000000..403e2419a --- /dev/null +++ b/roms/u-boot/board/google/chromebook_coral/variant_gpio.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + * + * Taken from coreboot file of the same name + */ + +#ifndef BASEBOARD_GPIO_H +#define BASEBOARD_GPIO_H + +#include <asm/arch/gpio.h> +#include <ec_commands.h> + +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 + +/* EC SMI */ +#define EC_SMI_GPI GPIO_49 + +/* + * On lidopen/lidclose GPIO_22 from North Community gets toggled and + * is used in _PRW to wake up device from sleep. GPIO_22 maps to + * group GPIO_GPE_N_31_0 and the pad is configured as SCI with + * EDGE_SINGLE and INVERT. + */ +#define GPE_EC_WAKE GPE0_DW1_22 + +/* Write Protect and indication if EC is in RW code. */ +#define GPIO_PCH_WP GPIO_75 +#define GPIO_EC_IN_RW GPIO_41 +/* Determine if board is in final shipping mode. */ +#define GPIO_SHIP_MODE GPIO_10 + +/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */ +#define DMIC_CONFIG_PIN GPIO_17 + +#ifndef __ASSEMBLY__ + +enum cros_gpio_t { + CROS_GPIO_REC = 1, /* Recovery */ + + /* Developer; * deprecated (chromium:942901) */ + CROS_GPIO_DEPRECATED_DEV = 2, + CROS_GPIO_WP = 3, /* Write Protect */ + CROS_GPIO_PE = 4, /* Phase enforcement for final product */ + + CROS_GPIO_ACTIVE_LOW = 0, + CROS_GPIO_ACTIVE_HIGH = 1, + + CROS_GPIO_VIRTUAL = -1, +}; +#endif + +#endif /* BASEBOARD_GPIO_H */ diff --git a/roms/u-boot/board/google/chromebook_link/Kconfig b/roms/u-boot/board/google/chromebook_link/Kconfig new file mode 100644 index 000000000..dd29ddf69 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_link/Kconfig @@ -0,0 +1,43 @@ +if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64 + +config SYS_BOARD + default "chromebook_link" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "chromebook_link" + +config SYS_TEXT_BASE + default 0xfff00000 if !SUPPORT_SPL + default 0x10000000 if SUPPORT_SPL + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select USE_EARLY_BOARD_INIT + select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_INTEL_ME + select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND + +config PCIE_ECAM_BASE + default 0xf0000000 + +config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + default y + +config SYS_CAR_ADDR + hex + default 0xff7e0000 + +config SYS_CAR_SIZE + hex + default 0x20000 + +endif diff --git a/roms/u-boot/board/google/chromebook_link/MAINTAINERS b/roms/u-boot/board/google/chromebook_link/MAINTAINERS new file mode 100644 index 000000000..e7aef5339 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_link/MAINTAINERS @@ -0,0 +1,13 @@ +CHROMEBOOK LINK BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/chromebook_link/ +F: include/configs/chromebook_link.h +F: configs/chromebook_link_defconfig + +CHROMEBOOK LINK 64-bit BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/chromebook_link/ +F: include/configs/chromebook_link.h +F: configs/chromebook_link64_defconfig diff --git a/roms/u-boot/board/google/chromebook_link/Makefile b/roms/u-boot/board/google/chromebook_link/Makefile new file mode 100644 index 000000000..d84a84899 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_link/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2011 The Chromium OS Authors. +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + +obj-y += link.o diff --git a/roms/u-boot/board/google/chromebook_link/link.c b/roms/u-boot/board/google/chromebook_link/link.c new file mode 100644 index 000000000..e357e6218 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_link/link.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014 Google, Inc + */ + +#include <common.h> diff --git a/roms/u-boot/board/google/chromebook_samus/Kconfig b/roms/u-boot/board/google/chromebook_samus/Kconfig new file mode 100644 index 000000000..9f66d7998 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_samus/Kconfig @@ -0,0 +1,52 @@ +if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL + +config SYS_BOARD + default "chromebook_samus" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "broadwell" + +config SYS_CONFIG_NAME + default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS + default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select USE_EARLY_BOARD_INIT + select INTEL_BROADWELL + select HAVE_INTEL_ME + select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND + +config PCIE_ECAM_BASE + default 0xf0000000 + +config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + default y + +config SYS_CAR_ADDR + hex + default 0xff7c0000 + +config SYS_CAR_SIZE + hex + default 0x40000 + +endif + +if TARGET_CHROMEBOOK_SAMUS_TPL + +config BOARD_SPECIFIC_OPTIONS_TPL # dummy + def_bool y + select SPL + select TPL + +endif diff --git a/roms/u-boot/board/google/chromebook_samus/MAINTAINERS b/roms/u-boot/board/google/chromebook_samus/MAINTAINERS new file mode 100644 index 000000000..ca4b16500 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_samus/MAINTAINERS @@ -0,0 +1,13 @@ +CHROMEBOOK SAMUS BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/chromebook_samus/ +F: include/configs/chromebook_samus.h +F: configs/chromebook_samus_defconfig + +CHROMEBOOK SAMUS TPL BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/chromebook_samus/ +F: include/configs/chromebook_samus.h +F: configs/chromebook_samus_tpl_defconfig diff --git a/roms/u-boot/board/google/chromebook_samus/Makefile b/roms/u-boot/board/google/chromebook_samus/Makefile new file mode 100644 index 000000000..68c9e4993 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_samus/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2016 Google, Inc + +obj-y += samus.o diff --git a/roms/u-boot/board/google/chromebook_samus/samus.c b/roms/u-boot/board/google/chromebook_samus/samus.c new file mode 100644 index 000000000..83edf8910 --- /dev/null +++ b/roms/u-boot/board/google/chromebook_samus/samus.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Google, Inc + */ + +#include <common.h> diff --git a/roms/u-boot/board/google/chromebox_panther/Kconfig b/roms/u-boot/board/google/chromebox_panther/Kconfig new file mode 100644 index 000000000..875df9d59 --- /dev/null +++ b/roms/u-boot/board/google/chromebox_panther/Kconfig @@ -0,0 +1,35 @@ +if TARGET_CHROMEBOX_PANTHER + +config SYS_BOARD + default "chromebox_panther" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "chromebox_panther" + +config SYS_TEXT_BASE + default 0xfff00000 + +# Panther actually uses haswell, not ivybridge, so this is just a placeholder +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_INTEL_ME + select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND + +config SYS_CAR_ADDR + hex + default 0xff7e0000 + +config SYS_CAR_SIZE + hex + default 0x20000 + +endif diff --git a/roms/u-boot/board/google/chromebox_panther/MAINTAINERS b/roms/u-boot/board/google/chromebox_panther/MAINTAINERS new file mode 100644 index 000000000..c88774bc8 --- /dev/null +++ b/roms/u-boot/board/google/chromebox_panther/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOX PANTHER BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/chromebook_panther/ +F: include/configs/chromebox_panther.h +F: configs/chromebox_panther_defconfig diff --git a/roms/u-boot/board/google/chromebox_panther/Makefile b/roms/u-boot/board/google/chromebox_panther/Makefile new file mode 100644 index 000000000..1a5518f13 --- /dev/null +++ b/roms/u-boot/board/google/chromebox_panther/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2015 Google, Inc + +obj-y += panther.o diff --git a/roms/u-boot/board/google/chromebox_panther/panther.c b/roms/u-boot/board/google/chromebox_panther/panther.c new file mode 100644 index 000000000..da3445bb1 --- /dev/null +++ b/roms/u-boot/board/google/chromebox_panther/panther.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Google, Inc + */ + +#include <common.h> diff --git a/roms/u-boot/board/google/common/Makefile b/roms/u-boot/board/google/common/Makefile new file mode 100644 index 000000000..d1f45c677 --- /dev/null +++ b/roms/u-boot/board/google/common/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2014 Google, Inc + +obj-$(CONFIG_X86) += early_init.o diff --git a/roms/u-boot/board/google/common/early_init.S b/roms/u-boot/board/google/common/early_init.S new file mode 100644 index 000000000..6ac64b338 --- /dev/null +++ b/roms/u-boot/board/google/common/early_init.S @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2014 Google, Inc + */ + +.globl early_board_init +early_board_init: + /* Enable post codes to EC */ +#ifdef CONFIG_EARLY_POST_CROS_EC + mov $0x1b, %ecx + rdmsr + and $0x100, %eax + test %eax, %eax + je 1f + + mov $0x8000f8f0, %eax + mov $0xcf8, %dx + out %eax, (%dx) + mov $0xfed1c001, %eax + mov $0xcfc, %dx + out %eax, (%dx) + mov $0xfed1f410, %esp + mov (%esp), %eax + and $0xfffffffb, %eax + mov %eax, (%esp) +1: +#endif + jmp early_board_init_ret diff --git a/roms/u-boot/board/google/gru/Kconfig b/roms/u-boot/board/google/gru/Kconfig new file mode 100644 index 000000000..61f7bbca9 --- /dev/null +++ b/roms/u-boot/board/google/gru/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CHROMEBOOK_BOB + +config SYS_BOARD + default "gru" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "gru" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/roms/u-boot/board/google/gru/MAINTAINERS b/roms/u-boot/board/google/gru/MAINTAINERS new file mode 100644 index 000000000..e1cda756b --- /dev/null +++ b/roms/u-boot/board/google/gru/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK BOB BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/gru/ +F: include/configs/gru.h +F: configs/chromebook_bob_defconfig diff --git a/roms/u-boot/board/google/gru/Makefile b/roms/u-boot/board/google/gru/Makefile new file mode 100644 index 000000000..9117534a4 --- /dev/null +++ b/roms/u-boot/board/google/gru/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += gru.o diff --git a/roms/u-boot/board/google/gru/gru.c b/roms/u-boot/board/google/gru/gru.c new file mode 100644 index 000000000..23080c179 --- /dev/null +++ b/roms/u-boot/board/google/gru/gru.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google + */ + +#include <common.h> +#include <dm.h> +#include <init.h> + +#ifdef CONFIG_SPL_BUILD +/* provided to defeat compiler optimisation in board_init_f() */ +void gru_dummy_function(int i) +{ +} + +int board_early_init_f(void) +{ +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB + int sum, i; + + /* + * Add a delay and ensure that the compiler does not optimise this out. + * This is needed since the power rails tail a while to turn on, and + * we get garbage serial output otherwise. + */ + sum = 0; + for (i = 0; i < 150000; i++) + sum += i; + gru_dummy_function(sum); +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + + return 0; +} +#endif + +#ifndef CONFIG_SPL_BUILD +int board_early_init_r(void) +{ + struct udevice *clk; + int ret; + + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(clk_rk3399), &clk); + if (ret) { + debug("%s: CLK init failed: %d\n", __func__, ret); + return ret; + } + + return 0; +} +#endif diff --git a/roms/u-boot/board/google/imx8mq_phanbell/Kconfig b/roms/u-boot/board/google/imx8mq_phanbell/Kconfig new file mode 100644 index 000000000..fba2e9ce6 --- /dev/null +++ b/roms/u-boot/board/google/imx8mq_phanbell/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8MQ_PHANBELL + +config SYS_BOARD + default "imx8mq_phanbell" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "imx8mq_phanbell" + +endif diff --git a/roms/u-boot/board/google/imx8mq_phanbell/MAINTAINERS b/roms/u-boot/board/google/imx8mq_phanbell/MAINTAINERS new file mode 100644 index 000000000..b233e6b57 --- /dev/null +++ b/roms/u-boot/board/google/imx8mq_phanbell/MAINTAINERS @@ -0,0 +1,8 @@ +i.MX 8MQ PHANBELL BOARD +M: Fabio Estevam <festevam@gmail.com> +M: Marco Franchi <marcofrk@gmail.com> +M: Alifer Moraes <alifer.wsdm@gmail.com> +S: Maintained +F: board/google/imx8mq_phanbell/ +F: include/configs/imx8mq_phanbell.h +F: configs/imx8mq_phanbell_defconfig diff --git a/roms/u-boot/board/google/imx8mq_phanbell/Makefile b/roms/u-boot/board/google/imx8mq_phanbell/Makefile new file mode 100644 index 000000000..d6427cf8e --- /dev/null +++ b/roms/u-boot/board/google/imx8mq_phanbell/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 NXP +# + +obj-y += imx8mq_phanbell.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_1g.o +endif diff --git a/roms/u-boot/board/google/imx8mq_phanbell/README b/roms/u-boot/board/google/imx8mq_phanbell/README new file mode 100644 index 000000000..88a136b32 --- /dev/null +++ b/roms/u-boot/board/google/imx8mq_phanbell/README @@ -0,0 +1,37 @@ +U-Boot for Google's i.MX8MQ Phanbell board + +Quick Start +=========== +- Build the ARM Trusted firmware binary +- Get ddr and hdmi firmware +- Build U-Boot +- Boot + +Get and Build the ARM Trusted firmware +====================================== +Note: srctree is U-Boot source directory +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +branch: imx_4.19.35_1.0.0 +$ make PLAT=imx8mq bl31 +$ cp build/imx8mq/release/bl31.bin $(builddir) + +Get the ddr and hdmi firmware +============================= +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin +$ chmod +x firmware-imx-7.9.bin +$ ./firmware-imx-7.9.bin +$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir) +$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir) + +Build U-Boot +============ +$ export CROSS_COMPILE=aarch64-linux-gnu- +$ make imx8mq_phanbell_defconfig +$ make flash.bin + +Burn the flash.bin to MicroSD card offset 33KB +$sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=33 + +Boot +==== +Set Boot switch SW1: 1011 to boot from Micro SD. diff --git a/roms/u-boot/board/google/imx8mq_phanbell/imx8mq_phanbell.c b/roms/u-boot/board/google/imx8mq_phanbell/imx8mq_phanbell.c new file mode 100644 index 000000000..d0a740dd3 --- /dev/null +++ b/roms/u-boot/board/google/imx8mq_phanbell/imx8mq_phanbell.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include <common.h> +#include <env.h> +#include <init.h> +#include <malloc.h> +#include <errno.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm-generic/gpio.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/gpio.h> +#include <asm/arch/clock.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +#ifdef CONFIG_FEC_MXC +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} diff --git a/roms/u-boot/board/google/imx8mq_phanbell/lpddr4_timing_1g.c b/roms/u-boot/board/google/imx8mq_phanbell/lpddr4_timing_1g.c new file mode 100644 index 000000000..7800011a0 --- /dev/null +++ b/roms/u-boot/board/google/imx8mq_phanbell/lpddr4_timing_1g.c @@ -0,0 +1,1731 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304, 0x1}, + {0x3d400030, 0x1}, + {0x3d400000, 0xa1080020}, + {0x3d400028, 0x0}, + {0x3d400020, 0x203}, + {0x3d400024, 0x3e800}, + {0x3d400064, 0x610090}, + {0x3d4000d0, 0xc003061c}, + {0x3d4000d4, 0x9e0000}, + {0x3d4000dc, 0xd4002d}, + {0x3d4000e0, 0x310008}, + {0x3d4000e8, 0x66004a}, + {0x3d4000ec, 0x16004a}, + {0x3d400100, 0x1a201b22}, + {0x3d400104, 0x60633}, + {0x3d40010c, 0xc0c000}, + {0x3d400110, 0xf04080f}, + {0x3d400114, 0x2040c0c}, + {0x3d400118, 0x1010007}, + {0x3d40011c, 0x401}, + {0x3d400130, 0x20600}, + {0x3d400134, 0xc100002}, + {0x3d400138, 0x96}, + {0x3d400144, 0xa00050}, + {0x3d400180, 0xc3200018}, + {0x3d400184, 0x28061a8}, + {0x3d400188, 0x0}, + {0x3d400190, 0x497820a}, + {0x3d400194, 0x80303}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0xdf00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x11}, + {0x3d4001b4, 0x170a}, + {0x3d4001c0, 0x1}, + {0x3d4001c4, 0x1}, + {0x3d4000f4, 0x639}, + {0x3d400108, 0x70e1617}, + {0x3d400200, 0x1f}, + {0x3d40020c, 0x0}, + {0x3d400210, 0x1f1f}, + {0x3d400204, 0x80808}, + {0x3d400214, 0x7070707}, + {0x3d400218, 0xf070707}, + {0x3d402020, 0x1}, + {0x3d402024, 0xd0c0}, + {0x3d402050, 0x20d040}, + {0x3d402064, 0x14001f}, + {0x3d4020dc, 0x940009}, + {0x3d4020e0, 0x310000}, + {0x3d4020e8, 0x66004a}, + {0x3d4020ec, 0x16004a}, + {0x3d402100, 0xb070508}, + {0x3d402104, 0x3040b}, + {0x3d402108, 0x305090c}, + {0x3d40210c, 0x505000}, + {0x3d402110, 0x4040204}, + {0x3d402114, 0x2030303}, + {0x3d402118, 0x1010004}, + {0x3d40211c, 0x301}, + {0x3d402130, 0x20300}, + {0x3d402134, 0xa100002}, + {0x3d402138, 0x20}, + {0x3d402144, 0x220011}, + {0x3d402180, 0xc0a70006}, + {0x3d402190, 0x3858202}, + {0x3d402194, 0x80303}, + {0x3d4021b4, 0x502}, + {0x3d400244, 0x0}, + {0x3d400250, 0x29001505}, + {0x3d400254, 0x2c}, + {0x3d40025c, 0x5900575b}, + {0x3d400264, 0x90000096}, + {0x3d40026c, 0x1000012c}, + {0x3d400300, 0x16}, + {0x3d400304, 0x0}, + {0x3d40030c, 0x0}, + {0x3d400320, 0x1}, + {0x3d40036c, 0x11}, + {0x3d400400, 0x111}, + {0x3d400404, 0x10f3}, + {0x3d400408, 0x72ff}, + {0x3d400490, 0x1}, + {0x3d400494, 0xe00}, + {0x3d400498, 0x62ffff}, + {0x3d40049c, 0xe00}, + {0x3d4004a0, 0xffff}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x2}, + {0x110a3, 0x3}, + {0x110a4, 0x4}, + {0x110a5, 0x5}, + {0x110a6, 0x6}, + {0x110a7, 0x7}, + {0x120a0, 0x0}, + {0x120a1, 0x1}, + {0x120a2, 0x2}, + {0x120a3, 0x3}, + {0x120a4, 0x4}, + {0x120a5, 0x5}, + {0x120a6, 0x6}, + {0x120a7, 0x7}, + {0x130a0, 0x0}, + {0x130a1, 0x1}, + {0x130a2, 0x2}, + {0x130a3, 0x3}, + {0x130a4, 0x4}, + {0x130a5, 0x5}, + {0x130a6, 0x6}, + {0x130a7, 0x7}, + {0x20110, 0x2}, + {0x20111, 0x3}, + {0x20112, 0x4}, + {0x20113, 0x5}, + {0x20114, 0x0}, + {0x20115, 0x1}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x1205f, 0x1ff}, + {0x1215f, 0x1ff}, + {0x1305f, 0x1ff}, + {0x1315f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x11205f, 0x1ff}, + {0x11215f, 0x1ff}, + {0x11305f, 0x1ff}, + {0x11315f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x3055, 0x1ff}, + {0x4055, 0x1ff}, + {0x5055, 0x1ff}, + {0x6055, 0x1ff}, + {0x7055, 0x1ff}, + {0x8055, 0x1ff}, + {0x9055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x20024, 0x1ab}, + {0x2003a, 0x0}, + {0x120024, 0x1ab}, + {0x2003a, 0x0}, + {0x20056, 0x3}, + {0x120056, 0xa}, + {0x1004d, 0xe00}, + {0x1014d, 0xe00}, + {0x1104d, 0xe00}, + {0x1114d, 0xe00}, + {0x1204d, 0xe00}, + {0x1214d, 0xe00}, + {0x1304d, 0xe00}, + {0x1314d, 0xe00}, + {0x11004d, 0xe00}, + {0x11014d, 0xe00}, + {0x11104d, 0xe00}, + {0x11114d, 0xe00}, + {0x11204d, 0xe00}, + {0x11214d, 0xe00}, + {0x11304d, 0xe00}, + {0x11314d, 0xe00}, + {0x10049, 0xeba}, + {0x10149, 0xeba}, + {0x11049, 0xeba}, + {0x11149, 0xeba}, + {0x12049, 0xeba}, + {0x12149, 0xeba}, + {0x13049, 0xeba}, + {0x13149, 0xeba}, + {0x110049, 0xeba}, + {0x110149, 0xeba}, + {0x111049, 0xeba}, + {0x111149, 0xeba}, + {0x112049, 0xeba}, + {0x112149, 0xeba}, + {0x113049, 0xeba}, + {0x113149, 0xeba}, + {0x43, 0xe7}, + {0x1043, 0xe7}, + {0x2043, 0xe7}, + {0x3043, 0xe7}, + {0x4043, 0xe7}, + {0x5043, 0xe7}, + {0x6043, 0xe7}, + {0x7043, 0xe7}, + {0x8043, 0xe7}, + {0x9043, 0xe7}, + {0x20018, 0x3}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x20008, 0x320}, + {0x120008, 0xa7}, + {0x20088, 0x9}, + {0x200b2, 0xdc}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x12043, 0x5a1}, + {0x12143, 0x5a1}, + {0x13043, 0x5a1}, + {0x13143, 0x5a1}, + {0x1200b2, 0xdc}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x112043, 0x5a1}, + {0x112143, 0x5a1}, + {0x113043, 0x5a1}, + {0x113143, 0x5a1}, + {0x200fa, 0x1}, + {0x1200fa, 0x1}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5555}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x200c7, 0x80}, + {0x1200c7, 0x80}, + {0x200ca, 0x106}, + {0x1200ca, 0x106}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xc80}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x2dd4}, + {0x5401a, 0x31}, + {0x5401b, 0x4a66}, + {0x5401c, 0x4a08}, + {0x5401e, 0x16}, + {0x5401f, 0x2dd4}, + {0x54020, 0x31}, + {0x54021, 0x4a66}, + {0x54022, 0x4a08}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xd400}, + {0x54033, 0x312d}, + {0x54034, 0x6600}, + {0x54035, 0x84a}, + {0x54036, 0x4a}, + {0x54037, 0x1600}, + {0x54038, 0xd400}, + {0x54039, 0x312d}, + {0x5403a, 0x6600}, + {0x5403b, 0x84a}, + {0x5403c, 0x4a}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x29c}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x31}, + {0x5401b, 0x4a66}, + {0x5401c, 0x4a08}, + {0x5401e, 0x16}, + {0x5401f, 0x994}, + {0x54020, 0x31}, + {0x54021, 0x4a66}, + {0x54022, 0x4a08}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0x9400}, + {0x54033, 0x3109}, + {0x54034, 0x6600}, + {0x54035, 0x84a}, + {0x54036, 0x4a}, + {0x54037, 0x1600}, + {0x54038, 0x9400}, + {0x54039, 0x3109}, + {0x5403a, 0x6600}, + {0x5403b, 0x84a}, + {0x5403c, 0x4a}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xc80}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54010, 0x1f7f}, + {0x54012, 0x110}, + {0x54019, 0x2dd4}, + {0x5401a, 0x31}, + {0x5401b, 0x4a66}, + {0x5401c, 0x4a08}, + {0x5401e, 0x16}, + {0x5401f, 0x2dd4}, + {0x54020, 0x31}, + {0x54021, 0x4a66}, + {0x54022, 0x4a08}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xd400}, + {0x54033, 0x312d}, + {0x54034, 0x6600}, + {0x54035, 0x84a}, + {0x54036, 0x4a}, + {0x54037, 0x1600}, + {0x54038, 0xd400}, + {0x54039, 0x312d}, + {0x5403a, 0x6600}, + {0x5403b, 0x84a}, + {0x5403c, 0x4a}, + {0x5403d, 0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xf}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x630}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x630}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x630}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x630}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x630}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x630}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x630}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x630}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x630}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x630}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x630}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x630}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x630}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xa}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x2}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x900a4, 0x10}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x623}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x623}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x790}, + {0x900a9, 0x11a}, + {0x900aa, 0x8}, + {0x900ab, 0x7aa}, + {0x900ac, 0x2a}, + {0x900ad, 0x10}, + {0x900ae, 0x7b2}, + {0x900af, 0x2a}, + {0x900b0, 0x0}, + {0x900b1, 0x7c8}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x0}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xc}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x0}, + {0x90169, 0x8}, + {0x9016a, 0x8}, + {0x9016b, 0x448}, + {0x9016c, 0x109}, + {0x9016d, 0xf}, + {0x9016e, 0x7c0}, + {0x9016f, 0x109}, + {0x90170, 0x0}, + {0x90171, 0xe8}, + {0x90172, 0x109}, + {0x90173, 0x47}, + {0x90174, 0x630}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0x618}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0xe0}, + {0x9017b, 0x109}, + {0x9017c, 0x0}, + {0x9017d, 0x7c8}, + {0x9017e, 0x109}, + {0x9017f, 0x8}, + {0x90180, 0x8140}, + {0x90181, 0x10c}, + {0x90182, 0x0}, + {0x90183, 0x1}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x4}, + {0x90187, 0x8}, + {0x90188, 0x8}, + {0x90189, 0x7c8}, + {0x9018a, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2a}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x64}, + {0x2000c, 0xc8}, + {0x2000d, 0x7d0}, + {0x2000e, 0x2c}, + {0x12000b, 0x14}, + {0x12000c, 0x29}, + {0x12000d, 0x1a1}, + {0x12000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x60}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x12011, 0x1}, + {0x12012, 0x1}, + {0x12013, 0x180}, + {0x12018, 0x1}, + {0x12002, 0x6209}, + {0x120b2, 0x1}, + {0x121b4, 0x1}, + {0x122b4, 0x1}, + {0x123b4, 0x1}, + {0x124b4, 0x1}, + {0x125b4, 0x1}, + {0x126b4, 0x1}, + {0x127b4, 0x1}, + {0x128b4, 0x1}, + {0x13011, 0x1}, + {0x13012, 0x1}, + {0x13013, 0x180}, + {0x13018, 0x1}, + {0x13002, 0x6209}, + {0x130b2, 0x1}, + {0x131b4, 0x1}, + {0x132b4, 0x1}, + {0x133b4, 0x1}, + {0x134b4, 0x1}, + {0x135b4, 0x1}, + {0x136b4, 0x1}, + {0x137b4, 0x1}, + {0x138b4, 0x1}, + {0x2003a, 0x2}, + {0xc0080, 0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 667, }, +}; diff --git a/roms/u-boot/board/google/imx8mq_phanbell/spl.c b/roms/u-boot/board/google/imx8mq_phanbell/spl.c new file mode 100644 index 000000000..eec3f3d93 --- /dev/null +++ b/roms/u-boot/board/google/imx8mq_phanbell/spl.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + */ + +#include <common.h> +#include <hang.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <errno.h> +#include <init.h> +#include <log.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/sections.h> +#include <linux/delay.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void spl_dram_init(void) +{ + /* ddr init */ + ddr_init(&dram_timing); +} + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + usdhc_cfg[0].max_bus_width = 8; + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + usdhc_cfg[1].max_bus_width = 4; + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/roms/u-boot/board/google/veyron/Kconfig b/roms/u-boot/board/google/veyron/Kconfig new file mode 100644 index 000000000..7f55d78da --- /dev/null +++ b/roms/u-boot/board/google/veyron/Kconfig @@ -0,0 +1,63 @@ +if TARGET_CHROMEBOOK_JERRY + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif + +if TARGET_CHROMEBIT_MICKEY + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif + +if TARGET_CHROMEBOOK_MINNIE + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif + +if TARGET_CHROMEBOOK_SPEEDY + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/roms/u-boot/board/google/veyron/MAINTAINERS b/roms/u-boot/board/google/veyron/MAINTAINERS new file mode 100644 index 000000000..d97978076 --- /dev/null +++ b/roms/u-boot/board/google/veyron/MAINTAINERS @@ -0,0 +1,27 @@ +CHROMEBOOK JERRY BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/veyron/ +F: include/configs/veyron.h +F: configs/chromebook_jerry_defconfig + +CHROMEBIT MICKEY BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/veyron/ +F: include/configs/veyron.h +F: configs/chromebit_mickey_defconfig + +CHROMEBOOK MINNIE BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/veyron/ +F: include/configs/veyron.h +F: configs/chromebook_minnie_defconfig + +CHROMEBOOK SPEEDY BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/veyron/ +F: include/configs/veyron.h +F: configs/chromebook_speedy_defconfig diff --git a/roms/u-boot/board/google/veyron/Makefile b/roms/u-boot/board/google/veyron/Makefile new file mode 100644 index 000000000..98683579d --- /dev/null +++ b/roms/u-boot/board/google/veyron/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += veyron.o diff --git a/roms/u-boot/board/google/veyron/veyron.c b/roms/u-boot/board/google/veyron/veyron.c new file mode 100644 index 000000000..32dbcdc4d --- /dev/null +++ b/roms/u-boot/board/google/veyron/veyron.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2015 Google, Inc + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <init.h> +#include <log.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/global_data.h> +#include <dt-bindings/clock/rk3288-cru.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <power/regulator.h> + +/* + * We should increase the DDR voltage to 1.2V using the PWM regulator. + * There is a U-Boot driver for this but it may need to add support for the + * 'voltage-table' property. + */ +#ifndef CONFIG_SPL_BUILD +#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) +static int veyron_init(void) +{ + struct udevice *dev; + struct clk clk; + int ret; + + ret = regulator_get_by_platname("vdd_arm", &dev); + if (ret) { + debug("Cannot set regulator name\n"); + return ret; + } + + /* Slowly raise to max CPU voltage to prevent overshoot */ + ret = regulator_set_value(dev, 1200000); + if (ret) + return ret; + udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ + ret = regulator_set_value(dev, 1400000); + if (ret) + return ret; + udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ + + ret = rockchip_get_clk(&clk.dev); + if (ret) + return ret; + clk.id = PLL_APLL; + ret = clk_set_rate(&clk, 1800000000); + if (IS_ERR_VALUE(ret)) + return ret; + + ret = regulator_get_by_platname("vcc33_sd", &dev); + if (ret) { + debug("Cannot get regulator name\n"); + return ret; + } + + ret = regulator_set_value(dev, 3300000); + if (ret) + return ret; + + ret = regulators_enable_boot_on(false); + if (ret) { + debug("%s: Cannot enable boot on regulators\n", __func__); + return ret; + } + + return 0; +} +#endif + +int board_early_init_r(void) +{ + struct udevice *dev; + int ret; + +#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) + if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { + ret = veyron_init(); + if (ret) + return ret; + } +#endif + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return ret; + } + + return 0; +} +#endif |