diff options
Diffstat (limited to 'roms/u-boot/board/intel')
50 files changed, 1542 insertions, 0 deletions
diff --git a/roms/u-boot/board/intel/Kconfig b/roms/u-boot/board/intel/Kconfig new file mode 100644 index 000000000..7b16ec4dc --- /dev/null +++ b/roms/u-boot/board/intel/Kconfig @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + +if VENDOR_INTEL + +choice + prompt "Mainboard model" + optional + +config TARGET_BAYLEYBAY + bool "Bayley Bay" + help + This is the Intel Bayley Bay Customer Reference Board. It contains an + Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM + 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC, + PCIe and some other sensor interfaces. + +config TARGET_CHERRYHILL + bool "Cherry Hill" + help + This is the Intel Cherry Hill Customer Reference Board. It is in a + mini-ITX form factor containing the Intel Braswell SoC, which has + a 64-bit quad-core, single-thread, Intel Atom processor, along with + serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe, + some GPIOs, one HDMI and two DP video out. + +config TARGET_COUGARCANYON2 + bool "Cougar Canyon 2" + help + This is the Intel Cougar Canyon 2 Customer Reference Board. It + is built on the Chief River platform with Intel Ivybridge Processor + and Panther Point chipset. The board has 4GB RAM, with some other + peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI. + +config TARGET_CROWNBAY + bool "Crown Bay" + help + This is the Intel Crown Bay Customer Reference Board. It contains + the Intel Atom Processor E6xx populated on the COM Express module + with 1GB DDR2 soldered down memory and a carrier board with the + Intel Platform Controller Hub EG20T, other system components and + peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. + +config TARGET_EDISON + bool "Edison" + help + This is the Intel Edison Compute Module. It contains a dual core Intel + Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB + eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers. + +config TARGET_GALILEO + bool "Galileo" + help + This is the Intel Galileo board, which is the first in a family of + Arduino-certified development and prototyping boards based on Intel + architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit + single-core, single-thread, Intel Pentium processor instrunction set + architecture (ISA) compatible, operating at speeds up to 400Mhz, + along with 256MB DDR3 memory. It supports a wide range of industry + standard I/O interfaces, including a full-sized mini-PCIe slot, + one 100Mb Ethernet port, a microSD card slot, a USB host port and + a USB client port. + +config TARGET_MINNOWMAX + bool "Minnowboard MAX" + help + This is the Intel Minnowboard MAX. It contains an Atom E3800 + processor in a small form factor with Ethernet, micro-SD, USB 2, + USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. + It requires some binary blobs - see README.x86 for details. + + Note that PCIE_ECAM_BASE is set up by the FSP so the value used + by U-Boot matches that value. + +config TARGET_SLIMBOOTLOADER + bool "slimbootloader" + help + This target is used for running U-Boot on top of Slim Bootloader + boot firmware as a payload. Slim Bootloader does memory initialization + and silicon initialization, and it passes necessary information in + HOB (Hand Off Block) to a payload. The payload consumes HOB data + which is generated by Slim Bootloader for its driver initialization. + Slim Bootloader consumes FSP and its HOB, but FSP HOB is cleared + Before launching a payload. Instead, Slim Bootloader generates its + HOB data such as memory info, serial port info and so on. + Refer to doc/board/intel/slimbootloader.rst for the details. + +endchoice + +source "board/intel/bayleybay/Kconfig" +source "board/intel/cherryhill/Kconfig" +source "board/intel/cougarcanyon2/Kconfig" +source "board/intel/crownbay/Kconfig" +source "board/intel/edison/Kconfig" +source "board/intel/galileo/Kconfig" +source "board/intel/minnowmax/Kconfig" +source "board/intel/slimbootloader/Kconfig" + +endif diff --git a/roms/u-boot/board/intel/agilex-socdk/MAINTAINERS b/roms/u-boot/board/intel/agilex-socdk/MAINTAINERS new file mode 100644 index 000000000..fd05e9a4a --- /dev/null +++ b/roms/u-boot/board/intel/agilex-socdk/MAINTAINERS @@ -0,0 +1,13 @@ +SOCFPGA BOARD +M: Ley Foon Tan <ley.foon.tan@intel.com> +M: Chee Hong Ang <chee.hong.ang@intel.com> +S: Maintained +F: board/intel/agilex-socdk/ +F: include/configs/socfpga_agilex_socdk.h +F: configs/socfpga_agilex_atf_defconfig +F: configs/socfpga_agilex_defconfig + +SOCFPGA BOARD WITH VAB +M: Siew Chin Lim <elly.siew.chin.lim@intel.com> +S: Maintained +F: configs/socfpga_agilex_vab_defconfig diff --git a/roms/u-boot/board/intel/agilex-socdk/Makefile b/roms/u-boot/board/intel/agilex-socdk/Makefile new file mode 100644 index 000000000..b86223a57 --- /dev/null +++ b/roms/u-boot/board/intel/agilex-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2019 Intel Corporation <www.intel.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/roms/u-boot/board/intel/agilex-socdk/socfpga.c b/roms/u-boot/board/intel/agilex-socdk/socfpga.c new file mode 100644 index 000000000..72a3e0836 --- /dev/null +++ b/roms/u-boot/board/intel/agilex-socdk/socfpga.c @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> diff --git a/roms/u-boot/board/intel/bayleybay/.gitignore b/roms/u-boot/board/intel/bayleybay/.gitignore new file mode 100644 index 000000000..6eb8a5481 --- /dev/null +++ b/roms/u-boot/board/intel/bayleybay/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/roms/u-boot/board/intel/bayleybay/Kconfig b/roms/u-boot/board/intel/bayleybay/Kconfig new file mode 100644 index 000000000..a62249936 --- /dev/null +++ b/roms/u-boot/board/intel/bayleybay/Kconfig @@ -0,0 +1,28 @@ +if TARGET_BAYLEYBAY + +config SYS_BOARD + default "bayleybay" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "bayleybay" + +config SYS_TEXT_BASE + default 0xfff00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/roms/u-boot/board/intel/bayleybay/MAINTAINERS b/roms/u-boot/board/intel/bayleybay/MAINTAINERS new file mode 100644 index 000000000..85fa51626 --- /dev/null +++ b/roms/u-boot/board/intel/bayleybay/MAINTAINERS @@ -0,0 +1,6 @@ +Intel Bayley Bay +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/intel/bayleybay +F: include/configs/bayleybay.h +F: configs/bayleybay_defconfig diff --git a/roms/u-boot/board/intel/bayleybay/Makefile b/roms/u-boot/board/intel/bayleybay/Makefile new file mode 100644 index 000000000..d19447184 --- /dev/null +++ b/roms/u-boot/board/intel/bayleybay/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + +obj-y += bayleybay.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/roms/u-boot/board/intel/bayleybay/acpi/mainboard.asl b/roms/u-boot/board/intel/bayleybay/acpi/mainboard.asl new file mode 100644 index 000000000..2ab938a8d --- /dev/null +++ b/roms/u-boot/board/intel/bayleybay/acpi/mainboard.asl @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} + +/* PS/2 keyboard and mouse */ +Scope (\_SB.PCI0.LPCB) +{ + /* 8042 Keyboard */ + Device (PS2K) + { + Name(_HID, EISAID("PNP0303")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x60, 0x60, 0x00, 0x01) + IO(Decode16, 0x64, 0x64, 0x00, 0x01) + IRQNoFlags() { 1 } + }) + + Method(_STA, 0, Serialized) + { + Return (STA_VISIBLE) + } + } + + /* 8042 Mouse */ + Device (PS2M) + { + Name(_HID, EISAID("PNP0F03")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x60, 0x60, 0x00, 0x01) + IO(Decode16, 0x64, 0x64, 0x00, 0x01) + IRQNoFlags() { 12 } + }) + + Method(_STA, 0, Serialized) + { + Return (STA_VISIBLE) + } + } +} diff --git a/roms/u-boot/board/intel/bayleybay/bayleybay.c b/roms/u-boot/board/intel/bayleybay/bayleybay.c new file mode 100644 index 000000000..4f63c23a1 --- /dev/null +++ b/roms/u-boot/board/intel/bayleybay/bayleybay.c @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <asm/gpio.h> diff --git a/roms/u-boot/board/intel/bayleybay/dsdt.asl b/roms/u-boot/board/intel/bayleybay/dsdt.asl new file mode 100644 index 000000000..d2297ef59 --- /dev/null +++ b/roms/u-boot/board/intel/bayleybay/dsdt.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/roms/u-boot/board/intel/cherryhill/Kconfig b/roms/u-boot/board/intel/cherryhill/Kconfig new file mode 100644 index 000000000..a4fa004bf --- /dev/null +++ b/roms/u-boot/board/intel/cherryhill/Kconfig @@ -0,0 +1,25 @@ +if TARGET_CHERRYHILL + +config SYS_BOARD + default "cherryhill" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "braswell" + +config SYS_CONFIG_NAME + default "cherryhill" + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_BRASWELL + select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_MACRONIX + +endif diff --git a/roms/u-boot/board/intel/cherryhill/MAINTAINERS b/roms/u-boot/board/intel/cherryhill/MAINTAINERS new file mode 100644 index 000000000..6e90f6421 --- /dev/null +++ b/roms/u-boot/board/intel/cherryhill/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL CHERRYHILL BOARD +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/intel/cherryhill/ +F: include/configs/cherryhill.h +F: configs/cherryhill_defconfig diff --git a/roms/u-boot/board/intel/cherryhill/Makefile b/roms/u-boot/board/intel/cherryhill/Makefile new file mode 100644 index 000000000..ff6e14836 --- /dev/null +++ b/roms/u-boot/board/intel/cherryhill/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + +obj-y += cherryhill.o diff --git a/roms/u-boot/board/intel/cherryhill/cherryhill.c b/roms/u-boot/board/intel/cherryhill/cherryhill.c new file mode 100644 index 000000000..c037d5b14 --- /dev/null +++ b/roms/u-boot/board/intel/cherryhill/cherryhill.c @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <asm/arch/gpio.h> +#include <asm/fsp1/fsp_support.h> + +static const struct gpio_family gpio_family[] = { + GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0, + VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST), + + /* end of the table */ + GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0, + VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR), +}; + +static const struct gpio_pad gpio_pad[] = { + GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 29, NA, 0x4c38, NORTH), + GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 27, NA, 0x4c28, NORTH), + GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 20, NA, 0x4858, NORTH), + GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 37, NA, 0x5018, NORTH), + GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 42, NA, 0x5040, NORTH), + GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 35, NA, 0x5008, NORTH), + GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 40, NA, 0x5030, NORTH), + GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 45, NA, 0x5058, NORTH), + GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 34, NA, 0x5000, NORTH), + GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 38, NA, 0x5020, NORTH), + GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 43, NA, 0x5048, NORTH), + GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 36, NA, 0x5010, NORTH), + GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 41, NA, 0x5038, NORTH), + GPIO_PAD_CONF("N50: GP_CAMERASB10", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 39, NA, 0x5028, NORTH), + GPIO_PAD_CONF("N55: GP_CAMERASB11", GPIO, M1, GPO, LOW, + NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 44, NA, 0x5050, NORTH), + GPIO_PAD_CONF("N00: GPIO_DFX0", NATIVE, M5, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 0, NA, 0x4400, NORTH), + GPIO_PAD_CONF("N03: GPIO_DFX1", NATIVE, M5, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 3, NA, 0x4418, NORTH), + GPIO_PAD_CONF("N07: GPIO_DFX2", NATIVE, M5, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 2, NA, 0x4438, NORTH), + GPIO_PAD_CONF("N01: GPIO_DFX3", NATIVE, M5, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE, + NA, 1, NA, 0x4408, NORTH), + GPIO_PAD_CONF("N05: GPIO_DFX4", GPIO, M1, GPO, HIGH, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 5, NA, 0x4428, NORTH), + GPIO_PAD_CONF("N04: GPIO_DFX5", GPIO, M1, GPO, HIGH, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 4, NA, 0x4420, NORTH), + GPIO_PAD_CONF("N08: GPIO_DFX6", NATIVE, M8, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 8, NA, 0x4440, NORTH), + GPIO_PAD_CONF("N02: GPIO_DFX7", GPIO, M1, GPO, LOW, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 2, NA, 0x4410, NORTH), + GPIO_PAD_CONF("N15: GPIO_SUS0", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 9 , NA, 0x4800, NORTH), + GPIO_PAD_CONF("N19: GPIO_SUS1", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 13, NA, 0x4820, NORTH), + GPIO_PAD_CONF("N24: GPIO_SUS2", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 18, NA, 0x4848, NORTH), + GPIO_PAD_CONF("N17: GPIO_SUS3", NATIVE, M6, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 11, NA, 0x4810, NORTH), + GPIO_PAD_CONF("N22: GPIO_SUS4", GPIO, M1, GPO, HIGH, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 16, NA, 0x4838, NORTH), + GPIO_PAD_CONF("N20: GPIO_SUS5", GPIO, M1, GPO, HIGH, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 14, NA, 0x4828, NORTH), + GPIO_PAD_CONF("N25: GPIO_SUS6", GPIO, M1, GPI, NA, NA, + TRIG_EDGE_LOW, L9, NA, NA, NA, NON_MASKABLE, + EN_EDGE_RX_DATA, NO_INVERSION, + NA, 19, SCI, 0x4850, NORTH), + GPIO_PAD_CONF("N18: GPIO_SUS7", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 12, SMI, 0x4818, NORTH), + GPIO_PAD_CONF("N71: HV_DDI0_DDC_SCL", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 57, NA, 0x5458, NORTH), + GPIO_PAD_CONF("N66: HV_DDI0_DDC_SDA", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 52, NA, 0x5430, NORTH), + GPIO_PAD_CONF("N61: HV_DDI0_HPD", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE, + NA, 47, NA, 0x5408, NORTH), + GPIO_PAD_CONF("N64: HV_DDI1_HPD", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE, + NA, 50, NA, 0x5420, NORTH), + GPIO_PAD_CONF("N67: HV_DDI2_DDC_SCL", NATIVE, M3, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 53, NA, 0x5438, NORTH), + GPIO_PAD_CONF("N62: HV_DDI2_DDC_SDA", NATIVE, M3, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 48, NA, 0x5410, NORTH), + GPIO_PAD_CONF("N68: HV_DDI2_HPD", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE, + NA, 54, NA, 0x5440, NORTH), + GPIO_PAD_CONF("N65: PANEL0_BKLTCTL", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 51, NA, 0x5428, NORTH), + GPIO_PAD_CONF("N60: PANEL0_BKLTEN", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 46, NA, 0x5400, NORTH), + GPIO_PAD_CONF("N72: PANEL0_VDDEN", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 58, NA, 0x5460, NORTH), + GPIO_PAD_CONF("N63: PANEL1_BKLTCTL", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 49, NA, 0x5418, NORTH), + GPIO_PAD_CONF("N70: PANEL1_BKLTEN", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 56, NA, 0x5450, NORTH), + GPIO_PAD_CONF("N69: PANEL1_VDDEN", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 55, NA, 0x5448, NORTH), + GPIO_PAD_CONF("N32: PROCHOT_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 24, NA, 0x4c10, NORTH), + GPIO_PAD_CONF("N16: SEC_GPIO_SUS10", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 10, NA, 0x4808, NORTH), + GPIO_PAD_CONF("N21: SEC_GPIO_SUS11", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 15, NA, 0x4830, NORTH), + GPIO_PAD_CONF("N23: SEC_GPIO_SUS8", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 17, NA, 0x4840, NORTH), + GPIO_PAD_CONF("N27: SEC_GPIO_SUS9", GPIO, M1, GPI, LOW, NA, + TRIG_LEVEL, L15, NA, NA, NA, NON_MASKABLE, + EN_RX_DATA, INV_RX_DATA, + NA, 21, SCI, 0x4860, NORTH), + GPIO_PAD_CONF("N31: TCK", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 23, NA, 0x4c08, NORTH), + GPIO_PAD_CONF("N41: TDI", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 33, NA, 0x4c58, NORTH), + GPIO_PAD_CONF("N39: TDO", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 31, NA, 0x4c48, NORTH), + GPIO_PAD_CONF("N36: TDO_2", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 28, NA, 0x4c30, NORTH), + GPIO_PAD_CONF("N34: TMS", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 26, NA, 0x4c20, NORTH), + GPIO_PAD_CONF("N30: TRST_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 22, NA, 0x4c00, NORTH), + + GPIO_PAD_CONF("E21: MF_ISH_GPIO_0", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 18, NA, 0x4830, EAST), + GPIO_PAD_CONF("E18: MF_ISH_GPIO_1", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 15, NA, 0x4818, EAST), + GPIO_PAD_CONF("E24: MF_ISH_GPIO_2", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 21, NA, 0x4848, EAST), + GPIO_PAD_CONF("E15: MF_ISH_GPIO_3", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 12, NA, 0x4800, EAST), + GPIO_PAD_CONF("E22: MF_ISH_GPIO_4", GPIO, M1, GPI, NA, NA, + NA, L0, NA, NA, NA, NON_MASKABLE, NA, NO_INVERSION, + NA, 19, NA, 0x4838, EAST), + GPIO_PAD_CONF("E19: MF_ISH_GPIO_5", GPIO, M1, GPO, HIGH, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 16, NA, 0x4820, EAST), + GPIO_PAD_CONF("E25: MF_ISH_GPIO_6", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 22, NA, 0x4850, EAST), + GPIO_PAD_CONF("E16: MF_ISH_GPIO_7", GPIO, M1, GPO, HIGH, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 13, NA, 0x4808, EAST), + GPIO_PAD_CONF("E23: MF_ISH_GPIO_8", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 20, NA, 0x4840, EAST), + GPIO_PAD_CONF("E20: MF_ISH_GPIO_9", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 17, NA, 0x4828, EAST), + GPIO_PAD_CONF("E26: MF_ISH_I2C1_SDA", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 23, NA, 0x4858, EAST), + GPIO_PAD_CONF("E17: MF_ISH_I2C1_SCL", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 14, NA, 0x4810, EAST), + GPIO_PAD_CONF("E04: PMU_AC_PRESENT", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 4, NA, 0x4420, EAST), + GPIO_PAD_CONF("E01: PMU_BATLOW_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 1, NA, 0x4408, EAST), + GPIO_PAD_CONF("E05: PMU_PLTRST_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 5, NA, 0x4428, EAST), + GPIO_PAD_CONF("E07: PMU_SLP_LAN_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 7, NA, 0x4438, EAST), + GPIO_PAD_CONF("E03: PMU_SLP_S0IX_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 3, NA, 0x4418, EAST), + GPIO_PAD_CONF("E00: PMU_SLP_S3_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 0, NA, 0x4400, EAST), + GPIO_PAD_CONF("E09: PMU_SLP_S4_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 9, NA, 0x4448, EAST), + GPIO_PAD_CONF("E06: PMU_SUSCLK", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 6, NA, 0x4430, EAST), + GPIO_PAD_CONF("E10: PMU_WAKE_B", NATIVE, M1, NA, NA, NA, + NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 10, NA, 0x4450, EAST), + GPIO_PAD_CONF("E11: PMU_WAKE_LAN_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 11, NA, 0x4458, EAST), + GPIO_PAD_CONF("E02: SUS_STAT_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 2, NA, 0x4410, EAST), + + GPIO_PAD_CONF("SE16: SDMMC1_CLK", NATIVE, M1, NA, NA, HIGH, + NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION, + NA, 9, NA, 0x4808, SOUTHEAST), + GPIO_PAD_CONF("SE23: SDMMC1_CMD", NATIVE, M1, NA, NA, HIGH, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 16, NA, 0x4840, SOUTHEAST), + GPIO_PAD_CONF("SE17: SDMMC1_D0", NATIVE, M1, NA, NA, HIGH, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 10, NA, 0x4810, SOUTHEAST), + GPIO_PAD_CONF("SE24: SDMMC1_D1", NATIVE, M1, NA, NA, HIGH, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 17, NA, 0x4848, SOUTHEAST), + GPIO_PAD_CONF("SE20: SDMMC1_D2", NATIVE, M1, NA, NA, HIGH, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 13, NA, 0x4828, SOUTHEAST), + GPIO_PAD_CONF("SE26: SDMMC1_D3_CD_B", NATIVE, M1, NA, NA, HIGH, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 19, NA, 0x4858, SOUTHEAST), + GPIO_PAD_CONF("SE67: MMC1_D4_SD_WE", NATIVE, M1, NA, NA, HIGH, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 41, NA, 0x5438, SOUTHEAST), + GPIO_PAD_CONF("SE65: MMC1_D5", NATIVE, M1, NA, NA, HIGH, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 39, NA, 0x5428, SOUTHEAST), + GPIO_PAD_CONF("SE63: MMC1_D6", NATIVE, M1, NA, NA, HIGH, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 37, NA, 0x5418, SOUTHEAST), + GPIO_PAD_CONF("SE68: MMC1_D7", NATIVE, M1, NA, NA, HIGH, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 42, NA, 0x5440, SOUTHEAST), + GPIO_PAD_CONF("SE69: MMC1_RCLK", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 43, NA, 0x5448, SOUTHEAST), + GPIO_PAD_CONF("SE77: GPIO_ALERT", GPIO, M1, GPI, NA, NA, + TRIG_LEVEL, L2, NA, NA, NA, NON_MASKABLE, + EN_RX_DATA, INV_RX_DATA, + NA, 46, NA, 0x5810, SOUTHEAST), + GPIO_PAD_CONF("SE79: ILB_SERIRQ", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 48, NA, 0x5820, SOUTHEAST), + GPIO_PAD_CONF("SE51: MF_LPC_CLKOUT0", NATIVE, M1, NA, NA, NA, + NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION, + NA, 32, NA, 0x5030, SOUTHEAST), + GPIO_PAD_CONF("SE49: MF_LPC_CLKOUT1", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 30, NA, 0x5020, SOUTHEAST), + GPIO_PAD_CONF("SE47: MF_LPC_AD0", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 28, NA, 0x5010, SOUTHEAST), + GPIO_PAD_CONF("SE52: MF_LPC_AD1", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 33, NA, 0x5038, SOUTHEAST), + GPIO_PAD_CONF("SE45: MF_LPC_AD2", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 26, NA, 0x5000, SOUTHEAST), + GPIO_PAD_CONF("SE50: MF_LPC_AD3", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 31, NA, 0x5028, SOUTHEAST), + GPIO_PAD_CONF("SE46: LPC_CLKRUNB", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 27, NA, 0x5008, SOUTHEAST), + GPIO_PAD_CONF("SE48: LPC_FRAMEB", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 29, NA, 0x5018, SOUTHEAST), + GPIO_PAD_CONF("SE00: MF_PLT_CLK0", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 0, NA, 0x4400, SOUTHEAST), + GPIO_PAD_CONF("SE02: MF_PLT_CLK1", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 1, NA, 0x4410, SOUTHEAST), + GPIO_PAD_CONF("SE07: MF_PLT_CLK2", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 7, NA, 0x4438, SOUTHEAST), + GPIO_PAD_CONF("SE04: MF_PLT_CLK3", GPIO, M1, GPI, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 4, NA, 0x4420, SOUTHEAST), + GPIO_PAD_CONF("SE03: MF_PLT_CLK4", GPIO, M1, GPO, LOW, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 3, NA, 0x4418, SOUTHEAST), + GPIO_PAD_CONF("SE06: MF_PLT_CLK5", GPIO, M3, GPO, LOW, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 6, NA, 0x4430, SOUTHEAST), + GPIO_PAD_CONF("SE83: SUSPWRDNACK", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 52, NA, 0x5840, SOUTHEAST), + GPIO_PAD_CONF("SE05: PWM0", GPIO, M1, GPO, LOW, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 5, NA, 0x4428, SOUTHEAST), + GPIO_PAD_CONF("SE01: PWM1", GPIO, M1, GPO, HIGH, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 1, NA, 0x4408, SOUTHEAST), + GPIO_PAD_CONF("SE85: SDMMC3_1P8_EN", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 54, NA, 0x5850, SOUTHEAST), + GPIO_PAD_CONF("SE81: SDMMC3_CD_B", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 50, NA, 0x5830, SOUTHEAST), + GPIO_PAD_CONF("SE31: SDMMC3_CLK", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 21, NA, 0x4c08, SOUTHEAST), + GPIO_PAD_CONF("SE34: SDMMC3_CMD", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 24, NA, 0x4c20, SOUTHEAST), + GPIO_PAD_CONF("SE35: SDMMC3_D0", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 25, NA, 0x4c28, SOUTHEAST), + GPIO_PAD_CONF("SE30: SDMMC3_D1", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 20, NA, 0x4c00, SOUTHEAST), + GPIO_PAD_CONF("SE33: SDMMC3_D2", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 23, NA, 0x4c18, SOUTHEAST), + GPIO_PAD_CONF("SE32: SDMMC3_D3", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 22, NA, 0x4c10, SOUTHEAST), + GPIO_PAD_CONF("SE78: SDMMC3_PWR_EN_B", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION, + NA, 47, NA, 0x5818, SOUTHEAST), + GPIO_PAD_CONF("SE19: SDMMC2_CLK", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 12, NA, 0x4820, SOUTHEAST), + GPIO_PAD_CONF("SE22: SDMMC2_CMD", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 15, NA, 0x4838, SOUTHEAST), + GPIO_PAD_CONF("SE25: SDMMC2_D0", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 18, NA, 0x4850, SOUTHEAST), + GPIO_PAD_CONF("SE18: SDMMC2_D1", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 11, NA, 0x4818, SOUTHEAST), + GPIO_PAD_CONF("SE21: SDMMC2_D2", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 14, NA, 0x4830, SOUTHEAST), + GPIO_PAD_CONF("SE15: SDMMC2_D3_CD_B", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 8, NA, 0x4800, SOUTHEAST), + GPIO_PAD_CONF("SE62: SPI1_CLK", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 36, NA, 0x5410, SOUTHEAST), + GPIO_PAD_CONF("SE61: SPI1_CS0_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 35, NA, 0x5408, SOUTHEAST), + GPIO_PAD_CONF("SE66: SPI1_CS1_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 40, NA, 0x5430, SOUTHEAST), + GPIO_PAD_CONF("SE60: SPI1_MISO", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 34, NA, 0x5400, SOUTHEAST), + GPIO_PAD_CONF("SE64: SPI1_MOSI", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 38, NA, 0x5420, SOUTHEAST), + GPIO_PAD_CONF("SE80: USB_OC0_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 49, NA, 0x5828, SOUTHEAST), + GPIO_PAD_CONF("SE75: USB_OC1_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 44, NA, 0x5800, SOUTHEAST), + GPIO_PAD_CONF("SW02: FST_SPI_CLK", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 2, NA, 0x4410, SOUTHWEST), + GPIO_PAD_CONF("SW06: FST_SPI_CS0_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 6, NA, 0x4430, SOUTHWEST), + GPIO_PAD_CONF("SW04: FST_SPI_CS1_B", GPIO, M1, GPO, HIGH, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 4, NA, 0x4420, SOUTHWEST), + GPIO_PAD_CONF("SW07: FST_SPI_CS2_B", GPIO, M1, GPO, LOW, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 7, NA, 0x4438, SOUTHWEST), + GPIO_PAD_CONF("SW01: FST_SPI_D0", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 1, NA, 0x4408, SOUTHWEST), + GPIO_PAD_CONF("SW05: FST_SPI_D1", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 5, NA, 0x4428, SOUTHWEST), + GPIO_PAD_CONF("SW00: FST_SPI_D2", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 0, NA, 0x4400, SOUTHWEST), + GPIO_PAD_CONF("SW03: FST_SPI_D3", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 3, NA, 0x4418, SOUTHWEST), + GPIO_PAD_CONF("SW30: MF_HDA_CLK", NATIVE, M2, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 16, NA, 0x4c00, SOUTHWEST), + GPIO_PAD_CONF("SW37: MF_HDA_DOCKENB", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 23, NA, 0x4c38, SOUTHWEST), + GPIO_PAD_CONF("SW34: MF_HDA_DOCKRSTB", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 20, NA, 0x4c20, SOUTHWEST), + GPIO_PAD_CONF("SW31: MF_HDA_RSTB", NATIVE, M2, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 17, NA, 0x4c08, SOUTHWEST), + GPIO_PAD_CONF("SW32: MF_HDA_SDI0", NATIVE, M2, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 18, NA, 0x4c10, SOUTHWEST), + GPIO_PAD_CONF("SW36: MF_HDA_SDI1", NATIVE, M2, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 22, NA, 0x4c30, SOUTHWEST), + GPIO_PAD_CONF("SW33: MF_HDA_SDO", NATIVE, M2, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 19, NA, 0x4c18, SOUTHWEST), + GPIO_PAD_CONF("SW35: MF_HDA_SYNC", NATIVE, M2, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 21, NA, 0x4c28, SOUTHWEST), + GPIO_PAD_CONF("SW18: UART1_CTS_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 11, NA, 0x4818, SOUTHWEST), + GPIO_PAD_CONF("SW15: UART1_RTS_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 8, NA, 0x4800, SOUTHWEST), + GPIO_PAD_CONF("SW16: UART1_RXD", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 9, NA, 0x4808, SOUTHWEST), + GPIO_PAD_CONF("SW20: UART1_TXD", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 13, NA, 0x4828, SOUTHWEST), + GPIO_PAD_CONF("SW22: UART2_CTS_B", NATIVE, M1, NA, NA, NA, + NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION, + NA, 15, NA, 0x4838, SOUTHWEST), + GPIO_PAD_CONF("SW19: UART2_RTS_B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 12, NA, 0x4820, SOUTHWEST), + GPIO_PAD_CONF("SW17: UART2_RXD", NATIVE, M1, NA, NA, NA, + NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION, + NA, 10, NA, 0x4810, SOUTHWEST), + GPIO_PAD_CONF("SW21: UART2_TXD", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 14, NA, 0x4830, SOUTHWEST), + GPIO_PAD_CONF("SW50: I2C4_SCL", NATIVE, M3, NA, NA, NA, + NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 29, NA, 0x5028, SOUTHWEST), + GPIO_PAD_CONF("SW46: I2C4_SDA", NATIVE, M3, NA, NA, NA, + NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 25, NA, 0x5008, SOUTHWEST), + GPIO_PAD_CONF("SW49: I2C_NFC_SDA", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE, + NA, 28, NA, 0x5020, SOUTHWEST), + GPIO_PAD_CONF("SW52: I2C_NFC_SCL", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE, + NA, 31, NA, 0x5038, SOUTHWEST), + GPIO_PAD_CONF("SW77: GP_SSP_2_CLK", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 50, NA, 0x5c10, SOUTHWEST), + GPIO_PAD_CONF("SW81: GP_SSP_2_FS", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 54, NA, 0x5c30, SOUTHWEST), + GPIO_PAD_CONF("SW79: GP_SSP_2_RXD", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 52, NA, 0x5c20, SOUTHWEST), + GPIO_PAD_CONF("SW82: GP_SSP_2_TXD", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE, + NA, 55, NA, 0x5C38, SOUTHWEST), + GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 48, NA, 0x5c00, SOUTHWEST), + GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 49, NA, 0x5c08, SOUTHWEST), + GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 51, NA, 0x5c18, SOUTHWEST), + GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 53, NA, 0x5c28, SOUTHWEST), + GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 40, NA, 0x5800, SOUTHWEST), + GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 41, NA, 0x5808, SOUTHWEST), + GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA, + NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION, + NA, 43, NA, 0x5818, SOUTHWEST), + GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 45, NA, 0x5828, SOUTHWEST), + GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA, + NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION, + NA, 42, NA, 0x5810, SOUTHWEST), + GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA, + NA, NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 44, NA, 0x5820, SOUTHWEST), + GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 46, NA, 0x5830, SOUTHWEST), + GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, + NA, 47, NA, 0x5838, SOUTHWEST), + GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NA, + NA, 48, NA, 0x5c00, SOUTHWEST), + GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NA, + NA, 49, NA, 0x5c08, SOUTHWEST), + GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NA, + NA, 51, NA, 0x5c18, SOUTHWEST), + GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NA, + NA, 53, NA, 0x5c28, SOUTHWEST), + GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, NA, + NA, NA, NA, NA, NA, NA, NA, + NA, 40, NA, 0x5800, SOUTHWEST), + GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, NA, + NA, NA, NA, NA, NA, NA, NA, + NA, 41, NA, 0x5808, SOUTHWEST), + GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA, + NA, NA, NA, ENABLE, NA, NA, NA, NA, + NA, 43, NA, 0x5818, SOUTHWEST), + GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA, + NA, NA, NA, NA, NA, NA, NA, NA, + NA, 45, NA, 0x5828, SOUTHWEST), + GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA, + NA, NA, NA, ENABLE, NA, NA, NA, NA, + NA, 42, NA, 0x5810, SOUTHWEST), + GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA, + NA, NA, NA, P_20K_H, NA, NA, NA, NA, NA, + NA, 44, NA, 0x5820, SOUTHWEST), + GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NA, + NA, 46, NA, 0x5830, SOUTHWEST), + GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA, + NA, NA, P_20K_H, NA, NA, NA, NA, NA, + NA, 47, NA, 0x5838, SOUTHWEST), + + /* end of the table */ + GPIO_PAD_CONF("GPIO PAD TABLE END", NATIVE, M1, NA, NA, NA, + NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, + NA, 0, NA, 0, TERMINATOR), +}; + +void update_fsp_gpio_configs(const struct gpio_family **family, + const struct gpio_pad **pad) +{ + *family = gpio_family; + *pad = gpio_pad; +} diff --git a/roms/u-boot/board/intel/cougarcanyon2/Kconfig b/roms/u-boot/board/intel/cougarcanyon2/Kconfig new file mode 100644 index 000000000..ed764485a --- /dev/null +++ b/roms/u-boot/board/intel/cougarcanyon2/Kconfig @@ -0,0 +1,27 @@ +if TARGET_COUGARCANYON2 + +config SYS_BOARD + default "cougarcanyon2" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "cougarcanyon2" + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select NORTHBRIDGE_INTEL_IVYBRIDGE + select HAVE_FSP + select BOARD_ROMSIZE_KB_2048 + select BOARD_EARLY_INIT_F + select SPI_FLASH_WINBOND + +endif diff --git a/roms/u-boot/board/intel/cougarcanyon2/MAINTAINERS b/roms/u-boot/board/intel/cougarcanyon2/MAINTAINERS new file mode 100644 index 000000000..a486739b5 --- /dev/null +++ b/roms/u-boot/board/intel/cougarcanyon2/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL COUGAR CANYON 2 BOARD +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/intel/cougarcanyon2/ +F: include/configs/cougarcanyon2.h +F: configs/cougarcanyon2_defconfig diff --git a/roms/u-boot/board/intel/cougarcanyon2/Makefile b/roms/u-boot/board/intel/cougarcanyon2/Makefile new file mode 100644 index 000000000..13b19ae65 --- /dev/null +++ b/roms/u-boot/board/intel/cougarcanyon2/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + +obj-y += cougarcanyon2.o diff --git a/roms/u-boot/board/intel/cougarcanyon2/cougarcanyon2.c b/roms/u-boot/board/intel/cougarcanyon2/cougarcanyon2.c new file mode 100644 index 000000000..ce11eae59 --- /dev/null +++ b/roms/u-boot/board/intel/cougarcanyon2/cougarcanyon2.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <init.h> +#include <pci.h> +#include <smsc_sio1007.h> +#include <asm/ibmpc.h> +#include <asm/lpc_common.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> + +#define SIO1007_RUNTIME_IOPORT 0x180 + +int board_early_init_f(void) +{ + struct udevice *pch; + int ret; + + ret = uclass_first_device(UCLASS_PCH, &pch); + if (ret) + return ret; + if (!pch) + return -ENODEV; + + /* Initialize LPC interface to turn on superio chipset decode range */ + dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE); + dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN); + dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B | + (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN); + dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B | + SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN); + + /* Enable legacy serial port at 0x3f8 */ + sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ); + + /* Enable SIO1007 runtime I/O port at 0x180 */ + sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT); + + /* + * On Cougar Canyon 2 board, the RS232 transiver connected to serial + * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007. + * Set the pin value to 1 to enable the RS232 transiver. + */ + sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT, + GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL); + sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1); + + return 0; +} diff --git a/roms/u-boot/board/intel/crownbay/Kconfig b/roms/u-boot/board/intel/crownbay/Kconfig new file mode 100644 index 000000000..1eed227c7 --- /dev/null +++ b/roms/u-boot/board/intel/crownbay/Kconfig @@ -0,0 +1,26 @@ +if TARGET_CROWNBAY + +config SYS_BOARD + default "crownbay" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "queensbay" + +config SYS_CONFIG_NAME + default "crownbay" + +config SYS_TEXT_BASE + default 0xfff00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_QUEENSBAY + select BOARD_ROMSIZE_KB_1024 + select BOARD_EARLY_INIT_F + select SPI_FLASH_SST + +endif diff --git a/roms/u-boot/board/intel/crownbay/MAINTAINERS b/roms/u-boot/board/intel/crownbay/MAINTAINERS new file mode 100644 index 000000000..1eb68693d --- /dev/null +++ b/roms/u-boot/board/intel/crownbay/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL CROWNBAY BOARD +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/intel/crownbay/ +F: include/configs/crownbay.h +F: configs/crownbay_defconfig diff --git a/roms/u-boot/board/intel/crownbay/Makefile b/roms/u-boot/board/intel/crownbay/Makefile new file mode 100644 index 000000000..6abd3eeb5 --- /dev/null +++ b/roms/u-boot/board/intel/crownbay/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + +obj-y += crownbay.o diff --git a/roms/u-boot/board/intel/crownbay/crownbay.c b/roms/u-boot/board/intel/crownbay/crownbay.c new file mode 100644 index 000000000..55095deea --- /dev/null +++ b/roms/u-boot/board/intel/crownbay/crownbay.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <init.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h> +#include <smsc_lpc47m.h> + +int board_early_init_f(void) +{ + lpc47m_enable_serial(PNP_DEV(LPC47M_IO_PORT, LPC47M_SP1), + UART0_BASE, UART0_IRQ); + lpc47m_enable_kbc(PNP_DEV(LPC47M_IO_PORT, LPC47M_KBC), + KBD_IRQ, MSE_IRQ); + + return 0; +} diff --git a/roms/u-boot/board/intel/edison/.gitignore b/roms/u-boot/board/intel/edison/.gitignore new file mode 100644 index 000000000..6eb8a5481 --- /dev/null +++ b/roms/u-boot/board/intel/edison/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/roms/u-boot/board/intel/edison/Kconfig b/roms/u-boot/board/intel/edison/Kconfig new file mode 100644 index 000000000..23b2af482 --- /dev/null +++ b/roms/u-boot/board/intel/edison/Kconfig @@ -0,0 +1,36 @@ +if TARGET_EDISON + +config SYS_BOARD + default "edison" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "tangier" + +config SYS_CONFIG_NAME + default "edison" + +config SYS_MALLOC_LEN + default 0x08000000 + +config SYS_TEXT_BASE + default 0x01101000 + +config ROM_TABLE_ADDR + default 0x0e4500 + +config ROM_TABLE_SIZE + default 0x007b00 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_LOAD_FROM_32_BIT + select INTEL_MID + select INTEL_TANGIER + select BOARD_LATE_INIT + select MD5 + imply BINMAN + +endif diff --git a/roms/u-boot/board/intel/edison/MAINTAINERS b/roms/u-boot/board/intel/edison/MAINTAINERS new file mode 100644 index 000000000..4bc4a00c8 --- /dev/null +++ b/roms/u-boot/board/intel/edison/MAINTAINERS @@ -0,0 +1,6 @@ +Intel Edison Board +M: Andy Shevchenko <andriy.shevchenko@linux.intel.com> +S: Maintained +F: board/intel/edison +F: include/configs/edison.h +F: configs/edison_defconfig diff --git a/roms/u-boot/board/intel/edison/Makefile b/roms/u-boot/board/intel/edison/Makefile new file mode 100644 index 000000000..1eaf7ca7f --- /dev/null +++ b/roms/u-boot/board/intel/edison/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += edison.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/roms/u-boot/board/intel/edison/config.mk b/roms/u-boot/board/intel/edison/config.mk new file mode 100644 index 000000000..8c6087e29 --- /dev/null +++ b/roms/u-boot/board/intel/edison/config.mk @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +# +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. +# Copyright (c) 2017 Intel Corporation +# + +# Add 4096 bytes of zeroes to u-boot.bin +quiet_cmd_mkalign_eds = EDSALGN $@ +cmd_mkalign_eds = \ + dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \ + mv $@ $^ + +INPUTS-y += u-boot-align.bin +u-boot-align.bin: u-boot.bin + $(call if_changed,mkalign_eds) + +HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros diff --git a/roms/u-boot/board/intel/edison/dsdt.asl b/roms/u-boot/board/intel/edison/dsdt.asl new file mode 100644 index 000000000..3b75c4e76 --- /dev/null +++ b/roms/u-boot/board/intel/edison/dsdt.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 Intel Corporation + * + * Partially based on dsdt.asl for other x86 boards + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> +} diff --git a/roms/u-boot/board/intel/edison/edison-environment.txt b/roms/u-boot/board/intel/edison/edison-environment.txt new file mode 100644 index 000000000..afe009204 --- /dev/null +++ b/roms/u-boot/board/intel/edison/edison-environment.txt @@ -0,0 +1,48 @@ +partitions=uuid_disk=${uuid_disk};name=u-boot0,start=1MiB,size=2MiB,uuid=${uuid_uboot0};name=u-boot-env0,size=1MiB,uuid=${uuid_uboot_env0};name=u-boot1,size=2MiB,uuid=${uuid_uboot1};name=u-boot-env1,size=1MiB,uuid=${uuid_uboot_env1};name=factory,size=1MiB,uuid=${uuid_factory};name=panic,size=24MiB,uuid=${uuid_panic};name=boot,size=32MiB,uuid=${uuid_boot};name=rootfs,size=1536MiB,uuid=${uuid_rootfs};name=update,size=768MiB,uuid=${uuid_update};name=home,size=-,uuid=${uuid_home}; +do_dfu_alt_info_mmc=setenv dfu_alt_info "ifwi${hardware_id} raw 0 8192 mmcpart 1;ifwib${hardware_id} raw 0 8192 mmcpart 2;u-boot0 part 0 1;u-boot-env0 part 0 2;u-boot1 part 0 3;u-boot-env1 part 0 4;boot part 0 7;rootfs part 0 8;update part 0 9;home part 0 10;vmlinuz fat 0 7;initrd fat 0 7" +dfu_alt_info_ram=kernel ram ${loadaddr} 0x800000 +do_dfu_alt_info_ifwi=setenv dfu_alt_info "ifwi${hardware_id} raw 0 8192 mmcpart 1;ifwib${hardware_id} raw 0 8192 mmcpart 2" +dfu_alt_info_reset=reset ram 0x0 0x0 +bootargs_console=console=ttyMFD2 earlyprintk=ttyMFD2,keep +bootargs_debug=loglevel=4 +do_bootargs_rootfs=setenv bootargs_rootfs rootwait root=PARTUUID=${uuid_rootfs} rootfstype=ext4 +first_install_retry=0 +first_install_max_retries=3 +ota_update_retry=0 +ota_update_max_retries=3 +audio_codec_name=audio_codec="dummy" +do_audio_support=setenv audio_support platform_mrfld_audio.${audio_codec_name} +do_compute_target=if itest.b ${first_install_retry} -gt ${first_install_max_retries} || itest.b ${ota_update_retry} -gt ${ota_update_max_retries}; then echo "Switch to Rescue target"; setenv bootargs_target rescue; saveenv; fi +mmc-bootargs=run do_bootargs_rootfs; run do_audio_support; setenv bootargs ${bootargs_rootfs} ${bootargs_console} ${bootargs_debug} g_multi.ethernet_config=${bootargs_ethconfig} systemd.unit=${bootargs_target}.target hardware_id=${hardware_id} g_multi.iSerialNumber=${serial#} g_multi.dev_addr=${usb0addr} ${audio_support} +loadaddr=0x100000 +load_kernel=fatload mmc 0:7 ${loadaddr} vmlinuz +do_partition_done=0 +do_partition=if itest.b ${do_partition_done} -eq 1; then echo "Partitioning already done..."; else run do_force_partition ; fi +do_force_partition=echo "Partitioning using GPT"; gpt write mmc 0 ${partitions} ; mmc rescan; setenv do_partition_done 1 ; saveenv +do_flash_ifwi=run do_dfu_alt_info_ifwi ; dfu 0 mmc 0 $dfu_to_sec +do_flash_os=if itest.b ${do_flash_os_done} -eq 1 ; then echo "Flashing already done..." ; else run do_force_flash_os; fi +do_force_flash_os=run do_dfu_alt_info_mmc ; sleep 1 ; setenv do_flash_os_done 1 ; saveenv ; dfu 0 mmc 0 $dfu_to_sec +do_flashall=run do_partition;run do_flash_ifwi;run do_flash_os +do_dnx=setenv dfu_alt_info ${dfu_alt_info_ram};dfu 0 ram 0 ram;run bootcmd +init_dfu=run do_dfu_alt_info_mmc ; saveenv +bootcmd=echo "Target:${target_name}"; run do_partition; run do_handle_bootargs_mode; +do_handle_bootargs_mode=run do_preprocess_bootargs_mode; if itest.s $bootargs_mode == "ota" ; then run do_ota; fi; if itest.s $bootargs_mode == "boot" ; then run do_boot; fi; if itest.s $bootargs_mode == "flash"; then run do_flash; fi; run do_fallback; exit; +do_preprocess_bootargs_mode=if env exists bootargs_mode ; then ; else setenv bootargs_mode "boot" ;fi; +do_fallback=echo "Unknown boot mode: $bootargs_mode"; env delete -f bootargs_mode; saveenv; echo "Resetting to default boot mode and reboot..."; reset; +do_boot=run boot_target_cmd; +do_flash=run do_force_flash_os; +ota_done=0 +ota_script_addr=0x100000 +do_ota_init=setenv ota_status 1 ; env delete -f bootargs_mode +do_load_ota_scr=if fatload mmc 0:9 $ota_script_addr ota_update.scr ; then setenv ota_status 0 ; else setenv ota_status 1 ; fi +do_source_ota_scr=if test $ota_status -eq 0 ; then if source $ota_script_addr ; then setenv ota_status 0 ; else setenv ota_status 2 ; fi ; fi +do_ota_clean=saveenv ; reset +do_ota=run do_ota_init ; run do_load_ota_scr ; run do_source_ota_scr ; run do_ota_clean +target_name=blank +bootdelay=1 +do_flash_os_done=1 +bootargs_target=multi-user +bootargs_ethconfig=cdc +dfu_to_sec=3 +do_probe_dfu=run do_dfu_alt_info_mmc ; dfu 0 mmc 0 $dfu_to_sec +boot_target_cmd=run do_flash_os;run do_probe_dfu;run do_compute_target;run mmc-bootargs;run load_kernel;zboot ${loadaddr} diff --git a/roms/u-boot/board/intel/edison/edison-osip.dat b/roms/u-boot/board/intel/edison/edison-osip.dat new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/roms/u-boot/board/intel/edison/edison-osip.dat diff --git a/roms/u-boot/board/intel/edison/edison.c b/roms/u-boot/board/intel/edison/edison.c new file mode 100644 index 000000000..11e7f74e4 --- /dev/null +++ b/roms/u-boot/board/intel/edison/edison.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2017 Intel Corporation + */ +#include <common.h> +#include <env.h> +#include <init.h> +#include <mmc.h> +#include <u-boot/md5.h> + +#include <asm/cache.h> +#include <asm/pmu.h> +#include <asm/scu.h> +#include <asm/u-boot-x86.h> + +/* List of Intel Tangier LSSs */ +#define PMU_LSS_TANGIER_SDIO0_01 1 + +int board_early_init_r(void) +{ + pmu_turn_power(PMU_LSS_TANGIER_SDIO0_01, true); + return 0; +} + +static void assign_serial(void) +{ + struct mmc *mmc = find_mmc_device(0); + unsigned char ssn[16]; + char usb0addr[18]; + char serial[33]; + int i; + + if (!mmc) + return; + + md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn); + + snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x", + ssn[13], ssn[14], ssn[15]); + env_set("usb0addr", usb0addr); + + for (i = 0; i < 16; i++) + snprintf(&serial[2 * i], 3, "%02x", ssn[i]); + env_set("serial#", serial); + +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) + env_save(); +#endif +} + +static void assign_hardware_id(void) +{ + struct ipc_ifwi_version v; + char hardware_id[4]; + int ret; + + ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, 4); + if (ret < 0) + printf("Can't retrieve hardware revision\n"); + + snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id); + env_set("hardware_id", hardware_id); + +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) + env_save(); +#endif +} + +int board_late_init(void) +{ + if (!env_get("serial#")) + assign_serial(); + + if (!env_get("hardware_id")) + assign_hardware_id(); + + return 0; +} diff --git a/roms/u-boot/board/intel/galileo/.gitignore b/roms/u-boot/board/intel/galileo/.gitignore new file mode 100644 index 000000000..6eb8a5481 --- /dev/null +++ b/roms/u-boot/board/intel/galileo/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/roms/u-boot/board/intel/galileo/Kconfig b/roms/u-boot/board/intel/galileo/Kconfig new file mode 100644 index 000000000..fb8d94fb5 --- /dev/null +++ b/roms/u-boot/board/intel/galileo/Kconfig @@ -0,0 +1,25 @@ +if TARGET_GALILEO + +config SYS_BOARD + default "galileo" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "quark" + +config SYS_CONFIG_NAME + default "galileo" + +config SYS_TEXT_BASE + default 0xfff10000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_QUARK + select BOARD_ROMSIZE_KB_1024 + select SPI_FLASH_WINBOND + +endif diff --git a/roms/u-boot/board/intel/galileo/MAINTAINERS b/roms/u-boot/board/intel/galileo/MAINTAINERS new file mode 100644 index 000000000..dbbc82e8a --- /dev/null +++ b/roms/u-boot/board/intel/galileo/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL GALILEO BOARD +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/intel/galileo/ +F: include/configs/galileo.h +F: configs/galileo_defconfig diff --git a/roms/u-boot/board/intel/galileo/Makefile b/roms/u-boot/board/intel/galileo/Makefile new file mode 100644 index 000000000..4130bb023 --- /dev/null +++ b/roms/u-boot/board/intel/galileo/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + +obj-y += galileo.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/roms/u-boot/board/intel/galileo/acpi/mainboard.asl b/roms/u-boot/board/intel/galileo/acpi/mainboard.asl new file mode 100644 index 000000000..beb9d93ec --- /dev/null +++ b/roms/u-boot/board/intel/galileo/acpi/mainboard.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/roms/u-boot/board/intel/galileo/dsdt.asl b/roms/u-boot/board/intel/galileo/dsdt.asl new file mode 100644 index 000000000..d2297ef59 --- /dev/null +++ b/roms/u-boot/board/intel/galileo/dsdt.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/roms/u-boot/board/intel/galileo/galileo.c b/roms/u-boot/board/intel/galileo/galileo.c new file mode 100644 index 000000000..341b627a6 --- /dev/null +++ b/roms/u-boot/board/intel/galileo/galileo.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/device.h> +#include <asm/arch/quark.h> + +/* + * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin. + * + * We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this + * pin, as these APIs will eventually call into gpio_ich6_of_to_plat() + * in the Intel ICH6 GPIO driver where it calls PCI configuration space access + * APIs which will trigger PCI enumeration process. + * + * Check <asm/arch-quark/quark.h> for more details. + */ +void board_assert_perst(void) +{ + u32 base, port, val; + + /* retrieve the GPIO IO base */ + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base); + base = (base & 0xffff) & ~0x7f; + + /* enable the pin */ + port = base + 0x20; + val = inl(port); + val |= (1 << 0); + outl(val, port); + + /* configure the pin as output */ + port = base + 0x24; + val = inl(port); + val &= ~(1 << 0); + outl(val, port); + + /* pull it down (assert) */ + port = base + 0x28; + val = inl(port); + val &= ~(1 << 0); + outl(val, port); +} + +void board_deassert_perst(void) +{ + u32 base, port, val; + + /* retrieve the GPIO IO base */ + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base); + base = (base & 0xffff) & ~0x7f; + + /* pull it up (de-assert) */ + port = base + 0x28; + val = inl(port); + val |= (1 << 0); + outl(val, port); +} diff --git a/roms/u-boot/board/intel/minnowmax/.gitignore b/roms/u-boot/board/intel/minnowmax/.gitignore new file mode 100644 index 000000000..6eb8a5481 --- /dev/null +++ b/roms/u-boot/board/intel/minnowmax/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/roms/u-boot/board/intel/minnowmax/Kconfig b/roms/u-boot/board/intel/minnowmax/Kconfig new file mode 100644 index 000000000..82a6ca904 --- /dev/null +++ b/roms/u-boot/board/intel/minnowmax/Kconfig @@ -0,0 +1,31 @@ +if TARGET_MINNOWMAX + +config SYS_BOARD + default "minnowmax" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "minnowmax" + +config SYS_TEXT_BASE + default 0xfff00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_STMICRO + # Enable Winbond so we can use Dediprog em100pro emulator which does + # not support N25Q064 + select SPI_FLASH_WINBOND + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/roms/u-boot/board/intel/minnowmax/MAINTAINERS b/roms/u-boot/board/intel/minnowmax/MAINTAINERS new file mode 100644 index 000000000..d655761d5 --- /dev/null +++ b/roms/u-boot/board/intel/minnowmax/MAINTAINERS @@ -0,0 +1,6 @@ +CircuitCo Minnowboard Max +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/intel/minnowmax +F: include/configs/minnowmax.h +F: configs/minnowmax_defconfig diff --git a/roms/u-boot/board/intel/minnowmax/Makefile b/roms/u-boot/board/intel/minnowmax/Makefile new file mode 100644 index 000000000..d339b5ad0 --- /dev/null +++ b/roms/u-boot/board/intel/minnowmax/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015, Google, Inc + +obj-y += minnowmax.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/roms/u-boot/board/intel/minnowmax/acpi/mainboard.asl b/roms/u-boot/board/intel/minnowmax/acpi/mainboard.asl new file mode 100644 index 000000000..beb9d93ec --- /dev/null +++ b/roms/u-boot/board/intel/minnowmax/acpi/mainboard.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/roms/u-boot/board/intel/minnowmax/dsdt.asl b/roms/u-boot/board/intel/minnowmax/dsdt.asl new file mode 100644 index 000000000..d2297ef59 --- /dev/null +++ b/roms/u-boot/board/intel/minnowmax/dsdt.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/roms/u-boot/board/intel/minnowmax/minnowmax.c b/roms/u-boot/board/intel/minnowmax/minnowmax.c new file mode 100644 index 000000000..b02e3f0d4 --- /dev/null +++ b/roms/u-boot/board/intel/minnowmax/minnowmax.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015, Google, Inc + */ + +#include <common.h> +#include <dm.h> +#include <init.h> +#include <log.h> +#include <asm/gpio.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> + +#define GPIO_BANKE_NAME "gpioe" + +int misc_init_r(void) +{ + struct udevice *dev; + struct gpio_desc desc; + int ret; + + /* + * Turn on USB VBUS for the two USB ports on the board. + * Each port's VBUS is controlled by a GPIO pin. + */ + + ret = uclass_find_device_by_name(UCLASS_GPIO, GPIO_BANKE_NAME, &dev); + if (ret) { + debug("%s: GPIO %s device cannot be not found (ret=%d)\n", + __func__, GPIO_BANKE_NAME, ret); + return ret; + } + + ret = device_probe(dev); + if (ret) { + debug("%s: GPIO %s device probe failed (ret=%d)\n", + __func__, GPIO_BANKE_NAME, ret); + return ret; + } + + desc.dev = dev; + desc.flags = GPIOD_IS_OUT; + + /* GPIO E8 controls the bottom port */ + desc.offset = 8; + + ret = dm_gpio_request(&desc, "usb_host_en0"); + if (ret) + return ret; + dm_gpio_set_value(&desc, 1); + + /* GPIO E9 controls the upper port */ + desc.offset = 9; + + ret = dm_gpio_request(&desc, "usb_host_en1"); + if (ret) + return ret; + + dm_gpio_set_value(&desc, 1); + + return 0; +} diff --git a/roms/u-boot/board/intel/slimbootloader/Kconfig b/roms/u-boot/board/intel/slimbootloader/Kconfig new file mode 100644 index 000000000..8c7e22cc3 --- /dev/null +++ b/roms/u-boot/board/intel/slimbootloader/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Intel Corporation <www.intel.com> + +if TARGET_SLIMBOOTLOADER + +config SYS_BOARD + default "slimbootloader" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "slimbootloader" + +config SYS_CONFIG_NAME + default "slimbootloader" + +config SYS_TEXT_BASE + default 0x00100000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYS_SLIMBOOTLOADER + select USB_STORAGE + select USB_KEYBOARD + +endif diff --git a/roms/u-boot/board/intel/slimbootloader/MAINTAINERS b/roms/u-boot/board/intel/slimbootloader/MAINTAINERS new file mode 100644 index 000000000..e6935517e --- /dev/null +++ b/roms/u-boot/board/intel/slimbootloader/MAINTAINERS @@ -0,0 +1,6 @@ +Intel Slim Bootloader Payload +M: Aiden Park <aiden.park@intel.com> +S: Maintained +F: board/intel/slimbootloader +F: include/configs/slimbootloader.h +F: configs/slimbootloader_defconfig diff --git a/roms/u-boot/board/intel/slimbootloader/Makefile b/roms/u-boot/board/intel/slimbootloader/Makefile new file mode 100644 index 000000000..50330cc6e --- /dev/null +++ b/roms/u-boot/board/intel/slimbootloader/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Intel Corporation <www.intel.com> + +obj-y += slimbootloader.o diff --git a/roms/u-boot/board/intel/slimbootloader/slimbootloader.c b/roms/u-boot/board/intel/slimbootloader/slimbootloader.c new file mode 100644 index 000000000..b20ddf0c6 --- /dev/null +++ b/roms/u-boot/board/intel/slimbootloader/slimbootloader.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include <common.h> +#include <init.h> + +int board_early_init_r(void) +{ + /* + * Make sure PCI bus is enumerated so that peripherals on the PCI bus + * can be discovered by their drivers. + * + * Slim Bootloader has already done PCI bus enumeration before loading + * U-Boot, so U-Boot needs to preserve PCI configuration. + * Therefore, '# CONFIG_PCI_PNP is not set' is included in defconfig. + */ + pci_init(); + + return 0; +} |