5 files changed, 195 insertions, 0 deletions
diff --git a/roms/u-boot/board/mpc8308_p1m/Kconfig b/roms/u-boot/board/mpc8308_p1m/Kconfig
new file mode 100644
index 000000000..b7e39dafb
--- /dev/null
+++ b/roms/u-boot/board/mpc8308_p1m/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_MPC8308_P1M
+
+config SYS_BOARD
+	default "mpc8308_p1m"
+
+config SYS_CONFIG_NAME
+	default "mpc8308_p1m"
+
+endif
diff --git a/roms/u-boot/board/mpc8308_p1m/MAINTAINERS b/roms/u-boot/board/mpc8308_p1m/MAINTAINERS
new file mode 100644
index 000000000..80d8de771
--- /dev/null
+++ b/roms/u-boot/board/mpc8308_p1m/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8308_P1M BOARD
+M:	Ilya Yanok <yanok@emcraft.com>
+S:	Maintained
+F:	board/mpc8308_p1m/
+F:	include/configs/mpc8308_p1m.h
+F:	configs/mpc8308_p1m_defconfig
diff --git a/roms/u-boot/board/mpc8308_p1m/Makefile b/roms/u-boot/board/mpc8308_p1m/Makefile
new file mode 100644
index 000000000..4ec3b0cda
--- /dev/null
+++ b/roms/u-boot/board/mpc8308_p1m/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+
+obj-y	:= mpc8308_p1m.o sdram.o
diff --git a/roms/u-boot/board/mpc8308_p1m/mpc8308_p1m.c b/roms/u-boot/board/mpc8308_p1m/mpc8308_p1m.c
new file mode 100644
index 000000000..87607bd48
--- /dev/null
+++ b/roms/u-boot/board/mpc8308_p1m/mpc8308_p1m.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+int checkboard(void)
+{
+	printf("Board: MPC8308 P1M\n");
+
+	return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+	law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(1, pcie_reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+
+	return 0;
+}
+#endif
+
+int board_eth_init(struct bd_info *bis)
+{
+	int rv, num_if = 0;
+
+	/* Initialize TSECs first */
+	rv = cpu_eth_init(bis);
+	if (rv >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize TSECs.\n");
+
+	rv = pci_eth_init(bis);
+	if (rv >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+	return num_if;
+}
diff --git a/roms/u-boot/board/mpc8308_p1m/sdram.c b/roms/u-boot/board/mpc8308_p1m/sdram.c
new file mode 100644
index 000000000..62a2d8a53
--- /dev/null
+++ b/roms/u-boot/board/mpc8308_p1m/sdram.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This files is  mostly identical to the original from
+ * board/freescale/mpc8308rdb/sdram.c
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mpc83xx.h>
+#include <asm/global_data.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+			CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+}
+
+int dram_init(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
+}