diff options
Diffstat (limited to 'roms/u-boot/board/sunxi')
| -rw-r--r-- | roms/u-boot/board/sunxi/MAINTAINERS | 531 | ||||
| -rw-r--r-- | roms/u-boot/board/sunxi/Makefile | 14 | ||||
| -rw-r--r-- | roms/u-boot/board/sunxi/README.nand | 54 | ||||
| -rw-r--r-- | roms/u-boot/board/sunxi/README.sunxi64 | 216 | ||||
| -rw-r--r-- | roms/u-boot/board/sunxi/board.c | 1057 | ||||
| -rw-r--r-- | roms/u-boot/board/sunxi/chip.c | 100 | ||||
| -rw-r--r-- | roms/u-boot/board/sunxi/dram_sun4i_auto.c | 36 | ||||
| -rw-r--r-- | roms/u-boot/board/sunxi/dram_sun5i_auto.c | 39 | ||||
| -rw-r--r-- | roms/u-boot/board/sunxi/dram_timings_sun4i.h | 205 | ||||
| -rw-r--r-- | roms/u-boot/board/sunxi/gmac.c | 78 |
10 files changed, 2330 insertions, 0 deletions
diff --git a/roms/u-boot/board/sunxi/MAINTAINERS b/roms/u-boot/board/sunxi/MAINTAINERS new file mode 100644 index 000000000..76eba2ad2 --- /dev/null +++ b/roms/u-boot/board/sunxi/MAINTAINERS @@ -0,0 +1,531 @@ +SUNXI BOARD +M: Hans de Goede <hdegoede@redhat.com> +S: Maintained +F: board/sunxi/ +F: include/configs/sun4i.h +F: configs/A10-OLinuXino-Lime_defconfig +F: configs/ba10_tv_box_defconfig +F: configs/Chuwi_V7_CW0825_defconfig +F: configs/Cubieboard_defconfig +F: configs/dserve_dsrv9703c_defconfig +F: configs/Hyundai_A7HD_defconfig +F: configs/inet1_defconfig +F: configs/inet97fv2_defconfig +F: configs/inet9f_rev03_defconfig +F: configs/jesurun_q5_defconfig +F: configs/Mele_A1000_defconfig +F: configs/Mele_M3_defconfig +F: configs/Mini-X_defconfig +F: configs/mk802_defconfig +F: configs/mk802ii_defconfig +F: configs/pov_protab2_ips9_defconfig +F: include/configs/sun5i.h +F: configs/A10s-OLinuXino-M_defconfig +F: configs/A13-OLinuXino_defconfig +F: configs/A13-OLinuXinoM_defconfig +F: configs/Auxtek-T003_defconfig +F: configs/Auxtek-T004_defconfig +F: configs/CHIP_defconfig +F: configs/CHIP_pro_defconfig +F: configs/difrnce_dit4350_defconfig +F: configs/Empire_electronix_d709_defconfig +F: configs/Empire_electronix_m712_defconfig +F: configs/inet98v_rev2_defconfig +F: configs/mk802_a10s_defconfig +F: configs/q8_a13_tablet_defconfig +F: configs/r7-tv-dongle_defconfig +F: configs/UTOO_P66_defconfig +F: configs/Wobo_i5_defconfig +F: include/configs/sun6i.h +F: configs/colorfly_e708_q1_defconfig +F: configs/CSQ_CS908_defconfig +F: configs/inet_q972_defconfig +F: configs/Mele_A1000G_quad_defconfig +F: configs/Mele_M9_defconfig +F: configs/Sinovoip_BPI_M2_defconfig +F: include/configs/sun7i.h +F: configs/A20-OLinuXino_MICRO_defconfig +F: configs/A20-OLinuXino_MICRO-eMMC_defconfig +F: configs/Bananapi_defconfig +F: configs/Bananapro_defconfig +F: configs/i12-tvbox_defconfig +F: configs/Linksprite_pcDuino3_defconfig +F: configs/Linksprite_pcDuino3_fdt_defconfig +F: configs/Orangepi_defconfig +F: configs/Orangepi_mini_defconfig +F: configs/qt840a_defconfig +F: configs/Wits_Pro_A20_DKT_defconfig +F: include/configs/sun8i.h +F: configs/sun8i_a23_evb_defconfig +F: configs/ga10h_v1_1_defconfig +F: configs/gt90h_v4_defconfig +F: configs/inet86dz_defconfig +F: configs/orangepi_2_defconfig +F: configs/orangepi_lite_defconfig +F: configs/orangepi_one_defconfig +F: configs/orangepi_pc_defconfig +F: configs/orangepi_pc_plus_defconfig +F: configs/orangepi_plus_defconfig +F: configs/orangepi_plus2e_defconfig +F: configs/polaroid_mid2407pxe03_defconfig +F: configs/polaroid_mid2809pxe04_defconfig +F: configs/q8_a23_tablet_800x480_defconfig +F: configs/q8_a33_tablet_800x480_defconfig +F: configs/q8_a33_tablet_1024x600_defconfig +F: include/configs/sun9i.h +F: configs/Merrii_A80_Optimus_defconfig +F: include/configs/sun50i.h + +A20-OLIMEX-SOM-EVB BOARD +M: Marcus Cooper <codekipper@gmail.com> +S: Maintained +F: configs/A20-Olimex-SOM-EVB_defconfig + +A20-OLINUXINO-LIME BOARD +M: FUKAUMI Naoki <naobsd@gmail.com> +S: Maintained +F: configs/A20-OLinuXino-Lime_defconfig + +A20-OLINUXINO-LIME2 BOARD +M: Iain Paton <ipaton0@gmail.com> +S: Maintained +F: configs/A20-OLinuXino-Lime2_defconfig + +A20-OLINUXINO-LIME2-EMMC BOARD +M: Olliver Schinagl <oliver@schinagl.nl> +S: Maintained +F: configs/A20-OLinuXino-Lime2-eMMC_defconfig + +A33-OLINUXINO BOARD +M: Stefan Mavrodiev <stefan.mavrodiev@gmail.com> +S: Maintained +F: configs/A33-OLinuXino_defconfig + +A64-OLINUXINO BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/a64-olinuxino_defconfig + +A64-OLINUXINO-EMMC BOARD +M: Sunil Mohan Adapa <sunil@medhas.org> +S: Maintained +F: configs/a64-olinuxino-emmc_defconfig + +A80 OPTIMUS BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Merrii_A80_Optimus_defconfig + +AINOL AW1 BOARD +M: Paul Kocialkowski <contact@paulk.fr> +S: Maintained +F: configs/Ainol_AW1_defconfig + +AMARULA A64-RELIC +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/amarula_a64_relic_defconfig +F: arch/arm/dts/sun50i-a64-amarula-relic.dts + +AMPE A76 BOARD +M: Paul Kocialkowski <contact@paulk.fr> +S: Maintained +F: configs/Ampe_A76_defconfig + +BANANAPI M1 PLUS +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/bananapi_m1_plus_defconfig + +BANANAPI M2 BERRY +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/bananapi_m2_berry_defconfig + +BANANAPI M2 PLUS BOARDS +M: Icenowy Zheng <icenowy@aosc.io> +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/bananapi_m2_plus_h3_defconfig +F: configs/bananapi_m2_plus_h5_defconfig + +BANANAPI M2 ULTRA BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Bananapi_M2_Ultra_defconfig +F: arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts + +BANANAPI M2 MAGIC BOARD +M: Maxime Ripard <mripard@kernel.org> +S: Maintained +F: configs/Bananapi_m2m_defconfig +F: arch/arm/dts/sun8i-r16-bananapi-m2m.dts + +BANANAPI M2 ZERO BOARD +M: Icenowy Zheng <icenowy@aosc.io> +S: Maintained +F: configs/bananapi_m2_zero_defconfig + +BANANAPI M64 +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/bananapi_m64_defconfig + +BEELINK GS1 +M: Clément Péron <peron.clem@gmail.com> +S: Maintained +F: configs/beelink_gs1_defconfig +F: arch/arm/dts/sun50i-h6-beelink-gs1.dts + +BEELINK X2 BOARD +M: Marcus Cooper <codekipper@gmail.com> +S: Maintained +F: configs/beelink_x2_defconfig +F: arch/arm/dts/sun8i-h3-beelink-x2.dts + +COLOMBUS BOARD +M: Maxime Ripard <mripard@kernel.org> +S: Maintained +F: configs/Colombus_defconfig + +CUBIEBOARD2 BOARD +M: Ian Campbell <ijc@hellion.org.uk> +M: Hans de Goede <hdegoede@redhat.com> +S: Maintained +F: include/configs/sun7i.h +F: configs/Cubieboard2_defconfig +F: configs/Cubietruck_defconfig + +CUBIEBOARD4 BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Cubieboard4_defconfig + +CUBIETRUCK-PLUS BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Cubietruck_plus_defconfig + +EMLID NEUTIS N5 DEV BOARD +M: Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com> +S: Maintained +F: configs/emlid_neutis_n5_devboard_defconfig + +GEMEI-G9 TABLET +M: Priit Laes <plaes@plaes.org> +S: Maintained +F: configs/sunxi_Gemei_G9_defconfig + +H8HOMLET PROTO A83T BOARD +M: VishnuPatekar <vishnupatekar0510@gmail.com> +S: Maintained +F: configs/h8_homlet_v2_defconfig + +HUMMINGBIRD-A31 BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Hummingbird_A31_defconfig + +ICnova-A20-SWAC BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: configs/icnova-a20-swac_defconfig + +ITEAD IBOX BOARD +M: Marcus Cooper <codekipper@gmail.com> +S: Maintained +F: configs/Itead_Ibox_A20_defconfig + +INET 3F BOARD +M: Paul Kocialkowski <contact@paulk.fr> +S: Maintained +F: configs/iNet_3F_defconfig + +INET 3W BOARD +M: Paul Kocialkowski <contact@paulk.fr> +S: Maintained +F: configs/iNet_3W_defconfig + +INET 86VS BOARD +M: Michal Suchanek <hramrach@gmail.com> +S: Maintained +F: configs/iNet_86VS_defconfig + +INET D978 BOARD +M: Icenowy Zheng <icenowy@aosc.xyz> +S: Maintained +F: configs/iNet_D978_rev2_defconfig + +LAMOBO-R1 BOARD +M: Jelle de Jong <jelledejong@powercraft.nl> +S: Maintained +F: configs/Lamobo_R1_defconfig + +LICHEEPI-ZERO BOARD +M: Icenowy Zheng <icenowy@aosc.xyz> +S: Maintained +F: configs/LicheePi_Zero_defconfig + +LINKSPRITE-PCDUINO BOARD +M: Zoltan Herpai <wigyori@uid0.hu> +S: Maintained +F: configs/Linksprite_pcDuino_defconfig + +LINKSPRITE-PCDUINO3-NANO BOARD +M: Adam Sampson <ats@offog.org> +S: Maintained +F: configs/Linksprite_pcDuino3_Nano_defconfig + +MARSBOARD-A10 BOARD +M: Aleksei Mamlin <mamlinav@gmail.com> +S: Maintained +F: configs/Marsboard_A10_defconfig + +MELE I7 BOARD +M: Marcus Cooper <codekipper@gmail.com> +S: Maintained +F: configs/Mele_I7_defconfig + +MELE M5 BOARD +M: Ian Campbell <ijc@hellion.org.uk> +S: Maintained +F: configs/Mele_M5_defconfig + +MIXTILE-LOFTQ BOARD +M: Phil Han <pengphei@sina.com> +S: Maintained +F: configs/mixtile_loftq_defconfig + +MK808C BOARD +M: Marcus Cooper <codekipper@gmail.com> +S: Maintained +F: configs/MK808C_defconfig + +MSI-PRIMO73 BOARD +M: Siarhei Siamashka <siarhei.siamashka@gmail.com> +S: Maintained +F: configs/MSI_Primo73_defconfig + +MSI-PRIMO81 BOARD +M: Siarhei Siamashka <siarhei.siamashka@gmail.com> +S: Maintained +F: configs/MSI_Primo81_defconfig + +LIBRETECH ALL-H3-CC BOARDS +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/libretech_all_h3_cc_h2_plus_defconfig +F: configs/libretech_all_h3_cc_h3_defconfig +F: configs/libretech_all_h3_cc_h5_defconfig + +LIBRETECH ALL-H3-IT BOARDS +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/libretech_all_h3_it_h5_defconfig + +LIBRETECH ALL-H5-CC BOARDS +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/libretech_all_h5_cc_h5_defconfig + +NANOPI-M1 BOARD +M: Mylène Josserand <mylene.josserand@free-electrons.com> +S: Maintained +F: configs/nanopi_m1_defconfig + +NANOPI-M1 PLUS BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/nanopi_m1_plus_defconfig + +NANOPI-NEO BOARD +M: Jelle van der Waa <jelle@vdwaa.nl> +S: Maintained +F: configs/nanopi_neo_defconfig + +NANOPI-NEO2 BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/nanopi_neo2_defconfig + +NANOPI-NEO-PLUS2 BOARD +M: Antony Antony <antony@phenome.org> +S: Maintained +F: configs/nanopi_neo_plus2_defconfig + +NANOPI-NEO-AIR BOARD +M: Jelle van der Waa <jelle@vdwaa.nl> +S: Maintained +F: configs/nanopi_neo_air_defconfig + +NANOPI-A64 BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/nanopi_a64_defconfig + +NINTENDO NES CLASSIC EDITION BOARD +M: FUKAUMI Naoki <naobsd@gmail.com> +S: Maintained +F: configs/Nintendo_NES_Classic_Edition_defconfig + +OCEANIC 5205 5INMFD BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/oceanic_5205_5inmfd_defconfig + +OLIMEX A20-SOM204 BOARD +M: Stefan Mavrodiev <stefan@olimex.com> +S: Maintained +F: configs/A20-Olimex-SOM204-EVB_defconfig +F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig + +OLIMEX TERES-I BOARD +M: Jonas Smedegaard <dr@jones.dk> +M: Icenowy Zheng <icenowy@aosc.io> +S: Maintained +F: configs/teres_i_defconfig + +ORANGEPI 3 BOARD +M: Andre Heider <a.heider@gmail.com> +S: Maintained +F: configs/orangepi_3_defconfig + +ORANGEPI LITE2 BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi_lite2_defconfig + +ORANGEPI ONE PLUS BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi_one_plus_defconfig + +ORANGEPI WIN/WIN PLUS BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi_win_defconfig + +ORANGEPI ZERO BOARD +M: Icenowy Zheng <icenowy@aosc.xyz> +S: Maintained +F: configs/orangepi_zero_defconfig + +ORANGEPI ZERO PLUS BOARD +M: Hauke Mehrtens <hauke@hauke-m.de> +S: Maintained +F: configs/orangepi_zero_plus_defconfig + +ORANGEPI ZERO PLUS 2 BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi_zero_plus2_defconfig + +ORANGEPI ZERO PLUS 2 H3 BOARD +M: Diego Rondini <diego.rondini@kynetics.com> +S: Maintained +F: configs/orangepi_zero_plus2_h3_defconfig + +ORANGEPI ZERO 2 BOARD +M: Jernej Skrabec <jernej.skrabec@siol.net> +S: Maintained +F: configs/orangepi_zero2_defconfig + +ORANGEPI PC 2 BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/orangepi_pc2_defconfig + +ORANGEPI PRIME BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi_prime_defconfig + +ORANGEPI R1 BOARD +M: Hauke Mehrtens <hauke@hauke-m.de> +S: Maintained +F: configs/orangepi_r1_defconfig + +PINEBOOK BOARD: +M: Vasily Khoruzhick <anarsoul@gmail.com> +S: Maintained +F: configs/pinebook_defconfig + +PINECUBE BOARD: +M: Icenowy Zheng <icenowy@aosc.io> +S: Maintained +F: configs/pinecube_defconfig + +PINE64 BOARDS +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/pine64_plus_defconfig +F: configs/pine64-lts_defconfig + +PINE H64 BOARD +M: Icenowy Zheng <icenowy@aosc.io> +S: Maintained +F: configs/pine_h64_defconfig + +PINEPHONE BOARD +M: Samuel Holland <samuel@sholland.org> +S: Maintained +F: configs/pinephone_defconfig + +R16 EVB PARROT BOARD +M: Quentin Schulz <quentin.schulz@free-electrons.com> +S: Maintained +F: configs/parrot_r16_defconfig + +SINLINX SINA31s BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Sinlinx_SinA31s_defconfig +W: http://linux-sunxi.org/Sinlinx_SinA31s + +SINLINX SINA33 BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Sinlinx_SinA33_defconfig +W: http://linux-sunxi.org/Sinlinx_SinA33 + +SINOVOIP BPI M3 A83T BOARD +M: VishnuPatekar <vishnupatekar0510@gmail.com> +S: Maintained +F: configs/Sinovoip_BPI_M3_defconfig + +SOPINE BOARD +M: Icenowy Zheng <icenowy@aosc.io> +S: Maintained +F: configs/sopine_baseboard_defconfig + +SUNCHIP CX-A99 BOARD +M: Rask Ingemann Lambertsen <rask@formelder.dk> +S: Maintained +F: configs/Sunchip_CX-A99_defconfig +W: https://linux-sunxi.org/Sunchip_CX-A99 + +TANIX TX6 BOARD +M: Jernej Skrabec <jernej.skrabec@siol.net> +S: Maintained +F: configs/tanix_tx6_defconfig +W: https://linux-sunxi.org/Tanix_TX6 + +TBS A711 BOARD +M: Maxime Ripard <mripard@kernel.org> +S: Maintained +F: configs/tbs_a711_defconfig + +WEXLER-TAB7200 BOARD +M: Aleksei Mamlin <mamlinav@gmail.com> +S: Maintained +F: configs/Wexler_TAB7200_defconfig + +YONES TOPTECH BD1078 BOARD +M: Paul Kocialkowski <contact@paulk.fr> +S: Maintained +F: configs/Yones_Toptech_BD1078_defconfig + +YONES TOPTECH BS1078 V2 BOARD +M: Peter Korsgaard <peter@korsgaard.com> +S: Maintained +F: configs/Yones_Toptech_BS1078_V2_defconfig diff --git a/roms/u-boot/board/sunxi/Makefile b/roms/u-boot/board/sunxi/Makefile new file mode 100644 index 000000000..d96b7897b --- /dev/null +++ b/roms/u-boot/board/sunxi/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> +# +# Based on some other board Makefile +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +obj-y += board.o +obj-$(CONFIG_SUN7I_GMAC) += gmac.o +obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o +obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o +obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o +obj-$(CONFIG_CHIP_DIP_SCAN) += chip.o diff --git a/roms/u-boot/board/sunxi/README.nand b/roms/u-boot/board/sunxi/README.nand new file mode 100644 index 000000000..0e97316ae --- /dev/null +++ b/roms/u-boot/board/sunxi/README.nand @@ -0,0 +1,54 @@ +Allwinner NAND flashing +======================= + +A lot of Allwinner devices, especially the older ones (pre-H3 era), +comes with a NAND. NANDs storages are a pretty weak choice when it +comes to the reliability, and it comes with a number of flaws like +read and write disturbs, data retention issues, bloks becoming +unusable, etc. + +In order to mitigate that, various strategies have been found to be +able to recover from those issues like ECC, hardware randomization, +and of course, redundancy for the critical parts. + +This is obviously something that we will take into account when +creating our images. However, the BROM will use a quite weird pattern +when accessing the NAND, and will access only at most 4kB per page, +which means that we also have to split that binary accross several +pages. + +In order to accomodate that, we create a tool that will generate an +SPL image that is ready to be programmed directly embedding the ECCs, +randomized, and with the necessary bits needed to reduce the number of +bitflips. The U-Boot build system, when configured for the NAND (with +CONFIG_MTD_RAW_NAND=y) will also generate the image sunxi-spl-with-ecc.bin +that will have been generated by that tool. + +In order to flash your U-Boot image onto a board, assuming that the +board is in FEL mode, you'll need the sunxi-tools that you can find at +this repository: https://github.com/linux-sunxi/sunxi-tools + +Then, you'll need to first load an SPL to initialise the RAM: +sunxi-fel spl spl/sunxi-spl.bin + +Load the binaries we'll flash into RAM: +sunxi-fel write 0x4a000000 u-boot-dtb.bin +sunxi-fel write 0x43000000 spl/sunxi-spl-with-ecc.bin + +And execute U-Boot +sunxi-fel exe 0x4a000000 + +On your board, you'll now have all the needed binaries into RAM, so +you only need to erase the NAND... + +nand erase.chip + +Then write the SPL and its backup: + +nand write.raw.noverify 0x43000000 0 40 +nand write.raw.noverify 0x43000000 0x400000 40 + +And finally write the U-Boot binary: +nand write 0x4a000000 0x800000 0xc0000 + +You can now reboot and enjoy your NAND.
\ No newline at end of file diff --git a/roms/u-boot/board/sunxi/README.sunxi64 b/roms/u-boot/board/sunxi/README.sunxi64 new file mode 100644 index 000000000..4803bc9ff --- /dev/null +++ b/roms/u-boot/board/sunxi/README.sunxi64 @@ -0,0 +1,216 @@ +Allwinner 64-bit boards README +============================== + +Newer Allwinner SoCs feature ARMv8 cores (ARM Cortex-A53) with support for +both the 64-bit AArch64 mode and the ARMv7 compatible 32-bit AArch32 mode. +Examples are the Allwinner A64 (used for instance on the Pine64 board) or +the Allwinner H5 SoC (as used on the OrangePi PC 2). +These SoCs are wired to start in AArch32 mode on reset and execute 32-bit +code from the Boot ROM (BROM). As this has some implications on U-Boot, this +file describes how to make full use of the 64-bit capabilities. + +Quick Start / Overview +====================== +- Build the ARM Trusted Firmware binary (see "ARM Trusted Firmware (ATF)" below) + $ cd /src/arm-trusted-firmware + $ make PLAT=sun50i_a64 DEBUG=1 bl31 +- Build the SCP firmware binary (see "SCP firmware (Crust)" below) + $ cd /src/crust + $ make pine64_plus_defconfig && make -j5 scp +- Build U-Boot (see "SPL/U-Boot" below) + $ export BL31=/path/to/bl31.bin + $ export SCP=/src/crust/build/scp/scp.bin + $ make pine64_plus_defconfig && make -j5 +- Transfer to an uSD card (see "microSD card" below) + $ dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1 +- Boot and enjoy! + +Building the firmware +===================== + +The Allwinner A64/H5/H6 firmware consists of several parts: U-Boot's SPL, +ARM Trusted Firmware (ATF), optional System Control Processor (SCP) firmware +(e.g. Crust), and the U-Boot proper. + +The SPL will load all of the other firmware binaries into RAM, along with the +right device tree blob (.dtb), and will pass execution to ATF (in EL3). If SCP +firmware was loaded, ATF will power on the SCP and wait for it to boot. +ATF will then drop into U-Boot proper (in EL2). + +As the ATF binary and SCP firmware will become part of the U-Boot image file, +you will need to build them first. + + ARM Trusted Firmware (ATF) +---------------------------- +Checkout the latest master branch from the official ATF repository [1] and +build it: +$ export CROSS_COMPILE=aarch64-linux-gnu- +$ make PLAT=sun50i_a64 DEBUG=1 bl31 +The resulting binary is build/sun50i_a64/debug/bl31.bin. Either put the +location of this file into the BL31 environment variable or copy this to +the root of your U-Boot build directory (or create a symbolic link). +$ export BL31=/src/arm-trusted-firmware/build/sun50i_a64/debug/bl31.bin + (adjust the actual path accordingly) +The platform target "sun50i_a64" covers all boards with either an Allwinner +A64 or H5 SoC (since they are very similar). For boards with an Allwinner H6 +SoC use "sun50i_h6". + +If you run into size issues with the resulting U-Boot image file, it might +help to use a release build, by using "DEBUG=0" when building bl31.bin. +As sometimes the ATF build process is a bit picky about the toolchain used, +or if you can't be bothered with building ATF, there are known working +binaries in the firmware repository[3], purely for convenience reasons. + + SCP firmware (Crust) +---------------------- +SCP firmware is responsible for implementing system suspend/resume, and (on +boards without a PMIC) soft poweroff/on. ATF contains fallback code for CPU +power control, so SCP firmware is optional if you don't need either of these +features. It runs on the AR100, with is an or1k CPU, not ARM, so it needs a +different cross toolchain. + +There is one SCP firmware implementation currently available, Crust: +$ git clone https://github.com/crust-firmware/crust +$ cd crust +$ export CROSS_COMPILE=or1k-linux-musl- +$ make pine64_plus_defconfig +$ make scp + +The same configuration generally works on any board with the same SoC (A64, H5, +or H6), so if there is no config for your board, use one for a similar board. + +Like for ATF, U-Boot finds the SCP firmware binary via an environment variable: +$ export SCP=/src/crust/build/scp/scp.bin + +If you do not want to use SCP firmware, you can silence the warning from binman +by pointing it to an empty file: +$ export SCP=/dev/null + + SPL/U-Boot +------------ +Both U-Boot proper and the SPL are using the 64-bit mode. As the boot ROM +enters the SPL still in AArch32 secure SVC mode, there is some shim code to +enter AArch64 very early. The rest of the SPL runs in AArch64 EL3. +U-Boot proper runs in EL2 and can load any AArch64 code (using the "go" +command), EFI applications (with "bootefi") or arm64 Linux kernel images +(often named "Image"), using the "booti" command. + +$ make clean +$ export CROSS_COMPILE=aarch64-linux-gnu- +$ make pine64_plus_defconfig +$ make + +This will build the SPL in spl/sunxi-spl.bin and a FIT image called u-boot.itb, +which contains the rest of the firmware. u-boot-sunxi-with-spl.bin joins those +two components in one convenient image file. + + +Boot process +============ +The on-die BROM code will try several methods to load and execute the firmware. +On a typical board like the Pine64 this will result in the following boot order: + +1) Reading 32KB from sector 16 (@8K) of the microSD card to SRAM A1. If the +BROM finds the magic "eGON" header in the first bytes, it will execute that +code. If not (no SD card at all or invalid magic), it will: +2) Try to read 32KB from sector 16 (@8K) of memory connected to the MMC2 +controller, typically an on-board eMMC chip. If there is no eMMC or it does +not contain a valid boot header, it will: +3) Initialize the SPI0 controller and try to access a NOR flash connected to +it (using the CS0 pin). If a flash chip is found, the BROM will load the +first 32KB (from offset 0) into SRAM A1. Now it checks for the magic eGON +header and checksum and will execute the code upon finding it. If not, it will: +4) Initialize the USB OTG controller and will wait for a host to connect to +it, speaking the Allwinner proprietary (but deciphered) "FEL" USB protocol. + + +To boot the Pine64 board, you can use U-Boot and any of the described methods. + +FEL boot (USB OTG) +------------------ +FEL is the name of the Allwinner defined USB boot protocol built in the +mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely +by using the USB-OTG interface and a host port on another computer. +As the FEL mode is controlled by the boot ROM, it expects to be running in +AArch32. For now the AArch64 SPL cannot properly return into FEL mode, so the +feature is disabled in the configuration at the moment. +The repository in [3] contains FEL capable SPL binaries, built using an +off-tree branch to generate 32-bit ARM code (along with instructions +how to re-create them). + +microSD card +------------ +Transfer the SPL and the U-Boot FIT image directly to an uSD card: +# dd if=spl/sunxi-spl.bin of=/dev/sdx bs=8k seek=1 +# dd if=u-boot.itb of=/dev/sdx bs=8k seek=5 +# sync +(replace /dev/sdx with you SD card device file name, which could be +/dev/mmcblk[x] as well). + +Alternatively you can use the SPL and the U-Boot FIT image combined into a +single file and transfer that instead: +# dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1 + +You can partition the microSD card, but leave the first MB unallocated (most +partitioning tools will do this anyway). + +NOR flash +--------- +Some boards (like the SoPine, Pinebook or the OrangePi PC2) come with a +soldered SPI NOR flash chip. On other boards like the Pine64 such a chip +can be connected to the SPI0/CS0 pins on the PI-2 headers. +Create the SPL and FIT image like described above for the SD card. +Now connect either an "A to A" USB cable to the upper USB port on the Pine64 +or get an adaptor and use a regular A-microB cable connected to it. Other +boards often have a proper micro-B USB socket connected to the USB OTB port. +Remove a microSD card from the slot and power on the board. +On your host computer download and build the sunxi-tools package[2], then +use "sunxi-fel" to access the board: +$ ./sunxi-fel ver -v -p +This should give you an output starting with: AWUSBFEX soc=00001689(A64) ... +Now use the sunxi-fel tool to write to the NOR flash: +$ ./sunxi-fel spiflash-write 0 spl/sunxi-spl.bin +$ ./sunxi-fel spiflash-write 32768 u-boot.itb +Now boot the board without an SD card inserted and you should see the +U-Boot prompt on the serial console. + +(Legacy) boot0 method +--------------------- +boot0 is Allwinner's secondary program loader and it can be used as some kind +of SPL replacement to get U-Boot up and running from an microSD card. +For some time using boot0 was the only option to get the Pine64 booted. +With working DRAM init code in U-Boot's SPL this is no longer necessary, +but this method is described here for the sake of completeness. +Please note that this method works only with the boot0 files shipped with +A64 based boards, the H5 uses an incompatible layout which is not supported +by this method. + +The boot0 binary is a 32 KByte blob and contained in the official Pine64 images +distributed by Pine64 or Allwinner. It can be easily extracted from a micro +SD card or an image file: +# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4 +where /dev/sd<x> is the device name of the uSD card or the name of the image +file. Apparently Allwinner allows re-distribution of this proprietary code +"as-is". +This boot0 blob takes care of DRAM initialisation and loads the remaining +firmware parts, then switches the core into AArch64 mode. +The original boot0 code looks for U-Boot at a certain place on an uSD card +(at 19096 KB), also it expects a header with magic bytes and a checksum. +There is a tool called boot0img[3] which takes a boot0.bin image and a compiled +U-Boot binary (plus other binaries) and will populate that header accordingly. +To make space for the magic header, the pine64_plus_defconfig will make sure +there is sufficient space at the beginning of the U-Boot binary. +boot0img will also take care of putting the different binaries at the right +places on the uSD card and works around unused, but mandatory parts by using +trampoline code. See the output of "boot0img -h" for more information. +boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead +fetching it from just behind the boot0 binary (-B option). +$ ./boot0img -o firmware.img -B boot0.img -u u-boot-dtb.bin -e -s bl31.bin \ +-a 0x44008 -d trampoline64:0x44000 +Then write this image to a microSD card, replacing /dev/sdx with the right +device file (see above): +$ dd if=firmware.img of=/dev/sdx bs=8k seek=1 + +[1] https://github.com/ARM-software/arm-trusted-firmware.git +[2] git://github.com/linux-sunxi/sunxi-tools.git +[3] https://github.com/apritzel/pine64/ diff --git a/roms/u-boot/board/sunxi/board.c b/roms/u-boot/board/sunxi/board.c new file mode 100644 index 000000000..21651a1bf --- /dev/null +++ b/roms/u-boot/board/sunxi/board.c @@ -0,0 +1,1057 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * Some board init for the Allwinner A10-evb board. + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <hang.h> +#include <image.h> +#include <init.h> +#include <log.h> +#include <mmc.h> +#include <axp_pmic.h> +#include <generic-phy.h> +#include <phy-sun4i-usb.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/display.h> +#include <asm/arch/dram.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> +#include <asm/arch/prcm.h> +#include <asm/arch/spl.h> +#include <asm/global_data.h> +#include <linux/delay.h> +#include <u-boot/crc.h> +#ifndef CONFIG_ARM64 +#include <asm/armv7.h> +#endif +#include <asm/gpio.h> +#include <asm/io.h> +#include <u-boot/crc.h> +#include <env_internal.h> +#include <linux/libfdt.h> +#include <fdt_support.h> +#include <nand.h> +#include <net.h> +#include <spl.h> +#include <sy8106a.h> +#include <asm/setup.h> + +#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) +/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ +int soft_i2c_gpio_sda; +int soft_i2c_gpio_scl; + +static int soft_i2c_board_init(void) +{ + int ret; + + soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); + if (soft_i2c_gpio_sda < 0) { + printf("Error invalid soft i2c sda pin: '%s', err %d\n", + CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); + return soft_i2c_gpio_sda; + } + ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); + if (ret) { + printf("Error requesting soft i2c sda pin: '%s', err %d\n", + CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); + return ret; + } + + soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); + if (soft_i2c_gpio_scl < 0) { + printf("Error invalid soft i2c scl pin: '%s', err %d\n", + CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); + return soft_i2c_gpio_scl; + } + ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); + if (ret) { + printf("Error requesting soft i2c scl pin: '%s', err %d\n", + CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); + return ret; + } + + return 0; +} +#else +static int soft_i2c_board_init(void) { return 0; } +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void i2c_init_board(void) +{ +#ifdef CONFIG_I2C0_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN5I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN8I_V3S) + sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); + clock_twi_onoff(0, 1); +#endif +#endif + +#ifdef CONFIG_I2C1_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1); + clock_twi_onoff(1, 1); +#endif +#endif + +#ifdef CONFIG_I2C2_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); + clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); + clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); + clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); + clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2); + clock_twi_onoff(2, 1); +#endif +#endif + +#ifdef CONFIG_I2C3_ENABLE +#if defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); + sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); + clock_twi_onoff(3, 1); +#elif defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); + sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); + clock_twi_onoff(3, 1); +#endif +#endif + +#ifdef CONFIG_I2C4_ENABLE +#if defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); + sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); + clock_twi_onoff(4, 1); +#endif +#endif + +#ifdef CONFIG_R_I2C_ENABLE +#ifdef CONFIG_MACH_SUN50I + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); +#elif CONFIG_MACH_SUN50I_H616 + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); +#else + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); +#endif +#endif +} + +#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT) +enum env_location env_get_location(enum env_operation op, int prio) +{ + switch (prio) { + case 0: + return ENVL_FAT; + + case 1: + return ENVL_MMC; + + default: + return ENVL_UNKNOWN; + } +} +#endif + +#ifdef CONFIG_DM_MMC +static void mmc_pinmux_setup(int sdc); +#endif + +/* add board specific code here */ +int board_init(void) +{ + __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin; + + gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); + +#ifndef CONFIG_ARM64 + asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); + debug("id_pfr1: 0x%08x\n", id_pfr1); + /* Generic Timer Extension available? */ + if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { + uint32_t freq; + + debug("Setting CNTFRQ\n"); + + /* + * CNTFRQ is a secure register, so we will crash if we try to + * write this from the non-secure world (read is OK, though). + * In case some bootcode has already set the correct value, + * we avoid the risk of writing to it. + */ + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); + if (freq != COUNTER_FREQUENCY) { + debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", + freq, COUNTER_FREQUENCY); +#ifdef CONFIG_NON_SECURE + printf("arch timer frequency is wrong, but cannot adjust it\n"); +#else + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); +#endif + } + } +#endif /* !CONFIG_ARM64 */ + + ret = axp_gpio_init(); + if (ret) + return ret; + + /* strcmp() would look better, but doesn't get optimised away. */ + if (CONFIG_SATAPWR[0]) { + satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR); + if (satapwr_pin >= 0) { + gpio_request(satapwr_pin, "satapwr"); + gpio_direction_output(satapwr_pin, 1); + + /* + * Give the attached SATA device time to power-up + * to avoid link timeouts + */ + mdelay(500); + } + } + + if (CONFIG_MACPWR[0]) { + macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR); + if (macpwr_pin >= 0) { + gpio_request(macpwr_pin, "macpwr"); + gpio_direction_output(macpwr_pin, 1); + } + } + +#if CONFIG_IS_ENABLED(DM_I2C) + /* + * Temporary workaround for enabling I2C clocks until proper sunxi DM + * clk, reset and pinctrl drivers land. + */ + i2c_init_board(); +#endif + +#ifdef CONFIG_DM_MMC + /* + * Temporary workaround for enabling MMC clocks until a sunxi DM + * pinctrl driver lands. + */ + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); +#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); +#endif +#endif /* CONFIG_DM_MMC */ + + /* Uses dm gpio code so do this here and not in i2c_init_board() */ + return soft_i2c_board_init(); +} + +/* + * On older SoCs the SPL is actually at address zero, so using NULL as + * an error value does not work. + */ +#define INVALID_SPL_HEADER ((void *)~0UL) + +static struct boot_file_head * get_spl_header(uint8_t req_version) +{ + struct boot_file_head *spl = (void *)(ulong)SPL_ADDR; + uint8_t spl_header_version = spl->spl_signature[3]; + + /* Is there really the SPL header (still) there? */ + if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) + return INVALID_SPL_HEADER; + + if (spl_header_version < req_version) { + printf("sunxi SPL version mismatch: expected %u, got %u\n", + req_version, spl_header_version); + return INVALID_SPL_HEADER; + } + + return spl; +} + +static const char *get_spl_dt_name(void) +{ + struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION); + + /* Check if there is a DT name stored in the SPL header. */ + if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) + return (char *)spl + spl->dt_name_offset; + + return NULL; +} + +int dram_init(void) +{ + struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION); + + if (spl == INVALID_SPL_HEADER) + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, + PHYS_SDRAM_0_SIZE); + else + gd->ram_size = (phys_addr_t)spl->dram_size << 20; + + if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE) + gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE; + + return 0; +} + +#if defined(CONFIG_NAND_SUNXI) +static void nand_pinmux_setup(void) +{ + unsigned int pin; + + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); + +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I + for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); +#endif + /* sun4i / sun7i do have a PC23, but it is not used for nand, + * only sun7i has a PC24 */ +#ifdef CONFIG_MACH_SUN7I + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); +#endif +} + +static void nand_clock_setup(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ + defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I + setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); +#endif + setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); +} + +void board_nand_init(void) +{ + nand_pinmux_setup(); + nand_clock_setup(); +#ifndef CONFIG_SPL_BUILD + sunxi_nand_init(); +#endif +} +#endif + +#ifdef CONFIG_MMC +static void mmc_pinmux_setup(int sdc) +{ + unsigned int pin; + __maybe_unused int pins; + + switch (sdc) { + case 0: + /* SDC0: PF0-PF5 */ + for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 1: + pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); + +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + if (pins == SUNXI_GPIO_H) { + /* SDC1: PH22-PH-27 */ + for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + } else { + /* SDC1: PG0-PG5 */ + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + } +#elif defined(CONFIG_MACH_SUN5I) + /* SDC1: PG3-PG8 */ + for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN6I) + /* SDC1: PG0-PG5 */ + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN8I) + if (pins == SUNXI_GPIO_D) { + /* SDC1: PD2-PD7 */ + for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + } else { + /* SDC1: PG0-PG5 */ + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + } +#endif + break; + + case 2: + pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); + +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) + /* SDC2: PC6-PC11 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN5I) + if (pins == SUNXI_GPIO_E) { + /* SDC2: PE4-PE9 */ + for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + } else { + /* SDC2: PC6-PC15 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + } +#elif defined(CONFIG_MACH_SUN6I) + if (pins == SUNXI_GPIO_A) { + /* SDC2: PA9-PA14 */ + for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + } else { + /* SDC2: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); + } +#elif defined(CONFIG_MACH_SUN8I_R40) + /* SDC2: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); +#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) + /* SDC2: PC5-PC6, PC8-PC16 */ + for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN50I_H6) + /* SDC2: PC4-PC14 */ + for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN9I) + /* SDC2: PC6-PC16 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#endif + break; + + case 3: + pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); + +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + /* SDC3: PI4-PI9 */ + for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#elif defined(CONFIG_MACH_SUN6I) + if (pins == SUNXI_GPIO_A) { + /* SDC3: PA9-PA14 */ + for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + } else { + /* SDC3: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); + } +#endif + break; + + default: + printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); + break; + } +} + +int board_mmc_init(struct bd_info *bis) +{ + __maybe_unused struct mmc *mmc0, *mmc1; + + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); + mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); + if (!mmc0) + return -1; + +#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); + mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); + if (!mmc1) + return -1; +#endif + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD + +static void sunxi_spl_store_dram_size(phys_addr_t dram_size) +{ + struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION); + + if (spl == INVALID_SPL_HEADER) + return; + + /* Promote the header version for U-Boot proper, if needed. */ + if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION) + spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION; + + spl->dram_size = dram_size >> 20; +} + +void sunxi_board_init(void) +{ + int power_failed = 0; + +#ifdef CONFIG_SY8106A_POWER + power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); +#endif + +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ + defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \ + defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + power_failed = axp_init(); + +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER + power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); +#endif +#if !defined(CONFIG_AXP305_POWER) + power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); + power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); +#endif +#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) + power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); +#endif +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER + power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); +#endif + +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ + defined CONFIG_AXP818_POWER + power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); +#endif +#if !defined(CONFIG_AXP305_POWER) + power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); +#endif +#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER) + power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); +#endif +#ifdef CONFIG_AXP209_POWER + power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); +#endif + +#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ + defined(CONFIG_AXP818_POWER) + power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); + power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); +#if !defined CONFIG_AXP809_POWER + power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); + power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); +#endif + power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); + power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); + power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); +#endif + +#ifdef CONFIG_AXP818_POWER + power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); + power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); + power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); +#endif + +#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); +#endif +#endif + printf("DRAM:"); + gd->ram_size = sunxi_dram_init(); + printf(" %d MiB\n", (int)(gd->ram_size >> 20)); + if (!gd->ram_size) + hang(); + + sunxi_spl_store_dram_size(gd->ram_size); + + /* + * Only clock up the CPU to full speed if we are reasonably + * assured it's being powered with suitable core voltage + */ + if (!power_failed) + clock_set_pll1(CONFIG_SYS_CLK_FREQ); + else + printf("Failed to set core voltage! Can't set CPU frequency\n"); +} +#endif + +#ifdef CONFIG_USB_GADGET +int g_dnl_board_usb_cable_connected(void) +{ + struct udevice *dev; + struct phy phy; + int ret; + + ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev); + if (ret) { + pr_err("%s: Cannot find USB device\n", __func__); + return ret; + } + + ret = generic_phy_get_by_name(dev, "usb", &phy); + if (ret) { + pr_err("failed to get %s USB PHY\n", dev->name); + return ret; + } + + ret = generic_phy_init(&phy); + if (ret) { + pr_debug("failed to init %s USB PHY\n", dev->name); + return ret; + } + + ret = sun4i_usb_phy_vbus_detect(&phy); + if (ret == 1) { + pr_err("A charger is plugged into the OTG\n"); + return -ENODEV; + } + + return ret; +} +#endif + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial_string; + unsigned long long serial; + + serial_string = env_get("serial#"); + + if (serial_string) { + serial = simple_strtoull(serial_string, NULL, 16); + + serialnr->high = (unsigned int) (serial >> 32); + serialnr->low = (unsigned int) (serial & 0xffffffff); + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} +#endif + +/* + * Check the SPL header for the "sunxi" variant. If found: parse values + * that might have been passed by the loader ("fel" utility), and update + * the environment accordingly. + */ +static void parse_spl_header(const uint32_t spl_addr) +{ + struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION); + + if (spl == INVALID_SPL_HEADER) + return; + + if (!spl->fel_script_address) + return; + + if (spl->fel_uEnv_length != 0) { + /* + * data is expected in uEnv.txt compatible format, so "env + * import -t" the string(s) at fel_script_address right away. + */ + himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address, + spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); + return; + } + /* otherwise assume .scr format (mkimage-type script) */ + env_set_hex("fel_scriptaddr", spl->fel_script_address); +} + +static bool get_unique_sid(unsigned int *sid) +{ + if (sunxi_get_sid(sid) != 0) + return false; + + if (!sid[0]) + return false; + + /* + * The single words 1 - 3 of the SID have quite a few bits + * which are the same on many models, so we take a crc32 + * of all 3 words, to get a more unique value. + * + * Note we only do this on newer SoCs as we cannot change + * the algorithm on older SoCs since those have been using + * fixed mac-addresses based on only using word 3 for a + * long time and changing a fixed mac-address with an + * u-boot update is not good. + */ +#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ + !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ + !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) + sid[3] = crc32(0, (unsigned char *)&sid[1], 12); +#endif + + /* Ensure the NIC specific bytes of the mac are not all 0 */ + if ((sid[3] & 0xffffff) == 0) + sid[3] |= 0x800000; + + return true; +} + +/* + * Note this function gets called multiple times. + * It must not make any changes to env variables which already exist. + */ +static void setup_environment(const void *fdt) +{ + char serial_string[17] = { 0 }; + unsigned int sid[4]; + uint8_t mac_addr[6]; + char ethaddr[16]; + int i; + + if (!get_unique_sid(sid)) + return; + + for (i = 0; i < 4; i++) { + sprintf(ethaddr, "ethernet%d", i); + if (!fdt_get_alias(fdt, ethaddr)) + continue; + + if (i == 0) + strcpy(ethaddr, "ethaddr"); + else + sprintf(ethaddr, "eth%daddr", i); + + if (env_get(ethaddr)) + continue; + + /* Non OUI / registered MAC address */ + mac_addr[0] = (i << 4) | 0x02; + mac_addr[1] = (sid[0] >> 0) & 0xff; + mac_addr[2] = (sid[3] >> 24) & 0xff; + mac_addr[3] = (sid[3] >> 16) & 0xff; + mac_addr[4] = (sid[3] >> 8) & 0xff; + mac_addr[5] = (sid[3] >> 0) & 0xff; + + eth_env_set_enetaddr(ethaddr, mac_addr); + } + + if (!env_get("serial#")) { + snprintf(serial_string, sizeof(serial_string), + "%08x%08x", sid[0], sid[3]); + + env_set("serial#", serial_string); + } +} + +int misc_init_r(void) +{ + const char *spl_dt_name; + uint boot; + + env_set("fel_booted", NULL); + env_set("fel_scriptaddr", NULL); + env_set("mmc_bootdev", NULL); + + boot = sunxi_get_boot_device(); + /* determine if we are running in FEL mode */ + if (boot == BOOT_DEVICE_BOARD) { + env_set("fel_booted", "1"); + parse_spl_header(SPL_ADDR); + /* or if we booted from MMC, and which one */ + } else if (boot == BOOT_DEVICE_MMC1) { + env_set("mmc_bootdev", "0"); + } else if (boot == BOOT_DEVICE_MMC2) { + env_set("mmc_bootdev", "1"); + } + + /* Set fdtfile to match the FIT configuration chosen in SPL. */ + spl_dt_name = get_spl_dt_name(); + if (spl_dt_name) { + char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : ""; + char str[64]; + + snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name); + env_set("fdtfile", str); + } + + setup_environment(gd->fdt_blob); + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_USB_ETHER + usb_ether_init(); +#endif + + return 0; +} + +static void bluetooth_dt_fixup(void *blob) +{ + /* Some devices ship with a Bluetooth controller default address. + * Set a valid address through the device tree. + */ + uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN]; + unsigned int sid[4]; + int i; + + if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0]) + return; + + if (eth_env_get_enetaddr("bdaddr", tmp)) { + /* Convert between the binary formats of the corresponding stacks */ + for (i = 0; i < ETH_ALEN; ++i) + bdaddr[i] = tmp[ETH_ALEN - i - 1]; + } else { + if (!get_unique_sid(sid)) + return; + + bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1; + bdaddr[1] = (sid[3] >> 8) & 0xff; + bdaddr[2] = (sid[3] >> 16) & 0xff; + bdaddr[3] = (sid[3] >> 24) & 0xff; + bdaddr[4] = (sid[0] >> 0) & 0xff; + bdaddr[5] = 0x02; + } + + do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP, + "local-bd-address", bdaddr, ETH_ALEN, 1); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int __maybe_unused r; + + /* + * Call setup_environment again in case the boot fdt has + * ethernet aliases the u-boot copy does not have. + */ + setup_environment(blob); + + bluetooth_dt_fixup(blob); + +#ifdef CONFIG_VIDEO_DT_SIMPLEFB + r = sunxi_simplefb_setup(blob); + if (r) + return r; +#endif + return 0; +} + +#ifdef CONFIG_SPL_LOAD_FIT + +static void set_spl_dt_name(const char *name) +{ + struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION); + + if (spl == INVALID_SPL_HEADER) + return; + + /* Promote the header version for U-Boot proper, if needed. */ + if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION) + spl->spl_signature[3] = SPL_DT_HEADER_VERSION; + + strcpy((char *)&spl->string_pool, name); + spl->dt_name_offset = offsetof(struct boot_file_head, string_pool); +} + +int board_fit_config_name_match(const char *name) +{ + const char *best_dt_name = get_spl_dt_name(); + int ret; + +#ifdef CONFIG_DEFAULT_DEVICE_TREE + if (best_dt_name == NULL) + best_dt_name = CONFIG_DEFAULT_DEVICE_TREE; +#endif + + if (best_dt_name == NULL) { + /* No DT name was provided, so accept the first config. */ + return 0; + } +#ifdef CONFIG_PINE64_DT_SELECTION + if (strstr(best_dt_name, "-pine64-plus")) { + /* Differentiate the Pine A64 boards by their DRAM size. */ + if ((gd->ram_size == 512 * 1024 * 1024)) + best_dt_name = "sun50i-a64-pine64"; + } +#endif +#ifdef CONFIG_PINEPHONE_DT_SELECTION + if (strstr(best_dt_name, "-pinephone")) { + /* Differentiate the PinePhone revisions by GPIO inputs. */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO); + sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT); + udelay(100); + + /* PL6 is pulled low by the modem on v1.2. */ + if (gpio_get_value(SUNXI_GPL(6)) == 0) + best_dt_name = "sun50i-a64-pinephone-1.2"; + else + best_dt_name = "sun50i-a64-pinephone-1.1"; + + sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE); + sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE); + prcm_apb0_disable(PRCM_APB0_GATE_PIO); + } +#endif + + ret = strcmp(name, best_dt_name); + + /* + * If one of the FIT configurations matches the most accurate DT name, + * update the SPL header to provide that DT name to U-Boot proper. + */ + if (ret == 0) + set_spl_dt_name(best_dt_name); + + return ret; +} +#endif diff --git a/roms/u-boot/board/sunxi/chip.c b/roms/u-boot/board/sunxi/chip.c new file mode 100644 index 000000000..cde04bebe --- /dev/null +++ b/roms/u-boot/board/sunxi/chip.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 + * Köry Maincent, Bootlin, <kory.maincent@bootlin.com> + * Based on initial code from Maxime Ripard + */ + +#include <common.h> +#include <malloc.h> +#include <dm.h> +#include <w1.h> +#include <w1-eeprom.h> +#include <dm/device-internal.h> + +#include <asm/arch/gpio.h> + +#include <extension_board.h> + +#define for_each_w1_device(b, d) \ + for (device_find_first_child(b, d); *d; device_find_next_child(d)) + +#define dip_convert(field) \ + ( \ + (sizeof(field) == 1) ? field : \ + (sizeof(field) == 2) ? be16_to_cpu(field) : \ + (sizeof(field) == 4) ? be32_to_cpu(field) : \ + -1 \ + ) + +#define DIP_MAGIC 0x50494843 /* CHIP */ + +struct dip_w1_header { + u32 magic; /* CHIP */ + u8 version; /* spec version */ + u32 vendor_id; + u16 product_id; + u8 product_version; + char vendor_name[32]; + char product_name[32]; + u8 rsvd[36]; /* rsvd for future spec versions */ + u8 data[16]; /* user data, per-dip specific */ +} __packed; + +int extension_board_scan(struct list_head *extension_list) +{ + struct extension *dip; + struct dip_w1_header w1_header; + struct udevice *bus, *dev; + u32 vid; + u16 pid; + int ret; + + int num_dip = 0; + + sunxi_gpio_set_pull(SUNXI_GPD(2), SUNXI_GPIO_PULL_UP); + + ret = w1_get_bus(0, &bus); + if (ret) { + printf("one wire interface not found\n"); + return 0; + } + + for_each_w1_device(bus, &dev) { + if (w1_get_device_family(dev) != W1_FAMILY_DS2431) + continue; + + ret = device_probe(dev); + if (ret) { + printf("Couldn't probe device %s: error %d", + dev->name, ret); + continue; + } + + w1_eeprom_read_buf(dev, 0, (u8 *)&w1_header, sizeof(w1_header)); + + if (w1_header.magic != DIP_MAGIC) + continue; + + vid = dip_convert(w1_header.vendor_id); + pid = dip_convert(w1_header.product_id); + + printf("DIP: %s (0x%x) from %s (0x%x)\n", + w1_header.product_name, pid, + w1_header.vendor_name, vid); + + dip = calloc(1, sizeof(struct extension)); + if (!dip) { + printf("Error in memory allocation\n"); + return num_dip; + } + + snprintf(dip->overlay, sizeof(dip->overlay), "dip-%x-%x.dtbo", + vid, pid); + strncpy(dip->name, w1_header.product_name, 32); + strncpy(dip->owner, w1_header.vendor_name, 32); + list_add_tail(&dip->list, extension_list); + num_dip++; + } + return num_dip; +} diff --git a/roms/u-boot/board/sunxi/dram_sun4i_auto.c b/roms/u-boot/board/sunxi/dram_sun4i_auto.c new file mode 100644 index 000000000..e8bbee4ee --- /dev/null +++ b/roms/u-boot/board/sunxi/dram_sun4i_auto.c @@ -0,0 +1,36 @@ +#include <common.h> +#include <init.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = CONFIG_DRAM_CLK, + .type = 3, + .rank_num = 1, + .density = 0, + .io_width = 0, + .bus_width = 0, + .zq = CONFIG_DRAM_ZQ, + .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), + .size = 0, +#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC + .cas = 6, + .tpr0 = 0x30926692, + .tpr1 = 0x1090, + .tpr2 = 0x1a0c8, + .emr2 = 0, +#else +# include "dram_timings_sun4i.h" + .active_windowing = 1, +#endif + .tpr3 = CONFIG_DRAM_TPR3, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = CONFIG_DRAM_EMR1, + .emr3 = 0, + .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/roms/u-boot/board/sunxi/dram_sun5i_auto.c b/roms/u-boot/board/sunxi/dram_sun5i_auto.c new file mode 100644 index 000000000..a5f4f8b74 --- /dev/null +++ b/roms/u-boot/board/sunxi/dram_sun5i_auto.c @@ -0,0 +1,39 @@ +/* DRAM parameters for auto dram configuration on sun5i and sun7i */ + +#include <common.h> +#include <init.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = CONFIG_DRAM_CLK, + .mbus_clock = CONFIG_DRAM_MBUS_CLK, + .type = 3, + .rank_num = 1, + .density = 0, + .io_width = 0, + .bus_width = 0, + .zq = CONFIG_DRAM_ZQ, + .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), + .size = 0, +#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC + .cas = 9, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .emr2 = 0x10, +#else +# include "dram_timings_sun4i.h" + .active_windowing = 1, +#endif + .tpr3 = CONFIG_DRAM_TPR3, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = CONFIG_DRAM_EMR1, + .emr3 = 0, + .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/roms/u-boot/board/sunxi/dram_timings_sun4i.h b/roms/u-boot/board/sunxi/dram_timings_sun4i.h new file mode 100644 index 000000000..29b934da6 --- /dev/null +++ b/roms/u-boot/board/sunxi/dram_timings_sun4i.h @@ -0,0 +1,205 @@ +/* This file is automatically generated, do not edit */ + +#if defined(CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H) +# if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */ + .cas = 6, + .tpr0 = 0x268e5590, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x288f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x2a8f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */ + .cas = 7, + .tpr0 = 0x2ab06690, + .tpr1 = 0xa0a8, + .tpr2 = 0x22a00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */ + .cas = 7, + .tpr0 = 0x2cb16690, + .tpr1 = 0xa0b0, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */ + .cas = 7, + .tpr0 = 0x30b26690, + .tpr1 = 0xa0b8, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */ + .cas = 7, + .tpr0 = 0x30b27790, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */ + .cas = 7, + .tpr0 = 0x32b27790, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */ + .cas = 7, + .tpr0 = 0x34d37790, + .tpr1 = 0xa0d0, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */ + .cas = 7, + .tpr0 = 0x36d47790, + .tpr1 = 0xa0d8, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333H @540MHz, timings: 9-8-8-20 */ + .cas = 9, + .tpr0 = 0x36b488b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2b600, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333H @552MHz, timings: 9-8-8-20 */ + .cas = 9, + .tpr0 = 0x38b488b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333H @576MHz, timings: 9-8-8-21 */ + .cas = 9, + .tpr0 = 0x3ab588b4, + .tpr1 = 0xa0d0, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333H @600MHz, timings: 9-9-9-22 */ + .cas = 9, + .tpr0 = 0x3cb699b4, + .tpr1 = 0xa0d8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333H @624MHz, timings: 9-9-9-23 */ + .cas = 9, + .tpr0 = 0x3eb799b4, + .tpr1 = 0xa0e8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333H @648MHz, timings: 9-9-9-24 */ + .cas = 9, + .tpr0 = 0x42b899b4, + .tpr1 = 0xa0f0, + .tpr2 = 0x2c200, + .emr2 = 0x10, +# else +# error CONFIG_DRAM_CLK is set too high +# endif +#elif defined(CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J) +# if CONFIG_DRAM_CLK <= 360 /* DDR3-800E @360MHz, timings: 6-6-6-14 */ + .cas = 6, + .tpr0 = 0x268e6690, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 384 /* DDR3-800E @384MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x2a8f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 396 /* DDR3-800E @396MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x2a8f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066G @408MHz, timings: 8-7-7-16 */ + .cas = 8, + .tpr0 = 0x2cb07790, + .tpr1 = 0xa0a8, + .tpr2 = 0x22a00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066G @432MHz, timings: 8-7-7-17 */ + .cas = 8, + .tpr0 = 0x2eb17790, + .tpr1 = 0xa0b0, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066G @456MHz, timings: 8-7-7-18 */ + .cas = 8, + .tpr0 = 0x30b27790, + .tpr1 = 0xa0b8, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066G @468MHz, timings: 8-8-8-18 */ + .cas = 8, + .tpr0 = 0x32b28890, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066G @480MHz, timings: 8-8-8-18 */ + .cas = 8, + .tpr0 = 0x34b28890, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066G @504MHz, timings: 8-8-8-19 */ + .cas = 8, + .tpr0 = 0x36d38890, + .tpr1 = 0xa0d0, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066G @528MHz, timings: 8-8-8-20 */ + .cas = 8, + .tpr0 = 0x38d48890, + .tpr1 = 0xa0d8, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333J @540MHz, timings: 10-9-9-20 */ + .cas = 10, + .tpr0 = 0x38b499b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2b600, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333J @552MHz, timings: 10-9-9-20 */ + .cas = 10, + .tpr0 = 0x3ab499b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333J @576MHz, timings: 10-9-9-21 */ + .cas = 10, + .tpr0 = 0x3cb599b4, + .tpr1 = 0xa0d0, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333J @600MHz, timings: 10-9-9-22 */ + .cas = 10, + .tpr0 = 0x3eb699b4, + .tpr1 = 0xa0d8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333J @624MHz, timings: 10-10-10-23 */ + .cas = 10, + .tpr0 = 0x40b7aab4, + .tpr1 = 0xa0e8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333J @648MHz, timings: 10-10-10-24 */ + .cas = 10, + .tpr0 = 0x44b8aab4, + .tpr1 = 0xa0f0, + .tpr2 = 0x2c200, + .emr2 = 0x10, +# else +# error CONFIG_DRAM_CLK is set too high +# endif +#else +# error CONFIG_DRAM_TIMINGS_* is not defined +#endif diff --git a/roms/u-boot/board/sunxi/gmac.c b/roms/u-boot/board/sunxi/gmac.c new file mode 100644 index 000000000..d8fdf7728 --- /dev/null +++ b/roms/u-boot/board/sunxi/gmac.c @@ -0,0 +1,78 @@ +#include <common.h> +#include <netdev.h> +#include <miiphy.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> + +void eth_init_board(void) +{ + int pin; + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Set MII clock */ +#ifdef CONFIG_RGMII + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | + CCM_GMAC_CTRL_GPIT_RGMII); + setbits_le32(&ccm->gmac_clk_cfg, + CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); +#else + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | + CCM_GMAC_CTRL_GPIT_MII); +#endif + +#ifndef CONFIG_MACH_SUN6I + /* Configure pin mux settings for GMAC */ +#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) { +#else + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { +#endif +#ifdef CONFIG_RGMII + /* skip unused pins in RGMII mode */ + if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) + continue; +#endif + sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC); + sunxi_gpio_set_drv(pin, 3); + } +#elif defined CONFIG_RGMII + /* Configure sun6i RGMII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); + sunxi_gpio_set_drv(pin, 3); + } +#elif defined CONFIG_GMII + /* Configure sun6i GMII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); + sunxi_gpio_set_drv(pin, 2); + } +#else + /* Configure sun6i MII mode pin mux settings */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); + for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); + for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); + for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); + for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++) + sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); +#endif +} |