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-rw-r--r--roms/u-boot/board/tbs/tbs2910/Kconfig15
-rw-r--r--roms/u-boot/board/tbs/tbs2910/MAINTAINERS8
-rw-r--r--roms/u-boot/board/tbs/tbs2910/Makefile5
-rw-r--r--roms/u-boot/board/tbs/tbs2910/tbs2910.c182
-rw-r--r--roms/u-boot/board/tbs/tbs2910/tbs2910.cfg114
5 files changed, 324 insertions, 0 deletions
diff --git a/roms/u-boot/board/tbs/tbs2910/Kconfig b/roms/u-boot/board/tbs/tbs2910/Kconfig
new file mode 100644
index 000000000..d0ff2191a
--- /dev/null
+++ b/roms/u-boot/board/tbs/tbs2910/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TBS2910
+
+config SYS_BOARD
+ default "tbs2910"
+
+config SYS_VENDOR
+ default "tbs"
+
+config SYS_CONFIG_NAME
+ default "tbs2910"
+
+config IMX_CONFIG
+ default "board/tbs/tbs2910/tbs2910.cfg"
+
+endif
diff --git a/roms/u-boot/board/tbs/tbs2910/MAINTAINERS b/roms/u-boot/board/tbs/tbs2910/MAINTAINERS
new file mode 100644
index 000000000..1e3c0d0ec
--- /dev/null
+++ b/roms/u-boot/board/tbs/tbs2910/MAINTAINERS
@@ -0,0 +1,8 @@
+TBS2910 BOARD
+M: Soeren Moch <smoch@web.de>
+S: Maintained
+F: arch/arm/dts/imx6q-tbs2910.dts
+F: board/tbs/tbs2910/
+F: configs/tbs2910_defconfig
+F: doc/board/tbs/
+F: include/configs/tbs2910.h
diff --git a/roms/u-boot/board/tbs/tbs2910/Makefile b/roms/u-boot/board/tbs/tbs2910/Makefile
new file mode 100644
index 000000000..78f4a3eec
--- /dev/null
+++ b/roms/u-boot/board/tbs/tbs2910/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2014 Soeren Moch <smoch@web.de>
+
+obj-y := tbs2910.o
diff --git a/roms/u-boot/board/tbs/tbs2910/tbs2910.c b/roms/u-boot/board/tbs/tbs2910/tbs2910.c
new file mode 100644
index 000000000..faf73cc21
--- /dev/null
+++ b/roms/u-boot/board/tbs/tbs2910/tbs2910.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Soeren Moch <smoch@web.de>
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/global_data.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int dram_init(void)
+{
+ gd->ram_size = 2048ul * 1024 * 1024;
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+/* set environment device to boot device when booting from SD */
+int board_mmc_get_env_dev(int devno)
+{
+ return devno - 1;
+}
+
+int board_mmc_get_env_part(int devno)
+{
+ return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
+}
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+#ifdef CONFIG_VIDEO_IPUV3
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ /* 1024x768@60Hz (VESA)*/
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15384,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+ s32 timeout = 100000;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
+ reg = readl(&ccm->analog_pll_video);
+ reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
+ writel(reg, &ccm->analog_pll_video);
+
+ reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
+ reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
+ writel(reg, &ccm->analog_pll_video);
+
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+ reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
+ writel(reg, &ccm->analog_pll_video);
+
+ while (timeout--)
+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+ break;
+ if (timeout < 0)
+ printf("Warning: video pll lock timeout!\n");
+
+ reg = readl(&ccm->analog_pll_video);
+ reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
+ reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
+ writel(reg, &ccm->analog_pll_video);
+
+ /* gate ipu1_di0_clk */
+ reg = readl(&ccm->CCGR3);
+ reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &ccm->CCGR3);
+
+ /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
+ reg = readl(&ccm->chsccdr);
+ reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
+ MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+ reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
+ (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
+ (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &ccm->chsccdr);
+
+ /* enable ipu1_di0_clk */
+ reg = readl(&ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &ccm->CCGR3);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ /* 8 bit bus width */
+ {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_VIDEO_IPUV3
+ setup_display();
+#endif
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
diff --git a/roms/u-boot/board/tbs/tbs2910/tbs2910.cfg b/roms/u-boot/board/tbs/tbs2910/tbs2910.cfg
new file mode 100644
index 000000000..3ca807b31
--- /dev/null
+++ b/roms/u-boot/board/tbs/tbs2910/tbs2910.cfg
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Soeren Moch <smoch@web.de>
+ */
+
+#define __ASSEMBLY__
+#include "asm/arch/crm_regs.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/mx6-ddr.h"
+
+/* image version 2 for imx6 */
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+/* set the default clock gates to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */
+DATA 4, CCM_CCOSR, 0x000000fb
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x77177717
+DATA 4, MX6_IOMUXC_GPR7, 0x77177717
+
+
+/*
+ * DDR3/DDR3L settings
+ * use default 40 Ohm pad drive strength, no odt
+ * 4x256Mx16 DDR3L-1066 7-7-7
+ */
+
+/* disable dq pullup */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* disable dqs pullup */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+/* set ddr input mode for dq signals */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* set ddr input mode for dqs signals */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* set pad calibration type to DDR3 */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+/* dqs write delay */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f
+/* dqs read delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+/* dqs read gating control */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300
+/* start delay line calibration */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
+/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
+/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */
+DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
+/* ODT timing */
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+/* read odt settings, 120 Ohm */
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
+/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
+/* interleaved bank access (row/bank/col), 5 cycles additional read delay */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+/* 2GiByte RAM at cs0 */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+/* load mode registers of external ddr chips */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+/* externel chip ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+/* configure and start refreshes, 8 refresh commands at 32 kHz */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+/* set automatic self refresh */
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+/* controller configuration finished */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000