diff options
Diffstat (limited to 'roms/u-boot/cmd/x86')
| -rw-r--r-- | roms/u-boot/cmd/x86/Makefile | 7 | ||||
| -rw-r--r-- | roms/u-boot/cmd/x86/cbsysinfo.c | 394 | ||||
| -rw-r--r-- | roms/u-boot/cmd/x86/exception.c | 29 | ||||
| -rw-r--r-- | roms/u-boot/cmd/x86/fsp.c | 110 | ||||
| -rw-r--r-- | roms/u-boot/cmd/x86/hob.c | 165 | ||||
| -rw-r--r-- | roms/u-boot/cmd/x86/mtrr.c | 191 |
6 files changed, 896 insertions, 0 deletions
diff --git a/roms/u-boot/cmd/x86/Makefile b/roms/u-boot/cmd/x86/Makefile new file mode 100644 index 000000000..5f82204c8 --- /dev/null +++ b/roms/u-boot/cmd/x86/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_CMD_CBSYSINFO) += cbsysinfo.o +obj-y += mtrr.o +obj-$(CONFIG_CMD_EXCEPTION) += exception.o +obj-$(CONFIG_USE_HOB) += hob.o +obj-$(CONFIG_HAVE_FSP) += fsp.o diff --git a/roms/u-boot/cmd/x86/cbsysinfo.c b/roms/u-boot/cmd/x86/cbsysinfo.c new file mode 100644 index 000000000..34fdaf5b1 --- /dev/null +++ b/roms/u-boot/cmd/x86/cbsysinfo.c @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <asm/cb_sysinfo.h> +#include <command.h> +#include <console.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void cbprompt(const char *name) +{ + for (; *name == '>'; name++) + puts(" "); + printf("%-12s: ", name); +} + +static void print_dec(const char *name, int value) +{ + cbprompt(name); + printf(value > 9 ? "0d%d\n" : "%d\n", value); +} + +static void print_hex(const char *name, int value) +{ + cbprompt(name); + printf("%x\n", value); +} + +static void print_addr(const char *name, ulong value) +{ + cbprompt(name); + printf("%08lx\n", value); +} + +static void print_addr64(const char *name, u64 value) +{ + cbprompt(name); + printf("%16llx\n", value); +} + +static void print_ptr(const char *name, const void *value) +{ + cbprompt(name); + printf("%p\n", value); +} + +static void print_str(const char *name, const char *value) +{ + if (value) { + cbprompt(name); + printf("%s\n", value); + } +} + +static void print_idx(const char *name, uint idx, const u8 *strings) +{ + const char *ptr; + + cbprompt(name); + ptr = (char *)strings + idx; + printf("%d: %s\n", idx, ptr ? ptr : "(unknown)"); +} + +static const char *const cb_mem_name[] = { + NULL, + "ram", + "reserved", + "acpi", + "nvs", + "unusable", + "vendor", +}; + +static const char *get_mem_name(int tag) +{ + if (tag >= CB_MEM_RAM && tag <= CB_MEM_VENDOR_RSVD) + return cb_mem_name[tag]; + + if (tag == CB_MEM_TABLE) + return "table"; + + return "(unknown)"; +} + +static const struct timestamp_id_to_name { + uint id; + const char *name; +} timestamp_ids[] = { + /* Marker to report base_time */ + { 0, "1st timestamp" }, + { TS_START_ROMSTAGE, "start of romstage" }, + { TS_BEFORE_INITRAM, "before ram initialization" }, + { TS_AFTER_INITRAM, "after ram initialization" }, + { TS_END_ROMSTAGE, "end of romstage" }, + { TS_START_VBOOT, "start of verified boot" }, + { TS_END_VBOOT, "end of verified boot" }, + { TS_START_COPYRAM, "starting to load ramstage" }, + { TS_END_COPYRAM, "finished loading ramstage" }, + { TS_START_RAMSTAGE, "start of ramstage" }, + { TS_START_BOOTBLOCK, "start of bootblock" }, + { TS_END_BOOTBLOCK, "end of bootblock" }, + { TS_START_COPYROM, "starting to load romstage" }, + { TS_END_COPYROM, "finished loading romstage" }, + { TS_START_ULZMA, "starting LZMA decompress (ignore for x86)" }, + { TS_END_ULZMA, "finished LZMA decompress (ignore for x86)" }, + { TS_START_ULZ4F, "starting LZ4 decompress (ignore for x86)" }, + { TS_END_ULZ4F, "finished LZ4 decompress (ignore for x86)" }, + { TS_DEVICE_ENUMERATE, "device enumeration" }, + { TS_DEVICE_CONFIGURE, "device configuration" }, + { TS_DEVICE_ENABLE, "device enable" }, + { TS_DEVICE_INITIALIZE, "device initialization" }, + { TS_DEVICE_DONE, "device setup done" }, + { TS_CBMEM_POST, "cbmem post" }, + { TS_WRITE_TABLES, "write tables" }, + { TS_FINALIZE_CHIPS, "finalize chips" }, + { TS_LOAD_PAYLOAD, "load payload" }, + { TS_ACPI_WAKE_JUMP, "ACPI wake jump" }, + { TS_SELFBOOT_JUMP, "selfboot jump" }, + + { TS_START_COPYVER, "starting to load verstage" }, + { TS_END_COPYVER, "finished loading verstage" }, + { TS_START_TPMINIT, "starting to initialize TPM" }, + { TS_END_TPMINIT, "finished TPM initialization" }, + { TS_START_VERIFY_SLOT, "starting to verify keyblock/preamble (RSA)" }, + { TS_END_VERIFY_SLOT, "finished verifying keyblock/preamble (RSA)" }, + { TS_START_HASH_BODY, "starting to verify body (load+SHA2+RSA) " }, + { TS_DONE_LOADING, "finished loading body (ignore for x86)" }, + { TS_DONE_HASHING, "finished calculating body hash (SHA2)" }, + { TS_END_HASH_BODY, "finished verifying body signature (RSA)" }, + + { TS_START_COPYVPD, "starting to load Chrome OS VPD" }, + { TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" }, + { TS_END_COPYVPD_RW, "finished loading Chrome OS VPD (RW)" }, + + { TS_U_BOOT_INITTED, "U-Boot start" }, + { TS_RO_PARAMS_INIT, "RO parameter init" }, + { TS_RO_VB_INIT, "RO vboot init" }, + { TS_RO_VB_SELECT_FIRMWARE, "RO vboot select firmware" }, + { TS_RO_VB_SELECT_AND_LOAD_KERNEL, "RO vboot select&load kernel" }, + { TS_RW_VB_SELECT_AND_LOAD_KERNEL, "RW vboot select&load kernel" }, + { TS_VB_SELECT_AND_LOAD_KERNEL, "vboot select&load kernel" }, + { TS_VB_EC_VBOOT_DONE, "finished EC verification" }, + { TS_VB_STORAGE_INIT_DONE, "finished storage device initialization" }, + { TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" }, + { TS_VB_VBOOT_DONE, "finished vboot kernel verification" }, + { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, + { TS_START_KERNEL, "jumping to kernel" }, + { TS_U_BOOT_START_KERNEL, "just before jump to kernel" }, + + /* Intel ME-related timestamps */ + { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgment of raminit"}, + { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"}, + + /* FSP-related timestamps */ + { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" }, + { TS_FSP_MEMORY_INIT_END, "returning from FspMemoryInit" }, + { TS_FSP_TEMP_RAM_EXIT_START, "calling FspTempRamExit" }, + { TS_FSP_TEMP_RAM_EXIT_END, "returning from FspTempRamExit" }, + { TS_FSP_SILICON_INIT_START, "calling FspSiliconInit" }, + { TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit" }, + { TS_FSP_BEFORE_ENUMERATE, "calling FspNotify(AfterPciEnumeration)" }, + { TS_FSP_AFTER_ENUMERATE, + "returning from FspNotify(AfterPciEnumeration)" }, + { TS_FSP_BEFORE_FINALIZE, "calling FspNotify(ReadyToBoot)" }, + { TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" }, + { TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" }, + { TS_FSP_AFTER_END_OF_FIRMWARE, + "returning from FspNotify(EndOfFirmware)" }, +}; + +static const char *timestamp_name(uint32_t id) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { + if (timestamp_ids[i].id == id) + return timestamp_ids[i].name; + } + + return "<unknown>"; +} + +static void show_table(struct sysinfo_t *info, bool verbose) +{ + struct cb_serial *ser = info->serial; + int i; + + printf("Coreboot table at %lx, decoded to %p", + gd->arch.coreboot_table, info); + if (info->header) + printf(", forwarded to %p\n", info->header); + printf("\n"); + + print_dec("CPU KHz", info->cpu_khz); + + print_addr("Serial I/O port", info->ser_ioport); + print_addr(">base", info->ser_base); + print_ptr(">pointer", ser); + if (ser) { + print_hex(">type", ser->type); + print_addr(">base", ser->baseaddr); + print_dec(">baud", ser->baud); + print_hex(">regwidth", ser->regwidth); + print_dec(">input_hz", ser->input_hertz); + print_addr(">PCI addr", ser->uart_pci_addr); + } + + print_dec("Mem ranges", info->n_memranges); + printf("%12s: %-11s || base || size\n", "id", "type"); + for (i = 0; i < info->n_memranges; i++) { + const struct memrange *mr = &info->memrange[i]; + + printf("%12d: %02x:%-8s %016llx %016llx\n", i, mr->type, + get_mem_name(mr->type), mr->base, mr->size); + } + print_ptr("option_table", info->option_table); + + print_hex("CMOS start", info->cmos_range_start); + if (info->cmos_range_start) { + print_hex(">CMOS end", info->cmos_range_end); + print_hex(">CMOS csum loc", info->cmos_checksum_location); + } + + print_hex("VBNV start", info->vbnv_start); + print_hex("VBNV size", info->vbnv_size); + + print_str("CB version", info->cb_version); + print_str(">Extra", info->extra_version); + print_str(">Build", info->build); + print_str(">Time", info->compile_time); + print_str(">By", info->compile_by); + print_str(">Host", info->compile_host); + print_str(">Domain", info->compile_domain); + print_str(">Compiler", info->compiler); + print_str(">Linker", info->linker); + print_str(">Assembler", info->assembler); + + print_ptr("Framebuffer", info->framebuffer); + if (info->framebuffer) { + struct cb_framebuffer *fb = info->framebuffer; + + print_addr64(">Phys addr", fb->physical_address); + print_dec(">X res", fb->x_resolution); + print_dec(">X res", fb->y_resolution); + print_hex(">Bytes / line", fb->bytes_per_line); + print_dec(">Bpp", fb->bits_per_pixel); + printf(" %-12s red %d/%d, green %d/%d, blue %d/%d, reserved %d/%d\n", + "pos/size", fb->red_mask_pos, fb->red_mask_size, + fb->green_mask_pos, fb->green_mask_size, + fb->blue_mask_pos, fb->blue_mask_size, + fb->reserved_mask_pos, fb->reserved_mask_size); + } + + print_dec("GPIOs", info->num_gpios); + printf("%12s: %4s %12s %3s %s\n", "id", "port", "polarity", "val", + "name"); + for (i = 0; i < info->num_gpios; i++) { + const struct cb_gpio *gpio = &info->gpios[i]; + char portstr[4]; + + if (gpio->port == 0xffffffff) + strcpy(portstr, "-"); + else + sprintf(portstr, "%x", gpio->port); + printf("%12d: %4s %12s %3d %s\n", i, portstr, + gpio->polarity == CB_GPIO_ACTIVE_LOW ? "active-low" : + "active-high", gpio->value, gpio->name); + } + print_dec("MACs", info->num_macs); + for (i = 0; i < info->num_macs; i++) { + const struct mac_address *mac = &info->macs[i]; + int j; + + printf("%12d: ", i); + for (j = 0; j < sizeof(mac->mac_addr); j++) + printf("%s%02x", j ? ":" : "", mac->mac_addr[j]); + printf("\n"); + } + print_str(">Serial #", info->serialno); + print_ptr("Multiboot tab", info->mbtable); + print_ptr("CB header", info->header); + print_ptr("CB mainboard", info->mainboard); + if (info->mainboard) { + struct cb_mainboard *mb = info->mainboard; + + print_idx(">vendor", mb->vendor_idx, mb->strings); + print_idx(">part_number", mb->part_number_idx, mb->strings); + } + print_ptr("vboot handoff", info->vboot_handoff); + print_hex(">size", info->vboot_handoff_size); + print_ptr(">vdat addr", info->vdat_addr); + print_hex(">size", info->vdat_size); + + print_addr64("SMBIOS", info->smbios_start); + print_hex(">size", info->smbios_size); + print_hex("ROM MTRR", info->x86_rom_var_mtrr_index); + + print_ptr("Tstamp table", info->tstamp_table); + if (verbose && info->tstamp_table) { + struct timestamp_table *ts = info->tstamp_table; + + printf("%-12s", "Base_time"); + print_grouped_ull(ts->base_time, 12); + printf("\n"); + print_dec("Tick MHz", ts->tick_freq_mhz); + for (i = 0; i < ts->num_entries; i++) { + const struct timestamp_entry *tse; + + tse = &ts->entries[i]; + printf(" "); + print_grouped_ull(tse->entry_stamp, 12); + printf(" %s\n", timestamp_name(tse->entry_id)); + } + } + + print_ptr("CBmem cons", info->cbmem_cons); + if (info->cbmem_cons) { + struct cbmem_console *cons = info->cbmem_cons; + int i; + + print_hex("Size", cons->size); + print_hex("Cursor", cons->cursor); + if (verbose) { + for (i = 0; i < cons->cursor; i++) { + int ch = cons->body[i]; + + putc(ch); + + if (ch == '\n') { + /* check for ctrl-c to abort... */ + if (ctrlc()) { + puts("Abort\n"); + return; + } + printf(" "); + } + } + printf("\n"); + } + } + + print_ptr("MRC cache", info->mrc_cache); + print_ptr("ACPI GNVS", info->acpi_gnvs); + print_hex("Board ID", info->board_id); + print_hex("RAM code", info->ram_code); + print_ptr("WiFi calib", info->wifi_calibration); + print_addr64("Ramoops buff", info->ramoops_buffer); + print_hex(">size", info->ramoops_buffer_size); + print_hex("SF size", info->spi_flash.size); + print_hex("SF sector", info->spi_flash.sector_size); + print_hex("SF erase cmd", info->spi_flash.erase_cmd); + + print_addr64("FMAP offset", info->fmap_offset); + print_addr64("CBFS offset", info->cbfs_offset); + print_addr64("CBFS size", info->cbfs_size); + print_addr64("Boot media size", info->boot_media_size); + print_addr64("MTC start", info->mtc_start); + print_hex("MTC size", info->mtc_size); + + print_ptr("Chrome OS VPD", info->chromeos_vpd); +} + +static int do_cbsysinfo(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + bool verbose = false; + + if (argc > 1) { + if (!strcmp("-v", argv[1])) + verbose = true; + else + return CMD_RET_USAGE; + } + + if (!gd->arch.coreboot_table) { + printf("No coreboot sysinfo table found\n"); + return CMD_RET_FAILURE; + } + show_table(&lib_sysinfo, verbose); + + return 0; +} + +U_BOOT_CMD( + cbsysinfo, 2, 1, do_cbsysinfo, + "Show coreboot sysinfo table", + "[-v] Dumps out the contents of the sysinfo table. This only\n" + "works if U-Boot is booted from coreboot" +); diff --git a/roms/u-boot/cmd/x86/exception.c b/roms/u-boot/cmd/x86/exception.c new file mode 100644 index 000000000..82faaa913 --- /dev/null +++ b/roms/u-boot/cmd/x86/exception.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * The 'exception' command can be used for testing exception handling. + * + * Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de> + */ + +#include <common.h> +#include <command.h> + +static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + asm volatile (".word 0xffff\n"); + return CMD_RET_FAILURE; +} + +static struct cmd_tbl cmd_sub[] = { + U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined, + "", ""), +}; + +static char exception_help_text[] = + "<ex>\n" + " The following exceptions are available:\n" + " undefined - undefined instruction\n" + ; + +#include <exception.h> diff --git a/roms/u-boot/cmd/x86/fsp.c b/roms/u-boot/cmd/x86/fsp.c new file mode 100644 index 000000000..82e4415b1 --- /dev/null +++ b/roms/u-boot/cmd/x86/fsp.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014-2015, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <command.h> +#include <asm/fsp/fsp_support.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int do_hdr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct fsp_header *hdr; + u32 img_addr; + char *sign; + uint addr; + int i; + +#ifdef CONFIG_FSP_VERSION2 + /* + * Only FSP-S is displayed. FSP-M was used in SPL but may not still be + * around, and we didn't keep a pointer to it. + */ + hdr = gd->arch.fsp_s_hdr; + img_addr = hdr->img_base; + addr = img_addr; +#else + addr = CONFIG_FSP_ADDR; + hdr = fsp_find_header(); + img_addr = hdr->img_base; +#endif + sign = (char *)&hdr->sign; + + printf("FSP : binary %08x, header %08x\n", addr, (int)hdr); + printf("Header : sign "); + for (i = 0; i < sizeof(hdr->sign); i++) + printf("%c", *sign++); + printf(", size %x, rev %d\n", hdr->hdr_len, hdr->hdr_rev); + printf("Image : rev "); + if (hdr->hdr_rev == FSP_HEADER_REVISION_1) { + printf("%d.%d", + (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff); + } else { + printf("%d.%d.%d.%d", + (hdr->img_rev >> 24) & 0xff, (hdr->img_rev >> 16) & 0xff, + (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff); + } + printf(", id "); + for (i = 0; i < ARRAY_SIZE(hdr->img_id); i++) + printf("%c", hdr->img_id[i]); + printf(", addr %08x, size %x\n", img_addr, hdr->img_size); + if (hdr->hdr_rev >= FSP_HEADER_REVISION_1) { + printf("GFX :%ssupported\n", + hdr->img_attr & FSP_ATTR_GRAPHICS_SUPPORT ? " " : " un"); + } + printf("VPD : addr %08x, size %x\n", + hdr->cfg_region_off + img_addr, hdr->cfg_region_size); + if (hdr->hdr_rev <= FSP_HEADER_REVISION_2) + printf("\nNumber of APIs Supported : %d\n", hdr->api_num); + if (hdr->fsp_tempram_init) + printf("\tTempRamInit : %08x\n", + hdr->fsp_tempram_init + img_addr); + if (hdr->fsp_init) + printf("\tFspInit : %08x\n", hdr->fsp_init + img_addr); + if (hdr->fsp_notify) + printf("\tFspNotify : %08x\n", hdr->fsp_notify + img_addr); + if (hdr->hdr_rev >= FSP_HEADER_REVISION_1) { + if (hdr->fsp_mem_init) + printf("\tMemoryInit : %08x\n", + hdr->fsp_mem_init + img_addr); + if (hdr->fsp_tempram_exit) + printf("\tTempRamExit : %08x\n", + hdr->fsp_tempram_exit + img_addr); + if (hdr->fsp_silicon_init) + printf("\tSiliconInit : %08x\n", + hdr->fsp_silicon_init + img_addr); + } + + return 0; +} + +static struct cmd_tbl fsp_commands[] = { + U_BOOT_CMD_MKENT(hdr, 0, 1, do_hdr, "", ""), +}; + +static int do_fsp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct cmd_tbl *fsp_cmd; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + fsp_cmd = find_cmd_tbl(argv[1], fsp_commands, ARRAY_SIZE(fsp_commands)); + argc -= 2; + argv += 2; + if (!fsp_cmd || argc > fsp_cmd->maxargs) + return CMD_RET_USAGE; + + ret = fsp_cmd->cmd(fsp_cmd, flag, argc, argv); + + return cmd_process_error(fsp_cmd, ret); +} + +U_BOOT_CMD( + fsp, 2, 1, do_fsp, + "Show Intel Firmware Support Package (FSP) related information", + "hdr - Print FSP header information" +); diff --git a/roms/u-boot/cmd/x86/hob.c b/roms/u-boot/cmd/x86/hob.c new file mode 100644 index 000000000..01db93eb3 --- /dev/null +++ b/roms/u-boot/cmd/x86/hob.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014-2015, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <command.h> +#include <efi.h> +#include <uuid.h> +#include <asm/global_data.h> +#include <asm/hob.h> +#include <asm/fsp/fsp_hob.h> + +DECLARE_GLOBAL_DATA_PTR; + +static char *hob_type[] = { + "reserved", + "Hand-off", + "Mem Alloc", + "Res Desc", + "GUID Ext", + "FV", + "CPU", + "Mem Pool", + "reserved", + "FV2", + "Load PEIM", + "Capsule", +}; + +static char *res_type[] = { + "System", + "Memory-mapped I/O", + "I/O", + "Firmware device", + "Memory-mapped I/O port", + "Reserved", + "I/O reserved", +}; + +static struct guid_name { + efi_guid_t guid; + const char *name; +} guid_name[] = { + { FSP_HOB_RESOURCE_OWNER_TSEG_GUID, "TSEG" }, + { FSP_HOB_RESOURCE_OWNER_FSP_GUID, "FSP" }, + { FSP_HOB_RESOURCE_OWNER_SMM_PEI_SMRAM_GUID, "SMM PEI SMRAM" }, + { FSP_NON_VOLATILE_STORAGE_HOB_GUID, "NVS" }, + { FSP_VARIABLE_NV_DATA_HOB_GUID, "Variable NVS" }, + { FSP_GRAPHICS_INFO_HOB_GUID, "Graphics info" }, + { FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID1, "PCD database ea" }, + { FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID2, "PCD database 9b" }, + { FSP_HOB_RESOURCE_OWNER_PEIM_DXE_GUID, "PEIM Init DXE" }, + { FSP_HOB_RESOURCE_OWNER_ALLOC_STACK_GUID, "Alloc stack" }, + { FSP_HOB_RESOURCE_OWNER_SMBIOS_MEMORY_GUID, "SMBIOS memory" }, + { {}, "zero-guid" }, + {} +}; + +static const char *guid_to_name(const efi_guid_t *guid) +{ + struct guid_name *entry; + + for (entry = guid_name; entry->name; entry++) { + if (!guidcmp(guid, &entry->guid)) + return entry->name; + } + + return NULL; +} + +static void show_hob_details(const struct hob_header *hdr) +{ + const void *ptr = hdr; + + switch (hdr->type) { + case HOB_TYPE_RES_DESC: { + const struct hob_res_desc *res = ptr; + const char *typename; + + typename = res->type > 0 && res->type <= RES_MAX_MEM_TYPE ? + res_type[res->type] : "unknown"; + + printf(" base = %08llx, len = %08llx, end = %08llx, type = %d (%s)\n\n", + res->phys_start, res->len, res->phys_start + res->len, + res->type, typename); + break; + } + } +} + +static int do_hob(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct hob_header *hdr; + uint type; + char *desc; + int i = 0; + efi_guid_t *guid; + char uuid[UUID_STR_LEN + 1]; + bool verbose = false; + int seq = -1; /* Show all by default */ + + argc--; + argv++; + if (argc) { + if (!strcmp("-v", *argv)) { + verbose = true; + argc--; + argv++; + } + if (argc) + seq = simple_strtol(*argv, NULL, 16); + } + hdr = gd->arch.hob_list; + + printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr); + + printf("# | Address | Type | Len | "); + printf("%36s\n", "GUID"); + printf("---|----------|-----------|------|-"); + printf("------------------------------------\n"); + for (i = 0; !end_of_hob(hdr); i++, hdr = get_next_hob(hdr)) { + if (seq != -1 && seq != i) + continue; + printf("%02x | %08x | ", i, (unsigned int)hdr); + type = hdr->type; + if (type == HOB_TYPE_UNUSED) + desc = "*Unused*"; + else if (type == HOB_TYPE_EOH) + desc = "*EOH*"; + else if (type >= 0 && type <= ARRAY_SIZE(hob_type)) + desc = hob_type[type]; + else + desc = "*Invalid*"; + printf("%-9s | %04x | ", desc, hdr->len); + + if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC || + type == HOB_TYPE_GUID_EXT) { + const char *name; + + guid = (efi_guid_t *)(hdr + 1); + name = guid_to_name(guid); + if (!name) { + uuid_bin_to_str(guid->b, uuid, + UUID_STR_FORMAT_GUID); + name = uuid; + } + printf("%36s", name); + } else { + printf("%36s", "Not Available"); + } + printf("\n"); + if (verbose) + show_hob_details(hdr); + } + + return 0; +} + +U_BOOT_CMD(hob, 3, 1, do_hob, + "[-v] [seq] Print Hand-Off Block (HOB) information" + " -v - Show detailed HOB information where available" + " seq - Record # to show (all by default)", + "" +); diff --git a/roms/u-boot/cmd/x86/mtrr.c b/roms/u-boot/cmd/x86/mtrr.c new file mode 100644 index 000000000..fc61a549b --- /dev/null +++ b/roms/u-boot/cmd/x86/mtrr.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 Google, Inc + */ + +#include <common.h> +#include <command.h> +#include <log.h> +#include <asm/msr.h> +#include <asm/mp.h> +#include <asm/mtrr.h> + +static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { + "Uncacheable", + "Combine", + "2", + "3", + "Through", + "Protect", + "Back", +}; + +static void read_mtrrs(void *arg) +{ + struct mtrr_info *info = arg; + + mtrr_read_all(info); +} + +static int do_mtrr_list(int reg_count, int cpu_select) +{ + struct mtrr_info info; + int ret; + int i; + + printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", + "Mask ||", "Size ||"); + memset(&info, '\0', sizeof(info)); + ret = mp_run_on_cpus(cpu_select, read_mtrrs, &info); + if (ret) + return log_msg_ret("run", ret); + for (i = 0; i < reg_count; i++) { + const char *type = "Invalid"; + uint64_t base, mask, size; + bool valid; + + base = info.mtrr[i].base; + mask = info.mtrr[i].mask; + size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); + size |= (1 << 12) - 1; + size += 1; + valid = mask & MTRR_PHYS_MASK_VALID; + type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; + printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, + valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK, + mask & ~MTRR_PHYS_MASK_VALID, size); + } + + return 0; +} + +static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[]) +{ + const char *typename = argv[0]; + uint32_t start, size; + uint64_t base, mask; + int i, type = -1; + bool valid; + int ret; + + if (argc < 3) + return CMD_RET_USAGE; + for (i = 0; i < MTRR_TYPE_COUNT; i++) { + if (*typename == *mtrr_type_name[i]) + type = i; + } + if (type == -1) { + printf("Invalid type name %s\n", typename); + return CMD_RET_USAGE; + } + start = simple_strtoul(argv[1], NULL, 16); + size = simple_strtoul(argv[2], NULL, 16); + + base = start | type; + valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID; + mask = ~((uint64_t)size - 1); + mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; + if (valid) + mask |= MTRR_PHYS_MASK_VALID; + + ret = mtrr_set(cpu_select, reg, base, mask); + if (ret) + return CMD_RET_FAILURE; + + return 0; +} + +static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int reg_count = mtrr_get_var_count(); + int cmd; + int cpu_select; + uint reg; + int ret; + + cpu_select = MP_SELECT_BSP; + if (argc >= 3 && !strcmp("-c", argv[1])) { + const char *cpustr; + + cpustr = argv[2]; + if (*cpustr == 'a') + cpu_select = MP_SELECT_ALL; + else + cpu_select = simple_strtol(cpustr, NULL, 16); + argc -= 2; + argv += 2; + } + argc--; + argv++; + cmd = argv[0] ? *argv[0] : 0; + if (argc < 1 || !cmd) { + cmd = 'l'; + reg = 0; + } + if (cmd != 'l') { + if (argc < 2) + return CMD_RET_USAGE; + reg = simple_strtoul(argv[1], NULL, 16); + if (reg >= reg_count) { + printf("Invalid register number\n"); + return CMD_RET_USAGE; + } + } + if (cmd == 'l') { + bool first; + int i; + + i = mp_first_cpu(cpu_select); + if (i < 0) { + printf("Invalid CPU (err=%d)\n", i); + return CMD_RET_FAILURE; + } + first = true; + for (; i >= 0; i = mp_next_cpu(cpu_select, i)) { + if (!first) + printf("\n"); + printf("CPU %d:\n", i); + ret = do_mtrr_list(reg_count, i); + if (ret) { + printf("Failed to read CPU %d (err=%d)\n", i, + ret); + return CMD_RET_FAILURE; + } + first = false; + } + } else { + switch (cmd) { + case 'e': + ret = mtrr_set_valid(cpu_select, reg, true); + break; + case 'd': + ret = mtrr_set_valid(cpu_select, reg, false); + break; + case 's': + ret = do_mtrr_set(cpu_select, reg, argc - 2, argv + 2); + break; + default: + return CMD_RET_USAGE; + } + if (ret) { + printf("Operation failed (err=%d)\n", ret); + return CMD_RET_FAILURE; + } + } + + return 0; +} + +U_BOOT_CMD( + mtrr, 8, 1, do_mtrr, + "Use x86 memory type range registers (32-bit only)", + "[list] - list current registers\n" + "set <reg> <type> <start> <size> - set a register\n" + "\t<type> is Uncacheable, Combine, Through, Protect, Back\n" + "disable <reg> - disable a register\n" + "enable <reg> - enable a register\n" + "\n" + "Precede command with '-c <n>|all' to access a particular hex CPU, e.g.\n" + " mtrr -c all list; mtrr -c 2e list" +); |