diff options
Diffstat (limited to 'roms/u-boot/doc/board/intel')
| -rw-r--r-- | roms/u-boot/doc/board/intel/bayleybay.rst | 29 | ||||
| -rw-r--r-- | roms/u-boot/doc/board/intel/cherryhill.rst | 30 | ||||
| -rw-r--r-- | roms/u-boot/doc/board/intel/cougarcanyon2.rst | 24 | ||||
| -rw-r--r-- | roms/u-boot/doc/board/intel/crownbay.rst | 43 | ||||
| -rw-r--r-- | roms/u-boot/doc/board/intel/edison.rst | 170 | ||||
| -rw-r--r-- | roms/u-boot/doc/board/intel/galileo.rst | 22 | ||||
| -rw-r--r-- | roms/u-boot/doc/board/intel/index.rst | 16 | ||||
| -rw-r--r-- | roms/u-boot/doc/board/intel/minnowmax.rst | 70 | ||||
| -rw-r--r-- | roms/u-boot/doc/board/intel/slimbootloader.rst | 177 |
9 files changed, 581 insertions, 0 deletions
diff --git a/roms/u-boot/doc/board/intel/bayleybay.rst b/roms/u-boot/doc/board/intel/bayleybay.rst new file mode 100644 index 000000000..db97f645f --- /dev/null +++ b/roms/u-boot/doc/board/intel/bayleybay.rst @@ -0,0 +1,29 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com> + +Bayley Bay CRB +============== + +This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. +Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at +the time of writing). Put it in the corresponding board directory and rename +it to fsp.bin. + +Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same +board directory as vga.bin. + +You still need two more binary blobs. For Bayley Bay, they can be extracted +from the sample SPI image provided in the FSP (SPI.bin at the time of writing):: + + $ ./tools/ifdtool -x BayleyBay/SPI.bin + $ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin + $ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make bayleybay_defconfig + $ make all + +Note that the debug version of the FSP is bigger in size. If this version +is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of +the default value 0xfffc0000. diff --git a/roms/u-boot/doc/board/intel/cherryhill.rst b/roms/u-boot/doc/board/intel/cherryhill.rst new file mode 100644 index 000000000..151f0613f --- /dev/null +++ b/roms/u-boot/doc/board/intel/cherryhill.rst @@ -0,0 +1,30 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com> + +Cherry Hill CRB +=============== + +This uses Intel FSP for Braswell platform. Download it from Intel FSP website, +put the .fd file to the board directory and rename it to fsp.bin. + +Extract descriptor.bin and me.bin from the original BIOS on the board using +ifdtool and put them to the board directory as well. + +Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS +image for the integrated graphics device. Instead a new binary called Video +BIOS Table (VBT) is shipped. Put it to the board directory and rename it to +vbt.bin if you want graphics support in U-Boot. + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make cherryhill_defconfig + $ make all + +An important note for programming u-boot.rom to the on-board SPI flash is that +you need make sure the SPI flash's 'quad enable' bit in its status register +matches the settings in the descriptor.bin, otherwise the board won't boot. + +For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the +status register by DediProg in: Config > Modify Status Register > Write Status +Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it +persists in SPI flash part regardless of the u-boot.rom image burned. diff --git a/roms/u-boot/doc/board/intel/cougarcanyon2.rst b/roms/u-boot/doc/board/intel/cougarcanyon2.rst new file mode 100644 index 000000000..5e3e7a182 --- /dev/null +++ b/roms/u-boot/doc/board/intel/cougarcanyon2.rst @@ -0,0 +1,24 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com> + +Cougar Canyon 2 CRB +=================== + +This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors +with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP +website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the +time of writing) in the board directory and rename it to fsp.bin. + +Now build U-Boot and obtain u-boot.rom:: + + $ make cougarcanyon2_defconfig + $ make all + +The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in +the board manual. The SPI-0 flash should have flash descriptor plus ME firmware +and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0 +flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program +this image to the SPI-0 flash according to the board manual just once and we are +all set. For programming U-Boot we just need to program SPI-1 flash. Since the +default u-boot.rom image for this board is set to 2MB, it should be programmed +to the last 2MB of the 8MB chip, address range [600000, 7FFFFF]. diff --git a/roms/u-boot/doc/board/intel/crownbay.rst b/roms/u-boot/doc/board/intel/crownbay.rst new file mode 100644 index 000000000..4fcf9811c --- /dev/null +++ b/roms/u-boot/doc/board/intel/crownbay.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com> + +Crown Bay CRB +============= + +U-Boot support of Intel `Crown Bay`_ board relies on a binary blob called +Firmware Support Package (`FSP`_) to perform all the necessary initialization +steps as documented in the BIOS Writer Guide, including initialization of the +CPU, memory controller, chipset and certain bus interfaces. + +Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too. + + * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd + * ./Microcode/C0_22211.BIN + +Rename the first one to fsp.bin and second one to cmc.bin and put them in the +board directory. + +Note the FSP release version 001 has a bug which could cause random endless +loop during the FspInit call. This bug was published by Intel although Intel +did not describe any details. We need manually apply the patch to the FSP +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP +binary, change the following five bytes values from orginally E8 42 FF FF FF +to B8 00 80 0B 00. + +As for the video ROM, you need manually extract it from the Intel provided +BIOS for Crown Bay `here`_, using the AMI `MMTool`_. Check PCI option +ROM ID 8086:4108, extract and save it as vga.bin in the board directory. + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make crownbay_defconfig + $ make all + +.. _`Crown Bay`: http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +.. _`FSP`: http://www.intel.com/fsp +.. _`here`: http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html +.. _`MMTool`: http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/ diff --git a/roms/u-boot/doc/board/intel/edison.rst b/roms/u-boot/doc/board/intel/edison.rst new file mode 100644 index 000000000..5a65673d1 --- /dev/null +++ b/roms/u-boot/doc/board/intel/edison.rst @@ -0,0 +1,170 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Andy Shevchenko <andriy.shevchenko@linux.intel.com> + +Edison +====== + +Build Instructions for U-Boot as main bootloader +------------------------------------------------ + +Simple you can build U-Boot and obtain u-boot.bin:: + + $ make edison_defconfig + $ make all + +Updating U-Boot on Edison +------------------------- + +By default Intel Edison boards are shipped with preinstalled heavily +patched U-Boot v2014.04. Though it supports DFU which we may be able to +use. + +1. Prepare u-boot.bin as described in chapter above. You still need one + more step (if and only if you have original U-Boot), i.e. run the + following command:: + + $ truncate -s %4096 u-boot.bin + +2. Run your board and interrupt booting to U-Boot console. In the console + call:: + + => run do_force_flash_os + +3. Wait for few seconds, it will prepare environment variable and runs + DFU. Run DFU command from the host system:: + + $ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin + +4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and + reset the board:: + + => reset + +Updating U-Boot using xFSTK +--------------------------- + +You can also update U-Boot using the xfstk-dldr-solo tool if you can build it. +One way to do that is to follow the `xFSTK`_ instructions. In short, after you +install all necessary dependencies and clone repository, it will look like this: + +.. code-block:: sh + + cd xFSTK + export DISTRIBUTION_NAME=ubuntu20.04 + export BUILD_VERSION=1.8.5 + git checkout v$BUILD_VERSION + ... + +Once you have built it, you can copy xfstk-dldr-solo to /usr/local/bin and +libboost_program_options.so.1.54.0 to /usr/lib/i386-linux-gnu/ and with luck +it will work. You might find this `drive`_ helpful. + +If it does, then you can download and unpack the Edison recovery image, +install dfu-util, reset your board and flash U-Boot like this: + +.. code-block:: sh + + xfstk-dldr-solo --gpflags 0x80000007 \ + --osimage u-boot-edison.img \ + --fwdnx recover/edison_dnx_fwr.bin \ + --fwimage recover/edison_ifwi-dbg-00.bin \ + --osdnx recover/edison_dnx_osr.bin + +This should show the following + +.. code-block:: none + + XFSTK Downloader Solo 1.8.5 + Copyright (c) 2015 Intel Corporation + Build date and time: Aug 15 2020 15:07:13 + + .Intel SoC Device Detection Found + Parsing Commandline.... + Registering Status Callback.... + .Initiating Download Process.... + .......(lots of dots)........XFSTK-STATUS--Reconnecting to device - Attempt #1 + .......(even more dots)...................... + +You have about 10 seconds after resetting the board to type the above command. +If you want to check if the board is ready, type: + +.. code-block:: none + + lsusb | egrep "8087|8086" + Bus 001 Device 004: ID 8086:e005 Intel Corp. + +If you see a device with the same ID as above, the board is waiting for your +command. + +After about 5 seconds you should see some console output from the board: + +.. code-block:: none + + ****************************** + PSH KERNEL VERSION: b0182b2b + WR: 20104000 + ****************************** + + SCU IPC: 0x800000d0 0xfffce92c + + PSH miaHOB version: TNG.B0.VVBD.0000000c + + microkernel built 11:24:08 Feb 5 2015 + + ******* PSH loader ******* + PCM page cache size = 192 KB + Cache Constraint = 0 Pages + Arming IPC driver .. + Adding page store pool .. + PagestoreAddr(IMR Start Address) = 0x04899000 + pageStoreSize(IMR Size) = 0x00080000 + + *** Ready to receive application *** + +After another 10 seconds the xFSTK tool completes and the board resets. About +10 seconds after that should see the above message again and then within a few +seconds U-Boot should start on your board: + +.. code-block:: none + + U-Boot 2020.10-rc3 (Sep 03 2020 - 18:44:28 -0600) + + CPU: Genuine Intel(R) CPU 4000 @ 500MHz + DRAM: 980.6 MiB + WDT: Started with servicing (60s timeout) + MMC: mmc@ff3fc000: 0, mmc@ff3fa000: 1 + Loading Environment from MMC... OK + In: serial + Out: serial + Err: serial + Saving Environment to MMC... Writing to redundant MMC(0)... OK + Saving Environment to MMC... Writing to MMC(0)... OK + Net: No ethernet found. + Hit any key to stop autoboot: 0 + Target:blank + Partitioning using GPT + Writing GPT: success! + Saving Environment to MMC... Writing to redundant MMC(0)... OK + Flashing already done... + 5442816 bytes read in 238 ms (21.8 MiB/s) + Valid Boot Flag + Setup Size = 0x00003c00 + Magic signature found + Using boot protocol version 2.0c + Linux kernel version 3.10.17-poky-edison+ (ferry@kalamata) #1 SMP PREEMPT Mon Jan 11 14:54:18 CET 2016 + Building boot_params at 0x00090000 + Loading bzImage at address 100000 (5427456 bytes) + Magic signature found + Kernel command line: "rootwait ..." + Magic signature found + + Starting kernel ... + + ... + + Poky (Yocto Project Reference Distro) 1.7.2 edison ttyMFD2 + + edison login: + +.. _xFSTK: https://github.com/edison-fw/xFSTK +.. _drive: https://drive.google.com/drive/u/0/folders/1URPHrOk9-UBsh8hjv-7WwC0W6Fy61uAJ diff --git a/roms/u-boot/doc/board/intel/galileo.rst b/roms/u-boot/doc/board/intel/galileo.rst new file mode 100644 index 000000000..f51a06bb9 --- /dev/null +++ b/roms/u-boot/doc/board/intel/galileo.rst @@ -0,0 +1,22 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com> + +Galileo +======= + +Only one binary blob is needed for Remote Management Unit (RMU) within Intel +Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is +needed by the Quark SoC itself. + +You can get the binary blob from Quark Board Support Package from Intel website: + + * ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin + +Rename the file and put it to the board directory by:: + + $ cp RMU.bin board/intel/galileo/rmu.bin + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make galileo_defconfig + $ make all diff --git a/roms/u-boot/doc/board/intel/index.rst b/roms/u-boot/doc/board/intel/index.rst new file mode 100644 index 000000000..f545dee87 --- /dev/null +++ b/roms/u-boot/doc/board/intel/index.rst @@ -0,0 +1,16 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Intel +===== + +.. toctree:: + :maxdepth: 2 + + bayleybay + cherryhill + cougarcanyon2 + crownbay + edison + galileo + minnowmax + slimbootloader diff --git a/roms/u-boot/doc/board/intel/minnowmax.rst b/roms/u-boot/doc/board/intel/minnowmax.rst new file mode 100644 index 000000000..028121735 --- /dev/null +++ b/roms/u-boot/doc/board/intel/minnowmax.rst @@ -0,0 +1,70 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Simon Glass <sjg@chromium.org> + +Minnowboard MAX +=============== + +This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. +Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at +the time of writing). Put it in the corresponding board directory and rename +it to fsp.bin. + +Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same +board directory as vga.bin. + +You still need two more binary blobs. For Minnowboard MAX, we can reuse the +same ME firmware above, but for flash descriptor, we need get that somewhere +else, as the one above does not seem to work, probably because it is not +designed for the Minnowboard MAX. Now download the original firmware image +for this board from: + + * http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip + +Unzip it:: + + $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip + +Use ifdtool in the U-Boot tools directory to extract the images from that +file, for example:: + + $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin + +This will provide the descriptor file - copy this into the correct place:: + + $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make minnowmax_defconfig + $ make all + +Checksums are as follows (but note that newer versions will invalidate this):: + + $ md5sum -b board/intel/minnowmax/*.bin + ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin + 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin + 894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin + a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin + +The ROM image is broken up into these parts: + +====== ================== ============================ +Offset Description Controlling config +====== ================== ============================ +000000 descriptor.bin Hard-coded to 0 in ifdtool +001000 me.bin Set by the descriptor +500000 <spare> +6ef000 Environment CONFIG_ENV_OFFSET +6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE +700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE +7b0000 vga.bin CONFIG_VGA_BIOS_ADDR +7c0000 fsp.bin CONFIG_FSP_ADDR +7f8000 <spare> (depends on size of fsp.bin) +7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16 +====== ================== ============================ + +Overall ROM image size is controlled by CONFIG_ROM_SIZE. + +Note that the debug version of the FSP is bigger in size. If this version +is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of +the default value 0xfffc0000. diff --git a/roms/u-boot/doc/board/intel/slimbootloader.rst b/roms/u-boot/doc/board/intel/slimbootloader.rst new file mode 100644 index 000000000..18f1cc056 --- /dev/null +++ b/roms/u-boot/doc/board/intel/slimbootloader.rst @@ -0,0 +1,177 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Aiden Park <aiden.park@intel.com> + +Slim Bootloader +=============== + +Introduction +------------ + +This target is to enable U-Boot_ as a payload of `Slim Bootloader`_ (a.k.a SBL) +boot firmware which currently supports QEMU, Apollolake, Whiskeylake, +Coffeelake-R platforms. + +The `Slim Bootloader`_ is designed with multi-stages (Stage1A/B, Stage2, Payload) +architecture to cover from reset vector to OS booting and it consumes +`Intel FSP`_ for silicon initialization. + +* Stage1A: Reset vector, CAR init with FSP-T +* Stage1B: Memory init with FSP-M, CAR teardown, Continue execution in memory +* Stage2 : Rest of Silicon init with FSP-S, Create HOB, Hand-off to Payload +* Payload: Payload init with HOB, Load OS from media, Booting OS + +The Slim Bootloader stages (Stage1A/B, Stage2) focus on chipset, hardware and +platform specific initialization, and it provides useful information to a +payload in a HOB (Hand-Off Block) which has serial port, memory map, performance +data info and so on. This is Slim Bootloader architectural design to make a +payload light-weight, platform independent and more generic across different +boot solutions or payloads, and to minimize hardware re-initialization in a +payload. + +Build Instruction for U-Boot as a Slim Bootloader payload +--------------------------------------------------------- + +Build U-Boot and obtain u-boot-dtb.bin:: + + $ make distclean + $ make slimbootloader_defconfig + $ make all + +Prepare Slim Bootloader +----------------------- + +1. Setup Build Environment for Slim Bootloader. + + Refer to `Getting Started`_ page in `Slim Bootloader`_ document site. + +2. Get source code. Let's simply clone the repo:: + + $ git clone https://github.com/slimbootloader/slimbootloader.git + +3. Copy u-boot-dtb.bin to Slim Bootloader. + Slim Bootloader looks for a payload from the specific location. + Copy the build u-boot-dtb.bin to the expected location:: + + $ mkdir -p <Slim Bootloader Dir>/PayloadPkg/PayloadBins/ + $ cp <U-Boot Dir>/u-boot-dtb.bin <Slim Bootloader Dir>/PayloadPkg/PayloadBins/u-boot-dtb.bin + +Build Instruction for Slim Bootloader for QEMU target +----------------------------------------------------- + +Slim Bootloader supports multiple payloads, and a board of Slim Bootloader +detects its target payload by PayloadId in board configuration. +The PayloadId can be any 4 Bytes value. + +1. Update PayloadId. Let's use 'U-BT' as an example:: + + $ vi Platform/QemuBoardPkg/CfgData/CfgDataExt_Brd1.dlt + -GEN_CFG_DATA.PayloadId | 'AUTO' + +GEN_CFG_DATA.PayloadId | 'U-BT' + +2. Update payload text base. PAYLOAD_EXE_BASE must be the same as U-Boot + CONFIG_SYS_TEXT_BASE in board/intel/slimbootloader/Kconfig. + PAYLOAD_LOAD_HIGH must be 0:: + + $ vi Platform/QemuBoardPkg/BoardConfig.py + + self.PAYLOAD_LOAD_HIGH = 0 + + self.PAYLOAD_EXE_BASE = 0x00100000 + +3. Build QEMU target. Make sure u-boot-dtb.bin and U-BT PayloadId + in build command. The output is Outputs/qemu/SlimBootloader.bin:: + + $ python BuildLoader.py build qemu -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma" + +4. Launch Slim Bootloader on QEMU. + You should reach at U-Boot serial console:: + + $ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin + +Test Linux booting on QEMU target +--------------------------------- + +Let's use LeafHill (APL) Yocto image for testing. +Download it from http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/machines/leafhill/. + +1. Prepare Yocto hard disk image:: + + $ wget http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/machines/leafhill/leafhill-4.0-jethro-2.0.tar.bz2 + $ tar -xvf leafhill-4.0-jethro-2.0.tar.bz2 + $ ls -l leafhill-4.0-jethro-2.0/binary/core-image-sato-intel-corei7-64.hddimg + +2. Launch Slim Bootloader on QEMU with disk image:: + + $ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin -drive id=mydrive,if=none,file=/path/to/core-image-sato-intel-corei7-64.hddimg,format=raw -device ide-hd,drive=mydrive + +3. Update boot environment values on shell:: + + => setenv bootfile vmlinuz + => setenv bootdev scsi + => boot + +Build Instruction for Slim Bootloader for LeafHill (APL) target +--------------------------------------------------------------- + +Prepare U-Boot and Slim Bootloader as described at the beginning of this page. +Also, the PayloadId needs to be set for APL board. + +1. Update PayloadId. Let's use 'U-BT' as an example:: + + $ vi Platform/ApollolakeBoardPkg/CfgData/CfgData_Int_LeafHill.dlt + -GEN_CFG_DATA.PayloadId | 'AUTO + +GEN_CFG_DATA.PayloadId | 'U-BT' + +2. Update payload text base. + +* PAYLOAD_EXE_BASE must be the same as U-Boot CONFIG_SYS_TEXT_BASE + in board/intel/slimbootloader/Kconfig. +* PAYLOAD_LOAD_HIGH must be 0:: + + $ vi Platform/ApollolakeBoardPkg/BoardConfig.py + + self.PAYLOAD_LOAD_HIGH = 0 + + self.PAYLOAD_EXE_BASE = 0x00100000 + +3. Build APL target. Make sure u-boot-dtb.bin and U-BT PayloadId + in build command. The output is Outputs/apl/Stitch_Components.zip:: + + $ python BuildLoader.py build apl -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma" + +4. Stitch IFWI. + + Refer to Apollolake_ page in Slim Bootloader document site:: + + $ python Platform/ApollolakeBoardPkg/Script/StitchLoader.py -i <Existing IFWI> -s Outputs/apl/Stitch_Components.zip -o <Output IFWI> + +5. Flash IFWI. + + Use DediProg to flash IFWI. You should reach at U-Boot serial console. + + +Build Instruction to use ELF U-Boot +----------------------------------- + +1. Enable CONFIG_OF_EMBED:: + + $ vi configs/slimbootloader_defconfig + +CONFIG_OF_EMBED=y + +2. Build U-Boot:: + + $ make distclean + $ make slimbootloader_defconfig + $ make all + $ strip u-boot (removing symbol for reduced size) + +3. Do same steps as above + +* Copy u-boot (ELF) to PayloadBins directory +* Update PayloadId 'U-BT' as above. +* No need to set PAYLOAD_LOAD_HIGH and PAYLOAD_EXE_BASE. +* Build Slim Bootloader. Use u-boot instead of u-boot-dtb.bin:: + + $ python BuildLoader.py build <qemu or apl> -p "OsLoader.efi:LLDR:Lz4;u-boot:U-BT:Lzma" + +.. _U-Boot: https://source.denx.de/ +.. _`Slim Bootloader`: https://github.com/slimbootloader/ +.. _`Intel FSP`: https://github.com/IntelFsp/ +.. _`Getting Started`: https://slimbootloader.github.io/getting-started/ +.. _Apollolake: https://slimbootloader.github.io/supported-hardware/apollo-lake-crb.html#stitching |