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Diffstat (limited to 'roms/u-boot/doc/device-tree-bindings/i2c')
13 files changed, 473 insertions, 0 deletions
diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/generic-acpi.txt b/roms/u-boot/doc/device-tree-bindings/i2c/generic-acpi.txt new file mode 100644 index 000000000..3510a71b5 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/generic-acpi.txt @@ -0,0 +1,42 @@ +I2C generic device +================== + +This is used only to generate ACPI tables for an I2C device. + +Required properties : + + - compatible : "i2c-chip"; + - reg : I2C chip address + - acpi,hid : HID name for the device + +Optional properies in addition to device.txt: + + - reset-gpios : GPIO used to assert reset to the device + - irq-gpios : GPIO used for interrupt (if Interrupt is not used) + - stop-gpios : GPIO used to stop the device + - interrupts-extended : Interrupt to use for the device + - reset-delay-ms : Delay after de-asserting reset, in ms + - reset-off-delay-ms : Delay after asserting reset (during power off) + - enable-delay-ms : Delay after asserting enable + - enable-off-delay-ms : Delay after de-asserting enable (during power off) + - stop-delay-ms : Delay after de-aserting stop + - stop-off-delay-ms : Delay after asserting stop (during power off) + - hid-descr-addr : HID register offset (for Human Interface Devices) + +Example +------- + + elan-touchscreen@10 { + compatible = "i2c-chip"; + reg = <0x10>; + acpi,hid = "ELAN0001"; + acpi,ddn = "ELAN Touchscreen"; + interrupts-extended = <&acpi_gpe GPIO_21_IRQ + IRQ_TYPE_EDGE_FALLING>; + linux,probed; + reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <20>; + enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>; + enable-delay-ms = <1>; + acpi,has-power-resource; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/i2c-at91.txt b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-at91.txt new file mode 100644 index 000000000..2065b7341 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-at91.txt @@ -0,0 +1,26 @@ +I2C for Atmel platforms + +Required properties : +- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c", + "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c", + "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c". +- reg: physical base address of the controller and length of memory mapped + region. +- #address-cells = <1>; +- #size-cells = <0>; +- clocks: phandles to input clocks. + +Optional properties: +- clock-frequency: Desired I2C bus frequency in Hz, default value is 100000. +- Child nodes conforming to i2c bus binding. + +Examples : + +i2c0: i2c@f8028000 { + compatible = "atmel,sama5d2-i2c"; + reg = <0xf8028000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + clock-frequency = <100000>; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/i2c-cdns.txt b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-cdns.txt new file mode 100644 index 000000000..202e0b762 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-cdns.txt @@ -0,0 +1,20 @@ +Cadence I2C controller Device Tree Bindings +------------------------------------------- + +Required properties: +- compatible : Should be "cdns,i2c-r1p10" or "xlnx,zynq-spi-r1p10". +- reg : Physical base address and size of I2C registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller +- clocks : Clock phandles (see clock bindings for details). + +Example: + i2c0: i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + reg = <0xe0004000 0x1000>; + clocks = <&clkc 38>; + interrupts = <0 25 4>; + interrupt-parent = <&intc>; + status = "disabled"; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/i2c-cortina.txt b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-cortina.txt new file mode 100644 index 000000000..59d523582 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-cortina.txt @@ -0,0 +1,18 @@ +* I2C for Cortina platforms + +Required properties : +- compatible : Must be "cortina,ca-i2c" +- reg : Offset and length of the register set for the device + +Recommended properties : +- clock-frequency : desired I2C bus clock frequency in Hz. If not specified, + default value is 100000. Possible values are 100000, + 400000 and 1000000. + +Examples : + + i2c: i2c@f4329120 { + compatible = "cortina,ca-i2c"; + reg = <0x0 0xf4329120 0x28>; + clock-frequency = <400000>; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/i2c-designware.txt b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-designware.txt new file mode 100644 index 000000000..be766be81 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-designware.txt @@ -0,0 +1,73 @@ +* Synopsys DesignWare I2C + +Required properties : + + - compatible : should be "snps,designware-i2c" + or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback + - reg : Offset and length of the register set for the device + - interrupts : <IRQ> where IRQ is the interrupt number. + - clocks : phandles for the clocks, see the description of clock-names below. + The phandle for the "ic_clk" clock is required. The phandle for the "pclk" + clock is optional. If a single clock is specified but no clock-name, it is + the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first. + +Recommended properties : + + - clock-frequency : desired I2C bus clock frequency in Hz. + +Optional properties : + + - clock-names : Contains the names of the clocks: + "ic_clk", for the core clock used to generate the external I2C clock. + "pclk", the interface clock, required for register access. + + - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold + time, named ICPU_CFG:TWI_DELAY in the datasheet. + + - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds. + This option is only supported in hardware blocks version 1.11a or newer and + on Microsemi SoCs ("mscc,ocelot-i2c" compatible). + + - i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds. + This value which is by default 300ns is used to compute the tLOW period. + + - i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds. + This value which is by default 300ns is used to compute the tHIGH period. + +Examples : + + i2c@f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xf0000 0x1000>; + interrupts = <11>; + clock-frequency = <400000>; + }; + + i2c@1120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x1120000 0x1000>; + interrupt-parent = <&ictl>; + interrupts = <12 1>; + clock-frequency = <400000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <300>; + i2c-scl-falling-time-ns = <300>; + };x + + i2c@1120000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2000 0x100>; + clock-frequency = <400000>; + clocks = <&i2cclk>; + interrupts = <0>; + + eeprom@64 { + compatible = "linux,slave-24c02"; + reg = <0x40000064>; + }; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/i2c-gpio.txt b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-gpio.txt new file mode 100644 index 000000000..b06b82993 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-gpio.txt @@ -0,0 +1,41 @@ +I2C gpio device binding +======================= + +Driver: +- drivers/i2c/i2c-gpio.c + +Software i2c device-tree node properties: +Required: +* #address-cells = <1>; +* #size-cells = <0>; +* compatible = "i2c-gpio"; +* gpios = <sda ...>, <scl ...>; + +Optional: +* i2c-gpio,delay-us = <5>; + The resulting transfer speed can be adjusted by setting the delay[us] + between gpio-toggle operations. Speed [Hz] = 1000000 / 4 * udelay[us], + It not defined, then default is 5us (~50KHz). +* i2c-gpio,deblock + Run deblocking sequence when the driver gets probed. +* i2c-gpio,scl-output-only; + Set if SCL is an output only + +Example: + +i2c-gpio@1 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "i2c-gpio"; + gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, /* SDA */ + <&gpd1 1 GPIO_ACTIVE_HIGH>; /* CLK */ + + i2c-gpio,delay-us = <5>; + + some_device@5 { + compatible = "some_device"; + reg = <0x5>; + ... + }; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/i2c-mux.txt b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-mux.txt new file mode 100644 index 000000000..af84cce5c --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-mux.txt @@ -0,0 +1,60 @@ +Common i2c bus multiplexer/switch properties. + +An i2c bus multiplexer/switch will have several child busses that are +numbered uniquely in a device dependent manner. The nodes for an i2c bus +multiplexer/switch will have one child node for each child +bus. + +Required properties: +- #address-cells = <1>; +- #size-cells = <0>; + +Required properties for child nodes: +- #address-cells = <1>; +- #size-cells = <0>; +- reg : The sub-bus number. + +Optional properties for child nodes: +- Other properties specific to the multiplexer/switch hardware. +- Child nodes conforming to i2c bus binding + + +Example : + + /* + An NXP pca9548 8 channel I2C multiplexer at address 0x70 + with two NXP pca8574 GPIO expanders attached, one each to + ports 3 and 4. + */ + + mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + gpio1: gpio@38 { + compatible = "nxp,pca8574"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + gpio2: gpio@38 { + compatible = "nxp,pca8574"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/i2c-stm32.txt b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-stm32.txt new file mode 100644 index 000000000..df03743ac --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/i2c-stm32.txt @@ -0,0 +1,30 @@ +* I2C controller embedded in STMicroelectronis STM32 platforms + +Required properties : +- compatible : Must be "st,stm32f7-i2c" +- reg : Offset and length of the register set for the device +- resets: Must contain the phandle to the reset controller +- clocks: Must contain the input clock of the I2C instance +- A pinctrl state named "default" must be defined to set pins in mode of + operation for I2C transfer +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties : +- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, + the default 100 kHz frequency will be used. As only Normal, Fast and Fast+ + modes are implemented, possible values are 100000, 400000 and 1000000. + +Example : + + i2c1: i2c@40005400 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005400 0x400>; + resets = <&rcc 181>; + clocks = <&clk_pclk1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/i2c.txt b/roms/u-boot/doc/device-tree-bindings/i2c/i2c.txt new file mode 100644 index 000000000..9698e4899 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/i2c.txt @@ -0,0 +1,46 @@ +U-Boot I2C +---------- + +U-Boot's I2C model has the concept of an offset within a chip (I2C target +device). The offset can be up to 4 bytes long, but is normally 1 byte, +meaning that offsets from 0 to 255 are supported by the chip. This often +corresponds to register numbers. + +Apart from the controller-specific I2C bindings, U-Boot supports a special +property which allows the chip offset length to be selected. + +Optional properties: +- u-boot,i2c-offset-len - length of chip offset in bytes. If omitted the + default value of 1 is used. +- u-boot,i2c-transaction-bytes - the length of single I2C transaction on + the bus. Some devices require more than single byte transmission + (e.g. mc34708 mfd). This information is necessary to correctly + initialize (put into idle state) I2C bus after soft reset. +- gpios = <sda ...>, <scl ...>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c_xfer>; + pinctrl-1 = <&i2c_gpio>; + Pin description for I2C bus software deblocking. + + +Example +------- + +i2c4: i2c@12ca0000 { + cros-ec@1e { + reg = <0x1e>; + compatible = "google,cros-ec"; + i2c-max-frequency = <100000>; + u-boot,i2c-offset-len = <0>; + u-boot,i2c-transaction-bytes = <3>; + ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_xfer>; + pinctrl-1 = <&i2c1_gpio>; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>, /* SDA */ + <&gpio1 27 GPIO_ACTIVE_LOW>; /* SCL */ +}; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/roms/u-boot/doc/device-tree-bindings/i2c/nvidia,tegra186-bpmp-i2c.txt new file mode 100644 index 000000000..ab240e10d --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/nvidia,tegra186-bpmp-i2c.txt @@ -0,0 +1,42 @@ +NVIDIA Tegra186 BPMP I2C controller + +In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW +devices, such as the I2C controller for the power management I2C bus. Software +running on other CPUs must perform IPC to the BPMP in order to execute +transactions on that I2C bus. This binding describes an I2C bus that is +accessed in such a fashion. + +The BPMP I2C node must be located directly inside the main BPMP node. See +../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. + +This node represents an I2C controller. See ../i2c/i2c.txt for details of the +core I2C binding. + +Required properties: +- compatible: + Array of strings. + One of: + - "nvidia,tegra186-bpmp-i2c". +- #address-cells: Address cells for I2C device address. + Single-cell integer. + Must be <1>. +- #size-cells: + Single-cell integer. + Must be <0>. +- nvidia,bpmp-bus-id: + Single-cell integer. + Indicates the I2C bus number this DT node represent, as defined by the + BPMP firmware. + +Example: + +bpmp { + ... + + i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + #address-cells = <1>; + #size-cells = <0>; + nvidia,bpmp-bus-id = <5>; + }; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/nx_i2c.txt b/roms/u-boot/doc/device-tree-bindings/i2c/nx_i2c.txt new file mode 100644 index 000000000..9f3abe78e --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/nx_i2c.txt @@ -0,0 +1,28 @@ +I2C controller embedded in Nexell's/Samsung's SoC S5P4418 and S5P6818 + +Driver: +- drivers/i2c/nx_i2c.c + +Required properties: +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "nexell,s5pxx18-i2c"; +- reg = <i2c_base 0x100>; + Where i2c_base has to be the base address of the i2c-register set. + I2C0: 0xc00a4000 + I2C1: 0xc00a5000 + I2C2: 0xc00a6000 + +Optional properties: +- clock-frequency: Desired I2C bus frequency in Hz, default value is 100000. +- i2c-sda-delay-ns (S5P6818 only): SDA delay in ns, default value is 0. +- Child nodes conforming to i2c bus binding. + +Example: + i2c0:i2c@c00a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nexell,s5pxx18-i2c"; + reg = <0xc00a4000 0x100>; + clock-frequency = <400000>; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/octeon-i2c.txt b/roms/u-boot/doc/device-tree-bindings/i2c/octeon-i2c.txt new file mode 100644 index 000000000..9c1908ec2 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/octeon-i2c.txt @@ -0,0 +1,24 @@ +* I2C controller embedded in Marvell Octeon platforms + +Required properties : +- compatible : Must be "cavium,octeon-7890-twsi" or a compatible string +- reg : Offset and length of the register set for the device +- clocks: Must contain the input clock of the I2C instance +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties : +- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, + the default 100 kHz frequency will be used. As only Normal, Fast and Fast+ + modes are implemented, possible values are 100000, 400000 and 1000000. + +Example : + + i2c0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7890-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + clock-frequency = <100000>; + clocks = <&sclk>; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/i2c/tegra20-i2c.txt b/roms/u-boot/doc/device-tree-bindings/i2c/tegra20-i2c.txt new file mode 100644 index 000000000..72649dffa --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/i2c/tegra20-i2c.txt @@ -0,0 +1,23 @@ +(Placeholder note while we locate the kernel Tegra20 bindings) + +Added in U-Boot: + +Required properties: + - clocks : Two clocks must be given, each as a phandle to the Tegra's + CAR node and the clock number as a parameter: + - the I2C clock to use for the peripheral + - the pll_p_out3 clock, which can be used for fast operation. This + does not change and is the same for all I2C nodes. + +Example: +(TODO: merge with existing example): + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 116 >; + /* PERIPH_ID_I2C2, PLL_P_OUT3 */ + clocks = <&tegra_car 54>, <&tegra_car 124>; + }; |