diff options
Diffstat (limited to 'roms/u-boot/doc/device-tree-bindings/misc')
14 files changed, 533 insertions, 0 deletions
diff --git a/roms/u-boot/doc/device-tree-bindings/misc/altera_sysid.txt b/roms/u-boot/doc/device-tree-bindings/misc/altera_sysid.txt new file mode 100644 index 000000000..54462eb5e --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/altera_sysid.txt @@ -0,0 +1,4 @@ +Altera sysid + +Required properties: +- compatible : should be "altr,sysid-1.0" diff --git a/roms/u-boot/doc/device-tree-bindings/misc/bootcounter.txt b/roms/u-boot/doc/device-tree-bindings/misc/bootcounter.txt new file mode 100644 index 000000000..d32fbc37b --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/bootcounter.txt @@ -0,0 +1,21 @@ +U-Boot bootcounter Devicetree Binding +===================================== + +The device tree node describes the U-Boot bootcounter +memory based device binding. + +Required properties : + +- compatible : "u-boot,bootcount"; +- single-word : set this, if you have only one word space + for storing the bootcounter. + +Example +------- + +MPC83xx based board: + +bootcount@0x13ff8 { + compatible = "u-boot,bootcount"; + reg = <0x13ff8 0x08>; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/cros-ec.txt b/roms/u-boot/doc/device-tree-bindings/misc/cros-ec.txt new file mode 100644 index 000000000..07ea7cdea --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/cros-ec.txt @@ -0,0 +1,38 @@ +Chrome OS CROS_EC Binding +====================== + +The device tree node which describes the operation of the CROS_EC interface +is as follows: + +Required properties : +- compatible = "google,cros-ec" + +Optional properties : +- spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus + operation +- i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus + operation +- ec-interrupt : Selects the EC interrupt, defined as a GPIO according + to the platform +- optimise-flash-write : Boolean property - if present then flash blocks + containing all 0xff will not be written, since we assume that the EC + uses that pattern for erased blocks + +The CROS_EC node should appear as a subnode of the interrupt that connects it +to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate +the unit address on that bus. + + +Example +======= + + spi@131b0000 { + cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + spi-max-frequency = <5000000>; + ec-interrupt = <&gpio 174 1>; + optimise-flash-write; + status = "disabled"; + }; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/esm-k3.txt b/roms/u-boot/doc/device-tree-bindings/misc/esm-k3.txt new file mode 100644 index 000000000..01c8b6b29 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/esm-k3.txt @@ -0,0 +1,25 @@ +Texas Instruments K3 ESM Binding +====================== + +ESM (Error Signaling Module) is an IP block on TI K3 devices that allows +handling of safety events somewhat similar to what interrupt controller +would do. The safety signals have their separate paths within the SoC, +and they are handled by the ESM, which routes them to the proper +destination, which can be system reset, interrupt controller, etc. In +the simplest configuration the signals are just routed to reset the +SoC. + +Required properties : +- compatible : "ti,j721e-esm" +- ti,esm-pins : integer array of esm events IDs to route to external event + pin which can be used to reset the SoC. The array can + have arbitrary amount of event IDs listed on it. + +Example +======= + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <344>, <345>; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/esm-pmic.txt b/roms/u-boot/doc/device-tree-bindings/misc/esm-pmic.txt new file mode 100644 index 000000000..a60ad7467 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/esm-pmic.txt @@ -0,0 +1,19 @@ +PMIC ESM Binding +====================== + +Certain Power Management ICs contain safety handling logic within them, +allowing automatic reset of the board in case a safety error is signaled. +For this purpose, ESM (Error Signal Monitor) is implemented within +the PMIC running its own state machine. + +Required properties : +- compatible : "ti,tps659413-esm" + +Example +======= + +&tps659413a { + esm: esm { + compatible = "ti,tps659413-esm"; + }; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/fs_loader.txt b/roms/u-boot/doc/device-tree-bindings/misc/fs_loader.txt new file mode 100644 index 000000000..884fbf47c --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/fs_loader.txt @@ -0,0 +1,48 @@ +* File system firmware loader + +Required properties: +-------------------- + +- compatible: should contain "u-boot,fs-loader" +- phandlepart: which block storage device and partition the image loading from, + this property is required for mmc, usb and sata. This is unsigned + 32-bit array. For example phandlepart=<&mmc_0 1>, meaning use + that MMC0 node pointer, partition 1. +- mdtpart: which partition of ubi the image loading from, this property is + required for ubi and mounting. +- ubivol: which volume of ubi the image loading from, this property is required + for ubi and mounting. + +Example of storage device and partition search set for mmc, usb, sata and +ubi in device tree source as shown in below: + + Example of storage type and device partition search set for mmc, usb, + sata and ubi as shown in below: + Example for mmc: + fs_loader0: fs-loader@0 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&mmc_0 1>; + }; + + Example for usb: + fs_loader1: fs-loader@1 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&usb0 1>; + }; + + Example for sata: + fs_loader2: fs-loader@2 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&sata0 1>; + }; + + Example for ubi: + fs_loader3: fs-loader@3 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + mtdpart = "UBI", + ubivol = "ubi0"; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/roms/u-boot/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt new file mode 100644 index 000000000..929ae88c5 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -0,0 +1,155 @@ +Intel Bay Trail FSP UPD Binding +=============================== + +The device tree node which describes the overriding of the Intel Bay Trail FSP +UPD data for configuring the SoC. + +All properties can be found within the `upd-region` struct in +arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in +Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties +is matched up to Intel's E3800 FSPv4 release. + +# Boolean properties: + +- fsp,enable-sdio +- fsp,enable-sdcard +- fsp,enable-hsuart0 +- fsp,enable-hsuart1 +- fsp,enable-spi +- fsp,enable-sata +- fsp,enable-azalia +- fsp,enable-xhci +- fsp,enable-dma0 +- fsp,enable-dma1 +- fsp,enable-i2-c0 +- fsp,enable-i2-c1 +- fsp,enable-i2-c2 +- fsp,enable-i2-c3 +- fsp,enable-i2-c4 +- fsp,enable-i2-c5 +- fsp,enable-i2-c6 +- fsp,enable-pwm0 +- fsp,enable-pwm1 +- fsp,enable-hsi +- fsp,mrc-debug-msg +- fsp,isp-enable +- fsp,igd-render-standby +- fsp,txe-uma-enable +- fsp,emmc45-ddr50-enabled +- fsp,emmc45-hs200-enabled +- fsp,enable-igd +- fsp,enable-memory-down + +If you set "fsp,enable-memory-down" you are strongly encouraged to provide an +"fsp,memory-down-params{};" to specify how your memory is configured. If you +do not set "fsp,enable-memory-down", then the DIMM SPD information will be +discovered by the FSP and used to setup main memory. + + +# Integer properties: + +- fsp,mrc-init-tseg-size +- fsp,mrc-init-mmio-size +- fsp,mrc-init-spd-addr1 +- fsp,mrc-init-spd-addr2 +- fsp,emmc-boot-mode +- fsp,sata-mode +- fsp,lpe-mode +- fsp,lpss-sio-mode +- fsp,igd-dvmt50-pre-alloc +- fsp,aperture-size +- fsp,gtt-size +- fsp,scc-mode +- fsp,os-selection +- fsp,emmc45-retune-timer-value + +- fsp,memory-down-params { + + # Boolean properties: + + - fsp,dimm-0-enable + - fsp,dimm-1-enable + + # Integer properties: + + - fsp,dram-speed + - fsp,dram-type + - fsp,dimm-width + - fsp,dimm-density + - fsp,dimm-bus-width + - fsp,dimm-sides + - fsp,dimm-tcl + - fsp,dimm-trpt-rcd + - fsp,dimm-twr + - fsp,dimm-twtr + - fsp,dimm-trrd + - fsp,dimm-trtp + - fsp,dimm-tfaw +}; + +For all integer properties, available options are listed in fsp_configs.h in +arch/x86/include/asm/arch-baytrail/fsp directory (eg: MRC_INIT_TSEG_SIZE_1MB). + + +Example (from MinnowMax Dual Core): +----------------------------------- + +/ { + ... + + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>; + fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-hsuart1; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <SATA_MODE_AHCI>; + fsp,lpe-mode = <LPE_MODE_PCI>; + fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>; + fsp,aperture-size = <APERTURE_SIZE_256MB>; + fsp,gtt-size = <GTT_SIZE_2MB>; + fsp,scc-mode = <SCC_MODE_PCI>; + fsp,os-selection = <OS_SELECTION_LINUX>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + fsp,enable-memory-down; + fsp,memory-down-params { + compatible = "intel,baytrail-fsp-mdp"; + fsp,dram-speed = <DRAM_SPEED_1066MTS>; + fsp,dram-type = <DRAM_TYPE_DDR3L>; + fsp,dimm-0-enable; + fsp,dimm-width = <DIMM_WIDTH_X16>; + fsp,dimm-density = <DIMM_DENSITY_4GBIT>; + fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>; + fsp,dimm-sides = <DIMM_SIDES_1RANKS>; + fsp,dimm-tcl = <0xb>; + fsp,dimm-trpt-rcd = <0xb>; + fsp,dimm-twr = <0xc>; + fsp,dimm-twtr = <6>; + fsp,dimm-trrd = <6>; + fsp,dimm-trtp = <6>; + fsp,dimm-tfaw = <0x14>; + }; + }; + + ... +}; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/intel,irq-router.txt b/roms/u-boot/doc/device-tree-bindings/misc/intel,irq-router.txt new file mode 100644 index 000000000..09e97b430 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/intel,irq-router.txt @@ -0,0 +1,61 @@ +Intel Interrupt Router Device Binding +===================================== + +The device tree node which describes the operation of the Intel Interrupt Router +device is as follows: + +Required properties : +- reg : Specifies the interrupt router's PCI configuration space address as + defined by the Open Firmware spec. +- compatible = "intel,irq-router" +- intel,pirq-config : Specifies the IRQ routing register programming mechanism. + Valid values are: + "pci": IRQ routing is controlled by PCI configuration registers + "ibase": IRQ routing is in the memory-mapped IBASE register block +- intel,ibase-offset : IBASE register offset in the interrupt router's PCI + configuration space, required only if intel,pirq-config = "ibase". +- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must + be specified. The 8-bit ACTL register is seen on ICH series chipset, like + ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register. +- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either + in the interrupt router's PCI configuration space, or IBASE. +- intel,pirq-link : Specifies the PIRQ link information with two cells. The + first cell is the register offset that controls the first PIRQ link routing. + The second cell is the total number of PIRQ links the router supports. +- intel,pirq-regmap : Specifies PIRQ routing register offset of all PIRQ links, + encoded as 2 cells a group for each link. The first cell is the PIRQ link + number (0 for PIRQA, 1 for PIRQB, etc). The second cell is the PIRQ routing + register offset from the interrupt router's base address. If this property + is omitted, it indicates a consecutive register offset from the first PIRQ + link, as specified by the first cell of intel,pirq-link. +- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the + 8259 PIC. Bit N is 1 means IRQ N is available to be routed. +- intel,pirq-routing : Specifies all PCI devices' IRQ routing information, + encoded as 3 cells a group for a device. The first cell is the device's PCI + bus number, device number and function number encoding with PCI_BDF() macro. + The second cell is the PCI interrupt pin used by this device. The last cell + is which PIRQ line the PCI interrupt pin is routed to. + + +Example +------- + +#include <dt-bindings/interrupt-router/intel-irq.h> + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0xdef8>; + intel,pirq-routing = < + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQB + PCI_BDF(0, 8, 0) INTA PIRQC + PCI_BDF(0, 8, 1) INTB PIRQD + PCI_BDF(1, 6, 0) INTA PIRQE + PCI_BDF(1, 6, 1) INTB PIRQF + PCI_BDF(1, 6, 2) INTC PIRQG + PCI_BDF(1, 6, 3) INTD PIRQH + >; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/intel-lpc.txt b/roms/u-boot/doc/device-tree-bindings/misc/intel-lpc.txt new file mode 100644 index 000000000..ba6ca9dbc --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/intel-lpc.txt @@ -0,0 +1,64 @@ +Intel LPC Device Binding +======================== + +The device tree node which describes the operation of the Intel Low Pin +Count device is as follows: + +Required properties : +- compatible = "intel,lpc" +- intel,alt-gp-smi-enable : Enable SMI sources. This cell is written to the + ALT_GP_SMI_EN register +- intel,gen-dec : Specifies the values for the gen-dec registers. Up to four + cell pairs can be provided - the first of each pair is the base address and + the second is the size. These are written into the GENx_DEC registers of + the LPC device +- intel,gpi-routing : Specifies the GPI routing. There are 16 cells, valid + values are: + 0 No effect (default) + 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + 2 SCI (if corresponding GPIO_EN bit is also set) +- intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H, + one cell for each. + 0x00 - 0000 = Reserved + 0x01 - 0001 = Reserved + 0x02 - 0010 = Reserved + 0x03 - 0011 = IRQ3 + 0x04 - 0100 = IRQ4 + 0x05 - 0101 = IRQ5 + 0x06 - 0110 = IRQ6 + 0x07 - 0111 = IRQ7 + 0x08 - 1000 = Reserved + 0x09 - 1001 = IRQ9 + 0x0A - 1010 = IRQ10 + 0x0B - 1011 = IRQ11 + 0x0C - 1100 = IRQ12 + 0x0D - 1101 = Reserved + 0x0E - 1110 = IRQ14 + 0x0F - 1111 = IRQ15 + PIRQ[n]_ROUT[7] - PIRQ Routing Control + 0x80 - The PIRQ is not routed. + + +Example +------- + +lpc { + compatible = "intel,lpc"; + #address-cells = <1>; + #size-cells = <1>; + intel,gen-dec = <0x800 0xfc 0x900 0xfc>; + + intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b + 0x80 0x80 0x80 0x80>; + /* + * GPI routing + * 0 No effect (default) + * 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is + * also set) + * 2 SCI (if corresponding GPIO_EN bit is also set) + */ + intel,gpi-routing = <0 0 0 0 0 0 0 2 + 1 0 0 0 0 0 0 0>; + /* Enable EC SMI source */ + intel,alt-gp-smi-enable = <0x0100>; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt b/roms/u-boot/doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt new file mode 100644 index 000000000..64a9b5b15 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt @@ -0,0 +1,24 @@ +MPC83xx SerDes controller devices + +MPC83xx SoCs contain a built-in SerDes controller that determines which +protocols (SATA, PCI Express, SGMII, ...) are used on the system's serdes lines +and how the lines are configured. + +Required properties: +- compatible: must be "fsl,mpc83xx-serdes" +- reg: must point to the serdes controller's register map +- proto: selects for which protocol the serdes lines are configured. One of + "sata", "pex", "pex-x2", "sgmii" +- serdes-clk: determines the frequency the serdes lines are configured for. One + of 100, 125, 150. +- vdd: determines whether 1.0V core VDD is used or not + +Example: + +SERDES: serdes@e3000 { + reg = <0xe3000 0x200>; + compatible = "fsl,mpc83xx-serdes"; + proto = "pex"; + serdes-clk = <100>; + vdd; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt b/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt new file mode 100644 index 000000000..db2ff8ca1 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt @@ -0,0 +1,20 @@ +gdsys IO endpoint of IHS FPGA devices + +The IO endpoint of IHS FPGA devices is a packet-based transmission interface +that allows interconnected gdsys devices to send and receive data over the +FPGA's main ethernet connection. + +Required properties: +- compatible: must be "gdsys,io-endpoint" +- reg: describes the address and length of the endpoint's register map (within + the FPGA's register space) + +Example: + +fpga0_ep0 { + compatible = "gdsys,io-endpoint"; + reg = <0x020 0x10 + 0x320 0x10 + 0x340 0x10 + 0x360 0x10>; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt b/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt new file mode 100644 index 000000000..acd466fdc --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt @@ -0,0 +1,19 @@ +gdsys IHS FPGA for CON devices + +The gdsys IHS FPGA is the main FPGA on gdsys CON devices. This driver provides +support for enabling and starting the FPGA, as well as verifying working bus +communication. + +Required properties: +- compatible: must be "gdsys,iocon_fpga" +- reset-gpios: List of GPIOs controlling the FPGA's reset +- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is + done + +Example: + +FPGA0 { + compatible = "gdsys,iocon_fpga"; + reset-gpios = <&PPCPCA 26 0>; + done-gpios = <&GPIO_VB0 19 0>; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt b/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt new file mode 100644 index 000000000..819db22bf --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt @@ -0,0 +1,19 @@ +gdsys IHS FPGA for CPU devices + +The gdsys IHS FPGA is the main FPGA on gdsys CPU devices. This driver provides +support for enabling and starting the FPGA, as well as verifying working bus +communication. + +Required properties: +- compatible: must be "gdsys,iocpu_fpga" +- reset-gpios: List of GPIOs controlling the FPGA's reset +- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is + done + +Example: + +FPGA0 { + compatible = "gdsys,iocpu_fpga"; + reset-gpios = <&PPCPCA 26 0>; + done-gpios = <&GPIO_VB0 19 0>; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,soc.txt b/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,soc.txt new file mode 100644 index 000000000..278e935b1 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/misc/misc/gdsys,soc.txt @@ -0,0 +1,16 @@ +gdsys soc bus driver + +This driver provides a simple interface for the busses associated with gdsys +IHS FPGAs. The bus itself contains devices whose register maps are contained +within the FPGA's register space. + +Required properties: +- fpga: A phandle to the controlling IHS FPGA + +Example: + +FPGA0BUS: fpga0bus { + compatible = "gdsys,soc"; + ranges = <0x0 0xe0600000 0x00004000>; + fpga = <&FPGA0>; +}; |