diff options
Diffstat (limited to 'roms/u-boot/doc/device-tree-bindings/usb')
8 files changed, 335 insertions, 0 deletions
diff --git a/roms/u-boot/doc/device-tree-bindings/usb/dwc2.txt b/roms/u-boot/doc/device-tree-bindings/usb/dwc2.txt new file mode 100644 index 000000000..61493f7cb --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/usb/dwc2.txt @@ -0,0 +1,58 @@ +Platform DesignWare HS OTG USB 2.0 controller +----------------------------------------------------- + +Required properties: +- compatible : One of: + - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC. + - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC. + - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc; + - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc; + - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc; + - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; + - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs; + - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; + - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs; + - "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs; + - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs; + - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs; + - snps,dwc2: A generic DWC2 USB controller with default parameters. + - "st,stm32f4x9-fsotg": The DWC2 USB FS/HS controller instance in STM32F4x9 SoCs + configured in FS mode; + - "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs + configured in HS mode; + - "st,stm32f7-hsotg": The DWC2 USB HS controller instance in STM32F7 SoCs + configured in HS mode; +- reg : Should contain 1 register range (address and length) +- interrupts : Should contain 1 interrupt +- clocks: clock provider specifier +- clock-names: shall be "otg" +Refer to clk/clock-bindings.txt for generic clock consumer properties + +Optional properties: +- phys: phy provider specifier +- phy-names: shall be "usb2-phy" +Refer to phy/phy-bindings.txt for generic phy consumer properties +- dr_mode: shall be one of "host", "peripheral" and "otg" + Refer to usb/generic.txt +- g-rx-fifo-size: size of rx fifo size in gadget mode. +- g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode. +- g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode. +- usb33d-supply: external VBUS and ID sensing comparators supply, in order to + perform OTG operation, used on STM32MP1 SoCs. +- u-boot,force-b-session-valid: force B-peripheral session instead of relying on + VBUS sensing (only valid when dr_mode = "peripheral" and for u-boot). + +Deprecated properties: +- g-use-dma: gadget DMA mode is automatically detected + +Example: + + usb@101c0000 { + compatible = "ralink,rt3050-usb, snps,dwc2"; + reg = <0x101c0000 40000>; + interrupts = <18>; + clocks = <&usb_otg_ahb_clk>; + clock-names = "otg"; + phys = <&usbphy>; + phy-names = "usb2-phy"; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/usb/dwc3-st.txt b/roms/u-boot/doc/device-tree-bindings/usb/dwc3-st.txt new file mode 100644 index 000000000..a26a1397e --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/usb/dwc3-st.txt @@ -0,0 +1,60 @@ +ST DWC3 glue logic + +This file documents the parameters for the dwc3-st driver. +This driver controls the glue logic used to configure the dwc3 core on +STiH407 based platforms. + +Required properties: + - compatible : must be "st,stih407-dwc3" + - reg : glue logic base address and USB syscfg ctrl register offset + - reg-names : should be "reg-glue" and "syscfg-reg" + - st,syscon : should be phandle to system configuration node which + encompasses the glue registers + - resets : list of phandle and reset specifier pairs. There should be two entries, one + for the powerdown and softreset lines of the usb3 IP + - reset-names : list of reset signal names. Names should be "powerdown" and "softreset" + + - #address-cells, #size-cells : should be '1' if the device has sub-nodes + with 'reg' property + + - pinctl-names : A pinctrl state named "default" must be defined + + - pinctrl-0 : Pin control group + + - ranges : allows valid 1:1 translation between child's address space and + parent's address space + +Sub-nodes: +The dwc3 core should be added as subnode to ST DWC3 glue as shown in the +example below. + +NB: The dr_mode property is NOT optional for this driver, as the default value +is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are +either "host" or "device". + +Example: + +st_dwc3: dwc3@8f94000 { + status = "disabled"; + compatible = "st,stih407-dwc3"; + reg = <0x08f94000 0x1000>, <0x110 0x4>; + reg-names = "reg-glue", "syscfg-reg"; + st,syscfg = <&syscfg_core>; + resets = <&powerdown STIH407_USB3_POWERDOWN>, + <&softreset STIH407_MIPHY2_SOFTRESET>; + reset-names = "powerdown", "softreset"; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + ranges; + + dwc3: dwc3@9900000 { + compatible = "snps,dwc3"; + reg = <0x09900000 0x100000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; + dr_mode = "host"; + phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>; + }; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/usb/ehci-msm.txt b/roms/u-boot/doc/device-tree-bindings/usb/ehci-msm.txt new file mode 100644 index 000000000..205bb0722 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/usb/ehci-msm.txt @@ -0,0 +1,10 @@ +Chipidea EHCI controller (part of OTG controller) used on Qualcomm devices. + +Required properties: +- compatible: must be "qcom,ehci-host" +- reg: start address and size of the registers + +ehci@78d9000 { + compatible = "qcom,ehci-host"; + reg = <0x78d9000 0x400>; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/usb/generic.txt b/roms/u-boot/doc/device-tree-bindings/usb/generic.txt new file mode 100644 index 000000000..a02a198df --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/usb/generic.txt @@ -0,0 +1,31 @@ +Generic USB Properties + +Optional properties: + - maximum-speed: tells USB controllers we want to work up to a certain + speed. Valid arguments are "super-speed-plus", + "super-speed", "high-speed", "full-speed" and + "low-speed". In case this isn't passed via DT, USB + controllers should default to their maximum HW + capability. + - dr_mode: tells Dual-Role USB controllers that we want to work on a + particular mode. Valid arguments are "host", + "peripheral" and "otg". In case this attribute isn't + passed via DT, USB DRD controllers should default to + OTG. + - phy_type: tells USB controllers that we want to configure the core to support + a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is + selected. Valid arguments are "utmi" and "utmi_wide". + In case this isn't passed via DT, USB controllers should + default to HW capability. + +This is an attribute to a USB controller such as: + +dwc3@4a030000 { + compatible = "synopsys,dwc3"; + reg = <0x4a030000 0xcfff>; + interrupts = <0 92 4> + usb-phy = <&usb2_phy>, <&usb3,phy>; + maximum-speed = "super-speed"; + dr_mode = "otg"; + phy_type = "utmi_wide"; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/usb/marvell.xhci-usb.txt b/roms/u-boot/doc/device-tree-bindings/usb/marvell.xhci-usb.txt new file mode 100644 index 000000000..e042d1b96 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/usb/marvell.xhci-usb.txt @@ -0,0 +1,28 @@ +Marvell SOC USB controllers + +This controller is integrated in Armada 3700/8K. +It uses the same properties as a generic XHCI host controller + +Required properties : + - compatible: should be one or more of: + - "marvell,armada3700-xhci", "generic-xhci" for Armada 37xx SoCs + - "marvell,armada-8k-xhci", "generic-xhci" for Armada A8K SoCs + - reg: should contain address and length of the standard XHCI + register set for the device. + - interrupts: one XHCI interrupt should be described here. + +Optional properties: + - clocks: phandle to system controller clock driving this unit + - vbus-supply : If present, specifies the fixed regulator to be turned on + for providing power to the USB VBUS rail. + +Example: + cpm_usb3_0: usb3@500000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; + reg = <0x500000 0x4000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpm_syscon0 1 22>; + vbus-supply = <®_usb3h0_vbus>; + status = "disabled"; + }; diff --git a/roms/u-boot/doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt b/roms/u-boot/doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt new file mode 100644 index 000000000..2a298f7b1 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt @@ -0,0 +1,44 @@ +MediaTek xHCI + +The device node for USB3 host controller on MediaTek SoCs. + +Required properties: + - compatible : should be "mediatek,mtk-xhci" + - reg : specifies physical base address and size of the registers + - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control + - power-domains : a phandle to USB power domain node to control USB's + MTCMOS + - vusb33-supply : regulator of USB avdd3.3v + + - clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names + - clock-names : must contain + "sys_ck": controller clock used by normal mode, + the following ones are optional: + "ref_ck": reference clock used by low power mode etc, + "mcu_ck": mcu_bus clock for register access, + "dma_ck": dma_bus clock for data transfer by DMA, + "xhci_ck": controller clock + + - phys : list of all the USB PHYs on this HCD + - phy-names: name specifier for the USB PHY + +Optional properties: + - vbus-supply : reference to the VBUS regulator; + - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, + bit1 for u3port1, ... etc; + - mediatek,u2p-dis-msk : mask to disable u2ports, bit0 for u2port0, + bit1 for u2port1, ... etc; + +Example: +xhci: usb@1a0c0000 { + compatible = "mediatek,mt7629-xhci", "mediatek,mtk-xhci"; + reg = <0x1a0c0000 0x1000>, <0x1a0c3e00 0x0100>; + reg-names = "mac", "ippc"; + power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>; + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, <&ssusbsys CLK_SSUSB_REF_EN>, + <&ssusbsys CLK_SSUSB_MCU_EN>, <&ssusbsys CLK_SSUSB_DMA_EN>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/usb/mediatek,mtu3.txt b/roms/u-boot/doc/device-tree-bindings/usb/mediatek,mtu3.txt new file mode 100644 index 000000000..ab877bfa8 --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/usb/mediatek,mtu3.txt @@ -0,0 +1,79 @@ +The device node for Mediatek USB3 DRD controller + +Required properties: + - compatible : should be "mediatek,<soc-model>-mtu3", "mediatek,mtu3", + soc-model is the name of SoC, such as mt8512 etc, + when using "mediatek,mtu3" compatible string, you need SoC specific + ones in addition, one of: + - "mediatek,mt8512-mtu3" + - reg : specifies physical base address and size of the registers + - reg-names: should be + - "ippc" : IP Port Control + - power-domains : a phandle to USB power domain node to control USB's MTCMOS + - clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names + - clock-names : must contain "sys_ck" for clock of controller, + the following clocks are optional: + "ref_ck", "mcu_ck", "dma_ck" and "xhci_ck"; + - phys : list of all the USB PHYs on this HCD + - #address-cells, #size-cells : used for sub-nodes with 'reg' property + - ranges : allows valid 1:1 translation between child's address space and + parent's address space + +Optional properties: + - vusb33-supply : regulator of USB AVDD3.3v + - vbus-supply : regulator of VBUS 5v, needed when supports host mode. + +Sub-nodes: +Required properties: + - compatible : should be "mediatek,ssusb" + - reg : specifies physical base address and size of the registers + - reg-names: should be + - "mac" : SSUSB MAC, include xHCI and device + - interrupts : interrupt used by xHCI or device + - dr_mode : should be one of "host" or "peripheral", + see : usb/generic.txt + +Optional properties: + - pinctrl-names : a pinctrl state named "default" is optional + - pinctrl-0 : pin control group + See: pinctrl/pinctrl-bindings.txt + + - device mode: + - maximum-speed : valid arguments are "full-speed", "high-speed", + "super-speed" and "super-speed-plus", + see: usb/generic.txt + - mediatek,force-vbus : force vbus as valid by SW + + - host mode (dr_mode is "host"): + - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, + bit1 for u3port1, ... etc; + +Example: +usb3: usb@11213e00 { + compatible = "mediatek,mt8512-mtu3", "mediatek,mtu3"; + reg = <0x11213e00 0x0100>; + reg-names = "ippc"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u2port1 PHY_TYPE_USB2>; + power-domains = <&scpsys MT8512_POWER_DOMAIN_USB>; + clocks = <&infracfg CLK_INFRA_USB_SYS>, + <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_INFRA_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + vusb33-supply = <reg_3p3v>; + vbus-supply = <&usb_p0_vbus>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + ssusb: usb@11210000 { + compatible = "mediatek,ssusb"; + reg = <0x11210000 0x3e00>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; + reg-names = "mac"; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + status = "disabled"; + }; +}; diff --git a/roms/u-boot/doc/device-tree-bindings/usb/tegra-usb.txt b/roms/u-boot/doc/device-tree-bindings/usb/tegra-usb.txt new file mode 100644 index 000000000..5282d44ac --- /dev/null +++ b/roms/u-boot/doc/device-tree-bindings/usb/tegra-usb.txt @@ -0,0 +1,25 @@ +Tegra SOC USB controllers + +The device node for a USB controller that is part of a Tegra +SOC is as described in the document "Open Firmware Recommended +Practice : Universal Serial Bus" with the following modifications +and additions : + +Required properties : + - compatible : Should be "nvidia,tegra20-ehci" for USB controllers + used in host mode. + - phy_type : Should be one of "ulpi" or "utmi". + - nvidia,vbus-gpio : If present, specifies a gpio that needs to be + activated for the bus to be powered. + +Optional properties: + - dr_mode : dual role mode. Indicates the working mode for + nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", + or "otg". Default to "host" if not defined for backward compatibility. + host means this is a host controller + peripheral means it is device controller + otg means it can operate as either ("on the go") + - nvidia,has-legacy-mode : boolean indicates whether this controller can + operate in legacy mode (as APX 2500 / 2600). In legacy mode some + registers are accessed through the APB_MISC base address instead of + the USB controller. |