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-rw-r--r--roms/u-boot/drivers/pinctrl/mscc/Kconfig50
-rw-r--r--roms/u-boot/drivers/pinctrl/mscc/Makefile8
-rw-r--r--roms/u-boot/drivers/pinctrl/mscc/mscc-common.c277
-rw-r--r--roms/u-boot/drivers/pinctrl/mscc/mscc-common.h66
-rw-r--r--roms/u-boot/drivers/pinctrl/mscc/pinctrl-jr2.c323
-rw-r--r--roms/u-boot/drivers/pinctrl/mscc/pinctrl-luton.c186
-rw-r--r--roms/u-boot/drivers/pinctrl/mscc/pinctrl-ocelot.c202
-rw-r--r--roms/u-boot/drivers/pinctrl/mscc/pinctrl-serval.c233
-rw-r--r--roms/u-boot/drivers/pinctrl/mscc/pinctrl-servalt.c269
9 files changed, 1614 insertions, 0 deletions
diff --git a/roms/u-boot/drivers/pinctrl/mscc/Kconfig b/roms/u-boot/drivers/pinctrl/mscc/Kconfig
new file mode 100644
index 000000000..aab67fabd
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/mscc/Kconfig
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config PINCTRL_MSCC
+ bool
+
+config PINCTRL_MSCC_OCELOT
+ depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi ocelot family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi ocelot SoCs.
+
+config PINCTRL_MSCC_LUTON
+ depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi luton family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi luton SoCs.
+
+config PINCTRL_MSCC_JR2
+ depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi jr2 family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi jr2 SoCs.
+
+config PINCTRL_MSCC_SERVALT
+ depends on SOC_SERVALT && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi servalt family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi servalt SoCs.
+
+config PINCTRL_MSCC_SERVAL
+ depends on SOC_SERVAL && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi serval family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi serval SoCs.
+
diff --git a/roms/u-boot/drivers/pinctrl/mscc/Makefile b/roms/u-boot/drivers/pinctrl/mscc/Makefile
new file mode 100644
index 000000000..fd7eba2a0
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/mscc/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-y += mscc-common.o
+obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
+obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
+obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
+obj-$(CONFIG_PINCTRL_MSCC_SERVALT) += pinctrl-servalt.o
+obj-$(CONFIG_PINCTRL_MSCC_SERVAL) += pinctrl-serval.o
diff --git a/roms/u-boot/drivers/pinctrl/mscc/mscc-common.c b/roms/u-boot/drivers/pinctrl/mscc/mscc-common.c
new file mode 100644
index 000000000..307ed1db8
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/mscc/mscc-common.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <alexandre.belloni@free-electrons.com>
+ * Author: <gregory.clement@bootlin.com>
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include "mscc-common.h"
+
+static void mscc_writel(unsigned int offset, void *addr)
+{
+ if (offset < 32)
+ writel(BIT(offset), addr);
+ else
+ writel(BIT(offset % 32), addr + 4);
+}
+
+static unsigned int mscc_readl(unsigned int offset, void *addr)
+{
+ if (offset < 32)
+ return readl(addr);
+ else
+ return readl(addr + 4);
+}
+
+static void mscc_setbits(unsigned int offset, void *addr)
+{
+ if (offset < 32)
+ writel(readl(addr) | BIT(offset), addr);
+ else
+ writel(readl(addr + 4) | BIT(offset % 32), addr + 4);
+}
+
+static void mscc_clrbits(unsigned int offset, void *addr)
+{
+ if (offset < 32)
+ writel(readl(addr) & ~BIT(offset), addr);
+ else
+ writel(readl(addr + 4) & ~BIT(offset % 32), addr + 4);
+}
+
+static int mscc_get_functions_count(struct udevice *dev)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->num_func;
+}
+
+static const char *mscc_get_function_name(struct udevice *dev,
+ unsigned int function)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->function_names[function];
+}
+
+static int mscc_pin_function_idx(unsigned int pin, unsigned int function,
+ const struct mscc_pin_data *mscc_pins)
+{
+ struct mscc_pin_caps *p = mscc_pins[pin].drv_data;
+ int i;
+
+ for (i = 0; i < MSCC_FUNC_PER_PIN; i++) {
+ if (function == p->functions[i])
+ return i;
+ }
+
+ return -1;
+}
+
+static int mscc_pinmux_set_mux(struct udevice *dev,
+ unsigned int pin_selector, unsigned int selector)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+ struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data;
+ int f, offset, regoff;
+
+ f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins);
+ if (f < 0)
+ return -EINVAL;
+ /*
+ * f is encoded on two bits.
+ * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
+ * ALT1
+ * This is racy because both registers can't be updated at the same time
+ * but it doesn't matter much for now.
+ */
+ offset = pin->pin;
+ regoff = info->mscc_gpios[MSCC_GPIO_ALT0];
+ if (offset >= 32) {
+ offset = offset % 32;
+ regoff = info->mscc_gpios[MSCC_GPIO_ALT1];
+ }
+
+ if (f & BIT(0))
+ mscc_setbits(offset, info->regs + regoff);
+ else
+ mscc_clrbits(offset, info->regs + regoff);
+
+ if (f & BIT(1))
+ mscc_setbits(offset, info->regs + regoff + 4);
+ else
+ mscc_clrbits(offset, info->regs + regoff + 4);
+
+ return 0;
+}
+
+static int mscc_pctl_get_groups_count(struct udevice *dev)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->num_pins;
+}
+
+static const char *mscc_pctl_get_group_name(struct udevice *dev,
+ unsigned int group)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->mscc_pins[group].name;
+}
+
+static int mscc_create_group_func_map(struct udevice *dev,
+ struct mscc_pinctrl *info)
+{
+ u16 pins[info->num_pins];
+ int f, npins, i;
+
+ for (f = 0; f < info->num_func; f++) {
+ for (npins = 0, i = 0; i < info->num_pins; i++) {
+ if (mscc_pin_function_idx(i, f, info->mscc_pins) >= 0)
+ pins[npins++] = i;
+ }
+
+ info->func[f].ngroups = npins;
+ info->func[f].groups = devm_kzalloc(dev, npins * sizeof(char *),
+ GFP_KERNEL);
+ if (!info->func[f].groups)
+ return -ENOMEM;
+
+ for (i = 0; i < npins; i++)
+ info->func[f].groups[i] = info->mscc_pins[pins[i]].name;
+ }
+
+ return 0;
+}
+
+static int mscc_pinctrl_register(struct udevice *dev, struct mscc_pinctrl *info)
+{
+ int ret;
+
+ ret = mscc_create_group_func_map(dev, info);
+ if (ret) {
+ dev_err(dev, "Unable to create group func map.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mscc_gpio_get(struct udevice *dev, unsigned int offset)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev->parent);
+ unsigned int val;
+
+ if (mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]) &
+ BIT(offset % 32))
+ val = mscc_readl(offset,
+ info->regs + info->mscc_gpios[MSCC_GPIO_OUT]);
+ else
+ val = mscc_readl(offset,
+ info->regs + info->mscc_gpios[MSCC_GPIO_IN]);
+
+ return !!(val & BIT(offset % 32));
+}
+
+static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev->parent);
+
+ if (value)
+ mscc_writel(offset,
+ info->regs + info->mscc_gpios[MSCC_GPIO_OUT_SET]);
+ else
+ mscc_writel(offset,
+ info->regs + info->mscc_gpios[MSCC_GPIO_OUT_CLR]);
+
+ return 0;
+}
+
+static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev->parent);
+ unsigned int val;
+
+ val = mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
+
+ return (val & BIT(offset % 32)) ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev->parent);
+
+ mscc_clrbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
+
+ return 0;
+}
+
+static int mscc_gpio_direction_output(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev->parent);
+
+ mscc_setbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
+
+ return mscc_gpio_set(dev, offset, value);
+}
+
+const struct dm_gpio_ops mscc_gpio_ops = {
+ .set_value = mscc_gpio_set,
+ .get_value = mscc_gpio_get,
+ .get_function = mscc_gpio_get_direction,
+ .direction_input = mscc_gpio_direction_input,
+ .direction_output = mscc_gpio_direction_output,
+};
+
+const struct pinctrl_ops mscc_pinctrl_ops = {
+ .get_pins_count = mscc_pctl_get_groups_count,
+ .get_pin_name = mscc_pctl_get_group_name,
+ .get_functions_count = mscc_get_functions_count,
+ .get_function_name = mscc_get_function_name,
+ .pinmux_set = mscc_pinmux_set_mux,
+ .set_state = pinctrl_generic_set_state,
+};
+
+int mscc_pinctrl_probe(struct udevice *dev, int num_func,
+ const struct mscc_pin_data *mscc_pins, int num_pins,
+ char * const *function_names,
+ const unsigned long *mscc_gpios)
+{
+ struct mscc_pinctrl *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->regs = dev_remap_addr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+ priv->func = devm_kzalloc(dev, num_func * sizeof(struct mscc_pmx_func),
+ GFP_KERNEL);
+ priv->num_func = num_func;
+ priv->mscc_pins = mscc_pins;
+ priv->num_pins = num_pins;
+ priv->function_names = function_names;
+ priv->mscc_gpios = mscc_gpios;
+ ret = mscc_pinctrl_register(dev, priv);
+
+ return ret;
+}
diff --git a/roms/u-boot/drivers/pinctrl/mscc/mscc-common.h b/roms/u-boot/drivers/pinctrl/mscc/mscc-common.h
new file mode 100644
index 000000000..3c5c1faf8
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/mscc/mscc-common.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <alexandre.belloni@free-electrons.com>
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#define MSCC_FUNC_PER_PIN 4
+
+enum mscc_regs_gpio {
+ MSCC_GPIO_OUT_SET,
+ MSCC_GPIO_OUT_CLR,
+ MSCC_GPIO_OUT,
+ MSCC_GPIO_IN,
+ MSCC_GPIO_OE,
+ MSCC_GPIO_INTR,
+ MSCC_GPIO_INTR_ENA,
+ MSCC_GPIO_INTR_IDENT,
+ MSCC_GPIO_ALT0,
+ MSCC_GPIO_ALT1,
+};
+
+struct mscc_pin_caps {
+ unsigned int pin;
+ unsigned char functions[MSCC_FUNC_PER_PIN];
+};
+
+struct mscc_pin_data {
+ const char *name;
+ struct mscc_pin_caps *drv_data;
+};
+
+#define MSCC_P(p, f0, f1, f2) \
+static struct mscc_pin_caps mscc_pin_##p = { \
+ .pin = p, \
+ .functions = { \
+ FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
+ }, \
+}
+
+struct mscc_pmx_func {
+ const char **groups;
+ unsigned int ngroups;
+};
+
+struct mscc_pinctrl {
+ struct udevice *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *regs;
+ struct mscc_pmx_func *func;
+ int num_func;
+ const struct mscc_pin_data *mscc_pins;
+ int num_pins;
+ char * const *function_names;
+ const unsigned long *mscc_gpios;
+};
+
+int mscc_pinctrl_probe(struct udevice *dev, int num_func,
+ const struct mscc_pin_data *mscc_pins, int num_pins,
+ char * const *function_names,
+ const unsigned long *mscc_gpios);
+const struct pinctrl_ops mscc_pinctrl_ops;
+
+const struct dm_gpio_ops mscc_gpio_ops;
diff --git a/roms/u-boot/drivers/pinctrl/mscc/pinctrl-jr2.c b/roms/u-boot/drivers/pinctrl/mscc/pinctrl-jr2.c
new file mode 100644
index 000000000..cb340581c
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/mscc/pinctrl-jr2.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <horatiu.vultur@microchip.com>
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_IRQ0_IN,
+ FUNC_IRQ0_OUT,
+ FUNC_IRQ1_IN,
+ FUNC_IRQ1_OUT,
+ FUNC_MIIM1,
+ FUNC_MIIM2,
+ FUNC_PCI_WAKE,
+ FUNC_PTP0,
+ FUNC_PTP1,
+ FUNC_PTP2,
+ FUNC_PTP3,
+ FUNC_PWM,
+ FUNC_RECO_CLK0,
+ FUNC_RECO_CLK1,
+ FUNC_SFP0,
+ FUNC_SFP1,
+ FUNC_SFP2,
+ FUNC_SFP3,
+ FUNC_SFP4,
+ FUNC_SFP5,
+ FUNC_SFP6,
+ FUNC_SFP7,
+ FUNC_SFP8,
+ FUNC_SFP9,
+ FUNC_SFP10,
+ FUNC_SFP11,
+ FUNC_SFP12,
+ FUNC_SFP13,
+ FUNC_SFP14,
+ FUNC_SFP15,
+ FUNC_SG0,
+ FUNC_SG1,
+ FUNC_SG2,
+ FUNC_SI,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_TWI2,
+ FUNC_TWI_SCL_M,
+ FUNC_UART,
+ FUNC_UART2,
+ FUNC_MAX
+};
+
+static char * const jr2_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0_IN] = "irq0_in",
+ [FUNC_IRQ0_OUT] = "irq0_out",
+ [FUNC_IRQ1_IN] = "irq1_in",
+ [FUNC_IRQ1_OUT] = "irq1_out",
+ [FUNC_MIIM1] = "miim1",
+ [FUNC_MIIM2] = "miim2",
+ [FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_PTP0] = "ptp0",
+ [FUNC_PTP1] = "ptp1",
+ [FUNC_PTP2] = "ptp2",
+ [FUNC_PTP3] = "ptp3",
+ [FUNC_PWM] = "pwm",
+ [FUNC_RECO_CLK0] = "reco_clk0",
+ [FUNC_RECO_CLK1] = "reco_clk1",
+ [FUNC_SFP0] = "sfp0",
+ [FUNC_SFP1] = "sfp1",
+ [FUNC_SFP2] = "sfp2",
+ [FUNC_SFP3] = "sfp3",
+ [FUNC_SFP4] = "sfp4",
+ [FUNC_SFP5] = "sfp5",
+ [FUNC_SFP6] = "sfp6",
+ [FUNC_SFP7] = "sfp7",
+ [FUNC_SFP8] = "sfp8",
+ [FUNC_SFP9] = "sfp9",
+ [FUNC_SFP10] = "sfp10",
+ [FUNC_SFP11] = "sfp11",
+ [FUNC_SFP12] = "sfp12",
+ [FUNC_SFP13] = "sfp13",
+ [FUNC_SFP14] = "sfp14",
+ [FUNC_SFP15] = "sfp15",
+ [FUNC_SG0] = "sg0",
+ [FUNC_SG1] = "sg1",
+ [FUNC_SG2] = "sg2",
+ [FUNC_SI] = "si",
+ [FUNC_TACHO] = "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_TWI2] = "twi2",
+ [FUNC_TWI_SCL_M] = "twi_scl_m",
+ [FUNC_UART] = "uart",
+ [FUNC_UART2] = "uart2",
+};
+
+#define JR2_P(p, f0, f1) \
+static struct mscc_pin_caps jr2_pin_##p = { \
+ .pin = p, \
+ .functions = { \
+ FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
+ }, \
+}
+
+JR2_P(0, SG0, NONE);
+JR2_P(1, SG0, NONE);
+JR2_P(2, SG0, NONE);
+JR2_P(3, SG0, NONE);
+JR2_P(4, SG1, NONE);
+JR2_P(5, SG1, NONE);
+JR2_P(6, IRQ0_IN, IRQ0_OUT);
+JR2_P(7, IRQ1_IN, IRQ1_OUT);
+JR2_P(8, PTP0, NONE);
+JR2_P(9, PTP1, NONE);
+JR2_P(10, UART, NONE);
+JR2_P(11, UART, NONE);
+JR2_P(12, SG1, NONE);
+JR2_P(13, SG1, NONE);
+JR2_P(14, TWI, TWI_SCL_M);
+JR2_P(15, TWI, NONE);
+JR2_P(16, SI, TWI_SCL_M);
+JR2_P(17, SI, TWI_SCL_M);
+JR2_P(18, SI, TWI_SCL_M);
+JR2_P(19, PCI_WAKE, NONE);
+JR2_P(20, IRQ0_OUT, TWI_SCL_M);
+JR2_P(21, IRQ1_OUT, TWI_SCL_M);
+JR2_P(22, TACHO, NONE);
+JR2_P(23, PWM, NONE);
+JR2_P(24, UART2, NONE);
+JR2_P(25, UART2, SI);
+JR2_P(26, PTP2, SI);
+JR2_P(27, PTP3, SI);
+JR2_P(28, TWI2, SI);
+JR2_P(29, TWI, SI);
+JR2_P(30, SG2, SI);
+JR2_P(31, SG2, SI);
+JR2_P(32, SG2, SI);
+JR2_P(33, SG2, SI);
+JR2_P(34, NONE, TWI_SCL_M);
+JR2_P(35, NONE, TWI_SCL_M);
+JR2_P(36, NONE, TWI_SCL_M);
+JR2_P(37, NONE, TWI_SCL_M);
+JR2_P(38, NONE, TWI_SCL_M);
+JR2_P(39, NONE, TWI_SCL_M);
+JR2_P(40, NONE, TWI_SCL_M);
+JR2_P(41, NONE, TWI_SCL_M);
+JR2_P(42, NONE, TWI_SCL_M);
+JR2_P(43, NONE, TWI_SCL_M);
+JR2_P(44, NONE, SFP8);
+JR2_P(45, NONE, SFP9);
+JR2_P(46, NONE, SFP10);
+JR2_P(47, NONE, SFP11);
+JR2_P(48, SFP0, NONE);
+JR2_P(49, SFP1, SI);
+JR2_P(50, SFP2, SI);
+JR2_P(51, SFP3, SI);
+JR2_P(52, SFP4, NONE);
+JR2_P(53, SFP5, NONE);
+JR2_P(54, SFP6, NONE);
+JR2_P(55, SFP7, NONE);
+JR2_P(56, MIIM1, SFP12);
+JR2_P(57, MIIM1, SFP13);
+JR2_P(58, MIIM2, SFP14);
+JR2_P(59, MIIM2, SFP15);
+JR2_P(60, NONE, NONE);
+JR2_P(61, NONE, NONE);
+JR2_P(62, NONE, NONE);
+JR2_P(63, NONE, NONE);
+
+#define JR2_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &jr2_pin_##n \
+}
+
+static const struct mscc_pin_data jr2_pins[] = {
+ JR2_PIN(0),
+ JR2_PIN(1),
+ JR2_PIN(2),
+ JR2_PIN(3),
+ JR2_PIN(4),
+ JR2_PIN(5),
+ JR2_PIN(6),
+ JR2_PIN(7),
+ JR2_PIN(8),
+ JR2_PIN(9),
+ JR2_PIN(10),
+ JR2_PIN(11),
+ JR2_PIN(12),
+ JR2_PIN(13),
+ JR2_PIN(14),
+ JR2_PIN(15),
+ JR2_PIN(16),
+ JR2_PIN(17),
+ JR2_PIN(18),
+ JR2_PIN(19),
+ JR2_PIN(20),
+ JR2_PIN(21),
+ JR2_PIN(22),
+ JR2_PIN(23),
+ JR2_PIN(24),
+ JR2_PIN(25),
+ JR2_PIN(26),
+ JR2_PIN(27),
+ JR2_PIN(28),
+ JR2_PIN(29),
+ JR2_PIN(30),
+ JR2_PIN(31),
+ JR2_PIN(32),
+ JR2_PIN(33),
+ JR2_PIN(34),
+ JR2_PIN(35),
+ JR2_PIN(36),
+ JR2_PIN(37),
+ JR2_PIN(38),
+ JR2_PIN(39),
+ JR2_PIN(40),
+ JR2_PIN(41),
+ JR2_PIN(42),
+ JR2_PIN(43),
+ JR2_PIN(44),
+ JR2_PIN(45),
+ JR2_PIN(46),
+ JR2_PIN(47),
+ JR2_PIN(48),
+ JR2_PIN(49),
+ JR2_PIN(50),
+ JR2_PIN(51),
+ JR2_PIN(52),
+ JR2_PIN(53),
+ JR2_PIN(54),
+ JR2_PIN(55),
+ JR2_PIN(56),
+ JR2_PIN(57),
+ JR2_PIN(58),
+ JR2_PIN(59),
+ JR2_PIN(60),
+ JR2_PIN(61),
+ JR2_PIN(62),
+ JR2_PIN(63),
+};
+
+static const unsigned long jr2_gpios[] = {
+ [MSCC_GPIO_OUT_SET] = 0x00,
+ [MSCC_GPIO_OUT_CLR] = 0x08,
+ [MSCC_GPIO_OUT] = 0x10,
+ [MSCC_GPIO_IN] = 0x18,
+ [MSCC_GPIO_OE] = 0x20,
+ [MSCC_GPIO_INTR] = 0x28,
+ [MSCC_GPIO_INTR_ENA] = 0x30,
+ [MSCC_GPIO_INTR_IDENT] = 0x38,
+ [MSCC_GPIO_ALT0] = 0x40,
+ [MSCC_GPIO_ALT1] = 0x48,
+};
+
+static int jr2_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "jr2-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(jr2_pins);
+
+ return 0;
+}
+
+static struct driver jr2_gpio_driver = {
+ .name = "jr2-gpio",
+ .id = UCLASS_GPIO,
+ .probe = jr2_gpio_probe,
+ .ops = &mscc_gpio_ops,
+};
+
+static int jr2_pinctrl_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = mscc_pinctrl_probe(dev, FUNC_MAX, jr2_pins,
+ ARRAY_SIZE(jr2_pins),
+ jr2_function_names,
+ jr2_gpios);
+
+ if (ret)
+ return ret;
+
+ ret = device_bind(dev, &jr2_gpio_driver, "jr2-gpio", NULL,
+ dev_ofnode(dev), NULL);
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id jr2_pinctrl_of_match[] = {
+ { .compatible = "mscc,jaguar2-pinctrl" },
+ {},
+};
+
+U_BOOT_DRIVER(jr2_pinctrl) = {
+ .name = "jr2-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(jr2_pinctrl_of_match),
+ .probe = jr2_pinctrl_probe,
+ .priv_auto = sizeof(struct mscc_pinctrl),
+ .ops = &mscc_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/mscc/pinctrl-luton.c b/roms/u-boot/drivers/pinctrl/mscc/pinctrl-luton.c
new file mode 100644
index 000000000..325c9a970
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/mscc/pinctrl-luton.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <gregory.clement@bootlin.com>
+ * License: Dual MIT/GPL
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_SIO,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_PHY_LED,
+ FUNC_EXT_IRQ,
+ FUNC_SFP,
+ FUNC_SI,
+ FUNC_PWM,
+ FUNC_UART,
+ FUNC_MAX
+};
+
+static char * const luton_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_SIO] = "sio",
+ [FUNC_TACHO] = "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_PHY_LED] = "phy_led",
+ [FUNC_EXT_IRQ] = "ext_irq",
+ [FUNC_SFP] = "sfp",
+ [FUNC_SI] = "si",
+ [FUNC_PWM] = "pwm",
+ [FUNC_UART] = "uart",
+};
+
+MSCC_P(0, SIO, NONE, NONE);
+MSCC_P(1, SIO, NONE, NONE);
+MSCC_P(2, SIO, NONE, NONE);
+MSCC_P(3, SIO, NONE, NONE);
+MSCC_P(4, TACHO, NONE, NONE);
+MSCC_P(5, TWI, PHY_LED, NONE);
+MSCC_P(6, TWI, PHY_LED, NONE);
+MSCC_P(7, NONE, PHY_LED, NONE);
+MSCC_P(8, EXT_IRQ, PHY_LED, NONE);
+MSCC_P(9, EXT_IRQ, PHY_LED, NONE);
+MSCC_P(10, SFP, PHY_LED, NONE);
+MSCC_P(11, SFP, PHY_LED, NONE);
+MSCC_P(12, SFP, PHY_LED, NONE);
+MSCC_P(13, SFP, PHY_LED, NONE);
+MSCC_P(14, SI, PHY_LED, NONE);
+MSCC_P(15, SI, PHY_LED, NONE);
+MSCC_P(16, SI, PHY_LED, NONE);
+MSCC_P(17, SFP, PHY_LED, NONE);
+MSCC_P(18, SFP, PHY_LED, NONE);
+MSCC_P(19, SFP, PHY_LED, NONE);
+MSCC_P(20, SFP, PHY_LED, NONE);
+MSCC_P(21, SFP, PHY_LED, NONE);
+MSCC_P(22, SFP, PHY_LED, NONE);
+MSCC_P(23, SFP, PHY_LED, NONE);
+MSCC_P(24, SFP, PHY_LED, NONE);
+MSCC_P(25, SFP, PHY_LED, NONE);
+MSCC_P(26, SFP, PHY_LED, NONE);
+MSCC_P(27, SFP, PHY_LED, NONE);
+MSCC_P(28, SFP, PHY_LED, NONE);
+MSCC_P(29, PWM, NONE, NONE);
+MSCC_P(30, UART, NONE, NONE);
+MSCC_P(31, UART, NONE, NONE);
+
+#define LUTON_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &mscc_pin_##n \
+}
+
+static const struct mscc_pin_data luton_pins[] = {
+ LUTON_PIN(0),
+ LUTON_PIN(1),
+ LUTON_PIN(2),
+ LUTON_PIN(3),
+ LUTON_PIN(4),
+ LUTON_PIN(5),
+ LUTON_PIN(6),
+ LUTON_PIN(7),
+ LUTON_PIN(8),
+ LUTON_PIN(9),
+ LUTON_PIN(10),
+ LUTON_PIN(11),
+ LUTON_PIN(12),
+ LUTON_PIN(13),
+ LUTON_PIN(14),
+ LUTON_PIN(15),
+ LUTON_PIN(16),
+ LUTON_PIN(17),
+ LUTON_PIN(18),
+ LUTON_PIN(19),
+ LUTON_PIN(20),
+ LUTON_PIN(21),
+ LUTON_PIN(22),
+ LUTON_PIN(23),
+ LUTON_PIN(24),
+ LUTON_PIN(25),
+ LUTON_PIN(26),
+ LUTON_PIN(27),
+ LUTON_PIN(28),
+ LUTON_PIN(29),
+ LUTON_PIN(30),
+ LUTON_PIN(31),
+};
+
+static const unsigned long luton_gpios[] = {
+ [MSCC_GPIO_OUT_SET] = 0x00,
+ [MSCC_GPIO_OUT_CLR] = 0x04,
+ [MSCC_GPIO_OUT] = 0x08,
+ [MSCC_GPIO_IN] = 0x0c,
+ [MSCC_GPIO_OE] = 0x10,
+ [MSCC_GPIO_INTR] = 0x14,
+ [MSCC_GPIO_INTR_ENA] = 0x18,
+ [MSCC_GPIO_INTR_IDENT] = 0x1c,
+ [MSCC_GPIO_ALT0] = 0x20,
+ [MSCC_GPIO_ALT1] = 0x24,
+};
+
+static int luton_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "luton-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(luton_pins);
+
+ return 0;
+}
+
+static struct driver luton_gpio_driver = {
+ .name = "luton-gpio",
+ .id = UCLASS_GPIO,
+ .probe = luton_gpio_probe,
+ .ops = &mscc_gpio_ops,
+};
+
+int luton_pinctrl_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
+ ARRAY_SIZE(luton_pins), luton_function_names,
+ luton_gpios);
+
+ if (ret)
+ return ret;
+
+ ret = device_bind(dev, &luton_gpio_driver, "luton-gpio", NULL,
+ dev_ofnode(dev), NULL);
+
+ return 0;
+}
+
+static const struct udevice_id luton_pinctrl_of_match[] = {
+ {.compatible = "mscc,luton-pinctrl"},
+ {},
+};
+
+U_BOOT_DRIVER(luton_pinctrl) = {
+ .name = "luton-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(luton_pinctrl_of_match),
+ .probe = luton_pinctrl_probe,
+ .priv_auto = sizeof(struct mscc_pinctrl),
+ .ops = &mscc_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/mscc/pinctrl-ocelot.c b/roms/u-boot/drivers/pinctrl/mscc/pinctrl-ocelot.c
new file mode 100644
index 000000000..57e2ef0d7
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/mscc/pinctrl-ocelot.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <alexandre.belloni@free-electrons.com>
+ * Author: <gregory.clement@bootlin.com>
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_IRQ0_IN,
+ FUNC_IRQ0_OUT,
+ FUNC_IRQ1_IN,
+ FUNC_IRQ1_OUT,
+ FUNC_MIIM1,
+ FUNC_PCI_WAKE,
+ FUNC_PTP0,
+ FUNC_PTP1,
+ FUNC_PTP2,
+ FUNC_PTP3,
+ FUNC_PWM,
+ FUNC_RECO_CLK0,
+ FUNC_RECO_CLK1,
+ FUNC_SFP0,
+ FUNC_SFP1,
+ FUNC_SFP2,
+ FUNC_SFP3,
+ FUNC_SFP4,
+ FUNC_SFP5,
+ FUNC_SG0,
+ FUNC_SI,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_TWI_SCL_M,
+ FUNC_UART,
+ FUNC_UART2,
+ FUNC_MAX
+};
+
+static char * const ocelot_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0_IN] = "irq0_in",
+ [FUNC_IRQ0_OUT] = "irq0_out",
+ [FUNC_IRQ1_IN] = "irq1_in",
+ [FUNC_IRQ1_OUT] = "irq1_out",
+ [FUNC_MIIM1] = "miim1",
+ [FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_PTP0] = "ptp0",
+ [FUNC_PTP1] = "ptp1",
+ [FUNC_PTP2] = "ptp2",
+ [FUNC_PTP3] = "ptp3",
+ [FUNC_PWM] = "pwm",
+ [FUNC_RECO_CLK0] = "reco_clk0",
+ [FUNC_RECO_CLK1] = "reco_clk1",
+ [FUNC_SFP0] = "sfp0",
+ [FUNC_SFP1] = "sfp1",
+ [FUNC_SFP2] = "sfp2",
+ [FUNC_SFP3] = "sfp3",
+ [FUNC_SFP4] = "sfp4",
+ [FUNC_SFP5] = "sfp5",
+ [FUNC_SG0] = "sg0",
+ [FUNC_SI] = "si",
+ [FUNC_TACHO] = "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_TWI_SCL_M] = "twi_scl_m",
+ [FUNC_UART] = "uart",
+ [FUNC_UART2] = "uart2",
+};
+
+MSCC_P(0, SG0, NONE, NONE);
+MSCC_P(1, SG0, NONE, NONE);
+MSCC_P(2, SG0, NONE, NONE);
+MSCC_P(3, SG0, NONE, NONE);
+MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI);
+MSCC_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
+MSCC_P(6, UART, TWI_SCL_M, NONE);
+MSCC_P(7, UART, TWI_SCL_M, NONE);
+MSCC_P(8, SI, TWI_SCL_M, IRQ0_OUT);
+MSCC_P(9, SI, TWI_SCL_M, IRQ1_OUT);
+MSCC_P(10, PTP2, TWI_SCL_M, SFP0);
+MSCC_P(11, PTP3, TWI_SCL_M, SFP1);
+MSCC_P(12, UART2, TWI_SCL_M, SFP2);
+MSCC_P(13, UART2, TWI_SCL_M, SFP3);
+MSCC_P(14, MIIM1, TWI_SCL_M, SFP4);
+MSCC_P(15, MIIM1, TWI_SCL_M, SFP5);
+MSCC_P(16, TWI, NONE, SI);
+MSCC_P(17, TWI, TWI_SCL_M, SI);
+MSCC_P(18, PTP0, TWI_SCL_M, NONE);
+MSCC_P(19, PTP1, TWI_SCL_M, NONE);
+MSCC_P(20, RECO_CLK0, TACHO, NONE);
+MSCC_P(21, RECO_CLK1, PWM, NONE);
+
+#define OCELOT_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &mscc_pin_##n \
+}
+
+static const struct mscc_pin_data ocelot_pins[] = {
+ OCELOT_PIN(0),
+ OCELOT_PIN(1),
+ OCELOT_PIN(2),
+ OCELOT_PIN(3),
+ OCELOT_PIN(4),
+ OCELOT_PIN(5),
+ OCELOT_PIN(6),
+ OCELOT_PIN(7),
+ OCELOT_PIN(8),
+ OCELOT_PIN(9),
+ OCELOT_PIN(10),
+ OCELOT_PIN(11),
+ OCELOT_PIN(12),
+ OCELOT_PIN(13),
+ OCELOT_PIN(14),
+ OCELOT_PIN(15),
+ OCELOT_PIN(16),
+ OCELOT_PIN(17),
+ OCELOT_PIN(18),
+ OCELOT_PIN(19),
+ OCELOT_PIN(20),
+ OCELOT_PIN(21),
+};
+
+static const unsigned long ocelot_gpios[] = {
+ [MSCC_GPIO_OUT_SET] = 0x00,
+ [MSCC_GPIO_OUT_CLR] = 0x04,
+ [MSCC_GPIO_OUT] = 0x08,
+ [MSCC_GPIO_IN] = 0x0c,
+ [MSCC_GPIO_OE] = 0x10,
+ [MSCC_GPIO_INTR] = 0x14,
+ [MSCC_GPIO_INTR_ENA] = 0x18,
+ [MSCC_GPIO_INTR_IDENT] = 0x1c,
+ [MSCC_GPIO_ALT0] = 0x20,
+ [MSCC_GPIO_ALT1] = 0x24,
+};
+
+static int ocelot_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "ocelot-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(ocelot_pins);
+
+ return 0;
+}
+
+static struct driver ocelot_gpio_driver = {
+ .name = "ocelot-gpio",
+ .id = UCLASS_GPIO,
+ .probe = ocelot_gpio_probe,
+ .ops = &mscc_gpio_ops,
+};
+
+int ocelot_pinctrl_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
+ ARRAY_SIZE(ocelot_pins),
+ ocelot_function_names,
+ ocelot_gpios);
+
+ if (ret)
+ return ret;
+
+ ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL,
+ dev_ofnode(dev), NULL);
+
+ return ret;
+}
+
+static const struct udevice_id ocelot_pinctrl_of_match[] = {
+ {.compatible = "mscc,ocelot-pinctrl"},
+ {},
+};
+
+U_BOOT_DRIVER(ocelot_pinctrl) = {
+ .name = "ocelot-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ocelot_pinctrl_of_match),
+ .probe = ocelot_pinctrl_probe,
+ .priv_auto = sizeof(struct mscc_pinctrl),
+ .ops = &mscc_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/mscc/pinctrl-serval.c b/roms/u-boot/drivers/pinctrl/mscc/pinctrl-serval.c
new file mode 100644
index 000000000..a6b9796df
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/mscc/pinctrl-serval.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <horatiu.vultur@microchip.com>
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_IRQ0,
+ FUNC_IRQ1,
+ FUNC_MIIM1,
+ FUNC_PCI_WAKE,
+ FUNC_PTP0,
+ FUNC_PTP1,
+ FUNC_PTP2,
+ FUNC_PTP3,
+ FUNC_PWM,
+ FUNC_RECO_CLK0,
+ FUNC_RECO_CLK1,
+ FUNC_SFP0,
+ FUNC_SFP1,
+ FUNC_SFP2,
+ FUNC_SFP3,
+ FUNC_SFP4,
+ FUNC_SFP5,
+ FUNC_SFP6,
+ FUNC_SFP7,
+ FUNC_SFP8,
+ FUNC_SFP9,
+ FUNC_SFP10,
+ FUNC_SIO,
+ FUNC_SI,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_TWI_SCL_M,
+ FUNC_UART,
+ FUNC_UART2,
+ FUNC_MD,
+ FUNC_PTP1588,
+ FUNC_MAX
+};
+
+static char * const serval_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0] = "irq0",
+ [FUNC_IRQ1] = "irq1",
+ [FUNC_MIIM1] = "miim1",
+ [FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_PTP0] = "ptp0",
+ [FUNC_PTP1] = "ptp1",
+ [FUNC_PTP2] = "ptp2",
+ [FUNC_PTP3] = "ptp3",
+ [FUNC_PWM] = "pwm",
+ [FUNC_RECO_CLK0] = "reco_clk0",
+ [FUNC_RECO_CLK1] = "reco_clk1",
+ [FUNC_SFP0] = "sfp0",
+ [FUNC_SFP1] = "sfp1",
+ [FUNC_SFP2] = "sfp2",
+ [FUNC_SFP3] = "sfp3",
+ [FUNC_SFP4] = "sfp4",
+ [FUNC_SFP5] = "sfp5",
+ [FUNC_SFP6] = "sfp6",
+ [FUNC_SFP7] = "sfp7",
+ [FUNC_SFP8] = "sfp8",
+ [FUNC_SFP9] = "sfp9",
+ [FUNC_SFP10] = "sfp10",
+ [FUNC_SIO] = "sio",
+ [FUNC_SI] = "si",
+ [FUNC_TACHO] = "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_TWI_SCL_M] = "twi_scl_m",
+ [FUNC_UART] = "uart",
+ [FUNC_UART2] = "uart2",
+ [FUNC_MD] = "md",
+ [FUNC_PTP1588] = "1588",
+};
+
+MSCC_P(0, SIO, NONE, NONE);
+MSCC_P(1, SIO, NONE, NONE);
+MSCC_P(2, SIO, NONE, NONE);
+MSCC_P(3, SIO, NONE, NONE);
+MSCC_P(4, TACHO, NONE, NONE);
+MSCC_P(5, PWM, NONE, NONE);
+MSCC_P(6, TWI, NONE, NONE);
+MSCC_P(7, TWI, NONE, NONE);
+MSCC_P(8, SI, NONE, NONE);
+MSCC_P(9, SI, MD, NONE);
+MSCC_P(10, SI, MD, NONE);
+MSCC_P(11, SFP0, MD, TWI_SCL_M);
+MSCC_P(12, SFP1, MD, TWI_SCL_M);
+MSCC_P(13, SFP2, UART2, TWI_SCL_M);
+MSCC_P(14, SFP3, UART2, TWI_SCL_M);
+MSCC_P(15, SFP4, PTP1588, TWI_SCL_M);
+MSCC_P(16, SFP5, PTP1588, TWI_SCL_M);
+MSCC_P(17, SFP6, PCI_WAKE, TWI_SCL_M);
+MSCC_P(18, SFP7, NONE, TWI_SCL_M);
+MSCC_P(19, SFP8, NONE, TWI_SCL_M);
+MSCC_P(20, SFP9, NONE, TWI_SCL_M);
+MSCC_P(21, SFP10, NONE, TWI_SCL_M);
+MSCC_P(22, NONE, NONE, NONE);
+MSCC_P(23, NONE, NONE, NONE);
+MSCC_P(24, NONE, NONE, NONE);
+MSCC_P(25, NONE, NONE, NONE);
+MSCC_P(26, UART, NONE, NONE);
+MSCC_P(27, UART, NONE, NONE);
+MSCC_P(28, IRQ0, NONE, NONE);
+MSCC_P(29, IRQ1, NONE, NONE);
+MSCC_P(30, PTP1588, NONE, NONE);
+MSCC_P(31, PTP1588, NONE, NONE);
+
+#define SERVAL_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &mscc_pin_##n \
+}
+
+static const struct mscc_pin_data serval_pins[] = {
+ SERVAL_PIN(0),
+ SERVAL_PIN(1),
+ SERVAL_PIN(2),
+ SERVAL_PIN(3),
+ SERVAL_PIN(4),
+ SERVAL_PIN(5),
+ SERVAL_PIN(6),
+ SERVAL_PIN(7),
+ SERVAL_PIN(8),
+ SERVAL_PIN(9),
+ SERVAL_PIN(10),
+ SERVAL_PIN(11),
+ SERVAL_PIN(12),
+ SERVAL_PIN(13),
+ SERVAL_PIN(14),
+ SERVAL_PIN(15),
+ SERVAL_PIN(16),
+ SERVAL_PIN(17),
+ SERVAL_PIN(18),
+ SERVAL_PIN(19),
+ SERVAL_PIN(20),
+ SERVAL_PIN(21),
+ SERVAL_PIN(22),
+ SERVAL_PIN(23),
+ SERVAL_PIN(24),
+ SERVAL_PIN(25),
+ SERVAL_PIN(26),
+ SERVAL_PIN(27),
+ SERVAL_PIN(28),
+ SERVAL_PIN(29),
+ SERVAL_PIN(30),
+ SERVAL_PIN(31),
+};
+
+static const unsigned long serval_gpios[] = {
+ [MSCC_GPIO_OUT_SET] = 0x00,
+ [MSCC_GPIO_OUT_CLR] = 0x04,
+ [MSCC_GPIO_OUT] = 0x08,
+ [MSCC_GPIO_IN] = 0x0c,
+ [MSCC_GPIO_OE] = 0x10,
+ [MSCC_GPIO_INTR] = 0x14,
+ [MSCC_GPIO_INTR_ENA] = 0x18,
+ [MSCC_GPIO_INTR_IDENT] = 0x1c,
+ [MSCC_GPIO_ALT0] = 0x20,
+ [MSCC_GPIO_ALT1] = 0x24,
+};
+
+static int serval_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "serval-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(serval_pins);
+
+ return 0;
+}
+
+static struct driver serval_gpio_driver = {
+ .name = "serval-gpio",
+ .id = UCLASS_GPIO,
+ .probe = serval_gpio_probe,
+ .ops = &mscc_gpio_ops,
+};
+
+static int serval_pinctrl_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = mscc_pinctrl_probe(dev, FUNC_MAX, serval_pins,
+ ARRAY_SIZE(serval_pins),
+ serval_function_names,
+ serval_gpios);
+
+ if (ret)
+ return ret;
+
+ ret = device_bind(dev, &serval_gpio_driver, "serval-gpio", NULL,
+ dev_ofnode(dev), NULL);
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id serval_pinctrl_of_match[] = {
+ { .compatible = "mscc,serval-pinctrl" },
+ {},
+};
+
+U_BOOT_DRIVER(serval_pinctrl) = {
+ .name = "serval-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(serval_pinctrl_of_match),
+ .probe = serval_pinctrl_probe,
+ .priv_auto = sizeof(struct mscc_pinctrl),
+ .ops = &mscc_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/mscc/pinctrl-servalt.c b/roms/u-boot/drivers/pinctrl/mscc/pinctrl-servalt.c
new file mode 100644
index 000000000..8e8678580
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/mscc/pinctrl-servalt.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <horatiu.vultur@microchip.com>
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include "mscc-common.h"
+
+enum {
+ FUNC_NONE,
+ FUNC_GPIO,
+ FUNC_IRQ0_IN,
+ FUNC_IRQ0_OUT,
+ FUNC_IRQ1_IN,
+ FUNC_IRQ1_OUT,
+ FUNC_MIIM1,
+ FUNC_MIIM2,
+ FUNC_PCI_WAKE,
+ FUNC_PTP0,
+ FUNC_PTP1,
+ FUNC_PTP2,
+ FUNC_PTP3,
+ FUNC_PWM,
+ FUNC_RCVRD_CLK0,
+ FUNC_RCVRD_CLK1,
+ FUNC_RCVRD_CLK2,
+ FUNC_RCVRD_CLK3,
+ FUNC_REF_CLK0,
+ FUNC_REF_CLK1,
+ FUNC_REF_CLK2,
+ FUNC_REF_CLK3,
+ FUNC_SFP0,
+ FUNC_SFP1,
+ FUNC_SFP2,
+ FUNC_SFP3,
+ FUNC_SFP4,
+ FUNC_SFP5,
+ FUNC_SFP6,
+ FUNC_SFP7,
+ FUNC_SFP8,
+ FUNC_SFP9,
+ FUNC_SFP10,
+ FUNC_SFP11,
+ FUNC_SFP12,
+ FUNC_SFP13,
+ FUNC_SFP14,
+ FUNC_SFP15,
+ FUNC_SIO,
+ FUNC_SPI,
+ FUNC_TACHO,
+ FUNC_TWI,
+ FUNC_TWI2,
+ FUNC_TWI_SCL_M,
+ FUNC_UART,
+ FUNC_UART2,
+ FUNC_MAX
+};
+
+static char * const servalt_function_names[] = {
+ [FUNC_NONE] = "none",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0_IN] = "irq0_in",
+ [FUNC_IRQ0_OUT] = "irq0_out",
+ [FUNC_IRQ1_IN] = "irq1_in",
+ [FUNC_IRQ1_OUT] = "irq1_out",
+ [FUNC_MIIM1] = "miim1",
+ [FUNC_MIIM2] = "miim2",
+ [FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_PTP0] = "ptp0",
+ [FUNC_PTP1] = "ptp1",
+ [FUNC_PTP2] = "ptp2",
+ [FUNC_PTP3] = "ptp3",
+ [FUNC_PWM] = "pwm",
+ [FUNC_RCVRD_CLK0] = "rcvrd_clk0",
+ [FUNC_RCVRD_CLK1] = "rcvrd_clk1",
+ [FUNC_RCVRD_CLK2] = "rcvrd_clk2",
+ [FUNC_RCVRD_CLK3] = "rcvrd_clk3",
+ [FUNC_REF_CLK0] = "ref_clk0",
+ [FUNC_REF_CLK1] = "ref_clk1",
+ [FUNC_REF_CLK2] = "ref_clk2",
+ [FUNC_REF_CLK3] = "ref_clk3",
+ [FUNC_SFP0] = "sfp0",
+ [FUNC_SFP1] = "sfp1",
+ [FUNC_SFP2] = "sfp2",
+ [FUNC_SFP3] = "sfp3",
+ [FUNC_SFP4] = "sfp4",
+ [FUNC_SFP5] = "sfp5",
+ [FUNC_SFP6] = "sfp6",
+ [FUNC_SFP7] = "sfp7",
+ [FUNC_SFP8] = "sfp8",
+ [FUNC_SFP9] = "sfp9",
+ [FUNC_SFP10] = "sfp10",
+ [FUNC_SFP11] = "sfp11",
+ [FUNC_SFP12] = "sfp12",
+ [FUNC_SFP13] = "sfp13",
+ [FUNC_SFP14] = "sfp14",
+ [FUNC_SFP15] = "sfp15",
+ [FUNC_SIO] = "sio",
+ [FUNC_SPI] = "spi",
+ [FUNC_TACHO] = "tacho",
+ [FUNC_TWI] = "twi",
+ [FUNC_TWI2] = "twi2",
+ [FUNC_TWI_SCL_M] = "twi_scl_m",
+ [FUNC_UART] = "uart",
+ [FUNC_UART2] = "uart2",
+};
+
+MSCC_P(0, SIO, NONE, NONE);
+MSCC_P(1, SIO, NONE, NONE);
+MSCC_P(2, SIO, NONE, NONE);
+MSCC_P(3, SIO, NONE, NONE);
+MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
+MSCC_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
+MSCC_P(6, UART, NONE, NONE);
+MSCC_P(7, UART, NONE, NONE);
+MSCC_P(8, SPI, SFP0, TWI_SCL_M);
+MSCC_P(9, PCI_WAKE, SFP1, SPI);
+MSCC_P(10, PTP0, SFP2, TWI_SCL_M);
+MSCC_P(11, PTP1, SFP3, TWI_SCL_M);
+MSCC_P(12, REF_CLK0, SFP4, TWI_SCL_M);
+MSCC_P(13, REF_CLK1, SFP5, TWI_SCL_M);
+MSCC_P(14, REF_CLK2, IRQ0_OUT, SPI);
+MSCC_P(15, REF_CLK3, IRQ1_OUT, SPI);
+MSCC_P(16, TACHO, SFP6, SPI);
+MSCC_P(17, PWM, NONE, TWI_SCL_M);
+MSCC_P(18, PTP2, SFP7, SPI);
+MSCC_P(19, PTP3, SFP8, SPI);
+MSCC_P(20, UART2, SFP9, SPI);
+MSCC_P(21, UART2, NONE, NONE);
+MSCC_P(22, MIIM1, SFP10, TWI2);
+MSCC_P(23, MIIM1, SFP11, TWI2);
+MSCC_P(24, TWI, NONE, NONE);
+MSCC_P(25, TWI, SFP12, TWI_SCL_M);
+MSCC_P(26, TWI_SCL_M, SFP13, SPI);
+MSCC_P(27, TWI_SCL_M, SFP14, SPI);
+MSCC_P(28, TWI_SCL_M, SFP15, SPI);
+MSCC_P(29, TWI_SCL_M, NONE, NONE);
+MSCC_P(30, TWI_SCL_M, NONE, NONE);
+MSCC_P(31, TWI_SCL_M, NONE, NONE);
+MSCC_P(32, TWI_SCL_M, NONE, NONE);
+MSCC_P(33, RCVRD_CLK0, NONE, NONE);
+MSCC_P(34, RCVRD_CLK1, NONE, NONE);
+MSCC_P(35, RCVRD_CLK2, NONE, NONE);
+MSCC_P(36, RCVRD_CLK3, NONE, NONE);
+
+#define SERVALT_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &mscc_pin_##n \
+}
+
+static const struct mscc_pin_data servalt_pins[] = {
+ SERVALT_PIN(0),
+ SERVALT_PIN(1),
+ SERVALT_PIN(2),
+ SERVALT_PIN(3),
+ SERVALT_PIN(4),
+ SERVALT_PIN(5),
+ SERVALT_PIN(6),
+ SERVALT_PIN(7),
+ SERVALT_PIN(8),
+ SERVALT_PIN(9),
+ SERVALT_PIN(10),
+ SERVALT_PIN(11),
+ SERVALT_PIN(12),
+ SERVALT_PIN(13),
+ SERVALT_PIN(14),
+ SERVALT_PIN(15),
+ SERVALT_PIN(16),
+ SERVALT_PIN(17),
+ SERVALT_PIN(18),
+ SERVALT_PIN(19),
+ SERVALT_PIN(20),
+ SERVALT_PIN(21),
+ SERVALT_PIN(22),
+ SERVALT_PIN(23),
+ SERVALT_PIN(24),
+ SERVALT_PIN(25),
+ SERVALT_PIN(26),
+ SERVALT_PIN(27),
+ SERVALT_PIN(28),
+ SERVALT_PIN(29),
+ SERVALT_PIN(30),
+ SERVALT_PIN(31),
+ SERVALT_PIN(32),
+ SERVALT_PIN(33),
+ SERVALT_PIN(34),
+ SERVALT_PIN(35),
+ SERVALT_PIN(36),
+};
+
+static const unsigned long servalt_gpios[] = {
+ [MSCC_GPIO_OUT_SET] = 0x00,
+ [MSCC_GPIO_OUT_CLR] = 0x08,
+ [MSCC_GPIO_OUT] = 0x10,
+ [MSCC_GPIO_IN] = 0x18,
+ [MSCC_GPIO_OE] = 0x20,
+ [MSCC_GPIO_INTR] = 0x28,
+ [MSCC_GPIO_INTR_ENA] = 0x30,
+ [MSCC_GPIO_INTR_IDENT] = 0x38,
+ [MSCC_GPIO_ALT0] = 0x40,
+ [MSCC_GPIO_ALT1] = 0x48,
+};
+
+static int servalt_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "servalt-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(servalt_pins);
+
+ return 0;
+}
+
+static struct driver servalt_gpio_driver = {
+ .name = "servalt-gpio",
+ .id = UCLASS_GPIO,
+ .probe = servalt_gpio_probe,
+ .ops = &mscc_gpio_ops,
+};
+
+static int servalt_pinctrl_probe(struct udevice *dev)
+{
+ int ret;
+
+ ret = mscc_pinctrl_probe(dev, FUNC_MAX, servalt_pins,
+ ARRAY_SIZE(servalt_pins),
+ servalt_function_names,
+ servalt_gpios);
+
+ if (ret)
+ return ret;
+
+ ret = device_bind(dev, &servalt_gpio_driver, "servalt-gpio", NULL,
+ dev_ofnode(dev), NULL);
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id servalt_pinctrl_of_match[] = {
+ { .compatible = "mscc,servalt-pinctrl" },
+ {},
+};
+
+U_BOOT_DRIVER(servalt_pinctrl) = {
+ .name = "servalt-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(servalt_pinctrl_of_match),
+ .probe = servalt_pinctrl_probe,
+ .priv_auto = sizeof(struct mscc_pinctrl),
+ .ops = &mscc_pinctrl_ops,
+};