diff options
Diffstat (limited to 'tests/tcg/xtensa')
45 files changed, 6799 insertions, 0 deletions
diff --git a/tests/tcg/xtensa/Makefile.softmmu-target b/tests/tcg/xtensa/Makefile.softmmu-target new file mode 100644 index 000000000..9530cac2a --- /dev/null +++ b/tests/tcg/xtensa/Makefile.softmmu-target @@ -0,0 +1,42 @@ +# +# Xtensa softmmu tests +# + +ifneq ($(TARGET_WORDS_BIGENDIAN),y) + +XTENSA_SRC = $(SRC_PATH)/tests/tcg/xtensa +XTENSA_ALL = $(filter-out $(XTENSA_SRC)/linker.ld.S,$(wildcard $(XTENSA_SRC)/*.S)) +XTENSA_TESTS = $(patsubst $(XTENSA_SRC)/%.S, %, $(XTENSA_ALL)) +# Filter out common blobs and broken tests +XTENSA_BROKEN_TESTS = crt vectors +XTENSA_USABLE_TESTS = $(filter-out $(XTENSA_BROKEN_TESTS), $(XTENSA_TESTS)) + +# add to the list of tests +TESTS += $(XTENSA_USABLE_TESTS) +VPATH += $(XTENSA_SRC) + +CORE=dc232b +QEMU_OPTS+=-M sim -cpu $(CORE) -nographic -semihosting -icount 6 $(EXTFLAGS) -kernel + +INCLUDE_DIRS = $(SRC_PATH)/target/xtensa/core-$(CORE) +XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS)) + +vectors_ASFLAGS = -mtext-section-literals +ASFLAGS = -Wa,--no-absolute-literals +LDFLAGS = -Tlinker.ld -nostartfiles -nostdlib + +CRT = crt.o vectors.o + +linker.ld: linker.ld.S + $(CC) $(XTENSA_INC) -E -P $< -o $@ + +$(XTENSA_USABLE_TESTS): linker.ld macros.inc $(CRT) Makefile.softmmu-target + +# special rule for common blobs +%.o: %.S + $(CC) $(XTENSA_INC) $($*_ASFLAGS) $(ASFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + +%: %.S + $(CC) $(XTENSA_INC) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(NOSTDFLAGS) $(CRT) + +endif diff --git a/tests/tcg/xtensa/crt.S b/tests/tcg/xtensa/crt.S new file mode 100644 index 000000000..d9846acac --- /dev/null +++ b/tests/tcg/xtensa/crt.S @@ -0,0 +1,24 @@ +.section .init + j 1f +.section .init.text +1: + movi a2, _start + jx a2 + +.text +.global _start +_start: + movi a2, 1 + wsr a2, windowstart + movi a2, 0 + wsr a2, windowbase + movi a1, _fstack + movi a2, 0x4000f + wsr a2, ps + isync + + call0 main + + mov a3, a2 + movi a2, 1 + simcall diff --git a/tests/tcg/xtensa/fpu.h b/tests/tcg/xtensa/fpu.h new file mode 100644 index 000000000..42e321747 --- /dev/null +++ b/tests/tcg/xtensa/fpu.h @@ -0,0 +1,142 @@ +#if XCHAL_HAVE_DFP || XCHAL_HAVE_FP_DIV +#define DFPU 1 +#else +#define DFPU 0 +#endif + +#define FCR_RM_NEAREST 0 +#define FCR_RM_TRUNC 1 +#define FCR_RM_CEIL 2 +#define FCR_RM_FLOOR 3 + +#define FSR__ 0x00000000 +#define FSR_I 0x00000080 +#define FSR_U 0x00000100 +#define FSR_O 0x00000200 +#define FSR_Z 0x00000400 +#define FSR_V 0x00000800 + +#define FSR_UI (FSR_U | FSR_I) +#define FSR_OI (FSR_O | FSR_I) + +#define F32_0 0x00000000 +#define F32_0_5 0x3f000000 +#define F32_1 0x3f800000 +#define F32_MAX 0x7f7fffff +#define F32_PINF 0x7f800000 +#define F32_NINF 0xff800000 + +#define F32_DNAN 0x7fc00000 +#define F32_SNAN(v) (0x7f800000 | (v)) +#define F32_QNAN(v) (0x7fc00000 | (v)) + +#define F32_MINUS 0x80000000 + +#define F64_0 0x0000000000000000 +#define F64_MIN_NORM 0x0010000000000000 +#define F64_1 0x3ff0000000000000 +#define F64_MAX_2 0x7fe0000000000000 +#define F64_MAX 0x7fefffffffffffff +#define F64_PINF 0x7ff0000000000000 +#define F64_NINF 0xfff0000000000000 + +#define F64_DNAN 0x7ff8000000000000 +#define F64_SNAN(v) (0x7ff0000000000000 | (v)) +#define F64_QNAN(v) (0x7ff8000000000000 | (v)) + +#define F64_MINUS 0x8000000000000000 + +.macro test_op1_rm op, fr0, fr1, v0, r, sr + movi a2, 0 + wur a2, fsr + movfp \fr0, \v0 + \op \fr1, \fr0 + check_res \fr1, \r, \sr +.endm + +.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r, sr + movi a2, 0 + wur a2, fsr + movfp \fr0, \v0 + movfp \fr1, \v1 + \op \fr2, \fr0, \fr1 + check_res \fr2, \r, \sr +.endm + +.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r, sr + movi a2, 0 + wur a2, fsr + movfp \fr0, \v0 + movfp \fr1, \v1 + movfp \fr2, \v2 + \op \fr0, \fr1, \fr2 + check_res \fr3, \r, \sr +.endm + +.macro test_op1_ex op, fr0, fr1, v0, rm, r, sr + movi a2, \rm + wur a2, fcr + test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr + movi a2, (\rm) | 0x7c + wur a2, fcr + test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr +.endm + +.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r, sr + movi a2, \rm + wur a2, fcr + test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr + movi a2, (\rm) | 0x7c + wur a2, fcr + test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr +.endm + +.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r, sr + movi a2, \rm + wur a2, fcr + test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr + movi a2, (\rm) | 0x7c + wur a2, fcr + test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr +.endm + +.macro test_op1 op, fr0, fr1, v0, r0, r1, r2, r3, sr0, sr1, sr2, sr3 + test_op1_ex \op, \fr0, \fr1, \v0, 0, \r0, \sr0 + test_op1_ex \op, \fr0, \fr1, \v0, 1, \r1, \sr1 + test_op1_ex \op, \fr0, \fr1, \v0, 2, \r2, \sr2 + test_op1_ex \op, \fr0, \fr1, \v0, 3, \r3, \sr3 +.endm + +.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3, sr0, sr1, sr2, sr3 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0, \sr0 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1, \sr1 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2, \sr2 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3, \sr3 +.endm + +.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3, sr0, sr1, sr2, sr3 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0, \sr0 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1, \sr1 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2, \sr2 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3, \sr3 +.endm + +.macro test_op2_cpe op + set_vector kernel, 2f + movi a2, 0 + wsr a2, cpenable +1: + \op f2, f0, f1 + test_fail +2: + rsr a2, excvaddr + movi a3, 1b + assert eq, a2, a3 + rsr a2, exccause + movi a3, 32 + assert eq, a2, a3 + + set_vector kernel, 0 + movi a2, 1 + wsr a2, cpenable +.endm diff --git a/tests/tcg/xtensa/linker.ld.S b/tests/tcg/xtensa/linker.ld.S new file mode 100644 index 000000000..ac89b0054 --- /dev/null +++ b/tests/tcg/xtensa/linker.ld.S @@ -0,0 +1,166 @@ +#include "core-isa.h" + +#ifndef XCHAL_VECBASE_RESET_VADDR +#define XCHAL_VECBASE_RESET_VADDR XCHAL_WINDOW_VECTORS_VADDR +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#endif + +#define RAM_SIZE 0x08000000 /* 128M */ +#define ROM_SIZE 0x00001000 /* 4k */ +#define VECTORS_RESERVED_SIZE 0x1000 + +#if XCHAL_HAVE_BE +OUTPUT_FORMAT("elf32-xtensa-be") +#else +OUTPUT_FORMAT("elf32-xtensa-le") +#endif +ENTRY(_start) + +MEMORY { + ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = RAM_SIZE + rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = ROM_SIZE +} + +SECTIONS +{ + .init : + { + *(.init) + *(.init.*) + } > rom + +#if XCHAL_HAVE_WINDOWED + .vector.window XCHAL_WINDOW_VECTORS_VADDR : + { + . = XCHAL_WINDOW_OF4_VECOFS; + *(.vector.window_overflow_4) + . = XCHAL_WINDOW_UF4_VECOFS; + *(.vector.window_underflow_4) + . = XCHAL_WINDOW_OF8_VECOFS; + *(.vector.window_overflow_8) + . = XCHAL_WINDOW_UF8_VECOFS; + *(.vector.window_underflow_8) + . = XCHAL_WINDOW_OF12_VECOFS; + *(.vector.window_overflow_12) + . = XCHAL_WINDOW_UF12_VECOFS; + *(.vector.window_underflow_12) + } +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2 + .vector.level2 XCHAL_INTLEVEL2_VECTOR_VADDR : + { + *(.vector.level2) + } +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3 + .vector.level3 XCHAL_INTLEVEL3_VECTOR_VADDR : + { + *(.vector.level3) + } +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4 + .vector.level4 XCHAL_INTLEVEL4_VECTOR_VADDR : + { + *(.vector.level4) + } +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5 + .vector.level5 XCHAL_INTLEVEL5_VECTOR_VADDR : + { + *(.vector.level5) + } +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6 + .vector.level6 XCHAL_INTLEVEL6_VECTOR_VADDR : + { + *(.vector.level6) + } +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7 + .vector.level7 XCHAL_INTLEVEL7_VECTOR_VADDR : + { + *(.vector.level7) + } +#endif + .vector.kernel XCHAL_KERNEL_VECTOR_VADDR : + { + *(.vector.kernel) + } + .vector.user XCHAL_USER_VECTOR_VADDR : + { + *(.vector.user) + } + .vector.double XCHAL_DOUBLEEXC_VECTOR_VADDR : + { + *(.vector.double) + } + + .vector.text XCHAL_VECBASE_RESET_VADDR + VECTORS_RESERVED_SIZE : + { + *(.vector.window_overflow_4.*) + *(.vector.window_underflow_4.*) + *(.vector.window_overflow_8.*) + *(.vector.window_underflow_8.*) + *(.vector.window_overflow_12.*) + *(.vector.window_underflow_12.*) + + *(.vector.level2.*) + *(.vector.level3.*) + *(.vector.level4.*) + *(.vector.level5.*) + *(.vector.level6.*) + *(.vector.level7.*) + + *(.vector.kernel.*) + *(.vector.user.*) + *(.vector.double.*) + } > ram + + .text : + { + _ftext = .; + *(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*) + _etext = .; + } > ram + + .rodata : + { + . = ALIGN(4); + _frodata = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + _erodata = .; + } > ram + + .data : + { + . = ALIGN(4); + _fdata = .; + *(.data .data.* .gnu.linkonce.d.*) + *(.data1) + _gp = ALIGN(16); + *(.sdata .sdata.* .gnu.linkonce.s.*) + _edata = .; + } > ram + + .bss : + { + . = ALIGN(4); + _fbss = .; + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + _ebss = .; + _end = .; + } > ram +} + +PROVIDE(_fstack = (ORIGIN(ram) & 0xf0000000) + LENGTH(ram) - 16); diff --git a/tests/tcg/xtensa/macros.inc b/tests/tcg/xtensa/macros.inc new file mode 100644 index 000000000..f88937c7b --- /dev/null +++ b/tests/tcg/xtensa/macros.inc @@ -0,0 +1,122 @@ +#include "core-isa.h" + +.macro test_suite name +.data +status: .word result +result: .space 1024 +.text +.global main +.align 4 +main: +.endm + +.macro reset_ps + movi a2, 0x4000f + wsr a2, ps + isync +.endm + +.macro test_suite_end + reset_ps + movi a0, status + l32i a2, a0, 0 + movi a0, result + sub a2, a2, a0 + movi a3, 0 + beqz a2, 2f +1: + l32i a1, a0, 0 + or a3, a3, a1 + addi a0, a0, 4 + addi a2, a2, -1 + bnez a2, 1b +2: + exit +.endm + +.macro print text +.data +97: .ascii "\text\n" +98: + .align 4 +.text + movi a2, 4 + movi a3, 2 + movi a4, 97b + movi a5, 98b + sub a5, a5, a4 + simcall +.endm + +.macro test_init +.endm + +.macro test name +#ifdef DEBUG + print test_\name +#endif + test_init +test_\name: +.global test_\name +.endm + +.macro test_end +99: + reset_ps + movi a2, status + l32i a3, a2, 0 + addi a3, a3, 4 + s32i a3, a2, 0 +.endm + +.macro exit + movi a2, 1 + simcall +.endm + +.macro test_fail + movi a2, status + l32i a2, a2, 0 + movi a3, 1 + s32i a3, a2, 0 +#ifdef DEBUG + print failed +#endif + j 99f +.endm + +.macro assert cond, arg1, arg2 + b\cond \arg1, \arg2, 90f + test_fail +90: + nop +.endm + +.macro set_vector vector, addr + movi a2, handler_\vector + movi a3, \addr + s32i a3, a2, 0 +.endm + +.macro dump r +#ifdef DEBUG +.data +.align 4 +1: .word 0 +.text + movi a4, 1b + s32i a2, a4, 0 + movi a2, 4 + movi a3, 1 + movi a5, 4 + simcall + movi a4, 1b + l32i a2, a4, 0 +#endif +.endm + +#define glue(a, b) _glue(a, b) +#define _glue(a, b) a ## b + +#define glue3(a, b, c) _glue3(a, b, c) +#define _glue3(a, b, c) a ## b ## c diff --git a/tests/tcg/xtensa/test_b.S b/tests/tcg/xtensa/test_b.S new file mode 100644 index 000000000..713a454c5 --- /dev/null +++ b/tests/tcg/xtensa/test_b.S @@ -0,0 +1,245 @@ +#include "macros.inc" + +test_suite b + +test bnone + movi a2, 0xa5a5ff00 + movi a3, 0x5a5a00ff + bnone a2, a3, 1f + test_fail +1: + movi a2, 0xa5a5ff01 + bnone a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test beq + movi a2, 0 + movi a3, 0 + beq a2, a3, 1f + test_fail +1: + movi a2, 1 + beq a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test blt + movi a2, 6 + movi a3, 7 + blt a2, a3, 1f + test_fail +1: + movi a2, 0xffffffff + blt a2, a3, 1f + test_fail +1: + movi a2, 7 + blt a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test bltu + movi a2, 6 + movi a3, 7 + bltu a2, a3, 1f + test_fail +1: + movi a2, 7 + bltu a2, a3, 1f + j 2f +1: + test_fail +2: + movi a2, 0xffffffff + bltu a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test ball + movi a2, 0xa5a5ffa5 + movi a3, 0xa5a5ff00 + ball a2, a3, 1f + test_fail +1: + movi a2, 0xa5a5a5a5 + ball a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test bbc + movi a2, 0xfffffffd +#undef BIT +#if XCHAL_HAVE_BE +#define BIT 0xfffffffe +#else +#define BIT 0xffffff01 +#endif + movi a3, BIT + bbc a2, a3, 1f + test_fail +1: + movi a2, 8 +#undef BIT +#if XCHAL_HAVE_BE +#define BIT 0xfffffffc +#else +#define BIT 0xffffff03 +#endif + movi a3, BIT + bbc a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test bbci + movi a2, 0xfffdffff + bbci.l a2, 17, 1f + test_fail +1: + movi a2, 0x00020000 + bbci.l a2, 17, 1f + j 2f +1: + test_fail +2: +test_end + +test bany + movi a2, 0xa5a5ff01 + movi a3, 0x5a5a00ff + bany a2, a3, 1f + test_fail +1: + movi a2, 0xa5a5ff00 + bany a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test bne + movi a2, 1 + movi a3, 0 + bne a2, a3, 1f + test_fail +1: + movi a2, 0 + bne a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test bge + movi a2, 7 + movi a3, 7 + bge a2, a3, 1f + test_fail +1: + movi a2, 6 + bge a2, a3, 1f + j 2f +1: + test_fail +2: + movi a2, 0xffffffff + bge a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test bgeu + movi a2, 7 + movi a3, 7 + bgeu a2, a3, 1f + test_fail +1: + movi a2, 0xffffffff + bgeu a2, a3, 1f + test_fail +1: + movi a2, 6 + bgeu a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test bnall + movi a2, 0xa5a5a5a5 + movi a3, 0xa5a5ff00 + bnall a2, a3, 1f + test_fail +1: + movi a2, 0xa5a5ffa5 + bnall a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test bbs + movi a2, 8 +#undef BIT +#if XCHAL_HAVE_BE +#define BIT 0xfffffffc +#else +#define BIT 0xffffff03 +#endif + movi a3, BIT + bbs a2, a3, 1f + test_fail +1: + movi a2, 0xfffffffd +#undef BIT +#if XCHAL_HAVE_BE +#define BIT 0xfffffffe +#else +#define BIT 0xffffff01 +#endif + movi a3, BIT + bbs a2, a3, 1f + j 2f +1: + test_fail +2: +test_end + +test bbsi + movi a2, 0x00020000 + bbsi.l a2, 17, 1f + test_fail +1: + movi a2, 0xfffdffff + bbsi.l a2, 17, 1f + j 2f +1: + test_fail +2: +test_end + +test_suite_end diff --git a/tests/tcg/xtensa/test_bi.S b/tests/tcg/xtensa/test_bi.S new file mode 100644 index 000000000..4f94c0c7e --- /dev/null +++ b/tests/tcg/xtensa/test_bi.S @@ -0,0 +1,103 @@ +#include "macros.inc" + +test_suite bi + +test beqi + movi a2, 7 + beqi a2, 7, 1f + test_fail +1: + movi a2, 1 + beqi a2, 7, 1f + j 2f +1: + test_fail +2: +test_end + +test bnei + movi a2, 1 + bnei a2, 7, 1f + test_fail +1: + movi a2, 7 + bnei a2, 7, 1f + j 2f +1: + test_fail +2: +test_end + +test blti + movi a2, 6 + blti a2, 7, 1f + test_fail +1: + movi a2, 0xffffffff + blti a2, 7, 1f + test_fail +1: + movi a2, 7 + blti a2, 7, 1f + j 2f +1: + test_fail +2: +test_end + +test bgei + movi a2, 7 + bgei a2, 7, 1f + test_fail +1: + movi a2, 6 + bgei a2, 7, 1f + j 2f +1: + test_fail +2: + movi a2, 0xffffffff + bgei a2, 7, 1f + j 2f +1: + test_fail +2: +test_end + +test bltui + movi a2, 6 + bltui a2, 7, 1f + test_fail +1: + movi a2, 7 + bltui a2, 7, 1f + j 2f +1: + test_fail +2: + movi a2, 0xffffffff + bltui a2, 7, 1f + j 2f +1: + test_fail +2: +test_end + +test bgeui + movi a2, 7 + bgeui a2, 7, 1f + test_fail +1: + movi a2, 0xffffffff + bgeui a2, 7, 1f + test_fail +1: + movi a2, 6 + bgeui a2, 7, 1f + j 2f +1: + test_fail +2: +test_end + +test_suite_end diff --git a/tests/tcg/xtensa/test_boolean.S b/tests/tcg/xtensa/test_boolean.S new file mode 100644 index 000000000..5a850bfe7 --- /dev/null +++ b/tests/tcg/xtensa/test_boolean.S @@ -0,0 +1,27 @@ +#include "macros.inc" + +test_suite boolean + +#if XCHAL_HAVE_BOOLEANS + +test all4 + movi a2, 0xfec0 + wsr a2, br + all4 b0, b0 + rsr a3, br + assert eq, a2, a3 + all4 b0, b4 + rsr a3, br + assert eq, a2, a3 + all4 b0, b8 + rsr a3, br + assert eq, a2, a3 + all4 b0, b12 + rsr a3, br + addi a2, a2, 1 + assert eq, a2, a3 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_break.S b/tests/tcg/xtensa/test_break.S new file mode 100644 index 000000000..3379a3f9f --- /dev/null +++ b/tests/tcg/xtensa/test_break.S @@ -0,0 +1,266 @@ +#include "macros.inc" + +test_suite break + +#if XCHAL_HAVE_DEBUG + +#define debug_level XCHAL_DEBUGLEVEL +#define debug_vector glue(level, XCHAL_DEBUGLEVEL) +#define EPC_DEBUG glue(epc, XCHAL_DEBUGLEVEL) + +test break + set_vector debug_vector, 0 + rsil a2, debug_level + _break 0, 0 + + set_vector debug_vector, 2f + rsil a2, debug_level - 1 +1: + _break 0, 0 + test_fail +2: + rsr a2, ps + movi a3, 0x1f + and a2, a2, a3 + movi a3, 0x10 | debug_level + assert eq, a2, a3 + rsr a2, EPC_DEBUG + movi a3, 1b + assert eq, a2, a3 + rsr a2, debugcause + movi a3, 0x8 + assert eq, a2, a3 +test_end + +test breakn + set_vector debug_vector, 0 + rsil a2, debug_level + _break.n 0 + + set_vector debug_vector, 2f + rsil a2, debug_level - 1 +1: + _break.n 0 + test_fail +2: + rsr a2, ps + movi a3, 0x1f + and a2, a2, a3 + movi a3, 0x10 | debug_level + assert eq, a2, a3 + rsr a2, EPC_DEBUG + movi a3, 1b + assert eq, a2, a3 + rsr a2, debugcause + movi a3, 0x10 + assert eq, a2, a3 +test_end + +#if XCHAL_NUM_IBREAK +test ibreak + set_vector debug_vector, 0 + rsil a2, debug_level + movi a2, 1f + wsr a2, ibreaka0 + movi a2, 1 + wsr a2, ibreakenable + isync +1: + rsil a2, debug_level - 1 + movi a2, 1f + wsr a2, ibreaka0 + movi a2, 0 + wsr a2, ibreakenable + isync +1: + set_vector debug_vector, 2f + movi a2, 1f + wsr a2, ibreaka0 + movi a2, 1 + wsr a2, ibreakenable + isync +1: + test_fail +2: + rsr a2, ps + movi a3, 0x1f + and a2, a2, a3 + movi a3, 0x10 | debug_level + assert eq, a2, a3 + rsr a2, EPC_DEBUG + movi a3, 1b + assert eq, a2, a3 + rsr a2, debugcause + movi a3, 0x2 + assert eq, a2, a3 +test_end + +test ibreak_remove + set_vector debug_vector, 3f + rsil a2, debug_level - 1 + movi a2, 2f + wsr a2, ibreaka0 + movi a3, 1 +1: + wsr a3, ibreakenable + isync +2: + beqz a3, 4f + test_fail +3: + assert eqi, a3, 1 + rsr a2, ps + movi a3, 0x1f + and a2, a2, a3 + movi a3, 0x10 | debug_level + assert eq, a2, a3 + rsr a2, EPC_DEBUG + movi a3, 2b + assert eq, a2, a3 + rsr a2, debugcause + movi a3, 0x2 + assert eq, a2, a3 + + movi a2, 0x40000 + wsr a2, ps + isync + movi a3, 0 + j 1b +4: +test_end + +test ibreak_priority + set_vector debug_vector, 2f + rsil a2, debug_level - 1 + movi a2, 1f + wsr a2, ibreaka0 + movi a2, 1 + wsr a2, ibreakenable + isync +1: + break 0, 0 + test_fail +2: + rsr a2, debugcause + movi a3, 0x2 + assert eq, a2, a3 +test_end +#endif + +test icount + set_vector debug_vector, 2f + rsil a2, debug_level - 1 + movi a2, -2 + wsr a2, icount + movi a2, 1 + wsr a2, icountlevel + isync + rsil a2, 0 + nop +1: + break 0, 0 + test_fail +2: + movi a2, 0 + wsr a2, icountlevel + rsr a2, EPC_DEBUG + movi a3, 1b + assert eq, a2, a3 + rsr a2, debugcause + movi a3, 0x1 + assert eq, a2, a3 +test_end + +.macro check_dbreak dr + rsr a2, EPC_DEBUG + movi a3, 1b + assert eq, a2, a3 + rsr a2, debugcause + movi a3, 0x4 | (\dr << 8) + assert eq, a2, a3 + movi a2, 0 + wsr a2, dbreakc\dr +.endm + +.macro dbreak_test dr, ctl, break, access, op + set_vector debug_vector, 2f + rsil a2, debug_level - 1 + movi a2, \ctl + wsr a2, dbreakc\dr + movi a2, \break + wsr a2, dbreaka\dr + movi a2, \access + isync +1: + \op a3, a2, 0 + test_fail +2: + check_dbreak \dr + reset_ps +.endm + +#if XCHAL_NUM_DBREAK +test dbreak_exact + dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui + dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui + dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007c, l32i + + dbreak_test 1, 0x8000003f, 0xd000007f, 0xd000007f, s8i + dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007e, s16i + dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s32i +test_end + +test dbreak_overlap + dbreak_test 0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui + dbreak_test 1, 0x4000003f, 0xd000007d, 0xd000007c, l32i + + dbreak_test 0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui + dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007c, l32i + + dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui + dbreak_test 1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui + + dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007b, l8ui + dbreak_test 1, 0x40000038, 0xd0000078, 0xd000007a, l16ui + dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007c, l32i + + dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000075, l8ui + dbreak_test 0, 0x40000030, 0xd0000070, 0xd0000076, l16ui + dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000078, l32i + + dbreak_test 0, 0x40000020, 0xd0000060, 0xd000006f, l8ui + dbreak_test 1, 0x40000020, 0xd0000060, 0xd0000070, l16ui + dbreak_test 0, 0x40000020, 0xd0000060, 0xd0000074, l32i + + + dbreak_test 0, 0x8000003f, 0xd000007d, 0xd000007c, s16i + dbreak_test 1, 0x8000003f, 0xd000007d, 0xd000007c, s32i + + dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007f, s8i + dbreak_test 1, 0x8000003e, 0xd000007e, 0xd000007c, s32i + + dbreak_test 0, 0x8000003c, 0xd000007c, 0xd000007d, s8i + dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s16i + + dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007b, s8i + dbreak_test 1, 0x80000038, 0xd0000078, 0xd000007a, s16i + dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007c, s32i + + dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000075, s8i + dbreak_test 0, 0x80000030, 0xd0000070, 0xd0000076, s16i + dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000078, s32i + + dbreak_test 0, 0x80000020, 0xd0000060, 0xd000006f, s8i + dbreak_test 1, 0x80000020, 0xd0000060, 0xd0000070, s16i + dbreak_test 0, 0x80000020, 0xd0000060, 0xd0000074, s32i +test_end + +test dbreak_invalid + dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui + dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i +test_end +#endif + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_bz.S b/tests/tcg/xtensa/test_bz.S new file mode 100644 index 000000000..b68135011 --- /dev/null +++ b/tests/tcg/xtensa/test_bz.S @@ -0,0 +1,57 @@ +#include "macros.inc" + +test_suite bz + +test beqz + movi a2, 0 + _beqz a2, 1f + test_fail +1: + movi a2, 1 + _beqz a2, 1f + j 2f +1: + test_fail +2: +test_end + +test bnez + movi a2, 1 + _bnez a2, 1f + test_fail +1: + movi a2, 0 + _bnez a2, 1f + j 2f +1: + test_fail +2: +test_end + +test bltz + movi a2, 0xffffffff + bltz a2, 1f + test_fail +1: + movi a2, 0 + bltz a2, 1f + j 2f +1: + test_fail +2: +test_end + +test bgez + movi a2, 0 + bgez a2, 1f + test_fail +1: + movi a2, 0xffffffff + bgez a2, 1f + j 2f +1: + test_fail +2: +test_end + +test_suite_end diff --git a/tests/tcg/xtensa/test_cache.S b/tests/tcg/xtensa/test_cache.S new file mode 100644 index 000000000..7e6ba4c18 --- /dev/null +++ b/tests/tcg/xtensa/test_cache.S @@ -0,0 +1,135 @@ +#include "macros.inc" + +.purgem test_init +.macro test_init + call0 cache_unlock_invalidate +.endm + +test_suite cache + +#if XCHAL_HAVE_PTP_MMU + +.macro pf_op op + \op a2, 0 + \op a3, 0 + \op a4, 0 +.endm + +test prefetch + movi a2, 0xd0000000 /* cacheable */ + movi a3, 0xd8000000 /* non-cacheable */ + movi a4, 0x00001235 /* unmapped */ + +#if XCHAL_DCACHE_SIZE + pf_op dpfr + pf_op dpfro + pf_op dpfw + pf_op dpfwo +#endif +#ifdef XCHAL_ICACHE_SIZE + pf_op ipf +#endif +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY +#if XCHAL_DCACHE_LINE_LOCKABLE + dpfl a2, 0 +#endif +#if XCHAL_ICACHE_LINE_LOCKABLE + ipfl a2, 0 +#endif +#endif +test_end + +.macro cache_fault op, addr, exc_code + set_vector kernel, 2f + + movi a4, \addr +1: + \op a4, 0 + test_fail +2: + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 + rsr a2, excvaddr + assert eq, a2, a4 + rsr a2, exccause + movi a3, \exc_code + assert eq, a2, a3 +.endm + +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY + +#if XCHAL_DCACHE_LINE_LOCKABLE +test dpfl_tlb_miss + cache_fault dpfl, 0x00002345, 24 +test_end +#endif + +#if XCHAL_DCACHE_SIZE +#if XCHAL_DCACHE_IS_WRITEBACK +test dhwb_tlb_miss + cache_fault dhwb, 0x00002345, 24 +test_end + +test dhwbi_tlb_miss + cache_fault dhwbi, 0x00002345, 24 +test_end +#endif + +test dhi_tlb_miss + cache_fault dhi, 0x00002345, 24 +test_end + +#if XCHAL_DCACHE_LINE_LOCKABLE +test dhu_tlb_miss + cache_fault dhu, 0x00002345, 24 +test_end +#endif +#endif + +#if XCHAL_ICACHE_SIZE +#if XCHAL_ICACHE_LINE_LOCKABLE +test ipfl_tlb_miss + cache_fault ipfl, 0x00002345, 16 +test_end + +test ihu_tlb_miss + cache_fault ihu, 0x00002345, 16 +test_end +#endif + +test ihi_tlb_miss + cache_fault ihi, 0x00002345, 16 +test_end +#endif + +#endif + +#endif + +test_suite_end + +cache_unlock_invalidate: +#if XCHAL_DCACHE_SIZE + movi a2, 0 + movi a3, XCHAL_DCACHE_SIZE +1: +#if XCHAL_DCACHE_LINE_LOCKABLE + diu a2, 0 +#endif + dii a2, 0 + addi a2, a2, XCHAL_DCACHE_LINESIZE + bltu a2, a3, 1b +#endif +#if XCHAL_ICACHE_SIZE + movi a2, 0 + movi a3, XCHAL_ICACHE_SIZE +1: +#if XCHAL_ICACHE_LINE_LOCKABLE + iiu a2, 0 +#endif + iii a2, 0 + addi a2, a2, XCHAL_ICACHE_LINESIZE + bltu a2, a3, 1b +#endif + ret diff --git a/tests/tcg/xtensa/test_clamps.S b/tests/tcg/xtensa/test_clamps.S new file mode 100644 index 000000000..d9b2c38ac --- /dev/null +++ b/tests/tcg/xtensa/test_clamps.S @@ -0,0 +1,46 @@ +#include "macros.inc" + +test_suite clamps + +#if XCHAL_HAVE_CLAMPS + +test clamps + movi a2, 0 + movi a3, 0 + clamps a4, a2, 7 + assert eq, a3, a4 + + movi a2, 0x7f + movi a3, 0x7f + clamps a4, a2, 7 + assert eq, a3, a4 + + movi a2, 0xffffff80 + movi a3, 0xffffff80 + clamps a4, a2, 7 + assert eq, a3, a4 + + movi a2, 0x80 + movi a3, 0x7f + clamps a2, a2, 7 + assert eq, a3, a2 + + movi a2, 0xffffff7f + movi a3, 0xffffff80 + clamps a2, a2, 7 + assert eq, a3, a2 + + movi a2, 0x7fffffff + movi a3, 0x7f + clamps a2, a2, 7 + assert eq, a3, a2 + + movi a2, 0x80000000 + movi a3, 0xffffff80 + clamps a2, a2, 7 + assert eq, a3, a2 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_dfp0_arith.S b/tests/tcg/xtensa/test_dfp0_arith.S new file mode 100644 index 000000000..53bf8122d --- /dev/null +++ b/tests/tcg/xtensa/test_dfp0_arith.S @@ -0,0 +1,162 @@ +#include "macros.inc" +#include "fpu.h" + +test_suite fp0_arith + +#if XCHAL_HAVE_DFP + +.macro movfp fr, v + movi a2, ((\v) >> 32) & 0xffffffff + movi a3, ((\v) & 0xffffffff) + wfrd \fr, a2, a3 +.endm + +.macro check_res fr, r, sr + rfrd a2, \fr + dump a2 + movi a3, ((\r) >> 32) & 0xffffffff + assert eq, a2, a3 + rfr a2, \fr + dump a2 + movi a3, ((\r) & 0xffffffff) + assert eq, a2, a3 + rur a2, fsr + movi a3, \sr + assert eq, a2, a3 +.endm + +test add_d + movi a2, 1 + wsr a2, cpenable + + /* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */ + test_op2 add.d, f6, f7, f8, F64_MAX, F64_MAX, \ + F64_PINF, F64_MAX, F64_PINF, F64_MAX, \ + FSR_OI, FSR_OI, FSR_OI, FSR_OI +test_end + +test add_d_inf + /* 1 + +inf = +inf */ + test_op2 add.d, f6, f7, f8, F64_1, F64_PINF, \ + F64_PINF, F64_PINF, F64_PINF, F64_PINF, \ + FSR__, FSR__, FSR__, FSR__ + + /* +inf + -inf = default NaN */ + test_op2 add.d, f0, f1, f2, F64_PINF, F64_NINF, \ + F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +test add_d_nan_dfpu + /* 1 + QNaN = QNaN */ + test_op2 add.d, f9, f10, f11, F64_1, F64_QNAN(1), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + /* 1 + SNaN = QNaN */ + test_op2 add.d, f12, f13, f14, F64_1, F64_SNAN(1), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + + /* SNaN1 + SNaN2 = QNaN2 */ + test_op2 add.d, f15, f0, f1, F64_SNAN(1), F64_SNAN(2), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + /* QNaN1 + SNaN2 = QNaN2 */ + test_op2 add.d, f5, f6, f7, F64_QNAN(1), F64_SNAN(2), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + /* SNaN1 + QNaN2 = QNaN2 */ + test_op2 add.d, f8, f9, f10, F64_SNAN(1), F64_QNAN(2), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +test sub_d + /* norm - norm = denorm */ + test_op2 sub.d, f6, f7, f8, F64_MIN_NORM | 1, F64_MIN_NORM, \ + 0x00000001, 0x00000001, 0x00000001, 0x00000001, \ + FSR__, FSR__, FSR__, FSR__ +test_end + +test mul_d + test_op2 mul.d, f0, f1, f2, F64_1 | 1, F64_1 | 1, \ + F64_1 | 2, F64_1 | 2, F64_1 | 3, F64_1 | 2, \ + FSR_I, FSR_I, FSR_I, FSR_I + /* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */ + test_op2 mul.d, f6, f7, f8, F64_MAX_2, F64_MAX_2, \ + F64_PINF, F64_MAX, F64_PINF, F64_MAX, \ + FSR_OI, FSR_OI, FSR_OI, FSR_OI + /* min norm * min norm = 0/denorm */ + test_op2 mul.d, f6, f7, f8, F64_MIN_NORM, F64_MIN_NORM, \ + F64_0, F64_0, 0x00000001, F64_0, \ + FSR_UI, FSR_UI, FSR_UI, FSR_UI + /* inf * 0 = default NaN */ + test_op2 mul.d, f6, f7, f8, F64_PINF, F64_0, \ + F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +test madd_d + test_op3 madd.d, f0, f1, f2, f0, F64_0, F64_1 | 1, F64_1 | 1, \ + F64_1 | 2, F64_1 | 2, F64_1 | 3, F64_1 | 2, \ + FSR_I, FSR_I, FSR_I, FSR_I +test_end + +test madd_d_precision + test_op3 madd.d, f0, f1, f2, f0, \ + F64_MINUS | F64_1 | 2, F64_1 | 1, F64_1 | 1, \ + 0x3970000000000000, 0x3970000000000000, 0x3970000000000000, 0x3970000000000000, \ + FSR__, FSR__, FSR__, FSR__ +test_end + +test madd_d_nan_dfpu + /* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */ + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_1, \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_1, \ + F64_QNAN(2), F64_QNAN(2), F64_QNAN(2), F64_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_1, F64_QNAN(3), \ + F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_1, \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_QNAN(3), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_QNAN(3), \ + F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_QNAN(3), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + + /* inf * 0 = default NaN */ + test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_PINF, F64_0, \ + F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V + /* inf * 0 + SNaN1 = QNaN1 */ + test_op3 madd.d, f0, f1, f2, f0, F64_SNAN(1), F64_PINF, F64_0, \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + /* inf * 0 + QNaN1 = QNaN1 */ + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_PINF, F64_0, \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + + /* madd/msub SNaN turns to QNaN and sets Invalid flag */ + test_op3 madd.d, f0, f1, f2, f0, F64_SNAN(1), F64_1, F64_1, \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_SNAN(2), F64_1, \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_exclusive.S b/tests/tcg/xtensa/test_exclusive.S new file mode 100644 index 000000000..7757a552e --- /dev/null +++ b/tests/tcg/xtensa/test_exclusive.S @@ -0,0 +1,48 @@ +#include "macros.inc" + +test_suite exclusive + +#if XCHAL_HAVE_EXCLUSIVE + +test exclusive_nowrite + movi a2, 0x29 + wsr a2, atomctl + clrex + movi a2, 1f + movi a3, 1 + s32ex a3, a2 + getex a3 + assert eqi, a3, 0 + l32i a3, a2, 0 + assert eqi, a3, 3 + +.data +.align 4 +1: + .word 3 +.text +test_end + +test exclusive_write + movi a2, 0x29 + wsr a2, atomctl + movi a2, 1f + l32ex a3, a2 + assert eqi, a3, 3 + movi a3, 2 + s32ex a3, a2 + getex a3 + assert eqi, a3, 1 + l32i a3, a2, 0 + assert eqi, a3, 2 + +.data +.align 4 +1: + .word 3 +.text +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_extui.S b/tests/tcg/xtensa/test_extui.S new file mode 100644 index 000000000..c32bb824d --- /dev/null +++ b/tests/tcg/xtensa/test_extui.S @@ -0,0 +1,26 @@ +#include "macros.inc" + +test_suite extui + +.macro test_extui v, shiftimm, maskimm + .if \shiftimm + \maskimm <= 32 + movi a2, \v + extui a3, a2, \shiftimm, \maskimm + movi a4, ((\v) >> (\shiftimm)) & ((1 << (\maskimm)) - 1) + assert eq, a3, a4 + .endif +.endm + +test extui + .set shiftimm, 0 + .rept 32 + .set maskimm, 1 + .rept 16 + test_extui 0xc8df1370, shiftimm, maskimm + .set maskimm, maskimm + 1 + .endr + .set shiftimm, shiftimm + 1 + .endr +test_end + +test_suite_end diff --git a/tests/tcg/xtensa/test_flix.S b/tests/tcg/xtensa/test_flix.S new file mode 100644 index 000000000..7af06b2b8 --- /dev/null +++ b/tests/tcg/xtensa/test_flix.S @@ -0,0 +1,77 @@ +#include "macros.inc" + +test_suite flix + +#if XCHAL_HAVE_FLIX3 + +test misc + { + mov a3, a4 + mov a2, a3 + nop + } + { + nop + bne.w18 a2, a3, 1f + } + movi a2, 1f + { + mov a2, a3 + mov a3, a2 + nop + } + { + l32i a2, a3, 0 + add a4, a4, a2 + nop + } + { + mov a3, a4 + jx a3 + nop + } +1: +test_end + +test sum + + movi a2, 0 + movi a3, 2f + movi a4, 0 + movi a5, 4 + + loop a5, 1f + { + l32i a2, a3, 0 + addi a3, a3, 4 + add a4, a4, a2 + } +1: + add a4, a4, a2 + assert eqi, a4, 10 + .data +2: + .word 1, 2, 3, 4 + .previous +test_end + +test rep_dependency + + { + movi a2, 1 + movi a3, 2 + nop + } + { + or a2, a3, a3 + or a3, a2, a2 + nop + } + assert eqi, a2, 2 + assert eqi, a3, 1 + +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_fp0_arith.S b/tests/tcg/xtensa/test_fp0_arith.S new file mode 100644 index 000000000..7eefc1da4 --- /dev/null +++ b/tests/tcg/xtensa/test_fp0_arith.S @@ -0,0 +1,261 @@ +#include "macros.inc" +#include "fpu.h" + +test_suite fp0_arith + +#if XCHAL_HAVE_FP + +.macro movfp fr, v + movi a2, \v + wfr \fr, a2 +.endm + +.macro check_res fr, r, sr + rfr a2, \fr + dump a2 + movi a3, \r + assert eq, a2, a3 + rur a2, fsr +#if DFPU + movi a3, \sr + assert eq, a2, a3 +#else + assert eqi, a2, 0 +#endif +.endm + +test add_s + movi a2, 1 + wsr a2, cpenable + + test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \ + 0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001, \ + FSR_I, FSR_I, FSR_I, FSR_I + test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \ + 0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002, \ + FSR_I, FSR_I, FSR_I, FSR_I + + /* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */ + test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \ + 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \ + FSR_OI, FSR_OI, FSR_OI, FSR_OI +test_end + +test add_s_inf + /* 1 + +inf = +inf */ + test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \ + 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000, \ + FSR__, FSR__, FSR__, FSR__ + + /* +inf + -inf = default NaN */ + test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \ + 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +#if DFPU +test add_s_nan_dfpu + /* 1 + QNaN = QNaN */ + test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR__, FSR__, FSR__, FSR__ + /* 1 + SNaN = QNaN */ + test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR_V, FSR_V, FSR_V, FSR_V + + /* SNaN1 + SNaN2 = QNaN2 */ + test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \ + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \ + FSR_V, FSR_V, FSR_V, FSR_V + test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR_V, FSR_V, FSR_V, FSR_V + /* QNaN1 + SNaN2 = QNaN2 */ + test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \ + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \ + FSR_V, FSR_V, FSR_V, FSR_V + /* SNaN1 + QNaN2 = QNaN2 */ + test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end +#else +test add_s_nan_fpu2k + /* 1 + QNaN = QNaN */ + test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR__, FSR__, FSR__, FSR__ + /* 1 + SNaN = SNaN */ + test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \ + 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \ + FSR__, FSR__, FSR__, FSR__ + /* SNaN1 + SNaN2 = SNaN1 */ + test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \ + 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \ + FSR__, FSR__, FSR__, FSR__ + test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \ + 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \ + FSR__, FSR__, FSR__, FSR__ + /* QNaN1 + SNaN2 = QNaN1 */ + test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR__, FSR__, FSR__, FSR__ + /* SNaN1 + QNaN2 = SNaN1 */ + test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \ + 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \ + FSR__, FSR__, FSR__, FSR__ +test_end +#endif + +test sub_s + test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \ + 0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000, \ + FSR_I, FSR_I, FSR_I, FSR_I + test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \ + 0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001, \ + FSR_I, FSR_I, FSR_I, FSR_I + + /* norm - norm = denorm */ + test_op2 sub.s, f6, f7, f8, 0x00800001, 0x00800000, \ + 0x00000001, 0x00000001, 0x00000001, 0x00000001, \ + FSR__, FSR__, FSR__, FSR__ +test_end + +test mul_s + test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \ + 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \ + FSR_I, FSR_I, FSR_I, FSR_I + /* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */ + test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \ + 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \ + FSR_OI, FSR_OI, FSR_OI, FSR_OI + /* min norm * min norm = 0/denorm */ + test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \ + 0x00000000, 0x00000000, 0x00000001, 0x00000000, \ + FSR_UI, FSR_UI, FSR_UI, FSR_UI + /* inf * 0 = default NaN */ + test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \ + 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +test madd_s + test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \ + 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \ + FSR_I, FSR_I, FSR_I, FSR_I +test_end + +test madd_s_precision + test_op3 madd.s, f0, f1, f2, f0, 0xbf800002, 0x3f800001, 0x3f800001, \ + 0x28800000, 0x28800000, 0x28800000, 0x28800000, \ + FSR__, FSR__, FSR__, FSR__ +test_end + +#if DFPU +test madd_s_nan_dfpu + /* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \ + F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \ + F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \ + F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + + /* inf * 0 = default NaN */ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \ + F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V + /* inf * 0 + SNaN1 = QNaN1 */ + test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_PINF, F32_0, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + /* inf * 0 + QNaN1 = QNaN1 */ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_PINF, F32_0, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + + /* madd/msub SNaN turns to QNaN and sets Invalid flag */ + test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end +#else +test madd_s_nan_fpu2k + /* FPU2000 madd/msub NaN1, NaN2, NaN3 priority: NaN2, NaN3, NaN1 */ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \ + F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \ + F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \ + F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \ + F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \ + F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \ + F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + + /* inf * 0 = default NaN */ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \ + F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \ + FSR__, FSR__, FSR__, FSR__ + /* inf * 0 + SNaN1 = SNaN1 */ + test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_PINF, F32_0, \ + F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + /* inf * 0 + QNaN1 = QNaN1 */ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_PINF, F32_0, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + + /* madd/msub SNaN is preserved */ + test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \ + F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \ + F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), \ + FSR__, FSR__, FSR__, FSR__ +test_end +#endif + +test msub_s + test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \ + 0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001, \ + FSR_I, FSR_I, FSR_I, FSR_I +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_fp0_conv.S b/tests/tcg/xtensa/test_fp0_conv.S new file mode 100644 index 000000000..cfee6e517 --- /dev/null +++ b/tests/tcg/xtensa/test_fp0_conv.S @@ -0,0 +1,315 @@ +#include "macros.inc" +#include "fpu.h" + +test_suite fp0_conv + +#if XCHAL_HAVE_FP + +.macro movfp fr, v + movi a2, \v + wfr \fr, a2 +.endm + +.macro test_ftoi_ex op, r0, fr0, v, c, r, sr + movi a2, 0 + wur a2, fsr + movfp \fr0, \v + \op \r0, \fr0, \c + dump \r0 + movi a3, \r + assert eq, \r0, a3 + rur a2, fsr +#if DFPU + movi a3, \sr + assert eq, a2, a3 +#else + assert eqi, a2, 0 +#endif +.endm + +.macro test_ftoi op, r0, fr0, v, c, r, sr + movi a2, 0 + wur a2, fcr + test_ftoi_ex \op, \r0, \fr0, \v, \c, \r, \sr + movi a2, 0x7c + wur a2, fcr + test_ftoi_ex \op, \r0, \fr0, \v, \c, \r, \sr +.endm + + +.macro test_itof_ex op, fr0, ar0, v, c, r, sr + movi a2, 0 + wur a2, fsr + movi \ar0, \v + \op \fr0, \ar0, \c + + rfr a2, \fr0 + dump a2 + movi a3, \r + assert eq, a2, a3 + rur a2, fsr +#if DFPU + movi a3, \sr + assert eq, a2, a3 +#else + assert eqi, a2, 0 +#endif +.endm + +.macro test_itof_rm op, fr0, ar0, v, c, rm, r, sr + movi a2, \rm + wur a2, fcr + test_itof_ex \op, \fr0, \ar0, \v, \c, \r, \sr + movi a2, (\rm) | 0x7c + wur a2, fcr + test_itof_ex \op, \fr0, \ar0, \v, \c, \r, \sr +.endm + +.macro test_itof op, fr0, ar0, v, c, r0, r1, r2, r3, sr + test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0, \sr + test_itof_rm \op, \fr0, \ar0, \v, \c, 1, \r1, \sr + test_itof_rm \op, \fr0, \ar0, \v, \c, 2, \r2, \sr + test_itof_rm \op, \fr0, \ar0, \v, \c, 3, \r3, \sr +.endm + +test round_s + movi a2, 1 + wsr a2, cpenable + + /* NaN */ + test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V + test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V + + /* -inf */ + test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V + + /* negative overflow */ + test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V + test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__ + test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__ + + /* negative */ + test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */ + test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2, FSR_I /* -1.5 */ + test_ftoi round.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */ + test_ftoi round.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */ + test_ftoi round.s, a2, f0, 0xbf400000, 0, -1, FSR_I /* -0.75 */ + test_ftoi round.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */ + + /* positive */ + test_ftoi round.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */ + test_ftoi round.s, a2, f0, 0x3f400000, 0, 1, FSR_I /* 0.75 */ + test_ftoi round.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */ + test_ftoi round.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */ + test_ftoi round.s, a2, f0, 0x3fc00000, 0, 2, FSR_I /* 1.5 */ + test_ftoi round.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */ + + /* positive overflow */ + test_ftoi round.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__ + test_ftoi round.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V + test_ftoi round.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V + + /* +inf */ + test_ftoi round.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V + + /* NaN */ + test_ftoi round.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V + test_ftoi round.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V +test_end + +test trunc_s + /* NaN */ + test_ftoi trunc.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V + test_ftoi trunc.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V + + /* -inf */ + test_ftoi trunc.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V + + /* negative overflow */ + test_ftoi trunc.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V + test_ftoi trunc.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__ + test_ftoi trunc.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__ + + /* negative */ + test_ftoi trunc.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */ + test_ftoi trunc.s, a2, f0, 0xbfc00000, 0, -1, FSR_I /* -1.5 */ + test_ftoi trunc.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */ + test_ftoi trunc.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */ + test_ftoi trunc.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */ + test_ftoi trunc.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */ + + /* positive */ + test_ftoi trunc.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */ + test_ftoi trunc.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */ + test_ftoi trunc.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */ + test_ftoi trunc.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */ + test_ftoi trunc.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */ + test_ftoi trunc.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */ + + /* positive overflow */ + test_ftoi trunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__ + test_ftoi trunc.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V + test_ftoi trunc.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V + + /* +inf */ + test_ftoi trunc.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V + + /* NaN */ + test_ftoi trunc.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V + test_ftoi trunc.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V +test_end + +test floor_s + /* NaN */ + test_ftoi floor.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V + test_ftoi floor.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V + + /* -inf */ + test_ftoi floor.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V + + /* negative overflow */ + test_ftoi floor.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V + test_ftoi floor.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__ + test_ftoi floor.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__ + + /* negative */ + test_ftoi floor.s, a2, f0, 0xbfa00000, 1, -3, FSR_I /* -1.25 * 2 */ + test_ftoi floor.s, a2, f0, 0xbfc00000, 0, -2, FSR_I /* -1.5 */ + test_ftoi floor.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */ + test_ftoi floor.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */ + test_ftoi floor.s, a2, f0, 0xbf400000, 0, -1, FSR_I /* -0.75 */ + test_ftoi floor.s, a2, f0, 0xbf000000, 0, -1, FSR_I /* -0.5 */ + + /* positive */ + test_ftoi floor.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */ + test_ftoi floor.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */ + test_ftoi floor.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */ + test_ftoi floor.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */ + test_ftoi floor.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */ + test_ftoi floor.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */ + + /* positive overflow */ + test_ftoi floor.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__ + test_ftoi floor.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V + test_ftoi floor.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V + + /* +inf */ + test_ftoi floor.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V + + /* NaN */ + test_ftoi floor.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V + test_ftoi floor.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V +test_end + +test ceil_s + /* NaN */ + test_ftoi ceil.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V + test_ftoi ceil.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V + + /* -inf */ + test_ftoi ceil.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V + + /* negative overflow */ + test_ftoi ceil.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V + test_ftoi ceil.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__ + test_ftoi ceil.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__ + + /* negative */ + test_ftoi ceil.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */ + test_ftoi ceil.s, a2, f0, 0xbfc00000, 0, -1, FSR_I /* -1.5 */ + test_ftoi ceil.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */ + test_ftoi ceil.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */ + test_ftoi ceil.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */ + test_ftoi ceil.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */ + + /* positive */ + test_ftoi ceil.s, a2, f0, 0x3f000000, 0, 1, FSR_I /* 0.5 */ + test_ftoi ceil.s, a2, f0, 0x3f400000, 0, 1, FSR_I /* 0.75 */ + test_ftoi ceil.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */ + test_ftoi ceil.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */ + test_ftoi ceil.s, a2, f0, 0x3fc00000, 0, 2, FSR_I /* 1.5 */ + test_ftoi ceil.s, a2, f0, 0x3fa00000, 1, 3, FSR_I /* 1.25 * 2 */ + + /* positive overflow */ + test_ftoi ceil.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__ + test_ftoi ceil.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V + test_ftoi ceil.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V + + /* +inf */ + test_ftoi ceil.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V + + /* NaN */ + test_ftoi ceil.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V + test_ftoi ceil.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V +test_end + +test utrunc_s + /* NaN */ + test_ftoi utrunc.s, a2, f0, 0xffc00001, 0, 0xffffffff, FSR_V + test_ftoi utrunc.s, a2, f0, 0xff800001, 0, 0xffffffff, FSR_V + + /* -inf */ + test_ftoi utrunc.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V + + /* negative overflow */ + test_ftoi utrunc.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V + test_ftoi utrunc.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR_V + test_ftoi utrunc.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR_V + + /* negative */ + test_ftoi utrunc.s, a2, f0, 0xbfa00000, 1, -2, FSR_V /* -1.25 * 2 */ + test_ftoi utrunc.s, a2, f0, 0xbfc00000, 0, -1, FSR_V /* -1.5 */ + test_ftoi utrunc.s, a2, f0, 0xbf800000, 1, -2, FSR_V /* -1 * 2 */ + test_ftoi utrunc.s, a2, f0, 0xbf800000, 0, -1, FSR_V /* -1 */ + test_ftoi utrunc.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */ + test_ftoi utrunc.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */ + + /* positive */ + test_ftoi utrunc.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */ + test_ftoi utrunc.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */ + test_ftoi utrunc.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */ + test_ftoi utrunc.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */ + test_ftoi utrunc.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */ + test_ftoi utrunc.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */ + + /* positive overflow */ + test_ftoi utrunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__ + test_ftoi utrunc.s, a2, f0, 0x4f000000, 0, 0x80000000, FSR__ + test_ftoi utrunc.s, a2, f0, 0x4effffff, 1, 0xffffff00, FSR__ + test_ftoi utrunc.s, a2, f0, 0x4f800000, 1, 0xffffffff, FSR_V + + /* +inf */ + test_ftoi utrunc.s, a2, f0, 0x7f800000, 0, 0xffffffff, FSR_V + + /* NaN */ + test_ftoi utrunc.s, a2, f0, 0x7f800001, 0, 0xffffffff, FSR_V + test_ftoi utrunc.s, a2, f0, 0x7fc00000, 0, 0xffffffff, FSR_V +test_end + +test float_s + test_itof float.s, f0, a2, -1, 0, \ + 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000, FSR__ + test_itof float.s, f0, a2, 0, 0, 0, 0, 0, 0, FSR__ + test_itof float.s, f0, a2, 1, 1, \ + 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000, FSR__ + test_itof float.s, f0, a2, 1, 0, \ + 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, FSR__ + test_itof float.s, f0, a2, 0x7fffffff, 0, \ + 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff, FSR_I +test_end + +test ufloat_s + test_itof ufloat.s, f0, a2, 0, 0, 0, 0, 0, 0, FSR__ + test_itof ufloat.s, f0, a2, 1, 1, \ + 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000, FSR__ + test_itof ufloat.s, f0, a2, 1, 0, \ + 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, FSR__ + test_itof ufloat.s, f0, a2, 0x7fffffff, 0, \ + 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff, FSR_I + test_itof ufloat.s, f0, a2, 0xffffffff, 0, \ + 0x4f800000, 0x4f7fffff, 0x4f800000, 0x4f7fffff, FSR_I +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_fp0_div.S b/tests/tcg/xtensa/test_fp0_div.S new file mode 100644 index 000000000..c3e7ad7bb --- /dev/null +++ b/tests/tcg/xtensa/test_fp0_div.S @@ -0,0 +1,82 @@ +#include "macros.inc" +#include "fpu.h" + +test_suite fp0_div + +#if XCHAL_HAVE_FP_DIV + +.macro divs_seq q, a, b, r, y, y0, an, bn, e, ex + div0.s \y0, \b + nexp01.s \bn, \b + const.s \e, 1 + maddn.s \e, \bn, \y0 + mov.s \y, \y0 + mov.s \ex, \b + nexp01.s \an, \a + maddn.s \y, \e, \y0 + const.s \e, 1 + const.s \q, 0 + neg.s \r, \an + maddn.s \e, \bn, \y + maddn.s \q, \r, \y0 + mkdadj.s \ex, \a + maddn.s \y, \e, \y + maddn.s \r, \bn, \q + const.s \e, 1 + maddn.s \e, \bn, \y + maddn.s \q, \r, \y + neg.s \r, \an + maddn.s \y, \e, \y + maddn.s \r, \bn, \q + addexpm.s \q, \ex + addexp.s \y, \ex + divn.s \q, \r, \y +.endm + +.macro div_s fr0, fr1, fr2 + divs_seq \fr0, \fr1, \fr2, f9, f10, f11, f12, f13, f14, f15 +.endm + +.macro movfp fr, v + movi a2, \v + wfr \fr, a2 +.endm + +.macro check_res fr, r, sr + rfr a2, \fr + dump a2 + movi a3, \r + assert eq, a2, a3 + rur a2, fsr + movi a3, \sr + assert eq, a2, a3 +.endm + +test div_s + movi a2, 1 + wsr a2, cpenable + + test_op2 div_s, f0, f1, f2, 0x40000000, 0x40400000, \ + 0x3f2aaaab, 0x3f2aaaaa, 0x3f2aaaab, 0x3f2aaaaa, \ + FSR_I, FSR_I, FSR_I, FSR_I + test_op2 div_s, f3, f4, f5, F32_1, F32_0, \ + F32_PINF, F32_PINF, F32_PINF, F32_PINF, \ + FSR_Z, FSR_Z, FSR_Z, FSR_Z + test_op2 div_s, f6, f7, f8, F32_0, F32_0, \ + F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V + + /* MAX_FLOAT / 0.5 = +inf/MAX_FLOAT */ + test_op2 div_s, f0, f1, f2, F32_MAX, F32_0_5, \ + F32_PINF, F32_MAX, F32_PINF, F32_MAX, \ + FSR_OI, FSR_OI, FSR_OI, FSR_OI + + /* 0.5 / MAX_FLOAT = denorm */ + test_op2 div_s, f0, f1, f2, F32_0_5, F32_MAX, \ + 0x00100000, 0x00100000, 0x00100001, 0x00100000, \ + FSR_UI, FSR_UI, FSR_UI, FSR_UI +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_fp0_sqrt.S b/tests/tcg/xtensa/test_fp0_sqrt.S new file mode 100644 index 000000000..585973dce --- /dev/null +++ b/tests/tcg/xtensa/test_fp0_sqrt.S @@ -0,0 +1,76 @@ +#include "macros.inc" +#include "fpu.h" + +test_suite fp0_sqrt + +#if XCHAL_HAVE_FP_SQRT + +.macro sqrt_seq r, a, y, t1, hn, h2, t5, h + sqrt0.s \y, \a + const.s \t1, 0 + maddn.s \t1, \y, \y + nexp01.s \hn, \a + const.s \r, 3 + addexp.s \hn, \r + maddn.s \r, \t1, \hn + nexp01.s \t1, \a + neg.s \h2, \t1 + maddn.s \y, \r, \y + const.s \r, 0 + const.s \t5, 0 + const.s \h, 0 + maddn.s \r, \h2, \y + maddn.s \t5, \y, \hn + const.s \hn, 3 + maddn.s \h, \hn, \y + maddn.s \t1, \r, \r + maddn.s \hn, \t5, \y + neg.s \y, \h + maddn.s \r, \t1, \y + maddn.s \h, \hn, \h + mksadj.s \y, \a + nexp01.s \a, \a + maddn.s \a, \r, \r + neg.s \t1, \h + addexpm.s \r, \y + addexp.s \t1, \y + divn.s \r, \a, \t1 +.endm + +.macro sqrt_s fr0, fr1 + sqrt_seq \fr0, \fr1, f10, f11, f12, f13, f14, f15 +.endm + +.macro movfp fr, v + movi a2, \v + wfr \fr, a2 +.endm + +.macro check_res fr, r, sr + rfr a2, \fr + dump a2 + movi a3, \r + assert eq, a2, a3 + rur a2, fsr + movi a3, \sr + assert eq, a2, a3 +.endm + +test sqrt_s + movi a2, 1 + wsr a2, cpenable + + test_op1 sqrt_s, f0, f1, 0x40000000, \ + 0x3fb504f3, 0x3fb504f3, 0x3fb504f4, 0x3fb504f3, \ + FSR_I, FSR_I, FSR_I, FSR_I + test_op1 sqrt_s, f3, f4, F32_1, \ + F32_1, F32_1, F32_1, F32_1, \ + FSR__, FSR__, FSR__, FSR__ + test_op1 sqrt_s, f6, f7, F32_MINUS | F32_1, \ + F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_fp1.S b/tests/tcg/xtensa/test_fp1.S new file mode 100644 index 000000000..77336a3fc --- /dev/null +++ b/tests/tcg/xtensa/test_fp1.S @@ -0,0 +1,147 @@ +#include "macros.inc" +#include "fpu.h" + +test_suite fp1 + +#if XCHAL_HAVE_FP + +.macro movfp fr, v + movi a2, \v + wfr \fr, a2 +.endm + +.macro test_ord_ex op, br, fr0, fr1, v0, v1, r, sr + movi a2, 0 + wur a2, fsr + movfp \fr0, \v0 + movfp \fr1, \v1 + \op \br, \fr0, \fr1 + movi a2, 0 + movi a3, 1 + movt a2, a3, \br + assert eqi, a2, \r + rur a2, fsr +#if DFPU + movi a3, \sr + assert eq, a2, a3 +#else + assert eqi, a2, 0 +#endif +.endm + +.macro test_ord op, br, fr0, fr1, v0, v1, r, sr + movi a2, 0 + wur a2, fcr + test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr + movi a2, 0x7c + wur a2, fcr + test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr +.endm + +.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI, qnan_sr + test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa, FSR__ /* ord == ord */ + test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab, FSR__ /* ord < ord */ + test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba, FSR__ /* ord > ord */ + test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI, FSR__ /* ord +INF */ + test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa, FSR__ /* +INF ord */ + test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN, \qnan_sr /* ord -QNaN */ + test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN, FSR_V /* ord -SNaN */ + test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN, FSR_V /* ord +SNaN */ + test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN, \qnan_sr /* ord +QNaN */ + test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na, \qnan_sr /* -QNaN ord */ + test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na, FSR_V /* -SNaN ord */ + test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na, FSR_V /* +SNaN ord */ + test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na, \qnan_sr /* +QNaN ord */ + test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II, FSR__ /* +INF +INF */ + test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN, \qnan_sr /* +INF +QNaN */ + test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI, \qnan_sr /* +QNaN +INF */ +.endm + +test un_s + movi a2, 1 + wsr a2, cpenable + test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, FSR__ +test_end + +test oeq_s + test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, FSR__ +test_end + +test ueq_s + test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, FSR__ +test_end + +test olt_s + test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, FSR_V +test_end + +test ult_s + test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, FSR__ +test_end + +test ole_s + test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, FSR_V +test_end + +test ule_s + test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, FSR__ +test_end + +.macro test_cond op, fr0, fr1, cr, v0, v1, r + movfp \fr0, \v0 + movfp \fr1, \v1 + \op \fr0, \fr1, \cr + rfr a2, \fr0 + movi a3, \r + assert eq, a2, a3 +.endm + +test moveqz_s + movi a3, 0 + test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000 + movi a3, 1 + test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0 +test_end + +test movnez_s + movi a3, 0 + test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0 + movi a3, 1 + test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000 +test_end + +test movltz_s + movi a3, -1 + test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000 + movi a3, 0 + test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0 + movi a3, 1 + test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0 +test_end + +test movgez_s + movi a3, -1 + test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0 + movi a3, 0 + test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000 + movi a3, 1 + test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000 +test_end + +test movf_s + olt.s b0, f0, f0 + test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000 + ueq.s b0, f0, f0 + test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0 +test_end + +test movt_s + ueq.s b0, f0, f0 + test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000 + olt.s b0, f0, f0 + test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_fp_cpenable.S b/tests/tcg/xtensa/test_fp_cpenable.S new file mode 100644 index 000000000..882bb2f3c --- /dev/null +++ b/tests/tcg/xtensa/test_fp_cpenable.S @@ -0,0 +1,27 @@ +#include "macros.inc" + +test_suite fp_cpenable + +#if XCHAL_HAVE_FP + +test rur + set_vector kernel, 2f + movi a2, 0 + wsr a2, cpenable + isync +1: + rur a2, fsr + //wfr f0, a2 + test_fail +2: + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + movi a2, 32 + rsr a3, exccause + assert eq, a2, a3 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_interrupt.S b/tests/tcg/xtensa/test_interrupt.S new file mode 100644 index 000000000..efedc43f6 --- /dev/null +++ b/tests/tcg/xtensa/test_interrupt.S @@ -0,0 +1,259 @@ +#include "macros.inc" + +#define LSBIT(v) ((v) & -(v)) + +#define LEVEL_MASK(x) glue3(XCHAL_INTLEVEL, x, _MASK) +#define LEVEL_SOFT_MASK(x) (LEVEL_MASK(x) & XCHAL_INTTYPE_MASK_SOFTWARE) + +#define L1_SOFT_MASK LEVEL_SOFT_MASK(1) +#define L1_SOFT LSBIT(L1_SOFT_MASK) + +#if LEVEL_SOFT_MASK(2) +#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(2) +#elif LEVEL_SOFT_MASK(3) +#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(3) +#elif LEVEL_SOFT_MASK(4) +#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(4) +#elif LEVEL_SOFT_MASK(5) +#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(5) +#elif LEVEL_SOFT_MASK(6) +#define HIGH_LEVEL_SOFT_MASK LEVEL_SOFT_MASK(6) +#else +#define HIGH_LEVEL_SOFT_MASK 0 +#endif + +#define HIGH_LEVEL_SOFT LSBIT(HIGH_LEVEL_SOFT_MASK) + +#if LEVEL_SOFT_MASK(2) +#define HIGH_LEVEL_SOFT_LEVEL 2 +#elif LEVEL_SOFT_MASK(3) +#define HIGH_LEVEL_SOFT_LEVEL 3 +#elif LEVEL_SOFT_MASK(4) +#define HIGH_LEVEL_SOFT_LEVEL 4 +#elif LEVEL_SOFT_MASK(5) +#define HIGH_LEVEL_SOFT_LEVEL 5 +#elif LEVEL_SOFT_MASK(6) +#define HIGH_LEVEL_SOFT_LEVEL 6 +#else +#define HIGH_LEVEL_SOFT_LEVEL 0 +#endif + +test_suite interrupt + +#if XCHAL_HAVE_INTERRUPTS + +.macro clear_interrupts + movi a2, 0 + wsr a2, intenable +#if XCHAL_NUM_TIMERS + wsr a2, ccompare0 +#endif +#if XCHAL_NUM_TIMERS > 1 + wsr a2, ccompare1 +#endif +#if XCHAL_NUM_TIMERS > 2 + wsr a2, ccompare2 +#endif + esync + rsr a2, interrupt + wsr a2, intclear + + esync + rsr a2, interrupt + assert eqi, a2, 0 +.endm + +.macro check_l1 + rsr a2, ps + movi a3, 0x1f /* EXCM | INTMASK */ + and a2, a2, a3 + assert eqi, a2, 0x10 /* only EXCM is set for level-1 interrupt */ + rsr a2, exccause + assert eqi, a2, 4 +.endm + +test rsil + clear_interrupts + + rsr a2, ps + rsil a3, 7 + rsr a4, ps + assert eq, a2, a3 + movi a2, 0xf + and a2, a4, a2 + assert eqi, a2, 7 + xor a3, a3, a4 + movi a2, 0xfffffff0 + and a2, a3, a2 + assert eqi, a2, 0 +test_end + +#if L1_SOFT +test soft_disabled + set_vector kernel, 1f + clear_interrupts + + movi a2, L1_SOFT + wsr a2, intset + esync + rsr a3, interrupt + movi a4, ~XCHAL_INTTYPE_MASK_TIMER + and a3, a3, a4 + assert eq, a2, a3 + wsr a2, intclear + esync + rsr a3, interrupt + and a3, a3, a4 + assert eqi, a3, 0 + j 2f +1: + test_fail +2: +test_end + +test soft_intenable + set_vector kernel, 1f + clear_interrupts + + movi a2, L1_SOFT + wsr a2, intset + esync + rsr a3, interrupt + movi a4, ~XCHAL_INTTYPE_MASK_TIMER + and a3, a3, a4 + assert eq, a2, a3 + rsil a3, 0 + wsr a2, intenable + esync + test_fail +1: + check_l1 +test_end + +test soft_rsil + set_vector kernel, 1f + clear_interrupts + + movi a2, L1_SOFT + wsr a2, intset + esync + rsr a3, interrupt + movi a4, ~XCHAL_INTTYPE_MASK_TIMER + and a3, a3, a4 + assert eq, a2, a3 + wsr a2, intenable + rsil a3, 0 + esync + test_fail +1: + check_l1 +test_end + +test soft_waiti + set_vector kernel, 1f + clear_interrupts + + movi a2, L1_SOFT + wsr a2, intset + esync + rsr a3, interrupt + movi a4, ~XCHAL_INTTYPE_MASK_TIMER + and a3, a3, a4 + assert eq, a2, a3 + wsr a2, intenable + waiti 0 + test_fail +1: + check_l1 +test_end + +test soft_user + set_vector kernel, 1f + set_vector user, 2f + clear_interrupts + + movi a2, L1_SOFT + wsr a2, intset + esync + rsr a3, interrupt + movi a4, ~XCHAL_INTTYPE_MASK_TIMER + and a3, a3, a4 + assert eq, a2, a3 + wsr a2, intenable + + rsr a2, ps + movi a3, 0x20 + or a2, a2, a3 + wsr a2, ps + waiti 0 +1: + test_fail +2: + check_l1 +test_end + +#if HIGH_LEVEL_SOFT +test soft_priority + set_vector kernel, 1f + set_vector glue(level, HIGH_LEVEL_SOFT_LEVEL), 2f + clear_interrupts + + movi a2, L1_SOFT | HIGH_LEVEL_SOFT + wsr a2, intenable + rsil a3, 0 + esync + wsr a2, intset + esync +1: + test_fail +2: + rsr a2, ps + movi a3, 0x1f /* EXCM | INTMASK */ + and a2, a2, a3 + movi a3, 0x10 | HIGH_LEVEL_SOFT_LEVEL + assert eq, a2, a3 /* EXCM and INTMASK are set + for high-priority interrupt */ +test_end +#endif +#endif + +#if HIGH_LEVEL_SOFT +test eps_epc_rfi + set_vector glue(level, HIGH_LEVEL_SOFT_LEVEL), 3f + clear_interrupts + reset_ps + + movi a2, L1_SOFT_MASK | HIGH_LEVEL_SOFT_MASK + wsr a2, intenable + rsil a3, 0 + rsr a3, ps + esync + wsr a2, intset +1: + esync +2: + test_fail +3: + rsr a2, glue(eps, HIGH_LEVEL_SOFT_LEVEL) + assert eq, a2, a3 + rsr a2, glue(epc, HIGH_LEVEL_SOFT_LEVEL) + movi a3, 1b + assert ge, a2, a3 + movi a3, 2b + assert ge, a3, a2 + movi a2, 4f + wsr a2, glue(epc, HIGH_LEVEL_SOFT_LEVEL) + movi a2, 0x40000 | HIGH_LEVEL_SOFT_LEVEL + wsr a2, glue(eps, HIGH_LEVEL_SOFT_LEVEL) + rfi HIGH_LEVEL_SOFT_LEVEL + test_fail +4: + rsr a2, ps + movi a3, 0x40000 | HIGH_LEVEL_SOFT_LEVEL + assert eq, a2, a3 +test_end +#endif + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_load_store.S b/tests/tcg/xtensa/test_load_store.S new file mode 100644 index 000000000..b339f40f1 --- /dev/null +++ b/tests/tcg/xtensa/test_load_store.S @@ -0,0 +1,221 @@ +#include "macros.inc" + +test_suite load_store + +.macro load_ok_test op, type, data, value + .data + .align 4 +1: + \type \data + .previous + + reset_ps + set_vector kernel, 0 + movi a3, 1b + addi a4, a4, 1 + mov a5, a4 + \op a5, a3, 0 + movi a6, \value + assert eq, a5, a6 +.endm + +#if XCHAL_UNALIGNED_LOAD_EXCEPTION +.macro load_unaligned_test will_trap, op, type, data, value + .data + .align 4 + .byte 0 +1: + \type \data + .previous + + reset_ps + .ifeq \will_trap + set_vector kernel, 0 + .else + set_vector kernel, 2f + .endif + movi a3, 1b + addi a4, a4, 1 + mov a5, a4 +1: + \op a5, a3, 0 + .ifeq \will_trap + movi a6, \value + assert eq, a5, a6 + .else + test_fail +2: + rsr a6, exccause + movi a7, 9 + assert eq, a6, a7 + rsr a6, epc1 + movi a7, 1b + assert eq, a6, a7 + rsr a6, excvaddr + assert eq, a6, a3 + assert eq, a5, a4 + .endif + reset_ps +.endm +#else +.macro load_unaligned_test will_trap, op, type, data, value + .data + .align 4 +1: + \type \data + .previous + + reset_ps + set_vector kernel, 0 + movi a3, 1b + 1 + addi a4, a4, 1 + mov a5, a4 + \op a5, a3, 0 + movi a6, \value + assert eq, a5, a6 +.endm +#endif + +.macro store_ok_test op, type, value + .data + .align 4 + .byte 0, 0, 0, 0x55 +1: + \type 0 +2: + .byte 0xaa + .previous + + reset_ps + set_vector kernel, 0 + movi a3, 1b + movi a5, \value + \op a5, a3, 0 + movi a3, 2b + l8ui a5, a3, 0 + movi a6, 0xaa + assert eq, a5, a6 + movi a3, 1b - 1 + l8ui a5, a3, 0 + movi a6, 0x55 + assert eq, a5, a6 +.endm + +#if XCHAL_UNALIGNED_STORE_EXCEPTION +.macro store_unaligned_test will_trap, op, nop, type, value + .data + .align 4 + .byte 0x55 +1: + \type 0 +2: + .byte 0xaa + .previous + + reset_ps + .ifeq \will_trap + set_vector kernel, 0 + .else + set_vector kernel, 4f + .endif + movi a3, 1b + movi a5, \value +3: + \op a5, a3, 0 + .ifne \will_trap + test_fail +4: + rsr a6, exccause + movi a7, 9 + assert eq, a6, a7 + rsr a6, epc1 + movi a7, 3b + assert eq, a6, a7 + rsr a6, excvaddr + assert eq, a6, a3 + l8ui a5, a3, 0 + assert eqi, a5, 0 + .endif + reset_ps + movi a3, 2b + l8ui a5, a3, 0 + movi a6, 0xaa + assert eq, a5, a6 + movi a3, 1b - 1 + l8ui a5, a3, 0 + movi a6, 0x55 + assert eq, a5, a6 +.endm +#else +.macro store_unaligned_test will_trap, sop, lop, type, value + .data + .align 4 + .byte 0x55 +1: + \type 0 + .previous + + reset_ps + set_vector kernel, 0 + movi a3, 1b + movi a5, \value + \sop a5, a3, 0 + movi a3, 1b - 1 + \lop a6, a3, 0 + assert eq, a5, a6 +.endm +#endif + +test load_ok + load_ok_test l16si, .short, 0x00001234, 0x00001234 + load_ok_test l16si, .short, 0x000089ab, 0xffff89ab + load_ok_test l16ui, .short, 0x00001234, 0x00001234 + load_ok_test l16ui, .short, 0x000089ab, 0x000089ab + load_ok_test l32i, .word, 0x12345678, 0x12345678 +#if XCHAL_HAVE_RELEASE_SYNC + load_ok_test l32ai, .word, 0x12345678, 0x12345678 +#endif +test_end + +#undef WILL_TRAP +#if XCHAL_UNALIGNED_LOAD_HW +#define WILL_TRAP 0 +#else +#define WILL_TRAP 1 +#endif + +test load_unaligned + load_unaligned_test WILL_TRAP, l16si, .short, 0x00001234, 0x00001234 + load_unaligned_test WILL_TRAP, l16si, .short, 0x000089ab, 0xffff89ab + load_unaligned_test WILL_TRAP, l16ui, .short, 0x00001234, 0x00001234 + load_unaligned_test WILL_TRAP, l16ui, .short, 0x000089ab, 0x000089ab + load_unaligned_test WILL_TRAP, l32i, .word, 0x12345678, 0x12345678 +#if XCHAL_HAVE_RELEASE_SYNC + load_unaligned_test 1, l32ai, .word, 0x12345678, 0x12345678 +#endif +test_end + +test store_ok + store_ok_test s16i, .short, 0x00001234 + store_ok_test s32i, .word, 0x12345678 +#if XCHAL_HAVE_RELEASE_SYNC + store_ok_test s32ri, .word, 0x12345678 +#endif +test_end + +#undef WILL_TRAP +#if XCHAL_UNALIGNED_STORE_HW +#define WILL_TRAP 0 +#else +#define WILL_TRAP 1 +#endif + +test store_unaligned + store_unaligned_test WILL_TRAP, s16i, l16ui, .short, 0x00001234 + store_unaligned_test WILL_TRAP, s32i, l32i, .word, 0x12345678 +#if XCHAL_HAVE_RELEASE_SYNC + store_unaligned_test 1, s32ri, l32i, .word, 0x12345678 +#endif +test_end + +test_suite_end diff --git a/tests/tcg/xtensa/test_loop.S b/tests/tcg/xtensa/test_loop.S new file mode 100644 index 000000000..0cfd8661e --- /dev/null +++ b/tests/tcg/xtensa/test_loop.S @@ -0,0 +1,167 @@ +#include "macros.inc" + +test_suite loop + +#if XCHAL_HAVE_LOOPS + +test loop + movi a2, 0 + movi a3, 5 + loop a3, 1f + addi a2, a2, 1 +1: + assert eqi, a2, 5 +test_end + +test loop0 + movi a2, 0 + loop a2, 1f + rsr a2, lcount + assert eqi, a2, -1 + j 1f +1: +test_end + +test loop_jump + movi a2, 0 + movi a3, 5 + loop a3, 1f + addi a2, a2, 1 + j 1f +1: + assert eqi, a2, 1 +test_end + +test loop_branch + movi a2, 0 + movi a3, 5 + loop a3, 1f + addi a2, a2, 1 + beqi a2, 3, 1f +1: + assert eqi, a2, 3 +test_end + +test loop_manual + movi a2, 0 + movi a3, 5 + movi a4, 1f + movi a5, 2f + wsr a3, lcount + wsr a4, lbeg + wsr a5, lend + isync + j 1f +.align 4 +1: + addi a2, a2, 1 +2: + assert eqi, a2, 6 +test_end + +test loop_excm + movi a2, 0 + movi a3, 5 + rsr a4, ps + movi a5, 0x10 + or a4, a4, a5 + wsr a4, ps + isync + loop a3, 1f + addi a2, a2, 1 +1: + xor a4, a4, a5 + isync + wsr a4, ps + assert eqi, a2, 1 +test_end + +test lbeg_invalidation + movi a2, 0 + movi a3, 1 + movi a4, 1f + movi a5, 3f + wsr a3, lcount + wsr a4, lbeg + wsr a5, lend + isync + j 1f +.align 4 +1: + addi a2, a2, 1 + j 2f +.align 4 +2: + addi a2, a2, 2 + movi a3, 2b + wsr a3, lbeg + isync + nop +3: + assert eqi, a2, 5 +test_end + +test lend_invalidation + movi a2, 0 + movi a3, 5 + movi a4, 1f + movi a5, 2f + wsr a3, lcount + wsr a4, lbeg + wsr a5, lend + isync + j 1f +.align 4 +1: + addi a2, a2, 1 +2: + beqi a3, 3, 1f + assert eqi, a2, 6 + movi a3, 3 + wsr a3, lcount + wsr a4, lend + isync + j 1b +1: + assert eqi, a2, 7 +test_end + +test loopnez + movi a2, 0 + movi a3, 5 + loopnez a3, 1f + addi a2, a2, 1 +1: + assert eqi, a2, 5 + + movi a2, 0 + movi a3, 0 + loopnez a3, 1f + test_fail +1: +test_end + +test loopgtz + movi a2, 0 + movi a3, 5 + loopgtz a3, 1f + addi a2, a2, 1 +1: + assert eqi, a2, 5 + + movi a2, 0 + movi a3, 0 + loopgtz a3, 1f + test_fail +1: + + movi a2, 0 + movi a3, 0x80000000 + loopgtz a3, 1f + test_fail +1: +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S new file mode 100644 index 000000000..348822bdd --- /dev/null +++ b/tests/tcg/xtensa/test_lsc.S @@ -0,0 +1,266 @@ +#include "macros.inc" +#include "fpu.h" + +test_suite lsc + +#if XCHAL_HAVE_FP + +test lsi + movi a2, 1 + wsr a2, cpenable + + movi a2, 1f + lsi f1, a2, 4 +#if DFPU + lsi f2, a2, 8 + lsip f0, a2, 8 +#else + lsi f0, a2, 0 + lsiu f2, a2, 8 +#endif + movi a3, 1f + 8 + assert eq, a2, a3 + rfr a2, f0 + movi a3, 0x3f800000 + assert eq, a2, a3 + rfr a2, f1 + movi a3, 0x40000000 + assert eq, a2, a3 + rfr a2, f2 + movi a3, 0x40400000 + assert eq, a2, a3 +.data + .align 4 +1: +.float 1, 2, 3 +.text +test_end + +test ssi + movi a2, 1f + movi a3, 0x40800000 + wfr f3, a3 + movi a3, 0x40a00000 + wfr f4, a3 + movi a3, 0x40c00000 + wfr f5, a3 + ssi f4, a2, 4 +#if DFPU + ssi f5, a2, 8 + ssip f3, a2, 8 +#else + ssi f3, a2, 0 + ssiu f5, a2, 8 +#endif + movi a3, 1f + 8 + assert eq, a2, a3 + l32i a4, a2, -8 + movi a3, 0x40800000 + assert eq, a4, a3 + l32i a4, a2, -4 + movi a3, 0x40a00000 + assert eq, a4, a3 + l32i a4, a2, 0 + movi a3, 0x40c00000 + assert eq, a4, a3 +.data + .align 4 +1: +.float 0, 0, 0 +.text +test_end + +test lsx + movi a2, 1f + movi a3, 0 + movi a4, 4 + movi a5, 8 + lsx f7, a2, a4 +#if DFPU + lsx f8, a2, a5 + lsxp f6, a2, a5 +#else + lsx f6, a2, a3 + lsxu f8, a2, a5 +#endif + movi a3, 1f + 8 + assert eq, a2, a3 + rfr a2, f6 + movi a3, 0x40e00000 + assert eq, a2, a3 + rfr a2, f7 + movi a3, 0x41000000 + assert eq, a2, a3 + rfr a2, f8 + movi a3, 0x41100000 + assert eq, a2, a3 +.data + .align 4 +1: +.float 7, 8, 9 +.text +test_end + +test ssx + movi a2, 1f + movi a4, 0x41200000 + wfr f9, a4 + movi a4, 0x41300000 + wfr f10, a4 + movi a4, 0x41400000 + wfr f11, a4 + movi a3, 0 + movi a4, 4 + movi a5, 8 + ssx f10, a2, a4 +#if DFPU + ssx f11, a2, a5 + ssxp f9, a2, a5 +#else + ssx f9, a2, a3 + ssxu f11, a2, a5 +#endif + movi a3, 1f + 8 + assert eq, a2, a3 + l32i a4, a2, -8 + movi a3, 0x41200000 + assert eq, a4, a3 + l32i a4, a2, -4 + movi a3, 0x41300000 + assert eq, a4, a3 + l32i a4, a2, 0 + movi a3, 0x41400000 + assert eq, a4, a3 +.data + .align 4 +1: +.float 0, 0, 0 +.text +test_end + +#endif + +#if XCHAL_HAVE_DFP + +#if XCHAL_HAVE_BE +#define F64_HIGH_OFF 0 +#else +#define F64_HIGH_OFF 4 +#endif + +.macro movdf fr, hi, lo + movi a2, \hi + movi a3, \lo + wfrd \fr, a2, a3 +.endm + +test ldi + movi a2, 1 + wsr a2, cpenable + + movi a2, 1f + ldi f1, a2, 8 + ldi f2, a2, 16 + ldip f0, a2, 16 + movi a3, 1f + 16 + assert eq, a2, a3 + rfrd a2, f0 + movi a3, 0x3ff00000 + assert eq, a2, a3 + rfrd a2, f1 + movi a3, 0x40000000 + assert eq, a2, a3 + rfrd a2, f2 + movi a3, 0x40080000 + assert eq, a2, a3 +.data + .align 8 +1: +.double 1, 2, 3 +.text +test_end + +test sdi + movdf f3, 0x40800000, 0 + movdf f4, 0x40a00000, 0 + movdf f5, 0x40c00000, 0 + movi a2, 1f + sdi f4, a2, 8 + sdi f5, a2, 16 + sdip f3, a2, 16 + movi a3, 1f + 16 + assert eq, a2, a3 + l32i a4, a2, -16 + F64_HIGH_OFF + movi a3, 0x40800000 + assert eq, a4, a3 + l32i a4, a2, -8 + F64_HIGH_OFF + movi a3, 0x40a00000 + assert eq, a4, a3 + l32i a4, a2, F64_HIGH_OFF + movi a3, 0x40c00000 + assert eq, a4, a3 +.data + .align 8 +1: +.double 0, 0, 0 +.text +test_end + +test ldx + movi a2, 1f + movi a3, 0 + movi a4, 8 + movi a5, 16 + ldx f7, a2, a4 + ldx f8, a2, a5 + ldxp f6, a2, a5 + movi a3, 1f + 16 + assert eq, a2, a3 + rfrd a2, f6 + movi a3, 0x401c0000 + assert eq, a2, a3 + rfrd a2, f7 + movi a3, 0x40200000 + assert eq, a2, a3 + rfrd a2, f8 + movi a3, 0x40220000 + assert eq, a2, a3 +.data + .align 8 +1: +.double 7, 8, 9 +.text +test_end + +test sdx + movdf f9, 0x41200000, 0 + movdf f10, 0x41300000, 0 + movdf f11, 0x41400000, 0 + movi a2, 1f + movi a3, 0 + movi a4, 8 + movi a5, 16 + sdx f10, a2, a4 + sdx f11, a2, a5 + sdxp f9, a2, a5 + movi a3, 1f + 16 + assert eq, a2, a3 + l32i a4, a2, -16 + F64_HIGH_OFF + movi a3, 0x41200000 + assert eq, a4, a3 + l32i a4, a2, -8 + F64_HIGH_OFF + movi a3, 0x41300000 + assert eq, a4, a3 + l32i a4, a2, F64_HIGH_OFF + movi a3, 0x41400000 + assert eq, a4, a3 +.data + .align 8 +1: +.double 0, 0, 0 +.text +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_mac16.S b/tests/tcg/xtensa/test_mac16.S new file mode 100644 index 000000000..ee0cedd2a --- /dev/null +++ b/tests/tcg/xtensa/test_mac16.S @@ -0,0 +1,247 @@ +#include "macros.inc" + +test_suite mac16 + +#if XCHAL_HAVE_MAC16 + +#define ext16(v) (((v) & 0xffff) | (((v) & 0x8000) * 0x1ffffffe)) +#define mul16(a, b) ((ext16(a) * ext16(b))) + +.macro assert_acc_value v + rsr a4, ACCLO + movi a5, (\v) & 0xffffffff + assert eq, a4, a5 + rsr a4, ACCHI + movi a5, (\v) >> 32 + sext a5, a5, 7 + assert eq, a4, a5 +.endm + +.macro init_reg sr, reg, val + .if (\sr) + movi a4, \val + wsr a4, \reg + .else + movi \reg, \val + .endif +.endm + +.macro test_mulxx mulop, comb, s, t, a, b + init_reg \comb & 2, \s, \a + init_reg \comb & 1, \t, \b + + \mulop\().ll \s, \t + assert_acc_value mul16(\a, \b) + + \mulop\().lh \s, \t + assert_acc_value mul16(\a, (\b >> 16)) + + \mulop\().hl \s, \t + assert_acc_value mul16((\a >> 16), \b) + + \mulop\().hh \s, \t + assert_acc_value mul16((\a >> 16), (\b >> 16)) +.endm + +test mul_aa + test_mulxx mul.aa, 0, a2, a3, 0xf7315a5a, 0xa5a5137f +test_end + +test mul_ad + test_mulxx mul.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f +test_end + +test mul_da + test_mulxx mul.da, 2, m1, a3, 0xf7315a5a, 0xa5a5137f +test_end + +test mul_dd + test_mulxx mul.dd, 3, m0, m3, 0xf7315a5a, 0xa5a5137f +test_end + + +.macro init_acc iv + movi a4, (\iv) & 0xffffffff + wsr a4, ACCLO + movi a4, (\iv) >> 32 + wsr a4, ACCHI +.endm + +.macro test_mulxxx mulop, comb, s, t, a, b, iv, op + init_reg \comb & 2, \s, \a + init_reg \comb & 1, \t, \b + + init_acc \iv + \mulop\().ll \s, \t + assert_acc_value (\iv \op mul16(\a, \b)) + + init_acc \iv + \mulop\().lh \s, \t + assert_acc_value (\iv \op mul16(\a, (\b >> 16))) + + init_acc \iv + \mulop\().hl \s, \t + assert_acc_value (\iv \op mul16((\a >> 16), \b)) + + init_acc \iv + \mulop\().hh \s, \t + assert_acc_value (\iv \op mul16((\a >> 16), (\b >> 16))) +.endm + + +test mula_aa + test_mulxxx mula.aa, 0, a2, a3, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, + +test_end + +test mula_ad + test_mulxxx mula.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, + +test_end + +test mula_da + test_mulxxx mula.da, 2, m1, a3, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + +test_end + +test mula_dd + test_mulxxx mula.dd, 3, m0, m3, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + +test_end + + +test muls_aa + test_mulxxx muls.aa, 0, a2, a3, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, - +test_end + +test muls_ad + test_mulxxx muls.ad, 1, a2, m2, 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, - +test_end + +test muls_da + test_mulxxx muls.da, 2, m1, a3, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, - +test_end + +test muls_dd + test_mulxxx muls.dd, 3, m0, m3, 0xf7315a5a, 0xa5a5137f, 0xfff73155aa, - +test_end + +test ldinc + movi a2, 1f - 4 + ldinc m0, a2 + movi a3, 1f + assert eq, a2, a3 + rsr a3, m0 + movi a4, 0x55aa137f + assert eq, a3, a4 + ldinc m1, a2 + movi a3, 1f + 4 + assert eq, a2, a3 + rsr a3, m1 + movi a4, 0x12345678 + assert eq, a3, a4 + +.data +1: .word 0x55aa137f, 0x12345678, 0x137fa5a5 +.text +test_end + +test lddec + movi a2, 1f + lddec m2, a2 + movi a3, 1f - 4 + assert eq, a2, a3 + rsr a3, m2 + movi a4, 0x12345678 + assert eq, a3, a4 + lddec m3, a2 + movi a3, 1f - 8 + assert eq, a2, a3 + rsr a3, m3 + movi a4, 0x55aa137f + assert eq, a3, a4 +.data + .word 0x55aa137f, 0x12345678 +1: +.text +test_end + + +.macro test_mulxxx_ld mulop, ldop, comb, w, x, s, t, a, b, iv, op + init_reg \comb & 2, \s, \a + init_reg \comb & 1, \t, \b + + init_acc \iv + \mulop\().ll.\ldop \w, \x, \s, \t + assert_acc_value (\iv \op mul16(\a, \b)) + + init_acc \iv + \mulop\().lh.\ldop \w, \x, \s, \t + assert_acc_value (\iv \op mul16(\a, (\b >> 16))) + + init_acc \iv + \mulop\().hl.\ldop \w, \x, \s, \t + assert_acc_value (\iv \op mul16((\a >> 16), \b)) + + init_acc \iv + \mulop\().hh.\ldop \w, \x, \s, \t + assert_acc_value (\iv \op mul16((\a >> 16), (\b >> 16))) +.endm + +test mula_da_ldinc + movi a2, 1f - 4 + test_mulxxx_ld mula.da, ldinc, 2, m1, a2, m1, a3, \ + 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + + movi a3, 1f + 12 + assert eq, a2, a3 + rsr a2, m1 + movi a3, 0x12345678 + assert eq, a2, a3 +.data +1: .word 0xf7315a5a, 0xf7315a5a, 0xf7315a5a, 0x12345678 +.text +test_end + +test mula_dd_ldinc + movi a2, 1f - 4 + test_mulxxx_ld mula.dd, ldinc, 3, m2, a2, m1, m2, \ + 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + + movi a3, 1f + 12 + assert eq, a2, a3 + rsr a2, m2 + movi a3, 0x12345678 + assert eq, a2, a3 +.data +1: .word 0xa5a5137f, 0xa5a5137f, 0xa5a5137f, 0x12345678 +.text +test_end + +test mula_da_lddec + movi a2, 1f + test_mulxxx_ld mula.da, lddec, 2, m1, a2, m1, a3, \ + 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + + movi a3, 1f - 16 + assert eq, a2, a3 + rsr a2, m1 + movi a3, 0x12345678 + assert eq, a2, a3 +.data + .word 0x12345678, 0xf7315a5a, 0xf7315a5a, 0xf7315a5a +1: +.text +test_end + +test mula_dd_lddec + movi a2, 1f + test_mulxxx_ld mula.dd, lddec, 3, m2, a2, m1, m2, \ + 0xf7315a5a, 0xa5a5137f, 0x0ff73155aa, + + movi a3, 1f - 16 + assert eq, a2, a3 + rsr a2, m2 + movi a3, 0x12345678 + assert eq, a2, a3 +.data + .word 0x12345678, 0xa5a5137f, 0xa5a5137f, 0xa5a5137f +1: +.text +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_max.S b/tests/tcg/xtensa/test_max.S new file mode 100644 index 000000000..f349d578e --- /dev/null +++ b/tests/tcg/xtensa/test_max.S @@ -0,0 +1,85 @@ +#include "macros.inc" + +test_suite max + +#if XCHAL_HAVE_MINMAX + +test max + movi a2, 0xffffffff + movi a3, 1 + movi a4, 1 + max a5, a2, a3 + assert eq, a5, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 1 + max a5, a2, a3 + assert eq, a5, a4 + + movi a2, 0xffffffff + movi a3, 1 + movi a4, 1 + max a2, a2, a3 + assert eq, a2, a4 + + movi a2, 0xffffffff + movi a3, 1 + movi a4, 1 + max a3, a2, a3 + assert eq, a3, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 1 + max a2, a2, a3 + assert eq, a2, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 1 + max a3, a2, a3 + assert eq, a3, a4 +test_end + +test maxu + movi a2, 0xffffffff + movi a3, 1 + movi a4, 0xffffffff + maxu a5, a2, a3 + assert eq, a5, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 0xffffffff + maxu a5, a2, a3 + assert eq, a5, a4 + + movi a2, 0xffffffff + movi a3, 1 + movi a4, 0xffffffff + maxu a2, a2, a3 + assert eq, a2, a4 + + movi a2, 0xffffffff + movi a3, 1 + movi a4, 0xffffffff + maxu a3, a2, a3 + assert eq, a3, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 0xffffffff + maxu a2, a2, a3 + assert eq, a2, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 0xffffffff + maxu a3, a2, a3 + assert eq, a3, a4 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_min.S b/tests/tcg/xtensa/test_min.S new file mode 100644 index 000000000..89ee10334 --- /dev/null +++ b/tests/tcg/xtensa/test_min.S @@ -0,0 +1,85 @@ +#include "macros.inc" + +test_suite min + +#if XCHAL_HAVE_MINMAX + +test min + movi a2, 0xffffffff + movi a3, 1 + movi a4, 0xffffffff + min a5, a2, a3 + assert eq, a5, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 0xffffffff + min a5, a2, a3 + assert eq, a5, a4 + + movi a2, 0xffffffff + movi a3, 1 + movi a4, 0xffffffff + min a2, a2, a3 + assert eq, a2, a4 + + movi a2, 0xffffffff + movi a3, 1 + movi a4, 0xffffffff + min a3, a2, a3 + assert eq, a3, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 0xffffffff + min a2, a2, a3 + assert eq, a2, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 0xffffffff + min a3, a2, a3 + assert eq, a3, a4 +test_end + +test minu + movi a2, 0xffffffff + movi a3, 1 + movi a4, 1 + minu a5, a2, a3 + assert eq, a5, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 1 + minu a5, a2, a3 + assert eq, a5, a4 + + movi a2, 0xffffffff + movi a3, 1 + movi a4, 1 + minu a2, a2, a3 + assert eq, a2, a4 + + movi a2, 0xffffffff + movi a3, 1 + movi a4, 1 + minu a3, a2, a3 + assert eq, a3, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 1 + minu a2, a2, a3 + assert eq, a2, a4 + + movi a2, 1 + movi a3, 0xffffffff + movi a4, 1 + minu a3, a2, a3 + assert eq, a3, a4 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_mmu.S b/tests/tcg/xtensa/test_mmu.S new file mode 100644 index 000000000..4cbd6ef4f --- /dev/null +++ b/tests/tcg/xtensa/test_mmu.S @@ -0,0 +1,747 @@ +#include "macros.inc" + +test_suite mmu + +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY + +.purgem test_init + +.macro clean_tlb_way way, page_size, n_entries + movi a2, \way + movi a3, \page_size + movi a4, \n_entries + loop a4, 1f + idtlb a2 + iitlb a2 + add a2, a2, a3 +1: +.endm + +.macro test_init + clean_tlb_way 0, 0x00001000, 4 + clean_tlb_way 1, 0x00001000, 4 + clean_tlb_way 2, 0x00001000, 4 + clean_tlb_way 3, 0x00001000, 4 + clean_tlb_way 4, 0x00100000, 4 + movi a2, 0x00000007 + idtlb a2 + movi a2, 0x00000008 + idtlb a2 + movi a2, 0x00000009 + idtlb a2 +.endm + +test tlb_group + movi a2, 0x04000002 /* PPN */ + movi a3, 0x01200004 /* VPN */ + wdtlb a2, a3 + witlb a2, a3 + movi a3, 0x00200004 + rdtlb0 a1, a3 + ritlb0 a2, a3 + movi a3, 0x01000001 + assert eq, a1, a3 + assert eq, a2, a3 + movi a3, 0x00200004 + rdtlb1 a1, a3 + ritlb1 a2, a3 + movi a3, 0x04000002 + assert eq, a1, a3 + assert eq, a2, a3 + movi a3, 0x01234567 + pdtlb a1, a3 + pitlb a2, a3 + movi a3, 0x01234014 + assert eq, a1, a3 + movi a3, 0x0123400c + assert eq, a2, a3 + movi a3, 0x00200004 + idtlb a3 + iitlb a3 + movi a3, 0x01234567 + pdtlb a1, a3 + pitlb a2, a3 + movi a3, 0x00000010 + and a1, a1, a3 + assert eqi, a1, 0 + movi a3, 0x00000008 + and a2, a2, a3 + assert eqi, a2, 0 +test_end + +test itlb_miss + set_vector kernel, 1f + + movi a3, 0x00100000 + jx a3 + test_fail +1: + rsr a2, excvaddr + assert eq, a2, a3 + rsr a2, exccause + movi a3, 16 + assert eq, a2, a3 +test_end + +test dtlb_miss + set_vector kernel, 1f + + movi a3, 0x00100000 + l8ui a2, a3, 0 + test_fail +1: + rsr a2, excvaddr + assert eq, a2, a3 + rsr a2, exccause + movi a3, 24 + assert eq, a2, a3 +test_end + +test itlb_multi_hit + set_vector kernel, 1f + + movi a2, 0x04000002 /* PPN */ + movi a3, 0xf0000004 /* VPN */ + witlb a2, a3 + movi a3, 0xf0000000 + pitlb a2, a3 + test_fail +1: + rsr a2, exccause + movi a3, 17 + assert eq, a2, a3 +test_end + +test dtlb_multi_hit + set_vector kernel, 1f + + movi a2, 0x04000002 /* PPN */ + movi a3, 0x01200004 /* VPN */ + wdtlb a2, a3 + movi a3, 0x01200007 /* VPN */ + wdtlb a2, a3 + movi a3, 0x01200000 + pdtlb a2, a3 + test_fail +1: + rsr a2, exccause + movi a3, 25 + assert eq, a2, a3 +test_end + +test inst_fetch_privilege + set_vector kernel, 3f + + movi a2, 0x4004f + wsr a2, ps +1: + isync + nop +2: + test_fail +3: + movi a1, 1b + rsr a2, excvaddr + rsr a3, epc1 + assert ge, a2, a1 + assert ge, a3, a1 + movi a1, 2b + assert lt, a2, a1 + assert lt, a3, a1 + rsr a2, exccause + movi a3, 18 + assert eq, a2, a3 + rsr a2, ps + movi a3, 0x4005f + assert eq, a2, a3 +test_end + +test load_store_privilege + set_vector kernel, 2f + + movi a3, 10f + pitlb a3, a3 + ritlb1 a2, a3 + movi a1, 0x10 + or a2, a2, a1 + movi a1, 0x000ff000 + and a3, a3, a1 + movi a1, 4 + or a3, a3, a1 + witlb a2, a3 + movi a3, 10f + movi a1, 0x000fffff + and a1, a3, a1 + + movi a2, 0x04000003 /* PPN */ + movi a3, 0x01200004 /* VPN */ + wdtlb a2, a3 + movi a3, 0x01200001 + movi a2, 0x4004f + jx a1 +10: + wsr a2, ps + isync +1: + l8ui a2, a3, 0 + test_fail +2: + rsr a2, excvaddr + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 1b + movi a1, 0x000fffff + and a3, a3, a1 + assert eq, a2, a3 + rsr a2, exccause + movi a3, 26 + assert eq, a2, a3 + rsr a2, ps + movi a3, 0x4005f + assert eq, a2, a3 +test_end + +test cring_load_store_privilege + set_vector kernel, 0 + set_vector double, 2f + + movi a2, 0x04000003 /* PPN */ + movi a3, 0x01200004 /* VPN */ + wdtlb a2, a3 + movi a3, 0x01200004 + movi a2, 0x4005f /* ring 1 + excm => cring == 0 */ + wsr a2, ps + isync + l8ui a2, a3, 0 /* cring used */ +1: + l32e a2, a3, -4 /* ring used */ + test_fail +2: + rsr a2, excvaddr + addi a2, a2, 4 + assert eq, a2, a3 + rsr a2, depc + movi a3, 1b + assert eq, a2, a3 + rsr a2, exccause + movi a3, 26 + assert eq, a2, a3 + rsr a2, ps + movi a3, 0x4005f + assert eq, a2, a3 +test_end + +test inst_fetch_prohibited + set_vector kernel, 2f + + movi a3, 10f + pitlb a3, a3 + ritlb1 a2, a3 + movi a1, 0xfffff000 + and a2, a2, a1 + movi a1, 0x4 + or a2, a2, a1 + movi a1, 0x000ff000 + and a3, a3, a1 + movi a1, 4 + or a3, a3, a1 + witlb a2, a3 + movi a3, 10f + movi a1, 0x000fffff + and a1, a3, a1 + jx a1 + .align 4 +10: + nop + test_fail +2: + rsr a2, excvaddr + assert eq, a2, a1 + rsr a2, epc1 + assert eq, a2, a1 + rsr a2, exccause + movi a3, 20 + assert eq, a2, a3 +test_end + +test load_prohibited + set_vector kernel, 2f + + movi a2, 0x0400000c /* PPN */ + movi a3, 0x01200004 /* VPN */ + wdtlb a2, a3 + movi a3, 0x01200002 +1: + l8ui a2, a3, 0 + test_fail +2: + rsr a2, excvaddr + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 + rsr a2, exccause + movi a3, 28 + assert eq, a2, a3 +test_end + +test store_prohibited + set_vector kernel, 2f + + movi a2, 0x04000001 /* PPN */ + movi a3, 0x01200004 /* VPN */ + wdtlb a2, a3 + movi a3, 0x01200003 + l8ui a2, a3, 0 +1: + s8i a2, a3, 0 + test_fail +2: + rsr a2, excvaddr + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 + rsr a2, exccause + movi a3, 29 + assert eq, a2, a3 +test_end + +/* Set up page table entry vaddr->paddr, ring=pte_ring, attr=pte_attr + * and DTLB way 7 to cover this PTE, ring=pt_ring, attr=pt_attr + */ +.macro pt_setup pt_ring, pt_attr, pte_ring, vaddr, paddr, pte_attr + movi a2, 0x80000000 + wsr a2, ptevaddr + + movi a3, 0x80000007 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */ + movi a4, 0x04000003 | ((\pt_ring) << 4) /* PADDR 64M */ + wdtlb a4, a3 + isync + + movi a3, ((\paddr) & 0xfffff000) | ((\pte_ring) << 4) | (\pte_attr) + movi a1, ((\vaddr) >> 12) << 2 + add a2, a1, a2 + s32i a3, a2, 0 + + movi a3, 0x80000007 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */ + movi a4, 0x04000000 | ((\pt_ring) << 4) | (\pt_attr) /* PADDR 64M */ + wdtlb a4, a3 + isync + + movi a3, (\vaddr) +.endm + +/* out: PS.RING=ring, PS.EXCM=excm, a3=vaddr */ +.macro go_ring ring, excm, vaddr + movi a3, 10f + pitlb a3, a3 + ritlb1 a2, a3 + movi a1, 0x10 + or a2, a2, a1 + movi a1, 0x000ff000 + and a3, a3, a1 + movi a1, 4 + or a3, a3, a1 + witlb a2, a3 + movi a3, 10f + movi a1, 0x000fffff + and a1, a3, a1 + + movi a2, 0 + wsr a2, excvaddr + + movi a3, \vaddr + movi a2, 0x4000f | ((\ring) << 6) | ((\excm) << 4) + jx a1 +10: + wsr a2, ps + isync +.endm + +/* in: a3 -- virtual address to test */ +.macro assert_auto_tlb + movi a2, 0x4000f + wsr a2, ps + isync + pdtlb a2, a3 + movi a1, 0xfffff01f + and a2, a2, a1 + movi a1, 0xfffff000 + and a1, a1, a3 + xor a1, a1, a2 + assert gei, a1, 0x10 + movi a2, 0x14 + assert lt, a1, a2 +.endm + +/* in: a3 -- virtual address to test */ +.macro assert_no_auto_tlb + movi a2, 0x4000f + wsr a2, ps + isync + pdtlb a2, a3 + movi a1, 0x10 + and a1, a1, a2 + assert eqi, a1, 0 +.endm + +.macro assert_sr sr, v + rsr a2, \sr + movi a1, (\v) + assert eq, a1, a2 +.endm + +.macro assert_epc1_1m vaddr + movi a2, (\vaddr) + movi a1, 0xfffff + and a1, a1, a2 + rsr a2, epc1 + assert eq, a1, a2 +.endm + +test dtlb_autoload + set_vector kernel, 0 + + pt_setup 0, 3, 1, 0x1000, 0x1000, 3 + assert_no_auto_tlb + + l8ui a1, a3, 0 + + rsr a2, excvaddr + assert eq, a2, a3 + + assert_auto_tlb +test_end + +test autoload_load_store_privilege + set_vector kernel, 0 + set_vector double, 2f + + pt_setup 0, 3, 0, 0x2000, 0x2000, 3 + movi a3, 0x2004 + assert_no_auto_tlb + + movi a2, 0x4005f /* ring 1 + excm => cring == 0 */ + wsr a2, ps + isync +1: + l32e a2, a3, -4 /* ring used */ + test_fail +2: + rsr a2, excvaddr + addi a1, a3, -4 + assert eq, a1, a2 + + assert_auto_tlb + assert_sr depc, 1b + assert_sr exccause, 26 +test_end + +test autoload_pte_load_prohibited + set_vector kernel, 2f + + pt_setup 0, 3, 0, 0x3000, 0, 0xc + assert_no_auto_tlb +1: + l32i a2, a3, 0 + test_fail +2: + rsr a2, excvaddr + assert eq, a2, a3 + + assert_auto_tlb + assert_sr epc1, 1b + assert_sr exccause, 28 +test_end + +test autoload_pt_load_prohibited + set_vector kernel, 2f + + pt_setup 0, 0xc, 0, 0x4000, 0x4000, 3 + assert_no_auto_tlb +1: + l32i a2, a3, 0 + test_fail +2: + rsr a2, excvaddr + assert eq, a2, a3 + + assert_no_auto_tlb + assert_sr epc1, 1b + assert_sr exccause, 24 +test_end + +test autoload_pt_privilege + set_vector kernel, 2f + pt_setup 0, 3, 1, 0x5000, 0, 3 + go_ring 1, 0, 0x5001 + + l8ui a2, a3, 0 +1: + syscall +2: + rsr a2, excvaddr + assert eq, a2, a3 + + assert_auto_tlb + assert_epc1_1m 1b + assert_sr exccause, 1 +test_end + +test autoload_pte_privilege + set_vector kernel, 2f + pt_setup 0, 3, 0, 0x6000, 0, 3 + go_ring 1, 0, 0x6001 +1: + l8ui a2, a3, 0 + syscall +2: + rsr a2, excvaddr + assert eq, a2, a3 + + assert_auto_tlb + assert_epc1_1m 1b + assert_sr exccause, 26 +test_end + +test autoload_3_level_pt + set_vector kernel, 2f + pt_setup 1, 3, 1, 0x00400000, 0, 3 + pt_setup 1, 3, 1, 0x80001000, 0x2000000, 3 + go_ring 1, 0, 0x00400001 +1: + l8ui a2, a3, 0 + syscall +2: + rsr a2, excvaddr + assert eq, a2, a3 + + assert_no_auto_tlb + assert_epc1_1m 1b + assert_sr exccause, 24 +test_end + +test cross_page_insn + set_vector kernel, 2f + + movi a2, 0x04000003 /* PPN */ + movi a3, 0x00007000 /* VPN */ + witlb a2, a3 + wdtlb a2, a3 + movi a3, 0x00008000 /* VPN */ + witlb a2, a3 + wdtlb a2, a3 + + movi a2, 0x00007fff + movi a3, 20f + movi a4, 21f + sub a4, a4, a3 + loop a4, 1f + l8ui a5, a3, 0 + s8i a5, a2, 0 + addi a2, a2, 1 + addi a3, a3, 1 +1: + movi a2, 0x00007fff + movi a3, 0x00008000 + /* DTLB: OK, ITLB: OK */ + jx a2 + + .begin no-transform +20: + l32i a2, a3, 0 + syscall +21: + .end no-transform + +2: + rsr a2, exccause + movi a3, 1 + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 0x8002 + assert eq, a2, a3 + rsr a2, excsave1 + movi a3, 0x00007fff + assert ne, a2, a3 + + reset_ps + set_vector kernel, 3f + + movi a2, 0x0400000c /* PPN */ + movi a3, 0x00008000 /* VPN */ + wdtlb a2, a3 + movi a2, 0x00007fff + movi a3, 0x00008000 + /* DTLB: FAIL, ITLB: OK */ + jx a2 +3: + rsr a2, exccause + movi a3, 28 + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 0x7fff + assert eq, a2, a3 + rsr a2, excsave1 + movi a3, 0x00007fff + assert eq, a2, a3 + + reset_ps + set_vector kernel, 4f + + movi a2, 0x0400000c /* PPN */ + movi a3, 0x00008000 /* VPN */ + witlb a2, a3 + movi a2, 0x04000003 /* PPN */ + wdtlb a2, a3 + movi a2, 0x00007fff + movi a3, 0x00008000 + /* DTLB: OK, ITLB: FAIL */ + jx a2 +4: + rsr a2, exccause + movi a3, 20 + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 0x7fff + assert eq, a2, a3 + rsr a2, excsave1 + movi a3, 0x00007fff + assert eq, a2, a3 + + reset_ps + set_vector kernel, 5f + + movi a2, 0x0400000c /* PPN */ + movi a3, 0x00008000 /* VPN */ + wdtlb a2, a3 + movi a2, 0x00007fff + movi a3, 0x00008000 + /* DTLB: FAIL, ITLB: FAIL */ + jx a2 +5: + rsr a2, exccause + movi a3, 20 + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 0x7fff + assert eq, a2, a3 + rsr a2, excsave1 + movi a3, 0x00007fff + assert eq, a2, a3 +test_end + +test cross_page_tb + set_vector kernel, 2f + + movi a2, 0x04000003 /* PPN */ + movi a3, 0x00007000 /* VPN */ + witlb a2, a3 + wdtlb a2, a3 + movi a3, 0x00008000 /* VPN */ + witlb a2, a3 + wdtlb a2, a3 + + movi a2, 0x00007ffc + movi a3, 20f + movi a4, 21f + sub a4, a4, a3 + loop a4, 1f + l8ui a5, a3, 0 + s8i a5, a2, 0 + addi a2, a2, 1 + addi a3, a3, 1 +1: + movi a2, 0x00007ffc + movi a3, 0x00008000 + /* DTLB: OK, ITLB: OK */ + jx a2 + + .begin no-transform +20: + l32i a2, a3, 0 + syscall +21: + .end no-transform + +2: + rsr a2, exccause + movi a3, 1 + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 0x7fff + assert eq, a2, a3 + rsr a2, excsave1 + movi a3, 0x00007ffc + assert ne, a2, a3 + + reset_ps + set_vector kernel, 3f + + movi a2, 0x0400000c /* PPN */ + movi a3, 0x00008000 /* VPN */ + wdtlb a2, a3 + movi a2, 0x00007ffc + movi a3, 0x00008000 + /* DTLB: FAIL, ITLB: OK */ + jx a2 +3: + rsr a2, exccause + movi a3, 28 + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 0x7ffc + assert eq, a2, a3 + rsr a2, excsave1 + movi a3, 0x00007ffc + assert eq, a2, a3 + + reset_ps + set_vector kernel, 4f + + movi a2, 0x0400000c /* PPN */ + movi a3, 0x00008000 /* VPN */ + witlb a2, a3 + movi a2, 0x04000003 /* PPN */ + wdtlb a2, a3 + movi a2, 0x00007ffc + movi a3, 0x00008000 + /* DTLB: OK, ITLB: FAIL */ + jx a2 +4: + rsr a2, exccause + movi a3, 20 + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 0x7fff + assert eq, a2, a3 + rsr a2, excsave1 + movi a3, 0x00007ffc + assert ne, a2, a3 + + reset_ps + set_vector kernel, 5f + + movi a2, 0x0400000c /* PPN */ + movi a3, 0x00008000 /* VPN */ + wdtlb a2, a3 + movi a2, 0x00007ffc + movi a3, 0x00008000 + /* DTLB: FAIL, ITLB: FAIL */ + jx a2 +5: + rsr a2, exccause + movi a3, 28 + assert eq, a2, a3 + rsr a2, epc1 + movi a3, 0x7ffc + assert eq, a2, a3 + rsr a2, excsave1 + movi a3, 0x00007ffc + assert eq, a2, a3 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_mul16.S b/tests/tcg/xtensa/test_mul16.S new file mode 100644 index 000000000..32507f7f1 --- /dev/null +++ b/tests/tcg/xtensa/test_mul16.S @@ -0,0 +1,87 @@ +#include "macros.inc" + +test_suite mul16 + +#if XCHAL_HAVE_MUL16 + +test mul16u_pp + movi a2, 0x137f5a5a + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0x06e180a6 + mul16u a5, a2, a4 + assert eq, a5, a6 + mul16u a2, a2, a4 + assert eq, a2, a6 + mul16u a3, a4, a3 + assert eq, a3, a6 +test_end + +test mul16u_np + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0x0c9d6bdb + mul16u a5, a2, a4 + assert eq, a5, a6 + mul16u a2, a2, a4 + assert eq, a2, a6 + mul16u a3, a4, a3 + assert eq, a3, a6 +test_end + +test mul16u_nn + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5f731 + movi a6, 0x9ff1e795 + mul16u a5, a2, a4 + assert eq, a5, a6 + mul16u a2, a2, a4 + assert eq, a2, a6 + mul16u a3, a4, a3 + assert eq, a3, a6 +test_end + +test mul16s_pp + movi a2, 0x137f5a5a + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0x06e180a6 + mul16s a5, a2, a4 + assert eq, a5, a6 + mul16s a2, a2, a4 + assert eq, a2, a6 + mul16s a3, a4, a3 + assert eq, a3, a6 +test_end + +test mul16s_np + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0xf91e6bdb + mul16s a5, a2, a4 + assert eq, a5, a6 + mul16s a2, a2, a4 + assert eq, a2, a6 + mul16s a3, a4, a3 + assert eq, a3, a6 +test_end + +test mul16s_nn + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5f731 + movi a6, 0x031be795 + mul16s a5, a2, a4 + assert eq, a5, a6 + mul16s a2, a2, a4 + assert eq, a2, a6 + mul16s a3, a4, a3 + assert eq, a3, a6 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_mul32.S b/tests/tcg/xtensa/test_mul32.S new file mode 100644 index 000000000..862d45abc --- /dev/null +++ b/tests/tcg/xtensa/test_mul32.S @@ -0,0 +1,24 @@ +#include "macros.inc" + +test_suite mul32 + +#if XCHAL_HAVE_MUL32 + +test mull + movi a2, 0x137f5a5a + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0x5de480a6 + mull a5, a2, a4 + assert eq, a5, a6 + mull a2, a2, a4 + assert eq, a2, a6 + mull a3, a4, a3 + assert eq, a3, a6 +test_end + +#endif + +/* unfortunately dc232b doesn't have muluh/mulsh*/ + +test_suite_end diff --git a/tests/tcg/xtensa/test_nsa.S b/tests/tcg/xtensa/test_nsa.S new file mode 100644 index 000000000..0af7d1f50 --- /dev/null +++ b/tests/tcg/xtensa/test_nsa.S @@ -0,0 +1,63 @@ +#include "macros.inc" + +test_suite nsa + +#if XCHAL_HAVE_NSA + +test nsa + movi a2, 0 + movi a3, 31 + nsa a4, a2 + assert eq, a3, a4 + + movi a2, 0xffffffff + movi a3, 31 + nsa a4, a2 + assert eq, a3, a4 + + movi a2, 1 + movi a3, 30 + nsa a2, a2 + assert eq, a3, a2 + + movi a2, 0xfffffffe + movi a3, 30 + nsa a2, a2 + assert eq, a3, a2 + + movi a2, 0x5a5a5a5a + movi a3, 0 + nsa a4, a2 + assert eq, a3, a4 + + movi a2, 0xa5a5a5a5 + movi a3, 0 + nsa a4, a2 + assert eq, a3, a4 +test_end + +test nsau + movi a2, 0 + movi a3, 32 + nsau a4, a2 + assert eq, a3, a4 + + movi a2, 0xffffffff + movi a3, 0 + nsau a4, a2 + assert eq, a3, a4 + + movi a2, 1 + movi a3, 31 + nsau a2, a2 + assert eq, a3, a2 + + movi a2, 0x5a5a5a5a + movi a3, 1 + nsau a2, a2 + assert eq, a3, a2 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_phys_mem.S b/tests/tcg/xtensa/test_phys_mem.S new file mode 100644 index 000000000..9bb3ee386 --- /dev/null +++ b/tests/tcg/xtensa/test_phys_mem.S @@ -0,0 +1,128 @@ +#include "macros.inc" + +test_suite phys_mem + +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY + +.purgem test_init + +.macro test_init + movi a2, 0xc0000003 /* PPN */ + movi a3, 0xc0000004 /* VPN */ + wdtlb a2, a3 + witlb a2, a3 + movi a2, 0xc0000000 + wsr a2, ptevaddr +.endm + +test inst_fetch_get_pte_no_phys + set_vector kernel, 2f + + movi a2, 0x20000000 + jx a2 +2: + movi a2, 0x20000000 + rsr a3, excvaddr + assert eq, a2, a3 + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 16 + assert eq, a2, a3 +test_end + +test read_get_pte_no_phys + set_vector kernel, 2f + + movi a2, 0x20000000 +1: + l32i a3, a2, 0 + test_fail +2: + movi a2, 0x20000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 24 + assert eq, a2, a3 +test_end + +test write_get_pte_no_phys + set_vector kernel, 2f + + movi a2, 0x20000000 +1: + s32i a3, a2, 0 + test_fail +2: + movi a2, 0x20000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 24 + assert eq, a2, a3 +test_end + +#endif + +test inst_fetch_no_phys + set_vector kernel, 2f + + movi a2, 0xc0000000 + jx a2 +2: + movi a2, 0xc0000000 + rsr a3, excvaddr + assert eq, a2, a3 + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 14 + assert eq, a2, a3 +test_end + +test read_no_phys + set_vector kernel, 2f + + movi a2, 0xc0000000 +1: + l32i a3, a2, 0 + test_fail +2: + movi a2, 0xc0000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 15 + assert eq, a2, a3 +test_end + +test write_no_phys + set_vector kernel, 2f + + movi a2, 0xc0000000 +1: + s32i a3, a2, 0 + test_fail +2: + movi a2, 0xc0000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 15 + assert eq, a2, a3 +test_end + +test_suite_end diff --git a/tests/tcg/xtensa/test_quo.S b/tests/tcg/xtensa/test_quo.S new file mode 100644 index 000000000..32886b913 --- /dev/null +++ b/tests/tcg/xtensa/test_quo.S @@ -0,0 +1,151 @@ +#include "macros.inc" + +test_suite quo + +#if XCHAL_HAVE_DIV32 + +test quou_pp + movi a2, 0x5a5a137f + mov a3, a2 + movi a4, 0x137f5a5a + movi a6, 0x4 + quou a5, a2, a4 + assert eq, a5, a6 + quou a2, a2, a4 + assert eq, a2, a6 + quou a4, a3, a4 + assert eq, a4, a6 +test_end + +test quou_np + movi a2, 0xa5a5137f + mov a3, a2 + movi a4, 0x137f5a5a + movi a6, 0x8 + quou a5, a2, a4 + assert eq, a5, a6 + quou a2, a2, a4 + assert eq, a2, a6 + quou a4, a3, a4 + assert eq, a4, a6 +test_end + +test quou_pn + movi a2, 0x5a5a137f + mov a3, a2 + movi a4, 0xf7315a5a + movi a6, 0 + quou a5, a2, a4 + assert eq, a5, a6 + quou a2, a2, a4 + assert eq, a2, a6 + quou a4, a3, a4 + assert eq, a4, a6 +test_end + +test quou_nn + movi a2, 0xf7315a5a + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0x1 + quou a5, a2, a4 + assert eq, a5, a6 + quou a2, a2, a4 + assert eq, a2, a6 + quou a4, a3, a4 + assert eq, a4, a6 +test_end + +test quou_exc + set_vector kernel, 2f + movi a2, 0xf7315a5a + movi a4, 0x00000000 +1: + quou a5, a2, a4 + test_fail +2: + rsr a2, exccause + assert eqi, a2, 6 /* INTEGER_DIVIDE_BY_ZERO_CAUSE */ + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 +test_end + +test quos_pp + movi a2, 0x5a5a137f + mov a3, a2 + movi a4, 0x137f5a5a + movi a6, 0x4 + quos a5, a2, a4 + assert eq, a5, a6 + quos a2, a2, a4 + assert eq, a2, a6 + quos a4, a3, a4 + assert eq, a4, a6 +test_end + +test quos_np + movi a2, 0xa5a5137f + mov a3, a2 + movi a4, 0x137f5a5a + movi a6, 0xfffffffc + quos a5, a2, a4 + assert eq, a5, a6 + quos a2, a2, a4 + assert eq, a2, a6 + quos a4, a3, a4 + assert eq, a4, a6 +test_end + +test quos_pn + movi a2, 0x5a5a137f + mov a3, a2 + movi a4, 0xf7315a5a + movi a6, 0xfffffff6 + quos a5, a2, a4 + assert eq, a5, a6 + quos a2, a2, a4 + assert eq, a2, a6 + quos a4, a3, a4 + assert eq, a4, a6 +test_end + +test quos_nn + movi a2, 0xf7315a5a + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0 + quos a5, a2, a4 + assert eq, a5, a6 + quos a2, a2, a4 + assert eq, a2, a6 + quos a4, a3, a4 + assert eq, a4, a6 +test_end + +test quos_over + movi a2, 0x80000000 + movi a4, 0xffffffff + movi a6, 0x80000000 + quos a5, a2, a4 + assert eq, a5, a6 +test_end + +test quos_exc + set_vector kernel, 2f + movi a2, 0xf7315a5a + movi a4, 0x00000000 +1: + quos a5, a2, a4 + test_fail +2: + rsr a2, exccause + assert eqi, a2, 6 /* INTEGER_DIVIDE_BY_ZERO_CAUSE */ + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_rem.S b/tests/tcg/xtensa/test_rem.S new file mode 100644 index 000000000..0b96bb339 --- /dev/null +++ b/tests/tcg/xtensa/test_rem.S @@ -0,0 +1,151 @@ +#include "macros.inc" + +test_suite rem + +#if XCHAL_HAVE_DIV32 + +test remu_pp + movi a2, 0x5a5a137f + mov a3, a2 + movi a4, 0x137f5a5a + movi a6, 0x0c5caa17 + remu a5, a2, a4 + assert eq, a5, a6 + remu a2, a2, a4 + assert eq, a2, a6 + remu a4, a3, a4 + assert eq, a4, a6 +test_end + +test remu_np + movi a2, 0xa5a5137f + mov a3, a2 + movi a4, 0x137f5a5a + movi a6, 0x9aa40af + remu a5, a2, a4 + assert eq, a5, a6 + remu a2, a2, a4 + assert eq, a2, a6 + remu a4, a3, a4 + assert eq, a4, a6 +test_end + +test remu_pn + movi a2, 0x5a5a137f + mov a3, a2 + movi a4, 0xf7315a5a + movi a6, 0x5a5a137f + remu a5, a2, a4 + assert eq, a5, a6 + remu a2, a2, a4 + assert eq, a2, a6 + remu a4, a3, a4 + assert eq, a4, a6 +test_end + +test remu_nn + movi a2, 0xf7315a5a + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0x518c46db + remu a5, a2, a4 + assert eq, a5, a6 + remu a2, a2, a4 + assert eq, a2, a6 + remu a4, a3, a4 + assert eq, a4, a6 +test_end + +test remu_exc + set_vector kernel, 2f + movi a2, 0xf7315a5a + movi a4, 0x00000000 +1: + remu a5, a2, a4 + test_fail +2: + rsr a2, exccause + assert eqi, a2, 6 /* INTEGER_DIVIDE_BY_ZERO_CAUSE */ + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 +test_end + +test rems_pp + movi a2, 0x5a5a137f + mov a3, a2 + movi a4, 0x137f5a5a + movi a6, 0x0c5caa17 + rems a5, a2, a4 + assert eq, a5, a6 + rems a2, a2, a4 + assert eq, a2, a6 + rems a4, a3, a4 + assert eq, a4, a6 +test_end + +test rems_np + movi a2, 0xa5a5137f + mov a3, a2 + movi a4, 0x137f5a5a + movi a6, 0xf3a27ce7 + rems a5, a2, a4 + assert eq, a5, a6 + rems a2, a2, a4 + assert eq, a2, a6 + rems a4, a3, a4 + assert eq, a4, a6 +test_end + +test rems_pn + movi a2, 0x5a5a137f + mov a3, a2 + movi a4, 0xf7315a5a + movi a6, 0x02479b03 + rems a5, a2, a4 + assert eq, a5, a6 + rems a2, a2, a4 + assert eq, a2, a6 + rems a4, a3, a4 + assert eq, a4, a6 +test_end + +test rems_nn + movi a2, 0xf7315a5a + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0xf7315a5a + rems a5, a2, a4 + assert eq, a5, a6 + rems a2, a2, a4 + assert eq, a2, a6 + rems a4, a3, a4 + assert eq, a4, a6 +test_end + +test rems_over + movi a2, 0x80000000 + movi a4, 0xffffffff + movi a6, 0 + rems a5, a2, a4 + assert eq, a5, a6 +test_end + +test rems_exc + set_vector kernel, 2f + movi a2, 0xf7315a5a + movi a4, 0x00000000 +1: + rems a5, a2, a4 + test_fail +2: + rsr a2, exccause + assert eqi, a2, 6 /* INTEGER_DIVIDE_BY_ZERO_CAUSE */ + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_rst0.S b/tests/tcg/xtensa/test_rst0.S new file mode 100644 index 000000000..143e90b40 --- /dev/null +++ b/tests/tcg/xtensa/test_rst0.S @@ -0,0 +1,156 @@ +#include "macros.inc" + +test_suite rst0 + +test and + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0x01250125 + and a5, a2, a4 + assert eq, a5, a6 + and a2, a2, a4 + assert eq, a2, a6 + and a3, a4, a3 + assert eq, a3, a6 +test_end + +test or + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0xb7ffb7ff + or a5, a2, a4 + assert eq, a5, a6 + or a2, a2, a4 + assert eq, a2, a6 + or a3, a4, a3 + assert eq, a3, a6 +test_end + +test xor + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0xb6dab6da + xor a5, a2, a4 + assert eq, a5, a6 + xor a2, a2, a4 + assert eq, a2, a6 + xor a3, a4, a3 + assert eq, a3, a6 +test_end + +test add + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0xb924b924 + add a5, a2, a4 + assert eq, a5, a6 + add a2, a2, a4 + assert eq, a2, a6 + add a4, a3, a4 + assert eq, a4, a6 +test_end + +#if XCHAL_HAVE_ADDX + +test addx2 + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0xcca45ec9 + addx2 a5, a2, a4 + assert eq, a5, a6 + addx2 a2, a2, a4 + assert eq, a2, a6 + addx2 a4, a3, a4 + assert eq, a4, a6 +test_end + +test addx4 + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0xf3a3aa13 + addx4 a5, a2, a4 + assert eq, a5, a6 + addx4 a2, a2, a4 + assert eq, a2, a6 + addx4 a4, a3, a4 + assert eq, a4, a6 +test_end + +test addx8 + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0x41a240a7 + addx8 a5, a2, a4 + assert eq, a5, a6 + addx8 a2, a2, a4 + assert eq, a2, a6 + addx8 a4, a3, a4 + assert eq, a4, a6 +test_end + +#endif + +test sub + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0x6dda9226 + sub a5, a2, a4 + assert eq, a5, a6 + sub a2, a2, a4 + assert eq, a2, a6 + sub a4, a3, a4 + assert eq, a4, a6 +test_end + +#if XCHAL_HAVE_ADDX + +test subx2 + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0x815a37cb + subx2 a5, a2, a4 + assert eq, a5, a6 + subx2 a2, a2, a4 + assert eq, a2, a6 + subx2 a4, a3, a4 + assert eq, a4, a6 +test_end + +test subx4 + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0xa8598315 + subx4 a5, a2, a4 + assert eq, a5, a6 + subx4 a2, a2, a4 + assert eq, a2, a6 + subx4 a4, a3, a4 + assert eq, a4, a6 +test_end + +test subx8 + movi a2, 0x137fa5a5 + mov a3, a2 + movi a4, 0xa5a5137f + movi a6, 0xf65819a9 + subx8 a5, a2, a4 + assert eq, a5, a6 + subx8 a2, a2, a4 + assert eq, a2, a6 + subx8 a4, a3, a4 + assert eq, a4, a6 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_s32c1i.S b/tests/tcg/xtensa/test_s32c1i.S new file mode 100644 index 000000000..2885d9d00 --- /dev/null +++ b/tests/tcg/xtensa/test_s32c1i.S @@ -0,0 +1,51 @@ +#include "macros.inc" + +test_suite s32c1i + +#if XCHAL_HAVE_S32C1I + +test s32c1i_nowrite +#if XCHAL_HW_VERSION >= 230000 + movi a2, 0x29 + wsr a2, atomctl +#endif + movi a2, 1f + movi a3, 1 + wsr a3, scompare1 + movi a1, 2 + s32c1i a1, a2, 0 + assert ne, a1, a3 + l32i a1, a2, 0 + assert eqi, a1, 3 + +.data +.align 4 +1: + .word 3 +.text +test_end + +test s32c1i_write +#if XCHAL_HW_VERSION >= 230000 + movi a2, 0x29 + wsr a2, atomctl +#endif + movi a2, 1f + movi a3, 3 + wsr a3, scompare1 + movi a1, 2 + s32c1i a1, a2, 0 + assert eq, a1, a3 + l32i a1, a2, 0 + assert eqi, a1, 2 + +.data +.align 4 +1: + .word 3 +.text +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_sar.S b/tests/tcg/xtensa/test_sar.S new file mode 100644 index 000000000..b615a5576 --- /dev/null +++ b/tests/tcg/xtensa/test_sar.S @@ -0,0 +1,111 @@ +#include "macros.inc" + +test_suite sar + +.macro test_sar prefix, imm + \prefix\()_set \imm + \prefix\()_ver \imm +.endm + +.macro tests_sar prefix + test_sar \prefix, 0 + test_sar \prefix, 1 + test_sar \prefix, 2 + test_sar \prefix, 3 + test_sar \prefix, 0x1f + test_sar \prefix, 0x20 + test_sar \prefix, 0x3f + test_sar \prefix, 0x40 + test_sar \prefix, 0xfffffffe +.endm + +.macro sar_set imm + movi a2, \imm + wsr a2, sar +.endm + +.macro sar_ver imm + rsr a3, sar + movi a2, \imm & 0x3f + assert eq, a2, a3 +.endm + +test sar + tests_sar sar +test_end + +.macro ssr_set imm + movi a2, \imm + ssr a2 +.endm + +.macro ssr_ver imm + rsr a3, sar + movi a2, \imm & 0x1f + assert eq, a2, a3 +.endm + +test ssr + tests_sar ssr +test_end + +.macro ssl_set imm + movi a2, \imm + ssl a2 +.endm + +.macro ssl_ver imm + rsr a3, sar + movi a2, 32 - (\imm & 0x1f) + assert eq, a2, a3 +.endm + +test ssl + tests_sar ssl +test_end + +.macro ssa8l_set imm + movi a2, \imm + ssa8l a2 +.endm + +.macro ssa8l_ver imm + rsr a3, sar + movi a2, (\imm & 0x3) << 3 + assert eq, a2, a3 +.endm + +test ssa8l + tests_sar ssa8l +test_end + +.macro ssa8b_set imm + movi a2, \imm + ssa8b a2 +.endm + +.macro ssa8b_ver imm + rsr a3, sar + movi a2, 32 - ((\imm & 0x3) << 3) + assert eq, a2, a3 +.endm + +test ssa8b + tests_sar ssa8b +test_end + +.macro ssai_set imm + ssai \imm & 0x1f +.endm + +.macro ssai_ver imm + rsr a3, sar + movi a2, \imm & 0x1f + assert eq, a2, a3 +.endm + +test ssai + tests_sar ssai +test_end + +test_suite_end diff --git a/tests/tcg/xtensa/test_sext.S b/tests/tcg/xtensa/test_sext.S new file mode 100644 index 000000000..483d2176e --- /dev/null +++ b/tests/tcg/xtensa/test_sext.S @@ -0,0 +1,73 @@ +#include "macros.inc" + +test_suite sext + +#if XCHAL_HAVE_SEXT + +test sext + movi a2, 0xffffff5a + movi a3, 0x0000005a + sext a4, a2, 7 + assert eq, a3, a4 + + movi a2, 0x000000a5 + movi a3, 0xffffffa5 + sext a4, a2, 7 + assert eq, a3, a4 + + movi a2, 0xfffffaa5 + movi a3, 0x000000a5 + sext a4, a2, 8 + assert eq, a3, a4 + + movi a2, 0x0000055a + movi a3, 0xffffff5a + sext a4, a2, 8 + assert eq, a3, a4 + + movi a2, 0xffff5a5a + movi a3, 0x00005a5a + sext a4, a2, 15 + assert eq, a3, a4 + + movi a2, 0x0000a5a5 + movi a3, 0xffffa5a5 + sext a4, a2, 15 + assert eq, a3, a4 + + movi a2, 0x00055a5a + movi a3, 0xffff5a5a + sext a4, a2, 16 + assert eq, a3, a4 + + movi a2, 0x000aa5a5 + movi a3, 0x0000a5a5 + sext a4, a2, 16 + assert eq, a3, a4 + + movi a2, 0x005a5a5a + movi a3, 0xffda5a5a + sext a4, a2, 22 + assert eq, a3, a4 + + movi a2, 0xffa5a5a5 + movi a3, 0x0025a5a5 + sext a4, a2, 22 + assert eq, a3, a4 +test_end + +test sext_same_rs + movi a2, 0xffffff5a + movi a3, 0x0000005a + sext a2, a2, 7 + assert eq, a3, a2 + + movi a2, 0x000000a5 + movi a3, 0xffffffa5 + sext a2, a2, 7 + assert eq, a3, a2 +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_shift.S b/tests/tcg/xtensa/test_shift.S new file mode 100644 index 000000000..5df9ed4b1 --- /dev/null +++ b/tests/tcg/xtensa/test_shift.S @@ -0,0 +1,206 @@ +#include "macros.inc" + +test_suite shift + +.macro test_shift prefix, dst, src, v, imm + \prefix\()_set \dst, \src, \v, \imm + \prefix\()_ver \dst, \v, \imm +.endm + +.macro test_shift_sd prefix, v, imm + test_shift \prefix, a3, a2, \v, \imm + test_shift \prefix, a2, a2, \v, \imm +.endm + +.macro tests_imm_shift prefix, v + test_shift_sd \prefix, \v, 1 + test_shift_sd \prefix, \v, 2 + test_shift_sd \prefix, \v, 7 + test_shift_sd \prefix, \v, 8 + test_shift_sd \prefix, \v, 15 + test_shift_sd \prefix, \v, 16 + test_shift_sd \prefix, \v, 31 +.endm + +.macro tests_shift prefix, v + test_shift_sd \prefix, \v, 0 + tests_imm_shift \prefix, \v + test_shift_sd \prefix, \v, 32 +.endm + + +.macro slli_set dst, src, v, imm + movi \src, \v + slli \dst, \src, \imm +.endm + +.macro slli_ver dst, v, imm + mov a2, \dst + movi a3, ((\v) << (\imm)) & 0xffffffff + assert eq, a2, a3 +.endm + +test slli + tests_imm_shift slli, 0xa3c51249 +test_end + + +.macro srai_set dst, src, v, imm + movi \src, \v + srai \dst, \src, \imm +.endm + +.macro srai_ver dst, v, imm + mov a2, \dst + .if (\imm) + movi a3, (((\v) >> (\imm)) & 0xffffffff) | \ + ~((((\v) & 0x80000000) >> ((\imm) - 1)) - 1) + .else + movi a3, \v + .endif + assert eq, a2, a3 +.endm + +test srai + tests_imm_shift srai, 0x49a3c512 + tests_imm_shift srai, 0xa3c51249 +test_end + + +.macro srli_set dst, src, v, imm + movi \src, \v + srli \dst, \src, \imm +.endm + +.macro srli_ver dst, v, imm + mov a2, \dst + movi a3, (((\v) >> (\imm)) & 0xffffffff) + assert eq, a2, a3 +.endm + +test srli + tests_imm_shift srli, 0x49a3c512 + tests_imm_shift srli, 0xa3c51249 +test_end + + +.macro sll_set dst, src, v, imm + movi a2, \imm + ssl a2 + movi \src, \v + sll \dst, \src +.endm + +.macro sll_sar_set dst, src, v, imm + movi a2, 32 - \imm + wsr a2, sar + movi \src, \v + sll \dst, \src +.endm + +.macro sll_ver dst, v, imm + slli_ver \dst, \v, (\imm) & 0x1f +.endm + +.macro sll_sar_ver dst, v, imm + slli_ver \dst, \v, \imm +.endm + +test sll + tests_shift sll, 0xa3c51249 + tests_shift sll_sar, 0xa3c51249 +test_end + + +.macro srl_set dst, src, v, imm + movi a2, \imm + ssr a2 + movi \src, \v + srl \dst, \src +.endm + +.macro srl_sar_set dst, src, v, imm + movi a2, \imm + wsr a2, sar + movi \src, \v + srl \dst, \src +.endm + +.macro srl_ver dst, v, imm + srli_ver \dst, \v, (\imm) & 0x1f +.endm + +.macro srl_sar_ver dst, v, imm + srli_ver \dst, \v, \imm +.endm + +test srl + tests_shift srl, 0xa3c51249 + tests_shift srl_sar, 0xa3c51249 + tests_shift srl, 0x49a3c512 + tests_shift srl_sar, 0x49a3c512 +test_end + + +.macro sra_set dst, src, v, imm + movi a2, \imm + ssr a2 + movi \src, \v + sra \dst, \src +.endm + +.macro sra_sar_set dst, src, v, imm + movi a2, \imm + wsr a2, sar + movi \src, \v + sra \dst, \src +.endm + +.macro sra_ver dst, v, imm + srai_ver \dst, \v, (\imm) & 0x1f +.endm + +.macro sra_sar_ver dst, v, imm + srai_ver \dst, \v, \imm +.endm + +test sra + tests_shift sra, 0xa3c51249 + tests_shift sra_sar, 0xa3c51249 + tests_shift sra, 0x49a3c512 + tests_shift sra_sar, 0x49a3c512 +test_end + + +.macro src_set dst, src, v, imm + movi a2, \imm + ssr a2 + movi \src, (\v) & 0xffffffff + movi a4, (\v) >> 32 + src \dst, a4, \src +.endm + +.macro src_sar_set dst, src, v, imm + movi a2, \imm + wsr a2, sar + movi \src, (\v) & 0xffffffff + movi a4, (\v) >> 32 + src \dst, a4, \src +.endm + +.macro src_ver dst, v, imm + src_sar_ver \dst, \v, (\imm) & 0x1f +.endm + +.macro src_sar_ver dst, v, imm + mov a2, \dst + movi a3, ((\v) >> (\imm)) & 0xffffffff + assert eq, a2, a3 +.endm + +test src + tests_shift src, 0xa3c51249215c3a94 + tests_shift src_sar, 0xa3c51249215c3a94 +test_end + +test_suite_end diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S new file mode 100644 index 000000000..b1a91a063 --- /dev/null +++ b/tests/tcg/xtensa/test_sr.S @@ -0,0 +1,236 @@ +#include "macros.inc" + +test_suite sr + +#if XCHAL_HAVE_BE +#define LOW__SR 0x04 +#define HI_RSR 0x30 +#define HI_WSR 0x31 +#define HI_XSR 0x16 +#else +#define LOW__SR 0x40 +#define HI_RSR 0x03 +#define HI_WSR 0x13 +#define HI_XSR 0x61 +#endif + +.macro sr_op sym, op_sym, op_byte, sr + .if \sym + \op_sym a4, \sr + .else + .byte LOW__SR, \sr, \op_byte + .endif +.endm + +.macro test_sr_op sym, mask, op, op_byte, sr + movi a4, 0 + .if (\mask) + set_vector kernel, 0 + sr_op \sym, \op, \op_byte, \sr + .else + set_vector kernel, 2f +1: + sr_op \sym, \op, \op_byte, \sr + test_fail +2: + reset_ps + rsr a2, exccause + assert eqi, a2, 0 + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 + .endif +.endm + +.macro test_sr_mask sr, sym, mask +test \sr + test_sr_op \sym, \mask & 1, rsr, HI_RSR, \sr + test_sr_op \sym, \mask & 2, wsr, HI_WSR, \sr + test_sr_op \sym, \mask & 4, xsr, HI_XSR, \sr +test_end +.endm + +.macro test_sr sr, conf + test_sr_mask \sr, \conf, 7 +.endm + +#if XCHAL_HAVE_MAC16 +test_sr acchi, 1 +test_sr acclo, 1 +#else +test_sr_mask /*acchi*/17, 0, 0 +test_sr_mask /*acclo*/16, 0, 0 +#endif + +#if XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000 +test_sr atomctl, 1 +#else +test_sr_mask /*atomctl*/99, 0, 0 +#endif + +#if XCHAL_HAVE_BOOLEANS +test_sr br, 1 +#else +test_sr_mask /*br*/4, 0, 0 +#endif + +test_sr_mask /*cacheattr*/98, 0, 0 + +#if XCHAL_HAVE_CCOUNT +test_sr ccompare0, 1 +test_sr ccount, 1 +#else +test_sr_mask /*ccompare0*/240, 0, 0 +test_sr_mask /*ccount*/234, 0, 0 +#endif + +#if XCHAL_HAVE_CP +test_sr cpenable, 1 +#else +test_sr_mask /*cpenable*/224, 0, 0 +#endif + +#if XCHAL_HAVE_DEBUG +#if XCHAL_NUM_DBREAK +test_sr dbreaka0, 1 +test_sr dbreakc0, 1 +#endif +test_sr_mask debugcause, 1, 1 +#else +test_sr_mask /*dbreaka0*/144, 0, 0 +test_sr_mask /*dbreakc0*/160, 0, 0 +test_sr_mask /*debugcause*/233, 0, 0 +#endif + +test_sr depc, 1 + +#if XCHAL_HAVE_PTP_MMU +test_sr dtlbcfg, 1 +#else +test_sr_mask /*dtlbcfg*/92, 0, 0 +#endif + +test_sr epc1, 1 + +#if XCHAL_NUM_INTLEVELS > 1 +test_sr epc2, 1 +test_sr eps2, 1 +#else +test_sr_mask /*epc2*/178, 0, 0 +test_sr_mask /*eps2*/194, 0, 0 +#endif + +test_sr exccause, 1 +test_sr excsave1, 1 + +#if XCHAL_NUM_INTLEVELS > 1 +test_sr excsave2, 1 +#else +test_sr_mask /*excsave2*/210, 0, 0 +#endif + +test_sr excvaddr, 1 + +#if XCHAL_HAVE_DEBUG +#if XCHAL_NUM_IBREAK +test_sr ibreaka0, 1 +test_sr ibreakenable, 1 +#endif +test_sr icount, 1 +test_sr icountlevel, 1 +#else +test_sr_mask /*ibreaka0*/128, 0, 0 +test_sr_mask /*ibreakenable*/96, 0, 0 +test_sr_mask /*icount*/236, 0, 0 +test_sr_mask /*icountlevel*/237, 0, 0 +#endif + +test_sr_mask /*intclear*/227, 0, 2 +test_sr_mask /*interrupt*/226, 0, 3 +test_sr intenable, 1 + +#if XCHAL_HAVE_PTP_MMU +test_sr itlbcfg, 1 +#else +test_sr_mask /*itlbcfg*/91, 0, 0 +#endif + +#if XCHAL_HAVE_LOOPS +test_sr lbeg, 1 +test_sr lcount, 1 +test_sr lend, 1 +#else +test_sr_mask /*lbeg*/0, 0, 0 +test_sr_mask /*lcount*/2, 0, 0 +test_sr_mask /*lend*/1, 0, 0 +#endif + +#if XCHAL_HAVE_ABSOLUTE_LITERALS +test_sr litbase, 1 +#else +test_sr_mask /*litbase*/5, 0, 0 +#endif + +#if XCHAL_HAVE_MAC16 +test_sr m0, 1 +#else +test_sr_mask /*m0*/32, 0, 0 +#endif + +#if XCHAL_HW_VERSION >= 250000 +test_sr_mask /*memctl*/97, 0, 7 +#else +test_sr_mask /*memctl*/97, 0, 0 +#endif + +#if XCHAL_NUM_MISC_REGS +test_sr misc0, 1 +#else +test_sr_mask /*misc0*/244, 0, 0 +#endif + +#if XCHAL_HAVE_PREFETCH +test_sr prefctl, 1 +#else +test_sr_mask /*prefctl*/40, 0, 0 +#endif + +#if XCHAL_HAVE_PRID +test_sr_mask /*prid*/235, 0, 1 +#else +test_sr_mask /*prid*/235, 0, 0 +#endif + +test_sr ps, 1 + +#if XCHAL_HAVE_PTP_MMU +test_sr ptevaddr, 1 +test_sr rasid, 1 +#else +test_sr_mask /*ptevaddr*/83, 0, 0 +test_sr_mask /*rasid*/90, 0, 0 +#endif + +test_sr sar, 1 + +#if XCHAL_HAVE_S32C1I +test_sr scompare1, 1 +#else +test_sr_mask /*scompare1*/12, 0, 0 +#endif + +#if XCHAL_HAVE_VECBASE +test_sr vecbase, 1 +#else +test_sr_mask /*vecbase*/231, 0, 0 +#endif + +#if XCHAL_HAVE_WINDOWED +test_sr windowbase, 1 +test_sr windowstart, 1 +#else +test_sr_mask /*windowbase*/72, 0, 0 +test_sr_mask /*windowstart*/73, 0, 0 +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_timer.S b/tests/tcg/xtensa/test_timer.S new file mode 100644 index 000000000..1ec8e2088 --- /dev/null +++ b/tests/tcg/xtensa/test_timer.S @@ -0,0 +1,257 @@ +#include "macros.inc" + +#define CCOUNT_SHIFT 4 +#define WAIT_LOOPS 20 +#define level1 kernel +#define INTERRUPT_LEVEL(n) glue3(XCHAL_INT, n, _LEVEL) + +.macro make_ccount_delta target, delta + rsr \delta, ccount + rsr \target, ccount + sub \delta, \target, \delta + slli \delta, \delta, CCOUNT_SHIFT + add \target, \target, \delta +.endm + +test_suite timer + +#if XCHAL_HAVE_CCOUNT + +test ccount + rsr a3, ccount + rsr a4, ccount + assert ne, a3, a4 +test_end + +test ccount_write + rsr a3, ccount + rsr a4, ccount + sub a4, a4, a3 + movi a2, 0x12345678 + wsr a2, ccount + esync + rsr a3, ccount + sub a3, a3, a2 + slli a4, a4, 2 + assert ltu, a3, a4 +test_end + +#if XCHAL_NUM_TIMERS + +test ccount_update_deadline + movi a2, 0 + wsr a2, intenable + rsr a2, interrupt + wsr a2, intclear + movi a2, 0 +#if XCHAL_NUM_TIMERS > 1 + wsr a2, ccompare1 +#endif +#if XCHAL_NUM_TIMERS > 2 + wsr a2, ccompare2 +#endif + movi a2, 0x12345678 + wsr a2, ccompare0 + rsr a3, interrupt + assert eqi, a3, 0 + movi a2, 0x12345677 + wsr a2, ccount + esync + nop + rsr a2, interrupt + movi a3, 1 << XCHAL_TIMER0_INTERRUPT + assert eq, a2, a3 +test_end + +test ccompare + movi a2, 0 + wsr a2, intenable + rsr a2, interrupt + wsr a2, intclear + movi a2, 0 +#if XCHAL_NUM_TIMERS > 1 + wsr a2, ccompare1 +#endif +#if XCHAL_NUM_TIMERS > 2 + wsr a2, ccompare2 +#endif + + make_ccount_delta a2, a15 + wsr a2, ccompare0 +1: + rsr a3, interrupt + rsr a4, ccount + rsr a5, interrupt + sub a4, a4, a2 + bgez a4, 2f + assert eqi, a3, 0 + j 1b +2: + assert nei, a5, 0 +test_end + +#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1 +test ccompare0_interrupt + set_vector kernel, 2f + movi a2, 0 + wsr a2, intenable + rsr a2, interrupt + wsr a2, intclear + movi a2, 0 +#if XCHAL_NUM_TIMERS > 1 + wsr a2, ccompare1 +#endif +#if XCHAL_NUM_TIMERS > 2 + wsr a2, ccompare2 +#endif + + movi a3, WAIT_LOOPS + make_ccount_delta a2, a15 + wsr a2, ccompare0 + rsync + rsr a2, interrupt + assert eqi, a2, 0 + + movi a2, 1 << XCHAL_TIMER0_INTERRUPT + wsr a2, intenable + rsil a2, 0 + loop a3, 1f + nop +1: + test_fail +2: + rsr a2, exccause + assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ +test_end +#endif + +#if XCHAL_NUM_TIMERS > 1 + +test ccompare1_interrupt + set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT)), 2f + movi a2, 0 + wsr a2, intenable + rsr a2, interrupt + wsr a2, intclear + movi a2, 0 + wsr a2, ccompare0 +#if XCHAL_NUM_TIMERS > 2 + wsr a2, ccompare2 +#endif + + movi a3, WAIT_LOOPS + make_ccount_delta a2, a15 + wsr a2, ccompare1 + rsync + rsr a2, interrupt + assert eqi, a2, 0 + movi a2, 1 << XCHAL_TIMER1_INTERRUPT + wsr a2, intenable + rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1 + loop a3, 1f + nop +1: + test_fail +2: +test_end + +#endif +#if XCHAL_NUM_TIMERS > 2 + +test ccompare2_interrupt + set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT)), 2f + movi a2, 0 + wsr a2, intenable + rsr a2, interrupt + wsr a2, intclear + movi a2, 0 + wsr a2, ccompare0 + wsr a2, ccompare1 + + movi a3, WAIT_LOOPS + make_ccount_delta a2, a15 + wsr a2, ccompare2 + rsync + rsr a2, interrupt + assert eqi, a2, 0 + movi a2, 1 << XCHAL_TIMER2_INTERRUPT + wsr a2, intenable + rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1 + loop a3, 1f + nop +1: + test_fail +2: +test_end + +#endif + +test ccompare_interrupt_masked + set_vector kernel, 2f + movi a2, 0 + wsr a2, intenable + rsr a2, interrupt + wsr a2, intclear + movi a2, 0 +#if XCHAL_NUM_TIMERS > 2 + wsr a2, ccompare2 +#endif + + movi a3, 2 * WAIT_LOOPS + make_ccount_delta a2, a15 +#if XCHAL_NUM_TIMERS > 1 + wsr a2, ccompare1 +#endif + add a2, a2, a15 + wsr a2, ccompare0 + rsync + rsr a2, interrupt + assert eqi, a2, 0 + + movi a2, 1 << XCHAL_TIMER0_INTERRUPT + wsr a2, intenable + rsil a2, 0 + loop a3, 1f + nop +1: + test_fail +2: + rsr a2, exccause + assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ +test_end + +test ccompare_interrupt_masked_waiti + set_vector kernel, 2f + movi a2, 0 + wsr a2, intenable + rsr a2, interrupt + wsr a2, intclear + movi a2, 0 +#if XCHAL_NUM_TIMERS > 2 + wsr a2, ccompare2 +#endif + + movi a3, 2 * WAIT_LOOPS + make_ccount_delta a2, a15 +#if XCHAL_NUM_TIMERS > 1 + wsr a2, ccompare1 +#endif + add a2, a2, a15 + wsr a2, ccompare0 + rsync + rsr a2, interrupt + assert eqi, a2, 0 + + movi a2, 1 << XCHAL_TIMER0_INTERRUPT + wsr a2, intenable + waiti 0 + test_fail +2: + rsr a2, exccause + assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ +test_end + +#endif +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_windowed.S b/tests/tcg/xtensa/test_windowed.S new file mode 100644 index 000000000..5ead90a79 --- /dev/null +++ b/tests/tcg/xtensa/test_windowed.S @@ -0,0 +1,367 @@ +#include "macros.inc" + +test_suite windowed + +#if XCHAL_HAVE_WINDOWED + +.altmacro + +.macro reset_window start + movi a2, 0xffff + wsr a2, windowstart + rsync + movi a2, 0 + wsr a2, windowbase + rsync + movi a2, \start + wsr a2, windowstart + rsync +.endm + +.macro overflow_test shift, window, probe_ok, probe_ex + set_vector window_overflow_4, 0 + set_vector window_overflow_8, 0 + set_vector window_overflow_12, 0 + + movi a2, 1 | (((1 << ((\window) / 4)) | 1) << ((\shift) / 4)) + wsr a2, windowstart + reset_ps + + mov a2, a\probe_ok + set_vector window_overflow_\window, 10f +1: + mov a2, a\probe_ex + test_fail +10: + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 + movi a2, 2f + wsr a2, epc1 + + rsr a2, windowbase + movi a3, (\shift) / 4 + assert eq, a2, a3 + rsr a2, ps + movi a3, 0x4001f + assert eq, a2, a3 + rfwo + test_fail +2: + rsr a2, windowbase + assert eqi, a2, 0 + rsr a2, windowstart + movi a3, 1 | ((1 << ((\window) / 4)) << ((\shift) / 4)) + assert eq, a2, a3 + rsr a2, ps + movi a3, 0x4000f + assert eq, a2, a3 +.endm + +.macro overflow_tests shift, window, probe + .if \probe < 15 + overflow_test \shift, \window, %((\shift) - 1), \probe + overflow_tests \shift, \window, %((\probe) + 1) + .endif +.endm + +.macro all_overflow_tests + .irp shift, 4, 8, 12 + .irp window, 4, 8, 12 + overflow_tests \shift, \window, \shift + .endr + .endr +.endm + +test overflow + all_overflow_tests +test_end + + +.macro underflow_test window + set_vector window_underflow_4, 0 + set_vector window_underflow_8, 0 + set_vector window_underflow_12, 0 + + set_vector window_underflow_\window, 10f + + reset_window 1 + reset_ps + + ssai 2 + movi a2, 2f + slli a2, a2, 2 + movi a3, (\window) / 4 + src a0, a3, a2 +1: + retw + test_fail +10: + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 + movi a2, 2f + wsr a2, epc1 + + rsr a2, ps + movi a3, 0x4001f + assert eq, a2, a3 + rsr a2, windowbase + movi a3, (XCHAL_NUM_AREGS - (\window)) / 4 + assert eq, a2, a3 + rsr a2, windowstart + assert eqi, a2, 1 + rfwu +2: + rsr a2, ps + movi a3, 0x4000f + assert eq, a2, a3 + rsr a2, windowbase + assert eqi, a2, 0 + rsr a2, windowstart + assert bsi.l, a2, 0 + assert bsi.l, a2, (XCHAL_NUM_AREGS - (\window)) / 4 +.endm + +test underflow + set_vector window_overflow_4, 0 + set_vector window_overflow_8, 0 + set_vector window_overflow_12, 0 + + underflow_test 4 + underflow_test 8 + underflow_test 12 +test_end + + +.macro retw_test window + reset_window %(1 | (1 << ((XCHAL_NUM_AREGS - \window) / 4))) + reset_ps + + ssai 2 + movi a2, 1f + slli a2, a2, 2 + movi a3, (\window) / 4 + src a0, a3, a2 + retw + test_fail +1: + rsr a2, ps + movi a3, 0x4000f + assert eq, a2, a3 + rsr a2, windowbase + movi a3, (XCHAL_NUM_AREGS - (\window)) / 4 + assert eq, a2, a3 + rsr a2, windowstart + assert bci.l, a2, 0 + assert bsi.l, a2, (XCHAL_NUM_AREGS - (\window)) / 4 +.endm + +test retw + set_vector window_underflow_4, 0 + set_vector window_underflow_8, 0 + set_vector window_underflow_12, 0 + + retw_test 4 + retw_test 8 + retw_test 12 +test_end + +test movsp + set_vector kernel, 2f + + reset_window 1 + reset_ps +1: + movsp a2, a3 + test_fail +2: + rsr a2, exccause + assert eqi, a2, 5 + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 + + set_vector kernel, 0 + + reset_window %(0x1 | (1 << ((XCHAL_NUM_AREGS / 4) - 1))) + reset_ps + + movsp a2, a3 +test_end + +test rotw + reset_window 0x4b + reset_ps + + movi a3, 0x10 + + rotw 1 + rsr a2, windowbase + assert eqi, a2, 1 + movi a3, 0x11 + movi a7, 0x12 + + rotw 2 + rsr a2, windowbase + assert eqi, a2, 3 + movi a3, 0x13 + movi a7, 0x14 + movi a11, 0x15 + + rotw 3 + rsr a2, windowbase + assert eqi, a2, 6 + movi a3, 0x16 + movi a7, 0x17 + +#if XCHAL_NUM_AREGS == 32 + movi a2, 0x44 + wsr a2, windowstart +#elif XCHAL_NUM_AREGS == 64 + movi a2, 0x4004 + wsr a2, windowstart + rotw -8 +#else +#error XCHAL_NUM_AREGS unsupported +#endif + rsync + + movi a2, 0x10 + assert eq, a2, a11 + movi a11, 0x18 + movi a2, 0x11 + assert eq, a2, a15 + movi a15, 0x19 + + rotw 4 + movi a2, 0x12 + assert eq, a2, a3 + movi a2, 0x13 + assert eq, a2, a7 + movi a2, 0x14 + assert eq, a2, a11 + movi a2, 0x15 + assert eq, a2, a15 + + movi a2, 0x5 + wsr a2, windowstart + rsync + + rotw -2 + movi a2, 0x18 + assert eq, a2, a3 + movi a2, 0x19 + assert eq, a2, a7 +test_end + +.macro callw_test window + call\window 2f +1: + test_fail + .align 4 +2: + rsr a2, windowbase + assert eqi, a2, 0 + rsr a2, ps + movi a3, 0x4000f | ((\window) << 14) + assert eq, a2, a3 + movi a2, 1b + slli a2, a2, 2 + ssai 2 + movi a3, (\window) / 4 + src a2, a3, a2 + assert eq, a2, a\window +.endm + +test callw + reset_window 0x1 + reset_ps + + callw_test 4 + callw_test 8 + callw_test 12 +test_end + + +.macro entry_test window + reset_window 0x1 + reset_ps + movi a2, 0x4000f | ((\window) << 14) + wsr a2, ps + isync + movi a3, 0x12345678 + j 1f + .align 4 +1: + entry a3, 0x5678 + movi a2, 0x12340000 + assert eq, a2, a3 + rsr a2, windowbase + assert eqi, a2, (\window) / 4 + rsr a2, windowstart + movi a3, 1 | (1 << ((\window) / 4)) + assert eq, a2, a3 + rotw -(\window) / 4 +.endm + +test entry + entry_test 4 + entry_test 8 + entry_test 12 +test_end + +.macro entry_overflow_test window, free, next_window + set_vector window_overflow_4, 0 + set_vector window_overflow_8, 0 + set_vector window_overflow_12, 0 + set_vector window_overflow_\next_window, 10f + + movi a2, \window + movi a2, \free + movi a2, \next_window + reset_window %(1 | ((1 | (1 << ((\next_window) / 4))) << ((\free) / 4))) + reset_ps + movi a2, 0x4000f | ((\window) << 14) + wsr a2, ps + isync + movi a3, 0x12345678 + j 1f + .align 4 +1: + entry a3, 0x5678 + test_fail + .align 4 +10: + rsr a2, epc1 + movi a3, 1b + assert eq, a2, a3 + movi a2, 2f + wsr a2, epc1 + + rsr a2, windowbase + movi a3, (\free) / 4 + assert eq, a2, a3 + rfwo +2: +.endm + +.macro all_entry_overflow_tests + .irp window, 4, 8, 12 + .irp next_window, 4, 8, 12 + .irp free, 4, 8, 12 + .if \free <= \window + entry_overflow_test \window, \free, \next_window + .endif + .endr + .endr + .endr +.endm + +test entry_overflow + all_entry_overflow_tests +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/vectors.S b/tests/tcg/xtensa/vectors.S new file mode 100644 index 000000000..cd48cfb65 --- /dev/null +++ b/tests/tcg/xtensa/vectors.S @@ -0,0 +1,65 @@ +#include "core-isa.h" + +.macro vector name + +.section .vector.\name, "ax" +.global vector_\name +vector_\name\(): + j 1f + .literal_position +1: + wsr a0, excsave1 + movi a0, 1f + ret.n + +.section .vector.\name\().text, "ax" + .literal_position +1: + rsr a0, excsave1 + wsr a2, excsave1 + movi a2, handler_\name + l32i a2, a2, 0 + beqz a2, 1f + jx a2 +1: + movi a3, 1b + movi a2, 1 + simcall + +.align 4 +.global handler_\name +handler_\name\(): .word 0 + +.endm + +#if XCHAL_HAVE_WINDOWED +vector window_overflow_4 +vector window_overflow_8 +vector window_overflow_12 +vector window_underflow_4 +vector window_underflow_8 +vector window_underflow_12 +#endif + +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2 +vector level2 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3 +vector level3 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4 +vector level4 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5 +vector level5 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6 +vector level6 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7 +vector level7 +#endif + +vector kernel +vector user +vector double |