aboutsummaryrefslogtreecommitdiffstats
path: root/capstone/suite/synctools/registerinfo.py
blob: 27e05d287a550010bc218cbd028688c9f6aaf21e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
#!/usr/bin/python
# convert LLVM GenRegisterInfo.inc for Capstone disassembler.
# by Nguyen Anh Quynh, 2019

import sys

if len(sys.argv) == 1:
    print("Syntax: %s <GenRegisterInfo.inc> <architecture>" %sys.argv[0])
    sys.exit(1)

f = open(sys.argv[1])
lines = f.readlines()
f.close()

arch = sys.argv[2]

print("""
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
""")

enum_count = 0

# 1st enum is register enum
for line in lines:
    line = line.rstrip()

    if len(line.strip()) == 0:
        continue

    if line.strip() == 'enum {':
        enum_count += 1
        print(line)
        continue

    if enum_count == 1:
        if line.strip() == '};':
            print(line)
            # done with first enum
            break
        else:
            # enum items
            print("  %s_%s" %(arch, line.strip()))

# 2nd enum is register class
enum_count = 0
print("\n// Register classes")
for line in lines:
    line = line.rstrip()

    if len(line.strip()) == 0:
        continue

    if line.strip() == 'enum {':
        enum_count += 1
        if enum_count == 2:
            print(line)
        continue

    if enum_count == 2:
        if line.strip() == '};':
            # done with 2nd enum
            print(line.strip())
            break
        else:
            # enum items
            print("  %s_%s" %(arch, line.strip()))

if arch.upper() == 'ARM':
    # 3rd enum is Subregister indices
    enum_count = 0
    print("\n// Subregister indices")
    for line in lines:
        line = line.rstrip()
    
        if len(line.strip()) == 0:
            continue
    
        if line.strip() == 'enum {':
            enum_count += 1
            if enum_count == 3:
                print(line)
            continue
    
        if enum_count == 3:
            if line.strip() == '};':
                # done with 2nd enum
                print(line.strip())
                break
            else:
                # enum items
                print("  %s_%s" %(arch, line.strip()))

if arch.upper() == 'AARCH64':
    # 3rd enum is Register alternate name indices
    enum_count = 0
    print("\n// Register alternate name indices")
    for line in lines:
        line = line.rstrip()
    
        if len(line.strip()) == 0:
            continue
    
        if line.strip() == 'enum {':
            enum_count += 1
            if enum_count == 3:
                print(line)
            continue
    
        if enum_count == 3:
            if line.strip() == '};':
                # done with 2nd enum
                print(line.strip())
                break
            else:
                # enum items
                print("  %s_%s" %(arch, line.strip()))

    # 4th enum is Subregister indices
    enum_count = 0
    print("\n// Subregister indices")
    for line in lines:
        line = line.rstrip()
    
        if len(line.strip()) == 0:
            continue
    
        if line.strip() == 'enum {':
            enum_count += 1
            if enum_count == 4:
                print(line)
            continue
    
        if enum_count == 4:
            if line.strip() == '};':
                # done with 2nd enum
                print(line.strip())
                break
            else:
                # enum items
                print("  %s_%s" %(arch, line.strip()))

# end of enum
print("")
print("#endif // GET_REGINFO_ENUM")

print("""
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

""")

# extract RegDiffLists
finding_struct = True
for line in lines:
    line = line.rstrip()

    if len(line.strip()) == 0:
        continue

    if arch + 'RegDiffLists' in line:
        finding_struct = False
        print("static const MCPhysReg " + arch + "RegDiffLists[] = {")
        continue

    if finding_struct:
        continue
    else:
        print(line)
        if line == '};':
            # done with this struct
            print("")
            break

# extract SubRegIdxLists
finding_struct = True
for line in lines:
    line = line.rstrip()

    if len(line.strip()) == 0:
        continue

    if arch + 'SubRegIdxLists' in line:
        finding_struct = False
        print("static const uint16_t " + arch + "SubRegIdxLists[] = {")
        continue

    if finding_struct:
        continue
    else:
        print(line)
        if line == '};':
            # done with this struct
            print("")
            break

# extract RegDesc
finding_struct = True
for line in lines:
    line = line.rstrip()

    if len(line.strip()) == 0:
        continue

    if arch + 'RegDesc' in line:
        finding_struct = False
        print("static const MCRegisterDesc " + arch + "RegDesc[] = {")
        continue

    if finding_struct:
        continue
    else:
        print(line)
        if line == '};':
            # done with this struct
            print("")
            break

# extract register classes
finding_struct = True
for line in lines:
    line = line.rstrip()

    if len(line.strip()) == 0:
        continue

    if 'Register classes' in line and 'namespace' in line:
        finding_struct = False
        continue

    if finding_struct:
        continue
    else:
        if 'const' in line:
            line2 = line.replace('const', 'static const')
            print(line2)
        elif '::' in line:
            line2 = line.replace('::', '_')
            print(line2)
        elif 'end anonymous namespace' in line:
            # done with this struct
            break
        else:
            print(line)

print("\n")

# extract MCRegisterClasses
finding_struct = True
for line in lines:
    line = line.rstrip()

    if len(line.strip()) == 0:
        continue

    if 'MCRegisterClass ' + arch + 'MCRegisterClasses[] = {' in line:
        finding_struct = False
        print("static const MCRegisterClass " + arch + "MCRegisterClasses[] = {")
        continue

    if finding_struct:
        continue
    else:
        if line == '};':
            # done with this struct
            print('};\n')
            break
        elif '::' in line:
            line = line.replace('::', '_')

        # { GR8, GR8Bits, 130, 20, sizeof(GR8Bits), X86_GR8RegClassID, 1, 1, 1, 1 },
        tmp = line.split(',')
        print("  %s, %s, %s }," %(tmp[0].strip(), tmp[1].strip(), tmp[4].strip()))

print("#endif // GET_REGINFO_MC_DESC")