blob: df418cfcd36cbe3994de9964f8f92b9fb39e80ee (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
/*
* ASPEED LPC Controller
*
* Copyright (C) 2017-2018 IBM Corp.
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*/
#ifndef ASPEED_LPC_H
#define ASPEED_LPC_H
#include "hw/sysbus.h"
#include <stdint.h>
#define TYPE_ASPEED_LPC "aspeed.lpc"
#define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC)
#define ASPEED_LPC_NR_REGS (0x260 >> 2)
enum aspeed_lpc_subdevice {
aspeed_lpc_kcs_1 = 0,
aspeed_lpc_kcs_2,
aspeed_lpc_kcs_3,
aspeed_lpc_kcs_4,
aspeed_lpc_ibt,
};
#define ASPEED_LPC_NR_SUBDEVS 5
typedef struct AspeedLPCState {
/* <private> */
SysBusDevice parent;
/*< public >*/
MemoryRegion iomem;
qemu_irq irq;
qemu_irq subdevice_irqs[ASPEED_LPC_NR_SUBDEVS];
uint32_t subdevice_irqs_pending;
uint32_t regs[ASPEED_LPC_NR_REGS];
uint32_t hicr7;
} AspeedLPCState;
#endif /* _ASPEED_LPC_H_ */
|
