blob: b4ee8e7f6c40b7198a56b14d500a2cd959d5c4f7 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
/*
* Arm SSE Subsystem System Timer
*
* Copyright (c) 2020 Linaro Limited
* Written by Peter Maydell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or
* (at your option) any later version.
*/
/*
* This is a model of the "System timer" which is documented in
* the Arm SSE-123 Example Subsystem Technical Reference Manual:
* https://developer.arm.com/documentation/101370/latest/
*
* QEMU interface:
* + QOM property "counter": link property to be set to the
* TYPE_SSE_COUNTER timestamp counter device this timer runs off
* + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: timer interrupt
*/
#ifndef SSE_TIMER_H
#define SSE_TIMER_H
#include "hw/sysbus.h"
#include "qom/object.h"
#include "hw/timer/sse-counter.h"
#define TYPE_SSE_TIMER "sse-timer"
OBJECT_DECLARE_SIMPLE_TYPE(SSETimer, SSE_TIMER)
struct SSETimer {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
qemu_irq irq;
SSECounter *counter;
QEMUTimer timer;
Notifier counter_notifier;
uint32_t cntfrq;
uint32_t cntp_ctl;
uint64_t cntp_cval;
uint64_t cntp_aival;
uint32_t cntp_aival_ctl;
uint32_t cntp_aival_reload;
};
#endif
|