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Diffstat (limited to 'bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0006-armv8-lx2160acex7-board-support-files.patch')
-rw-r--r--bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0006-armv8-lx2160acex7-board-support-files.patch519
1 files changed, 519 insertions, 0 deletions
diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0006-armv8-lx2160acex7-board-support-files.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0006-armv8-lx2160acex7-board-support-files.patch
new file mode 100644
index 00000000..c38abbf9
--- /dev/null
+++ b/bsp/meta-freescale-3rdparty/recipes-bsp/u-boot/u-boot-qoriq-lx2160acex7/0006-armv8-lx2160acex7-board-support-files.patch
@@ -0,0 +1,519 @@
+From c42a926fb0ff087b8c5cb774a67fb64aa1a566ce Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 13:45:24 +0300
+Subject: [PATCH 06/17] armv8: lx2160acex7: board support files
+
+The lx2160acex7 board support files does the following -
+1. Initializes 1GBps PHY address according to SERDES1 block config.
+2. Sets uart0 as the console
+3. Sets EMC2301 PWM fan controller to it's default value
+4. Misc FDT fixups prior to booting Linux
+
+Upstream-Status: Inappropriate [Solid-Run BSP]
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ board/solidrun/lx2160a/Kconfig | 22 ++
+ board/solidrun/lx2160a/MAINTAINERS | 8 +
+ board/solidrun/lx2160a/Makefile | 9 +
+ board/solidrun/lx2160a/ddr.c | 20 ++
+ board/solidrun/lx2160a/eth_lx2160acex7.c | 104 ++++++++
+ board/solidrun/lx2160a/lx2160a.c | 288 +++++++++++++++++++++++
+ 6 files changed, 451 insertions(+)
+ create mode 100644 board/solidrun/lx2160a/Kconfig
+ create mode 100644 board/solidrun/lx2160a/MAINTAINERS
+ create mode 100644 board/solidrun/lx2160a/Makefile
+ create mode 100644 board/solidrun/lx2160a/ddr.c
+ create mode 100644 board/solidrun/lx2160a/eth_lx2160acex7.c
+ create mode 100644 board/solidrun/lx2160a/lx2160a.c
+
+diff --git a/board/solidrun/lx2160a/Kconfig b/board/solidrun/lx2160a/Kconfig
+new file mode 100644
+index 0000000000..85abac9bfc
+--- /dev/null
++++ b/board/solidrun/lx2160a/Kconfig
+@@ -0,0 +1,22 @@
++if TARGET_LX2160ACEX7
++
++config SYS_BOARD
++ default "lx2160a"
++
++config SYS_VENDOR
++ default "solidrun"
++
++config SYS_SOC
++ default "fsl-layerscape"
++
++config SYS_CONFIG_NAME
++ default "lx2160acex7"
++
++config EMC2301
++ bool "Fan controller"
++ help
++ Enable the EMC2301 fan controller for configuration of fan
++ speed.
++
++source "board/freescale/common/Kconfig"
++endif
+diff --git a/board/solidrun/lx2160a/MAINTAINERS b/board/solidrun/lx2160a/MAINTAINERS
+new file mode 100644
+index 0000000000..688ff66afa
+--- /dev/null
++++ b/board/solidrun/lx2160a/MAINTAINERS
+@@ -0,0 +1,8 @@
++LX2160ACEX7 BOARD
++M: Rabeeh Khoury <rabeeh@solid-run.com>
++S: Maintained
++F: board/solidrun/lx2160a/
++F: include/configs/lx2160a_common.h
++F: include/configs/lx2160acex7.h
++F: configs/lx2160acex7_tfa_defconfig
++F: arch/arm/dts/fsl-lx2160a-cex7.dts
+diff --git a/board/solidrun/lx2160a/Makefile b/board/solidrun/lx2160a/Makefile
+new file mode 100644
+index 0000000000..c92266f322
+--- /dev/null
++++ b/board/solidrun/lx2160a/Makefile
+@@ -0,0 +1,9 @@
++#
++# Copyright 2019 SolidRun ltd.
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y += lx2160a.o
++obj-y += ddr.o
++obj-$(CONFIG_TARGET_LX2160ACEX7) += eth_lx2160acex7.o
+diff --git a/board/solidrun/lx2160a/ddr.c b/board/solidrun/lx2160a/ddr.c
+new file mode 100644
+index 0000000000..9c7bd10475
+--- /dev/null
++++ b/board/solidrun/lx2160a/ddr.c
+@@ -0,0 +1,20 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2019 SolidRun ltd.
++ */
++
++#include <common.h>
++#include <fsl_ddr_sdram.h>
++#include <fsl_ddr_dimm_params.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int fsl_initdram(void)
++{
++ gd->ram_size = tfa_get_dram_size();
++
++ if (!gd->ram_size)
++ gd->ram_size = fsl_ddr_sdram_size();
++
++ return 0;
++}
+diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
+new file mode 100644
+index 0000000000..97e414838f
+--- /dev/null
++++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
+@@ -0,0 +1,104 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2019 SolidRun ltd.
++ *
++ */
++
++#include <common.h>
++#include <command.h>
++#include <netdev.h>
++#include <malloc.h>
++#include <fsl_mdio.h>
++#include <miiphy.h>
++#include <phy.h>
++#include <fm_eth.h>
++#include <asm/io.h>
++#include <exports.h>
++#include <asm/arch/fsl_serdes.h>
++#include <fsl-mc/fsl_mc.h>
++#include <fsl-mc/ldpaa_wriop.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int board_eth_init(bd_t *bis)
++{
++#if defined(CONFIG_FSL_MC_ENET)
++ struct memac_mdio_info mdio_info;
++ struct memac_mdio_controller *reg;
++ int i, interface;
++ struct mii_dev *dev;
++ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
++ u32 srds_s1;
++
++ srds_s1 = in_le32(&gur->rcwsr[28]) &
++ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
++ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
++
++ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
++ mdio_info.regs = reg;
++ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
++
++ /* Register the EMI 1 */
++ fm_memac_mdio_init(bis, &mdio_info);
++
++ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
++ RGMII_PHY_ADDR1);
++ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
++ switch (srds_s1) {
++ case 3:
++ case 5:
++ case 8:
++ case 13:
++ case 14:
++ case 15:
++ case 17:
++ case 20:
++ case 23:
++ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
++ RGMII_PHY_ADDR1);
++ break;
++
++ default:
++ printf("SerDes1 protocol 0x%x is not supported on LX2160ACEX7\n",
++ srds_s1);
++ goto next;
++ }
++ for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC17; i++) {
++ interface = wriop_get_enet_if(i);
++ switch (interface) {
++ case PHY_INTERFACE_MODE_RGMII:
++ case PHY_INTERFACE_MODE_RGMII_ID:
++ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
++ wriop_set_mdio(i, dev);
++ break;
++ default:
++ break;
++ }
++ }
++
++next:
++ cpu_eth_init(bis);
++#endif /* CONFIG_FSL_MC_ENET */
++
++ return pci_eth_init(bis);
++}
++
++#if defined(CONFIG_RESET_PHY_R)
++void reset_phy(void)
++{
++#if defined(CONFIG_FSL_MC_ENET)
++ mc_env_boot();
++#endif
++}
++#endif /* CONFIG_RESET_PHY_R */
++
++int fdt_fixup_board_phy(void *fdt)
++{
++ int mdio_offset;
++ int ret;
++ struct mii_dev *dev;
++
++ ret = 0;
++
++ return ret;
++}
+diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
+new file mode 100644
+index 0000000000..b0d9f1012e
+--- /dev/null
++++ b/board/solidrun/lx2160a/lx2160a.c
+@@ -0,0 +1,288 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2019 SolidRun ltd.
++ */
++
++#include <common.h>
++#include <dm.h>
++#include <dm/platform_data/serial_pl01x.h>
++#include <i2c.h>
++#include <malloc.h>
++#include <errno.h>
++#include <netdev.h>
++#include <fsl_ddr.h>
++#include <fsl_sec.h>
++#include <asm/io.h>
++#include <fdt_support.h>
++#include <linux/libfdt.h>
++#include <fsl-mc/fsl_mc.h>
++#include <environment.h>
++#include <efi_loader.h>
++#include <asm/arch/mmu.h>
++#include <hwconfig.h>
++#include <asm/arch/fsl_serdes.h>
++#include <asm/arch/soc.h>
++#include "../../freescale/common/vid.h"
++#include <fsl_immap.h>
++
++#ifdef CONFIG_EMC2301
++#include "../common/emc2301.h"
++#endif
++
++
++DECLARE_GLOBAL_DATA_PTR;
++
++static struct pl01x_serial_platdata serial0 = {
++#if CONFIG_CONS_INDEX == 0
++ .base = CONFIG_SYS_SERIAL0,
++#elif CONFIG_CONS_INDEX == 1
++ .base = CONFIG_SYS_SERIAL1,
++#else
++#error "Unsupported console index value."
++#endif
++ .type = TYPE_PL011,
++};
++
++U_BOOT_DEVICE(nxp_serial0) = {
++ .name = "serial_pl01x",
++ .platdata = &serial0,
++};
++
++static struct pl01x_serial_platdata serial1 = {
++ .base = CONFIG_SYS_SERIAL1,
++ .type = TYPE_PL011,
++};
++
++U_BOOT_DEVICE(nxp_serial1) = {
++ .name = "serial_pl01x",
++ .platdata = &serial1,
++};
++
++int select_i2c_ch_pca9547(u8 ch)
++{
++ int ret;
++
++ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
++ if (ret) {
++ puts("PCA: failed to select proper channel\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static void uart_get_clock(void)
++{
++ serial0.clock = get_serial_clock();
++ serial1.clock = get_serial_clock();
++}
++
++int board_early_init_f(void)
++{
++#ifdef CONFIG_SYS_I2C_EARLY_INIT
++ i2c_early_init_f();
++#endif
++ /* get required clock for UART IP */
++ uart_get_clock();
++
++#ifdef CONFIG_EMC2301
++ select_i2c_ch_pca9547(I2C_MUX_CH_EMC2301);
++ emc2301_init();
++ set_fan_speed(I2C_EMC2301_PWM);
++ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
++#endif
++ fsl_lsch3_early_init_f();
++ return 0;
++}
++
++#ifdef CONFIG_OF_BOARD_FIXUP
++int board_fix_fdt(void *fdt)
++{
++ return 0;
++}
++#endif
++
++int esdhc_status_fixup(void *blob, const char *compat)
++{
++ /* Enable both esdhc DT nodes for LX2160ARDB */
++ do_fixup_by_compat(blob, compat, "status", "okay",
++ sizeof("okay"), 1);
++ return 0;
++}
++
++#if defined(CONFIG_VID)
++int i2c_multiplexer_select_vid_channel(u8 channel)
++{
++ return select_i2c_ch_pca9547(channel);
++}
++
++#endif
++
++int checkboard(void)
++{
++ enum boot_src src = get_boot_src();
++ char buf[64];
++ cpu_name(buf);
++ printf("Board: %s-CEX7, ", buf);
++
++ if (src == BOOT_SOURCE_SD_MMC) {
++ puts("SD\n");
++ }
++ puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz\n");
++ puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
++ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
++ return 0;
++}
++
++int config_board_mux(void)
++{
++ return 0;
++}
++
++unsigned long get_board_sys_clk(void)
++{
++ return 100000000;
++}
++
++unsigned long get_board_ddr_clk(void)
++{
++ return 100000000;
++}
++
++int board_init(void)
++{
++#ifdef CONFIG_ENV_IS_NOWHERE
++ gd->env_addr = (ulong)&default_environment[0];
++#endif
++
++ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
++
++#ifdef CONFIG_FSL_CAAM
++ sec_init();
++#endif
++
++ return 0;
++}
++
++void detail_board_ddr_info(void)
++{
++ int i;
++ u64 ddr_size = 0;
++
++ puts("\nDDR ");
++ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
++ ddr_size += gd->bd->bi_dram[i].size;
++ print_size(ddr_size, "");
++ print_ddr_info(0);
++}
++
++#if defined(CONFIG_ARCH_MISC_INIT)
++int arch_misc_init(void)
++{
++ config_board_mux();
++
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_FSL_MC_ENET
++extern int fdt_fixup_board_phy(void *fdt);
++
++void fdt_fixup_board_enet(void *fdt)
++{
++ int offset;
++
++ offset = fdt_path_offset(fdt, "/soc/fsl-mc");
++
++ if (offset < 0)
++ offset = fdt_path_offset(fdt, "/fsl-mc");
++
++ if (offset < 0) {
++ printf("%s: fsl-mc node not found in device tree (error %d)\n",
++ __func__, offset);
++ return;
++ }
++
++ if (get_mc_boot_status() == 0 &&
++ (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
++ fdt_status_okay(fdt, offset);
++ fdt_fixup_board_phy(fdt);
++ } else {
++ fdt_status_fail(fdt, offset);
++ }
++}
++
++void board_quiesce_devices(void)
++{
++ fsl_mc_ldpaa_exit(gd->bd);
++}
++#endif
++
++#ifdef CONFIG_OF_BOARD_SETUP
++
++int ft_board_setup(void *blob, bd_t *bd)
++{
++ int i;
++ bool mc_memory_bank = false;
++
++ u64 *base;
++ u64 *size;
++ u64 mc_memory_base = 0;
++ u64 mc_memory_size = 0;
++ u16 total_memory_banks;
++
++ ft_cpu_setup(blob, bd);
++
++ fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
++
++ if (mc_memory_base != 0)
++ mc_memory_bank = true;
++
++ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
++
++ base = calloc(total_memory_banks, sizeof(u64));
++ size = calloc(total_memory_banks, sizeof(u64));
++
++ /* fixup DT for the three GPP DDR banks */
++ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
++ base[i] = gd->bd->bi_dram[i].start;
++ size[i] = gd->bd->bi_dram[i].size;
++ }
++
++#ifdef CONFIG_RESV_RAM
++ /* reduce size if reserved memory is within this bank */
++ if (gd->arch.resv_ram >= base[0] &&
++ gd->arch.resv_ram < base[0] + size[0])
++ size[0] = gd->arch.resv_ram - base[0];
++ else if (gd->arch.resv_ram >= base[1] &&
++ gd->arch.resv_ram < base[1] + size[1])
++ size[1] = gd->arch.resv_ram - base[1];
++ else if (gd->arch.resv_ram >= base[2] &&
++ gd->arch.resv_ram < base[2] + size[2])
++ size[2] = gd->arch.resv_ram - base[2];
++#endif
++
++ if (mc_memory_base != 0) {
++ for (i = 0; i <= total_memory_banks; i++) {
++ if (base[i] == 0 && size[i] == 0) {
++ base[i] = mc_memory_base;
++ size[i] = mc_memory_size;
++ break;
++ }
++ }
++ }
++
++ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
++
++#ifdef CONFIG_USB
++ fsl_fdt_fixup_dr_usb(blob, bd);
++#endif
++
++#ifdef CONFIG_FSL_MC_ENET
++ fdt_fsl_mc_fixup_iommu_map_entry(blob);
++ fdt_fixup_board_enet(blob);
++#endif
++
++ return 0;
++}
++#endif
+--
+2.17.1
+