diff options
Diffstat (limited to 'bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0437-clk-renesas-r8a77965-cpg-mssr-Add-RPC-clocks.patch')
| -rw-r--r-- | bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0437-clk-renesas-r8a77965-cpg-mssr-Add-RPC-clocks.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0437-clk-renesas-r8a77965-cpg-mssr-Add-RPC-clocks.patch b/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0437-clk-renesas-r8a77965-cpg-mssr-Add-RPC-clocks.patch new file mode 100644 index 00000000..c51385cc --- /dev/null +++ b/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0437-clk-renesas-r8a77965-cpg-mssr-Add-RPC-clocks.patch @@ -0,0 +1,51 @@ +From c76e22071bc721ccd05a7e1acbe9a0e4ea078385 Mon Sep 17 00:00:00 2001 +From: Valentine Barshak <valentine.barshak@cogentembedded.com> +Date: Mon, 4 Nov 2019 01:00:35 +0300 +Subject: [PATCH 03/12] clk: renesas: r8a77965-cpg-mssr: Add RPC clocks + +This adds RPC clock support to the R8A77965 CPG MSSR driver. + +Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> +--- + drivers/clk/renesas/r8a77965-cpg-mssr.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c +index 3d4fe53..dbcd320 100644 +--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c +@@ -43,6 +43,7 @@ enum clk_ids { + CLK_S3, + CLK_SDSRC, + CLK_SSPSRC, ++ CLK_RPCSRC, + CLK_RINT, + + /* Module Clocks */ +@@ -68,9 +69,15 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { + DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), ++ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), + + DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), + ++ DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, ++ CLK_RPCSRC), ++ DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, ++ R8A77965_CLK_RPC), ++ + /* Core Clock Outputs */ + DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("zg", R8A77965_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4), +@@ -215,6 +222,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { + DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2), + DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4), ++ DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2), + DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6), + DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6), + DEF_MOD("adg", 922, R8A77965_CLK_S0D1), +-- +2.7.4 + |