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Diffstat (limited to 'bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0512-arm64-dts-renesas-add-H3-GMSL2-Videobox.patch')
-rw-r--r--bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0512-arm64-dts-renesas-add-H3-GMSL2-Videobox.patch1949
1 files changed, 1949 insertions, 0 deletions
diff --git a/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0512-arm64-dts-renesas-add-H3-GMSL2-Videobox.patch b/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0512-arm64-dts-renesas-add-H3-GMSL2-Videobox.patch
new file mode 100644
index 00000000..198d1daf
--- /dev/null
+++ b/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0512-arm64-dts-renesas-add-H3-GMSL2-Videobox.patch
@@ -0,0 +1,1949 @@
+From fabd912331128d45339dd6f9282aa623c1b92bb1 Mon Sep 17 00:00:00 2001
+From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Date: Thu, 30 Apr 2020 16:34:44 +0300
+Subject: [PATCH 2/2] arm64: dts: renesas: add H3 GMSL2 Videobox
+
+This is GMSL2 RCAR H3 Videobox 2.1 support
+This is interim support since all serializers soon will
+be integrated to PnP.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+---
+ arch/arm64/boot/dts/renesas/Makefile | 1 +
+ .../renesas/r8a7795-h3ulcb-4x2g-vb2.1-gmsl2.dts | 68 +
+ .../dts/renesas/r8a7795-h3ulcb-vb2.1-gmsl2.dts | 68 +
+ arch/arm64/boot/dts/renesas/ulcb-vb2-gmsl2.dtsi | 1662 ++++++++++++++++++++
+ arch/arm64/boot/dts/renesas/ulcb-vb2.1-gmsl2.dtsi | 90 ++
+ 5 files changed, 1889 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-4x2g-vb2.1-gmsl2.dts
+ create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.1-gmsl2.dts
+ create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb2-gmsl2.dtsi
+ create mode 100644 arch/arm64/boot/dts/renesas/ulcb-vb2.1-gmsl2.dtsi
+
+diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
+index f18c742..cd53aaf 100644
+--- a/arch/arm64/boot/dts/renesas/Makefile
++++ b/arch/arm64/boot/dts/renesas/Makefile
+@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb r8a7795-h3ulcb-4x2g-kf.dtb r
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vb.dtb r8a7795-es1-h3ulcb-vb.dtb r8a7795-h3ulcb-4x2g-vb.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vb2.dtb r8a7795-es1-h3ulcb-vb2.dtb r8a7795-h3ulcb-4x2g-vb2.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vb2.1.dtb r8a7795-h3ulcb-4x2g-vb2.1.dtb
++dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vb2.1-gmsl2.dtb r8a7795-h3ulcb-4x2g-vb2.1-gmsl2.dtb
+ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-vbm.dtb r8a7795-es1-h3ulcb-vbm.dtb r8a7795-h3ulcb-4x2g-vbm.dtb
+ dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb-kf.dtb
+ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle-function.dtb
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-4x2g-vb2.1-gmsl2.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-4x2g-vb2.1-gmsl2.dts
+new file mode 100644
+index 0000000..54170c9
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-4x2g-vb2.1-gmsl2.dts
+@@ -0,0 +1,68 @@
++/*
++ * Device Tree Source for the 8GB H3ULCB Videobox board V2.1 on r8a7795
++ *
++ * Copyright (C) 2019 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "r8a7795-h3ulcb-4x2g.dts"
++#include "ulcb-vb2.1-gmsl2.dtsi"
++
++/ {
++ model = "Renesas H3ULCB Videobox V2.1 board based on r8a7795 with 8GiB (4 x 2 GiB)";
++
++ hdmi1-out {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi1_con: endpoint {
++ remote-endpoint = <&rcar_dw_hdmi1_out>;
++ };
++ };
++ };
++};
++
++&du {
++ ports {
++ port@2 {
++ endpoint {
++ remote-endpoint = <&rcar_dw_hdmi1_in>;
++ };
++ };
++ port@3 {
++ endpoint {
++ remote-endpoint = <&lvds_in>;
++ };
++ };
++ };
++};
++
++&hdmi1 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ rcar_dw_hdmi1_in: endpoint {
++ remote-endpoint = <&du_out_hdmi1>;
++ };
++ };
++ port@1 {
++ reg = <1>;
++ rcar_dw_hdmi1_out: endpoint {
++ remote-endpoint = <&hdmi1_con>;
++ };
++ };
++ };
++};
++
++&hsusb {
++ status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.1-gmsl2.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.1-gmsl2.dts
+new file mode 100644
+index 0000000..144b035
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-vb2.1-gmsl2.dts
+@@ -0,0 +1,68 @@
++/*
++ * Device Tree Source for the H3ULCB Videobox board V2.1 on r8a7795
++ *
++ * Copyright (C) 2019 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "r8a7795-h3ulcb.dts"
++#include "ulcb-vb2.1-gmsl2.dtsi"
++
++/ {
++ model = "Renesas H3ULCB Videobox V2.1 board based on r8a7795";
++
++ hdmi1-out {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi1_con: endpoint {
++ remote-endpoint = <&rcar_dw_hdmi1_out>;
++ };
++ };
++ };
++};
++
++&du {
++ ports {
++ port@2 {
++ endpoint {
++ remote-endpoint = <&rcar_dw_hdmi1_in>;
++ };
++ };
++ port@3 {
++ endpoint {
++ remote-endpoint = <&lvds_in>;
++ };
++ };
++ };
++};
++
++&hdmi1 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ rcar_dw_hdmi1_in: endpoint {
++ remote-endpoint = <&du_out_hdmi1>;
++ };
++ };
++ port@1 {
++ reg = <1>;
++ rcar_dw_hdmi1_out: endpoint {
++ remote-endpoint = <&hdmi1_con>;
++ };
++ };
++ };
++};
++
++&hsusb {
++ status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb2-gmsl2.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb2-gmsl2.dtsi
+new file mode 100644
+index 0000000..64f54f5
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/ulcb-vb2-gmsl2.dtsi
+@@ -0,0 +1,1662 @@
++/*
++ * Device Tree Source for the ULCB Videobox V2 board
++ *
++ * Copyright (C) 2018 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "camera.dtsi"
++
++/ {
++ cs2300_ref_clk: cs2300_ref_clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <25000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ led5 {
++ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
++ };
++ led6 {
++ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
++ };
++ /* D13 - status 0 */
++ led_ext00 {
++ gpios = <&gpio_ext_led 0 GPIO_ACTIVE_LOW>;
++ /* linux,default-trigger = "heartbeat"; */
++ };
++ /* D14 - status 1 */
++ led_ext01 {
++ gpios = <&gpio_ext_led 1 GPIO_ACTIVE_LOW>;
++ /* linux,default-trigger = "mmc1"; */
++ };
++ /* D16 - HDMI0 */
++ led_ext02 {
++ gpios = <&gpio_ext_led 2 GPIO_ACTIVE_LOW>;
++ };
++ /* D18 - HDMI1 */
++ led_ext03 {
++ gpios = <&gpio_ext_led 3 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ vcc_sdhi3: regulator-vcc-sdhi3 {
++ compatible = "regulator-fixed";
++
++ regulator-name = "SDHI3 Vcc";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ vccq_sdhi3: regulator-vccq-sdhi3 {
++ compatible = "regulator-fixed";
++
++ regulator-name = "SDHI3 VccQ";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ fpdlink_switch: regulator@8 {
++ compatible = "regulator-fixed";
++ regulator-name = "fpdlink_on";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio1 20 0>;
++ enable-active-high;
++ regulator-always-on;
++ };
++
++ can2_power: regulator@9 {
++ compatible = "regulator-fixed";
++ regulator-name = "can2_power";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio_ext_pwr 8 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ can3_power: regulator@10 {
++ compatible = "regulator-fixed";
++ regulator-name = "can3_power";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio_ext_pwr 9 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ lvds {
++ compatible = "panel-lvds";
++
++ width-mm = <210>;
++ height-mm = <158>;
++
++ data-mapping = "jeida-24";
++
++ panel-timing {
++ /* 1280x800 @60Hz */
++ clock-frequency = <65000000>;
++ hactive = <1280>;
++ vactive = <800>;
++ hsync-len = <40>;
++ hfront-porch = <80>;
++ hback-porch = <40>;
++ vfront-porch = <14>;
++ vback-porch = <14>;
++ vsync-len = <4>;
++ };
++
++ port {
++ lvds_in: endpoint {
++ remote-endpoint = <&du_out_lvds0>;
++ };
++ };
++ };
++
++ excan_ref_clk: excan-ref-clock {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <16000000>;
++ };
++
++ spi_gpio_sw {
++ compatible = "spi-gpio";
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ gpio-sck = <&gpio0 8 GPIO_ACTIVE_HIGH>;
++ gpio-miso = <&gpio0 10 GPIO_ACTIVE_HIGH>;
++ gpio-mosi = <&gpio0 11 GPIO_ACTIVE_HIGH>;
++ cs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
++ num-chipselects = <1>;
++
++ spidev: spidev@0 {
++ compatible = "spidev", "spi-gpio";
++ reg = <0>;
++ spi-max-frequency = <25000000>;
++ spi-cpha;
++ spi-cpol;
++ };
++ };
++
++ spi_gpio_can {
++ compatible = "spi-gpio";
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ gpio-sck = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++ gpio-miso = <&gpio1 3 GPIO_ACTIVE_HIGH>;
++ gpio-mosi = <&gpio1 1 GPIO_ACTIVE_HIGH>;
++ cs-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
++ &gpio1 4 GPIO_ACTIVE_HIGH>;
++ num-chipselects = <2>;
++
++ spican0: spidev@0 {
++ compatible = "microchip,mcp2515";
++ reg = <0>;
++ clocks = <&excan_ref_clk>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <15 GPIO_ACTIVE_LOW>;
++ spi-max-frequency = <10000000>;
++ vdd-supply = <&can2_power>;
++ };
++ spican1: spidev@1 {
++ compatible = "microchip,mcp2515";
++ reg = <1>;
++ clocks = <&excan_ref_clk>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <5 GPIO_ACTIVE_LOW>;
++ spi-max-frequency = <10000000>;
++ vdd-supply = <&can3_power>;
++ };
++ };
++
++ /* camera slot A */
++ iio_hwmon_a: hwmon_a@1 {
++ compatible = "iio-hwmon";
++ io-channels =
++ /* current */
++ <&max2008x_a 0>,
++ <&max2008x_a 2>,
++ /* voltage */
++ <&max2008x_a 4>,
++ <&max2008x_a 6>,
++ /* misc voltages */
++ <&max2008x_a 8>,
++ <&max2008x_a 9>;
++ io-channel-names =
++ "camera-A-0-Iout",
++ "camera-A-1-Iout",
++ "camera-A-0-Vout",
++ "camera-A-1-Vout",
++ "cameras-A-Vregulator",
++ "cameras-A-3v3";
++ };
++};
++
++&pfc {
++ hscif4_pins: hscif4 {
++ groups = "hscif4_data_a", "hscif4_ctrl";
++ function = "hscif4";
++ };
++
++ usb0_pins: usb0 {
++ groups = "usb0";
++ function = "usb0";
++ };
++
++ usb2_pins: usb2 {
++ groups = "usb2";
++ function = "usb2";
++ };
++
++ usb30_pins: usb30 {
++ groups = "usb30";
++ function = "usb30";
++ };
++
++ can0_pins: can0 {
++ groups = "can0_data_a";
++ function = "can0";
++ };
++
++ can1_pins: can1 {
++ groups = "can1_data";
++ function = "can1";
++ };
++
++ canfd0_pins: canfd0 {
++ groups = "canfd0_data_a";
++ function = "canfd0";
++ };
++
++ canfd1_pins: canfd1 {
++ groups = "canfd1_data";
++ function = "canfd1";
++ };
++
++ sdhi3_pins: sd3 {
++ groups = "sdhi3_data4", "sdhi3_ctrl";
++ function = "sdhi3";
++ power-source = <3300>;
++ };
++
++ sdhi3_pins_uhs: sd3_uhs {
++ groups = "sdhi3_data4", "sdhi3_ctrl";
++ function = "sdhi3";
++ power-source = <1800>;
++ };
++};
++
++&gpio0 {
++ video_a_irq {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-A irq";
++ };
++
++ video_b_irq {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-B irq";
++ };
++
++ video_c_irq {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-C irq";
++ };
++ can2_irq {
++ gpio-hog;
++ gpios = <15 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "CAN2 irq";
++ };
++};
++
++&gpio1 {
++ can3_irq {
++ gpio-hog;
++ gpios = <5 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "CAN3 irq";
++ };
++ gpioext_4_22_irq {
++ gpio-hog;
++ gpios = <25 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "0x22@i2c4 irq";
++ };
++ m2_0_sleep {
++ gpio-hog;
++ gpios = <6 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "M2 0 SLEEP#";
++ };
++ m2_1_sleep {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "M2 1 SLEEP#";
++ };
++ m2_0_pcie_det {
++ gpio-hog;
++ gpios = <18 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 0 PCIe/SATA";
++ };
++ m2_1_pcie_det {
++ gpio-hog;
++ gpios = <19 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 1 PCIe/SATA";
++ };
++ m2_1_rst {
++ gpio-hog;
++ gpios = <11 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "M.2 1 RST#";
++ };
++ switch_ext_phy_reset {
++ gpio-hog;
++ gpios = <16 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR ext phy reset";
++ };
++ switch_sw_reset {
++ gpio-hog;
++ gpios = <17 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR switch reset";
++ };
++ switch_1v2_en {
++ gpio-hog;
++ gpios = <27 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR 1.2V en";
++ };
++};
++
++&gpio2 {
++ m2_0_wake {
++ gpio-hog;
++ gpios = <1 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 0 WAKE#";
++ };
++ m2_0_clkreq {
++ gpio-hog;
++ gpios = <5 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 0 CLKREQ#";
++ };
++ switch_3v3_en {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR 3.3V en";
++ };
++};
++
++&gpio3 {
++ switch_int_phy_reset {
++ gpio-hog;
++ gpios = <15 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR int phy reset";
++ };
++};
++
++&gpio5 {
++ switch_2v5_en {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR 2.5V en";
++ };
++ switch_25mhz_en {
++ gpio-hog;
++ gpios = <8 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "BR 25MHz clk en";
++ };
++};
++
++&gpio6 {
++ m2_1_wake {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 1 WAKE#";
++ };
++ m2_1_clkreq {
++ gpio-hog;
++ gpios = <10 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "M.2 1 CLKREQ#";
++ };
++
++ m2_0_rst {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "M.2 0 RST#";
++ };
++};
++
++&i2c2 {
++ clock-frequency = <400000>;
++
++ i2cswitch2: pca9548@74 {
++ compatible = "nxp,pca9548";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x74>;
++ reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>;
++
++ i2c@4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ /* USB3.0 HUB node(s) */
++ tusb8041_44@44 {
++ compatible = "ti,tusb8041";
++ reg = <0x44>;
++ reset-gpios = <&gpio5 5 0>;
++ ti,registers = /bits/ 8 <
++ 0x05 0x10
++ 0x06 0x0f
++ 0x07 0x8f
++ 0x08 0x0f
++ 0x0a 0x20
++ 0x0b 0x80>;
++ };
++ tusb8041_45@45 {
++ compatible = "ti,tusb8041";
++ reg = <0x45>;
++ reset-gpios = <&gpio5 5 0>;
++ ti,registers = /bits/ 8 <
++ 0x05 0x10
++ 0x06 0x0f
++ 0x07 0x8f
++ 0x08 0x0f
++ 0x0a 0x20
++ 0x0b 0x80>;
++ };
++ };
++
++ /* Slot A (CN10) */
++ i2c@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++
++ max96712@29 {
++ compatible = "maxim,max96712";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x29>;
++ clocks = <&cs2300_a>;
++ clock-names = "ref_clk";
++ shutdown-gpios = <&gpio_exp_a_5c 13 GPIO_ACTIVE_LOW>;
++
++ maxim,link-mipi-map = <1 1 1 1>;
++
++ poc0-supply = <&vdd_cam_a_0>;
++ poc1-supply = <&vdd_cam_a_1>;
++ poc2-supply = <&vdd_cam_a_2>;
++ poc3-supply = <&vdd_cam_a_3>;
++
++ port@0 {
++ reg = <4>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ max96712_des0ep0: endpoint@0 {
++ ser-addr = <0x0c>;
++ remote-endpoint = <&camera_in0>;
++ };
++ max96712_des0ep1: endpoint@1 {
++ ser-addr = <0x0d>;
++ remote-endpoint = <&camera_in1>;
++ };
++ max96712_des0ep2: endpoint@2 {
++ ser-addr = <0x0e>;
++ remote-endpoint = <&camera_in2>;
++ };
++ max96712_des0ep3: endpoint@3 {
++ ser-addr = <0x0f>;
++ remote-endpoint = <&camera_in3>;
++ };
++ };
++
++ port@1 {
++ max96712_des0csi0ep0: endpoint {
++ csi-rate = <1200>;
++ remote-endpoint = <&csi40_ep>;
++ };
++ };
++
++
++ i2c_des@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++
++ camera@0 {
++ compatible = COMPATIBLE_CAMERAS;
++ reg = <0x60 0x0c>;
++
++ port@0 {
++ camera_in0: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin0ep0>;
++ };
++ };
++ port@1 {
++ camera_max96712_des0ep0: endpoint {
++ remote-endpoint = <&max96712_des0ep0>;
++ };
++ };
++ };
++ };
++
++ i2c_des@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++
++ camera@1 {
++ compatible = COMPATIBLE_CAMERAS;
++ reg = <0x61 0x0d>;
++
++ port@0 {
++ camera_in1: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin1ep0>;
++ };
++ };
++ port@1 {
++ camera_max96712_des0ep1: endpoint {
++ remote-endpoint = <&max96712_des0ep1>;
++ };
++ };
++ };
++ };
++
++ i2c_des@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++
++ camera@2 {
++ compatible = COMPATIBLE_CAMERAS;
++ reg = <0x62 0x0e>;
++
++ port@0 {
++ camera_in2: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin2ep0>;
++ };
++ };
++ port@1 {
++ camera_max96712_des0ep2: endpoint {
++ remote-endpoint = <&max96712_des0ep2>;
++ };
++ };
++ };
++ };
++
++ i2c_des@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++
++ camera@3 {
++ compatible = COMPATIBLE_CAMERAS;
++ reg = <0x63 0x0f>;
++
++ port@0 {
++ camera_in3: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin3ep0>;
++ };
++ };
++ port@1 {
++ camera_max96712_des0ep3: endpoint {
++ remote-endpoint = <&max96712_des0ep3>;
++ };
++ };
++ };
++ };
++ };
++ };
++
++ /* Slot B (CN11) */
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++
++ max96712@29 {
++ compatible = "maxim,max96712_XX";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x29>;
++ clocks = <&cs2300_b>;
++ clock-names = "ref_clk";
++ shutdown-gpios = <&gpio_exp_b_5c 13 GPIO_ACTIVE_LOW>;
++
++ maxim,link-mipi-map = <1 1 1 1>;
++
++ poc0-supply = <&vdd_cam_b_0>;
++ poc1-supply = <&vdd_cam_b_1>;
++ poc2-supply = <&vdd_cam_b_2>;
++ poc3-supply = <&vdd_cam_b_3>;
++
++ port@0 {
++ reg = <4>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ max96712_des1ep0: endpoint@0 {
++ ser-addr = <0x1c>;
++ remote-endpoint = <&camera_in4>;
++ };
++ max96712_des1ep1: endpoint@1 {
++ ser-addr = <0x1d>;
++ remote-endpoint = <&camera_in5>;
++ };
++ max96712_des1ep2: endpoint@2 {
++ ser-addr = <0x1e>;
++ remote-endpoint = <&camera_in6>;
++ };
++ max96712_des1ep3: endpoint@3 {
++ ser-addr = <0x1f>;
++ remote-endpoint = <&camera_in7>;
++ };
++ };
++
++ port@1 {
++ reg = <5>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ max96712_des1csi0ep0: endpoint {
++ csi-rate = <1200>;
++ remote-endpoint = <&csi41_ep>;
++ };
++ };
++
++ i2c_des@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++
++ camera@0 {
++ compatible = COMPATIBLE_CAMERAS;
++ reg = <0x64 0x1c>;
++
++ port@0 {
++ camera_in4: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin4ep0>;
++ };
++ };
++ port@1 {
++ camera_max96712_des1ep0: endpoint {
++ remote-endpoint = <&max96712_des1ep0>;
++ };
++ };
++ };
++ };
++
++ i2c_des@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++
++ camera@1 {
++ compatible = COMPATIBLE_CAMERAS;
++ reg = <0x65 0x1d>;
++
++ port@0 {
++ camera_in5: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin5ep0>;
++ };
++ };
++ port@1 {
++ camera_max96712_des1ep1: endpoint {
++ remote-endpoint = <&max96712_des1ep1>;
++ };
++ };
++ };
++ };
++
++ i2c_des@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++
++ camera@2 {
++ compatible = COMPATIBLE_CAMERAS;
++ reg = <0x66 0x1e>;
++
++ port@0 {
++ camera_in6: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin6ep0>;
++ };
++ };
++ port@1 {
++ camera_max96712_des1ep2: endpoint {
++ remote-endpoint = <&max96712_des1ep2>;
++ };
++ };
++ };
++ };
++
++ i2c_des@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++
++ camera@3 {
++ compatible = COMPATIBLE_CAMERAS;
++ reg = <0x67 0x1f>;
++
++ port@0 {
++ camera_in7: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&vin7ep0>;
++ };
++ };
++ port@1 {
++ camera_max96712_des1ep3: endpoint {
++ remote-endpoint = <&max96712_des1ep3>;
++ };
++ };
++ };
++ };
++ };
++ };
++
++ /* Slot A (CN10) */
++ i2c@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++
++ /* PCA9535 is a redundant/deprecated card */
++ gpio_exp_a_26: gpio@26 {
++ compatible = "nxp,pca9535";
++ reg = <0x26>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ video_a_pwr_shdn {
++ gpio-hog;
++ gpios = <3 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR_SHDN";
++ };
++ video_a_cam_pwr0 {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR0";
++ };
++ video_a_cam_pwr1 {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR1";
++ };
++ video_a_cam_pwr2 {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR2";
++ };
++ video_a_cam_pwr3 {
++ gpio-hog;
++ gpios = <15 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR3";
++ };
++ video_a_des_shdn {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A DES_SHDN";
++ };
++ video_a_des_led {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "Video-A led";
++ };
++ };
++
++ gpio_exp_a_5c: gpio@5c {
++ compatible = "maxim,max7325";
++ reg = <0x5c>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ video_a_des_cfg0 {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-A cfg0";
++ };
++ video_a_pwr_shdn {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A PWR_SHDN";
++ };
++/*
++ video_a_des_shdn {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-A DES_SHDN";
++ };
++*/
++ video_a_led {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "Video-A LED";
++ };
++ };
++
++ cs2300_a: clk_multiplier_a@4e {
++ #clock-cells = <0>;
++ compatible = "cirrus,cs2300-cp";
++ reg = <0x4e>;
++ clocks = <&cs2300_ref_clk>;
++ clock-names = "clk_in";
++
++ assigned-clocks = <&cs2300_a>;
++ assigned-clock-rates = <25000000>;
++ };
++
++ dac_vcam_a: dac_vcam_a@60 {
++ compatible = "microchip,mcp4725";
++ reg = <0x60>;
++ };
++
++ max2008x_a: vcam_switch_a@28 {
++ compatible = "maxim,max2008x";
++ reg = <0x28>;
++ #io-channel-cells = <1>;
++
++ regulators {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ vdd_cam_a_0: SW0 {
++ reg = <0>;
++ regulator-name = "Camera-A-0";
++ };
++ vdd_cam_a_3: SW1 {
++ reg = <1>;
++ regulator-name = "Camera-A-3";
++ };
++ vdd_cam_a_1: SW2 {
++ reg = <2>;
++ regulator-name = "Camera-A-1";
++ };
++ vdd_cam_a_2: SW3 {
++ reg = <3>;
++ regulator-name = "Camera-A-2";
++ };
++ };
++ };
++ };
++
++ i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ /* Slot B (CN11) */
++
++ /* PCA9535 is a redundant/deprecated card */
++ gpio_exp_b_26: gpio@26 {
++ compatible = "nxp,pca9535";
++ reg = <0x26>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ video_b_des_cfg1 {
++ gpio-hog;
++ gpios = <5 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-B cfg1";
++ };
++ video_b_des_cfg0 {
++ gpio-hog;
++ gpios = <6 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-B cfg0";
++ };
++ video_b_pwr_shdn {
++ gpio-hog;
++ gpios = <3 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR_SHDN";
++ };
++ video_b_cam_pwr0 {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR0";
++ };
++ video_b_cam_pwr1 {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR1";
++ };
++ video_b_cam_pwr2 {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR2";
++ };
++ video_b_cam_pwr3 {
++ gpio-hog;
++ gpios = <15 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR3";
++ };
++ video_b_des_shdn {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B DES_SHDN";
++ };
++ video_b_des_led {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "Video-B led";
++ };
++ };
++
++ gpio_exp_b_5c: gpio@5c {
++ compatible = "maxim,max7325";
++ reg = <0x5c>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ video_b_des_cfg0 {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-B cfg0";
++ };
++ video_b_pwr_shdn {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B PWR_SHDN";
++ };
++/*
++ video_b_des_shdn {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-B DES_SHDN";
++ };
++*/
++ video_b_led {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "Video-B LED";
++ };
++ };
++
++ cs2300_b: clk_multiplier_b@4e {
++ #clock-cells = <0>;
++ compatible = "cirrus,cs2300-cp";
++ reg = <0x4e>;
++ clocks = <&cs2300_ref_clk>;
++ clock-names = "clk_in";
++
++ assigned-clocks = <&cs2300_b>;
++ assigned-clock-rates = <25000000>;
++ };
++
++ dac_vcam_b: dac_vcam_b@60 {
++ compatible = "microchip,mcp4725";
++ reg = <0x60>;
++ };
++
++ max2008x_b: vcam_switch_b@28 {
++ compatible = "maxim,max2008x";
++ reg = <0x28>;
++ #io-channel-cells = <1>;
++
++ regulators {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ vdd_cam_b_0: SW0 {
++ reg = <0>;
++ regulator-name = "Camera-B-0";
++ };
++ vdd_cam_b_3: SW1 {
++ reg = <1>;
++ regulator-name = "Camera-B-3";
++ };
++ vdd_cam_b_1: SW2 {
++ reg = <2>;
++ regulator-name = "Camera-B-1";
++ };
++ vdd_cam_b_2: SW3 {
++ reg = <3>;
++ regulator-name = "Camera-B-2";
++ };
++ };
++ };
++ };
++
++ i2c@5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ /* Slot C (CN12) */
++
++ gpio_exp_c_5c: gpio@5c {
++ compatible = "maxim,max7325";
++ reg = <0x5c>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ video_c_des_cfg0 {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "Video-C cfg0";
++ };
++ video_c_pwr_shdn {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-C PWR_SHDN";
++ };
++/*
++ video_c_des_shdn {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "Video-C DES_SHDN";
++ };
++*/
++ video_c_led {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "Video-C LED";
++ };
++ };
++
++ cs2300_c: clk_multiplier_c@4e {
++ #clock-cells = <0>;
++ compatible = "cirrus,cs2300-cp";
++ reg = <0x4e>;
++ clocks = <&cs2300_ref_clk>;
++ clock-names = "clk_in";
++
++ assigned-clocks = <&cs2300_c>;
++ assigned-clock-rates = <25000000>;
++ };
++
++ dac_vcam_c: dac_vcam_c@60 {
++ compatible = "microchip,mcp4725";
++ reg = <0x60>;
++ };
++
++ max2008x_c: vcam_switch_c@28 {
++ compatible = "maxim,max2008x";
++ reg = <0x28>;
++ #io-channel-cells = <1>;
++
++ regulators {
++ vdd_cam_c_0: SW0 {
++ regulator-name = "Camera-C-0";
++ };
++ vdd_cam_c_1: SW2 {
++ regulator-name = "Camera-C-1";
++ };
++ };
++ };
++ };
++ };
++};
++
++&i2c4 {
++ i2cswitch4: pca9548@74 {
++ compatible = "nxp,pca9548";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x74>;
++ reset-gpios= <&gpio5 15 GPIO_ACTIVE_LOW>;
++
++ i2c@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ /* FAN1 node - lm96063 */
++ fan_ctrl_1:lm96063-1@4c {
++ compatible = "lm96163";
++ reg = <0x4c>;
++ };
++ };
++
++ i2c@6 {
++ /* FAN2 */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <6>;
++ /* FAN2 node - lm96063 */
++ fan_ctrl_2:lm96063-2@4c {
++ compatible = "lm96163";
++ reg = <0x4c>;
++ };
++ };
++
++ i2c@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++
++ /* Power nodes - 2 x TPS544x20 */
++ tps_5v: tps544c20@0x2a {
++ compatible = "tps544c20";
++ reg = <0x2c>;
++ status = "disabled";
++ };
++ tps_3v3: tps544c20@0x22 {
++ compatible = "tps544c20";
++ reg = <0x24>;
++ status = "disabled";
++ };
++ };
++
++ i2c_power: i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ /* CAN and power board nodes */
++
++ gpio_ext_pwr: pca9535@22 {
++ compatible = "nxp,pca9535";
++ reg = <0x22>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ interrupt-parent = <&gpio1>;
++ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
++
++ /* enable input DCDC after wake-up signal released */
++ pwr_hold {
++ gpio-hog;
++ gpios = <11 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "pwr_hold";
++ };
++ pwr_5v_out {
++ gpio-hog;
++ gpios = <14 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "pwr_5v_out";
++ };
++ pwr_5v_oc {
++ gpio-hog;
++ gpios = <15 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "pwr_5v_oc";
++ };
++ pwr_wake8 {
++ gpio-hog;
++ gpios = <12 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "wake8";
++ };
++ pwr_wake7 {
++ gpio-hog;
++ gpios = <13 GPIO_ACTIVE_HIGH>;
++ input;
++ line-name = "wake7";
++ };
++
++ /* CAN0 */
++ can0_stby {
++ gpio-hog;
++ gpios = <4 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can0_stby";
++ };
++ can0_load {
++ gpio-hog;
++ gpios = <0 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "can0_120R_load";
++ };
++ /* CAN1 */
++ can1_stby {
++ gpio-hog;
++ gpios = <5 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can1_stby";
++ };
++ can1_load {
++ gpio-hog;
++ gpios = <1 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "can1_120R_load";
++ };
++ /* CAN2 */
++ can2_stby {
++ gpio-hog;
++ gpios = <6 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can2_stby";
++ };
++ can2_load {
++ gpio-hog;
++ gpios = <2 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "can2_120R_load";
++ };
++ /* CAN3 */
++ can3_stby {
++ gpio-hog;
++ gpios = <7 GPIO_ACTIVE_HIGH>;
++ output-low;
++ line-name = "can3_stby";
++ };
++ can3_load {
++ gpio-hog;
++ gpios = <3 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "can3_120R_load";
++ };
++ };
++ };
++
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ /* FPDLink output node - DS90UH947 */
++ };
++
++ i2c@4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ /* BCM switch node */
++ };
++
++ i2c@5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ /* LED board node(s) */
++
++ gpio_ext_led: pca9535@22 {
++ compatible = "nxp,pca9535";
++ reg = <0x22>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ /* gpios 0..7 are used for indication LEDs, low-active */
++ };
++ rtc: mcp79411@6f {
++ compatible = "microchip,mcp7941x";
++ reg = <0x6f>;
++ };
++ };
++
++ /* port 7 is not used */
++ };
++};
++
++&pcie_bus_clk {
++ clock-frequency = <100000000>;
++ status = "okay";
++};
++
++&pciec0 {
++ status = "okay";
++};
++
++&pciec1 {
++ status = "okay";
++};
++
++&vin0 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin0ep0: endpoint {
++ csi,select = "csi40";
++ virtual,channel = <0>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&camera_in0>;
++ };
++ };
++ port@1 {
++ csi40ep0: endpoint {
++ remote-endpoint = <&csi40_ep>;
++ };
++ };
++ port@2 {
++ vin0_mmax96712_des0ep0: endpoint {
++ remote-endpoint = <&max96712_des0ep0>;
++ };
++ };
++ };
++};
++
++&vin1 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin1ep0: endpoint {
++ csi,select = "csi40";
++ virtual,channel = <1>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&camera_in1>;
++ };
++ };
++ port@1 {
++ csi40ep1: endpoint {
++ remote-endpoint = <&csi40_ep>;
++ };
++ };
++ port@2 {
++ vin1_max96712_des0ep1: endpoint {
++ remote-endpoint = <&max96712_des0ep1>;
++ };
++ };
++ };
++};
++
++&vin2 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin2ep0: endpoint {
++ csi,select = "csi40";
++ virtual,channel = <2>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&camera_in2>;
++ };
++ };
++ port@1 {
++ csi40ep2: endpoint {
++ remote-endpoint = <&csi40_ep>;
++ };
++ };
++ port@2 {
++ vin2_max96712_des0ep2: endpoint {
++ remote-endpoint = <&max96712_des0ep2>;
++ };
++ };
++ };
++};
++
++&vin3 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin3ep0: endpoint {
++ csi,select = "csi40";
++ virtual,channel = <3>;
++ data-lanes = <1 2 3 4>;
++ remote-endpoint = <&camera_in3>;
++ };
++ };
++ port@1 {
++ csi40ep3: endpoint {
++ remote-endpoint = <&csi40_ep>;
++ };
++ };
++ port@2 {
++ vin3_max96712_des0ep3: endpoint {
++ remote-endpoint = <&max96712_des0ep3>;
++ };
++ };
++ };
++};
++
++&vin4 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin4ep0: endpoint {
++ csi,select = "csi41";
++ virtual,channel = <0>;
++ remote-endpoint = <&camera_in4>;
++ data-lanes = <1 2 3 4>;
++ };
++ };
++ port@1 {
++ csi41ep0: endpoint {
++ remote-endpoint = <&csi41_ep>;
++ };
++ };
++ port@2 {
++ vin4_max96712_des0ep1: endpoint {
++ remote-endpoint = <&max96712_des1ep0>;
++ };
++ };
++ };
++};
++
++&vin5 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin5ep0: endpoint@0 {
++ csi,select = "csi41";
++ virtual,channel = <1>;
++ remote-endpoint = <&camera_in5>;
++ data-lanes = <1 2 3 4>;
++ };
++ };
++ port@1 {
++ csi41ep1: endpoint {
++ remote-endpoint = <&csi41_ep>;
++ };
++ };
++ port@2 {
++ vin5_max96712_des0ep1: endpoint {
++ remote-endpoint = <&max96712_des1ep1>;
++ };
++ };
++ };
++};
++
++&vin6 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin6ep0: endpoint@0 {
++ csi,select = "csi41";
++ virtual,channel = <2>;
++ remote-endpoint = <&camera_in6>;
++ data-lanes = <1 2 3 4>;
++ };
++ };
++ port@1 {
++ csi41ep2: endpoint {
++ remote-endpoint = <&csi41_ep>;
++ };
++ };
++ port@2 {
++ vin6_max96712_des2ep2: endpoint {
++ remote-endpoint = <&max96712_des1ep2>;
++ };
++ };
++ };
++};
++
++&vin7 {
++ status = "okay";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ vin7ep0: endpoint@0 {
++ csi,select = "csi41";
++ virtual,channel = <3>;
++ remote-endpoint = <&camera_in7>;
++ data-lanes = <1 2 3 4>;
++ };
++ };
++ port@1 {
++ csi41ep3: endpoint {
++ remote-endpoint = <&csi41_ep>;
++ };
++ };
++ port@2 {
++ vin7_max96712_des2ep3: endpoint {
++ remote-endpoint = <&max96712_des1ep3>;
++ };
++ };
++ };
++};
++
++&csi40 {
++ status = "okay";
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ csi40_ep: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ csi-rate = <300>;
++ };
++ };
++};
++
++&csi41 {
++ status = "okay";
++
++ port {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ csi41_ep: endpoint {
++ clock-lanes = <0>;
++ data-lanes = <1 2 3 4>;
++ csi-rate = <300>;
++ };
++ };
++};
++
++&ssi1 {
++ /delete-property/shared-pin;
++};
++
++&sdhi3 {
++ pinctrl-0 = <&sdhi3_pins>;
++ pinctrl-1 = <&sdhi3_pins_uhs>;
++ pinctrl-names = "default", "state_uhs";
++
++ vmmc-supply = <&vcc_sdhi3>;
++ vqmmc-supply = <&vccq_sdhi3>;
++ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
++ wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
++ bus-width = <4>;
++ sd-uhs-sdr50;
++ status = "okay";
++};
++
++&msiof1 {
++ status = "disabled";
++};
++
++&usb2_phy0 {
++ pinctrl-0 = <&usb0_pins>;
++ pinctrl-names = "default";
++
++ status = "okay";
++};
++
++&usb2_phy2 {
++ pinctrl-0 = <&usb2_pins>;
++ pinctrl-names = "default";
++
++ status = "okay";
++};
++
++&xhci0 {
++ pinctrl-0 = <&usb30_pins>;
++ pinctrl-names = "default";
++
++ status = "okay";
++};
++
++&ehci0 {
++ status = "okay";
++};
++
++&ehci2 {
++ status = "okay";
++};
++
++&ohci0 {
++ status = "okay";
++};
++
++&ohci2 {
++ status = "okay";
++};
++
++&can0 {
++ pinctrl-0 = <&can0_pins>;
++ pinctrl-names = "default";
++ status = "disabled";
++};
++
++&can1 {
++ pinctrl-0 = <&can1_pins>;
++ pinctrl-names = "default";
++ status = "disabled";
++};
++
++&canfd {
++ pinctrl-0 = <&canfd0_pins &canfd1_pins>;
++ pinctrl-names = "default";
++ status = "okay";
++
++ channel0 {
++ status = "okay";
++ };
++
++ channel1 {
++ status = "okay";
++ };
++};
++
++/* uncomment to enable CN12 on VIN4-7 */
++//#include "ulcb-vb2-cn12.dtsi"
+diff --git a/arch/arm64/boot/dts/renesas/ulcb-vb2.1-gmsl2.dtsi b/arch/arm64/boot/dts/renesas/ulcb-vb2.1-gmsl2.dtsi
+new file mode 100644
+index 0000000..7334a5e
+--- /dev/null
++++ b/arch/arm64/boot/dts/renesas/ulcb-vb2.1-gmsl2.dtsi
+@@ -0,0 +1,90 @@
++/*
++ * Device Tree Source for the ULCB Videobox V2.1 board
++ *
++ * Copyright (C) 2019 Cogent Embedded, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "ulcb-vb2-gmsl2.dtsi"
++
++/{
++ leds {
++ led_button {
++ gpios = <&gpio_ext_led 9 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "cpu";
++ };
++ };
++
++ gpio_keys_polled {
++ compatible = "gpio-keys-polled";
++ poll-interval = <100>;
++ autorepeat;
++
++ button_pwr {
++ label = "GPIO Key POWER";
++ linux,code = <116>;
++ gpios = <&gpio_ext_led 8 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&i2c_power {
++ adc@48 {
++ reg = <0x48>;
++ compatible = "ti,ads1115";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ wake7_voltage: channel@4 {
++ /* single endded AIN0 */
++ reg = <4>;
++ };
++ wake8_voltage: channel@5 {
++ /* single endded AIN1 */
++ reg = <5>;
++ };
++ dc_prot_voltage: channel@6 {
++ /* single endded AIN2 */
++ reg = <6>;
++ };
++ dcdc_voltage: channel@7 {
++ /* single endded AIN3 */
++ reg = <7>;
++ };
++ };
++};
++
++&gpio6 {
++ /delete-node/m2_0_rst;
++
++ m2_0_rst {
++ gpio-hog;
++ gpios = <6 GPIO_ACTIVE_HIGH>;
++ output-high;
++ line-name = "M.2 0 RST#";
++ };
++};
++
++&pfc {
++ usb1_pins: usb1 {
++ groups = "usb1";
++ function = "usb1";
++ };
++};
++
++&usb2_phy1 {
++ pinctrl-0 = <&usb1_pins>;
++ pinctrl-names = "default";
++
++ status = "okay";
++};
++
++&ehci1 {
++ status = "okay";
++};
++
++&ohci1 {
++ status = "okay";
++};
+--
+2.7.4
+