diff options
Diffstat (limited to 'external/poky/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch')
-rw-r--r-- | external/poky/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch | 143 |
1 files changed, 78 insertions, 65 deletions
diff --git a/external/poky/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch b/external/poky/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch index 4d64bd53..c32867a2 100644 --- a/external/poky/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch +++ b/external/poky/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch @@ -1,7 +1,7 @@ -From 96ff7570c29f792c466a933529fefda9b8e97994 Mon Sep 17 00:00:00 2001 +From a0237ec2d1e58bd35c236df39dd5a06504c6d2ed Mon Sep 17 00:00:00 2001 From: Khem Raj <raj.khem@gmail.com> Date: Sun, 14 Feb 2016 17:06:19 +0000 -Subject: [PATCH 12/15] Add support for Netlogic XLP +Subject: [PATCH] Add support for Netlogic XLP Patch From: Nebu Philips <nphilips@netlogicmicro.com> @@ -26,18 +26,19 @@ Signed-off-by: Mark Hatle <mark.hatle@windriver.com> binutils/readelf.c | 1 + gas/config/tc-mips.c | 4 +++- gas/configure | 3 +++ + gas/configure.ac | 3 +++ include/elf/mips.h | 1 + include/opcode/mips.h | 6 ++++++ - ld/configure.tgt | 2 ++ + ld/configure.tgt | 3 +++ opcodes/mips-dis.c | 12 +++++------- opcodes/mips-opc.c | 31 ++++++++++++++++++++----------- - 14 files changed, 61 insertions(+), 21 deletions(-) + 15 files changed, 65 insertions(+), 21 deletions(-) diff --git a/bfd/aoutx.h b/bfd/aoutx.h -index 023843b0be..46246fec2d 100644 +index fa3a9746b6..5078024fd5 100644 --- a/bfd/aoutx.h +++ b/bfd/aoutx.h -@@ -798,6 +798,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch, +@@ -799,6 +799,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch, case bfd_mach_mipsisa64r6: case bfd_mach_mips_sb1: case bfd_mach_mips_xlr: @@ -46,10 +47,10 @@ index 023843b0be..46246fec2d 100644 arch_flags = M_MIPS2; break; diff --git a/bfd/archures.c b/bfd/archures.c -index 282e983086..b38b05d132 100644 +index 232103817c..b2b3b8c124 100644 --- a/bfd/archures.c +++ b/bfd/archures.c -@@ -183,6 +183,7 @@ DESCRIPTION +@@ -185,6 +185,7 @@ DESCRIPTION .#define bfd_mach_mips_octeon3 6503 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR'. *} .#define bfd_mach_mips_interaptiv_mr2 736550 {* decimal 'IA2'. *} @@ -58,10 +59,10 @@ index 282e983086..b38b05d132 100644 .#define bfd_mach_mipsisa32r2 33 .#define bfd_mach_mipsisa32r3 34 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h -index 93745bd3fd..326e9e49ed 100644 +index 7c13bc8c91..2e453c50c1 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h -@@ -2054,6 +2054,7 @@ enum bfd_architecture +@@ -1568,6 +1568,7 @@ enum bfd_architecture #define bfd_mach_mips_octeon3 6503 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR'. */ #define bfd_mach_mips_interaptiv_mr2 736550 /* decimal 'IA2'. */ @@ -70,10 +71,10 @@ index 93745bd3fd..326e9e49ed 100644 #define bfd_mach_mipsisa32r2 33 #define bfd_mach_mipsisa32r3 34 diff --git a/bfd/config.bfd b/bfd/config.bfd -index 8a11c0680a..c882421343 100644 +index 847f9f0ba9..a12707f827 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd -@@ -896,6 +896,11 @@ case "${targ}" in +@@ -894,6 +894,11 @@ case "${targ}" in targ_defvec=mips_elf32_le_vec targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec" ;; @@ -86,10 +87,10 @@ index 8a11c0680a..c882421343 100644 targ_defvec=mips_elf32_be_vec targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec" diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c -index cb50c64371..2b9d1d6ecf 100644 +index 802acb45f1..fd9ec4c0ad 100644 --- a/bfd/cpu-mips.c +++ b/bfd/cpu-mips.c -@@ -105,7 +105,8 @@ enum +@@ -108,7 +108,8 @@ enum I_mipsocteon3, I_xlr, I_interaptiv_mr2, @@ -99,21 +100,21 @@ index cb50c64371..2b9d1d6ecf 100644 }; #define NN(index) (&arch_info_struct[(index) + 1]) -@@ -158,7 +159,8 @@ static const bfd_arch_info_type arch_info_struct[] = - N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)), +@@ -163,7 +164,8 @@ static const bfd_arch_info_type arch_info_struct[] = + N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)), N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", FALSE, NN(I_interaptiv_mr2)), -- N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0) -+ N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)), -+ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0) +- N (64, 64, bfd_mach_mips_micromips, "mips:micromips", FALSE, NULL) ++ N (64, 64, bfd_mach_mips_micromips, "mips:micromips", FALSE, NN(I_micromips)), ++ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, NULL) }; /* The default architecture is mips:3000, but with a machine number of diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c -index d91942301c..5d1bd3f0b1 100644 +index d7e3aed3b6..7baeee9ee3 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c -@@ -6805,6 +6805,9 @@ _bfd_elf_mips_mach (flagword flags) +@@ -6999,6 +6999,9 @@ _bfd_elf_mips_mach (flagword flags) case E_MIPS_MACH_IAMR2: return bfd_mach_mips_interaptiv_mr2; @@ -123,7 +124,7 @@ index d91942301c..5d1bd3f0b1 100644 default: switch (flags & EF_MIPS_ARCH) { -@@ -12003,6 +12006,10 @@ mips_set_isa_flags (bfd *abfd) +@@ -12355,6 +12358,10 @@ mips_set_isa_flags (bfd *abfd) val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; break; @@ -134,19 +135,19 @@ index d91942301c..5d1bd3f0b1 100644 case bfd_mach_mipsisa32: val = E_MIPS_ARCH_32; break; -@@ -13992,6 +13999,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = - { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, - { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, - { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 }, +@@ -14379,6 +14386,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = + { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e }, + { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 }, + { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 }, + { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 }, /* MIPS64 extensions. */ { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, diff --git a/binutils/readelf.c b/binutils/readelf.c -index 2b78db219b..7a7178925f 100644 +index 6b5bebe743..d15a7828db 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c -@@ -3403,6 +3403,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) +@@ -3440,6 +3440,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break; @@ -155,10 +156,10 @@ index 2b78db219b..7a7178925f 100644 /* We simply ignore the field in this case to avoid confusion: MIPS ELF does not specify EF_MIPS_MACH, it is a GNU diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c -index 59df787155..48537226c0 100644 +index fc6898834e..2c7151ccdb 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c -@@ -552,6 +552,7 @@ static int mips_32bitmode = 0; +@@ -568,6 +568,7 @@ static int mips_32bitmode = 0; || mips_opts.arch == CPU_RM7000 \ || mips_opts.arch == CPU_VR5500 \ || mips_opts.micromips \ @@ -166,7 +167,7 @@ index 59df787155..48537226c0 100644 ) /* Whether the processor uses hardware interlocks to protect reads -@@ -581,6 +582,7 @@ static int mips_32bitmode = 0; +@@ -597,6 +598,7 @@ static int mips_32bitmode = 0; && mips_opts.isa != ISA_MIPS3) \ || mips_opts.arch == CPU_R4300 \ || mips_opts.micromips \ @@ -174,31 +175,45 @@ index 59df787155..48537226c0 100644 ) /* Whether the processor uses hardware interlocks to protect reads -@@ -19778,7 +19780,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = +@@ -20135,7 +20137,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = /* Broadcom XLP. XLP is mostly like XLR, with the prominent exception that it is MIPS64R2 rather than MIPS64. */ - { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, + { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP }, - /* MIPS 64 Release 6 */ - { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, + /* MIPS 64 Release 6. */ + { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, diff --git a/gas/configure b/gas/configure -index 134278fa25..2fdca147a1 100755 +index 60c1a055ae..59d6d11215 100755 --- a/gas/configure +++ b/gas/configure -@@ -13336,6 +13336,9 @@ _ACEOF +@@ -12722,6 +12722,9 @@ _ACEOF mipsisa64r6 | mipsisa64r6el) mips_cpu=mips64r6 ;; + mipsisa64r2nlm | mipsisa64r2nlmel) -+ mips_cpu=xlp -+ ;; ++ mips_cpu=xlp ++ ;; + mipstx39 | mipstx39el) + mips_cpu=r3900 + ;; +diff --git a/gas/configure.ac b/gas/configure.ac +index 6f32e55a1a..11c2e0d273 100644 +--- a/gas/configure.ac ++++ b/gas/configure.ac +@@ -325,6 +325,9 @@ changequote([,])dnl + mipsisa64r6 | mipsisa64r6el) + mips_cpu=mips64r6 + ;; ++ mipsisa64r2nlm | mipsisa64r2nlmel) ++ mips_cpu=xlp ++ ;; mipstx39 | mipstx39el) mips_cpu=r3900 ;; diff --git a/include/elf/mips.h b/include/elf/mips.h -index 4e2cde3279..c329f38929 100644 +index d116b036b6..dceeb3f156 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) @@ -210,10 +225,10 @@ index 4e2cde3279..c329f38929 100644 #define E_MIPS_MACH_OCTEON3 0x008e0000 #define E_MIPS_MACH_5400 0x00910000 diff --git a/include/opcode/mips.h b/include/opcode/mips.h -index 1ab1780567..74f457b579 100644 +index fd031f3758..a96a44df84 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h -@@ -1262,6 +1262,8 @@ static const unsigned int mips_isa_table[] = { +@@ -1260,6 +1260,8 @@ static const unsigned int mips_isa_table[] = { #define INSN_XLR 0x00000020 /* Imagination interAptiv MR2. */ #define INSN_INTERAPTIV_MR2 0x04000000 @@ -222,7 +237,7 @@ index 1ab1780567..74f457b579 100644 /* DSP ASE */ #define ASE_DSP 0x00000001 -@@ -1373,6 +1375,7 @@ static const unsigned int mips_isa_table[] = { +@@ -1384,6 +1386,7 @@ static const unsigned int mips_isa_table[] = { #define CPU_OCTEON3 6503 #define CPU_XLR 887682 /* decimal 'XLR' */ #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */ @@ -230,7 +245,7 @@ index 1ab1780567..74f457b579 100644 /* Return true if the given CPU is included in INSN_* mask MASK. */ -@@ -1453,6 +1456,9 @@ cpu_is_member (int cpu, unsigned int mask) +@@ -1461,6 +1464,9 @@ cpu_is_member (int cpu, unsigned int mask) return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); @@ -241,23 +256,24 @@ index 1ab1780567..74f457b579 100644 return FALSE; } diff --git a/ld/configure.tgt b/ld/configure.tgt -index 7fb2168503..a1db7adfe2 100644 +index f4f0eaf9b2..0da3eca19c 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt -@@ -450,6 +450,8 @@ mips*el-sde-elf* | mips*el-mti-elf* | mips*el-img-elf*) - mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) +@@ -520,6 +520,9 @@ mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) targ_emul=elf32btsmip - targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; + targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" + ;; +mipsisa64*-*-elf*) targ_emul=elf32btsmip -+ targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ;; ++ targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ++ ;; mips64*el-ps2-elf*) targ_emul=elf32lr5900n32 targ_extra_emuls="elf32lr5900" - targ_extra_libpath=$targ_extra_emuls ;; + targ_extra_libpath=$targ_extra_emuls diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c -index bbf21328e8..38e487c16f 100644 +index 755bbe294b..ce22ef683a 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c -@@ -656,13 +656,11 @@ const struct mips_arch_choice mips_arch_choices[] = +@@ -674,13 +674,11 @@ const struct mips_arch_choice mips_arch_choices[] = mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), mips_cp1_names_mips3264, mips_hwr_names_numeric }, @@ -277,10 +293,10 @@ index bbf21328e8..38e487c16f 100644 /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c -index 1cbcbc6abc..e1fbdc89de 100644 +index 5270aeefa8..d17dc78cd7 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c -@@ -329,6 +329,7 @@ decode_mips_operand (const char *p) +@@ -328,6 +328,7 @@ decode_mips_operand (const char *p) #define IOCT3 INSN_OCTEON3 #define XLR INSN_XLR #define IAMR2 INSN_INTERAPTIV_MR2 @@ -288,7 +304,7 @@ index 1cbcbc6abc..e1fbdc89de 100644 #define IVIRT ASE_VIRT #define IVIRT64 ASE_VIRT64 -@@ -974,6 +975,7 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -990,6 +991,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, @@ -296,7 +312,7 @@ index 1cbcbc6abc..e1fbdc89de 100644 /* ctc0 is at the bottom of the table. */ {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, -@@ -1006,12 +1008,13 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1022,12 +1024,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, @@ -311,7 +327,7 @@ index 1cbcbc6abc..e1fbdc89de 100644 /* dctr and dctw are used on the r5000. */ {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, -@@ -1083,6 +1086,7 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1099,6 +1102,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 }, {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, @@ -319,7 +335,7 @@ index 1cbcbc6abc..e1fbdc89de 100644 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE }, -@@ -1098,6 +1102,8 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1114,6 +1118,8 @@ const struct mips_opcode mips_builtin_opcodes[] = /* dmfc3 is at the bottom of the table. */ /* dmtc3 is at the bottom of the table. */ {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, @@ -328,7 +344,7 @@ index 1cbcbc6abc..e1fbdc89de 100644 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 }, -@@ -1251,9 +1257,9 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1267,9 +1273,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, @@ -341,7 +357,7 @@ index 1cbcbc6abc..e1fbdc89de 100644 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, -@@ -1418,7 +1424,7 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1438,7 +1444,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, @@ -350,7 +366,7 @@ index 1cbcbc6abc..e1fbdc89de 100644 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -@@ -1463,10 +1469,13 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1483,10 +1489,13 @@ const struct mips_opcode mips_builtin_opcodes[] = /* move is at the top of the table. */ {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, @@ -366,7 +382,7 @@ index 1cbcbc6abc..e1fbdc89de 100644 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -@@ -1516,7 +1525,7 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1536,7 +1545,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, @@ -375,7 +391,7 @@ index 1cbcbc6abc..e1fbdc89de 100644 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, -@@ -1953,9 +1962,9 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1978,9 +1987,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, @@ -388,6 +404,3 @@ index 1cbcbc6abc..e1fbdc89de 100644 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, --- -2.18.0 - |