diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/MdePkg/Library/BaseCpuLib/Ia32 | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/MdePkg/Library/BaseCpuLib/Ia32')
6 files changed, 170 insertions, 0 deletions
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.c b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.c new file mode 100644 index 000000000..89341c2f0 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.c @@ -0,0 +1,28 @@ +/** @file
+ CpuFlushTlb function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+/**
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+ VOID
+ )
+{
+ _asm {
+ mov eax, cr3
+ mov cr3, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.nasm b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.nasm new file mode 100644 index 000000000..bc3b68e3f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuFlushTlb.Asm
+;
+; Abstract:
+;
+; CpuFlushTlb function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuFlushTlb (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuFlushTlb)
+ASM_PFX(CpuFlushTlb):
+ mov eax, cr3
+ mov cr3, eax ; moving to CR3 flushes TLB
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c new file mode 100644 index 000000000..15d414992 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c @@ -0,0 +1,26 @@ +/** @file
+ CpuFlushTlb function for Ia32/X64 GCC.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseLib.h>
+
+/**
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+ VOID
+ )
+{
+ AsmWriteCr3 (AsmReadCr3 ());
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.c b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.c new file mode 100644 index 000000000..0fcaf224e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.c @@ -0,0 +1,28 @@ +/** @file
+ CpuSleep function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ )
+{
+ _asm {
+ hlt
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.nasm b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.nasm new file mode 100644 index 000000000..5e7f9abe6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.nasm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuSleep.Asm
+;
+; Abstract:
+;
+; CpuSleep function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuSleep (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuSleep)
+ASM_PFX(CpuSleep):
+ hlt
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c new file mode 100644 index 000000000..ad5b150d6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c @@ -0,0 +1,27 @@ +/** @file
+ CpuSleep function for Ia32/X64 GCC.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("hlt"::: "memory");
+}
+
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