diff options
author | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
---|---|---|
committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/arm/dts/socfpga_arria5.dtsi | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/arm/dts/socfpga_arria5.dtsi')
-rw-r--r-- | roms/u-boot/arch/arm/dts/socfpga_arria5.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/dts/socfpga_arria5.dtsi b/roms/u-boot/arch/arm/dts/socfpga_arria5.dtsi new file mode 100644 index 000000000..22dbf07af --- /dev/null +++ b/roms/u-boot/arch/arm/dts/socfpga_arria5.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + */ + +/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + mmc0: dwmmc0@ff704000 { + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; + +&watchdog0 { + status = "okay"; +}; |