Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

10 files changed, 1279 insertions, 0 deletions

diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/boot0.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/boot0.h
new file mode 100644
index 000000000..368becc87
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/boot0.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+
+#ifndef _ASM_ARCH_BOOT0_H
+#define _ASM_ARCH_BOOT0_H
+
+_start:
+	ARM_VECTORS
+
+	.word	0x0	/* key location */
+	.word	0x0	/* start address of image */
+	.word	0xfc00  /* maximum image size: 63KB */
+	.word	0x0	/* signature address */
+	.word	0x0	/* header revision ID low */
+	.word	0x0	/* header revision ID high */
+	.word	0x0	/* reserved */
+	.word	0x0	/* checksum */
+	.word	0x0	/* BL2 secure header */
+	.word	0x0	/* public key or digest offset for BL2 */
+
+#endif
diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/pinctrl.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/pinctrl.h
new file mode 100644
index 000000000..dd85464dd
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/pinctrl.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Google, Inc
+ */
+#ifndef _ASM_ARCH_PERIPH_H
+#define _ASM_ARCH_PERIPH_H
+
+/*
+ * Peripherals supported by the hardware.
+ * These are used to specify pinctrl settings.
+ */
+
+enum periph_id {
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+	PERIPH_ID_UART3,
+	PERIPH_ID_UART4,
+	PERIPH_ID_LPC,
+	PERIPH_ID_PWM0,
+	PERIPH_ID_PWM1,
+	PERIPH_ID_PWM2,
+	PERIPH_ID_PWM3,
+	PERIPH_ID_PWM4,
+	PERIPH_ID_PWM5,
+	PERIPH_ID_PWM6,
+	PERIPH_ID_PWM7,
+	PERIPH_ID_PWM8,
+	PERIPH_ID_MAC1,
+	PERIPH_ID_MAC2,
+	PERIPH_ID_VIDEO,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SPI2,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_I2C4,
+	PERIPH_ID_I2C5,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_I2C7,
+	PERIPH_ID_I2C8,
+	PERIPH_ID_I2C9,
+	PERIPH_ID_I2C10,
+	PERIPH_ID_I2C11,
+	PERIPH_ID_I2C12,
+	PERIPH_ID_I2C13,
+	PERIPH_ID_I2C14,
+	PERIPH_ID_SD1,
+	PERIPH_ID_SD2,
+};
+
+#endif  /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/platform.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/platform.h
new file mode 100644
index 000000000..d50ec5f8a
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/platform.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ * Ryan Chen <ryan_chen@aspeedtech.com>
+ *
+ */
+
+#ifndef _ASM_ARCH_PLATFORM_H
+#define _ASM_ARCH_PLATFORM_H
+
+#if defined(CONFIG_ASPEED_AST2500)
+#define ASPEED_MAC_COUNT	2
+#define ASPEED_DRAM_BASE	0x80000000
+#define ASPEED_SRAM_BASE	0x1e720000
+#define ASPEED_SRAM_SIZE	0x9000
+#elif defined(CONFIG_ASPEED_AST2600)
+#define ASPEED_MAC_COUNT	4
+#define ASPEED_DRAM_BASE	0x80000000
+#define ASPEED_SRAM_BASE	0x10000000
+#define ASPEED_SRAM_SIZE	0x10000
+#else
+#err "Unrecognized Aspeed platform."
+#endif
+
+#endif
diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
new file mode 100644
index 000000000..8db4901cc
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+#ifndef _ASM_ARCH_SCU_AST2500_H
+#define _ASM_ARCH_SCU_AST2500_H
+
+#define SCU_UNLOCK_VALUE		0x1688a8a8
+
+#define SCU_HWSTRAP_VGAMEM_SHIFT	2
+#define SCU_HWSTRAP_VGAMEM_MASK		(3 << SCU_HWSTRAP_VGAMEM_SHIFT)
+#define SCU_HWSTRAP_MAC1_RGMII		(1 << 6)
+#define SCU_HWSTRAP_MAC2_RGMII		(1 << 7)
+#define SCU_HWSTRAP_DDR4		(1 << 24)
+#define SCU_HWSTRAP_CLKIN_25MHZ		(1 << 23)
+
+#define SCU_MPLL_DENUM_SHIFT		0
+#define SCU_MPLL_DENUM_MASK		0x1f
+#define SCU_MPLL_NUM_SHIFT		5
+#define SCU_MPLL_NUM_MASK		(0xff << SCU_MPLL_NUM_SHIFT)
+#define SCU_MPLL_POST_SHIFT		13
+#define SCU_MPLL_POST_MASK		(0x3f << SCU_MPLL_POST_SHIFT)
+#define SCU_PCLK_DIV_SHIFT		23
+#define SCU_PCLK_DIV_MASK		(7 << SCU_PCLK_DIV_SHIFT)
+#define SCU_SDCLK_DIV_SHIFT		12
+#define SCU_SDCLK_DIV_MASK		(7 << SCU_SDCLK_DIV_SHIFT)
+#define SCU_HPLL_DENUM_SHIFT		0
+#define SCU_HPLL_DENUM_MASK		0x1f
+#define SCU_HPLL_NUM_SHIFT		5
+#define SCU_HPLL_NUM_MASK		(0xff << SCU_HPLL_NUM_SHIFT)
+#define SCU_HPLL_POST_SHIFT		13
+#define SCU_HPLL_POST_MASK		(0x3f << SCU_HPLL_POST_SHIFT)
+
+#define SCU_MACCLK_SHIFT		16
+#define SCU_MACCLK_MASK			(7 << SCU_MACCLK_SHIFT)
+
+#define SCU_MISC2_RGMII_HPLL		(1 << 23)
+#define SCU_MISC2_RGMII_CLKDIV_SHIFT	20
+#define SCU_MISC2_RGMII_CLKDIV_MASK	(3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
+#define SCU_MISC2_RMII_MPLL		(1 << 19)
+#define SCU_MISC2_RMII_CLKDIV_SHIFT	16
+#define SCU_MISC2_RMII_CLKDIV_MASK	(3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
+#define SCU_MISC2_UARTCLK_SHIFT		24
+
+#define SCU_MISC_D2PLL_OFF		(1 << 4)
+#define SCU_MISC_UARTCLK_DIV13		(1 << 12)
+#define SCU_MISC_GCRT_USB20CLK		(1 << 21)
+
+#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT	0
+#define SCU_MICDS_MAC1RGMII_TXDLY_MASK	(0x3f\
+					 << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT	6
+#define SCU_MICDS_MAC2RGMII_TXDLY_MASK	(0x3f\
+					 << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_RDLY_SHIFT	12
+#define SCU_MICDS_MAC1RMII_RDLY_MASK	(0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC2RMII_RDLY_SHIFT	18
+#define SCU_MICDS_MAC2RMII_RDLY_MASK	(0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_TXFALL	(1 << 24)
+#define SCU_MICDS_MAC2RMII_TXFALL	(1 << 25)
+#define SCU_MICDS_RMII1_RCLKEN		(1 << 29)
+#define SCU_MICDS_RMII2_RCLKEN		(1 << 30)
+#define SCU_MICDS_RGMIIPLL		(1 << 31)
+
+/*
+ * SYSRESET is actually more like a Power register,
+ * except that corresponding bit set to 1 means that
+ * the peripheral is off.
+ */
+#define SCU_SYSRESET_XDMA		(1 << 25)
+#define SCU_SYSRESET_MCTP		(1 << 24)
+#define SCU_SYSRESET_ADC		(1 << 23)
+#define SCU_SYSRESET_JTAG		(1 << 22)
+#define SCU_SYSRESET_MIC		(1 << 18)
+#define SCU_SYSRESET_SDIO		(1 << 16)
+#define SCU_SYSRESET_USB11HOST		(1 << 15)
+#define SCU_SYSRESET_USBHUB		(1 << 14)
+#define SCU_SYSRESET_CRT		(1 << 13)
+#define SCU_SYSRESET_MAC2		(1 << 12)
+#define SCU_SYSRESET_MAC1		(1 << 11)
+#define SCU_SYSRESET_PECI		(1 << 10)
+#define SCU_SYSRESET_PWM		(1 << 9)
+#define SCU_SYSRESET_PCI_VGA		(1 << 8)
+#define SCU_SYSRESET_2D			(1 << 7)
+#define SCU_SYSRESET_VIDEO		(1 << 6)
+#define SCU_SYSRESET_LPC		(1 << 5)
+#define SCU_SYSRESET_HAC		(1 << 4)
+#define SCU_SYSRESET_USBHID		(1 << 3)
+#define SCU_SYSRESET_I2C		(1 << 2)
+#define SCU_SYSRESET_AHB		(1 << 1)
+#define SCU_SYSRESET_SDRAM_WDT		(1 << 0)
+
+/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
+#define SCU_PINMUX_CTRL5_I2C		(1 << 16)
+
+/*
+ * The values are grouped by function, not by register.
+ * They are actually scattered across multiple loosely related registers.
+ */
+#define SCU_PIN_FUN_MAC1_MDC		(1 << 30)
+#define SCU_PIN_FUN_MAC1_MDIO		(1 << 31)
+#define SCU_PIN_FUN_MAC1_PHY_LINK	(1 << 0)
+#define SCU_PIN_FUN_MAC2_MDIO		(1 << 2)
+#define SCU_PIN_FUN_MAC2_PHY_LINK	(1 << 1)
+#define SCU_PIN_FUN_SCL1		(1 << 12)
+#define SCU_PIN_FUN_SCL2		(1 << 14)
+#define SCU_PIN_FUN_SDA1		(1 << 13)
+#define SCU_PIN_FUN_SDA2		(1 << 15)
+
+#define SCU_CLKSTOP_MAC1		(1 << 20)
+#define SCU_CLKSTOP_MAC2		(1 << 21)
+#define SCU_CLKSTOP_SDCLK		(1 << 27)
+
+#define SCU_D2PLL_EXT1_OFF		(1 << 0)
+#define SCU_D2PLL_EXT1_BYPASS		(1 << 1)
+#define SCU_D2PLL_EXT1_RESET		(1 << 2)
+#define SCU_D2PLL_EXT1_MODE_SHIFT	3
+#define SCU_D2PLL_EXT1_MODE_MASK	(3 << SCU_D2PLL_EXT1_MODE_SHIFT)
+#define SCU_D2PLL_EXT1_PARAM_SHIFT	5
+#define SCU_D2PLL_EXT1_PARAM_MASK	(0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
+
+#define SCU_D2PLL_NUM_SHIFT		0
+#define SCU_D2PLL_NUM_MASK		(0xff << SCU_D2PLL_NUM_SHIFT)
+#define SCU_D2PLL_DENUM_SHIFT		8
+#define SCU_D2PLL_DENUM_MASK		(0x1f << SCU_D2PLL_DENUM_SHIFT)
+#define SCU_D2PLL_POST_SHIFT		13
+#define SCU_D2PLL_POST_MASK		(0x3f << SCU_D2PLL_POST_SHIFT)
+#define SCU_D2PLL_ODIV_SHIFT		19
+#define SCU_D2PLL_ODIV_MASK		(7 << SCU_D2PLL_ODIV_SHIFT)
+#define SCU_D2PLL_SIC_SHIFT		22
+#define SCU_D2PLL_SIC_MASK		(0x1f << SCU_D2PLL_SIC_SHIFT)
+#define SCU_D2PLL_SIP_SHIFT		27
+#define SCU_D2PLL_SIP_MASK		(0x1f << SCU_D2PLL_SIP_SHIFT)
+
+#define SCU_CLKDUTY_DCLK_SHIFT		0
+#define SCU_CLKDUTY_DCLK_MASK		(0x3f << SCU_CLKDUTY_DCLK_SHIFT)
+#define SCU_CLKDUTY_RGMII1TXCK_SHIFT	8
+#define SCU_CLKDUTY_RGMII1TXCK_MASK	(0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT)
+#define SCU_CLKDUTY_RGMII2TXCK_SHIFT	16
+#define SCU_CLKDUTY_RGMII2TXCK_MASK	(0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
+
+#ifndef __ASSEMBLY__
+
+struct ast2500_clk_priv {
+	struct ast2500_scu *scu;
+};
+
+struct ast2500_scu {
+	u32 protection_key;
+	u32 sysreset_ctrl1;
+	u32 clk_sel1;
+	u32 clk_stop_ctrl1;
+	u32 freq_counter_ctrl;
+	u32 freq_counter_cmp;
+	u32 intr_ctrl;
+	u32 d2_pll_param;
+	u32 m_pll_param;
+	u32 h_pll_param;
+	u32 d_pll_param;
+	u32 misc_ctrl1;
+	u32 pci_config[3];
+	u32 sysreset_status;
+	u32 vga_handshake[2];
+	u32 mac_clk_delay;
+	u32 misc_ctrl2;
+	u32 vga_scratch[8];
+	u32 hwstrap;
+	u32 rng_ctrl;
+	u32 rng_data;
+	u32 rev_id;
+	u32 pinmux_ctrl[6];
+	u32 reserved0;
+	u32 extrst_sel;
+	u32 pinmux_ctrl1[4];
+	u32 reserved1[2];
+	u32 mac_clk_delay_100M;
+	u32 mac_clk_delay_10M;
+	u32 wakeup_enable;
+	u32 wakeup_control;
+	u32 reserved2[3];
+	u32 sysreset_ctrl2;
+	u32 clk_sel2;
+	u32 clk_stop_ctrl2;
+	u32 freerun_counter;
+	u32 freerun_counter_ext;
+	u32 clk_duty_meas_ctrl;
+	u32 clk_duty_meas_res;
+	u32 reserved3[4];
+	/* The next registers are not key-protected */
+	struct ast2500_cpu2 {
+		u32 ctrl;
+		u32 base_addr[9];
+		u32 cache_ctrl;
+	} cpu2;
+	u32 reserved4;
+	u32 d_pll_ext_param[3];
+	u32 d2_pll_ext_param[3];
+	u32 mh_pll_ext_param;
+	u32 reserved5;
+	u32 chip_id[2];
+	u32 reserved6[2];
+	u32 uart_clk_ctrl;
+	u32 reserved7[7];
+	u32 pcie_config;
+	u32 mmio_decode;
+	u32 reloc_ctrl_decode[2];
+	u32 mailbox_addr;
+	u32 shared_sram_decode[2];
+	u32 bmc_rev_id;
+	u32 reserved8;
+	u32 bmc_device_id;
+	u32 reserved9[13];
+	u32 clk_duty_sel;
+};
+
+/**
+ * ast_get_clk() - get a pointer to Clock Driver
+ *
+ * @devp, OUT - pointer to Clock Driver
+ * @return zero on success, error code (< 0) otherwise.
+ */
+int ast_get_clk(struct udevice **devp);
+
+/**
+ * ast_get_scu() - get a pointer to SCU registers
+ *
+ * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise
+ */
+void *ast_get_scu(void);
+
+/**
+ * ast_scu_unlock() - unlock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_unlock(struct ast2500_scu *scu);
+
+/**
+ * ast_scu_lock() - lock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_lock(struct ast2500_scu *scu);
+
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
new file mode 100644
index 000000000..a205fb1f7
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/scu_ast2600.h
@@ -0,0 +1,338 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef _ASM_ARCH_SCU_AST2600_H
+#define _ASM_ARCH_SCU_AST2600_H
+
+#define SCU_UNLOCK_KEY			0x1688a8a8
+
+#define SCU_CLKGATE1_EMMC			BIT(27)
+#define SCU_CLKGATE1_MAC2			BIT(21)
+#define SCU_CLKGATE1_MAC1			BIT(20)
+#define SCU_CLKGATE1_USB_HUB		BIT(14)
+#define SCU_CLKGATE1_USB_HOST2		BIT(7)
+
+#define SCU_CLKGATE2_FSI			BIT(30)
+#define SCU_CLKGATE2_MAC4			BIT(21)
+#define SCU_CLKGATE2_MAC3			BIT(20)
+#define SCU_CLKGATE2_SDIO			BIT(4)
+
+#define SCU_DRAM_HDSHK_SOC_INIT			BIT(7)
+#define SCU_DRAM_HDSHK_RDY			BIT(6)
+
+#define SCU_CLKSRC1_ECC_RSA_DIV_MASK		GENMASK(27, 26)
+#define SCU_CLKSRC1_ECC_RSA_DIV_SHIFT		26
+#define SCU_CLKSRC1_PCLK_DIV_MASK		GENMASK(25, 23)
+#define SCU_CLKSRC1_PCLK_DIV_SHIFT		23
+#define SCU_CLKSRC1_BCLK_DIV_MASK		GENMASK(22, 20)
+#define SCU_CLKSRC1_BCLK_DIV_SHIFT		20
+#define SCU_CLKSRC1_ECC_RSA			BIT(19)
+#define SCU_CLKSRC1_MAC_DIV_MASK		GENMASK(18, 16)
+#define SCU_CLKSRC1_MAC_DIV_SHIFT		16
+#define SCU_CLKSRC1_EMMC_EN			BIT(15)
+#define SCU_CLKSRC1_EMMC_DIV_MASK		GENMASK(14, 12)
+#define SCU_CLKSRC1_EMMC_DIV_SHIFT		12
+#define SCU_CLKSRC1_EMMC			BIT(11)
+
+#define SCU_CLKSRC2_RMII12			BIT(19)
+#define SCU_CLKSRC2_RMII12_DIV_MASK		GENMASK(18, 16)
+#define SCU_CLKSRC2_RMII12_DIV_SHIFT		16
+#define SCU_CLKSRC2_UART5			BIT(14)
+
+#define SCU_CLKSRC4_SDIO_EN			BIT(31)
+#define SCU_CLKSRC4_SDIO_DIV_MASK		GENMASK(30, 28)
+#define SCU_CLKSRC4_SDIO_DIV_SHIFT		28
+#define SCU_CLKSRC4_MAC_DIV_MASK		GENMASK(26, 24)
+#define SCU_CLKSRC4_MAC_DIV_SHIFT		24
+#define SCU_CLKSRC4_RMII34_DIV_MASK		GENMASK(18, 16)
+#define SCU_CLKSRC4_RMII34_DIV_SHIFT		16
+#define SCU_CLKSRC4_PCLK_DIV_MASK		GENMASK(11, 9)
+#define SCU_CLKSRC4_PCLK_DIV_SHIFT		9
+#define SCU_CLKSRC4_SDIO			BIT(8)
+#define SCU_CLKSRC4_UART6			BIT(5)
+#define SCU_CLKSRC4_UART4			BIT(3)
+#define SCU_CLKSRC4_UART3			BIT(2)
+#define SCU_CLKSRC4_UART2			BIT(1)
+#define SCU_CLKSRC4_UART1			BIT(0)
+
+#define SCU_CLKSRC5_UART13			BIT(12)
+#define SCU_CLKSRC5_UART12			BIT(11)
+#define SCU_CLKSRC5_UART11			BIT(10)
+#define SCU_CLKSRC5_UART10			BIT(9)
+#define SCU_CLKSRC5_UART9			BIT(8)
+#define SCU_CLKSRC5_UART8			BIT(7)
+#define SCU_CLKSRC5_UART7			BIT(6)
+#define SCU_CLKSRC5_HUXCLK_MASK			GENMASK(5, 3)
+#define SCU_CLKSRC5_HUXCLK_SHIFT		3
+#define SCU_CLKSRC5_UXCLK_MASK			GENMASK(2, 0)
+#define SCU_CLKSRC5_UXCLK_SHIFT			0
+
+#define SCU_PINCTRL1_EMMC_MASK			GENMASK(31, 24)
+#define SCU_PINCTRL1_EMMC_SHIFT			24
+
+#define SCU_PINCTRL16_MAC4_DRIVING_MASK		GENMASK(3, 2)
+#define SCU_PINCTRL16_MAC4_DRIVING_SHIFT	2
+#define SCU_PINCTRL16_MAC3_DRIVING_MASK		GENMASK(1, 0)
+#define SCU_PINCTRL16_MAC3_DRIVING_SHIFT	0
+
+#define SCU_HWSTRAP1_CPU_AXI_CLK_RATIO		BIT(16)
+#define SCU_HWSTRAP1_VGA_MEM_MASK		GENMASK(14, 13)
+#define SCU_HWSTRAP1_VGA_MEM_SHIFT		13
+#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK	GENMASK(12, 11)
+#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT	11
+#define SCU_HWSTRAP1_CPU_FREQ_MASK		GENMASK(10, 8)
+#define SCU_HWSTRAP1_CPU_FREQ_SHIFT		8
+#define SCU_HWSTRAP1_MAC2_INTF			BIT(7)
+#define SCU_HWSTRAP1_MAC1_INTF			BIT(6)
+
+#define SCU_EFUSE_DIS_DP			BIT(17)
+#define SCU_EFUSE_DIS_VGA			BIT(14)
+#define SCU_EFUSE_DIS_PCIE_EP			BIT(13)
+#define SCU_EFUSE_DIS_USB			BIT(12)
+#define SCU_EFUSE_DIS_RVAS			BIT(10)
+#define SCU_EFUSE_DIS_VIDEO_DEC			BIT(9)
+#define SCU_EFUSE_DIS_VIDEO			BIT(8)
+#define SCU_EFUSE_DIS_PCIE_RC			BIT(7)
+#define SCU_EFUSE_DIS_CM3			BIT(6)
+#define SCU_EFUSE_DIS_CA7			BIT(5)
+
+#define SCU_PLL_RST				BIT(25)
+#define SCU_PLL_BYPASS				BIT(24)
+#define SCU_PLL_OFF				BIT(23)
+#define SCU_PLL_DIV_MASK			GENMASK(22, 19)
+#define SCU_PLL_DIV_SHIFT			19
+#define SCU_PLL_DENUM_MASK			GENMASK(18, 13)
+#define SCU_PLL_DENUM_SHIFT			13
+#define SCU_PLL_NUM_MASK			GENMASK(12, 0)
+#define SCU_PLL_NUM_SHIFT			0
+
+#define SCU_UART_CLKGEN_N_MASK			GENMASK(17, 8)
+#define SCU_UART_CLKGEN_N_SHIFT			8
+#define SCU_UART_CLKGEN_R_MASK			GENMASK(7, 0)
+#define SCU_UART_CLKGEN_R_SHIFT			0
+
+#define SCU_HUART_CLKGEN_N_MASK			GENMASK(17, 8)
+#define SCU_HUART_CLKGEN_N_SHIFT		8
+#define SCU_HUART_CLKGEN_R_MASK			GENMASK(7, 0)
+#define SCU_HUART_CLKGEN_R_SHIFT		0
+
+#define SCU_MISC_CTRL1_UART5_DIV		BIT(12)
+
+#ifndef __ASSEMBLY__
+struct ast2600_scu {
+	uint32_t prot_key1;		/* 0x000 */
+	uint32_t chip_id1;		/* 0x004 */
+	uint32_t rsv_0x08;		/* 0x008 */
+	uint32_t rsv_0x0c;		/* 0x00C */
+	uint32_t prot_key2;		/* 0x010 */
+	uint32_t chip_id2;		/* 0x014 */
+	uint32_t rsv_0x18[10];		/* 0x018 ~ 0x03C */
+	uint32_t modrst_ctrl1;		/* 0x040 */
+	uint32_t modrst_clr1;		/* 0x044 */
+	uint32_t rsv_0x48;		/* 0x048 */
+	uint32_t rsv_0x4C;		/* 0x04C */
+	uint32_t modrst_ctrl2;		/* 0x050 */
+	uint32_t modrst_clr2;		/* 0x054 */
+	uint32_t rsv_0x58;		/* 0x058 */
+	uint32_t rsv_0x5C;		/* 0x05C */
+	uint32_t extrst_sel1;		/* 0x060 */
+	uint32_t sysrst_sts1_1;		/* 0x064 */
+	uint32_t sysrst_sts1_2;		/* 0x068 */
+	uint32_t sysrst_sts1_3;		/* 0x06C */
+	uint32_t extrst_sel2;		/* 0x070 */
+	uint32_t sysrst_sts2_1;		/* 0x074 */
+	uint32_t sysrst_sts2_2;		/* 0x078 */
+	uint32_t stsrst_sts3_2;		/* 0x07C */
+	uint32_t clkgate_ctrl1;		/* 0x080 */
+	uint32_t clkgate_clr1;		/* 0x084 */
+	uint32_t rsv_0x88;		/* 0x088 */
+	uint32_t rsv_0x8C;		/* 0x08C */
+	uint32_t clkgate_ctrl2;		/* 0x090 */
+	uint32_t clkgate_clr2;		/* 0x094 */
+	uint32_t rsv_0x98[10];		/* 0x098 ~ 0x0BC */
+	uint32_t misc_ctrl1;		/* 0x0C0 */
+	uint32_t misc_ctrl2;		/* 0x0C4 */
+	uint32_t debug_ctrl1;		/* 0x0C8 */
+	uint32_t rsv_0xCC;		/* 0x0CC */
+	uint32_t misc_ctrl3;		/* 0x0D0 */
+	uint32_t misc_ctrl4;		/* 0x0D4 */
+	uint32_t debug_ctrl2;		/* 0x0D8 */
+	uint32_t rsv_0xdc[9];		/* 0x0DC ~ 0x0FC */
+	uint32_t dram_hdshk;		/* 0x100 */
+	uint32_t soc_scratch[3];	/* 0x104 ~ 0x10C */
+	uint32_t rsv_0x110[4];		/* 0x110 ~ 0x11C*/
+	uint32_t cpu_scratch_wp;	/* 0x120 */
+	uint32_t rsv_0x124[23];		/* 0x124 */
+	uint32_t smp_boot[12];		/* 0x180 */
+	uint32_t cpu_scratch[20];	/* 0x1b0 */
+	uint32_t hpll;			/* 0x200 */
+	uint32_t hpll_ext;		/* 0x204 */
+	uint32_t rsv_0x208[2];		/* 0x208 ~ 0x20C */
+	uint32_t apll;			/* 0x210 */
+	uint32_t apll_ext;		/* 0x214 */
+	uint32_t rsv_0x218[2];		/* 0x218 ~ 0x21C */
+	uint32_t mpll;			/* 0x220 */
+	uint32_t mpll_ext;		/* 0x224 */
+	uint32_t rsv_0x228[6];		/* 0x228 ~ 0x23C */
+	uint32_t epll;			/* 0x240 */
+	uint32_t epll_ext;		/* 0x244 */
+	uint32_t rsv_0x248[6];		/* 0x248 ~ 0x25C */
+	uint32_t dpll;			/* 0x260 */
+	uint32_t dpll_ext;		/* 0x264 */
+	uint32_t rsv_0x268[38];		/* 0x268 ~ 0x2FC */
+	uint32_t clksrc1;		/* 0x300 */
+	uint32_t clksrc2;		/* 0x304 */
+	uint32_t clksrc3;		/* 0x308 */
+	uint32_t rsv_0x30c;		/* 0x30C */
+	uint32_t clksrc4;		/* 0x310 */
+	uint32_t clksrc5;		/* 0x314 */
+	uint32_t rsv_0x318[2];		/* 0x318 ~ 0x31C */
+	uint32_t freq_counter_ctrl1;	/* 0x320 */
+	uint32_t freq_counter_cmp1;	/* 0x324 */
+	uint32_t rsv_0x328[2];		/* 0x328 ~ 0x32C */
+	uint32_t freq_counter_ctrl2;	/* 0x330 */
+	uint32_t freq_counter_cmp2;	/* 0x334 */
+	uint32_t uart_clkgen;		/* 0x338 */
+	uint32_t huart_clkgen;		/* 0x33C */
+	uint32_t mac12_clk_delay;	/* 0x340 */
+	uint32_t rsv_0x344;		/* 0x344 */
+	uint32_t mac12_clk_delay_100M;	/* 0x348 */
+	uint32_t mac12_clk_delay_10M;	/* 0x34C */
+	uint32_t mac34_clk_delay;	/* 0x350 */
+	uint32_t rsv_0x354;		/* 0x354 */
+	uint32_t mac34_clk_delay_100M;	/* 0x358 */
+	uint32_t mac34_clk_delay_10M;	/* 0x35C */
+	uint32_t clkduty_meas_ctrl;	/* 0x360 */
+	uint32_t clkduty1;		/* 0x364 */
+	uint32_t clkduty2;		/* 0x368 */
+	uint32_t clkduty_meas_res;	/* 0x36C */
+	uint32_t clkduty_meas_ctrl2;	/* 0x370 */
+	uint32_t clkduty3;		/* 0x374 */
+	uint32_t rsv_0x378[34];		/* 0x378 ~ 0x3FC */
+	uint32_t pinmux1;		/* 0x400 */
+	uint32_t pinmux2;		/* 0x404 */
+	uint32_t rsv_0x408;		/* 0x408 */
+	uint32_t pinmux3;		/* 0x40C */
+	uint32_t pinmux4;		/* 0x410 */
+	uint32_t pinmux5;		/* 0x414 */
+	uint32_t pinmux6;		/* 0x418 */
+	uint32_t pinmux7;		/* 0x41C */
+	uint32_t rsv_0x420[4];		/* 0x420 ~ 0x42C */
+	uint32_t pinmux8;		/* 0x430 */
+	uint32_t pinmux9;		/* 0x434 */
+	uint32_t pinmux10;		/* 0x438 */
+	uint32_t rsv_0x43c;		/* 0x43C */
+	uint32_t pinmux12;		/* 0x440 */
+	uint32_t pinmux13;		/* 0x444 */
+	uint32_t rsv_0x448[2];		/* 0x448 ~ 0x44C */
+	uint32_t pinmux14;		/* 0x450 */
+	uint32_t pinmux15;		/* 0x454 */
+	uint32_t pinmux16;		/* 0x458 */
+	uint32_t rsv_0x45c[21];		/* 0x45C ~ 0x4AC */
+	uint32_t pinmux17;		/* 0x4B0 */
+	uint32_t pinmux18;		/* 0x4B4 */
+	uint32_t pinmux19;		/* 0x4B8 */
+	uint32_t pinmux20;		/* 0x4BC */
+	uint32_t rsv_0x4c0[5];		/* 0x4C0 ~ 0x4D0 */
+	uint32_t pinmux22;		/* 0x4D4 */
+	uint32_t pinmux23;		/* 0x4D8 */
+	uint32_t rsv_0x4dc[9];		/* 0x4DC ~ 0x4FC */
+	uint32_t hwstrap1;		/* 0x500 */
+	uint32_t hwstrap_clr1;		/* 0x504 */
+	uint32_t hwstrap_prot1;		/* 0x508 */
+	uint32_t rsv_0x50c;		/* 0x50C */
+	uint32_t hwstrap2;		/* 0x510 */
+	uint32_t hwstrap_clr2;		/* 0x514 */
+	uint32_t hwstrap_prot2;		/* 0x518 */
+	uint32_t rsv_0x51c;		/* 0x51C */
+	uint32_t rng_ctrl;		/* 0x520 */
+	uint32_t rng_data;		/* 0x524 */
+	uint32_t rsv_0x528[6];		/* 0x528 ~ 0x53C */
+	uint32_t pwr_save_wakeup_en1;	/* 0x540 */
+	uint32_t pwr_save_wakeup_ctrl1;	/* 0x544 */
+	uint32_t rsv_0x548[2];		/* 0x548 */
+	uint32_t pwr_save_wakeup_en2;	/* 0x550 */
+	uint32_t pwr_save_wakeup_ctrl2;	/* 0x554 */
+	uint32_t rsv_0x558[2];		/* 0x558 */
+	uint32_t intr1_ctrl_sts;	/* 0x560 */
+	uint32_t rsv_0x564[3];		/* 0x564 */
+	uint32_t intr2_ctrl_sts;	/* 0x570 */
+	uint32_t rsv_0x574[7];		/* 0x574 ~ 0x58C */
+	uint32_t otp_ctrl;		/* 0x590 */
+	uint32_t efuse;			/* 0x594 */
+	uint32_t rsv_0x598[6];		/* 0x598 */
+	uint32_t chip_unique_id[8];	/* 0x5B0 */
+	uint32_t rsv_0x5e0[8];		/* 0x5E0 ~ 0x5FC */
+	uint32_t disgpio_in_pull_down0;	/* 0x610 */
+	uint32_t disgpio_in_pull_down1;	/* 0x614 */
+	uint32_t disgpio_in_pull_down2;	/* 0x618 */
+	uint32_t disgpio_in_pull_down3;	/* 0x61C */
+	uint32_t rsv_0x620[4];		/* 0x620 ~ 0x62C */
+	uint32_t disgpio_in_pull_down4;	/* 0x630 */
+	uint32_t disgpio_in_pull_down5;	/* 0x634 */
+	uint32_t disgpio_in_pull_down6;	/* 0x638 */
+	uint32_t rsv_0x63c[5];		/* 0x63C ~ 0x64C */
+	uint32_t sli_driving_strength;	/* 0x650 */
+	uint32_t rsv_0x654[107];	/* 0x654 ~ 0x7FC */
+	uint32_t ca7_ctrl1;		/* 0x800 */
+	uint32_t ca7_ctrl2;		/* 0x804 */
+	uint32_t ca7_ctrl3;		/* 0x808 */
+	uint32_t ca7_ctrl4;		/* 0x80C */
+	uint32_t rsv_0x810[4];		/* 0x810 ~ 0x81C */
+	uint32_t ca7_parity_chk;	/* 0x820 */
+	uint32_t ca7_parity_clr;	/* 0x824 */
+	uint32_t rsv_0x828[118];	/* 0x828 ~ 0x9FC */
+	uint32_t cm3_ctrl;		/* 0xA00 */
+	uint32_t cm3_base;		/* 0xA04 */
+	uint32_t cm3_imem_addr;		/* 0xA08 */
+	uint32_t cm3_dmem_addr;		/* 0xA0C */
+	uint32_t rsv_0xa10[12];		/* 0xA10 ~ 0xA3C */
+	uint32_t cm3_cache_area;	/* 0xA40 */
+	uint32_t cm3_cache_invd_ctrl;	/* 0xA44 */
+	uint32_t cm3_cache_func_ctrl;	/* 0xA48 */
+	uint32_t rsv_0xa4c[108];	/* 0xA4C ~ 0xBFC */
+	uint32_t pci_cfg[3];		/* 0xC00 */
+	uint32_t rsv_0xc0c[5];		/* 0xC0C ~ 0xC1C */
+	uint32_t pcie_cfg;		/* 0xC20 */
+	uint32_t mmio_decode;		/* 0xC24 */
+	uint32_t reloc_ctrl_decode[2];	/* 0xC28 */
+	uint32_t rsv_0xc30[4];		/* 0xC30 ~ 0xC3C */
+	uint32_t mbox_decode;		/* 0xC40 */
+	uint32_t shared_sram_decode[2];	/* 0xC44 */
+	uint32_t bmc_rev_id;		/* 0xC4C */
+	uint32_t rsv_0xc50[5];		/* 0xC50 ~ 0xC60 */
+	uint32_t bmc_device_id;		/* 0xC64 */
+	uint32_t rsv_0xc68[102];	/* 0xC68 ~ 0xDFC */
+	uint32_t vga_scratch1;		/* 0xE00 */
+	uint32_t vga_scratch2;		/* 0xE04 */
+	uint32_t vga_scratch3;		/* 0xE08 */
+	uint32_t vga_scratch4;		/* 0xE0C */
+	uint32_t rsv_0xe10[4];		/* 0xE10 ~ 0xE1C */
+	uint32_t vga_scratch5;		/* 0xE20 */
+	uint32_t vga_scratch6;		/* 0xE24 */
+	uint32_t vga_scratch7;		/* 0xE28 */
+	uint32_t vga_scratch8;		/* 0xE2C */
+	uint32_t rsv_0xe30[52];		/* 0xE30 ~ 0xEFC */
+	uint32_t wr_prot1;		/* 0xF00 */
+	uint32_t wr_prot2;		/* 0xF04 */
+	uint32_t wr_prot3;		/* 0xF08 */
+	uint32_t wr_prot4;		/* 0xF0C */
+	uint32_t wr_prot5;		/* 0xF10 */
+	uint32_t wr_prot6;		/* 0xF18 */
+	uint32_t wr_prot7;		/* 0xF1C */
+	uint32_t wr_prot8;		/* 0xF20 */
+	uint32_t wr_prot9;		/* 0xF24 */
+	uint32_t rsv_0xf28[2];		/* 0xF28 ~ 0xF2C */
+	uint32_t wr_prot10;		/* 0xF30 */
+	uint32_t wr_prot11;		/* 0xF34 */
+	uint32_t wr_prot12;		/* 0xF38 */
+	uint32_t wr_prot13;		/* 0xF3C */
+	uint32_t wr_prot14;		/* 0xF40 */
+	uint32_t rsv_0xf44;		/* 0xF44 */
+	uint32_t wr_prot15;		/* 0xF48 */
+	uint32_t rsv_0xf4c[5];		/* 0xF4C ~ 0xF5C */
+	uint32_t wr_prot16;		/* 0xF60 */
+};
+#endif
+#endif
diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h
new file mode 100644
index 000000000..0bc551fbe
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+#ifndef _ASM_ARCH_SDRAM_AST2500_H
+#define _ASM_ARCH_SDRAM_AST2500_H
+
+#define SDRAM_UNLOCK_KEY		0xfc600309
+#define SDRAM_VIDEO_UNLOCK_KEY		0x2003000f
+
+#define SDRAM_PCR_CKE_EN		(1 << 0)
+#define SDRAM_PCR_AUTOPWRDN_EN		(1 << 1)
+#define SDRAM_PCR_CKE_DELAY_SHIFT	4
+#define SDRAM_PCR_CKE_DELAY_MASK	7
+#define SDRAM_PCR_RESETN_DIS		(1 << 7)
+#define SDRAM_PCR_ODT_EN		(1 << 8)
+#define SDRAM_PCR_ODT_AUTO_ON		(1 << 10)
+#define SDRAM_PCR_ODT_EXT_EN		(1 << 11)
+#define SDRAM_PCR_TCKE_PW_SHIFT		12
+#define SDRAM_PCR_TCKE_PW_MASK		7
+#define SDRAM_PCR_RGAP_CTRL_EN		(1 << 15)
+#define SDRAM_PCR_MREQI_DIS		(1 << 17)
+
+/* Fixed priority DRAM Requests mask */
+#define SDRAM_REQ_VGA_HW_CURSOR		(1 << 0)
+#define SDRAM_REQ_VGA_TEXT_CG_FONT	(1 << 1)
+#define SDRAM_REQ_VGA_TEXT_ASCII	(1 << 2)
+#define SDRAM_REQ_VGA_CRT		(1 << 3)
+#define SDRAM_REQ_SOC_DC_CURSOR		(1 << 4)
+#define SDRAM_REQ_SOC_DC_OCD		(1 << 5)
+#define SDRAM_REQ_SOC_DC_CRT		(1 << 6)
+#define SDRAM_REQ_VIDEO_HIPRI_WRITE	(1 << 7)
+#define SDRAM_REQ_USB20_EHCI1		(1 << 8)
+#define SDRAM_REQ_USB20_EHCI2		(1 << 9)
+#define SDRAM_REQ_CPU			(1 << 10)
+#define SDRAM_REQ_AHB2			(1 << 11)
+#define SDRAM_REQ_AHB			(1 << 12)
+#define SDRAM_REQ_MAC0			(1 << 13)
+#define SDRAM_REQ_MAC1			(1 << 14)
+#define SDRAM_REQ_PCIE			(1 << 16)
+#define SDRAM_REQ_XDMA			(1 << 17)
+#define SDRAM_REQ_ENCRYPTION		(1 << 18)
+#define SDRAM_REQ_VIDEO_FLAG		(1 << 21)
+#define SDRAM_REQ_VIDEO_LOW_PRI_WRITE	(1 << 28)
+#define SDRAM_REQ_2D_RW			(1 << 29)
+#define SDRAM_REQ_MEMCHECK		(1 << 30)
+
+#define SDRAM_ICR_RESET_ALL		(1 << 31)
+
+#define SDRAM_CONF_CAP_SHIFT		0
+#define SDRAM_CONF_CAP_MASK		3
+#define SDRAM_CONF_DDR4			(1 << 4)
+#define SDRAM_CONF_SCRAMBLE		(1 << 8)
+#define SDRAM_CONF_SCRAMBLE_PAT2	(1 << 9)
+#define SDRAM_CONF_CACHE_EN		(1 << 10)
+#define SDRAM_CONF_CACHE_INIT_EN	(1 << 12)
+#define SDRAM_CONF_DUALX8		(1 << 13)
+#define SDRAM_CONF_CACHE_INIT_DONE	(1 << 19)
+
+#define SDRAM_CONF_CAP_128M		0
+#define SDRAM_CONF_CAP_256M		1
+#define SDRAM_CONF_CAP_512M		2
+#define SDRAM_CONF_CAP_1024M		3
+
+#define SDRAM_MISC_DDR4_TREFRESH	(1 << 3)
+
+#define SDRAM_PHYCTRL0_INIT		(1 << 0)
+#define SDRAM_PHYCTRL0_AUTO_UPDATE	(1 << 1)
+#define SDRAM_PHYCTRL0_NRST		(1 << 2)
+
+#define SDRAM_REFRESH_CYCLES_SHIFT	0
+#define SDRAM_REFRESH_CYCLES_MASK	0xf
+#define SDRAM_REFRESH_ZQCS_EN		(1 << 7)
+#define SDRAM_REFRESH_PERIOD_SHIFT	8
+#define SDRAM_REFRESH_PERIOD_MASK	0xf
+
+#define SDRAM_TEST_LEN_SHIFT		4
+#define SDRAM_TEST_LEN_MASK		0xfffff
+#define SDRAM_TEST_START_ADDR_SHIFT	24
+#define SDRAM_TEST_START_ADDR_MASK	0x3f
+
+#define SDRAM_TEST_EN			(1 << 0)
+#define SDRAM_TEST_MODE_SHIFT		1
+#define SDRAM_TEST_MODE_MASK		3
+#define SDRAM_TEST_MODE_WO		0
+#define SDRAM_TEST_MODE_RB		1
+#define SDRAM_TEST_MODE_RW		2
+#define SDRAM_TEST_GEN_MODE_SHIFT	3
+#define SDRAM_TEST_GEN_MODE_MASK	7
+#define SDRAM_TEST_TWO_MODES		(1 << 6)
+#define SDRAM_TEST_ERRSTOP		(1 << 7)
+#define SDRAM_TEST_DONE			(1 << 12)
+#define SDRAM_TEST_FAIL			(1 << 13)
+
+#define SDRAM_AC_TRFC_SHIFT		0
+#define SDRAM_AC_TRFC_MASK		0xff
+
+#ifndef __ASSEMBLY__
+
+struct ast2500_sdrammc_regs {
+	u32 protection_key;
+	u32 config;
+	u32 gm_protection_key;
+	u32 refresh_timing;
+	u32 ac_timing[3];
+	u32 misc_control;
+	u32 mr46_mode_setting;
+	u32 mr5_mode_setting;
+	u32 mode_setting_control;
+	u32 mr02_mode_setting;
+	u32 mr13_mode_setting;
+	u32 power_control;
+	u32 req_limit_mask;
+	u32 pri_group_setting;
+	u32 max_grant_len[4];
+	u32 intr_ctrl;
+	u32 ecc_range_ctrl;
+	u32 first_ecc_err_addr;
+	u32 last_ecc_err_addr;
+	u32 phy_ctrl[4];
+	u32 ecc_test_ctrl;
+	u32 test_addr;
+	u32 test_fail_dq_bit;
+	u32 test_init_val;
+	u32 phy_debug_ctrl;
+	u32 phy_debug_data;
+	u32 reserved1[30];
+	u32 scu_passwd;
+	u32 reserved2[7];
+	u32 scu_mpll;
+	u32 reserved3[19];
+	u32 scu_hwstrap;
+};
+
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* _ASM_ARCH_SDRAM_AST2500_H */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
new file mode 100644
index 000000000..d2408c002
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef _ASM_ARCH_SDRAM_AST2600_H
+#define _ASM_ARCH_SDRAM_AST2600_H
+
+/* keys for unlocking HW */
+#define SDRAM_UNLOCK_KEY		0xFC600309
+#define SDRAM_VIDEO_UNLOCK_KEY		0x00440003
+
+/* Fixed priority DRAM Requests mask */
+#define REQ_PRI_VGA_HW_CURSOR_R         0
+#define REQ_PRI_VGA_CRT_R               1
+#define REQ_PRI_SOC_DISPLAY_CTRL_R      2
+#define REQ_PRI_PCIE_BUS1_RW            3
+#define REQ_PRI_VIDEO_HIGH_PRI_W        4
+#define REQ_PRI_CPU_RW                  5
+#define REQ_PRI_SLI_RW                  6
+#define REQ_PRI_PCIE_BUS2_RW            7
+#define REQ_PRI_USB2_0_HUB_EHCI1_DMA_RW 8
+#define REQ_PRI_USB2_0_DEV_EHCI2_DMA_RW 9
+#define REQ_PRI_USB1_1_UHCI_HOST_RW     10
+#define REQ_PRI_AHB_BUS_RW              11
+#define REQ_PRI_CM3_DATA_RW             12
+#define REQ_PRI_CM3_INST_R              13
+#define REQ_PRI_MAC0_DMA_RW             14
+#define REQ_PRI_MAC1_DMA_RW             15
+#define REQ_PRI_SDIO_DMA_RW             16
+#define REQ_PRI_PILOT_ENGINE_RW         17
+#define REQ_PRI_XDMA1_RW                18
+#define REQ_PRI_MCTP1_RW                19
+#define REQ_PRI_VIDEO_FLAG_RW           20
+#define REQ_PRI_VIDEO_LOW_PRI_W         21
+#define REQ_PRI_2D_ENGINE_DATA_RW       22
+#define REQ_PRI_ENC_ENGINE_RW           23
+#define REQ_PRI_MCTP2_RW                24
+#define REQ_PRI_XDMA2_RW                25
+#define REQ_PRI_ECC_RSA_RW              26
+
+#define MCR30_RESET_DLL_DELAY_EN	BIT(4)
+#define MCR30_MODE_REG_SEL_SHIFT	1
+#define MCR30_MODE_REG_SEL_MASK		GENMASK(3, 1)
+#define MCR30_SET_MODE_REG		BIT(0)
+
+#define MCR30_SET_MR(mr) ((mr << MCR30_MODE_REG_SEL_SHIFT) | MCR30_SET_MODE_REG)
+
+#define MCR34_SELF_REFRESH_STATUS_MASK	GENMASK(30, 28)
+
+#define MCR34_ODT_DELAY_SHIFT		12
+#define MCR34_ODT_DELAY_MASK		GENMASK(15, 12)
+#define MCR34_ODT_EXT_SHIFT		10
+#define MCR34_ODT_EXT_MASK		GENMASK(11, 10)
+#define MCR34_ODT_AUTO_ON		BIT(9)
+#define MCR34_ODT_EN			BIT(8)
+#define MCR34_RESETN_DIS		BIT(7)
+#define MCR34_MREQI_DIS			BIT(6)
+#define MCR34_MREQ_BYPASS_DIS		BIT(5)
+#define MCR34_RGAP_CTRL_EN		BIT(4)
+#define MCR34_CKE_OUT_IN_SELF_REF_DIS	BIT(3)
+#define MCR34_FOURCE_SELF_REF_EN	BIT(2)
+#define MCR34_AUTOPWRDN_EN		BIT(1)
+#define MCR34_CKE_EN			BIT(0)
+
+#define MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT	16
+#define MCR38_RW_MAX_GRANT_CNT_RQ_MASK	GENMASK(20, 16)
+
+/* default request queued limitation mask (0xFFBBFFF4) */
+#define MCR3C_DEFAULT_MASK                                                     \
+	~(REQ_PRI_VGA_HW_CURSOR_R | REQ_PRI_VGA_CRT_R | REQ_PRI_PCIE_BUS1_RW | \
+	  REQ_PRI_XDMA1_RW | REQ_PRI_2D_ENGINE_DATA_RW)
+
+#define MCR50_RESET_ALL_INTR		BIT(31)
+#define SDRAM_CONF_ECC_AUTO_SCRUBBING	BIT(9)
+#define SDRAM_CONF_SCRAMBLE		BIT(8)
+#define SDRAM_CONF_ECC_EN		BIT(7)
+#define SDRAM_CONF_DUALX8		BIT(5)
+#define SDRAM_CONF_DDR4			BIT(4)
+#define SDRAM_CONF_VGA_SIZE_SHIFT	2
+#define SDRAM_CONF_VGA_SIZE_MASK	GENMASK(3, 2)
+#define SDRAM_CONF_CAP_SHIFT		0
+#define SDRAM_CONF_CAP_MASK		GENMASK(1, 0)
+
+#define SDRAM_CONF_CAP_256M		0
+#define SDRAM_CONF_CAP_512M		1
+#define SDRAM_CONF_CAP_1024M		2
+#define SDRAM_CONF_CAP_2048M		3
+#define SDRAM_CONF_ECC_SETUP		(SDRAM_CONF_ECC_AUTO_SCRUBBING | SDRAM_CONF_ECC_EN)
+
+#define SDRAM_MISC_DDR4_TREFRESH	(1 << 3)
+
+#define SDRAM_PHYCTRL0_PLL_LOCKED	BIT(4)
+#define SDRAM_PHYCTRL0_NRST		BIT(2)
+#define SDRAM_PHYCTRL0_INIT		BIT(0)
+
+/* MCR0C */
+#define SDRAM_REFRESH_PERIOD_ZQCS_SHIFT	16
+#define SDRAM_REFRESH_PERIOD_ZQCS_MASK	GENMASK(31, 16)
+#define SDRAM_REFRESH_PERIOD_SHIFT	8
+#define SDRAM_REFRESH_PERIOD_MASK	GENMASK(15, 8)
+#define SDRAM_REFRESH_ZQCS_EN		BIT(7)
+#define SDRAM_RESET_DLL_ZQCL_EN		BIT(6)
+#define SDRAM_LOW_PRI_REFRESH_EN	BIT(5)
+#define SDRAM_FORCE_PRECHARGE_EN	BIT(4)
+#define SDRAM_REFRESH_EN		BIT(0)
+
+#define SDRAM_TEST_LEN_SHIFT		4
+#define SDRAM_TEST_LEN_MASK		0xfffff
+#define SDRAM_TEST_START_ADDR_SHIFT	24
+#define SDRAM_TEST_START_ADDR_MASK	0x3f
+
+#define SDRAM_TEST_EN			(1 << 0)
+#define SDRAM_TEST_MODE_SHIFT		1
+#define SDRAM_TEST_MODE_MASK		(0x3 << SDRAM_TEST_MODE_SHIFT)
+#define SDRAM_TEST_MODE_WO		(0x0 << SDRAM_TEST_MODE_SHIFT)
+#define SDRAM_TEST_MODE_RB		(0x1 << SDRAM_TEST_MODE_SHIFT)
+#define SDRAM_TEST_MODE_RW		(0x2 << SDRAM_TEST_MODE_SHIFT)
+
+#define SDRAM_TEST_GEN_MODE_SHIFT	3
+#define SDRAM_TEST_GEN_MODE_MASK	(7 << SDRAM_TEST_GEN_MODE_SHIFT)
+#define SDRAM_TEST_TWO_MODES		(1 << 6)
+#define SDRAM_TEST_ERRSTOP		(1 << 7)
+#define SDRAM_TEST_DONE			(1 << 12)
+#define SDRAM_TEST_FAIL			(1 << 13)
+
+#define SDRAM_AC_TRFC_SHIFT		0
+#define SDRAM_AC_TRFC_MASK		0xff
+
+#define SDRAM_ECC_RANGE_ADDR_MASK	GENMASK(30, 20)
+#define SDRAM_ECC_RANGE_ADDR_SHIFT	20
+
+#ifndef __ASSEMBLY__
+struct ast2600_sdrammc_regs {
+	u32 protection_key;		/* offset 0x00 */
+	u32 config;			/* offset 0x04 */
+	u32 gm_protection_key;		/* offset 0x08 */
+	u32 refresh_timing;		/* offset 0x0C */
+	u32 ac_timing[4];		/* offset 0x10 ~ 0x1C */
+	u32 mr01_mode_setting;		/* offset 0x20 */
+	u32 mr23_mode_setting;		/* offset 0x24 */
+	u32 mr45_mode_setting;		/* offset 0x28 */
+	u32 mr6_mode_setting;		/* offset 0x2C */
+	u32 mode_setting_control;	/* offset 0x30 */
+	u32 power_ctrl;			/* offset 0x34 */
+	u32 arbitration_ctrl;		/* offset 0x38 */
+	u32 req_limit_mask;		/* offset 0x3C */
+	u32 max_grant_len[4];		/* offset 0x40 ~ 0x4C */
+	u32 intr_ctrl;			/* offset 0x50 */
+	u32 ecc_range_ctrl;		/* offset 0x54 */
+	u32 first_ecc_err_addr;		/* offset 0x58 */
+	u32 last_ecc_err_addr;		/* offset 0x5C */
+	u32 phy_ctrl[4];		/* offset 0x60 ~ 0x6C */
+	u32 ecc_test_ctrl;		/* offset 0x70 */
+	u32 test_addr;			/* offset 0x74 */
+	u32 test_fail_dq_bit;		/* offset 0x78 */
+	u32 test_init_val;		/* offset 0x7C */
+	u32 req_input_ctrl;		/* offset 0x80 */
+	u32 req_high_pri_ctrl;		/* offset 0x84 */
+	u32 reserved0[6];		/* offset 0x88 ~ 0x9C */
+};
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* _ASM_ARCH_SDRAM_AST2600_H */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/timer.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/timer.h
new file mode 100644
index 000000000..ff24e2f86
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/timer.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+#ifndef _ASM_ARCH_TIMER_H
+#define _ASM_ARCH_TIMER_H
+
+/* Each timer has 4 control bits in ctrl1 register.
+ * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
+ * such that timer X uses bits (4 * X - 4):(4 * X - 1)
+ * If the timer does not support PWM, bit 4 is reserved.
+ */
+#define AST_TMC_EN			(1 << 0)
+#define AST_TMC_1MHZ			(1 << 1)
+#define AST_TMC_OVFINTR			(1 << 2)
+#define AST_TMC_PWM			(1 << 3)
+
+/* Timers are counted from 1 in the datasheet. */
+#define AST_TMC_CTRL1_SHIFT(n)			(4 * ((n) - 1))
+
+#define AST_TMC_RATE  (1000*1000)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * All timers share control registers, which makes it harder to make them
+ * separate devices. Since only one timer is needed at the moment, making
+ * it this just one device.
+ */
+
+struct ast_timer_counter {
+	u32 status;
+	u32 reload_val;
+	u32 match1;
+	u32 match2;
+};
+
+struct ast_timer {
+	struct ast_timer_counter timers1[3];
+	u32 ctrl1;
+	u32 ctrl2;
+#ifdef CONFIG_ASPEED_AST2500
+	u32 ctrl3;
+	u32 ctrl1_clr;
+#else
+	u32 reserved[2];
+#endif
+	struct ast_timer_counter timers2[5];
+};
+
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* _ASM_ARCH_TIMER_H */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt.h
new file mode 100644
index 000000000..fb04d41d3
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_WDT_H
+#define _ASM_ARCH_WDT_H
+
+#define WDT_BASE			0x1e785000
+
+/*
+ * Special value that needs to be written to counter_restart register to
+ * (re)start the timer
+ */
+#define WDT_COUNTER_RESTART_VAL		0x4755
+
+/* Control register */
+#define WDT_CTRL_RESET_MODE_SHIFT	5
+#define WDT_CTRL_RESET_MODE_MASK	3
+
+#define WDT_CTRL_EN			(1 << 0)
+#define WDT_CTRL_RESET			(1 << 1)
+#define WDT_CTRL_CLK1MHZ		(1 << 4)
+#define WDT_CTRL_2ND_BOOT		(1 << 7)
+
+/* Values for Reset Mode */
+#define WDT_CTRL_RESET_SOC		0
+#define WDT_CTRL_RESET_CHIP		1
+#define WDT_CTRL_RESET_CPU		2
+#define WDT_CTRL_RESET_MASK		3
+
+/* Reset Mask register */
+#define WDT_RESET_ARM			(1 << 0)
+#define WDT_RESET_COPROC		(1 << 1)
+#define WDT_RESET_SDRAM			(1 << 2)
+#define WDT_RESET_AHB			(1 << 3)
+#define WDT_RESET_I2C			(1 << 4)
+#define WDT_RESET_MAC1			(1 << 5)
+#define WDT_RESET_MAC2			(1 << 6)
+#define WDT_RESET_GCRT			(1 << 7)
+#define WDT_RESET_USB20			(1 << 8)
+#define WDT_RESET_USB11_HOST		(1 << 9)
+#define WDT_RESET_USB11_EHCI2		(1 << 10)
+#define WDT_RESET_VIDEO			(1 << 11)
+#define WDT_RESET_HAC			(1 << 12)
+#define WDT_RESET_LPC			(1 << 13)
+#define WDT_RESET_SDSDIO		(1 << 14)
+#define WDT_RESET_MIC			(1 << 15)
+#define WDT_RESET_CRT2C			(1 << 16)
+#define WDT_RESET_PWM			(1 << 17)
+#define WDT_RESET_PECI			(1 << 18)
+#define WDT_RESET_JTAG			(1 << 19)
+#define WDT_RESET_ADC			(1 << 20)
+#define WDT_RESET_GPIO			(1 << 21)
+#define WDT_RESET_MCTP			(1 << 22)
+#define WDT_RESET_XDMA			(1 << 23)
+#define WDT_RESET_SPI			(1 << 24)
+#define WDT_RESET_MISC			(1 << 25)
+
+#define WDT_RESET_DEFAULT						\
+	(WDT_RESET_ARM | WDT_RESET_COPROC | WDT_RESET_I2C |		\
+	 WDT_RESET_MAC1 | WDT_RESET_MAC2 | WDT_RESET_GCRT |		\
+	 WDT_RESET_USB20 | WDT_RESET_USB11_HOST | WDT_RESET_USB11_EHCI2 | \
+	 WDT_RESET_VIDEO | WDT_RESET_HAC | WDT_RESET_LPC |		\
+	 WDT_RESET_SDSDIO | WDT_RESET_MIC | WDT_RESET_CRT2C |		\
+	 WDT_RESET_PWM | WDT_RESET_PECI | WDT_RESET_JTAG |		\
+	 WDT_RESET_ADC | WDT_RESET_GPIO | WDT_RESET_MISC)
+
+#ifndef __ASSEMBLY__
+struct ast_wdt {
+	u32 counter_status;
+	u32 counter_reload_val;
+	u32 counter_restart;
+	u32 ctrl;
+	u32 timeout_status;
+	u32 clr_timeout_status;
+	u32 reset_width;
+	/* On pre-ast2500 SoCs this register is reserved. */
+	u32 reset_mask;
+};
+
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mode value from it.
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mode value
+ */
+u32 ast_reset_mode_from_flags(ulong flags);
+
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mask value from it. Reset Mask is only supported on ast2500
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mask value
+ */
+u32 ast_reset_mask_from_flags(ulong flags);
+
+/**
+ * Given Reset Mask and Reset Mode values, converts them to flags,
+ * suitable for passing into wdt_start or wdt_reset uclass functions.
+ *
+ * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
+ * can both be packed into single 32 bits wide value.
+ *
+ * @reset_mode: Reset Mode
+ * @reset_mask: Reset Mask
+ */
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
+#endif  /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARCH_WDT_H */
diff --git a/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt_ast2600.h b/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt_ast2600.h
new file mode 100644
index 000000000..96e8ca07e
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-aspeed/wdt_ast2600.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 Aspeed Technology Inc.
+ */
+
+#ifndef _ASM_ARCH_WDT_AST2600_H
+#define _ASM_ARCH_WDT_AST2600_H
+
+#define WDT_BASE			0x1e785000
+
+/*
+ * Special value that needs to be written to counter_restart register to
+ * (re)start the timer
+ */
+#define WDT_COUNTER_RESTART_VAL		0x4755
+
+/* reset mode */
+#define WDT_RESET_MODE_SOC		0
+#define WDT_RESET_MODE_CHIP		1
+#define WDT_RESET_MODE_CPU		2
+
+/* bit-fields of WDT control register */
+#define WDT_CTRL_2ND_BOOT		BIT(7)
+#define WDT_CTRL_RESET_MODE_MASK	GENMASK(6, 5)
+#define WDT_CTRL_RESET_MODE_SHIFT	5
+#define WDT_CTRL_CLK1MHZ		BIT(4)
+#define WDT_CTRL_RESET			BIT(1)
+#define WDT_CTRL_EN			BIT(0)
+
+/* bit-fields of WDT reset mask1 register */
+#define WDT_RESET_MASK1_RVAS		BIT(25)
+#define WDT_RESET_MASK1_GPIO1		BIT(24)
+#define WDT_RESET_MASK1_XDMA2		BIT(23)
+#define WDT_RESET_MASK1_XDMA1		BIT(22)
+#define WDT_RESET_MASK1_MCTP2		BIT(21)
+#define WDT_RESET_MASK1_MCTP1		BIT(20)
+#define WDT_RESET_MASK1_JTAG1		BIT(19)
+#define WDT_RESET_MASK1_SD_SDIO1	BIT(18)
+#define WDT_RESET_MASK1_MAC2		BIT(17)
+#define WDT_RESET_MASK1_MAC1		BIT(16)
+#define WDT_RESET_MASK1_GPMCU		BIT(15)
+#define WDT_RESET_MASK1_DPMCU		BIT(14)
+#define WDT_RESET_MASK1_DP		BIT(13)
+#define WDT_RESET_MASK1_HAC		BIT(12)
+#define WDT_RESET_MASK1_VIDEO		BIT(11)
+#define WDT_RESET_MASK1_CRT		BIT(10)
+#define WDT_RESET_MASK1_GCRT		BIT(9)
+#define WDT_RESET_MASK1_USB11_UHCI	BIT(8)
+#define WDT_RESET_MASK1_USB_PORTA	BIT(7)
+#define WDT_RESET_MASK1_USB_PORTB	BIT(6)
+#define WDT_RESET_MASK1_COPROC		BIT(5)
+#define WDT_RESET_MASK1_SOC		BIT(4)
+#define WDT_RESET_MASK1_SLI		BIT(3)
+#define WDT_RESET_MASK1_AHB		BIT(2)
+#define WDT_RESET_MASK1_SDRAM		BIT(1)
+#define WDT_RESET_MASK1_ARM		BIT(0)
+
+/* bit-fields of WDT reset mask2 register */
+#define WDT_RESET_MASK2_ESPI		BIT(26)
+#define WDT_RESET_MASK2_I3C_BUS8	BIT(25)
+#define WDT_RESET_MASK2_I3C_BUS7	BIT(24)
+#define WDT_RESET_MASK2_I3C_BUS6	BIT(23)
+#define WDT_RESET_MASK2_I3C_BUS5	BIT(22)
+#define WDT_RESET_MASK2_I3C_BUS4	BIT(21)
+#define WDT_RESET_MASK2_I3C_BUS3	BIT(20)
+#define WDT_RESET_MASK2_I3C_BUS2	BIT(19)
+#define WDT_RESET_MASK2_I3C_BUS1	BIT(18)
+#define WDT_RESET_MASK2_I3C_GLOBAL	BIT(17)
+#define WDT_RESET_MASK2_I2C		BIT(16)
+#define WDT_RESET_MASK2_FSI		BIT(15)
+#define WDT_RESET_MASK2_ADC		BIT(14)
+#define WDT_RESET_MASK2_PWM		BIT(13)
+#define WDT_RESET_MASK2_PECI		BIT(12)
+#define WDT_RESET_MASK2_LPC		BIT(11)
+#define WDT_RESET_MASK2_MDC_MDIO	BIT(10)
+#define WDT_RESET_MASK2_GPIO2		BIT(9)
+#define WDT_RESET_MASK2_JTAG2		BIT(8)
+#define WDT_RESET_MASK2_SD_SDIO2	BIT(7)
+#define WDT_RESET_MASK2_MAC4		BIT(6)
+#define WDT_RESET_MASK2_MAC3		BIT(5)
+#define WDT_RESET_MASK2_SOC		BIT(4)
+#define WDT_RESET_MASK2_SLI2		BIT(3)
+#define WDT_RESET_MASK2_AHB2		BIT(2)
+#define WDT_RESET_MASK2_SPI1_SPI2	BIT(1)
+#define WDT_RESET_MASK2_ARM		BIT(0)
+
+#define WDT_RESET_MASK1_DEFAULT						\
+	(WDT_RESET_MASK1_RVAS | WDT_RESET_MASK1_GPIO1 |			\
+	 WDT_RESET_MASK1_JTAG1 | WDT_RESET_MASK1_SD_SDIO1 |		\
+	 WDT_RESET_MASK1_MAC2 | WDT_RESET_MASK1_MAC1 |			\
+	 WDT_RESET_MASK1_HAC | WDT_RESET_MASK1_VIDEO |			\
+	 WDT_RESET_MASK1_CRT | WDT_RESET_MASK1_GCRT |			\
+	 WDT_RESET_MASK1_USB11_UHCI | WDT_RESET_MASK1_USB_PORTA	|	\
+	 WDT_RESET_MASK1_USB_PORTB | WDT_RESET_MASK1_COPROC |		\
+	 WDT_RESET_MASK1_SOC | WDT_RESET_MASK1_ARM)
+
+#define WDT_RESET_MASK2_DEFAULT						\
+	(WDT_RESET_MASK2_I3C_BUS8 | WDT_RESET_MASK2_I3C_BUS7 |		\
+	 WDT_RESET_MASK2_I3C_BUS6 | WDT_RESET_MASK2_I3C_BUS5 |		\
+	 WDT_RESET_MASK2_I3C_BUS4 | WDT_RESET_MASK2_I3C_BUS3 |		\
+	 WDT_RESET_MASK2_I3C_BUS2 | WDT_RESET_MASK2_I3C_BUS1 |		\
+	 WDT_RESET_MASK2_I3C_GLOBAL | WDT_RESET_MASK2_I2C |		\
+	 WDT_RESET_MASK2_FSI | WDT_RESET_MASK2_ADC |			\
+	 WDT_RESET_MASK2_PWM | WDT_RESET_MASK2_PECI |			\
+	 WDT_RESET_MASK2_LPC | WDT_RESET_MASK2_MDC_MDIO |		\
+	 WDT_RESET_MASK2_GPIO2 | WDT_RESET_MASK2_JTAG2 |		\
+	 WDT_RESET_MASK2_SD_SDIO2 | WDT_RESET_MASK2_MAC4 |		\
+	 WDT_RESET_MASK2_MAC3 | WDT_RESET_MASK2_SOC |			\
+	 WDT_RESET_MASK2_ARM)
+
+#ifndef __ASSEMBLY__
+struct ast2600_wdt {
+	u32 counter_status;
+	u32 counter_reload_val;
+	u32 counter_restart;
+	u32 ctrl;
+	u32 timeout_status;
+	u32 clr_timeout_status;
+	u32 reset_width;
+	u32 reset_mask1;
+	u32 reset_mask2;
+	u32 sw_reset_ctrl;
+	u32 sw_reset_mask1;
+	u32 sw_reset_mask2;
+	u32 sw_reset_disable;
+};
+#endif  /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARCH_WDT_AST2600_H */