Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

26 files changed, 3074 insertions, 0 deletions

diff --git a/roms/u-boot/arch/arm/mach-k3/Kconfig b/roms/u-boot/arch/arm/mach-k3/Kconfig
new file mode 100644
index 000000000..bfbce44bf
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/Kconfig
@@ -0,0 +1,153 @@
+if ARCH_K3
+
+choice
+	prompt "Texas Instruments' K3 based SoC select"
+	optional
+
+config SOC_K3_AM6
+	bool "TI's K3 based AM6 SoC Family Support"
+
+config SOC_K3_J721E
+	bool "TI's K3 based J721E SoC Family Support"
+
+config SOC_K3_AM642
+	bool "TI's K3 based AM642 SoC Family Support"
+
+endchoice
+
+config SYS_SOC
+	default "k3"
+
+config SYS_K3_NON_SECURE_MSRAM_SIZE
+	hex
+	default 0x80000 if SOC_K3_AM6
+	default 0x100000 if SOC_K3_J721E
+	default 0x1c0000 if SOC_K3_AM642
+	help
+	  Describes the total size of the MCU or OCMC MSRAM present on
+	  the SoC in use. This doesn't specify the total size of SPL as
+	  ROM can use some part of this RAM. Once ROM gives control to
+	  SPL then this complete size can be usable.
+
+config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
+	hex
+	default 0x58000 if SOC_K3_AM6
+	default 0xc0000 if SOC_K3_J721E
+	default 0x180000 if SOC_K3_AM642
+	help
+	  Describes the maximum size of the image that ROM can download
+	  from any boot media.
+
+config SYS_K3_MCU_SCRATCHPAD_BASE
+	hex
+	default 0x40280000 if SOC_K3_AM6
+	default 0x40280000 if SOC_K3_J721E
+	help
+	  Describes the base address of MCU Scratchpad RAM.
+
+config SYS_K3_MCU_SCRATCHPAD_SIZE
+	hex
+	default 0x200 if SOC_K3_AM6
+	default 0x200 if SOC_K3_J721E
+	help
+	  Describes the size of MCU Scratchpad RAM.
+
+config SYS_K3_BOOT_PARAM_TABLE_INDEX
+	hex
+	default 0x41c7fbfc if SOC_K3_AM6
+	default 0x41cffbfc if SOC_K3_J721E
+	default 0x701bebfc if SOC_K3_AM642
+	help
+	  Address at which ROM stores the value which determines if SPL
+	  is booted up by primary boot media or secondary boot media.
+
+config SYS_K3_KEY
+	string "Key used to generate x509 certificate"
+	help
+	  This option enables to provide a custom key that can be used for
+	  generating x509 certificate for spl binary. If not needed leave
+	  it blank so that a random key is generated and used.
+
+config SYS_K3_BOOT_CORE_ID
+	int
+	default 16
+
+config K3_EARLY_CONS
+	bool "Activate to allow for an early console during SPL"
+	depends on SPL
+	help
+	  Turn this option on to enable an early console functionality in SPL
+	  before the main console is being brought up. This can be useful in
+	  situations where the main console is dependent on System Firmware
+	  (SYSFW) being up and running, which is usually not the case during
+	  the very early stages of boot. Using this early console functionality
+	  will allow for an alternate serial port to be used to support things
+	  like UART-based boot and early diagnostic messages until the main
+	  console is ready to get activated.
+
+config K3_EARLY_CONS_IDX
+	depends on K3_EARLY_CONS
+	int "Index of serial device to use for SPL early console"
+	default 1
+	help
+	  Use this option to set the index of the serial device to be used
+	  for the early console during SPL execution.
+
+config K3_LOAD_SYSFW
+	bool
+	depends on SPL
+
+config K3_SYSFW_IMAGE_NAME
+	string "File name of SYSFW firmware and configuration blob"
+	depends on K3_LOAD_SYSFW
+	default	"sysfw.itb"
+	help
+	  Filename of the combined System Firmware and configuration image tree
+	  blob to be loaded when booting from a filesystem.
+
+config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
+	hex "MMC sector to load SYSFW firmware and configuration blob from"
+	depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+	default 0x3600
+	help
+	  Address on the MMC to load the combined System Firmware and
+	  configuration image tree blob from, when the MMC is being used
+	  in raw mode. Units: MMC sectors (1 sector = 512 bytes).
+
+config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
+	hex "MMC partition to load SYSFW firmware and configuration blob from"
+	depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+	default 2
+	help
+	  Partition on the MMC to the combined System Firmware and configuration
+	  image tree blob from, when the MMC is being used in raw mode.
+
+config K3_SYSFW_IMAGE_SIZE_MAX
+	int "Amount of memory dynamically allocated for loading SYSFW blob"
+	depends on K3_LOAD_SYSFW
+	default	278000
+	help
+	  Amount of memory (in bytes) reserved through dynamic allocation at
+	  runtime for loading the combined System Firmware and configuration image
+	  tree blob. Keep it as tight as possible, as this directly affects the
+	  overall SPL memory footprint.
+
+config K3_SYSFW_IMAGE_SPI_OFFS
+	hex "SPI offset of SYSFW firmware and configuration blob"
+	depends on K3_LOAD_SYSFW
+	default	0x6C0000
+	help
+	  Offset of the combined System Firmware and configuration image tree
+	  blob to be loaded when booting from a SPI flash memory.
+
+config SYS_K3_SPL_ATF
+	bool "Start Cortex-A from SPL"
+	depends on SPL && CPU_V7R
+	help
+	  Enabling this will try to start Cortex-A (typically with ATF)
+	  after SPL from R5.
+
+source "board/ti/am65x/Kconfig"
+source "board/ti/am64x/Kconfig"
+source "board/ti/j721e/Kconfig"
+endif
diff --git a/roms/u-boot/arch/arm/mach-k3/Makefile b/roms/u-boot/arch/arm/mach-k3/Makefile
new file mode 100644
index 000000000..890d1498d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+#	Lokesh Vutla <lokeshvutla@ti.com>
+
+obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
+obj-$(CONFIG_ARM64) += arm64-mmu.o
+obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
+obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
+obj-$(CONFIG_ARM64) += cache.o
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
+endif
+obj-y += common.o
diff --git a/roms/u-boot/arch/arm/mach-k3/am642_init.c b/roms/u-boot/arch/arm/mach-k3/am642_init.c
new file mode 100644
index 000000000..a433702b4
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/am642_init.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM642: SoC specific initialization
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *	Keerthy <j-keerthy@ti.com>
+ *	Dave Gerlach <d-gerlach@ti.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include <asm/arch/sys_proto.h>
+#include "common.h"
+#include <asm/arch/sys_proto.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+#include <mmc.h>
+#include <dm/root.h>
+
+#if defined(CONFIG_SPL_BUILD)
+
+static void ctrl_mmr_unlock(void)
+{
+	/* Unlock all PADCFG_MMR1 module registers */
+	mmr_unlock(PADCFG_MMR1_BASE, 1);
+
+	/* Unlock all CTRL_MMR0 module registers */
+	mmr_unlock(CTRL_MMR0_BASE, 0);
+	mmr_unlock(CTRL_MMR0_BASE, 1);
+	mmr_unlock(CTRL_MMR0_BASE, 2);
+	mmr_unlock(CTRL_MMR0_BASE, 3);
+	mmr_unlock(CTRL_MMR0_BASE, 5);
+	mmr_unlock(CTRL_MMR0_BASE, 6);
+}
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(".data");
+
+static void store_boot_info_from_rom(void)
+{
+	bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+	memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
+	       sizeof(struct rom_extended_boot_data));
+}
+
+#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
+void k3_mmc_stop_clock(void)
+{
+	if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+		struct mmc *mmc = find_mmc_device(0);
+
+		if (!mmc)
+			return;
+
+		mmc->saved_clock = mmc->clock;
+		mmc_set_clock(mmc, 0, true);
+	}
+}
+
+void k3_mmc_restart_clock(void)
+{
+	if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+		struct mmc *mmc = find_mmc_device(0);
+
+		if (!mmc)
+			return;
+
+		mmc_set_clock(mmc, mmc->saved_clock, false);
+	}
+}
+#else
+void k3_mmc_stop_clock(void) {}
+void k3_mmc_restart_clock(void) {}
+#endif
+
+#ifdef CONFIG_SPL_OF_LIST
+void do_dt_magic(void)
+{
+	int ret, rescan;
+
+	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
+		do_board_detect();
+
+	/*
+	 * Board detection has been done.
+	 * Let us see if another dtb wouldn't be a better match
+	 * for our board
+	 */
+	if (IS_ENABLED(CONFIG_CPU_V7R)) {
+		ret = fdtdec_resetup(&rescan);
+		if (!ret && rescan) {
+			dm_uninit();
+			dm_init_and_scan(true);
+		}
+	}
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+#if defined(CONFIG_K3_LOAD_SYSFW)
+	struct udevice *dev;
+	int ret;
+#endif
+
+#if defined(CONFIG_CPU_V7R)
+	setup_k3_mpu_regions();
+#endif
+
+	/*
+	 * Cannot delay this further as there is a chance that
+	 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+	 */
+	store_boot_info_from_rom();
+
+	ctrl_mmr_unlock();
+
+	/* Init DM early */
+	spl_early_init();
+
+	preloader_console_init();
+
+	do_dt_magic();
+
+#if defined(CONFIG_K3_LOAD_SYSFW)
+	/*
+	 * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
+	 * regardless of the result of pinctrl. Do this without probing the
+	 * device, but instead by searching the device that would request the
+	 * given sequence number if probed. The UART will be used by the system
+	 * firmware (SYSFW) image for various purposes and SYSFW depends on us
+	 * to initialize its pin settings.
+	 */
+	ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
+	if (!ret)
+		pinctrl_select_state(dev, "default");
+
+	/*
+	 * Load, start up, and configure system controller firmware.
+	 * This will determine whether or not ROM has already loaded
+	 * system firmware and if so, will only perform needed config
+	 * and not attempt to load firmware again.
+	 */
+	k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), k3_mmc_stop_clock,
+			k3_mmc_restart_clock);
+#endif
+
+	/* Output System Firmware version info */
+	k3_sysfw_print_ver();
+
+#if defined(CONFIG_K3_AM64_DDRSS)
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret)
+		panic("DRAM init failed: %d\n", ret);
+#endif
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_EMMCBOOT;
+
+	case BOOT_DEVICE_MMC2:
+		return MMCSD_MODE_FS;
+
+	default:
+		return MMCSD_MODE_RAW;
+	}
+}
+
+static u32 __get_backup_bootmedia(u32 main_devstat)
+{
+	u32 bkup_bootmode =
+	    (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
+	    MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
+	u32 bkup_bootmode_cfg =
+	    (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
+	    MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
+
+	switch (bkup_bootmode) {
+	case BACKUP_BOOT_DEVICE_UART:
+		return BOOT_DEVICE_UART;
+
+	case BACKUP_BOOT_DEVICE_USB:
+		return BOOT_DEVICE_USB;
+
+	case BACKUP_BOOT_DEVICE_ETHERNET:
+		return BOOT_DEVICE_ETHERNET;
+
+	case BACKUP_BOOT_DEVICE_MMC:
+		if (bkup_bootmode_cfg)
+			return BOOT_DEVICE_MMC2;
+		return BOOT_DEVICE_MMC1;
+
+	case BACKUP_BOOT_DEVICE_SPI:
+		return BOOT_DEVICE_SPI;
+
+	case BACKUP_BOOT_DEVICE_I2C:
+		return BOOT_DEVICE_I2C;
+	};
+
+	return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 main_devstat)
+{
+	u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+	    MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+	u32 bootmode_cfg =
+	    (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
+	    MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
+
+	switch (bootmode) {
+	case BOOT_DEVICE_OSPI:
+		fallthrough;
+	case BOOT_DEVICE_QSPI:
+		fallthrough;
+	case BOOT_DEVICE_XSPI:
+		fallthrough;
+	case BOOT_DEVICE_SPI:
+		return BOOT_DEVICE_SPI;
+
+	case BOOT_DEVICE_ETHERNET_RGMII:
+		fallthrough;
+	case BOOT_DEVICE_ETHERNET_RMII:
+		return BOOT_DEVICE_ETHERNET;
+
+	case BOOT_DEVICE_EMMC:
+		return BOOT_DEVICE_MMC1;
+
+	case BOOT_DEVICE_MMC:
+		if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
+		     MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
+			return BOOT_DEVICE_MMC2;
+		return BOOT_DEVICE_MMC1;
+
+	case BOOT_DEVICE_NOBOOT:
+		return BOOT_DEVICE_RAM;
+	}
+
+	return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+	if (bootindex == K3_PRIMARY_BOOTMODE)
+		return __get_primary_bootmedia(devstat);
+	else
+		return __get_backup_bootmedia(devstat);
+}
+#endif
+
+#if defined(CONFIG_SYS_K3_SPL_ATF)
+
+#define AM64X_DEV_RTI8			127
+#define AM64X_DEV_RTI9			128
+#define AM64X_DEV_R5FSS0_CORE0		121
+#define AM64X_DEV_R5FSS0_CORE1		122
+
+void release_resources_for_core_shutdown(void)
+{
+	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+	struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
+	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+	int ret;
+	u32 i;
+
+	const u32 put_device_ids[] = {
+		AM64X_DEV_RTI9,
+		AM64X_DEV_RTI8,
+	};
+
+	/* Iterate through list of devices to put (shutdown) */
+	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+		u32 id = put_device_ids[i];
+
+		ret = dev_ops->put_device(ti_sci, id);
+		if (ret)
+			panic("Failed to put device %u (%d)\n", id, ret);
+	}
+
+	const u32 put_core_ids[] = {
+		AM64X_DEV_R5FSS0_CORE1,
+		AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
+	};
+
+	/* Iterate through list of cores to put (shutdown) */
+	for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+		u32 id = put_core_ids[i];
+
+		/*
+		 * Queue up the core shutdown request. Note that this call
+		 * needs to be followed up by an actual invocation of an WFE
+		 * or WFI CPU instruction.
+		 */
+		ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+		if (ret)
+			panic("Failed sending core %u shutdown message (%d)\n",
+			      id, ret);
+	}
+}
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/am6_init.c b/roms/u-boot/arch/arm/mach-k3/am6_init.c
new file mode 100644
index 000000000..425b3f93c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/am6_init.c
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AM6: SoC specific initialization
+ *
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include <asm/arch/sys_proto.h>
+#include "common.h"
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <log.h>
+#include <mmc.h>
+#include <stdlib.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_K3_LOAD_SYSFW
+#ifdef CONFIG_TI_SECURE_DEVICE
+struct fwl_data main_cbass_fwls[] = {
+	{ "MMCSD1_CFG", 2057, 1 },
+	{ "MMCSD0_CFG", 2058, 1 },
+	{ "USB3SS0_SLV0", 2176, 2 },
+	{ "PCIE0_SLV", 2336, 8 },
+	{ "PCIE1_SLV", 2337, 8 },
+	{ "PCIE0_CFG", 2688, 1 },
+	{ "PCIE1_CFG", 2689, 1 },
+}, mcu_cbass_fwls[] = {
+	{ "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
+	{ "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
+	{ "MCU_FSS0_S1", 1033, 8 },
+	{ "MCU_FSS0_S0", 1036, 8 },
+	{ "MCU_CPSW0", 1220, 1 },
+};
+#endif
+#endif
+
+static void ctrl_mmr_unlock(void)
+{
+	/* Unlock all WKUP_CTRL_MMR0 module registers */
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+	/* Unlock all MCU_CTRL_MMR0 module registers */
+	mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+	mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+	mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+	mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
+
+	/* Unlock all CTRL_MMR0 module registers */
+	mmr_unlock(CTRL_MMR0_BASE, 0);
+	mmr_unlock(CTRL_MMR0_BASE, 1);
+	mmr_unlock(CTRL_MMR0_BASE, 2);
+	mmr_unlock(CTRL_MMR0_BASE, 3);
+	mmr_unlock(CTRL_MMR0_BASE, 6);
+	mmr_unlock(CTRL_MMR0_BASE, 7);
+}
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+
+static void store_boot_index_from_rom(void)
+{
+	bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+}
+
+#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
+void k3_mmc_stop_clock(void)
+{
+	if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+		struct mmc *mmc = find_mmc_device(0);
+
+		if (!mmc)
+			return;
+
+		mmc->saved_clock = mmc->clock;
+		mmc_set_clock(mmc, 0, true);
+	}
+}
+
+void k3_mmc_restart_clock(void)
+{
+	if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+		struct mmc *mmc = find_mmc_device(0);
+
+		if (!mmc)
+			return;
+
+		mmc_set_clock(mmc, mmc->saved_clock, false);
+	}
+}
+#else
+void k3_mmc_stop_clock(void) {}
+void k3_mmc_restart_clock(void) {}
+#endif
+#if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
+#define CTRLMMR_SERDES0_CTRL	0x00104080
+#define PCIE_LANE0		0x1
+static int fixup_usb_boot(void)
+{
+	int ret;
+
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_USB:
+		/*
+		 * If bootmode is Host bootmode, fixup the dr_mode to host
+		 * before the dwc3 bind takes place
+		 */
+		ret = fdt_find_and_setprop((void *)gd->fdt_blob,
+				"/interconnect@100000/dwc3@4000000/usb@10000",
+				"dr_mode", "host", 11, 0);
+		if (ret)
+			printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
+			       ret);
+		fallthrough;
+	case BOOT_DEVICE_DFU:
+		/*
+		 * The serdes mux between PCIe and USB3 needs to be set to PCIe for
+		 * accessing the interface at USB 2.0
+		 */
+		writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+	return fixup_usb_boot();
+}
+#endif
+void board_init_f(ulong dummy)
+{
+#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
+	struct udevice *dev;
+	size_t pool_size;
+	void *pool_addr;
+	int ret;
+#endif
+	/*
+	 * Cannot delay this further as there is a chance that
+	 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+	 */
+	store_boot_index_from_rom();
+
+	/* Make all control module registers accessible */
+	ctrl_mmr_unlock();
+
+#ifdef CONFIG_CPU_V7R
+	disable_linefill_optimization();
+	setup_k3_mpu_regions();
+#endif
+
+	/* Init DM early in-order to invoke system controller */
+	spl_early_init();
+
+#ifdef CONFIG_K3_EARLY_CONS
+	/*
+	 * Allow establishing an early console as required for example when
+	 * doing a UART-based boot. Note that this console may not "survive"
+	 * through a SYSFW PM-init step and will need a re-init in some way
+	 * due to changing module clock frequencies.
+	 */
+	early_console_init();
+#endif
+
+#ifdef CONFIG_K3_LOAD_SYSFW
+	/*
+	 * Initialize an early full malloc environment. Do so by allocating a
+	 * new malloc area inside the currently active pre-relocation "first"
+	 * malloc pool of which we use all that's left.
+	 */
+	pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
+	pool_addr = malloc(pool_size);
+	if (!pool_addr)
+		panic("ERROR: Can't allocate full malloc pool!\n");
+
+	mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+	debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx bytes\n",
+	      __func__, (unsigned long)pool_addr, (unsigned long)pool_size);
+	/*
+	 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
+	 * regardless of the result of pinctrl. Do this without probing the
+	 * device, but instead by searching the device that would request the
+	 * given sequence number if probed. The UART will be used by the system
+	 * firmware (SYSFW) image for various purposes and SYSFW depends on us
+	 * to initialize its pin settings.
+	 */
+	ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
+	if (!ret)
+		pinctrl_select_state(dev, "default");
+
+	/*
+	 * Load, start up, and configure system controller firmware while
+	 * also populating the SYSFW post-PM configuration callback hook.
+	 */
+	k3_sysfw_loader(false, k3_mmc_stop_clock, k3_mmc_restart_clock);
+
+	/* Prepare console output */
+	preloader_console_init();
+
+	/* Disable ROM configured firewalls right after loading sysfw */
+#ifdef CONFIG_TI_SECURE_DEVICE
+	remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
+	remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
+#endif
+#else
+	/* Prepare console output */
+	preloader_console_init();
+#endif
+
+	/* Output System Firmware version info */
+	k3_sysfw_print_ver();
+
+	/* Perform EEPROM-based board detection */
+	do_board_detect();
+
+#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
+	ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
+					  &dev);
+	if (ret)
+		printf("AVS init failed: %d\n", ret);
+#endif
+
+#ifdef CONFIG_K3_AM654_DDRSS
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret)
+		panic("DRAM init failed: %d\n", ret);
+#endif
+	spl_enable_dcache();
+}
+
+u32 spl_mmc_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SUPPORT_EMMC_BOOT)
+	u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+	u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
+			CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
+
+	/* eMMC boot0 mode is only supported for primary boot */
+	if (bootindex == K3_PRIMARY_BOOTMODE &&
+	    bootmode == BOOT_DEVICE_MMC1)
+		return MMCSD_MODE_EMMCBOOT;
+#endif
+
+	/* Everything else use filesystem if available */
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+	return MMCSD_MODE_FS;
+#else
+	return MMCSD_MODE_RAW;
+#endif
+}
+
+static u32 __get_backup_bootmedia(u32 devstat)
+{
+	u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
+			CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
+
+	switch (bkup_boot) {
+	case BACKUP_BOOT_DEVICE_USB:
+		return BOOT_DEVICE_USB;
+	case BACKUP_BOOT_DEVICE_UART:
+		return BOOT_DEVICE_UART;
+	case BACKUP_BOOT_DEVICE_ETHERNET:
+		return BOOT_DEVICE_ETHERNET;
+	case BACKUP_BOOT_DEVICE_MMC2:
+	{
+		u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
+			    CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
+		if (port == 0x0)
+			return BOOT_DEVICE_MMC1;
+		return BOOT_DEVICE_MMC2;
+	}
+	case BACKUP_BOOT_DEVICE_SPI:
+		return BOOT_DEVICE_SPI;
+	case BACKUP_BOOT_DEVICE_HYPERFLASH:
+		return BOOT_DEVICE_HYPERFLASH;
+	case BACKUP_BOOT_DEVICE_I2C:
+		return BOOT_DEVICE_I2C;
+	};
+
+	return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 devstat)
+{
+	u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
+			CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
+
+	if (bootmode == BOOT_DEVICE_OSPI || bootmode ==	BOOT_DEVICE_QSPI)
+		bootmode = BOOT_DEVICE_SPI;
+
+	if (bootmode == BOOT_DEVICE_MMC2) {
+		u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
+			    CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
+		if (port == 0x0)
+			bootmode = BOOT_DEVICE_MMC1;
+	} else if (bootmode == BOOT_DEVICE_MMC1) {
+		u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
+			    CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
+		if (port == 0x1)
+			bootmode = BOOT_DEVICE_MMC2;
+	} else if (bootmode == BOOT_DEVICE_DFU) {
+		u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
+			    CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
+		if (mode == 0x2)
+			bootmode = BOOT_DEVICE_USB;
+	}
+
+	return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+	if (bootindex == K3_PRIMARY_BOOTMODE)
+		return __get_primary_bootmedia(devstat);
+	else
+		return __get_backup_bootmedia(devstat);
+}
+#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+
+#define AM6_DEV_MCU_RTI0			134
+#define AM6_DEV_MCU_RTI1			135
+#define AM6_DEV_MCU_ARMSS0_CPU0			159
+#define AM6_DEV_MCU_ARMSS0_CPU1			245
+
+void release_resources_for_core_shutdown(void)
+{
+	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+	struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
+	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+	int ret;
+	u32 i;
+
+	const u32 put_device_ids[] = {
+		AM6_DEV_MCU_RTI0,
+		AM6_DEV_MCU_RTI1,
+	};
+
+	/* Iterate through list of devices to put (shutdown) */
+	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+		u32 id = put_device_ids[i];
+
+		ret = dev_ops->put_device(ti_sci, id);
+		if (ret)
+			panic("Failed to put device %u (%d)\n", id, ret);
+	}
+
+	const u32 put_core_ids[] = {
+		AM6_DEV_MCU_ARMSS0_CPU1,
+		AM6_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
+	};
+
+	/* Iterate through list of cores to put (shutdown) */
+	for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+		u32 id = put_core_ids[i];
+
+		/*
+		 * Queue up the core shutdown request. Note that this call
+		 * needs to be followed up by an actual invocation of an WFE
+		 * or WFI CPU instruction.
+		 */
+		ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+		if (ret)
+			panic("Failed sending core %u shutdown message (%d)\n",
+			      id, ret);
+	}
+}
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/arm64-mmu.c b/roms/u-boot/arch/arm/mach-k3/arm64-mmu.c
new file mode 100644
index 000000000..94242e1e5
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/arm64-mmu.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier:     GPL-2.0+
+/*
+ * K3: ARM64 MMU setup
+ *
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ *	Suman Anna <s-anna@ti.com>
+ * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
+ *
+ */
+
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+#ifdef CONFIG_SOC_K3_AM6
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 5)
+
+/* ToDo: Add 64bit IO */
+struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xa0000000UL,
+		.phys = 0xa0000000UL,
+		.size = 0x02100000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xa2100000UL,
+		.phys = 0xa2100000UL,
+		.size = 0x5df00000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x880000000UL,
+		.phys = 0x880000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x500000000UL,
+		.phys = 0x500000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = am654_mem_map;
+#endif /* CONFIG_SOC_K3_AM6 */
+
+#ifdef CONFIG_SOC_K3_J721E
+
+#ifdef CONFIG_TARGET_J721E_A72_EVM
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 6)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xa0000000UL,
+		.phys = 0xa0000000UL,
+		.size = 0x1bc00000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_NON_SHARE
+	}, {
+		.virt = 0xbbc00000UL,
+		.phys = 0xbbc00000UL,
+		.size = 0x44400000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x880000000UL,
+		.phys = 0x880000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x500000000UL,
+		.phys = 0x500000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x4d80000000UL,
+		.phys = 0x4d80000000UL,
+		.size = 0x0002000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = j721e_mem_map;
+#endif /* CONFIG_TARGET_J721E_A72_EVM */
+
+#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 5)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xa0000000UL,
+		.phys = 0xa0000000UL,
+		.size = 0x04800000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_NON_SHARE
+	}, {
+		.virt = 0xa4800000UL,
+		.phys = 0xa4800000UL,
+		.size = 0x5b800000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x880000000UL,
+		.phys = 0x880000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x500000000UL,
+		.phys = 0x500000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = j7200_mem_map;
+#endif /* CONFIG_TARGET_J7200_A72_EVM */
+
+#endif /* CONFIG_SOC_K3_J721E */
+
+#ifdef CONFIG_SOC_K3_AM642
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 3)
+
+/* ToDo: Add 64bit IO */
+struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x880000000UL,
+		.phys = 0x880000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x500000000UL,
+		.phys = 0x500000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = am64_mem_map;
+#endif /* CONFIG_SOC_K3_AM642 */
diff --git a/roms/u-boot/arch/arm/mach-k3/cache.S b/roms/u-boot/arch/arm/mach-k3/cache.S
new file mode 100644
index 000000000..a5717ea20
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/cache.S
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andrew F. Davis <afd@ti.com>
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#if defined(CONFIG_SPL_BUILD)
+ENTRY(__asm_invalidate_l3_dcache)
+	/* Invalidate SPL address range */
+	mov x0, #CONFIG_SPL_TEXT_BASE
+	add x1, x0, #CONFIG_SPL_MAX_SIZE
+	b __asm_flush_dcache_range
+ENDPROC(__asm_invalidate_l3_dcache)
+
+ENTRY(__asm_flush_l3_dcache)
+	/* Flush SPL address range */
+	mov x0, #CONFIG_SPL_TEXT_BASE
+	add x1, x0, #CONFIG_SPL_MAX_SIZE
+	b __asm_flush_dcache_range
+ENDPROC(__asm_flush_l3_dcache)
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/common.c b/roms/u-boot/arch/arm/mach-k3/common.c
new file mode 100644
index 000000000..9191f686f
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/common.c
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K3: Common Architecture initialization
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include "common.h"
+#include <dm.h>
+#include <remoteproc.h>
+#include <asm/cache.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <fdt_support.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <fs_loader.h>
+#include <fs.h>
+#include <env.h>
+#include <elf.h>
+#include <soc.h>
+
+struct ti_sci_handle *get_ti_sci_handle(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
+					  DM_DRIVER_GET(ti_sci), &dev);
+	if (ret)
+		panic("Failed to get SYSFW (%d)\n", ret);
+
+	return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
+}
+
+void k3_sysfw_print_ver(void)
+{
+	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+	char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
+
+	/*
+	 * Output System Firmware version info. Note that since the
+	 * 'firmware_description' field is not guaranteed to be zero-
+	 * terminated we manually add a \0 terminator if needed. Further
+	 * note that we intentionally no longer rely on the extended
+	 * printf() formatter '%.*s' to not having to require a more
+	 * full-featured printf() implementation.
+	 */
+	strncpy(fw_desc, ti_sci->version.firmware_description,
+		sizeof(ti_sci->version.firmware_description));
+	fw_desc[sizeof(fw_desc) - 1] = '\0';
+
+	printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
+	       ti_sci->version.abi_major, ti_sci->version.abi_minor,
+	       ti_sci->version.firmware_revision, fw_desc);
+}
+
+void mmr_unlock(phys_addr_t base, u32 partition)
+{
+	/* Translate the base address */
+	phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
+
+	/* Unlock the requested partition if locked using two-step sequence */
+	writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
+	writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
+}
+
+bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data)
+{
+	if (strncmp(data->header, K3_ROM_BOOT_HEADER_MAGIC, 7))
+		return false;
+
+	return data->num_components > 1;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_K3_EARLY_CONS
+int early_console_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
+				       &dev);
+	if (ret) {
+		printf("Error getting serial dev for early console! (%d)\n",
+		       ret);
+		return ret;
+	}
+
+	gd->cur_serial_dev = dev;
+	gd->flags |= GD_FLG_SERIAL_READY;
+	gd->have_console = 1;
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+
+void init_env(void)
+{
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	char *part;
+
+	env_init();
+	env_relocate();
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC2:
+		part = env_get("bootpart");
+		env_set("storage_interface", "mmc");
+		env_set("fw_dev_part", part);
+		break;
+	case BOOT_DEVICE_SPI:
+		env_set("storage_interface", "ubi");
+		env_set("fw_ubi_mtdpart", "UBI");
+		env_set("fw_ubi_volume", "UBI0");
+		break;
+	default:
+		printf("%s from device %u not supported!\n",
+		       __func__, spl_boot_device());
+		return;
+	}
+#endif
+}
+
+#ifdef CONFIG_FS_LOADER
+int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
+{
+	struct udevice *fsdev;
+	char *name = NULL;
+	int size = 0;
+
+	*loadaddr = 0;
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC2:
+		name = env_get(name_fw);
+		*loadaddr = env_get_hex(name_loadaddr, *loadaddr);
+		break;
+	default:
+		printf("Loading rproc fw image from device %u not supported!\n",
+		       spl_boot_device());
+		return 0;
+	}
+#endif
+	if (!*loadaddr)
+		return 0;
+
+	if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
+		size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr,
+						 0, 0);
+	}
+
+	return size;
+}
+#else
+int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
+{
+	return 0;
+}
+#endif
+
+__weak void start_non_linux_remote_cores(void)
+{
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	typedef void __noreturn (*image_entry_noargs_t)(void);
+	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+	u32 loadaddr = 0;
+	int ret, size;
+
+	/* Release all the exclusive devices held by SPL before starting ATF */
+	ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
+
+	ret = rproc_init();
+	if (ret)
+		panic("rproc failed to be initialized (%d)\n", ret);
+
+	init_env();
+	start_non_linux_remote_cores();
+	size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
+			     &loadaddr);
+
+
+	/*
+	 * It is assumed that remoteproc device 1 is the corresponding
+	 * Cortex-A core which runs ATF. Make sure DT reflects the same.
+	 */
+	ret = rproc_load(1, spl_image->entry_point, 0x200);
+	if (ret)
+		panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
+
+	/* Add an extra newline to differentiate the ATF logs from SPL */
+	printf("Starting ATF on ARM64 core...\n\n");
+
+	ret = rproc_start(1);
+	if (ret)
+		panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
+	if (!(size > 0 && valid_elf_image(loadaddr))) {
+		debug("Shutting down...\n");
+		release_resources_for_core_shutdown();
+
+		while (1)
+			asm volatile("wfe");
+	}
+
+	image_entry_noargs_t image_entry =
+		(image_entry_noargs_t)load_elf_image_phdr(loadaddr);
+
+	image_entry();
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT)
+int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
+{
+	u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
+	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+	int ret, node, subnode, len, prev_node;
+	u32 range[4], addr, size;
+	const fdt32_t *sub_reg;
+
+	ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
+	msmc_size = msmc_end - msmc_start + 1;
+	debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
+	      msmc_start, msmc_size);
+
+	/* find or create "msmc_sram node */
+	ret = fdt_path_offset(blob, parent_path);
+	if (ret < 0)
+		return ret;
+
+	node = fdt_find_or_add_subnode(blob, ret, node_name);
+	if (node < 0)
+		return node;
+
+	ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
+	if (ret < 0)
+		return ret;
+
+	reg[0] = cpu_to_fdt64(msmc_start);
+	reg[1] = cpu_to_fdt64(msmc_size);
+	ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
+	if (ret < 0)
+		return ret;
+
+	fdt_setprop_cell(blob, node, "#address-cells", 1);
+	fdt_setprop_cell(blob, node, "#size-cells", 1);
+
+	range[0] = 0;
+	range[1] = cpu_to_fdt32(msmc_start >> 32);
+	range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
+	range[3] = cpu_to_fdt32(msmc_size);
+	ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
+	if (ret < 0)
+		return ret;
+
+	subnode = fdt_first_subnode(blob, node);
+	prev_node = 0;
+
+	/* Look for invalid subnodes and delete them */
+	while (subnode >= 0) {
+		sub_reg = fdt_getprop(blob, subnode, "reg", &len);
+		addr = fdt_read_number(sub_reg, 1);
+		sub_reg++;
+		size = fdt_read_number(sub_reg, 1);
+		debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
+		      subnode, addr, size);
+		if (addr + size > msmc_size ||
+		    !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
+		    !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
+			fdt_del_node(blob, subnode);
+			debug("%s: deleting subnode %d\n", __func__, subnode);
+			if (!prev_node)
+				subnode = fdt_first_subnode(blob, node);
+			else
+				subnode = fdt_next_subnode(blob, prev_node);
+		} else {
+			prev_node = subnode;
+			subnode = fdt_next_subnode(blob, prev_node);
+		}
+	}
+
+	return 0;
+}
+
+int fdt_disable_node(void *blob, char *node_path)
+{
+	int offs;
+	int ret;
+
+	offs = fdt_path_offset(blob, node_path);
+	if (offs < 0) {
+		printf("Node %s not found.\n", node_path);
+		return offs;
+	}
+	ret = fdt_setprop_string(blob, offs, "status", "disabled");
+	if (ret < 0) {
+		printf("Could not add status property to node %s: %s\n",
+		       node_path, fdt_strerror(ret));
+		return ret;
+	}
+	return 0;
+}
+
+#endif
+
+#ifndef CONFIG_SYSRESET
+void reset_cpu(void)
+{
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	struct udevice *soc;
+	char name[64];
+	int ret;
+
+	printf("SoC:   ");
+
+	ret = soc_get(&soc);
+	if (ret) {
+		printf("UNKNOWN\n");
+		return 0;
+	}
+
+	ret = soc_get_family(soc, name, 64);
+	if (!ret) {
+		printf("%s ", name);
+	}
+
+	ret = soc_get_revision(soc, name, 64);
+	if (!ret) {
+		printf("%s\n", name);
+	}
+
+	return 0;
+}
+#endif
+
+bool soc_is_j721e(void)
+{
+	u32 soc;
+
+	soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
+		JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
+
+	return soc == J721E;
+}
+
+bool soc_is_j7200(void)
+{
+	u32 soc;
+
+	soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
+		JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
+
+	return soc == J7200;
+}
+
+#ifdef CONFIG_ARM64
+void board_prep_linux(bootm_headers_t *images)
+{
+	debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
+	      images->os.start, images->os.end);
+	__asm_flush_dcache_range(images->os.start,
+				 ROUND(images->os.end,
+				       CONFIG_SYS_CACHELINE_SIZE));
+}
+#endif
+
+#ifdef CONFIG_CPU_V7R
+void disable_linefill_optimization(void)
+{
+	u32 actlr;
+
+	/*
+	 * On K3 devices there are 2 conditions where R5F can deadlock:
+	 * 1.When software is performing series of store operations to
+	 *   cacheable write back/write allocate memory region and later
+	 *   on software execute barrier operation (DSB or DMB). R5F may
+	 *   hang at the barrier instruction.
+	 * 2.When software is performing a mix of load and store operations
+	 *   within a tight loop and store operations are all writing to
+	 *   cacheable write back/write allocates memory regions, R5F may
+	 *   hang at one of the load instruction.
+	 *
+	 * To avoid the above two conditions disable linefill optimization
+	 * inside Cortex R5F.
+	 */
+	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
+	actlr |= (1 << 13); /* Set DLFO bit  */
+	asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
+}
+#endif
+
+void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
+{
+	struct ti_sci_msg_fwl_region region;
+	struct ti_sci_fwl_ops *fwl_ops;
+	struct ti_sci_handle *ti_sci;
+	size_t i, j;
+
+	ti_sci = get_ti_sci_handle();
+	fwl_ops = &ti_sci->ops.fwl_ops;
+	for (i = 0; i < fwl_data_size; i++) {
+		for (j = 0; j <  fwl_data[i].regions; j++) {
+			region.fwl_id = fwl_data[i].fwl_id;
+			region.region = j;
+			region.n_permission_regs = 3;
+
+			fwl_ops->get_fwl_region(ti_sci, &region);
+
+			if (region.control != 0) {
+				pr_debug("Attempting to disable firewall %5d (%25s)\n",
+					 region.fwl_id, fwl_data[i].name);
+				region.control = 0;
+
+				if (fwl_ops->set_fwl_region(ti_sci, &region))
+					pr_err("Could not disable firewall %5d (%25s)\n",
+					       region.fwl_id, fwl_data[i].name);
+			}
+		}
+	}
+}
+
+void spl_enable_dcache(void)
+{
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
+
+	dram_init_banksize();
+
+	/* reserve TLB table */
+	gd->arch.tlb_size = PGTABLE_SIZE;
+
+	ram_top += get_effective_memsize();
+	/* keep ram_top in the 32-bit address space */
+	if (ram_top >= 0x100000000)
+		ram_top = (phys_addr_t) 0x100000000;
+
+	gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
+	debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
+	      gd->arch.tlb_addr + gd->arch.tlb_size);
+
+	dcache_enable();
+#endif
+}
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+void spl_board_prepare_for_boot(void)
+{
+	dcache_disable();
+}
+
+void spl_board_prepare_for_linux(void)
+{
+	dcache_disable();
+}
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/common.h b/roms/u-boot/arch/arm/mach-k3/common.h
new file mode 100644
index 000000000..a6dbc7808
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/common.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: Architecture common definitions
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <asm/armv7_mpu.h>
+#include <asm/hardware.h>
+
+#define J721E  0xbb64
+#define J7200  0xbb6d
+
+struct fwl_data {
+	const char *name;
+	u16 fwl_id;
+	u16 regions;
+};
+
+void setup_k3_mpu_regions(void);
+int early_console_init(void);
+void disable_linefill_optimization(void);
+void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
+void start_non_linux_remote_cores(void);
+int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
+void k3_sysfw_print_ver(void);
+void spl_enable_dcache(void);
+void mmr_unlock(phys_addr_t base, u32 partition);
+bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
diff --git a/roms/u-boot/arch/arm/mach-k3/config.mk b/roms/u-boot/arch/arm/mach-k3/config.mk
new file mode 100644
index 000000000..41fee2b5a
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/config.mk
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+#	Lokesh Vutla <lokeshvutla@ti.com>
+
+ifdef CONFIG_SPL_BUILD
+
+# Openssl is required to generate x509 certificate.
+# Error out if openssl is not available.
+ifeq ($(shell which openssl),)
+$(error "No openssl in $(PATH), consider installing openssl")
+endif
+
+IMAGE_SIZE= $(shell cat $(obj)/u-boot-spl.bin | wc -c)
+MAX_SIZE= $(shell printf "%d" $(CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE))
+
+ifeq ($(CONFIG_SYS_K3_KEY), "")
+KEY=""
+# On HS use real key or warn if not available
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/keys/custMpk.pem),)
+KEY=$(TI_SECURE_DEV_PKG)/keys/custMpk.pem
+else
+$(warning "WARNING: signing key not found. Random key will NOT work on HS hardware!")
+endif
+endif
+else
+KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY))
+endif
+
+# tiboot3.bin is mandated by ROM and ROM only supports R5 boot.
+# So restrict tiboot3.bin creation for CPU_V7R.
+ifdef CONFIG_CPU_V7R
+image_check: $(obj)/u-boot-spl.bin FORCE
+	@if [ $(IMAGE_SIZE) -gt $(MAX_SIZE) ]; then			    \
+		echo "===============================================" >&2; \
+		echo "ERROR: Final Image too big. " >&2;		    \
+		echo "$< size = $(IMAGE_SIZE), max size = $(MAX_SIZE)" >&2; \
+		echo "===============================================" >&2; \
+		exit 1;							    \
+	fi
+
+tiboot3.bin: image_check FORCE
+	$(srctree)/tools/k3_gen_x509_cert.sh -c 16 -b $(obj)/u-boot-spl.bin \
+				-o $@ -l $(CONFIG_SPL_TEXT_BASE) -k $(KEY)
+
+INPUTS-y	+= tiboot3.bin
+endif
+
+ifdef CONFIG_ARM64
+
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+SPL_ITS := u-boot-spl-k3_HS.its
+$(SPL_ITS): export IS_HS=1
+INPUTS-y	+= tispl.bin_HS
+else
+SPL_ITS := u-boot-spl-k3.its
+INPUTS-y	+= tispl.bin
+endif
+
+ifeq ($(CONFIG_SPL_OF_LIST),)
+LIST_OF_DTB := $(CONFIG_DEFAULT_DEVICE_TREE)
+else
+LIST_OF_DTB := $(CONFIG_SPL_OF_LIST)
+endif
+
+quiet_cmd_k3_mkits = MKITS   $@
+cmd_k3_mkits = \
+	$(srctree)/tools/k3_fit_atf.sh \
+	$(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@
+
+$(SPL_ITS): FORCE
+	$(call cmd,k3_mkits)
+endif
+
+else
+
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+INPUTS-y	+= u-boot.img_HS
+else
+INPUTS-y	+= u-boot.img
+endif
+endif
+
+include $(srctree)/arch/arm/mach-k3/config_secure.mk
diff --git a/roms/u-boot/arch/arm/mach-k3/config_secure.mk b/roms/u-boot/arch/arm/mach-k3/config_secure.mk
new file mode 100644
index 000000000..6d63c5766
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/config_secure.mk
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2018 Texas Instruments, Incorporated - http://www.ti.com/
+#	Andrew F. Davis <afd@ti.com>
+
+quiet_cmd_k3secureimg = SECURE  $@
+ifneq ($(TI_SECURE_DEV_PKG),)
+ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),)
+cmd_k3secureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \
+	$< $@ \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
+else
+cmd_k3secureimg = echo "WARNING:" \
+	"$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \
+	"$@ was NOT secured!"; cp $< $@
+endif
+else
+cmd_k3secureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
+	"variable must be defined for TI secure devices." \
+	"$@ was NOT secured!"; cp $< $@
+endif
+
+%.dtb_HS: %.dtb FORCE
+	$(call if_changed,k3secureimg)
+
+$(obj)/u-boot-spl-nodtb.bin_HS: $(obj)/u-boot-spl-nodtb.bin FORCE
+	$(call if_changed,k3secureimg)
+
+tispl.bin_HS: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$(subst ",,$(CONFIG_SPL_OF_LIST))) $(SPL_ITS) FORCE
+	$(call if_changed,mkfitimage)
+
+MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
+	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
+
+OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+$(OF_LIST_TARGETS): dtbs
+
+u-boot-nodtb.bin_HS: u-boot-nodtb.bin FORCE
+	$(call if_changed,k3secureimg)
+
+u-boot.img_HS: u-boot-nodtb.bin_HS u-boot.img $(patsubst %.dtb,%.dtb_HS,$(OF_LIST_TARGETS)) FORCE
+	$(call if_changed,mkimage)
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/am64_hardware.h b/roms/u-boot/arch/arm/mach-k3/include/mach/am64_hardware.h
new file mode 100644
index 000000000..c368aa7e6
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: AM64 SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#ifndef __ASM_ARCH_AM64_HARDWARE_H
+#define __ASM_ARCH_AM64_HARDWARE_H
+
+#include <config.h>
+
+#define CTRL_MMR0_BASE					0x43000000
+#define CTRLMMR_MAIN_DEVSTAT				(CTRL_MMR0_BASE + 0x30)
+
+#define PADCFG_MMR1_BASE				0xf0000
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK		0x00000078
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT		3
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK		0x00000380
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT		7
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK		0x00001c00
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT		10
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK		0x00002000
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT		13
+
+/* After the cfg mask and shifts have been applied */
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT		2
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK		0x04
+
+/*
+ * The CTRL_MMR and PADCFG_MMR memory space is divided into several
+ * equally-spaced partitions, so defining the partition size allows us to
+ * determine register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE			0x4000
+
+/*
+ * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0				0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL			0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK		BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT		0
+#define CTRLMMR_LOCK_KICK1				0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL			0xd172bc5a
+
+#define ROM_ENTENDED_BOOT_DATA_INFO			0x701beb00
+
+/* Use Last 1K as Scratch pad */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START		0x701bfc00
+
+#endif /* __ASM_ARCH_DRA8_HARDWARE_H */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/am64_spl.h b/roms/u-boot/arch/arm/mach-k3/include/mach/am64_spl.h
new file mode 100644
index 000000000..36826cfc4
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/am64_spl.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *	Keerthy <j-keerthy@ti.com>
+ */
+#ifndef _ASM_ARCH_AM64_SPL_H_
+#define _ASM_ARCH_AM64_SPL_H_
+
+/* Primary BootMode devices */
+#define BOOT_DEVICE_RAM			0x00
+#define BOOT_DEVICE_OSPI		0x01
+#define BOOT_DEVICE_QSPI		0x02
+#define BOOT_DEVICE_SPI			0x03
+#define BOOT_DEVICE_ETHERNET		0x04
+#define BOOT_DEVICE_ETHERNET_RGMII	0x04
+#define BOOT_DEVICE_ETHERNET_RMII	0x05
+#define BOOT_DEVICE_I2C			0x06
+#define BOOT_DEVICE_UART		0x07
+#define BOOT_DEVICE_MMC			0x08
+#define BOOT_DEVICE_EMMC		0x09
+
+#define BOOT_DEVICE_USB			0x0A
+#define BOOT_DEVICE_GPMC_NOR		0x0C
+#define BOOT_DEVICE_PCIE		0x0D
+#define BOOT_DEVICE_XSPI		0x0E
+
+#define BOOT_DEVICE_NOBOOT		0x0F
+
+#define BOOT_DEVICE_MMC2		0x08
+#define BOOT_DEVICE_MMC1		0x09
+/* INVALID */
+#define BOOT_DEVICE_MMC2_2		0x1F
+
+/* Backup BootMode devices */
+#define BACKUP_BOOT_DEVICE_USB		0x01
+#define BACKUP_BOOT_DEVICE_UART		0x03
+#define BACKUP_BOOT_DEVICE_ETHERNET	0x04
+#define BACKUP_BOOT_DEVICE_MMC		0x05
+#define BACKUP_BOOT_DEVICE_SPI		0x06
+#define BACKUP_BOOT_DEVICE_I2C		0x07
+
+#define K3_PRIMARY_BOOTMODE		0x0
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/am6_hardware.h b/roms/u-boot/arch/arm/mach-k3/include/mach/am6_hardware.h
new file mode 100644
index 000000000..1908a13f0
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: AM6 SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_AM6_HARDWARE_H
+#define __ASM_ARCH_AM6_HARDWARE_H
+
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define CTRL_MMR0_BASE					0x00100000
+#define CTRLMMR_MAIN_DEVSTAT				(CTRL_MMR0_BASE + 0x30)
+
+#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK		GENMASK(3, 0)
+#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT		0
+#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK		GENMASK(6, 4)
+#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT	4
+#define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK		GENMASK(12, 12)
+#define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT		12
+#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK		GENMASK(14, 14)
+#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT		14
+#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK		GENMASK(17, 17)
+#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT	12
+#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT		9
+#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK		GENMASK(10, 9)
+
+#define WKUP_CTRL_MMR0_BASE				0x43000000
+#define MCU_CTRL_MMR0_BASE				0x40f00000
+
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE			0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
+ * shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0				0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL			0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK		BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT		0
+#define CTRLMMR_LOCK_KICK1				0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL			0xd172bc5a
+
+/* MCU SCRATCHPAD usage */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
+
+#endif /* __ASM_ARCH_AM6_HARDWARE_H */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/am6_spl.h b/roms/u-boot/arch/arm/mach-k3/include/mach/am6_spl.h
new file mode 100644
index 000000000..61e038092
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/am6_spl.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _ASM_ARCH_AM6_SPL_H_
+#define _ASM_ARCH_AM6_SPL_H_
+
+#define BOOT_DEVICE_RAM			0x00
+#define BOOT_DEVICE_OSPI		0x01
+#define BOOT_DEVICE_QSPI		0x02
+#define BOOT_DEVICE_HYPERFLASH		0x03
+#define BOOT_DEVICE_SPI			0x04
+#define BOOT_DEVICE_I2C			0x05
+#define BOOT_DEVICE_MMC2		0x06
+#define BOOT_DEVICE_ETHERNET		0x07
+#define BOOT_DEVICE_DFU			0x08
+#define BOOT_DEVICE_USB			0x408
+#define BOOT_DEVICE_PCIE		0x09
+#define BOOT_DEVICE_UART		0x0a
+#define BOOT_DEVICE_NAND		0x0c
+#define BOOT_DEVICE_MMC1		0x0d
+#define BOOT_DEVICE_MMC2_2		0x0e
+
+#define BACKUP_BOOT_DEVICE_RAM		0x0
+#define BACKUP_BOOT_DEVICE_USB		0x1
+#define BACKUP_BOOT_DEVICE_UART		0x2
+#define BACKUP_BOOT_DEVICE_ETHERNET	0x3
+#define BACKUP_BOOT_DEVICE_MMC2		0x4
+#define BACKUP_BOOT_DEVICE_SPI		0x5
+#define BACKUP_BOOT_DEVICE_HYPERFLASH	0x6
+#define BACKUP_BOOT_DEVICE_I2C		0x7
+
+#define K3_PRIMARY_BOOTMODE		0x0
+#define K3_BACKUP_BOOTMODE		0x1
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/clock.h b/roms/u-boot/arch/arm/mach-k3/include/mach/clock.h
new file mode 100644
index 000000000..e3adbcd9d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/clock.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: Common SoC clock definitions.
+ *
+ * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <config.h>
+
+/* Clock Defines */
+#define V_OSCK				24000000
+#define V_SCLK				V_OSCK
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/hardware.h b/roms/u-boot/arch/arm/mach-k3/include/mach/hardware.h
new file mode 100644
index 000000000..8725e7d51
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/hardware.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _ASM_ARCH_HARDWARE_H_
+#define _ASM_ARCH_HARDWARE_H_
+
+#ifdef CONFIG_SOC_K3_AM6
+#include "am6_hardware.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_hardware.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_hardware.h"
+#endif
+
+/* Assuming these addresses and definitions stay common across K3 devices */
+#define CTRLMMR_WKUP_JTAG_ID	0x43000014
+#define JTAG_ID_VARIANT_SHIFT	28
+#define JTAG_ID_VARIANT_MASK	(0xf << 28)
+#define JTAG_ID_PARTNO_SHIFT	12
+#define JTAG_ID_PARTNO_MASK	(0xffff << 12)
+
+#define K3_ROM_BOOT_HEADER_MAGIC	"EXTBOOT"
+
+struct rom_extended_boot_data {
+	char header[8];
+	u32 num_components;
+};
+
+#endif /* _ASM_ARCH_HARDWARE_H_ */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_hardware.h b/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_hardware.h
new file mode 100644
index 000000000..b98f0a82f
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J721E SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_J721E_HARDWARE_H
+#define __ASM_ARCH_J721E_HARDWARE_H
+
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define CTRL_MMR0_BASE					0x00100000
+#define CTRLMMR_MAIN_DEVSTAT				(CTRL_MMR0_BASE + 0x30)
+
+#define MAIN_DEVSTAT_BOOT_MODE_B_MASK		BIT(0)
+#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT		0
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK		GENMASK(3, 1)
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT	1
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK	BIT(6)
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT		6
+#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK			BIT(7)
+#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT		7
+
+#define WKUP_CTRL_MMR0_BASE				0x43000000
+#define MCU_CTRL_MMR0_BASE				0x40f00000
+
+#define CTRLMMR_WKUP_DEVSTAT			(WKUP_CTRL_MMR0_BASE + 0x30)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK	GENMASK(5, 3)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT	3
+#define WKUP_DEVSTAT_MCU_OMLY_MASK		BIT(6)
+#define WKUP_DEVSTAT_MCU_ONLY_SHIFT		6
+
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE			0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
+ * shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0				0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL			0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK		BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT		0
+#define CTRLMMR_LOCK_KICK1				0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL			0xd172bc5a
+
+/* ROM HANDOFF Structure location */
+#define ROM_ENTENDED_BOOT_DATA_INFO			0x41cffb00
+
+/* MCU SCRATCHPAD usage */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START	CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
+
+#endif /* __ASM_ARCH_J721E_HARDWARE_H */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_spl.h b/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_spl.h
new file mode 100644
index 000000000..e8947917a
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/j721e_spl.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _ASM_ARCH_J721E_SPL_H_
+#define _ASM_ARCH_J721E_SPL_H_
+
+/* With BootMode B = 0 */
+#include <linux/bitops.h>
+#define BOOT_DEVICE_HYPERFLASH		0x00
+#define BOOT_DEVICE_OSPI		0x01
+#define BOOT_DEVICE_QSPI		0x02
+#define BOOT_DEVICE_SPI			0x03
+#define BOOT_DEVICE_ETHERNET		0x04
+#define BOOT_DEVICE_I2C			0x06
+#define BOOT_DEVICE_UART		0x07
+#define BOOT_DEVICE_NOR			BOOT_DEVICE_HYPERFLASH
+
+/* With BootMode B = 1 */
+#define BOOT_DEVICE_MMC2		0x10
+#define BOOT_DEVICE_MMC1		0x11
+#define BOOT_DEVICE_DFU			0x12
+#define BOOT_DEVICE_UFS			0x13
+#define BOOT_DEVIE_GPMC			0x14
+#define BOOT_DEVICE_PCIE		0x15
+#define BOOT_DEVICE_MMC2_2		0x16
+#define BOOT_DEVICE_RAM			0x17
+
+/* Backup boot modes with MCU Only = 0 */
+#define BACKUP_BOOT_DEVICE_RAM		0x0
+#define BACKUP_BOOT_DEVICE_USB		0x1
+#define BACKUP_BOOT_DEVICE_UART		0x3
+#define BACKUP_BOOT_DEVICE_ETHERNET	0x4
+#define BACKUP_BOOT_DEVICE_MMC2		0x5
+#define BACKUP_BOOT_DEVICE_SPI		0x6
+#define BACKUP_BOOT_DEVICE_I2C		0x7
+
+#define BOOT_MODE_B_SHIFT		4
+#define BOOT_MODE_B_MASK		BIT(4)
+
+#define K3_PRIMARY_BOOTMODE		0x0
+#define K3_BACKUP_BOOTMODE		0x1
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/spl.h b/roms/u-boot/arch/arm/mach-k3/include/mach/spl.h
new file mode 100644
index 000000000..ef1c3fb8c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/spl.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#ifdef CONFIG_SOC_K3_AM6
+#include "am6_spl.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_spl.h"
+#endif
+
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_spl.h"
+#endif
+#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/sys_proto.h b/roms/u-boot/arch/arm/mach-k3/include/mach/sys_proto.h
new file mode 100644
index 000000000..60287b261
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/sys_proto.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andreas Dannenberg <dannenberg@ti.com>
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+		  u32 bound);
+struct ti_sci_handle *get_ti_sci_handle(void);
+int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
+int do_board_detect(void);
+void release_resources_for_core_shutdown(void);
+int fdt_disable_node(void *blob, char *node_path);
+
+bool soc_is_j721e(void);
+bool soc_is_j7200(void);
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/include/mach/sysfw-loader.h b/roms/u-boot/arch/arm/mach-k3/include/mach/sysfw-loader.h
new file mode 100644
index 000000000..b23a9e821
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/include/mach/sysfw-loader.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andreas Dannenberg <dannenberg@ti.com>
+ */
+
+#ifndef _SYSFW_LOADER_H_
+#define _SYSFW_LOADER_H_
+
+void k3_sysfw_loader(bool rom_loaded_sysfw,
+		     void (*config_pm_pre_callback)(void),
+		     void (*config_pm_done_callback)(void));
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/j721e_init.c b/roms/u-boot/arch/arm/mach-k3/j721e_init.c
new file mode 100644
index 000000000..76a04a903
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/j721e_init.c
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721E: SoC specific initialization
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/armv7_mpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include "common.h"
+#include <asm/arch/sys_proto.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+#include <mmc.h>
+#include <remoteproc.h>
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_K3_LOAD_SYSFW
+#ifdef CONFIG_TI_SECURE_DEVICE
+struct fwl_data cbass_hc_cfg0_fwls[] = {
+	{ "PCIE0_CFG", 2560, 8 },
+	{ "PCIE1_CFG", 2561, 8 },
+	{ "USB3SS0_CORE", 2568, 4 },
+	{ "USB3SS1_CORE", 2570, 4 },
+	{ "EMMC8SS0_CFG", 2576, 4 },
+	{ "UFS_HCI0_CFG", 2580, 4 },
+	{ "SERDES0", 2584, 1 },
+	{ "SERDES1", 2585, 1 },
+}, cbass_hc0_fwls[] = {
+	{ "PCIE0_HP", 2528, 24 },
+	{ "PCIE0_LP", 2529, 24 },
+	{ "PCIE1_HP", 2530, 24 },
+	{ "PCIE1_LP", 2531, 24 },
+}, cbass_rc_cfg0_fwls[] = {
+	{ "EMMCSD4SS0_CFG", 2380, 4 },
+}, cbass_rc0_fwls[] = {
+	{ "GPMC0", 2310, 8 },
+}, infra_cbass0_fwls[] = {
+	{ "PLL_MMR0", 8, 26 },
+	{ "CTRL_MMR0", 9, 16 },
+}, mcu_cbass0_fwls[] = {
+	{ "MCU_R5FSS0_CORE0", 1024, 4 },
+	{ "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
+	{ "MCU_R5FSS0_CORE1", 1028, 4 },
+	{ "MCU_FSS0_CFG", 1032, 12 },
+	{ "MCU_FSS0_S1", 1033, 8 },
+	{ "MCU_FSS0_S0", 1036, 8 },
+	{ "MCU_PSROM49152X32", 1048, 1 },
+	{ "MCU_MSRAM128KX64", 1050, 8 },
+	{ "MCU_CTRL_MMR0", 1200, 8 },
+	{ "MCU_PLL_MMR0", 1201, 3 },
+	{ "MCU_CPSW0", 1220, 2 },
+}, wkup_cbass0_fwls[] = {
+	{ "WKUP_CTRL_MMR0", 131, 16 },
+};
+#endif
+#endif
+
+static void ctrl_mmr_unlock(void)
+{
+	/* Unlock all WKUP_CTRL_MMR0 module registers */
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
+	mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+	/* Unlock all MCU_CTRL_MMR0 module registers */
+	mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+	mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+	mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+	mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
+	mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
+
+	/* Unlock all CTRL_MMR0 module registers */
+	mmr_unlock(CTRL_MMR0_BASE, 0);
+	mmr_unlock(CTRL_MMR0_BASE, 1);
+	mmr_unlock(CTRL_MMR0_BASE, 2);
+	mmr_unlock(CTRL_MMR0_BASE, 3);
+	mmr_unlock(CTRL_MMR0_BASE, 5);
+	if (soc_is_j721e())
+		mmr_unlock(CTRL_MMR0_BASE, 6);
+	mmr_unlock(CTRL_MMR0_BASE, 7);
+}
+
+#if defined(CONFIG_K3_LOAD_SYSFW)
+void k3_mmc_stop_clock(void)
+{
+	if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+		struct mmc *mmc = find_mmc_device(0);
+
+		if (!mmc)
+			return;
+
+		mmc->saved_clock = mmc->clock;
+		mmc_set_clock(mmc, 0, true);
+	}
+}
+
+void k3_mmc_restart_clock(void)
+{
+	if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+		struct mmc *mmc = find_mmc_device(0);
+
+		if (!mmc)
+			return;
+
+		mmc_set_clock(mmc, mmc->saved_clock, false);
+	}
+}
+#endif
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(".data");
+
+static void store_boot_info_from_rom(void)
+{
+	bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+	memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
+	       sizeof(struct rom_extended_boot_data));
+}
+
+void board_init_f(ulong dummy)
+{
+#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
+	struct udevice *dev;
+	int ret;
+#endif
+	/*
+	 * Cannot delay this further as there is a chance that
+	 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+	 */
+	store_boot_info_from_rom();
+
+	/* Make all control module registers accessible */
+	ctrl_mmr_unlock();
+
+#ifdef CONFIG_CPU_V7R
+	disable_linefill_optimization();
+	setup_k3_mpu_regions();
+#endif
+
+	/* Init DM early */
+	spl_early_init();
+
+#ifdef CONFIG_K3_LOAD_SYSFW
+	/*
+	 * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
+	 * regardless of the result of pinctrl. Do this without probing the
+	 * device, but instead by searching the device that would request the
+	 * given sequence number if probed. The UART will be used by the system
+	 * firmware (SYSFW) image for various purposes and SYSFW depends on us
+	 * to initialize its pin settings.
+	 */
+	ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
+	if (!ret)
+		pinctrl_select_state(dev, "default");
+
+	/*
+	 * Load, start up, and configure system controller firmware. Provide
+	 * the U-Boot console init function to the SYSFW post-PM configuration
+	 * callback hook, effectively switching on (or over) the console
+	 * output.
+	 */
+	k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
+			k3_mmc_stop_clock, k3_mmc_restart_clock);
+
+	/* Prepare console output */
+	preloader_console_init();
+
+	/* Disable ROM configured firewalls right after loading sysfw */
+#ifdef CONFIG_TI_SECURE_DEVICE
+	remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
+	remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
+	remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
+	remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
+	remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
+	remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
+	remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
+#endif
+#else
+	/* Prepare console output */
+	preloader_console_init();
+#endif
+
+	/* Output System Firmware version info */
+	k3_sysfw_print_ver();
+
+	/* Perform EEPROM-based board detection */
+	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
+		do_board_detect();
+
+#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
+	ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
+					  &dev);
+	if (ret)
+		printf("AVS init failed: %d\n", ret);
+#endif
+
+#if defined(CONFIG_K3_J721E_DDRSS)
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret)
+		panic("DRAM init failed: %d\n", ret);
+#endif
+	spl_enable_dcache();
+}
+
+u32 spl_mmc_boot_mode(const u32 boot_device)
+{
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_EMMCBOOT;
+	case BOOT_DEVICE_MMC2:
+		return MMCSD_MODE_FS;
+	default:
+		return MMCSD_MODE_RAW;
+	}
+}
+
+static u32 __get_backup_bootmedia(u32 main_devstat)
+{
+	u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
+			MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
+
+	switch (bkup_boot) {
+	case BACKUP_BOOT_DEVICE_USB:
+		return BOOT_DEVICE_DFU;
+	case BACKUP_BOOT_DEVICE_UART:
+		return BOOT_DEVICE_UART;
+	case BACKUP_BOOT_DEVICE_ETHERNET:
+		return BOOT_DEVICE_ETHERNET;
+	case BACKUP_BOOT_DEVICE_MMC2:
+	{
+		u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
+			    MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
+		if (port == 0x0)
+			return BOOT_DEVICE_MMC1;
+		return BOOT_DEVICE_MMC2;
+	}
+	case BACKUP_BOOT_DEVICE_SPI:
+		return BOOT_DEVICE_SPI;
+	case BACKUP_BOOT_DEVICE_I2C:
+		return BOOT_DEVICE_I2C;
+	}
+
+	return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
+{
+
+	u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+			WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+
+	bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
+			BOOT_MODE_B_SHIFT;
+
+	if (bootmode == BOOT_DEVICE_OSPI || bootmode ==	BOOT_DEVICE_QSPI)
+		bootmode = BOOT_DEVICE_SPI;
+
+	if (bootmode == BOOT_DEVICE_MMC2) {
+		u32 port = (main_devstat &
+			    MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
+			   MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
+		if (port == 0x0)
+			bootmode = BOOT_DEVICE_MMC1;
+	}
+
+	return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
+	u32 main_devstat;
+
+	if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
+		printf("ERROR: MCU only boot is not yet supported\n");
+		return BOOT_DEVICE_RAM;
+	}
+
+	/* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
+	main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+	if (bootindex == K3_PRIMARY_BOOTMODE)
+		return __get_primary_bootmedia(main_devstat, wkup_devstat);
+	else
+		return __get_backup_bootmedia(main_devstat);
+}
+#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+
+#define J721E_DEV_MCU_RTI0			262
+#define J721E_DEV_MCU_RTI1			263
+#define J721E_DEV_MCU_ARMSS0_CPU0		250
+#define J721E_DEV_MCU_ARMSS0_CPU1		251
+
+void release_resources_for_core_shutdown(void)
+{
+	struct ti_sci_handle *ti_sci;
+	struct ti_sci_dev_ops *dev_ops;
+	struct ti_sci_proc_ops *proc_ops;
+	int ret;
+	u32 i;
+
+	const u32 put_device_ids[] = {
+		J721E_DEV_MCU_RTI0,
+		J721E_DEV_MCU_RTI1,
+	};
+
+	ti_sci = get_ti_sci_handle();
+	dev_ops = &ti_sci->ops.dev_ops;
+	proc_ops = &ti_sci->ops.proc_ops;
+
+	/* Iterate through list of devices to put (shutdown) */
+	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+		u32 id = put_device_ids[i];
+
+		ret = dev_ops->put_device(ti_sci, id);
+		if (ret)
+			panic("Failed to put device %u (%d)\n", id, ret);
+	}
+
+	const u32 put_core_ids[] = {
+		J721E_DEV_MCU_ARMSS0_CPU1,
+		J721E_DEV_MCU_ARMSS0_CPU0,	/* Handle CPU0 after CPU1 */
+	};
+
+	/* Iterate through list of cores to put (shutdown) */
+	for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+		u32 id = put_core_ids[i];
+
+		/*
+		 * Queue up the core shutdown request. Note that this call
+		 * needs to be followed up by an actual invocation of an WFE
+		 * or WFI CPU instruction.
+		 */
+		ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+		if (ret)
+			panic("Failed sending core %u shutdown message (%d)\n",
+			      id, ret);
+	}
+}
+#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+void start_non_linux_remote_cores(void)
+{
+	int size = 0, ret;
+	u32 loadaddr = 0;
+
+	if (!soc_is_j721e())
+		return;
+
+	size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
+			     &loadaddr);
+	if (size <= 0)
+		goto err_load;
+
+	/* assuming remoteproc 2 is aliased for the needed remotecore */
+	ret = rproc_load(2, loadaddr, size);
+	if (ret) {
+		printf("Firmware failed to start on rproc (%d)\n", ret);
+		goto err_load;
+	}
+
+	ret = rproc_start(2);
+	if (ret) {
+		printf("Firmware init failed on rproc (%d)\n", ret);
+		goto err_load;
+	}
+
+	printf("Remoteproc 2 started successfully\n");
+
+	return;
+
+err_load:
+	rproc_reset(2);
+}
+#endif
diff --git a/roms/u-boot/arch/arm/mach-k3/lowlevel_init.S b/roms/u-boot/arch/arm/mach-k3/lowlevel_init.S
new file mode 100644
index 000000000..70c5d1cad
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/lowlevel_init.S
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+
+	mrc	p15, 0, r0, c0, c0, 5		@ Read MPIDR
+	and	r0, #0xff
+	cmp	r0, #0x0
+	bne	park_cpu
+	bx	lr
+park_cpu:
+	wfi
+	b	park_cpu
+
+ENDPROC(lowlevel_init)
diff --git a/roms/u-boot/arch/arm/mach-k3/r5_mpu.c b/roms/u-boot/arch/arm/mach-k3/r5_mpu.c
new file mode 100644
index 000000000..3d2ff6775
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/r5_mpu.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K3: R5 MPU region definitions
+ *
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/kernel.h>
+#include "common.h"
+
+struct mpu_region_config k3_mpu_regions[16] = {
+	/*
+	 * Make all 4GB as Device Memory and not executable. We are overriding
+	 * it with next region for any requirement.
+	 */
+	{0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, SHARED_WRITE_BUFFERED,
+	 REGION_4GB},
+
+	/* SPL code area marking it as WB and Write allocate. */
+	{CONFIG_SPL_TEXT_BASE, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+	 O_I_WB_RD_WR_ALLOC, REGION_8MB},
+
+	/* U-Boot's code area marking it as WB and Write allocate */
+	{CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
+	 O_I_WB_RD_WR_ALLOC, REGION_2GB},
+	/* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
+	{0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,
+	 REGION_8MB},
+	{0x0, 4, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 5, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 6, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 7, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 8, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 9, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 10, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 11, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 12, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 13, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 14, 0x0, 0x0, 0x0, 0x0},
+	{0x0, 15, 0x0, 0x0, 0x0, 0x0},
+};
+
+void setup_k3_mpu_regions(void)
+{
+	setup_mpu_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions));
+}
diff --git a/roms/u-boot/arch/arm/mach-k3/security.c b/roms/u-boot/arch/arm/mach-k3/security.c
new file mode 100644
index 000000000..66f90a5a3
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/security.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * K3: Security functions
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andrew F. Davis <afd@ti.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <hang.h>
+#include <image.h>
+#include <log.h>
+#include <asm/cache.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <mach/spl.h>
+#include <spl.h>
+#include <asm/arch/sys_proto.h>
+
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+	u64 image_addr;
+	u32 image_size;
+	int ret;
+
+	image_addr = (uintptr_t)*p_image;
+	image_size = *p_size;
+
+	debug("Authenticating image at address 0x%016llx\n", image_addr);
+	debug("Authenticating image of size %d bytes\n", image_size);
+
+	flush_dcache_range((unsigned long)image_addr,
+			   ALIGN((unsigned long)image_addr + image_size,
+				 ARCH_DMA_MINALIGN));
+
+	/* Authenticate image */
+	ret = proc_ops->proc_auth_boot_image(ti_sci, &image_addr, &image_size);
+	if (ret) {
+		printf("Authentication failed!\n");
+		hang();
+	}
+
+	if (image_size)
+		invalidate_dcache_range((unsigned long)image_addr,
+					ALIGN((unsigned long)image_addr +
+					      image_size, ARCH_DMA_MINALIGN));
+
+	/*
+	 * The image_size returned may be 0 when the authentication process has
+	 * moved the image. When this happens no further processing on the
+	 * image is needed or often even possible as it may have also been
+	 * placed behind a firewall when moved.
+	 */
+	*p_size = image_size;
+
+	/*
+	 * Output notification of successful authentication to re-assure the
+	 * user that the secure code is being processed as expected. However
+	 * suppress any such log output in case of building for SPL and booting
+	 * via YMODEM. This is done to avoid disturbing the YMODEM serial
+	 * protocol transactions.
+	 */
+	if (!(IS_ENABLED(CONFIG_SPL_BUILD) &&
+	      IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) &&
+	      spl_boot_device() == BOOT_DEVICE_UART))
+		printf("Authentication passed\n");
+}
diff --git a/roms/u-boot/arch/arm/mach-k3/sysfw-loader.c b/roms/u-boot/arch/arm/mach-k3/sysfw-loader.c
new file mode 100644
index 000000000..0bacfc4d0
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-k3/sysfw-loader.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K3: System Firmware Loader
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andreas Dannenberg <dannenberg@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <image.h>
+#include <log.h>
+#include <spl.h>
+#include <malloc.h>
+#include <remoteproc.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <g_dnl.h>
+#include <usb.h>
+#include <dfu.h>
+#include <dm/uclass-internal.h>
+#include <spi_flash.h>
+
+#include <asm/arch/sys_proto.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Name of the FIT image nodes for SYSFW and its config data */
+#define SYSFW_FIRMWARE			"sysfw.bin"
+#define SYSFW_CFG_BOARD			"board-cfg.bin"
+#define SYSFW_CFG_PM			"pm-cfg.bin"
+#define SYSFW_CFG_RM			"rm-cfg.bin"
+#define SYSFW_CFG_SEC			"sec-cfg.bin"
+
+/*
+ * It is assumed that remoteproc device 0 is the corresponding
+ * system-controller that runs SYSFW. Make sure DT reflects the same.
+ */
+#define K3_SYSTEM_CONTROLLER_RPROC_ID	0
+
+static bool sysfw_loaded;
+static void *sysfw_load_address;
+
+/*
+ * Populate SPL hook to override the default load address used by the SPL
+ * loader function with a custom address for SYSFW loading.
+ */
+struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+	if (sysfw_loaded)
+		return (struct image_header *)(CONFIG_SYS_TEXT_BASE + offset);
+	else if (sysfw_load_address)
+		return sysfw_load_address;
+	else
+		panic("SYSFW load address not defined!");
+}
+
+/*
+ * Populate SPL hook to skip the default SPL loader FIT post-processing steps
+ * during SYSFW loading and return to the calling function so we can perform
+ * our own custom processing.
+ */
+bool spl_load_simple_fit_skip_processing(void)
+{
+	return !sysfw_loaded;
+}
+
+static int fit_get_data_by_name(const void *fit, int images, const char *name,
+				const void **addr, size_t *size)
+{
+	int node_offset;
+
+	node_offset = fdt_subnode_offset(fit, images, name);
+	if (node_offset < 0)
+		return -ENOENT;
+
+	return fit_image_get_data(fit, node_offset, addr, size);
+}
+
+static void k3_start_system_controller(int rproc_id, bool rproc_loaded,
+				       ulong addr, ulong size)
+{
+	int ret;
+
+	ret = rproc_dev_init(rproc_id);
+	if (ret)
+		panic("rproc failed to be initialized (%d)\n", ret);
+
+	if (!rproc_loaded) {
+		ret = rproc_load(rproc_id, addr, size);
+		if (ret)
+			panic("Firmware failed to start on rproc (%d)\n", ret);
+	}
+
+	ret = rproc_start(0);
+	if (ret)
+		panic("Firmware init failed on rproc (%d)\n", ret);
+}
+
+static void k3_sysfw_load_using_fit(void *fit)
+{
+	int images;
+	const void *sysfw_addr;
+	size_t sysfw_size;
+	int ret;
+
+	/* Find the node holding the images information */
+	images = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images < 0)
+		panic("Cannot find /images node (%d)\n", images);
+
+	/* Extract System Firmware (SYSFW) image from FIT */
+	ret = fit_get_data_by_name(fit, images, SYSFW_FIRMWARE,
+				   &sysfw_addr, &sysfw_size);
+	if (ret < 0)
+		panic("Error accessing %s node in FIT (%d)\n", SYSFW_FIRMWARE,
+		      ret);
+
+	/* Start up system controller firmware */
+	k3_start_system_controller(K3_SYSTEM_CONTROLLER_RPROC_ID, false,
+				   (ulong)sysfw_addr, (ulong)sysfw_size);
+}
+
+static void k3_sysfw_configure_using_fit(void *fit,
+					 struct ti_sci_handle *ti_sci)
+{
+	struct ti_sci_board_ops *board_ops = &ti_sci->ops.board_ops;
+	int images;
+	const void *cfg_fragment_addr;
+	size_t cfg_fragment_size;
+	int ret;
+
+	/* Find the node holding the images information */
+	images = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images < 0)
+		panic("Cannot find /images node (%d)\n", images);
+
+	/* Extract board configuration from FIT */
+	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_BOARD,
+				   &cfg_fragment_addr, &cfg_fragment_size);
+	if (ret < 0)
+		panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_BOARD,
+		      ret);
+
+	/* Apply board configuration to SYSFW */
+	ret = board_ops->board_config(ti_sci,
+				      (u64)(u32)cfg_fragment_addr,
+				      (u32)cfg_fragment_size);
+	if (ret)
+		panic("Failed to set board configuration (%d)\n", ret);
+
+	/* Extract power/clock (PM) specific configuration from FIT */
+	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_PM,
+				   &cfg_fragment_addr, &cfg_fragment_size);
+	if (ret < 0)
+		panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_PM,
+		      ret);
+
+	/* Apply power/clock (PM) specific configuration to SYSFW */
+	ret = board_ops->board_config_pm(ti_sci,
+					 (u64)(u32)cfg_fragment_addr,
+					 (u32)cfg_fragment_size);
+	if (ret)
+		panic("Failed to set board PM configuration (%d)\n", ret);
+
+	/* Extract resource management (RM) specific configuration from FIT */
+	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
+				   &cfg_fragment_addr, &cfg_fragment_size);
+	if (ret < 0)
+		panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
+		      ret);
+
+	/* Apply resource management (RM) configuration to SYSFW */
+	ret = board_ops->board_config_rm(ti_sci,
+					 (u64)(u32)cfg_fragment_addr,
+					 (u32)cfg_fragment_size);
+	if (ret)
+		panic("Failed to set board RM configuration (%d)\n", ret);
+
+	/* Extract security specific configuration from FIT */
+	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
+				   &cfg_fragment_addr, &cfg_fragment_size);
+	if (ret < 0)
+		panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_SEC,
+		      ret);
+
+	/* Apply security configuration to SYSFW */
+	ret = board_ops->board_config_security(ti_sci,
+					       (u64)(u32)cfg_fragment_addr,
+					       (u32)cfg_fragment_size);
+	if (ret)
+		panic("Failed to set board security configuration (%d)\n",
+		      ret);
+}
+
+#if CONFIG_IS_ENABLED(DFU)
+static int k3_sysfw_dfu_download(void *addr)
+{
+	char dfu_str[50];
+	int ret;
+
+	sprintf(dfu_str, "sysfw.itb ram 0x%p 0x%x", addr,
+		CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
+	ret = dfu_config_entities(dfu_str, "ram", "0");
+	if (ret) {
+		dfu_free_entities();
+		goto exit;
+	}
+
+	run_usb_dnl_gadget(0, "usb_dnl_dfu");
+exit:
+	dfu_free_entities();
+	return ret;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(SPI_LOAD)
+static void *k3_sysfw_get_spi_addr(void)
+{
+	struct udevice *dev;
+	fdt_addr_t addr;
+	int ret;
+
+	ret = uclass_find_device_by_seq(UCLASS_SPI, CONFIG_SF_DEFAULT_BUS,
+					&dev);
+	if (ret)
+		return NULL;
+
+	addr = dev_read_addr_index(dev, 1);
+	if (addr == FDT_ADDR_T_NONE)
+		return NULL;
+
+	return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS);
+}
+#endif
+
+void k3_sysfw_loader(bool rom_loaded_sysfw,
+		     void (*config_pm_pre_callback)(void),
+		     void (*config_pm_done_callback)(void))
+{
+	struct spl_image_info spl_image = { 0 };
+	struct spl_boot_device bootdev = { 0 };
+	struct ti_sci_handle *ti_sci;
+	int ret = 0;
+
+	if (rom_loaded_sysfw) {
+		k3_start_system_controller(K3_SYSTEM_CONTROLLER_RPROC_ID,
+					   rom_loaded_sysfw, 0, 0);
+		sysfw_loaded = true;
+		return;
+	}
+
+	/* Reserve a block of aligned memory for loading the SYSFW image */
+	sysfw_load_address = memalign(ARCH_DMA_MINALIGN,
+				      CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
+	if (!sysfw_load_address)
+		panic("Error allocating %u bytes of memory for SYSFW image\n",
+		      CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
+
+	debug("%s: allocated %u bytes at 0x%p\n", __func__,
+	      CONFIG_K3_SYSFW_IMAGE_SIZE_MAX, sysfw_load_address);
+
+	/* Set load address for legacy modes that bypass spl_get_load_buffer */
+	spl_image.load_addr = (uintptr_t)sysfw_load_address;
+
+	bootdev.boot_device = spl_boot_device();
+
+	/* Load combined System Controller firmware and config data image */
+	switch (bootdev.boot_device) {
+#if CONFIG_IS_ENABLED(MMC_SUPPORT)
+	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		ret = spl_mmc_load(&spl_image, &bootdev,
+#ifdef CONFIG_K3_SYSFW_IMAGE_NAME
+				   CONFIG_K3_SYSFW_IMAGE_NAME,
+#else
+				   NULL,
+#endif
+#ifdef CONFIG_K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
+				   CONFIG_K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART,
+#else
+				   0,
+#endif
+#ifdef CONFIG_K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
+				   CONFIG_K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT);
+#else
+				   0);
+#endif
+		break;
+#endif
+#if CONFIG_IS_ENABLED(SPI_LOAD)
+	case BOOT_DEVICE_SPI:
+		sysfw_load_address = k3_sysfw_get_spi_addr();
+		if (!sysfw_load_address)
+			ret = -ENODEV;
+		break;
+#endif
+#if CONFIG_IS_ENABLED(YMODEM_SUPPORT)
+	case BOOT_DEVICE_UART:
+#ifdef CONFIG_K3_EARLY_CONS
+		/*
+		 * Establish a serial console if not yet available as required
+		 * for UART-based boot. For this use the early console feature
+		 * that allows setting up a UART for use before SYSFW has been
+		 * brought up. Note that the associated UART module's clocks
+		 * must have gotten enabled by the ROM bootcode which will be
+		 * the case when continuing to boot serially from the same
+		 * UART that the ROM loaded the initial bootloader from.
+		 */
+		if (!gd->have_console)
+			early_console_init();
+#endif
+		ret = spl_ymodem_load_image(&spl_image, &bootdev);
+		break;
+#endif
+#if CONFIG_IS_ENABLED(DFU)
+	case BOOT_DEVICE_DFU:
+		ret = k3_sysfw_dfu_download(sysfw_load_address);
+		break;
+#endif
+#if CONFIG_IS_ENABLED(USB_STORAGE)
+	case BOOT_DEVICE_USB:
+		ret = spl_usb_load(&spl_image, &bootdev,
+				   CONFIG_SYS_USB_FAT_BOOT_PARTITION,
+#ifdef CONFIG_K3_SYSFW_IMAGE_NAME
+				   CONFIG_K3_SYSFW_IMAGE_NAME);
+#else
+				   NULL);
+#endif
+#endif
+		break;
+	default:
+		panic("Loading SYSFW image from device %u not supported!\n",
+		      bootdev.boot_device);
+	}
+
+	if (ret)
+		panic("Error %d occurred during loading SYSFW image!\n", ret);
+
+	/*
+	 * Now that SYSFW got loaded set helper flag to restore regular SPL
+	 * loader behavior so we can later boot into the next stage as expected.
+	 */
+	sysfw_loaded = true;
+
+	/* Ensure the SYSFW image is in FIT format */
+	if (image_get_magic((const image_header_t *)sysfw_load_address) !=
+	    FDT_MAGIC)
+		panic("SYSFW image not in FIT format!\n");
+
+	/* Extract and start SYSFW */
+	k3_sysfw_load_using_fit(sysfw_load_address);
+
+	/* Get handle for accessing SYSFW services */
+	ti_sci = get_ti_sci_handle();
+
+	if (config_pm_pre_callback)
+		config_pm_pre_callback();
+
+	/* Parse and apply the different SYSFW configuration fragments */
+	k3_sysfw_configure_using_fit(sysfw_load_address, ti_sci);
+
+	/*
+	 * Now that all clocks and PM aspects are setup, invoke a user-
+	 * provided callback function. Usually this callback would be used
+	 * to setup or re-configure the U-Boot console UART.
+	 */
+	if (config_pm_done_callback)
+		config_pm_done_callback();
+}