Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

5 files changed, 502 insertions, 0 deletions

diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3288/Kconfig b/roms/u-boot/arch/arm/mach-rockchip/rk3288/Kconfig
new file mode 100644
index 000000000..20a00c5be
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -0,0 +1,199 @@
+if ROCKCHIP_RK3288
+
+choice
+	prompt "RK3288 board select"
+
+config TARGET_CHROMEBOOK_JERRY
+	bool "Google/Rockchip Veyron-Jerry Chromebook"
+	select HAS_ROM
+	select BOARD_LATE_INIT
+	select ROCKCHIP_SPI_IMAGE
+	help
+	  Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
+	  HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
+	  WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
+	  the keyboard and battery functions.
+
+config TARGET_CHROMEBIT_MICKEY
+	bool "Google/Rockchip Veyron-Mickey Chromebit"
+	select BOARD_LATE_INIT
+	help
+	  Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
+	  and WiFi. It has a separate power port and is designed to connect
+	  to the HDMI input of a monitor or TV. It has no internal battery.
+	  Typically a USB hub or wireless keyboard/touchpad is used to get
+	  keyboard and mouse access.
+
+config TARGET_CHROMEBOOK_MINNIE
+	bool "Google/Rockchip Veyron-Minnie Chromebook"
+	select BOARD_LATE_INIT
+	help
+	  Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
+	  ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
+	  HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS
+	  EC (Cortex-M3) to provide access to the keyboard and battery
+	  functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
+	  internal MMC. The product name is ASUS Chromebook Flip.
+
+config TARGET_CHROMEBOOK_SPEEDY
+	bool "Google/Rockchip Veyron-Speedy Chromebook"
+	select BOARD_LATE_INIT
+	help
+	  Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports,
+	  micro HDMI, an 11.6 inch display, micro-SD card,
+	  HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS
+	  EC (Cortex-M3) to provide access to the keyboard and battery
+	  functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC.
+	  The product name is Asus Chromebook C201PA.
+
+config TARGET_EVB_RK3288
+	bool "Evb-RK3288"
+	select HAS_ROM
+	select BOARD_LATE_INIT
+	select TPL
+	help
+	  EVB-RK3288 is a RK3288-based development board with 2 USB ports,
+	  HDMI, VGA, micro-SD card, audio, WiFi  and Gigabit Ethernet, It
+	  also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
+	  provide access to display pins, I2C, SPI, UART and GPIOs.
+
+config TARGET_FENNEC_RK3288
+	bool "Fennec-RK3288"
+	select BOARD_LATE_INIT
+	help
+	  Fennec is a RK3288-based development board with 2 USB ports,
+	  HDMI, micro-SD card, audio, WiFi and Gigabit Ethernet. It also
+	  includes on-board eMMC and 2GB of SDRAM. Expansion connectors
+	  provide access to display pins, I2C, SPI, UART and GPIOs.
+
+config TARGET_FIREFLY_RK3288
+	bool "Firefly-RK3288"
+	select BOARD_LATE_INIT
+	select SPL_BOARD_INIT if SPL
+	select TPL
+	help
+	  Firefly is a RK3288-based development board with 2 USB ports,
+	  HDMI, VGA, micro-SD card, audio, WiFi  and Gigabit Ethernet, It
+	  also includes on-board eMMC and 1GB of SDRAM. Expansion connectors
+	  provide access to display pins, I2C, SPI, UART and GPIOs.
+
+config TARGET_MIQI_RK3288
+	bool "MiQi-RK3288"
+	select BOARD_LATE_INIT
+	help
+	  MiQi-RK3288 is a RK3288-based development board with 4 USB 2.0
+	  ports, HDMI, micro-SD card, 16 GB eMMC and Gigabit Ethernet. It
+	  has 1 or 2 GiB SDRAM. Expansion connectors provide access to
+	  I2C, SPI, UART, GPIOs and fan control.
+
+config TARGET_PHYCORE_RK3288
+	bool "phyCORE-RK3288"
+        select BOARD_LATE_INIT
+	select SPL_BOARD_INIT if SPL
+	help
+	  Add basic support for the PCM-947 carrier board, a RK3288 based
+	  development board made by PHYTEC. This board works in a combination
+	  with the phyCORE-RK3288 System on Module.
+
+config TARGET_POPMETAL_RK3288
+	bool "PopMetal-RK3288"
+	select BOARD_LATE_INIT
+	help
+	  PopMetal is a RK3288-based development board with 3 USB host ports,
+	  1 micro USB OTG port, HDMI, VGA, micro-SD card, audio, WiFi, Gigabit
+	  Ethernet and lots of sensors. It also includes on-board 8 GeMMC and
+	  2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
+	  GPIOs and display interface.
+
+config TARGET_VYASA_RK3288
+	bool "Vyasa-RK3288"
+	select BOARD_LATE_INIT
+	select TPL
+	help
+	  Vyasa is a RK3288-based development board with 2 USB ports,
+	  HDMI, VGA, micro-SD card, audio, WiFi  and Gigabit Ethernet, It
+	  also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
+	  provide access to display pins, I2C, SPI, UART and GPIOs.
+
+config TARGET_ROCK2
+	bool "Radxa Rock 2"
+	select BOARD_LATE_INIT
+	help
+	  Rock 2 is a SOM and base-board combination based on RK3288. It
+	  includes Ethernet, HDMI, 3 USB, micro-SD, audio, SATA, WiFi and
+	  space for a real-time-clock battery. There is also an expansion
+	  interface which provides access to many pins.
+
+config TARGET_TINKER_RK3288
+	bool "Tinker-RK3288"
+        select BOARD_LATE_INIT
+	select TPL
+	help
+	  Tinker is a RK3288-based development board with 2 USB ports, HDMI,
+	  micro-SD card, audio, Gigabit Ethernet. It also includes on-board
+	  8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
+	  I2C, SPI, UART, GPIOs.
+
+endchoice
+
+config ROCKCHIP_FAST_SPL
+	bool "Change the CPU to full speed in SPL"
+	depends on TARGET_CHROMEBOOK_JERRY
+	help
+	  Some boards want to boot as fast as possible. We can increase the
+	  CPU frequency in SPL if the power supply is configured to the correct
+	  voltage. This option is only available on boards which support it
+	  and have the required PMIC code.
+
+config ROCKCHIP_BOOT_MODE_REG
+	default 0xff730094
+
+config SYS_SOC
+	default "rk3288"
+
+config SYS_MALLOC_F_LEN
+	default 0x2000
+
+config SPL_DRIVERS_MISC_SUPPORT
+	default y
+
+config SPL_LIBCOMMON_SUPPORT
+	default y
+
+config SPL_LIBGENERIC_SUPPORT
+	default y
+
+config SPL_SERIAL_SUPPORT
+	default y
+
+config TPL_LDSCRIPT
+	default "arch/arm/mach-rockchip/u-boot-tpl.lds"
+
+config TPL_MAX_SIZE
+	default 32768
+
+config TPL_STACK
+        default 0xff718000
+
+config TPL_TEXT_BASE
+	default 0xff704000
+
+source "board/amarula/vyasa-rk3288/Kconfig"
+
+source "board/chipspark/popmetal_rk3288/Kconfig"
+
+source "board/firefly/firefly-rk3288/Kconfig"
+
+source "board/google/veyron/Kconfig"
+
+source "board/mqmaker/miqi_rk3288/Kconfig"
+
+source "board/phytec/phycore_rk3288/Kconfig"
+
+source "board/radxa/rock2/Kconfig"
+
+source "board/rockchip/evb_rk3288/Kconfig"
+
+source "board/rockchip/tinker_rk3288/Kconfig"
+
+endif
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3288/Makefile b/roms/u-boot/arch/arm/mach-rockchip/rk3288/Makefile
new file mode 100644
index 000000000..a0033a0d8
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3288/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2015 Google, Inc
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += clk_rk3288.o
+obj-y += rk3288.o
+obj-y += syscon_rk3288.o
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/roms/u-boot/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
new file mode 100644
index 000000000..fb4c0891d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3288/clk_rk3288.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_DRIVER_GET(rockchip_rk3288_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	struct rk3288_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->cru;
+}
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3288/rk3288.c b/roms/u-boot/arch/arm/mach-rockchip/rk3288/rk3288.c
new file mode 100644
index 000000000..bc20bc5ab
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ */
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <env.h>
+#include <clk.h>
+#include <init.h>
+#include <malloc.h>
+#include <asm/armv7.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cpu_rk3288.h>
+#include <asm/arch-rockchip/cru.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
+#include <asm/arch-rockchip/qos_rk3288.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GRF_BASE	0xff770000
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
+	[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
+};
+
+#ifdef CONFIG_SPL_BUILD
+static void configure_l2ctlr(void)
+{
+	u32 l2ctlr;
+
+	l2ctlr = read_l2ctlr();
+	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+	/*
+	 * Data RAM write latency: 2 cycles
+	 * Data RAM read latency: 2 cycles
+	 * Data RAM setup latency: 1 cycle
+	 * Tag RAM write latency: 1 cycle
+	 * Tag RAM read latency: 1 cycle
+	 * Tag RAM setup latency: 1 cycle
+	 */
+	l2ctlr |= (1 << 3 | 1 << 0);
+	write_l2ctlr(l2ctlr);
+}
+#endif
+
+int rk3288_qos_init(void)
+{
+	int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
+	/* set vop qos to higher priority */
+	writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
+	writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
+
+	if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+				       "rockchip,rk3288-tinker")) {
+		/* set isp qos to higher priority */
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
+	}
+
+	return 0;
+}
+
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	configure_l2ctlr();
+#else
+	/* We do some SoC one time setting here. */
+	struct rk3288_grf * const grf = (void *)GRF_BASE;
+
+	/* Use rkpwm by default */
+	rk_setreg(&grf->soc_con2, 1 << 0);
+
+	/*
+	 * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
+	 * cleared
+	 */
+	rk_clrreg(&grf->soc_con0, 1 << 12);
+
+	rk3288_qos_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	/* Enable early UART on the RK3288 */
+	struct rk3288_grf * const grf = (void *)GRF_BASE;
+
+	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
+		     GPIO7C6_MASK << GPIO7C6_SHIFT,
+		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
+		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
+}
+#endif
+
+__weak int rk3288_board_late_init(void)
+{
+	return 0;
+}
+
+int rk_board_late_init(void)
+{
+	return rk3288_board_late_init();
+}
+
+static int ft_rk3288w_setup(void *blob)
+{
+	const char *path;
+	int offs, ret;
+
+	path = "/clock-controller@ff760000";
+	offs = fdt_path_offset(blob, path);
+	if (offs < 0) {
+		debug("failed to found fdt path %s\n", path);
+		return offs;
+	}
+
+	ret = fdt_setprop_string(blob, offs, "compatible", "rockchip,rk3288w-cru");
+	if (ret) {
+		printf("failed to set rk3288w-cru compatible (ret=%d)\n", ret);
+		return ret;
+	}
+
+	return ret;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	if (soc_is_rk3288w())
+		return ft_rk3288w_setup(blob);
+
+	return 0;
+}
+
+static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc,
+		    char *const argv[])
+{
+	static const struct {
+		char *name;
+		int id;
+	} clks[] = {
+		{ "osc", CLK_OSC },
+		{ "apll", CLK_ARM },
+		{ "dpll", CLK_DDR },
+		{ "cpll", CLK_CODEC },
+		{ "gpll", CLK_GENERAL },
+#ifdef CONFIG_ROCKCHIP_RK3036
+		{ "mpll", CLK_NEW },
+#else
+		{ "npll", CLK_NEW },
+#endif
+	};
+	int ret, i;
+	struct udevice *dev;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret) {
+		printf("clk-uclass not found\n");
+		return 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(clks); i++) {
+		struct clk clk;
+		ulong rate;
+
+		clk.id = clks[i].id;
+		ret = clk_request(dev, &clk);
+		if (ret < 0)
+			continue;
+
+		rate = clk_get_rate(&clk);
+		printf("%s: %lu\n", clks[i].name, rate);
+
+		clk_free(&clk);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clock, 2, 1, do_clock,
+	"display information about clocks",
+	""
+);
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/roms/u-boot/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
new file mode 100644
index 000000000..9c1ae880c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3288_syscon_ids[] = {
+	{ .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC },
+	{ .compatible = "rockchip,rk3288-grf", .data = ROCKCHIP_SYSCON_GRF },
+	{ .compatible = "rockchip,rk3288-sgrf", .data = ROCKCHIP_SYSCON_SGRF },
+	{ .compatible = "rockchip,rk3288-pmu", .data = ROCKCHIP_SYSCON_PMU },
+	{ }
+};
+
+U_BOOT_DRIVER(syscon_rk3288) = {
+	.name = "rk3288_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3288_syscon_ids,
+};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3288_syscon_bind_of_plat(struct udevice *dev)
+{
+	dev->driver_data = dev->driver->of_match->data;
+	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3288_noc) = {
+	.name = "rockchip_rk3288_noc",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3288_syscon_ids,
+	.bind = rk3288_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rk3288_grf) = {
+	.name = "rockchip_rk3288_grf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3288_syscon_ids + 1,
+	.bind = rk3288_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
+	.name = "rockchip_rk3288_sgrf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3288_syscon_ids + 2,
+	.bind = rk3288_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
+	.name = "rockchip_rk3288_pmu",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3288_syscon_ids + 3,
+	.bind = rk3288_syscon_bind_of_plat,
+};
+#endif