Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

5 files changed, 428 insertions, 0 deletions

diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3368/Kconfig b/roms/u-boot/arch/arm/mach-rockchip/rk3368/Kconfig
new file mode 100644
index 000000000..78eb96df3
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -0,0 +1,80 @@
+if ROCKCHIP_RK3368
+
+choice
+	prompt "RK3368 board"
+
+config TARGET_LION_RK3368
+        bool "Theobroma Systems RK3368-uQ7 (Lion) module"
+	help
+	  The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm,
+	  MXM-230 connector) system-on-module designed by Theobroma
+	  Systems for industrial applications.
+
+	  It provides the following features:
+	   - 8x Cortex-A53 (in 2 clusters of 4 cores each)
+	   - (on-module) up to 4GB of DDR3 memory
+	   - (on-module) SPI-NOR flash
+	   - (on-module) eMMC
+	   - Gigabit Ethernet (with an on-module KSZ9031 PHY)
+	   - USB
+	   - HDMI
+	   - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
+	   - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
+	   - on-module STM32 providing CAN, RTC and fan-control
+	   - (optional on-module) EAL4+-certified security module
+
+config TARGET_SHEEP
+	bool "Sheep board"
+	help
+	  Sheep board is designed by Rockchip as a EVB board
+	  for rk3368.
+
+config TARGET_GEEKBOX
+	bool "GeekBox"
+
+config TARGET_EVB_PX5
+        bool "Evb-PX5"
+        help
+	 PX5 EVB is designed by Rockchip for automotive field
+         with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
+         HDMI video input/output interface, audio codec ES8396,
+         WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity
+         sensor STK3410.
+endchoice
+
+config ROCKCHIP_BOOT_MODE_REG
+	default 0xff738200
+
+config SYS_SOC
+	default "rk3368"
+
+config SYS_MALLOC_F_LEN
+	default 0x4000
+
+config SPL_LIBCOMMON_SUPPORT
+	default y
+
+config SPL_LIBGENERIC_SUPPORT
+	default y
+
+source "board/theobroma-systems/lion_rk3368/Kconfig"
+source "board/rockchip/sheep_rk3368/Kconfig"
+source "board/geekbuying/geekbox/Kconfig"
+source "board/rockchip/evb_px5/Kconfig"
+
+config SPL_LDSCRIPT
+	default "arch/arm/cpu/armv8/u-boot-spl.lds"
+
+config SPL_STACK_R_ADDR
+	default 0x04000000
+
+config TPL_MAX_SIZE
+        default 28672
+
+config TPL_STACK
+        default 0xff8cffff
+
+config TPL_TEXT_BASE
+        default 0xff8c1000
+
+endif
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3368/Makefile b/roms/u-boot/arch/arm/mach-rockchip/rk3368/Makefile
new file mode 100644
index 000000000..3bddc104a
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3368/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2016 Andreas Färber
+obj-y		+= clk_rk3368.o
+obj-y		+= rk3368.o
+obj-y 		+= syscon_rk3368.o
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/roms/u-boot/arch/arm/mach-rockchip/rk3368/clk_rk3368.c
new file mode 100644
index 000000000..b07531972
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3368/clk_rk3368.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_DRIVER_GET(rockchip_rk3368_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	struct rk3368_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->cru;
+}
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3368/rk3368.c b/roms/u-boot/arch/arm/mach-rockchip/rk3368/rk3368.c
new file mode 100644
index 000000000..9b7132d47
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3368/rk3368.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2016 Andreas Färber
+ */
+
+#include <common.h>
+#include <init.h>
+#include <syscon.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
+#include <asm/arch-rockchip/grf_rk3368.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMEM_BASE                  0xFF8C0000
+
+/* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
+#define MCU_SRAM_BASE			(IMEM_BASE + 1024 * 4)
+#define MCU_SRAM_BASE_BIT31_BIT28	((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
+#define MCU_SRAM_BASE_BIT27_BIT12	((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
+/* exsram may using by mcu to accessing dram(0x0-0x20000000) */
+#define MCU_EXSRAM_BASE    (0)
+#define MCU_EXSRAM_BASE_BIT31_BIT28       ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
+#define MCU_EXSRAM_BASE_BIT27_BIT12       ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
+/* experi no used, reserved value = 0 */
+#define MCU_EXPERI_BASE    (0)
+#define MCU_EXPERI_BASE_BIT31_BIT28       ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
+#define MCU_EXPERI_BASE_BIT27_BIT12       ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
+
+static struct mm_region rk3368_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xf0000000UL,
+		.phys = 0xf0000000UL,
+		.size = 0x10000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = rk3368_mem_map;
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
+	[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
+};
+
+#ifdef CONFIG_ARCH_EARLY_INIT_R
+static int mcu_init(void)
+{
+	struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	struct rk3368_cru *cru = rockchip_get_cru();
+
+	rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
+		     MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
+	rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
+		     MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
+	rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
+		     MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
+	rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
+		     MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
+	rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
+		     MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
+	rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
+		     MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
+
+	rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
+		     (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
+		     (5 << MCU_CLK_DIV_SHIFT));
+
+	 /* mcu dereset, for start running */
+	rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
+
+	return 0;
+}
+
+int arch_early_init_r(void)
+{
+	return mcu_init();
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * The SPL (and also the full U-Boot stage on the RK3368) will run in
+ * secure mode (i.e. EL3) and an ATF will eventually be booted before
+ * starting up the operating system... so we can initialize the SGRF
+ * here and rely on the ATF installing the final (secure) policy
+ * later.
+ */
+static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
+{
+	const uintptr_t SGRF_BASE =
+		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+
+	return SGRF_BASE + sizeof(u32) * no;
+}
+
+static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
+{
+	const uintptr_t SGRF_BASE =
+		(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+	const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
+	const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
+
+	return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
+}
+
+static void sgrf_init(void)
+{
+	struct rk3368_cru * const cru =
+		(struct rk3368_cru * const)rockchip_get_cru();
+	const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
+	const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
+	const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
+
+	/* Set all configurable IP to 'non secure'-mode */
+	rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
+	rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
+	rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
+
+	/*
+	 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
+	 * Original comment: "ddr space set no secure mode"
+	 */
+	rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
+	rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
+	rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
+
+	/* Set 'secure dma' to 'non secure'-mode */
+	rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
+	rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
+
+	dsb();  /* barrier */
+
+	rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+	rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+
+	dsb();  /* barrier */
+	udelay(10);
+
+	rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+	rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+}
+
+int arch_cpu_init(void)
+{
+	/* Reset security, so we can use DMA in the MMC drivers */
+	sgrf_init();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	/*
+	 * N.B.: This is called before the device-model has been
+	 *       initialised. For this reason, we can not access
+	 *       the GRF address range using the syscon API.
+	 */
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+	struct rk3368_grf * const grf =
+		(struct rk3368_grf * const)0xff770000;
+
+	enum {
+		GPIO2D1_MASK            = GENMASK(3, 2),
+		GPIO2D1_GPIO            = 0,
+		GPIO2D1_UART0_SOUT      = (1 << 2),
+
+		GPIO2D0_MASK            = GENMASK(1, 0),
+		GPIO2D0_GPIO            = 0,
+		GPIO2D0_UART0_SIN       = (1 << 0),
+	};
+
+	/* Enable early UART0 on the RK3368 */
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
+	struct rk3368_pmu_grf * const pmugrf __maybe_unused =
+		(struct rk3368_pmu_grf * const)0xff738000;
+
+	enum {
+		/* UART4 */
+		GPIO0D2_MASK		= GENMASK(5, 4),
+		GPIO0D2_GPIO		= 0,
+		GPIO0D2_UART4_SOUT	= (3 << 4),
+
+		GPIO0D3_MASK		= GENMASK(7, 6),
+		GPIO0D3_GPIO		= 0,
+		GPIO0D3_UART4_SIN	= (3 << 6),
+	};
+
+	/* Enable early UART4 on the PX5 */
+	rk_clrsetreg(&pmugrf->gpio0d_iomux,
+		     GPIO0D2_MASK | GPIO0D3_MASK,
+		     GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
+	struct rk3368_grf * const grf =
+		(struct rk3368_grf * const)0xff770000;
+
+	enum {
+		GPIO2A6_SHIFT           = 12,
+		GPIO2A6_MASK            = GENMASK(13, 12),
+		GPIO2A6_GPIO            = 0,
+		GPIO2A6_UART2_SIN       = (2 << GPIO2A6_SHIFT),
+
+		GPIO2A5_SHIFT           = 10,
+		GPIO2A5_MASK            = GENMASK(11, 10),
+		GPIO2A5_GPIO            = 0,
+		GPIO2A5_UART2_SOUT      = (2 << GPIO2A5_SHIFT),
+	};
+
+	/* Enable early UART2 on the RK3368 */
+	rk_clrsetreg(&grf->gpio2a_iomux,
+		     GPIO2A6_MASK, GPIO2A6_UART2_SIN);
+	rk_clrsetreg(&grf->gpio2a_iomux,
+		     GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
+#endif
+}
+#endif
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/roms/u-boot/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
new file mode 100644
index 000000000..dc2d831dd
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3368_syscon_ids[] = {
+	{ .compatible = "rockchip,rk3368-grf",
+	  .data = ROCKCHIP_SYSCON_GRF },
+	{ .compatible = "rockchip,rk3368-pmugrf",
+	  .data = ROCKCHIP_SYSCON_PMUGRF },
+	{ .compatible = "rockchip,rk3368-msch",
+	  .data = ROCKCHIP_SYSCON_MSCH },
+	{ .compatible = "rockchip,rk3368-sgrf",
+	  .data = ROCKCHIP_SYSCON_SGRF },
+	{ }
+};
+
+U_BOOT_DRIVER(syscon_rk3368) = {
+	.name = "rk3368_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids,
+};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3368_syscon_bind_of_plat(struct udevice *dev)
+{
+	dev->driver_data = dev->driver->of_match->data;
+	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3368_grf) = {
+	.name = "rockchip_rk3368_grf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids,
+	.bind = rk3368_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
+	.name = "rockchip_rk3368_pmugrf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids + 1,
+	.bind = rk3368_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_msch) = {
+	.name = "rockchip_rk3368_msch",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids + 2,
+	.bind = rk3368_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
+	.name = "rockchip_rk3368_sgrf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids + 3,
+	.bind = rk3368_syscon_bind_of_plat,
+};
+#endif