diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/arm/mach-snapdragon/include | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/arm/mach-snapdragon/include')
5 files changed, 109 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/mach-snapdragon/include/mach/dram.h b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/dram.h new file mode 100644 index 000000000..0a9eedda4 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/dram.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Snapdragon DRAM + * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com> + */ + +#ifndef DRAM_H +#define DRAM_H + +int msm_fixup_memory(void *blob); + +#endif diff --git a/roms/u-boot/arch/arm/mach-snapdragon/include/mach/gpio.h b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/gpio.h new file mode 100644 index 000000000..bbc2bc161 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Empty gpio.h + * + * This file must stay as arch/arm/include/asm/gpio.h requires it. + * + * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> + */ diff --git a/roms/u-boot/arch/arm/mach-snapdragon/include/mach/misc.h b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/misc.h new file mode 100644 index 000000000..c60e3e472 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/misc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Snapdragon DRAM + * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com> + */ + +#ifndef MISC_H +#define MISC_H + +u32 msm_board_serial(void); +void msm_generate_mac_addr(u8 *mac); + +#endif diff --git a/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h new file mode 100644 index 000000000..520e2e6bd --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm APQ8916 sysmap + * + * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> + */ +#ifndef _MACH_SYSMAP_APQ8016_H +#define _MACH_SYSMAP_APQ8016_H + +#define GICD_BASE (0x0b000000) +#define GICC_BASE (0x0a20c000) + +/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x2101C) +#define APCS_GPLL_ENA_VOTE (0x45000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) + +#define SDCC_BCR(n) ((n * 0x1000) + 0x41000) +#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) +#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) +#define SDCC_M(n) ((n * 0x1000) + 0x4100C) +#define SDCC_N(n) ((n * 0x1000) + 0x41010) +#define SDCC_D(n) ((n * 0x1000) + 0x41014) +#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) +#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) + +/* BLSP1 AHB clock (root clock for BLSP) */ +#define BLSP1_AHB_CBCR 0x1008 + +/* Uart clock control registers */ +#define BLSP1_UART2_BCR (0x3028) +#define BLSP1_UART2_APPS_CBCR (0x302C) +#define BLSP1_UART2_APPS_CMD_RCGR (0x3034) +#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) +#define BLSP1_UART2_APPS_M (0x303C) +#define BLSP1_UART2_APPS_N (0x3040) +#define BLSP1_UART2_APPS_D (0x3044) + +#endif diff --git a/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h new file mode 100644 index 000000000..36a902bd9 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm APQ8096 sysmap + * + * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> + */ +#ifndef _MACH_SYSMAP_APQ8096_H +#define _MACH_SYSMAP_APQ8096_H + +#define TLMM_BASE_ADDR (0x1010000) + +/* Strength (sdc1) */ +#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) + +/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x0000) +#define APCS_GPLL_ENA_VOTE (0x52000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) + +#define SDCC2_BCR (0x14000) /* block reset */ +#define SDCC2_APPS_CBCR (0x14004) /* branch control */ +#define SDCC2_AHB_CBCR (0x14008) +#define SDCC2_CMD_RCGR (0x14010) +#define SDCC2_CFG_RCGR (0x14014) +#define SDCC2_M (0x14018) +#define SDCC2_N (0x1401C) +#define SDCC2_D (0x14020) + +#define BLSP2_AHB_CBCR (0x25004) +#define BLSP2_UART2_APPS_CBCR (0x29004) +#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) +#define BLSP2_UART2_APPS_CFG_RCGR (0x29010) +#define BLSP2_UART2_APPS_M (0x29014) +#define BLSP2_UART2_APPS_N (0x29018) +#define BLSP2_UART2_APPS_D (0x2901C) + +#endif |