Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

82 files changed, 10992 insertions, 0 deletions

diff --git a/roms/u-boot/arch/arm/mach-socfpga/Kconfig b/roms/u-boot/arch/arm/mach-socfpga/Kconfig
new file mode 100644
index 000000000..0c3540623
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/Kconfig
@@ -0,0 +1,234 @@
+if ARCH_SOCFPGA
+
+config ERR_PTR_OFFSET
+	default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
+
+config NR_DRAM_BANKS
+	default 1
+
+config SOCFPGA_SECURE_VAB_AUTH
+	bool "Enable boot image authentication with Secure Device Manager"
+	depends on TARGET_SOCFPGA_AGILEX
+	select FIT_IMAGE_POST_PROCESS
+	select SHA384
+	select SHA512_ALGO
+	select SPL_FIT_IMAGE_POST_PROCESS
+	help
+	 All images loaded from FIT will be authenticated by Secure Device
+	 Manager.
+
+config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
+	bool "Allow non-FIT VAB signed images"
+	depends on SOCFPGA_SECURE_VAB_AUTH
+
+config SPL_SIZE_LIMIT
+	default 0x10000 if TARGET_SOCFPGA_GEN5
+
+config SPL_SIZE_LIMIT_PROVIDE_STACK
+	default 0x200 if TARGET_SOCFPGA_GEN5
+
+config SPL_STACK_R_ADDR
+	default 0x00800000 if TARGET_SOCFPGA_GEN5
+
+config SPL_SYS_MALLOC_F_LEN
+	default 0x800 if TARGET_SOCFPGA_GEN5
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
+	default 0xa2
+
+config SYS_MALLOC_F_LEN
+	default 0x2000 if TARGET_SOCFPGA_ARRIA10
+	default 0x2000 if TARGET_SOCFPGA_GEN5
+
+config SYS_TEXT_BASE
+	default 0x01000040 if TARGET_SOCFPGA_ARRIA10
+	default 0x01000040 if TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_AGILEX
+	bool
+	select ARMV8_MULTIENTRY
+	select ARMV8_SET_SMPEN
+	select BINMAN if SPL_ATF
+	select CLK
+	select FPGA_INTEL_SDM_MAILBOX
+	select NCORE_CACHE
+	select SPL_CLK if SPL
+	select TARGET_SOCFPGA_SOC64
+
+config TARGET_SOCFPGA_ARRIA5
+	bool
+	select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_ARRIA10
+	bool
+	select SPL_ALTERA_SDRAM
+	select SPL_BOARD_INIT if SPL
+	select SPL_CACHE if SPL
+	select CLK
+	select SPL_CLK if SPL
+	select DM_I2C
+	select DM_RESET
+	select SPL_DM_RESET if SPL
+	select REGMAP
+	select SPL_REGMAP if SPL
+	select SYSCON
+	select SPL_SYSCON if SPL
+	select ETH_DESIGNWARE_SOCFPGA
+	imply FPGA_SOCFPGA
+	imply SPL_USE_TINY_PRINTF
+
+config TARGET_SOCFPGA_CYCLONE5
+	bool
+	select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_GEN5
+	bool
+	select SPL_ALTERA_SDRAM
+	imply FPGA_SOCFPGA
+	imply SPL_SIZE_LIMIT_SUBTRACT_GD
+	imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
+	imply SPL_STACK_R
+	imply SPL_SYS_MALLOC_SIMPLE
+	imply SPL_USE_TINY_PRINTF
+
+config TARGET_SOCFPGA_SOC64
+	bool
+
+config TARGET_SOCFPGA_STRATIX10
+	bool
+	select ARMV8_MULTIENTRY
+	select ARMV8_SET_SMPEN
+	select BINMAN if SPL_ATF
+	select FPGA_INTEL_SDM_MAILBOX
+	select TARGET_SOCFPGA_SOC64
+
+choice
+	prompt "Altera SOCFPGA board select"
+	optional
+
+config TARGET_SOCFPGA_AGILEX_SOCDK
+	bool "Intel SOCFPGA SoCDK (Agilex)"
+	select TARGET_SOCFPGA_AGILEX
+
+config TARGET_SOCFPGA_ARIES_MCVEVK
+	bool "Aries MCVEVK (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+	bool "Altera SOCFPGA SoCDK (Arria 10)"
+	select TARGET_SOCFPGA_ARRIA10
+
+config TARGET_SOCFPGA_ARRIA5_SECU1
+	bool "ABB SECU1 (Arria V)"
+	select TARGET_SOCFPGA_ARRIA5
+	select VENDOR_KM
+
+config TARGET_SOCFPGA_ARRIA5_SOCDK
+	bool "Altera SOCFPGA SoCDK (Arria V)"
+	select TARGET_SOCFPGA_ARRIA5
+
+config TARGET_SOCFPGA_CYCLONE5_SOCDK
+	bool "Altera SOCFPGA SoCDK (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
+	bool "Devboards DBM-SoC1 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_EBV_SOCRATES
+	bool "EBV SoCrates (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_IS1
+	bool "IS1 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_SOFTING_VINING_FPGA
+	bool "Softing VIN|ING FPGA (Cyclone V)"
+	select BOARD_LATE_INIT
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_SR1500
+	bool "SR1500 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+	bool "Intel SOCFPGA SoCDK (Stratix 10)"
+	select TARGET_SOCFPGA_STRATIX10
+
+config TARGET_SOCFPGA_TERASIC_DE0_NANO
+	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_DE10_NANO
+	bool "Terasic DE10-Nano (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_DE1_SOC
+	bool "Terasic DE1-SoC (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_SOCKIT
+	bool "Terasic SoCkit (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+endchoice
+
+config SYS_BOARD
+	default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
+	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
+	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+	default "is1" if TARGET_SOCFPGA_IS1
+	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+	default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
+	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "sr1500" if TARGET_SOCFPGA_SR1500
+	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
+	default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+
+config SYS_VENDOR
+	default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
+	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
+	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
+	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
+	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
+	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
+	default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
+
+config SYS_SOC
+	default "socfpga"
+
+config SYS_CONFIG_NAME
+	default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
+	default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
+	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
+	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+	default "socfpga_is1" if TARGET_SOCFPGA_IS1
+	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
+	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+
+source "board/keymile/Kconfig"
+
+endif
diff --git a/roms/u-boot/arch/arm/mach-socfpga/Makefile b/roms/u-boot/arch/arm/mach-socfpga/Makefile
new file mode 100644
index 000000000..5779c5562
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/Makefile
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+# Copyright (C) 2017-2020 Intel Corporation <www.intel.com>
+
+obj-y	+= board.o
+obj-y	+= clock_manager.o
+obj-y	+= misc.o
+
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y	+= clock_manager_gen5.o
+obj-y	+= misc_gen5.o
+obj-y	+= reset_manager_gen5.o
+obj-y	+= scan_manager.o
+obj-y	+= system_manager_gen5.o
+obj-y	+= timer.o
+obj-y	+= wrap_pll_config.o
+obj-y	+= fpga_manager.o
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y	+= clock_manager_arria10.o
+obj-y	+= misc_arria10.o
+obj-y	+= pinmux_arria10.o
+obj-y	+= reset_manager_arria10.o
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y	+= clock_manager_s10.o
+obj-y	+= lowlevel_init_soc64.o
+obj-y	+= mailbox_s10.o
+obj-y	+= misc_s10.o
+obj-y	+= mmu-arm64_s10.o
+obj-y	+= reset_manager_s10.o
+obj-y	+= system_manager_soc64.o
+obj-y	+= timer_s10.o
+obj-y	+= wrap_handoff_soc64.o
+obj-y	+= wrap_pll_config_soc64.o
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y	+= clock_manager_agilex.o
+obj-y	+= lowlevel_init_soc64.o
+obj-y	+= mailbox_s10.o
+obj-y	+= misc_s10.o
+obj-y	+= mmu-arm64_s10.o
+obj-y	+= reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)	+= secure_vab.o
+obj-y	+= system_manager_soc64.o
+obj-y	+= timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)	+= vab.o
+obj-y	+= wrap_handoff_soc64.o
+obj-y	+= wrap_pll_config_soc64.o
+endif
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y	+= spl_gen5.o
+obj-y	+= freeze_controller.o
+obj-y	+= wrap_iocsr_config.o
+obj-y	+= wrap_pinmux_config.o
+obj-y	+= wrap_sdram_config.o
+endif
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y	+= spl_a10.o
+endif
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y	+= firewall.o
+obj-y	+= spl_s10.o
+obj-y	+= spl_soc64.o
+endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y	+= firewall.o
+obj-y	+= spl_agilex.o
+obj-y	+= spl_soc64.o
+endif
+else
+obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
+obj-$(CONFIG_SPL_ATF) += smc_api.o
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+# QTS-generated config file wrappers
+CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)
+CFLAGS_wrap_pinmux_config.o	+= -I$(srctree)/board/$(BOARDDIR)
+CFLAGS_wrap_pll_config.o	+= -I$(srctree)/board/$(BOARDDIR)
+CFLAGS_wrap_sdram_config.o	+= -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/roms/u-boot/arch/arm/mach-socfpga/board.c b/roms/u-boot/arch/arm/mach-socfpga/board.c
new file mode 100644
index 000000000..650122fcd
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/board.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Altera SoCFPGA common board code
+ *
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/secure_vab.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {
+#ifndef CONFIG_ARM64
+	/*
+	 * Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes
+	 * is disabled in ACTLR.
+	 * This is optional on CycloneV / ArriaV.
+	 * This is mandatory on Arria10, otherwise Linux refuses to boot.
+	 */
+	asm volatile(
+		"mcr p15, 0, %0, c1, c0, 1\n"
+		"mcr p15, 0, %0, c1, c0, 2\n"
+		"isb\n"
+		"dsb\n"
+	::"r"(0x0));
+#endif
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_GADGET
+struct dwc2_plat_otg_data socfpga_otg_data = {
+	.usb_gusbcfg	= 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node[2], count;
+	fdt_addr_t addr;
+
+	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
+					   COMPAT_ALTERA_SOCFPGA_DWC2USB,
+					   node, 2);
+	if (count <= 0)	/* No controller found. */
+		return 0;
+
+	addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
+	if (addr == FDT_ADDR_T_NONE) {
+		printf("UDC Controller has no 'reg' property!\n");
+		return -EINVAL;
+	}
+
+	/* Patch the address from OF into the controller pdata. */
+	socfpga_otg_data.regs_otg = addr;
+
+	return dwc2_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+	return 1;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) {
+		if (socfpga_vendor_authentication(p_image, p_size))
+			hang();
+	}
+}
+#endif
+
+#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
+void board_prep_linux(bootm_headers_t *images)
+{
+	if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
+	    !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
+		/*
+		 * Ensure the OS is always booted from FIT and with
+		 * VAB signed certificate
+		 */
+		if (!images->fit_uname_cfg) {
+			printf("Please use FIT with VAB signed images!\n");
+			hang();
+		}
+
+		env_set_hex("fdt_addr", (ulong)images->ft_addr);
+		debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
+	}
+
+	if (IS_ENABLED(CONFIG_CADENCE_QSPI)) {
+		if (env_get("linux_qspi_enable"))
+			run_command(env_get("linux_qspi_enable"), 0);
+	}
+}
+#endif
diff --git a/roms/u-boot/arch/arm/mach-socfpga/clock_manager.c b/roms/u-boot/arch/arm/mach-socfpga/clock_manager.c
new file mode 100644
index 000000000..9e645a425
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/clock_manager.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <command.h>
+#include <init.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void cm_wait_for_lock(u32 mask)
+{
+	u32 inter_val;
+	u32 retry = 0;
+	do {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+		inter_val = readl(socfpga_get_clkmgr_addr() +
+				  CLKMGR_INTER) & mask;
+#else
+		inter_val = readl(socfpga_get_clkmgr_addr() +
+				  CLKMGR_STAT) & mask;
+#endif
+		/* Wait for stable lock */
+		if (inter_val == mask)
+			retry++;
+		else
+			retry = 0;
+		if (retry >= 10)
+			break;
+	} while (1);
+}
+
+/* function to poll in the fsm busy bit */
+int cm_wait_for_fsm(void)
+{
+	return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
+				 CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
+				 false);
+}
+
+int set_cpu_clk_info(void)
+{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+	/* Calculate the clock frequencies required for drivers */
+	cm_get_l4_sp_clk_hz();
+	cm_get_mmc_controller_clk_hz();
+#endif
+
+	gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
+	gd->bd->bi_dsp_freq = 0;
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
+#else
+	gd->bd->bi_ddr_freq = 0;
+#endif
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+int cm_set_qspi_controller_clk_hz(u32 clk_hz)
+{
+	u32 reg;
+	u32 clk_khz;
+
+	/*
+	 * Store QSPI ref clock and set into sysmgr boot register.
+	 * Only clock freq in kHz degree is accepted due to limited bits[27:0]
+	 * is reserved for storing the QSPI clock freq into boot scratch cold0
+	 * register.
+	 */
+	if (clk_hz < 1000)
+		return -EINVAL;
+
+	clk_khz = clk_hz / 1000;
+	printf("QSPI: Reference clock at %d kHz\n", clk_khz);
+
+	reg = (readl(socfpga_get_sysmgr_addr() +
+		     SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
+		     ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
+
+	writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+
+	return 0;
+}
+
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+	return (readl(socfpga_get_sysmgr_addr() +
+		     SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
+		     SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000;
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	cm_print_clock_quick_summary();
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_showclocks,
+	"display clocks",
+	""
+);
+#endif
diff --git a/roms/u-boot/arch/arm/mach-socfpga/clock_manager_agilex.c b/roms/u-boot/arch/arm/mach-socfpga/clock_manager_agilex.c
new file mode 100644
index 000000000..e035c09aa
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/agilex-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+	struct udevice *dev;
+	struct clk clk;
+	ulong rate;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+					  DM_DRIVER_GET(socfpga_agilex_clk),
+					  &dev);
+	if (ret)
+		return 0;
+
+	clk.id = id;
+	ret = clk_request(dev, &clk);
+	if (ret < 0)
+		return 0;
+
+	rate = clk_get_rate(&clk);
+
+	clk_free(&clk);
+
+	if ((rate == (unsigned long)-ENOSYS) ||
+	    (rate == (unsigned long)-ENXIO) ||
+	    (rate == (unsigned long)-EIO)) {
+		debug("%s id %u: clk_get_rate err: %ld\n",
+		      __func__, id, rate);
+		return 0;
+	}
+
+	return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+	return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	return cm_get_rate_dm(AGILEX_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+	return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+	printf("MPU       %10d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+	printf("L4 Main	    %8d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+	printf("L4 sys free %8d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+	printf("L4 MP       %8d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+	printf("L4 SP       %8d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+	printf("SDMMC       %8d kHz\n",
+	       cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/clock_manager_arria10.c b/roms/u-boot/arch/arm/mach-socfpga/clock_manager_arria10.c
new file mode 100644
index 000000000..58d5d3fd8
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -0,0 +1,1014 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <clk.h>
+#include <dm/device-internal.h>
+#include <asm/arch/clock_manager.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_SPL_BUILD
+
+static u32 eosc1_hz;
+static u32 cb_intosc_hz;
+static u32 f2s_free_hz;
+
+struct mainpll_cfg {
+	u32 vco0_psrc;
+	u32 vco1_denom;
+	u32 vco1_numer;
+	u32 mpuclk;
+	u32 mpuclk_cnt;
+	u32 mpuclk_src;
+	u32 nocclk;
+	u32 nocclk_cnt;
+	u32 nocclk_src;
+	u32 cntr2clk_cnt;
+	u32 cntr3clk_cnt;
+	u32 cntr4clk_cnt;
+	u32 cntr5clk_cnt;
+	u32 cntr6clk_cnt;
+	u32 cntr7clk_cnt;
+	u32 cntr7clk_src;
+	u32 cntr8clk_cnt;
+	u32 cntr9clk_cnt;
+	u32 cntr9clk_src;
+	u32 cntr15clk_cnt;
+	u32 nocdiv_l4mainclk;
+	u32 nocdiv_l4mpclk;
+	u32 nocdiv_l4spclk;
+	u32 nocdiv_csatclk;
+	u32 nocdiv_cstraceclk;
+	u32 nocdiv_cspdbclk;
+};
+
+struct perpll_cfg {
+	u32 vco0_psrc;
+	u32 vco1_denom;
+	u32 vco1_numer;
+	u32 cntr2clk_cnt;
+	u32 cntr2clk_src;
+	u32 cntr3clk_cnt;
+	u32 cntr3clk_src;
+	u32 cntr4clk_cnt;
+	u32 cntr4clk_src;
+	u32 cntr5clk_cnt;
+	u32 cntr5clk_src;
+	u32 cntr6clk_cnt;
+	u32 cntr6clk_src;
+	u32 cntr7clk_cnt;
+	u32 cntr8clk_cnt;
+	u32 cntr8clk_src;
+	u32 cntr9clk_cnt;
+	u32 cntr9clk_src;
+	u32 emacctl_emac0sel;
+	u32 emacctl_emac1sel;
+	u32 emacctl_emac2sel;
+	u32 gpiodiv_gpiodbclk;
+};
+
+struct strtou32 {
+	const char *str;
+	const u32 val;
+};
+
+static const struct strtou32 mainpll_cfg_tab[] = {
+	{ "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) },
+	{ "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) },
+	{ "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) },
+	{ "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) },
+	{ "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) },
+	{ "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) },
+	{ "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) },
+	{ "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) },
+	{ "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) },
+	{ "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) },
+	{ "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) },
+	{ "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) },
+	{ "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) },
+	{ "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) },
+	{ "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) },
+	{ "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) },
+	{ "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) },
+	{ "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) },
+	{ "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) },
+	{ "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) },
+	{ "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) },
+	{ "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) },
+	{ "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) },
+	{ "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) },
+};
+
+static const struct strtou32 perpll_cfg_tab[] = {
+	{ "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) },
+	{ "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) },
+	{ "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) },
+	{ "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) },
+	{ "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) },
+	{ "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) },
+	{ "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) },
+	{ "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) },
+	{ "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) },
+	{ "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) },
+	{ "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) },
+	{ "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) },
+	{ "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) },
+	{ "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) },
+	{ "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) },
+	{ "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) },
+	{ "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) },
+	{ "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) },
+	{ "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) },
+	{ "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) },
+	{ "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) },
+};
+
+static const struct strtou32 alteragrp_cfg_tab[] = {
+	{ "nocclk", offsetof(struct mainpll_cfg, nocclk) },
+	{ "mpuclk", offsetof(struct mainpll_cfg, mpuclk) },
+};
+
+struct strtopu32 {
+	const char *str;
+	u32 *p;
+};
+
+const struct strtopu32 dt_to_val[] = {
+	{ "altera_arria10_hps_eosc1", &eosc1_hz },
+	{ "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz },
+	{ "altera_arria10_hps_f2h_free", &f2s_free_hz },
+};
+
+static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab,
+			int cfg_tab_len, void *cfg)
+{
+	int i;
+	u32 val;
+
+	for (i = 0; i < cfg_tab_len; i++) {
+		if (fdtdec_get_int_array(blob, node, cfg_tab[i].str, &val, 1)) {
+			/* could not find required property */
+			return -EINVAL;
+		}
+		*(u32 *)(cfg + cfg_tab[i].val) = val;
+	}
+
+	return 0;
+}
+
+static int of_get_input_clks(const void *blob)
+{
+	struct udevice *dev;
+	struct clk clk;
+	int i, ret;
+
+	for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
+		memset(&clk, 0, sizeof(clk));
+
+		ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str,
+						&dev);
+		if (ret)
+			return ret;
+
+		ret = clk_request(dev, &clk);
+		if (ret)
+			return ret;
+
+		*dt_to_val[i].p = clk_get_rate(&clk);
+	}
+
+	return 0;
+}
+
+static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
+			  struct perpll_cfg *per_cfg)
+{
+	int ret, node, child, len;
+	const char *node_name;
+
+	ret = of_get_input_clks(blob);
+	if (ret)
+		return ret;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT);
+
+	if (node < 0)
+		return -EINVAL;
+
+	child = fdt_first_subnode(blob, node);
+
+	if (child < 0)
+		return -EINVAL;
+
+	node_name = fdt_get_name(blob, child, &len);
+
+	while (node_name) {
+		if (!strcmp(node_name, "mainpll")) {
+			if (of_to_struct(blob, child, mainpll_cfg_tab,
+					 ARRAY_SIZE(mainpll_cfg_tab), main_cfg))
+				return -EINVAL;
+		} else if (!strcmp(node_name, "perpll")) {
+			if (of_to_struct(blob, child, perpll_cfg_tab,
+					 ARRAY_SIZE(perpll_cfg_tab), per_cfg))
+				return -EINVAL;
+		} else if (!strcmp(node_name, "alteragrp")) {
+			if (of_to_struct(blob, child, alteragrp_cfg_tab,
+					 ARRAY_SIZE(alteragrp_cfg_tab), main_cfg))
+				return -EINVAL;
+		}
+		child = fdt_next_subnode(blob, child);
+
+		if (child < 0)
+			break;
+
+		node_name = fdt_get_name(blob, child, &len);
+	}
+
+	return 0;
+}
+
+/* calculate the intended main VCO frequency based on handoff */
+static unsigned int cm_calc_handoff_main_vco_clk_hz
+					(struct mainpll_cfg *main_cfg)
+{
+	unsigned int clk_hz;
+
+	/* Check main VCO clock source: eosc, intosc or f2s? */
+	switch (main_cfg->vco0_psrc) {
+	case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
+		clk_hz = eosc1_hz;
+		break;
+	case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
+		clk_hz = cb_intosc_hz;
+		break;
+	case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
+		clk_hz = f2s_free_hz;
+		break;
+	default:
+		return 0;
+	}
+
+	/* calculate the VCO frequency */
+	clk_hz /= 1 + main_cfg->vco1_denom;
+	clk_hz *= 1 + main_cfg->vco1_numer;
+
+	return clk_hz;
+}
+
+/* calculate the intended periph VCO frequency based on handoff */
+static unsigned int cm_calc_handoff_periph_vco_clk_hz(
+		struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
+{
+	unsigned int clk_hz;
+
+	/* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */
+	switch (per_cfg->vco0_psrc) {
+	case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
+		clk_hz = eosc1_hz;
+		break;
+	case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
+		clk_hz = cb_intosc_hz;
+		break;
+	case CLKMGR_PERPLL_VCO0_PSRC_F2S:
+		clk_hz = f2s_free_hz;
+		break;
+	case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
+		clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
+		clk_hz /= main_cfg->cntr15clk_cnt;
+		break;
+	default:
+		return 0;
+	}
+
+	/* calculate the VCO frequency */
+	clk_hz /= 1 + per_cfg->vco1_denom;
+	clk_hz *= 1 + per_cfg->vco1_numer;
+
+	return clk_hz;
+}
+
+/* calculate the intended MPU clock frequency based on handoff */
+static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg,
+					       struct perpll_cfg *per_cfg)
+{
+	unsigned int clk_hz;
+
+	/* Check MPU clock source: main, periph, osc1, intosc or f2s? */
+	switch (main_cfg->mpuclk_src) {
+	case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
+		clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
+		clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK)
+			   + 1;
+		break;
+	case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
+		clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
+		clk_hz /= ((main_cfg->mpuclk >>
+			   CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
+			   CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
+		break;
+	case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
+		clk_hz = eosc1_hz;
+		break;
+	case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
+		clk_hz = cb_intosc_hz;
+		break;
+	case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
+		clk_hz = f2s_free_hz;
+		break;
+	default:
+		return 0;
+	}
+
+	clk_hz /= main_cfg->mpuclk_cnt + 1;
+	return clk_hz;
+}
+
+/* calculate the intended NOC clock frequency based on handoff */
+static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg,
+					       struct perpll_cfg *per_cfg)
+{
+	unsigned int clk_hz;
+
+	/* Check MPU clock source: main, periph, osc1, intosc or f2s? */
+	switch (main_cfg->nocclk_src) {
+	case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN:
+		clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
+		clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK)
+			 + 1;
+		break;
+	case CLKMGR_MAINPLL_NOCCLK_SRC_PERI:
+		clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
+		clk_hz /= ((main_cfg->nocclk >>
+			   CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
+			   CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1;
+		break;
+	case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1:
+		clk_hz = eosc1_hz;
+		break;
+	case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC:
+		clk_hz = cb_intosc_hz;
+		break;
+	case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA:
+		clk_hz = f2s_free_hz;
+		break;
+	default:
+		return 0;
+	}
+
+	clk_hz /= main_cfg->nocclk_cnt + 1;
+	return clk_hz;
+}
+
+/* return 1 if PLL ramp is required */
+static int cm_is_pll_ramp_required(int main0periph1,
+				   struct mainpll_cfg *main_cfg,
+				   struct perpll_cfg *per_cfg)
+{
+	/* Check for main PLL */
+	if (main0periph1 == 0) {
+		/*
+		 * PLL ramp is not required if both MPU clock and NOC clock are
+		 * not sourced from main PLL
+		 */
+		if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
+		    main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
+			return 0;
+
+		/*
+		 * PLL ramp is required if MPU clock is sourced from main PLL
+		 * and MPU clock is over 900MHz (as advised by HW team)
+		 */
+		if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
+		    (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
+		     CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
+			return 1;
+
+		/*
+		 * PLL ramp is required if NOC clock is sourced from main PLL
+		 * and NOC clock is over 300MHz (as advised by HW team)
+		 */
+		if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN &&
+		    (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
+		     CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
+			return 2;
+
+	} else if (main0periph1 == 1) {
+		/*
+		 * PLL ramp is not required if both MPU clock and NOC clock are
+		 * not sourced from periph PLL
+		 */
+		if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
+		    main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
+			return 0;
+
+		/*
+		 * PLL ramp is required if MPU clock are source from periph PLL
+		 * and MPU clock is over 900MHz (as advised by HW team)
+		 */
+		if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
+		    (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
+		     CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
+			return 1;
+
+		/*
+		 * PLL ramp is required if NOC clock are source from periph PLL
+		 * and NOC clock is over 300MHz (as advised by HW team)
+		 */
+		if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI &&
+		    (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
+		     CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
+			return 2;
+	}
+
+	return 0;
+}
+
+static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg,
+			      struct perpll_cfg *per_cfg,
+			      u32 safe_hz, u32 clk_hz)
+{
+	u32 cnt;
+	u32 clk;
+	u32 shift;
+	u32 mask;
+	u32 denom;
+
+	if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
+		cnt = main_cfg->mpuclk_cnt;
+		clk = main_cfg->mpuclk;
+		shift = 0;
+		mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
+		denom = main_cfg->vco1_denom;
+	} else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
+		cnt = main_cfg->nocclk_cnt;
+		clk = main_cfg->nocclk;
+		shift = 0;
+		mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
+		denom = main_cfg->vco1_denom;
+	} else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
+		cnt = main_cfg->mpuclk_cnt;
+		clk = main_cfg->mpuclk;
+		shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB;
+		mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
+		denom = per_cfg->vco1_denom;
+	} else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
+		cnt = main_cfg->nocclk_cnt;
+		clk = main_cfg->nocclk;
+		shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB;
+		mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
+		denom = per_cfg->vco1_denom;
+	} else {
+		return 0;
+	}
+
+	return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) *
+		(1 + denom) - 1;
+}
+
+/*
+ * Calculate the new PLL numerator which is based on existing DTS hand off and
+ * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the
+ * numerator while maintaining denominator as denominator will influence the
+ * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final
+ * value for numerator is minus with 1 to cater our register value
+ * representation.
+ */
+static unsigned int cm_calc_safe_pll_numer(int main0periph1,
+					   struct mainpll_cfg *main_cfg,
+					   struct perpll_cfg *per_cfg,
+					   unsigned int safe_hz)
+{
+	unsigned int clk_hz = 0;
+
+	/* Check for main PLL */
+	if (main0periph1 == 0) {
+		/* Check main VCO clock source: eosc, intosc or f2s? */
+		switch (main_cfg->vco0_psrc) {
+		case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
+			clk_hz = eosc1_hz;
+			break;
+		case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
+			clk_hz = cb_intosc_hz;
+			break;
+		case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
+			clk_hz = f2s_free_hz;
+			break;
+		default:
+			return 0;
+		}
+	} else if (main0periph1 == 1) {
+		/* Check periph VCO clock source: eosc, intosc, f2s, mainpll */
+		switch (per_cfg->vco0_psrc) {
+		case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
+			clk_hz = eosc1_hz;
+			break;
+		case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
+			clk_hz = cb_intosc_hz;
+			break;
+		case CLKMGR_PERPLL_VCO0_PSRC_F2S:
+			clk_hz = f2s_free_hz;
+			break;
+		case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
+			clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
+			clk_hz /= main_cfg->cntr15clk_cnt;
+			break;
+		default:
+			return 0;
+		}
+	} else {
+		return 0;
+	}
+
+	return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz);
+}
+
+/* ramping the main PLL to final value */
+static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
+			     struct perpll_cfg *per_cfg,
+			     unsigned int pll_ramp_main_hz)
+{
+	unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
+
+	/* find out the increment value */
+	if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
+		clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
+		clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
+	} else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
+		clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
+		clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
+	}
+
+	/* execute the ramping here */
+	for (clk_hz = pll_ramp_main_hz + clk_incr_hz;
+	     clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
+		writel((main_cfg->vco1_denom <<
+			CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+			cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
+			socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
+		mdelay(1);
+		cm_wait_for_lock(LOCKED_MASK);
+	}
+	writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+		main_cfg->vco1_numer,
+		socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
+	mdelay(1);
+	cm_wait_for_lock(LOCKED_MASK);
+}
+
+/* ramping the periph PLL to final value */
+static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
+			       struct perpll_cfg *per_cfg,
+			       unsigned int pll_ramp_periph_hz)
+{
+	unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
+
+	/* find out the increment value */
+	if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
+		clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
+		clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
+	} else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
+		clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
+		clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
+	}
+	/* execute the ramping here */
+	for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
+	     clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
+		writel((per_cfg->vco1_denom <<
+			      CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+			      cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
+						     clk_hz),
+			      socfpga_get_clkmgr_addr() +
+			      CLKMGR_A10_PERPLL_VCO1);
+		mdelay(1);
+		cm_wait_for_lock(LOCKED_MASK);
+	}
+	writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+		      per_cfg->vco1_numer,
+		      socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
+	mdelay(1);
+	cm_wait_for_lock(LOCKED_MASK);
+}
+
+/*
+ * Setup clocks while making no assumptions of the
+ * previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ *
+ * Put all plls in bypass
+ *
+ * Put all plls VCO registers back to reset value (bgpwr dwn).
+ *
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ *
+ * Delay 5 us.
+ *
+ * Deassert bg pwr dn and set numerator and denominator
+ *
+ * Start 7 us timer.
+ *
+ * set internal dividers
+ *
+ * Wait for 7 us timer.
+ *
+ * Enable plls
+ *
+ * Set external dividers while plls are locking
+ *
+ * Wait for pll lock
+ *
+ * Assert/deassert outreset all.
+ *
+ * Take all pll's out of bypass
+ *
+ * Clear safe mode
+ *
+ * set source main and peripheral clocks
+ *
+ * Ungate clocks
+ */
+
+static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
+{
+	unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0,
+		ramp_required;
+
+	/* gate off all mainpll clock excpet HW managed clock */
+	writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
+		CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
+		socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENR);
+
+	/* now we can gate off the rest of the peripheral clocks */
+	writel(0, socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EN);
+
+	/* Put all plls in external bypass */
+	writel(CLKMGR_MAINPLL_BYPASS_RESET,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSS);
+	writel(CLKMGR_PERPLL_BYPASS_RESET,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSS);
+
+	/*
+	 * Put all plls VCO registers back to reset value.
+	 * Some code might have messed with them. At same time set the
+	 * desired clock source
+	 */
+	writel(CLKMGR_MAINPLL_VCO0_RESET |
+	       CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
+	       (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0);
+
+	writel(CLKMGR_PERPLL_VCO0_RESET |
+	       CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
+	       (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0);
+
+	writel(CLKMGR_MAINPLL_VCO1_RESET,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
+	writel(CLKMGR_PERPLL_VCO1_RESET,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
+
+	/* clear the interrupt register status register */
+	writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
+		CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
+		CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
+		CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
+		CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
+		CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
+		CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
+		CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
+		socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR);
+
+	/* Program VCO Numerator and Denominator for main PLL */
+	ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
+	if (ramp_required) {
+		/* set main PLL to safe starting threshold frequency */
+		if (ramp_required == 1)
+			pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
+		else if (ramp_required == 2)
+			pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
+
+		writel((main_cfg->vco1_denom <<
+			CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+			cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
+					       pll_ramp_main_hz),
+			socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
+	} else
+		writel((main_cfg->vco1_denom <<
+		       CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+		       main_cfg->vco1_numer,
+		       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
+
+	/* Program VCO Numerator and Denominator for periph PLL */
+	ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
+	if (ramp_required) {
+		/* set periph PLL to safe starting threshold frequency */
+		if (ramp_required == 1)
+			pll_ramp_periph_hz =
+				CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
+		else if (ramp_required == 2)
+			pll_ramp_periph_hz =
+				CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
+
+		writel((per_cfg->vco1_denom <<
+			CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+			cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
+					       pll_ramp_periph_hz),
+			socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
+	} else
+		writel((per_cfg->vco1_denom <<
+			CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+			per_cfg->vco1_numer,
+			socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
+
+	/* Wait for at least 5 us */
+	udelay(5);
+
+	/* Now deassert BGPWRDN and PWRDN */
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
+		     CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
+		     CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
+		     CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
+		     CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
+
+	/* Wait for at least 7 us */
+	udelay(7);
+
+	/* enable the VCO and disable the external regulator to PLL */
+	writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
+		~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
+		CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
+		socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0);
+	writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0) &
+		~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
+		CLKMGR_PERPLL_VCO0_EN_SET_MSK,
+		socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0);
+
+	/* setup all the main PLL counter and clock source */
+	writel(main_cfg->nocclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_NOCCLK);
+	writel(main_cfg->mpuclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_MPUCLK);
+
+	/* main_emaca_clk divider */
+	writel(main_cfg->cntr2clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR2CLK);
+	/* main_emacb_clk divider */
+	writel(main_cfg->cntr3clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR3CLK);
+	/* main_emac_ptp_clk divider */
+	writel(main_cfg->cntr4clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR4CLK);
+	/* main_gpio_db_clk divider */
+	writel(main_cfg->cntr5clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR5CLK);
+	/* main_sdmmc_clk divider */
+	writel(main_cfg->cntr6clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR6CLK);
+	/* main_s2f_user0_clk divider */
+	writel(main_cfg->cntr7clk_cnt |
+	       (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR7CLK);
+	/* main_s2f_user1_clk divider */
+	writel(main_cfg->cntr8clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR8CLK);
+	/* main_hmc_pll_clk divider */
+	writel(main_cfg->cntr9clk_cnt |
+	       (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR9CLK);
+	/* main_periph_ref_clk divider */
+	writel(main_cfg->cntr15clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR15CLK);
+
+	/* setup all the peripheral PLL counter and clock source */
+	/* peri_emaca_clk divider */
+	writel(per_cfg->cntr2clk_cnt |
+	       (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR2CLK);
+	/* peri_emacb_clk divider */
+	writel(per_cfg->cntr3clk_cnt |
+	       (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR3CLK);
+	/* peri_emac_ptp_clk divider */
+	writel(per_cfg->cntr4clk_cnt |
+	       (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR4CLK);
+	/* peri_gpio_db_clk divider */
+	writel(per_cfg->cntr5clk_cnt |
+	       (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR5CLK);
+	/* peri_sdmmc_clk divider */
+	writel(per_cfg->cntr6clk_cnt |
+	       (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR6CLK);
+	/* peri_s2f_user0_clk divider */
+	writel(per_cfg->cntr7clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR7CLK);
+	/* peri_s2f_user1_clk divider */
+	writel(per_cfg->cntr8clk_cnt |
+	       (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR8CLK);
+	/* peri_hmc_pll_clk divider */
+	writel(per_cfg->cntr9clk_cnt,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR9CLK);
+
+	/* setup all the external PLL counter */
+	/* mpu wrapper / external divider */
+	writel(main_cfg->mpuclk_cnt |
+	       (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_MPUCLK);
+	/* NOC wrapper / external divider */
+	writel(main_cfg->nocclk_cnt |
+	       (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCCLK);
+	/* NOC subclock divider such as l4 */
+	writel(main_cfg->nocdiv_l4mainclk |
+	       (main_cfg->nocdiv_l4mpclk <<
+		CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) |
+	       (main_cfg->nocdiv_l4spclk <<
+		CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) |
+	       (main_cfg->nocdiv_csatclk <<
+		CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) |
+	       (main_cfg->nocdiv_cstraceclk <<
+		CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
+	       (main_cfg->nocdiv_cspdbclk <<
+		CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCDIV);
+	/* gpio_db external divider */
+	writel(per_cfg->gpiodiv_gpiodbclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_GPIOFIV);
+
+	/* setup the EMAC clock mux select */
+	writel((per_cfg->emacctl_emac0sel <<
+		CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) |
+	       (per_cfg->emacctl_emac1sel <<
+		CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
+	       (per_cfg->emacctl_emac2sel <<
+		CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EMACCTL);
+
+	/* at this stage, check for PLL lock status */
+	cm_wait_for_lock(LOCKED_MASK);
+
+	/*
+	 * after locking, but before taking out of bypass,
+	 * assert/deassert outresetall
+	 */
+	/* assert mainpll outresetall */
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
+		     CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
+	/* assert perpll outresetall */
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
+		     CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
+	/* de-assert mainpll outresetall */
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
+		     CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
+	/* de-assert perpll outresetall */
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
+		     CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
+
+	/* Take all PLLs out of bypass when boot mode is cleared. */
+	/* release mainpll from bypass */
+	writel(CLKMGR_MAINPLL_BYPASS_RESET,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR);
+	/* wait till Clock Manager is not busy */
+	cm_wait_for_fsm();
+
+	/* release perpll from bypass */
+	writel(CLKMGR_PERPLL_BYPASS_RESET,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR);
+	/* wait till Clock Manager is not busy */
+	cm_wait_for_fsm();
+
+	/* clear boot mode */
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
+		     CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
+	/* wait till Clock Manager is not busy */
+	cm_wait_for_fsm();
+
+	/* At here, we need to ramp to final value if needed */
+	if (pll_ramp_main_hz != 0)
+		cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz);
+	if (pll_ramp_periph_hz != 0)
+		cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz);
+
+	/* Now ungate non-hw-managed clocks */
+	writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
+	       CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENS);
+	writel(CLKMGR_PERPLL_EN_RESET,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_ENS);
+
+	/* Clear the loss lock and slip bits as they might set during
+	clock reconfiguration */
+	writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
+	       CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
+	       CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
+	       CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
+	       CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
+	       CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR);
+
+	return 0;
+}
+
+static void cm_use_intosc(void)
+{
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
+		     CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
+}
+
+int cm_basic_init(const void *blob)
+{
+	struct mainpll_cfg main_cfg;
+	struct perpll_cfg per_cfg;
+	int rval;
+
+	/* initialize to zero for use case of optional node */
+	memset(&main_cfg, 0, sizeof(main_cfg));
+	memset(&per_cfg, 0, sizeof(per_cfg));
+
+	rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg);
+	if (rval)
+		return rval;
+
+	cm_use_intosc();
+
+	return cm_full_cfg(&main_cfg, &per_cfg);
+}
+#endif
+
+static u32 cm_get_rate_dm(char *name)
+{
+	struct uclass *uc;
+	struct udevice *dev = NULL;
+	struct clk clk = { 0 };
+	ulong rate;
+	int ret;
+
+	/* Device addresses start at 1 */
+	ret = uclass_get(UCLASS_CLK, &uc);
+	if (ret)
+		return 0;
+
+	ret = uclass_get_device_by_name(UCLASS_CLK, name, &dev);
+	if (ret)
+		return 0;
+
+	ret = device_probe(dev);
+	if (ret)
+		return 0;
+
+	ret = clk_request(dev, &clk);
+	if (ret)
+		return 0;
+
+	rate = clk_get_rate(&clk);
+
+	clk_free(&clk);
+
+	return rate;
+}
+
+static u32 cm_get_rate_dm_khz(char *name)
+{
+	return cm_get_rate_dm(name) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	return cm_get_rate_dm("main_mpu_base_clk");
+}
+
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+	return cm_get_rate_dm("qspi_clk");
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+	return cm_get_rate_dm("l4_sp_clk");
+}
+
+void cm_print_clock_quick_summary(void)
+{
+	printf("MPU       %10d kHz\n", cm_get_rate_dm_khz("main_mpu_base_clk"));
+	printf("MMC         %8d kHz\n", cm_get_rate_dm_khz("sdmmc_clk"));
+	printf("QSPI        %8d kHz\n", cm_get_rate_dm_khz("qspi_clk"));
+	printf("SPI         %8d kHz\n", cm_get_rate_dm_khz("spi_m_clk"));
+	printf("EOSC1       %8d kHz\n", cm_get_rate_dm_khz("osc1"));
+	printf("cb_intosc   %8d kHz\n", cm_get_rate_dm_khz("cb_intosc_ls_clk"));
+	printf("f2s_free    %8d kHz\n", cm_get_rate_dm_khz("f2s_free_clk"));
+	printf("Main VCO    %8d kHz\n", cm_get_rate_dm_khz("main_pll@40"));
+	printf("NOC         %8d kHz\n", cm_get_rate_dm_khz("main_noc_base_clk"));
+	printf("L4 Main	    %8d kHz\n", cm_get_rate_dm_khz("l4_main_clk"));
+	printf("L4 MP       %8d kHz\n", cm_get_rate_dm_khz("l4_mp_clk"));
+	printf("L4 SP       %8d kHz\n", cm_get_rate_dm_khz("l4_sp_clk"));
+	printf("L4 sys free %8d kHz\n", cm_get_rate_dm_khz("l4_sys_free_clk"));
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/clock_manager_gen5.c b/roms/u-boot/arch/arm/mach-socfpga/clock_manager_gen5.c
new file mode 100644
index 000000000..8fa276079
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -0,0 +1,562 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
+#include <time.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <asm/arch/clock_manager.h>
+#include <wait_bit.h>
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void cm_write_bypass(u32 val)
+{
+	writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_BYPASS);
+	cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void cm_write_ctrl(u32 val)
+{
+	writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL);
+	cm_wait_for_fsm();
+}
+
+/* function to write a clock register that has phase information */
+static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
+{
+	int ret;
+
+	/* poll until phase is zero */
+	ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
+	if (ret)
+		return ret;
+
+	writel(value, reg_address);
+
+	return wait_for_bit_le32(reg_address, mask, false, 20000, false);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ * Put all plls in bypass
+ * Put all plls VCO registers back to reset value (bandgap power down).
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ * Delay 5 us.
+ * Deassert bandgap power down and set numerator and denominator
+ * Start 7 us timer.
+ * set internal dividers
+ * Wait for 7 us timer.
+ * Enable plls
+ * Set external dividers while plls are locking
+ * Wait for pll lock
+ * Assert/deassert outreset all.
+ * Take all pll's out of bypass
+ * Clear safe mode
+ * set source main and peripheral clocks
+ * Ungate clocks
+ */
+
+int cm_basic_init(const struct cm_config * const cfg)
+{
+	unsigned long end;
+	int ret;
+
+	/* Start by being paranoid and gate all sw managed clocks */
+
+	/*
+	 * We need to disable nandclk
+	 * and then do another apb access before disabling
+	 * gatting off the rest of the periperal clocks.
+	 */
+	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
+		readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN),
+		socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
+
+	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
+	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
+		socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN);
+
+	writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN);
+
+	/* now we can gate off the rest of the peripheral clocks */
+	writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
+
+	/* Put all plls in bypass */
+	cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
+			CLKMGR_BYPASS_MAINPLL);
+
+	/* Put all plls VCO registers back to reset value. */
+	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
+
+	/*
+	 * The clocks to the flash devices and the L4_MAIN clocks can
+	 * glitch when coming out of safe mode if their source values
+	 * are different from their reset value.  So the trick it to
+	 * put them back to their reset state, and change input
+	 * after exiting safe mode but before ungating the clocks.
+	 */
+	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
+		      socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
+	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
+		      socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
+
+	/* read back for the required 5 us delay. */
+	readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+	readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+	readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
+
+
+	/*
+	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
+	 * with numerator and denominator.
+	 */
+	writel(cfg->main_vco_base,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+	writel(cfg->peri_vco_base,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+	writel(cfg->sdram_vco_base,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
+
+	/*
+	 * Time starts here. Must wait 7 us from
+	 * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
+	 */
+	end = timer_get_us() + 7;
+
+	/* main mpu */
+	writel(cfg->mpuclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK);
+
+	/* altera group mpuclk */
+	writel(cfg->altera_grp_mpuclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK);
+
+	/* main main clock */
+	writel(cfg->mainclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINCLK);
+
+	/* main for dbg */
+	writel(cfg->dbgatclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGATCLK);
+
+	/* main for cfgs2fuser0clk */
+	writel(cfg->cfg2fuser0clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK);
+
+	/* Peri emac0 50 MHz default to RMII */
+	writel(cfg->emac0clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC0CLK);
+
+	/* Peri emac1 50 MHz default to RMII */
+	writel(cfg->emac1clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC1CLK);
+
+	/* Peri QSPI */
+	writel(cfg->mainqspiclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
+
+	writel(cfg->perqspiclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERQSPICLK);
+
+	/* Peri pernandsdmmcclk */
+	writel(cfg->mainnandsdmmcclk,
+	       socfpga_get_clkmgr_addr() +
+	       CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
+
+	writel(cfg->pernandsdmmcclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
+
+	/* Peri perbaseclk */
+	writel(cfg->perbaseclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK);
+
+	/* Peri s2fuser1clk */
+	writel(cfg->s2fuser1clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_S2FUSER1CLK);
+
+	/* 7 us must have elapsed before we can enable the VCO */
+	while (timer_get_us() < end)
+		;
+
+	/* Enable vco */
+	/* main pll vco */
+	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+
+	/* periferal pll */
+	writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+
+	/* sdram pll vco */
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
+
+	/* L3 MP and L3 SP */
+	writel(cfg->maindiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV);
+
+	writel(cfg->dbgdiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGDIV);
+
+	writel(cfg->tracediv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_TRACEDIV);
+
+	/* L4 MP, L4 SP, can0, and can1 */
+	writel(cfg->perdiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_DIV);
+
+	writel(cfg->gpiodiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_GPIODIV);
+
+	cm_wait_for_lock(LOCKED_MASK);
+
+	/* write the sdram clock counters before toggling outreset all */
+	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
+
+	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK);
+
+	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQCLK);
+
+	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK);
+
+	/*
+	 * after locking, but before taking out of bypass
+	 * assert/deassert outresetall
+	 */
+	u32 mainvco = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_MAINPLL_VCO);
+
+	/* assert main outresetall */
+	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+
+	u32 periphvco = readl(socfpga_get_clkmgr_addr() +
+			      CLKMGR_GEN5_PERPLL_VCO);
+
+	/* assert pheriph outresetall */
+	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+
+	/* assert sdram outresetall */
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN |
+	       CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
+
+	/* deassert main outresetall */
+	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+
+	/* deassert pheriph outresetall */
+	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+
+	/* deassert sdram outresetall */
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
+
+	/*
+	 * now that we've toggled outreset all, all the clocks
+	 * are aligned nicely; so we can change any phase.
+	 */
+	ret = cm_write_with_phase(cfg->ddrdqsclk,
+				  (const void *)(socfpga_get_clkmgr_addr() +
+				  CLKMGR_GEN5_SDRPLL_DDRDQSCLK),
+				  CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
+	if (ret)
+		return ret;
+
+	/* SDRAM DDR2XDQSCLK */
+	ret = cm_write_with_phase(cfg->ddr2xdqsclk,
+				  (const void *)(socfpga_get_clkmgr_addr() +
+				  CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK),
+				  CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
+	if (ret)
+		return ret;
+
+	ret = cm_write_with_phase(cfg->ddrdqclk,
+				  (const void *)(socfpga_get_clkmgr_addr() +
+				  CLKMGR_GEN5_SDRPLL_DDRDQCLK),
+				  CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
+	if (ret)
+		return ret;
+
+	ret = cm_write_with_phase(cfg->s2fuser2clk,
+				  (const void *)(socfpga_get_clkmgr_addr() +
+				  CLKMGR_GEN5_SDRPLL_S2FUSER2CLK),
+				  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
+	if (ret)
+		return ret;
+
+	/* Take all three PLLs out of bypass when safe mode is cleared. */
+	cm_write_bypass(0);
+
+	/* clear safe mode */
+	cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL) |
+		      CLKMGR_CTRL_SAFEMODE);
+
+	/*
+	 * now that safe mode is clear with clocks gated
+	 * it safe to change the source mux for the flashes the the L4_MAIN
+	 */
+	writel(cfg->persrc,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
+	writel(cfg->l4src,
+	       socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
+
+	/* Now ungate non-hw-managed clocks */
+	writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN);
+	writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
+	writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN);
+
+	/* Clear the loss of lock bits (write 1 to clear) */
+	writel(CLKMGR_INTER_SDRPLLLOST_MASK |
+		      CLKMGR_INTER_PERPLLLOST_MASK |
+		      CLKMGR_INTER_MAINPLLLOST_MASK,
+		      socfpga_get_clkmgr_addr() + CLKMGR_GEN5_INTER);
+
+	return 0;
+}
+
+static unsigned int cm_get_main_vco_clk_hz(void)
+{
+	u32 reg, clock;
+
+	/* get the main VCO clock */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+	clock = cm_get_osc_clk_hz(1);
+	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
+		  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
+	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
+		  CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+	return clock;
+}
+
+static unsigned int cm_get_per_vco_clk_hz(void)
+{
+	u32 reg, clock = 0;
+
+	/* identify PER PLL clock source */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
+	      CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
+	if (reg == CLKMGR_VCO_SSRC_EOSC1)
+		clock = cm_get_osc_clk_hz(1);
+	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+		clock = cm_get_osc_clk_hz(2);
+	else if (reg == CLKMGR_VCO_SSRC_F2S)
+		clock = cm_get_f2s_per_ref_clk_hz();
+
+	/* get the PER VCO clock */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
+		  CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
+	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
+		  CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+	return clock;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	u32 reg, clock;
+
+	clock = cm_get_main_vco_clk_hz();
+
+	/* get the MPU clock */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK);
+	clock /= (reg + 1);
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK);
+	clock /= (reg + 1);
+	return clock;
+}
+
+unsigned long cm_get_sdram_clk_hz(void)
+{
+	u32 reg, clock = 0;
+
+	/* identify SDRAM PLL clock source */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
+	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
+	      CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
+	if (reg == CLKMGR_VCO_SSRC_EOSC1)
+		clock = cm_get_osc_clk_hz(1);
+	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+		clock = cm_get_osc_clk_hz(2);
+	else if (reg == CLKMGR_VCO_SSRC_F2S)
+		clock = cm_get_f2s_sdr_ref_clk_hz();
+
+	/* get the SDRAM VCO clock */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
+	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
+		  CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
+	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
+		  CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
+
+	/* get the SDRAM (DDR_DQS) clock */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
+	reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
+	      CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
+	clock /= (reg + 1);
+
+	return clock;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+	u32 reg, clock = 0;
+
+	/* identify the source of L4 SP clock */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
+	reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
+	      CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
+
+	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
+		clock = cm_get_main_vco_clk_hz();
+
+		/* get the clock prior L4 SP divider (main clk) */
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_ALTR_MAINCLK);
+		clock /= (reg + 1);
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_MAINPLL_MAINCLK);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
+		clock = cm_get_per_vco_clk_hz();
+
+		/* get the clock prior L4 SP divider (periph_base_clk) */
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_PERPLL_PERBASECLK);
+		clock /= (reg + 1);
+	}
+
+	/* get the L4 SP clock which supplied to UART */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV);
+	reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
+	      CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
+	clock = clock / (1 << reg);
+
+	return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+	u32 reg, clock = 0;
+
+	/* identify the source of MMC clock */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
+	reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
+	      CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
+
+	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
+		clock = cm_get_f2s_per_ref_clk_hz();
+	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
+		clock = cm_get_main_vco_clk_hz();
+
+		/* get the SDMMC clock */
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
+		clock = cm_get_per_vco_clk_hz();
+
+		/* get the SDMMC clock */
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
+		clock /= (reg + 1);
+	}
+
+	/* further divide by 4 as we have fixed divider at wrapper */
+	clock /= 4;
+	return clock;
+}
+
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+	u32 reg, clock = 0;
+
+	/* identify the source of QSPI clock */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
+	reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
+	      CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
+
+	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
+		clock = cm_get_f2s_per_ref_clk_hz();
+	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
+		clock = cm_get_main_vco_clk_hz();
+
+		/* get the qspi clock */
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
+		clock = cm_get_per_vco_clk_hz();
+
+		/* get the qspi clock */
+		reg = readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_GEN5_PERPLL_PERQSPICLK);
+		clock /= (reg + 1);
+	}
+
+	return clock;
+}
+
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+	u32 reg, clock = 0;
+
+	clock = cm_get_per_vco_clk_hz();
+
+	/* get the clock prior L4 SP divider (periph_base_clk) */
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK);
+	clock /= (reg + 1);
+
+	return clock;
+}
+
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+	*rate = cm_get_spi_controller_clk_hz();
+
+	return 0;
+}
+
+void cm_print_clock_quick_summary(void)
+{
+	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
+	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
+	printf("EOSC1       %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
+	printf("EOSC2       %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
+	printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
+	printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
+	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
+	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+	printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/clock_manager_s10.c b/roms/u-boot/arch/arm/mach-socfpga/clock_manager_s10.c
new file mode 100644
index 000000000..4b4f0749d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/handoff_soc64.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void cm_write_bypass_mainpll(u32 val)
+{
+	writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_BYPASS);
+	cm_wait_for_fsm();
+}
+
+static void cm_write_bypass_perpll(u32 val)
+{
+	writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_BYPASS);
+	cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void cm_write_ctrl(u32 val)
+{
+	writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL);
+	cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+void cm_basic_init(const struct cm_config * const cfg)
+{
+	u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;
+
+	if (cfg == 0)
+		return;
+
+	/* Put all plls in bypass */
+	cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
+	cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
+
+	/* setup main PLL dividers where calculate the vcocalib value */
+	mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+		CLKMGR_FDBCK_MDIV_MASK;
+	refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		     CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+	mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+	hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+		CLKMGR_HSCNT_CONST;
+	vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+		   ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+		   CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+	writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+		~CLKMGR_PLLGLOB_RST_MASK),
+		socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
+	writel(cfg->main_pll_fdbck,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
+	writel(vcocalib,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_VCOCALIB);
+	writel(cfg->main_pll_pllc0,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC0);
+	writel(cfg->main_pll_pllc1,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC1);
+	writel(cfg->main_pll_nocdiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCDIV);
+
+	/* setup peripheral PLL dividers */
+	/* calculate the vcocalib value */
+	mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+		CLKMGR_FDBCK_MDIV_MASK;
+	refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		     CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+	mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+	hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+		CLKMGR_HSCNT_CONST;
+	vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+		   ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+		   CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+	writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+		~CLKMGR_PLLGLOB_RST_MASK),
+		socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
+	writel(cfg->per_pll_fdbck,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
+	writel(vcocalib,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_VCOCALIB);
+	writel(cfg->per_pll_pllc0,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC0);
+	writel(cfg->per_pll_pllc1,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC1);
+	writel(cfg->per_pll_emacctl,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EMACCTL);
+	writel(cfg->per_pll_gpiodiv,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_GPIODIV);
+
+	/* Take both PLL out of reset and power up */
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB,
+		     CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB,
+		     CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+#define LOCKED_MASK \
+	(CLKMGR_STAT_MAINPLL_LOCKED | \
+	CLKMGR_STAT_PERPLL_LOCKED)
+
+	cm_wait_for_lock(LOCKED_MASK);
+
+	/*
+	 * Dividers for C2 to C9 only init after PLLs are lock. As dividers
+	 * only take effect upon value change, we shall set a maximum value as
+	 * default value.
+	 */
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
+	writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
+
+	writel(cfg->main_pll_mpuclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
+	writel(cfg->main_pll_nocclk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
+	writel(cfg->main_pll_cntr2clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
+	writel(cfg->main_pll_cntr3clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
+	writel(cfg->main_pll_cntr4clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
+	writel(cfg->main_pll_cntr5clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
+	writel(cfg->main_pll_cntr6clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
+	writel(cfg->main_pll_cntr7clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
+	writel(cfg->main_pll_cntr8clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
+	writel(cfg->main_pll_cntr9clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
+	writel(cfg->per_pll_cntr2clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
+	writel(cfg->per_pll_cntr3clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
+	writel(cfg->per_pll_cntr4clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
+	writel(cfg->per_pll_cntr5clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
+	writel(cfg->per_pll_cntr6clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
+	writel(cfg->per_pll_cntr7clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
+	writel(cfg->per_pll_cntr8clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
+	writel(cfg->per_pll_cntr9clk,
+	       socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
+
+	/* Take all PLLs out of bypass */
+	cm_write_bypass_mainpll(0);
+	cm_write_bypass_perpll(0);
+
+	/* clear safe mode / out of boot mode */
+	cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL) &
+		      ~(CLKMGR_CTRL_SAFEMODE));
+
+	/* Now ungate non-hw-managed clocks */
+	writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_EN);
+	writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EN);
+
+	/* Clear the loss of lock bits (write 1 to clear) */
+	writel(CLKMGR_INTER_PERPLLLOST_MASK |
+		      CLKMGR_INTER_MAINPLLLOST_MASK,
+		      socfpga_get_clkmgr_addr() + CLKMGR_S10_INTRCLR);
+}
+
+static unsigned long cm_get_main_vco_clk_hz(void)
+{
+	 unsigned long fref, refdiv, mdiv, reg, vco;
+
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
+
+	fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+		CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+	switch (fref) {
+	case CLKMGR_VCO_PSRC_EOSC1:
+		fref = cm_get_osc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_INTOSC:
+		fref = cm_get_intosc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_F2S:
+		fref = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		  CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
+	mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+	vco = fref / refdiv;
+	vco = vco * (CLKMGR_MDIV_CONST + mdiv);
+	return vco;
+}
+
+static unsigned long cm_get_per_vco_clk_hz(void)
+{
+	unsigned long fref, refdiv, mdiv, reg, vco;
+
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
+
+	fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+		CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+	switch (fref) {
+	case CLKMGR_VCO_PSRC_EOSC1:
+		fref = cm_get_osc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_INTOSC:
+		fref = cm_get_intosc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_F2S:
+		fref = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+		  CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+	reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
+	mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+	vco = fref / refdiv;
+	vco = vco * (CLKMGR_MDIV_CONST + mdiv);
+	return vco;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	unsigned long clock = readl(socfpga_get_clkmgr_addr() +
+				    CLKMGR_S10_MAINPLL_MPUCLK);
+
+	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = cm_get_main_vco_clk_hz();
+		clock /= (readl(socfpga_get_clkmgr_addr() +
+				CLKMGR_S10_MAINPLL_PLLC0) &
+			  CLKMGR_PLLC0_DIV_MASK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = cm_get_per_vco_clk_hz();
+		clock /= (readl(socfpga_get_clkmgr_addr() +
+				CLKMGR_S10_PERPLL_PLLC0) &
+			  CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+			    CLKMGR_S10_MAINPLL_MPUCLK) & CLKMGR_CLKCNT_MSK);
+	return clock;
+}
+
+unsigned int cm_get_l3_main_clk_hz(void)
+{
+	u32 clock = readl(socfpga_get_clkmgr_addr() +
+			  CLKMGR_S10_MAINPLL_NOCCLK);
+
+	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = cm_get_main_vco_clk_hz();
+		clock /= (readl(socfpga_get_clkmgr_addr() +
+				CLKMGR_S10_MAINPLL_PLLC1) &
+			  CLKMGR_PLLC0_DIV_MASK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = cm_get_per_vco_clk_hz();
+		clock /= (readl(socfpga_get_clkmgr_addr() +
+			  CLKMGR_S10_PERPLL_PLLC1) & CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+		      CLKMGR_S10_MAINPLL_NOCCLK) & CLKMGR_CLKCNT_MSK);
+	return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+	u32 clock = readl(socfpga_get_clkmgr_addr() +
+			  CLKMGR_S10_PERPLL_CNTR6CLK);
+
+	clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = cm_get_l3_main_clk_hz();
+		clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+				    CLKMGR_S10_MAINPLL_CNTR6CLK) &
+			      CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = cm_get_l3_main_clk_hz();
+		clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+				    CLKMGR_S10_PERPLL_CNTR6CLK) &
+			      CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+	return clock / 4;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+	u32 clock = cm_get_l3_main_clk_hz();
+
+	clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
+			       CLKMGR_S10_MAINPLL_NOCDIV) >>
+			 CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
+	return clock;
+}
+
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+	u32 clock = cm_get_l3_main_clk_hz();
+
+	clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
+			       CLKMGR_S10_MAINPLL_NOCDIV) >>
+			 CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
+	return clock;
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+	return cm_get_l3_main_clk_hz() / 4;
+}
+
+void cm_print_clock_quick_summary(void)
+{
+	printf("MPU         %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
+	printf("L3 main     %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
+	printf("Main VCO    %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000));
+	printf("Per VCO     %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000));
+	printf("EOSC1       %d kHz\n", cm_get_osc_clk_hz() / 1000);
+	printf("HPS MMC     %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+	printf("UART        %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/firewall.c b/roms/u-boot/arch/arm/mach-socfpga/firewall.c
new file mode 100644
index 000000000..69229dc65
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/firewall.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/system_manager.h>
+
+static void firewall_l4_per_disable(void)
+{
+	const struct socfpga_firwall_l4_per *firwall_l4_per_base =
+		(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
+	u32 i;
+	const u32 *addr[] = {
+			&firwall_l4_per_base->nand,
+			&firwall_l4_per_base->nand_data,
+			&firwall_l4_per_base->usb0,
+			&firwall_l4_per_base->usb1,
+			&firwall_l4_per_base->spim0,
+			&firwall_l4_per_base->spim1,
+			&firwall_l4_per_base->emac0,
+			&firwall_l4_per_base->emac1,
+			&firwall_l4_per_base->emac2,
+			&firwall_l4_per_base->sdmmc,
+			&firwall_l4_per_base->gpio0,
+			&firwall_l4_per_base->gpio1,
+			&firwall_l4_per_base->i2c0,
+			&firwall_l4_per_base->i2c1,
+			&firwall_l4_per_base->i2c2,
+			&firwall_l4_per_base->i2c3,
+			&firwall_l4_per_base->i2c4,
+			&firwall_l4_per_base->timer0,
+			&firwall_l4_per_base->timer1,
+			&firwall_l4_per_base->uart0,
+			&firwall_l4_per_base->uart1
+			};
+
+	/*
+	 * The following lines of code will enable non-secure access
+	 * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
+	 * is needed as most OS run in non-secure mode. Thus we need to
+	 * enable non-secure access to these peripherals in order for the
+	 * OS to use these peripherals.
+	 */
+	for (i = 0; i < ARRAY_SIZE(addr); i++)
+		writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
+}
+
+static void firewall_l4_sys_disable(void)
+{
+	const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
+		(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
+	u32 i;
+	const u32 *addr[] = {
+			&firwall_l4_sys_base->dma_ecc,
+			&firwall_l4_sys_base->emac0rx_ecc,
+			&firwall_l4_sys_base->emac0tx_ecc,
+			&firwall_l4_sys_base->emac1rx_ecc,
+			&firwall_l4_sys_base->emac1tx_ecc,
+			&firwall_l4_sys_base->emac2rx_ecc,
+			&firwall_l4_sys_base->emac2tx_ecc,
+			&firwall_l4_sys_base->nand_ecc,
+			&firwall_l4_sys_base->nand_read_ecc,
+			&firwall_l4_sys_base->nand_write_ecc,
+			&firwall_l4_sys_base->ocram_ecc,
+			&firwall_l4_sys_base->sdmmc_ecc,
+			&firwall_l4_sys_base->usb0_ecc,
+			&firwall_l4_sys_base->usb1_ecc,
+			&firwall_l4_sys_base->clock_manager,
+			&firwall_l4_sys_base->io_manager,
+			&firwall_l4_sys_base->reset_manager,
+			&firwall_l4_sys_base->system_manager,
+			&firwall_l4_sys_base->watchdog0,
+			&firwall_l4_sys_base->watchdog1,
+			&firwall_l4_sys_base->watchdog2,
+			&firwall_l4_sys_base->watchdog3
+		};
+
+	for (i = 0; i < ARRAY_SIZE(addr); i++)
+		writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
+}
+
+static void firewall_bridge_disable(void)
+{
+	/* disable lwsocf2fpga and soc2fpga bridge security */
+	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
+	writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
+}
+
+void firewall_setup(void)
+{
+	firewall_l4_per_disable();
+	firewall_l4_sys_disable();
+	firewall_bridge_disable();
+
+	/* disable SMMU security */
+	writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
+
+	/* enable non-secure interface to DMA330 DMA and peripherals */
+	writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);
+	writel(SYSMGR_DMAPERIPH_ALL_NS,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/fpga_manager.c b/roms/u-boot/arch/arm/mach-socfpga/fpga_manager.c
new file mode 100644
index 000000000..18d692c63
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/fpga_manager.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * This file contains only support functions used also by the SoCFPGA
+ * platform code, the real meat is located in drivers/fpga/socfpga.c .
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+/* Timeout count */
+#define FPGA_TIMEOUT_CNT		0x1000000
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+	unsigned long val;
+
+	val = readl(&fpgamgr_regs->gpio_ext_porta);
+	return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+int fpgamgr_get_mode(void)
+{
+	unsigned long val;
+
+	val = readl(&fpgamgr_regs->stat);
+	return val & FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+	/* Check for init done signal */
+	if (!is_fpgamgr_initdone_high())
+		return 0;
+
+	/* Check again to avoid false glitches */
+	if (!is_fpgamgr_initdone_high())
+		return 0;
+
+	if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+		return 0;
+
+	return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+	unsigned long i;
+
+	/* If FPGA is blank, wait till WD invoke warm reset */
+	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+		/* check for init done signal */
+		if (!is_fpgamgr_initdone_high())
+			continue;
+		/* check again to avoid false glitches */
+		if (!is_fpgamgr_initdone_high())
+			continue;
+		return 1;
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/freeze_controller.c b/roms/u-boot/arch/arm/mach-socfpga/freeze_controller.c
new file mode 100644
index 000000000..561d3408c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/freeze_controller.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/freeze_controller.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+
+static const struct socfpga_freeze_controller *freeze_controller_base =
+		(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Default state from cold reset is FREEZE_ALL; the global
+ * flag is set to TRUE to indicate the IO banks are frozen
+ */
+static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
+	= { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
+	FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
+
+/* Freeze HPS IOs */
+void sys_mgr_frzctrl_freeze_req(void)
+{
+	u32 ioctrl_reg_offset;
+	u32 reg_value;
+	u32 reg_cfg_mask;
+	u32 channel_id;
+
+	/* select software FSM */
+	writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);
+
+	/* Freeze channel 0 to 2 */
+	for (channel_id = 0; channel_id <= 2; channel_id++) {
+		ioctrl_reg_offset = (u32)(
+			&freeze_controller_base->vioctrl + channel_id);
+
+		/*
+		 * Assert active low enrnsl, plniotri
+		 * and niotri signals
+		 */
+		reg_cfg_mask =
+			SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+		clrbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * Assert active low bhniotri signal and de-assert
+		 * active high csrdone
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+		clrbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/* Set global flag to indicate channel is frozen */
+		frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+	}
+
+	/* Freeze channel 3 */
+	/*
+	 * Assert active low enrnsl, plniotri and
+	 * niotri signals
+	 */
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+	clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+	/*
+	 * assert active low bhniotri & nfrzdrv signals,
+	 * de-assert active high csrdone and assert
+	 * active high frzreg and nfrzdrv signals
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
+	reg_value
+		= (reg_value & ~reg_cfg_mask)
+		| SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/*
+	 * assert active high reinit signal and de-assert
+	 * active high pllbiasen signals
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_value
+		= (reg_value &
+		~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
+		| SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/* Set global flag to indicate channel is frozen */
+	frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+}
+
+/* Unfreeze/Thaw HPS IOs */
+void sys_mgr_frzctrl_thaw_req(void)
+{
+	u32 ioctrl_reg_offset;
+	u32 reg_cfg_mask;
+	u32 reg_value;
+	u32 channel_id;
+	unsigned long eosc1_freq;
+
+	/* select software FSM */
+	writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);
+
+	/* Thaw channel 0 to 2 */
+	for (channel_id = 0; channel_id <= 2; channel_id++) {
+		ioctrl_reg_offset
+			= (u32)(&freeze_controller_base->vioctrl + channel_id);
+
+		/*
+		 * Assert active low bhniotri signal and
+		 * de-assert active high csrdone
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+		setbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * de-assert active low plniotri and niotri signals
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+		setbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * de-assert active low enrnsl signal
+		 */
+		setbits_le32(ioctrl_reg_offset,
+			SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
+
+		/* Set global flag to indicate channel is thawed */
+		frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
+	}
+
+	/* Thaw channel 3 */
+	/* de-assert active high reinit signal */
+	clrbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * assert active high pllbiasen signals
+	 */
+	setbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
+
+	/* Delay 1000 intosc cycles. The intosc is based on eosc1. */
+	eosc1_freq = cm_get_osc_clk_hz(1) / 1000;	/* kHz */
+	udelay(DIV_ROUND_UP(1000000, eosc1_freq));
+
+	/*
+	 * de-assert active low bhniotri signals,
+	 * assert active high csrdone and nfrzdrv signal
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_value = (reg_value
+		| SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
+		& ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/*
+	 * Delay 33 intosc
+	 * Use worst case which is fatest eosc1=50MHz, delay required
+	 * is 1/50MHz * 33 = 660ns ~= 1us
+	 */
+	udelay(1);
+
+	/* de-assert active low plniotri and niotri signals */
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+
+	setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * de-assert active high frzreg signal
+	 */
+	clrbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * de-assert active low enrnsl signal
+	 */
+	setbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
+
+	/* Set global flag to indicate channel is thawed */
+	frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
new file mode 100644
index 000000000..b947cc072
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
+ */
+
+#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
+#define _SOCFPGA_A10_BASE_HARDWARE_H_
+
+#define SOCFPGA_EMAC0_ADDRESS			0xff800000
+#define SOCFPGA_EMAC1_ADDRESS			0xff802000
+#define SOCFPGA_EMAC2_ADDRESS			0xff804000
+#define SOCFPGA_SDMMC_ADDRESS			0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS		0xff809000
+#define SOCFPGA_QSPIDATA_ADDRESS		0xffa00000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xffcfa000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS		0xffcfe400
+#define SOCFPGA_FPGAMGRREGS_ADDRESS		0xffd03000
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd06000
+#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS	0xffd07000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd07200
+#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS	0xffd07300
+#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS	0xffd07400
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_MPUSCU_ADDRESS			0xffffc000
+#define SOCFPGA_MPUL2_ADDRESS			0xfffff000
+#define SOCFPGA_I2C0_ADDRESS			0xffc02200
+#define SOCFPGA_I2C1_ADDRESS			0xffc02300
+#define SOCFPGA_I2C2_ADDRESS			0xffc02400
+#define SOCFPGA_I2C3_ADDRESS			0xffc02500
+#define SOCFPGA_I2C4_ADDRESS			0xffc02600
+
+#define SOCFPGA_ECC_OCRAM_ADDRESS		0xff8c3000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS		0xffd00100
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd05000
+
+#define SOCFPGA_SDR_ADDRESS			0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST		0xffd11000
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xffd12400
+#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS	0xffd13200
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS	0xffd13300
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS		0xffd13400
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST		0xffd13500
+
+#define SOCFPGA_PHYS_OCRAM_SIZE			0x40000
+
+#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
new file mode 100644
index 000000000..da966fb45
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_FPGA_SLAVES_ADDRESS	0xc0000000
+#define SOCFPGA_STM_ADDRESS		0xfc000000
+#define SOCFPGA_DAP_ADDRESS		0xff000000
+#define SOCFPGA_EMAC0_ADDRESS		0xff700000
+#define SOCFPGA_EMAC1_ADDRESS		0xff702000
+#define SOCFPGA_SDMMC_ADDRESS		0xff704000
+#define SOCFPGA_QSPI_ADDRESS		0xff705000
+#define SOCFPGA_GPIO0_ADDRESS		0xff708000
+#define SOCFPGA_GPIO1_ADDRESS		0xff709000
+#define SOCFPGA_GPIO2_ADDRESS		0xff70a000
+#define SOCFPGA_L3REGS_ADDRESS		0xff800000
+#define SOCFPGA_USB0_ADDRESS		0xffb00000
+#define SOCFPGA_USB1_ADDRESS		0xffb40000
+#define SOCFPGA_CAN0_ADDRESS		0xffc00000
+#define SOCFPGA_CAN1_ADDRESS		0xffc01000
+#define SOCFPGA_UART0_ADDRESS		0xffc02000
+#define SOCFPGA_UART1_ADDRESS		0xffc03000
+#define SOCFPGA_I2C0_ADDRESS		0xffc04000
+#define SOCFPGA_I2C1_ADDRESS		0xffc05000
+#define SOCFPGA_I2C2_ADDRESS		0xffc06000
+#define SOCFPGA_I2C3_ADDRESS		0xffc07000
+#define SOCFPGA_SDR_ADDRESS		0xffc20000
+#define SOCFPGA_L4WD0_ADDRESS		0xffd02000
+#define SOCFPGA_L4WD1_ADDRESS		0xffd03000
+#define SOCFPGA_CLKMGR_ADDRESS		0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS		0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS		0xffd08000
+#define SOCFPGA_SPIS0_ADDRESS		0xffe02000
+#define SOCFPGA_SPIS1_ADDRESS		0xffe03000
+#define SOCFPGA_SPIM0_ADDRESS		0xfff00000
+#define SOCFPGA_SPIM1_ADDRESS		0xfff01000
+#define SOCFPGA_SCANMGR_ADDRESS		0xfff02000
+#define SOCFPGA_ROM_ADDRESS		0xfffd0000
+#define SOCFPGA_MPUSCU_ADDRESS		0xfffec000
+#define SOCFPGA_MPUL2_ADDRESS		0xfffef000
+#define SOCFPGA_OCRAM_ADDRESS		0xffff0000
+#define SOCFPGA_LWFPGASLAVES_ADDRESS	0xff200000
+#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS	0xff400000
+#define SOCFPGA_HPS2FPGAREGS_ADDRESS	0xff500000
+#define SOCFPGA_FPGA2HPSREGS_ADDRESS	0xff600000
+#define SOCFPGA_FPGAMGRREGS_ADDRESS	0xff706000
+#define SOCFPGA_ACPIDMAP_ADDRESS	0xff707000
+#define SOCFPGA_NANDDATA_ADDRESS	0xff900000
+#define SOCFPGA_QSPIDATA_ADDRESS	0xffa00000
+#define SOCFPGA_NANDREGS_ADDRESS	0xffb80000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS	0xffb90000
+#define SOCFPGA_SPTIMER0_ADDRESS	0xffc08000
+#define SOCFPGA_SPTIMER1_ADDRESS	0xffc09000
+#define SOCFPGA_OSC1TIMER0_ADDRESS	0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS	0xffd01000
+#define SOCFPGA_DMANONSECURE_ADDRESS	0xffe00000
+#define SOCFPGA_DMASECURE_ADDRESS	0xffe01000
+
+#define SOCFPGA_PHYS_OCRAM_SIZE		0x10000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100644
index 000000000..d3eca65e9
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_CCU_ADDRESS			0xf7000000
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
+#define SOCFPGA_SDR_ADDRESS			0xf8011000
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020200
+#else
+#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020100
+#endif
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_MAILBOX_ADDRESS			0xffa30000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER1_ADDRESS		0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER			0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS			0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300
+#define SOCFPGA_FIREWALL_TCU			0xffd21400
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+#define GICD_BASE				0xfffc1000
+#define GICC_BASE				0xfffc2000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/boot0.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/boot0.h
new file mode 100644
index 000000000..c78def506
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Specialty padding for the Altera SoCFPGA preloader image
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+_start:
+	ARM_VECTORS
+
+#ifdef CONFIG_SPL_BUILD
+	.balignl 64,0xf33db33f;
+
+	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
+	.word	0xc01df00d;	/* Version, flags, length */
+	.word	0xcafec0d3;	/* Checksum, zero-pad */
+	nop;
+
+	b reset;		/* SoCFPGA Gen5 jumps here */
+	b reset;		/* SoCFPGA Gen10 trampoline */
+	nop;
+	nop;
+#endif
+
+#endif /* __BOOT0_H */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager.h
new file mode 100644
index 000000000..2f9b471af
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ */
+
+#ifndef _CLOCK_MANAGER_H_
+#define _CLOCK_MANAGER_H_
+
+phys_addr_t socfpga_get_clkmgr_addr(void);
+
+#ifndef __ASSEMBLY__
+void cm_wait_for_lock(u32 mask);
+int cm_wait_for_fsm(void);
+void cm_print_clock_quick_summary(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
+int cm_set_qspi_controller_clk_hz(u32 clk_hz);
+#endif
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/clock_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/clock_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/clock_manager_s10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#include <asm/arch/clock_manager_agilex.h>
+#endif
+
+#endif /* _CLOCK_MANAGER_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
new file mode 100644
index 000000000..386e82a4e
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLOCK_MANAGER_AGILEX_
+#define _CLOCK_MANAGER_AGILEX_
+
+unsigned long cm_get_mpu_clk_hz(void);
+
+#include <asm/arch/clock_manager_soc64.h>
+#include "../../../../../drivers/clk/altera/clk-agilex.h"
+
+#endif /* _CLOCK_MANAGER_AGILEX_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
new file mode 100644
index 000000000..798d3741b
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ */
+
+#ifndef CLOCK_MANAGER_ARRIA10
+#define CLOCK_MANAGER_ARRIA10
+
+#ifndef __ASSEMBLY__
+
+#include <linux/bitops.h>
+
+/* Clock manager group */
+#define CLKMGR_A10_CTRL				0x00
+#define CLKMGR_A10_INTR				0x04
+#define CLKMGR_A10_STAT				0x1c
+/* MainPLL group */
+#define CLKMGR_A10_MAINPLL_VCO0			0x40
+#define CLKMGR_A10_MAINPLL_VCO1			0x44
+#define CLKMGR_A10_MAINPLL_EN			0x48
+#define CLKMGR_A10_MAINPLL_ENS			0x4c
+#define CLKMGR_A10_MAINPLL_ENR			0x50
+#define CLKMGR_A10_MAINPLL_BYPASS		0x54
+#define CLKMGR_A10_MAINPLL_BYPASSS		0x58
+#define CLKMGR_A10_MAINPLL_BYPASSR		0x5c
+#define CLKMGR_A10_MAINPLL_MPUCLK		0x60
+#define CLKMGR_A10_MAINPLL_NOCCLK		0x64
+#define CLKMGR_A10_MAINPLL_CNTR2CLK		0x68
+#define CLKMGR_A10_MAINPLL_CNTR3CLK		0x6c
+#define CLKMGR_A10_MAINPLL_CNTR4CLK		0x70
+#define CLKMGR_A10_MAINPLL_CNTR5CLK		0x74
+#define CLKMGR_A10_MAINPLL_CNTR6CLK		0x78
+#define CLKMGR_A10_MAINPLL_CNTR7CLK		0x7c
+#define CLKMGR_A10_MAINPLL_CNTR8CLK		0x80
+#define CLKMGR_A10_MAINPLL_CNTR9CLK		0x84
+#define CLKMGR_A10_MAINPLL_CNTR15CLK		0x9c
+#define CLKMGR_A10_MAINPLL_NOCDIV		0xa8
+/* Peripheral PLL group */
+#define CLKMGR_A10_PERPLL_VCO0			0xc0
+#define CLKMGR_A10_PERPLL_VCO1			0xc4
+#define CLKMGR_A10_PERPLL_EN			0xc8
+#define CLKMGR_A10_PERPLL_ENS			0xcc
+#define CLKMGR_A10_PERPLL_ENR			0xd0
+#define CLKMGR_A10_PERPLL_BYPASS		0xd4
+#define CLKMGR_A10_PERPLL_BYPASSS		0xd8
+#define CLKMGR_A10_PERPLL_BYPASSR		0xdc
+#define CLKMGR_A10_PERPLL_CNTR2CLK		0xe8
+#define CLKMGR_A10_PERPLL_CNTR3CLK		0xec
+#define CLKMGR_A10_PERPLL_CNTR4CLK		0xf0
+#define CLKMGR_A10_PERPLL_CNTR5CLK		0xf4
+#define CLKMGR_A10_PERPLL_CNTR6CLK		0xf8
+#define CLKMGR_A10_PERPLL_CNTR7CLK		0xfc
+#define CLKMGR_A10_PERPLL_CNTR8CLK		0x100
+#define CLKMGR_A10_PERPLL_CNTR9CLK		0x104
+#define CLKMGR_A10_PERPLL_EMACCTL		0x128
+#define CLKMGR_A10_PERPLL_GPIOFIV		0x12c
+/* Altera group */
+#define CLKMGR_A10_ALTR_MPUCLK			0x140
+#define CLKMGR_A10_ALTR_NOCCLK			0x144
+
+#define CLKMGR_STAT				CLKMGR_A10_STAT
+#define CLKMGR_INTER				CLKMGR_A10_INTER
+#define CLKMGR_PERPLL_EN			CLKMGR_A10_PERPLL_EN
+
+#ifdef CONFIG_SPL_BUILD
+int cm_basic_init(const void *blob);
+#endif
+
+#include <linux/bitops.h>
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
+#endif /* __ASSEMBLY__ */
+
+#define LOCKED_MASK	(CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
+			 CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
+
+/* value */
+#define CLKMGR_MAINPLL_BYPASS_RESET			0x0000003f
+#define CLKMGR_PERPLL_BYPASS_RESET			0x000000ff
+#define CLKMGR_MAINPLL_VCO0_RESET			0x00010053
+#define CLKMGR_MAINPLL_VCO1_RESET			0x00010001
+#define CLKMGR_PERPLL_VCO0_RESET			0x00010053
+#define CLKMGR_PERPLL_VCO1_RESET			0x00010001
+#define CLKMGR_MAINPLL_VCO0_PSRC_EOSC			0x0
+#define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC		0x1
+#define CLKMGR_MAINPLL_VCO0_PSRC_F2S			0x2
+#define CLKMGR_PERPLL_VCO0_PSRC_EOSC			0x0
+#define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC		0x1
+#define CLKMGR_PERPLL_VCO0_PSRC_F2S			0x2
+#define CLKMGR_PERPLL_VCO0_PSRC_MAIN			0x3
+
+/* mask */
+#define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK		BIT(6)
+#define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK	BIT(7)
+#define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK	BIT(8)
+#define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK		BIT(9)
+#define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK		BIT(17)
+#define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK		BIT(0)
+#define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK		BIT(1)
+#define CLKMGR_MAINPLL_VCO0_EN_SET_MSK			BIT(2)
+#define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK		BIT(3)
+#define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK		BIT(4)
+#define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK		BIT(0)
+#define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK		BIT(1)
+#define CLKMGR_PERPLL_VCO0_EN_SET_MSK			BIT(2)
+#define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK		BIT(3)
+#define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK		BIT(4)
+#define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK	BIT(0)
+#define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK	BIT(1)
+#define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK		BIT(2)
+#define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK		BIT(3)
+#define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK	BIT(8)
+#define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK		BIT(9)
+#define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK	BIT(10)
+#define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK		BIT(11)
+#define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK		BIT(0)
+#define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK	0x00000300
+#define CLKMGR_PERPLL_EN_RESET				0x00000f7f
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		BIT(5)
+#define CLKMGR_MAINPLL_VCO0_PSRC_MSK			0x00000003
+#define CLKMGR_MAINPLL_VCO1_NUMER_MSK			0x00001fff
+#define CLKMGR_MAINPLL_VCO1_DENOM_MSK			0x0000003f
+#define CLKMGR_MAINPLL_CNTRCLK_MSK			0x000003ff
+#define CLKMGR_PERPLL_VCO0_PSRC_MSK			0x00000003
+#define CLKMGR_PERPLL_VCO1_NUMER_MSK			0x00001fff
+#define CLKMGR_PERPLL_VCO1_DENOM_MSK			0x0000003f
+#define CLKMGR_PERPLL_CNTRCLK_MSK			0x000003ff
+#define CLKMGR_MAINPLL_MPUCLK_SRC_MSK			0x00000007
+#define CLKMGR_MAINPLL_MPUCLK_CNT_MSK			0x000003ff
+#define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN			0
+#define CLKMGR_MAINPLL_MPUCLK_SRC_PERI			1
+#define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1			2
+#define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC		3
+#define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA			4
+#define CLKMGR_MAINPLL_NOCDIV_MSK			0x00000003
+#define CLKMGR_MAINPLL_NOCCLK_CNT_MSK			0x000003ff
+#define CLKMGR_MAINPLL_NOCCLK_SRC_MSK			0x00000007
+#define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN			0
+#define CLKMGR_MAINPLL_NOCCLK_SRC_PERI			1
+#define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1			2
+#define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC		3
+#define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA			4
+
+#define CLKMGR_PERPLLGRP_SRC_MSK			0x00000007
+#define CLKMGR_PERPLLGRP_SRC_MAIN			0
+#define CLKMGR_PERPLLGRP_SRC_PERI			1
+#define CLKMGR_PERPLLGRP_SRC_OSC1			2
+#define CLKMGR_PERPLLGRP_SRC_INTOSC			3
+#define CLKMGR_PERPLLGRP_SRC_FPGA			4
+
+/* bit shifting macro */
+#define CLKMGR_MAINPLL_VCO0_PSRC_LSB		8
+#define CLKMGR_PERPLL_VCO0_PSRC_LSB		8
+#define CLKMGR_MAINPLL_VCO1_DENOM_LSB		16
+#define CLKMGR_PERPLL_VCO1_DENOM_LSB		16
+#define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB	16
+#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB		16
+#define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB	0
+#define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB	8
+#define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB	16
+#define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB	24
+#define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB	26
+#define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB	28
+#define CLKMGR_MAINPLL_MPUCLK_SRC_LSB		16
+#define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB	16
+#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB		16
+#define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB		16
+#define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB	26
+#define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB	27
+#define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB	28
+
+/* PLL ramping work around */
+#define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ	900000000
+#define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ	300000000
+#define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ	100000000
+#define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ	33000000
+
+#define CLKMGR_STAT_BUSY			BIT(0)
+
+#endif /* CLOCK_MANAGER_ARRIA10 */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
new file mode 100644
index 000000000..4cc1268b4
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ */
+
+#ifndef _CLOCK_MANAGER_GEN5_H_
+#define _CLOCK_MANAGER_GEN5_H_
+
+#ifndef __ASSEMBLY__
+
+#include <linux/bitops.h>
+
+struct cm_config {
+	/* main group */
+	u32 main_vco_base;
+	u32 mpuclk;
+	u32 mainclk;
+	u32 dbgatclk;
+	u32 mainqspiclk;
+	u32 mainnandsdmmcclk;
+	u32 cfg2fuser0clk;
+	u32 maindiv;
+	u32 dbgdiv;
+	u32 tracediv;
+	u32 l4src;
+
+	/* peripheral group */
+	u32 peri_vco_base;
+	u32 emac0clk;
+	u32 emac1clk;
+	u32 perqspiclk;
+	u32 pernandsdmmcclk;
+	u32 perbaseclk;
+	u32 s2fuser1clk;
+	u32 perdiv;
+	u32 gpiodiv;
+	u32 persrc;
+
+	/* sdram pll group */
+	u32 sdram_vco_base;
+	u32 ddrdqsclk;
+	u32 ddr2xdqsclk;
+	u32 ddrdqclk;
+	u32 s2fuser2clk;
+
+	/* altera group */
+	u32 altera_grp_mpuclk;
+};
+
+/* Clock manager group */
+#define CLKMGR_GEN5_CTRL			0x00
+#define CLKMGR_GEN5_BYPASS			0x04
+#define CLKMGR_GEN5_INTER			0x08
+#define CLKMGR_GEN5_STAT			0x14
+/* MainPLL group */
+#define CLKMGR_GEN5_MAINPLL_VCO			0x40
+#define CLKMGR_GEN5_MAINPLL_MISC		0x44
+#define CLKMGR_GEN5_MAINPLL_MPUCLK		0x48
+#define CLKMGR_GEN5_MAINPLL_MAINCLK		0x4c
+#define CLKMGR_GEN5_MAINPLL_DBGATCLK		0x50
+#define CLKMGR_GEN5_MAINPLL_MAINQSPICLK		0x54
+#define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK	0x58
+#define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK	0x5c
+#define CLKMGR_GEN5_MAINPLL_EN			0x60
+#define CLKMGR_GEN5_MAINPLL_MAINDIV		0x64
+#define CLKMGR_GEN5_MAINPLL_DBGDIV		0x68
+#define CLKMGR_GEN5_MAINPLL_TRACEDIV		0x6c
+#define CLKMGR_GEN5_MAINPLL_L4SRC		0x70
+/* Peripheral PLL group */
+#define CLKMGR_GEN5_PERPLL_VCO			0x80
+#define CLKMGR_GEN5_PERPLL_MISC			0x84
+#define CLKMGR_GEN5_PERPLL_EMAC0CLK		0x88
+#define CLKMGR_GEN5_PERPLL_EMAC1CLK		0x8c
+#define CLKMGR_GEN5_PERPLL_PERQSPICLK		0x90
+#define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK	0x94
+#define CLKMGR_GEN5_PERPLL_PERBASECLK		0x98
+#define CLKMGR_GEN5_PERPLL_S2FUSER1CLK		0x9c
+#define CLKMGR_GEN5_PERPLL_EN			0xa0
+#define CLKMGR_GEN5_PERPLL_DIV			0xa4
+#define CLKMGR_GEN5_PERPLL_GPIODIV		0xa8
+#define CLKMGR_GEN5_PERPLL_SRC			0xac
+/* SDRAM PLL group */
+#define CLKMGR_GEN5_SDRPLL_VCO			0xc0
+#define CLKMGR_GEN5_SDRPLL_CTRL			0xc4
+#define CLKMGR_GEN5_SDRPLL_DDRDQSCLK		0xc8
+#define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK		0xcc
+#define CLKMGR_GEN5_SDRPLL_DDRDQCLK		0xd0
+#define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK		0xd4
+#define CLKMGR_GEN5_SDRPLL_EN			0xd8
+/* Altera group */
+#define CLKMGR_GEN5_ALTR_MPUCLK			0xe0
+#define CLKMGR_GEN5_ALTR_MAINCLK		0xe4
+
+#define CLKMGR_STAT				CLKMGR_GEN5_STAT
+#define CLKMGR_INTER				CLKMGR_GEN5_INTER
+#define CLKMGR_PERPLL_EN			CLKMGR_GEN5_PERPLL_EN
+
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(const int osc);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+
+/* Clock configuration accessors */
+int cm_basic_init(const struct cm_config * const cfg);
+const struct cm_config * const cm_get_default_config(void);
+#endif /* __ASSEMBLY__ */
+
+#include <linux/bitops.h>
+#define LOCKED_MASK \
+	(CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
+	CLKMGR_INTER_PERPLLLOCKED_MASK  | \
+	CLKMGR_INTER_MAINPLLLOCKED_MASK)
+
+#define CLKMGR_CTRL_SAFEMODE				BIT(0)
+#define CLKMGR_CTRL_SAFEMODE_OFFSET			0
+
+#define CLKMGR_BYPASS_PERPLLSRC				BIT(4)
+#define CLKMGR_BYPASS_PERPLLSRC_OFFSET			4
+#define CLKMGR_BYPASS_PERPLL				BIT(3)
+#define CLKMGR_BYPASS_PERPLL_OFFSET			3
+#define CLKMGR_BYPASS_SDRPLLSRC				BIT(2)
+#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET			2
+#define CLKMGR_BYPASS_SDRPLL				BIT(1)
+#define CLKMGR_BYPASS_SDRPLL_OFFSET			1
+#define CLKMGR_BYPASS_MAINPLL				BIT(0)
+#define CLKMGR_BYPASS_MAINPLL_OFFSET			0
+
+#define CLKMGR_INTER_MAINPLLLOST_MASK			BIT(3)
+#define CLKMGR_INTER_PERPLLLOST_MASK			BIT(4)
+#define CLKMGR_INTER_SDRPLLLOST_MASK			BIT(5)
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK			BIT(6)
+#define CLKMGR_INTER_PERPLLLOCKED_MASK			BIT(7)
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK			BIT(8)
+
+#define CLKMGR_STAT_BUSY				BIT(0)
+
+/* Main PLL */
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN			BIT(0)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET		0
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK		0x003f0000
+#define CLKMGR_MAINPLLGRP_VCO_EN			BIT(1)
+#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET			1
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK		0x0000fff8
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN			BIT(2)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET		2
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE		0x8001000d
+
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK		BIT(2)
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK		BIT(4)
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK		BIT(5)
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK		BIT(6)
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK		BIT(7)
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK		BIT(9)
+
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK		0x00000003
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET	2
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK		0x0000000c
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET	4
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK		0x00000070
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET	7
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK		0x00000380
+
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK		0x00000003
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET		2
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK		0x0000000c
+
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK	0x00000007
+
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP			BIT(0)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET		0
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP			BIT(1)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET		1
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE		0x00000000
+#define CLKMGR_L4_SP_CLK_SRC_MAINPLL			0x0
+#define CLKMGR_L4_SP_CLK_SRC_PERPLL			0x1
+
+/* Per PLL */
+#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK			0x003f0000
+#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK			0x0000fff8
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
+#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET		22
+#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK			0x00c00000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE		0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET		22
+#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK			0x00c00000
+
+#define CLKMGR_VCO_SSRC_EOSC1				0x0
+#define CLKMGR_VCO_SSRC_EOSC2				0x1
+#define CLKMGR_VCO_SSRC_F2S				0x2
+
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET	0
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK		0x00000400
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000100
+
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET		6
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK		0x000001c0
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET		9
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK		0x00000e00
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET		0
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK		0x00000007
+
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET	0
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK		0x00ffffff
+
+#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET		2
+#define CLKMGR_PERPLLGRP_SRC_NAND_MASK			0x0000000c
+#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET		4
+#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK			0x00000030
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE		0x00000015
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET		0
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK			0x00000003
+#define CLKMGR_SDMMC_CLK_SRC_F2S			0x0
+#define CLKMGR_SDMMC_CLK_SRC_MAIN			0x1
+#define CLKMGR_SDMMC_CLK_SRC_PER			0x2
+#define CLKMGR_QSPI_CLK_SRC_F2S				0x0
+#define CLKMGR_QSPI_CLK_SRC_MAIN			0x1
+#define CLKMGR_QSPI_CLK_SRC_PER				0x2
+
+/* SDR PLL */
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK			0x003f0000
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK			0x0000fff8
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL		BIT(24)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET		24
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET		25
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK		0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK		BIT(31)
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE		0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET		22
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK			0x00c00000
+
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET		9
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET	9
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET		9
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET	9
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK		0x00000e00
+
+#endif /* _CLOCK_MANAGER_GEN5_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
new file mode 100644
index 000000000..98c3bf1b0
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_CLOCK_MANAGER_S10_
+#define	_CLOCK_MANAGER_S10_
+
+#include <asm/arch/clock_manager_soc64.h>
+#include <linux/bitops.h>
+
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+
+struct cm_config {
+	/* main group */
+	u32 main_pll_mpuclk;
+	u32 main_pll_nocclk;
+	u32 main_pll_cntr2clk;
+	u32 main_pll_cntr3clk;
+	u32 main_pll_cntr4clk;
+	u32 main_pll_cntr5clk;
+	u32 main_pll_cntr6clk;
+	u32 main_pll_cntr7clk;
+	u32 main_pll_cntr8clk;
+	u32 main_pll_cntr9clk;
+	u32 main_pll_nocdiv;
+	u32 main_pll_pllglob;
+	u32 main_pll_fdbck;
+	u32 main_pll_pllc0;
+	u32 main_pll_pllc1;
+	u32 spare;
+
+	/* peripheral group */
+	u32 per_pll_cntr2clk;
+	u32 per_pll_cntr3clk;
+	u32 per_pll_cntr4clk;
+	u32 per_pll_cntr5clk;
+	u32 per_pll_cntr6clk;
+	u32 per_pll_cntr7clk;
+	u32 per_pll_cntr8clk;
+	u32 per_pll_cntr9clk;
+	u32 per_pll_emacctl;
+	u32 per_pll_gpiodiv;
+	u32 per_pll_pllglob;
+	u32 per_pll_fdbck;
+	u32 per_pll_pllc0;
+	u32 per_pll_pllc1;
+
+	/* incoming clock */
+	u32 hps_osc_clk_hz;
+	u32 fpga_clk_hz;
+};
+
+void cm_basic_init(const struct cm_config * const cfg);
+
+/* Control status */
+#define CLKMGR_S10_CTRL					0x00
+#define CLKMGR_S10_STAT					0x04
+#define CLKMGR_S10_INTRCLR				0x14
+/* Mainpll group */
+#define CLKMGR_S10_MAINPLL_EN				0x30
+#define CLKMGR_S10_MAINPLL_BYPASS			0x3c
+#define CLKMGR_S10_MAINPLL_MPUCLK			0x48
+#define CLKMGR_S10_MAINPLL_NOCCLK			0x4c
+#define CLKMGR_S10_MAINPLL_CNTR2CLK			0x50
+#define CLKMGR_S10_MAINPLL_CNTR3CLK			0x54
+#define CLKMGR_S10_MAINPLL_CNTR4CLK			0x58
+#define CLKMGR_S10_MAINPLL_CNTR5CLK			0x5c
+#define CLKMGR_S10_MAINPLL_CNTR6CLK			0x60
+#define CLKMGR_S10_MAINPLL_CNTR7CLK			0x64
+#define CLKMGR_S10_MAINPLL_CNTR8CLK			0x68
+#define CLKMGR_S10_MAINPLL_CNTR9CLK			0x6c
+#define CLKMGR_S10_MAINPLL_NOCDIV			0x70
+#define CLKMGR_S10_MAINPLL_PLLGLOB			0x74
+#define CLKMGR_S10_MAINPLL_FDBCK			0x78
+#define CLKMGR_S10_MAINPLL_MEMSTAT			0x80
+#define CLKMGR_S10_MAINPLL_PLLC0			0x84
+#define CLKMGR_S10_MAINPLL_PLLC1			0x88
+#define CLKMGR_S10_MAINPLL_VCOCALIB			0x8c
+/* Periphpll group */
+#define CLKMGR_S10_PERPLL_EN				0xa4
+#define CLKMGR_S10_PERPLL_BYPASS			0xb0
+#define CLKMGR_S10_PERPLL_CNTR2CLK			0xbc
+#define CLKMGR_S10_PERPLL_CNTR3CLK			0xc0
+#define CLKMGR_S10_PERPLL_CNTR4CLK			0xc4
+#define CLKMGR_S10_PERPLL_CNTR5CLK			0xc8
+#define CLKMGR_S10_PERPLL_CNTR6CLK			0xcc
+#define CLKMGR_S10_PERPLL_CNTR7CLK			0xd0
+#define CLKMGR_S10_PERPLL_CNTR8CLK			0xd4
+#define CLKMGR_S10_PERPLL_CNTR9CLK			0xd8
+#define CLKMGR_S10_PERPLL_EMACCTL			0xdc
+#define CLKMGR_S10_PERPLL_GPIODIV			0xe0
+#define CLKMGR_S10_PERPLL_PLLGLOB			0xe4
+#define CLKMGR_S10_PERPLL_FDBCK				0xe8
+#define CLKMGR_S10_PERPLL_MEMSTAT			0xf0
+#define CLKMGR_S10_PERPLL_PLLC0				0xf4
+#define CLKMGR_S10_PERPLL_PLLC1				0xf8
+#define CLKMGR_S10_PERPLL_VCOCALIB			0xfc
+
+#define CLKMGR_STAT					CLKMGR_S10_STAT
+#define CLKMGR_INTER					CLKMGR_S10_INTER
+#define CLKMGR_PERPLL_EN				CLKMGR_S10_PERPLL_EN
+
+
+#define CLKMGR_CTRL_SAFEMODE				BIT(0)
+#define CLKMGR_BYPASS_MAINPLL_ALL			0x00000007
+#define CLKMGR_BYPASS_PERPLL_ALL			0x0000007f
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK			0x00000001
+#define CLKMGR_INTER_PERPLLLOCKED_MASK			0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK			0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK			0x00000008
+#define CLKMGR_STAT_BUSY				BIT(0)
+#define CLKMGR_STAT_MAINPLL_LOCKED			BIT(8)
+#define CLKMGR_STAT_PERPLL_LOCKED			BIT(9)
+
+#define CLKMGR_PLLGLOB_PD_MASK				0x00000001
+#define CLKMGR_PLLGLOB_RST_MASK				0x00000002
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK			0X3
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET			16
+#define CLKMGR_VCO_PSRC_EOSC1				0
+#define CLKMGR_VCO_PSRC_INTOSC				1
+#define CLKMGR_VCO_PSRC_F2S				2
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK			0X3f
+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET			8
+
+#define CLKMGR_CLKSRC_MASK				0x7
+#define CLKMGR_CLKSRC_OFFSET				16
+#define CLKMGR_CLKSRC_MAIN				0
+#define CLKMGR_CLKSRC_PER				1
+#define CLKMGR_CLKSRC_OSC1				2
+#define CLKMGR_CLKSRC_INTOSC				3
+#define CLKMGR_CLKSRC_FPGA				4
+#define CLKMGR_CLKCNT_MSK				0x7ff
+
+#define CLKMGR_FDBCK_MDIV_MASK				0xff
+#define CLKMGR_FDBCK_MDIV_OFFSET			24
+
+#define CLKMGR_PLLC0_DIV_MASK				0xff
+#define CLKMGR_PLLC1_DIV_MASK				0xff
+#define CLKMGR_PLLC0_EN_OFFSET				27
+#define CLKMGR_PLLC1_EN_OFFSET				24
+
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET			0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET			8
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET			16
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET			24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET			26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET			28
+
+#define CLKMGR_NOCDIV_L4SPCLK_MASK			0X3
+#define CLKMGR_NOCDIV_DIV1				0
+#define CLKMGR_NOCDIV_DIV2				1
+#define CLKMGR_NOCDIV_DIV4				2
+#define CLKMGR_NOCDIV_DIV8				3
+#define CLKMGR_CSPDBGCLK_DIV1				0
+#define CLKMGR_CSPDBGCLK_DIV4				1
+
+#define CLKMGR_MSCNT_CONST				200
+#define CLKMGR_MDIV_CONST				6
+#define CLKMGR_HSCNT_CONST				9
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK			0xff
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET			9
+#define CLKMGR_VCOCALIB_HSCNT_MASK			0xff
+
+#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET			26
+#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET			27
+#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET			28
+
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000020
+
+#endif /* _CLOCK_MANAGER_S10_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
new file mode 100644
index 000000000..71fbaa766
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _CLOCK_MANAGER_SOC64_
+#define _CLOCK_MANAGER_SOC64_
+
+const unsigned int cm_get_osc_clk_hz(void);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+#define CLKMGR_INTOSC_HZ	400000000
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+#endif /* _CLOCK_MANAGER_SOC64_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/firewall.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/firewall.h
new file mode 100644
index 000000000..adab65bc9
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_FIREWALL_H_
+#define	_FIREWALL_H_
+
+#include <linux/bitops.h>
+
+struct socfpga_firwall_l4_per {
+	u32	nand;		/* 0x00 */
+	u32	nand_data;
+	u32	_pad_0x8;
+	u32	usb0;
+	u32	usb1;		/* 0x10 */
+	u32	_pad_0x14;
+	u32	_pad_0x18;
+	u32	spim0;
+	u32	spim1;		/* 0x20 */
+	u32	spis0;
+	u32	spis1;
+	u32	emac0;
+	u32	emac1;		/* 0x30 */
+	u32	emac2;
+	u32	_pad_0x38;
+	u32	_pad_0x3c;
+	u32	sdmmc;		/* 0x40 */
+	u32	gpio0;
+	u32	gpio1;
+	u32	_pad_0x4c;
+	u32	i2c0;		/* 0x50 */
+	u32	i2c1;
+	u32	i2c2;
+	u32	i2c3;
+	u32	i2c4;		/* 0x60 */
+	u32	timer0;
+	u32	timer1;
+	u32	uart0;
+	u32	uart1;		/* 0x70 */
+};
+
+struct socfpga_firwall_l4_sys {
+	u32	_pad_0x00;		/* 0x00 */
+	u32	_pad_0x04;
+	u32	dma_ecc;
+	u32	emac0rx_ecc;
+	u32	emac0tx_ecc;		/* 0x10 */
+	u32	emac1rx_ecc;
+	u32	emac1tx_ecc;
+	u32	emac2rx_ecc;
+	u32	emac2tx_ecc;		/* 0x20 */
+	u32	_pad_0x24;
+	u32	_pad_0x28;
+	u32	nand_ecc;
+	u32	nand_read_ecc;		/* 0x30 */
+	u32	nand_write_ecc;
+	u32	ocram_ecc;
+	u32	_pad_0x3c;
+	u32	sdmmc_ecc;		/* 0x40 */
+	u32	usb0_ecc;
+	u32	usb1_ecc;
+	u32	clock_manager;
+	u32	_pad_0x50;		/* 0x50 */
+	u32	io_manager;
+	u32	reset_manager;
+	u32	system_manager;
+	u32	osc0_timer;		/* 0x60 */
+	u32	osc1_timer;
+	u32	watchdog0;
+	u32	watchdog1;
+	u32	watchdog2;		/* 0x70 */
+	u32	watchdog3;
+};
+
+#define FIREWALL_L4_DISABLE_ALL		(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_BRIDGE_DISABLE_ALL	(~0)
+
+/* Cache coherency unit (CCU) registers */
+#define CCU_CPU0_MPRT_ADBASE_DDRREG		0x4400
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0		0x45c0
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A		0x45e0
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B		0x4600
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C		0x4620
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D		0x4640
+#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E		0x4660
+
+#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0		0x4688
+
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE0		0x18560
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A		0x18580
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B		0x185a0
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C		0x185c0
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D		0x185e0
+#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E		0x18600
+
+#define CCU_IOM_MPRT_ADMASK_MEM_RAM0		0x18628
+
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE0		0x2c520
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A		0x2c540
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B		0x2c560
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C		0x2c580
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D		0x2c5a0
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E		0x2c5c0
+
+#define CCU_ADMASK_P_MASK			BIT(0)
+#define CCU_ADMASK_NS_MASK			BIT(1)
+
+#define CCU_ADBASE_DI_MASK			BIT(4)
+
+#define CCU_REG_ADDR(reg)			\
+	(SOCFPGA_CCU_ADDRESS + (reg))
+
+/* Firewall MPU DDR SCR registers */
+#define FW_MPU_DDR_SCR_EN				0x00
+#define FW_MPU_DDR_SCR_EN_SET				0x04
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT		0x18
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT		0x1c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT		0x98
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT	0x9c
+
+#define MPUREGION0_ENABLE				BIT(0)
+#define NONMPUREGION0_ENABLE				BIT(8)
+
+#define FW_MPU_DDR_SCR_WRITEL(data, reg)		\
+	writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
+
+void firewall_setup(void);
+
+#endif /* _FIREWALL_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager.h
new file mode 100644
index 000000000..481b66bbd
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ */
+
+#ifndef	_FPGA_MANAGER_H_
+#define	_FPGA_MANAGER_H_
+
+#include <altera.h>
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/fpga_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/fpga_manager_arria10.h>
+#endif
+
+/* FPGA CD Ratio Value */
+#define CDRATIO_x1				0x0
+#define CDRATIO_x2				0x1
+#define CDRATIO_x4				0x2
+#define CDRATIO_x8				0x3
+
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
+int fpgamgr_get_mode(void);
+int fpgamgr_poll_fpga_ready(void);
+void fpgamgr_program_write(const void *rbf_data, size_t rbf_size);
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_dclkcnt_set(unsigned long cnt);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _FPGA_MANAGER_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
new file mode 100644
index 000000000..048708202
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ * All rights reserved.
+ */
+
+#include <asm/cache.h>
+#include <altera.h>
+#include <image.h>
+#include <linux/bitops.h>
+
+#ifndef _FPGA_MANAGER_ARRIA10_H_
+#define _FPGA_MANAGER_ARRIA10_H_
+
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK		BIT(0)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK	BIT(1)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK 		BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK 	BIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK		BIT(4)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK		BIT(5)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK		BIT(6)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK		BIT(7)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK	BIT(8)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK		BIT(9)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK		BIT(10)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK		BIT(11)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK		BIT(12)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK		BIT(13)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK    		BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK    		BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK    		BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
+	ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
+	ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
+	ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK	BIT(24)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK	BIT(25)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK		BIT(28)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK			BIT(29)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB			16
+
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK	BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK	BIT(1)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK	BIT(2)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK		BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK	BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK	BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK	BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK	BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK		BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK    	BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK    	BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK    		0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK		BIT(24)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB			16
+
+#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED	0xa65c
+#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED		0xa65d
+#define FPGA_SOCFPGA_A10_RBF_PERIPH		0x0001
+#define FPGA_SOCFPGA_A10_RBF_CORE		0x8001
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+	u32  _pad_0x0_0x7[2];
+	u32  dclkcnt;
+	u32  dclkstat;
+	u32  gpo;
+	u32  gpi;
+	u32  misci;
+	u32  _pad_0x1c_0x2f[5];
+	u32  emr_data0;
+	u32  emr_data1;
+	u32  emr_data2;
+	u32  emr_data3;
+	u32  emr_data4;
+	u32  emr_data5;
+	u32  emr_valid;
+	u32  emr_en;
+	u32  jtag_config;
+	u32  jtag_status;
+	u32  jtag_kick;
+	u32  _pad_0x5c_0x5f;
+	u32  jtag_data_w;
+	u32  jtag_data_r;
+	u32  _pad_0x68_0x6f[2];
+	u32  imgcfg_ctrl_00;
+	u32  imgcfg_ctrl_01;
+	u32  imgcfg_ctrl_02;
+	u32  _pad_0x7c_0x7f;
+	u32  imgcfg_stat;
+	u32  intr_masked_status;
+	u32  intr_mask;
+	u32  intr_polarity;
+	u32  dma_config;
+	u32  imgcfg_fifo_status;
+};
+
+enum rbf_type {
+	unknown,
+	periph_section,
+	core_section
+};
+
+enum rbf_security {
+	invalid,
+	unencrypted,
+	encrypted
+};
+
+struct rbf_info {
+	enum rbf_type section;
+	enum rbf_security security;
+};
+
+struct fpga_loadfs_info {
+	fpga_fs_info *fpga_fsinfo;
+	u32 remaining;
+	u32 offset;
+	struct rbf_info rbfinfo;
+};
+
+/* Functions */
+int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
+int fpgamgr_program_finish(void);
+int is_fpgamgr_user_mode(void);
+int fpgamgr_wait_early_user_mode(void);
+const char *get_fpga_filename(void);
+int is_fpgamgr_early_user_mode(void);
+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
+		  u32 offset);
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_ARRIA10_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
new file mode 100644
index 000000000..e08c00562
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ */
+
+#ifndef _FPGA_MANAGER_GEN5_H_
+#define _FPGA_MANAGER_GEN5_H_
+
+#include <linux/bitops.h>
+#define FPGAMGRREGS_STAT_MODE_MASK		0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK		0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB		3
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK		BIT(9)
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK		BIT(8)
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK	BIT(2)
+#define FPGAMGRREGS_CTRL_NCE_MASK		BIT(1)
+#define FPGAMGRREGS_CTRL_EN_MASK		BIT(0)
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB		6
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK	BIT(3)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK	BIT(2)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK	BIT(1)
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK	BIT(0)
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF		0x0
+#define FPGAMGRREGS_MODE_RESETPHASE		0x1
+#define FPGAMGRREGS_MODE_CFGPHASE		0x2
+#define FPGAMGRREGS_MODE_INITPHASE		0x3
+#define FPGAMGRREGS_MODE_USERMODE		0x4
+#define FPGAMGRREGS_MODE_UNKNOWN		0x5
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+	/* FPGA Manager Module */
+	u32	stat;			/* 0x00 */
+	u32	ctrl;
+	u32	dclkcnt;
+	u32	dclkstat;
+	u32	gpo;			/* 0x10 */
+	u32	gpi;
+	u32	misci;			/* 0x18 */
+	u32	_pad_0x1c_0x82c[517];
+
+	/* Configuration Monitor (MON) Registers */
+	u32	gpio_inten;		/* 0x830 */
+	u32	gpio_intmask;
+	u32	gpio_inttype_level;
+	u32	gpio_int_polarity;
+	u32	gpio_intstatus;		/* 0x840 */
+	u32	gpio_raw_intstatus;
+	u32	_pad_0x848;
+	u32	gpio_porta_eoi;
+	u32	gpio_ext_porta;		/* 0x850 */
+	u32	_pad_0x854_0x85c[3];
+	u32	gpio_1s_sync;		/* 0x860 */
+	u32	_pad_0x864_0x868[2];
+	u32	gpio_ver_id_code;
+	u32	gpio_config_reg2;	/* 0x870 */
+	u32	gpio_config_reg1;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_GEN5_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/freeze_controller.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/freeze_controller.h
new file mode 100644
index 000000000..80846a67f
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/freeze_controller.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ */
+
+#ifndef	_FREEZE_CONTROLLER_H_
+#define	_FREEZE_CONTROLLER_H_
+
+struct socfpga_freeze_controller {
+	u32	vioctrl;
+	u32	padding[3];
+	u32	hioctrl;
+	u32	src;
+	u32	hwctrl;
+};
+
+#define FREEZE_CHANNEL_NUM		(4)
+
+typedef enum {
+	FREEZE_CTRL_FROZEN = 0,
+	FREEZE_CTRL_THAWED = 1
+} FREEZE_CTRL_CHAN_STATE;
+
+#define SYSMGR_FRZCTRL_ADDRESS 0x40
+#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
+#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
+#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
+#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
+#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
+#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
+#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
+#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
+#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
+#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
+#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
+#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
+#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
+#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
+
+void sys_mgr_frzctrl_freeze_req(void);
+void sys_mgr_frzctrl_thaw_req(void);
+
+#endif /* _FREEZE_CONTROLLER_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/gpio.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/gpio.h
new file mode 100644
index 000000000..f216b8033
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _SOCFPGA_GPIO_H
+#define _SOCFPGA_GPIO_H
+
+#endif /* _SOCFPGA_GPIO_H */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
new file mode 100644
index 000000000..3750216a9
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _HANDOFF_SOC64_H_
+#define _HANDOFF_SOC64_H_
+
+/*
+ * Offset for HW handoff from Quartus tools
+ */
+/* HPS handoff */
+#define SOC64_HANDOFF_MAGIC_BOOT	0x424F4F54
+#define SOC64_HANDOFF_MAGIC_MUX	0x504D5558
+#define SOC64_HANDOFF_MAGIC_IOCTL	0x494F4354
+#define SOC64_HANDOFF_MAGIC_FPGA	0x46504741
+#define SOC64_HANDOFF_MAGIC_DELAY	0x444C4159
+#define SOC64_HANDOFF_MAGIC_CLOCK	0x434C4B53
+#define SOC64_HANDOFF_MAGIC_MISC	0x4D495343
+
+#define SOC64_HANDOFF_OFFSET_LENGTH	0x4
+#define SOC64_HANDOFF_OFFSET_DATA	0x10
+#define SOC64_HANDOFF_SIZE		4096
+
+#define SOC64_HANDOFF_BASE		0xFFE3F000
+#define SOC64_HANDOFF_MISC		(SOC64_HANDOFF_BASE + 0x610)
+#define SOC64_HANDOFF_MUX		(SOC64_HANDOFF_BASE + 0x10)
+#define SOC64_HANDOFF_IOCTL		(SOC64_HANDOFF_BASE + 0x1A0)
+#define SOC64_HANDOFF_FPGA		(SOC64_HANDOFF_BASE + 0x330)
+#define SOC64_HANDOFF_DELAY		(SOC64_HANDOFF_BASE + 0x3F0)
+#define SOC64_HANDOFF_CLOCK		(SOC64_HANDOFF_BASE + 0x580)
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#define SOC64_HANDOFF_CLOCK_OSC	(SOC64_HANDOFF_BASE + 0x608)
+#define SOC64_HANDOFF_CLOCK_FPGA	(SOC64_HANDOFF_BASE + 0x60C)
+#else
+#define SOC64_HANDOFF_CLOCK_OSC	(SOC64_HANDOFF_BASE + 0x5fc)
+#define SOC64_HANDOFF_CLOCK_FPGA	(SOC64_HANDOFF_BASE + 0x600)
+#endif
+
+#define SOC64_HANDOFF_MUX_LEN			96
+#define SOC64_HANDOFF_IOCTL_LEN			96
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#define SOC64_HANDOFF_FPGA_LEN			42
+#else
+#define SOC64_HANDOFF_FPGA_LEN			40
+#endif
+#define SOC64_HANDOFF_DELAY_LEN			96
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+enum endianness {
+	LITTLE_ENDIAN = 0,
+	BIG_ENDIAN
+};
+
+int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
+			 enum endianness big_endian);
+#endif
+#endif /* _HANDOFF_SOC64_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
new file mode 100644
index 000000000..fbaf11597
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _MAILBOX_S10_H_
+#define _MAILBOX_S10_H_
+
+/* user define Uboot ID */
+#include <linux/bitops.h>
+#define MBOX_CLIENT_ID_UBOOT	0xB
+#define MBOX_ID_UBOOT		0x1
+
+#define MBOX_CMD_DIRECT	0
+#define MBOX_CMD_INDIRECT	1
+
+#define MBOX_MAX_CMD_INDEX	2047
+#define MBOX_CMD_BUFFER_SIZE	32
+#define MBOX_RESP_BUFFER_SIZE	16
+
+#define MBOX_HDR_CMD_LSB	0
+#define MBOX_HDR_CMD_MSK	(BIT(11) - 1)
+#define MBOX_HDR_I_LSB		11
+#define MBOX_HDR_I_MSK		BIT(11)
+#define MBOX_HDR_LEN_LSB	12
+#define MBOX_HDR_LEN_MSK	0x007FF000
+#define MBOX_HDR_ID_LSB		24
+#define MBOX_HDR_ID_MSK		0x0F000000
+#define MBOX_HDR_CLIENT_LSB	28
+#define MBOX_HDR_CLIENT_MSK	0xF0000000
+
+/* Interrupt flags */
+#define MBOX_FLAGS_INT_COE	BIT(0)	/* COUT update interrupt enable */
+#define MBOX_FLAGS_INT_RIE	BIT(1)	/* RIN update interrupt enable */
+#define MBOX_FLAGS_INT_UAE	BIT(8)	/* Urgent ACK interrupt enable */
+#define MBOX_ALL_INTRS		(MBOX_FLAGS_INT_COE | \
+				 MBOX_FLAGS_INT_RIE | \
+				 MBOX_FLAGS_INT_UAE)
+
+/* Status */
+#define MBOX_STATUS_UA_MSK	BIT(8)
+
+#define MBOX_CMD_HEADER(client, id, len, indirect, cmd)     \
+	((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
+	(((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
+	(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK)  | \
+	(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)     | \
+	(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK))
+
+#define MBOX_RESP_ERR_GET(resp)				\
+	(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
+#define MBOX_RESP_LEN_GET(resp)			\
+	(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
+#define MBOX_RESP_ID_GET(resp)				\
+	(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
+#define MBOX_RESP_CLIENT_GET(resp)			\
+	(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
+
+/* Response error list */
+enum ALT_SDM_MBOX_RESP_CODE {
+	/* CMD completed successfully, but check resp ARGS for any errors */
+	MBOX_RESP_STATOK = 0,
+	/* CMD is incorrectly formatted in some way */
+	MBOX_RESP_INVALID_COMMAND = 1,
+	/* BootROM Command code not undesrtood */
+	MBOX_RESP_UNKNOWN_BR = 2,
+	/* CMD code not recognized by firmware */
+	MBOX_RESP_UNKNOWN = 3,
+	/* Length setting is not a valid length for this CMD type */
+	MBOX_RESP_INVALID_LEN = 4,
+	/* Indirect setting is not valid for this CMD type */
+	MBOX_RESP_INVALID_INDIRECT_SETTING = 5,
+	/* HW source which is not allowed to send CMD type */
+	MBOX_RESP_CMD_INVALID_ON_SRC = 6,
+	/* Client with ID not associated with any running PR CMD tries to run
+	 * RECONFIG_DATA RECONFIG_STATUS and accessing QSPI / SDMMC using ID
+	 * without exclusive access
+	 */
+	MBOX_RESP_CLIENT_ID_NO_MATCH = 8,
+	/* Address provided to the system is invalid (alignment, range
+	 * permission)
+	 */
+	MBOX_RESP_INVALID_ADDR = 0x9,
+	/* Signature authentication failed */
+	MBOX_RESP_AUTH_FAIL = 0xA,
+	/* CMD timed out */
+	MBOX_RESP_TIMEOUT = 0xB,
+	/* HW (i.e. QSPI) is not ready (initialized or configured) */
+	MBOX_RESP_HW_NOT_RDY = 0xC,
+	/* Invalid license for IID registration */
+	MBOX_RESP_PUF_ACCCES_FAILED = 0x80,
+	MBOX_PUF_ENROLL_DISABLE = 0x81,
+	MBOX_RESP_PUF_ENROLL_FAIL = 0x82,
+	MBOX_RESP_PUF_RAM_TEST_FAIL = 0x83,
+	MBOX_RESP_ATTEST_CERT_GEN_FAIL = 0x84,
+	/* Operation not allowed under current security settings */
+	MBOX_RESP_NOT_ALLOWED_UNDER_SECURITY_SETTINGS = 0x85,
+	MBOX_RESP_PUF_TRNG_FAIL = 0x86,
+	MBOX_RESP_FUSE_ALREADY_BLOWN = 0x87,
+	MBOX_RESP_INVALID_SIGNATURE = 0x88,
+	MBOX_RESP_INVALID_HASH = 0x8b,
+	MBOX_RESP_INVALID_CERTIFICATE = 0x91,
+	/* Indicates that the device (FPGA or HPS) is not configured */
+	MBOX_RESP_NOT_CONFIGURED = 0x100,
+	/* Indicates that the device is busy */
+	MBOX_RESP_DEVICE_BUSY = 0x1FF,
+	/* Indicates that there is no valid response available */
+	MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
+	/* General Error */
+	MBOX_RESP_ERROR = 0x3FF,
+};
+
+/* Mailbox command list */
+#define MBOX_RESTART		2
+#define MBOX_CONFIG_STATUS	4
+#define MBOX_RECONFIG		6
+#define MBOX_RECONFIG_MSEL	7
+#define MBOX_RECONFIG_DATA	8
+#define MBOX_RECONFIG_STATUS	9
+#define MBOX_VAB_SRC_CERT		11
+#define MBOX_QSPI_OPEN		50
+#define MBOX_QSPI_CLOSE		51
+#define MBOX_QSPI_DIRECT	59
+#define MBOX_REBOOT_HPS		71
+
+/* Mailbox registers */
+#define MBOX_CIN			0	/* command valid offset */
+#define MBOX_ROUT			4	/* response output offset */
+#define MBOX_URG			8	/* urgent command */
+#define MBOX_FLAGS			0x0c	/* interrupt enables */
+#define MBOX_COUT			0x20	/* command free offset */
+#define MBOX_RIN			0x24	/* respond valid offset */
+#define MBOX_STATUS			0x2c	/* mailbox status */
+#define MBOX_CMD_BUF			0x40	/* circular command buffer */
+#define MBOX_RESP_BUF			0xc0	/* circular response buffer */
+#define MBOX_DOORBELL_TO_SDM		0x400	/* Doorbell to SDM */
+#define MBOX_DOORBELL_FROM_SDM		0x480	/* Doorbell from SDM */
+
+/* Status and bit information returned by RECONFIG_STATUS */
+#define RECONFIG_STATUS_RESPONSE_LEN			6
+#define RECONFIG_STATUS_STATE				0
+#define RECONFIG_STATUS_PIN_STATUS			2
+#define RECONFIG_STATUS_SOFTFUNC_STATUS			3
+
+/* Macros for specifying number of arguments in mailbox command */
+#define MBOX_NUM_ARGS(n, b)				(((n) & 0xFF) << (b))
+#define MBOX_DIRECT_COUNT(n)				MBOX_NUM_ARGS((n), 0)
+#define MBOX_ARG_DESC_COUNT(n)				MBOX_NUM_ARGS((n), 8)
+#define MBOX_RESP_DESC_COUNT(n)				MBOX_NUM_ARGS((n), 16)
+
+#define MBOX_CFGSTAT_STATE_IDLE				0x00000000
+#define MBOX_CFGSTAT_STATE_CONFIG			0x10000000
+#define MBOX_CFGSTAT_STATE_FAILACK			0x08000000
+#define MBOX_CFGSTAT_STATE_ERROR_INVALID		0xf0000001
+#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT		0xf0000002
+#define MBOX_CFGSTAT_STATE_ERROR_AUTH			0xf0000003
+#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO		0xf0000004
+#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE		0xf0000005
+#define MBOX_CFGSTAT_STATE_ERROR_FAKE			0xf0000006
+#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO		0xf0000007
+#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR		0xf0000008
+
+#define RCF_SOFTFUNC_STATUS_CONF_DONE			BIT(0)
+#define RCF_SOFTFUNC_STATUS_INIT_DONE			BIT(1)
+#define RCF_SOFTFUNC_STATUS_SEU_ERROR			BIT(3)
+#define RCF_PIN_STATUS_NSTATUS				BIT(31)
+
+int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
+		  u32 *resp_buf_len, u32 *resp_buf);
+int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
+		       u8 urgent, u32 *resp_buf_len, u32 *resp_buf);
+int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
+int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
+int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
+int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
+int mbox_init(void);
+
+#ifdef CONFIG_CADENCE_QSPI
+int mbox_qspi_close(void);
+int mbox_qspi_open(void);
+#endif
+
+int mbox_reset_cold(void);
+int mbox_get_fpga_config_status(u32 cmd);
+int mbox_get_fpga_config_status_psci(u32 cmd);
+#endif /* _MAILBOX_S10_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/misc.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000000000..649d2f6ce
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ */
+
+#ifndef _SOCFPGA_MISC_H_
+#define _SOCFPGA_MISC_H_
+
+#include <asm/sections.h>
+
+void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
+
+struct bsel {
+	const char	*mode;
+	const char	*name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+void socfpga_fpga_add(void *fpga_desc);
+#else
+static inline void socfpga_fpga_add(void *fpga_desc) {}
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+void socfpga_sdram_remap_zero(void);
+static inline bool socfpga_is_booting_from_fpga(void)
+{
+	if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) &&
+	    (__image_copy_start < (char *)SOCFPGA_STM_ADDRESS))
+		return true;
+	return false;
+}
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+void socfpga_init_security_policies(void);
+void socfpga_sdram_remap_zero(void);
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+	defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+int is_fpga_config_ready(void);
+#endif
+
+void do_bridge_reset(int enable, unsigned int mask);
+void socfpga_pl310_clear(void);
+void socfpga_get_managers_addr(void);
+
+#endif /* _SOCFPGA_MISC_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/nic301.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/nic301.h
new file mode 100644
index 000000000..20bebb8c8
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/nic301.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef	_NIC301_REGISTERS_H_
+#define	_NIC301_REGISTERS_H_
+
+struct nic301_registers {
+	u32	remap;				/* 0x0 */
+	/* Security Register Group */
+	u32	_pad_0x4_0x8[1];
+	u32	l4main;
+	u32	l4sp;
+	u32	l4mp;				/* 0x10 */
+	u32	l4osc1;
+	u32	l4spim;
+	u32	stm;
+	u32	lwhps2fpgaregs;			/* 0x20 */
+	u32	_pad_0x24_0x28[1];
+	u32	usb1;
+	u32	nanddata;
+	u32	_pad_0x30_0x80[20];
+	u32	usb0;				/* 0x80 */
+	u32	nandregs;
+	u32	qspidata;
+	u32	fpgamgrdata;
+	u32	hps2fpgaregs;			/* 0x90 */
+	u32	acp;
+	u32	rom;
+	u32	ocram;
+	u32	sdrdata;			/* 0xA0 */
+	u32	_pad_0xa4_0x1fd0[1995];
+	/* ID Register Group */
+	u32	periph_id_4;			/* 0x1FD0 */
+	u32	_pad_0x1fd4_0x1fe0[3];
+	u32	periph_id_0;			/* 0x1FE0 */
+	u32	periph_id_1;
+	u32	periph_id_2;
+	u32	periph_id_3;
+	u32	comp_id_0;			/* 0x1FF0 */
+	u32	comp_id_1;
+	u32	comp_id_2;
+	u32	comp_id_3;
+	u32	_pad_0x2000_0x2008[2];
+	/* L4 MAIN */
+	u32	l4main_fn_mod_bm_iss;
+	u32	_pad_0x200c_0x3008[1023];
+	/* L4 SP */
+	u32	l4sp_fn_mod_bm_iss;
+	u32	_pad_0x300c_0x4008[1023];
+	/* L4 MP */
+	u32	l4mp_fn_mod_bm_iss;
+	u32	_pad_0x400c_0x5008[1023];
+	/* L4 OSC1 */
+	u32	l4osc_fn_mod_bm_iss;
+	u32	_pad_0x500c_0x6008[1023];
+	/* L4 SPIM */
+	u32	l4spim_fn_mod_bm_iss;
+	u32	_pad_0x600c_0x7008[1023];
+	/* STM */
+	u32	stm_fn_mod_bm_iss;
+	u32	_pad_0x700c_0x7108[63];
+	u32	stm_fn_mod;
+	u32	_pad_0x710c_0x8008[959];
+	/* LWHPS2FPGA */
+	u32	lwhps2fpga_fn_mod_bm_iss;
+	u32	_pad_0x800c_0x8108[63];
+	u32	lwhps2fpga_fn_mod;
+	u32	_pad_0x810c_0xa008[1983];
+	/* USB1 */
+	u32	usb1_fn_mod_bm_iss;
+	u32	_pad_0xa00c_0xa044[14];
+	u32	usb1_ahb_cntl;
+	u32	_pad_0xa048_0xb008[1008];
+	/* NANDDATA */
+	u32	nanddata_fn_mod_bm_iss;
+	u32	_pad_0xb00c_0xb108[63];
+	u32	nanddata_fn_mod;
+	u32	_pad_0xb10c_0x20008[21439];
+	/* USB0 */
+	u32	usb0_fn_mod_bm_iss;
+	u32	_pad_0x2000c_0x20044[14];
+	u32	usb0_ahb_cntl;
+	u32	_pad_0x20048_0x21008[1008];
+	/* NANDREGS */
+	u32	nandregs_fn_mod_bm_iss;
+	u32	_pad_0x2100c_0x21108[63];
+	u32	nandregs_fn_mod;
+	u32	_pad_0x2110c_0x22008[959];
+	/* QSPIDATA */
+	u32	qspidata_fn_mod_bm_iss;
+	u32	_pad_0x2200c_0x22044[14];
+	u32	qspidata_ahb_cntl;
+	u32	_pad_0x22048_0x23008[1008];
+	/* FPGAMGRDATA */
+	u32	fpgamgrdata_fn_mod_bm_iss;
+	u32	_pad_0x2300c_0x23040[13];
+	u32	fpgamgrdata_wr_tidemark;	/* 0x23040 */
+	u32	_pad_0x23044_0x23108[49];
+	u32	fn_mod;
+	u32	_pad_0x2310c_0x24008[959];
+	/* HPS2FPGA */
+	u32	hps2fpga_fn_mod_bm_iss;
+	u32	_pad_0x2400c_0x24040[13];
+	u32	hps2fpga_wr_tidemark;		/* 0x24040 */
+	u32	_pad_0x24044_0x24108[49];
+	u32	hps2fpga_fn_mod;
+	u32	_pad_0x2410c_0x25008[959];
+	/* ACP */
+	u32	acp_fn_mod_bm_iss;
+	u32	_pad_0x2500c_0x25108[63];
+	u32	acp_fn_mod;
+	u32	_pad_0x2510c_0x26008[959];
+	/* Boot ROM */
+	u32	bootrom_fn_mod_bm_iss;
+	u32	_pad_0x2600c_0x26108[63];
+	u32	bootrom_fn_mod;
+	u32	_pad_0x2610c_0x27008[959];
+	/* On-chip RAM */
+	u32	ocram_fn_mod_bm_iss;
+	u32	_pad_0x2700c_0x27040[13];
+	u32	ocram_wr_tidemark;		/* 0x27040 */
+	u32	_pad_0x27044_0x27108[49];
+	u32	ocram_fn_mod;
+	u32	_pad_0x2710c_0x42024[27590];
+	/* DAP */
+	u32	dap_fn_mod2;
+	u32	dap_fn_mod_ahb;
+	u32	_pad_0x4202c_0x42100[53];
+	u32	dap_read_qos;			/* 0x42100 */
+	u32	dap_write_qos;
+	u32	dap_fn_mod;
+	u32	_pad_0x4210c_0x43100[1021];
+	/* MPU */
+	u32	mpu_read_qos;			/* 0x43100 */
+	u32	mpu_write_qos;
+	u32	mpu_fn_mod;
+	u32	_pad_0x4310c_0x44028[967];
+	/* SDMMC */
+	u32	sdmmc_fn_mod_ahb;
+	u32	_pad_0x4402c_0x44100[53];
+	u32	sdmmc_read_qos;			/* 0x44100 */
+	u32	sdmmc_write_qos;
+	u32	sdmmc_fn_mod;
+	u32	_pad_0x4410c_0x45100[1021];
+	/* DMA */
+	u32	dma_read_qos;			/* 0x45100 */
+	u32	dma_write_qos;
+	u32	dma_fn_mod;
+	u32	_pad_0x4510c_0x46040[973];
+	/* FPGA2HPS */
+	u32	fpga2hps_wr_tidemark;		/* 0x46040 */
+	u32	_pad_0x46044_0x46100[47];
+	u32	fpga2hps_read_qos;		/* 0x46100 */
+	u32	fpga2hps_write_qos;
+	u32	fpga2hps_fn_mod;
+	u32	_pad_0x4610c_0x47100[1021];
+	/* ETR */
+	u32	etr_read_qos;			/* 0x47100 */
+	u32	etr_write_qos;
+	u32	etr_fn_mod;
+	u32	_pad_0x4710c_0x48100[1021];
+	/* EMAC0 */
+	u32	emac0_read_qos;			/* 0x48100 */
+	u32	emac0_write_qos;
+	u32	emac0_fn_mod;
+	u32	_pad_0x4810c_0x49100[1021];
+	/* EMAC1 */
+	u32	emac1_read_qos;			/* 0x49100 */
+	u32	emac1_write_qos;
+	u32	emac1_fn_mod;
+	u32	_pad_0x4910c_0x4a028[967];
+	/* USB0 */
+	u32	usb0_fn_mod_ahb;
+	u32	_pad_0x4a02c_0x4a100[53];
+	u32	usb0_read_qos;			/* 0x4A100 */
+	u32	usb0_write_qos;
+	u32	usb0_fn_mod;
+	u32	_pad_0x4a10c_0x4b100[1021];
+	/* NAND */
+	u32	nand_read_qos;			/* 0x4B100 */
+	u32	nand_write_qos;
+	u32	nand_fn_mod;
+	u32	_pad_0x4b10c_0x4c028[967];
+	/* USB1 */
+	u32	usb1_fn_mod_ahb;
+	u32	_pad_0x4c02c_0x4c100[53];
+	u32	usb1_read_qos;			/* 0x4C100 */
+	u32	usb1_write_qos;
+	u32	usb1_fn_mod;
+};
+
+#endif	/* _NIC301_REGISTERS_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/pinmux.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000000000..2de5033b1
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+#define PINMUX_UART		0xD
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+#endif /* _PINMUX_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager.h
new file mode 100644
index 000000000..1d68034cb
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ */
+
+#ifndef _RESET_MANAGER_H_
+#define _RESET_MANAGER_H_
+
+phys_addr_t socfpga_get_rstmgr_addr(void);
+
+void reset_cpu(void);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET	8
+#define RSTMGR_BANK_MASK	0x7
+#define RSTMGR_RESET_OFFSET	0
+#define RSTMGR_RESET_MASK	0x1f
+#define RSTMGR_DEFINE(_bank, _offset)		\
+	((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset)			\
+	(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset)			\
+	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/* Create a human-readable reference to SoCFPGA reset. */
+#define SOCFPGA_RESET(_name)	RSTMGR_##_name
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/reset_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/reset_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_SOC64)
+#include <asm/arch/reset_manager_soc64.h>
+#endif
+
+#endif /* _RESET_MANAGER_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
new file mode 100644
index 000000000..19507c292
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ */
+
+#ifndef _RESET_MANAGER_ARRIA10_H_
+#define _RESET_MANAGER_ARRIA10_H_
+
+#include <dt-bindings/reset/altr,rst-mgr-a10.h>
+#include <linux/bitops.h>
+
+void socfpga_watchdog_disable(void);
+void socfpga_reset_deassert_noc_ddr_scheduler(void);
+int socfpga_reset_deassert_bridges_handoff(void);
+void socfpga_reset_deassert_osc1wd0(void);
+int socfpga_bridges_reset(void);
+
+#define RSTMGR_A10_STATUS	0x00
+#define RSTMGR_A10_CTRL		0x0c
+#define RSTMGR_A10_MPUMODRST	0x20
+#define RSTMGR_A10_PER0MODRST	0x24
+#define RSTMGR_A10_PER1MODRST	0x28
+#define RSTMGR_A10_BRGMODRST	0x2c
+#define RSTMGR_A10_SYSMODRST	0x30
+
+#define RSTMGR_CTRL		RSTMGR_A10_CTRL
+
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2		RSTMGR_DEFINE(1, 2)
+#define RSTMGR_NAND		RSTMGR_DEFINE(1, 5)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1		RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0	RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1	RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0		RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1		RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1		RSTMGR_DEFINE(2, 17)
+#define RSTMGR_DDRSCH		RSTMGR_DEFINE(3, 6)
+
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK	BIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK	BIT(0)
+#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK	BIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK	BIT(2)
+#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK	BIT(3)
+#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK	BIT(4)
+#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK	BIT(5)
+#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK	BIT(6)
+#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK	BIT(7)
+#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK	BIT(8)
+#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK	BIT(9)
+#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK	BIT(10)
+#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK	BIT(11)
+#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK	BIT(12)
+#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK	BIT(13)
+#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK	BIT(14)
+#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK	BIT(15)
+#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK	BIT(16)
+#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK	BIT(17)
+#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK	BIT(18)
+#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK	BIT(19)
+#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK	BIT(20)
+#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK	BIT(21)
+#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK	BIT(22)
+#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK	BIT(24)
+#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK	BIT(25)
+#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK	BIT(26)
+#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK	BIT(27)
+#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK	BIT(28)
+#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK	BIT(29)
+#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK	BIT(30)
+#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK	BIT(31)
+
+#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK	BIT(0)
+#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK	BIT(1)
+#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK	BIT(2)
+#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK	BIT(3)
+#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK	BIT(4)
+#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK	BIT(5)
+#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK	BIT(8)
+#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK	BIT(9)
+#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK	BIT(10)
+#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK	BIT(11)
+#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK	BIT(12)
+#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK	BIT(16)
+#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK	BIT(17)
+#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK	BIT(24)
+#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK	BIT(25)
+#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK	BIT(26)
+
+#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK	BIT(0)
+#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK	BIT(1)
+#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK	BIT(2)
+#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK	BIT(3)
+#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK	BIT(4)
+#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK	BIT(5)
+#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK	BIT(6)
+
+#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK	BIT(0)
+#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK	BIT(1)
+#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK	BIT(2)
+#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK	BIT(3)
+
+#endif /* _RESET_MANAGER_ARRIA10_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
new file mode 100644
index 000000000..d108eac1e
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ */
+
+#ifndef _RESET_MANAGER_GEN5_H_
+#define _RESET_MANAGER_GEN5_H_
+
+#include <dt-bindings/reset/altr,rst-mgr.h>
+
+void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
+void socfpga_bridges_reset(int enable);
+
+#define RSTMGR_GEN5_STATUS	0x00
+#define RSTMGR_GEN5_CTRL	0x04
+#define RSTMGR_GEN5_MPUMODRST	0x10
+#define RSTMGR_GEN5_PERMODRST	0x14
+#define RSTMGR_GEN5_PER2MODRST	0x18
+#define RSTMGR_GEN5_BRGMODRST	0x1c
+#define RSTMGR_GEN5_MISCMODRST	0x20
+
+#define RSTMGR_CTRL		RSTMGR_GEN5_CTRL
+
+/*
+ * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... permodrst
+ * 2 ... per2modrst
+ * 3 ... brgmodrst
+ * 4 ... miscmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NAND		RSTMGR_DEFINE(1, 4)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(1, 6)
+#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(1, 8)
+#define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
+#define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
+
+#endif /* _RESET_MANAGER_GEN5_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
new file mode 100644
index 000000000..c8bb727aa
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _RESET_MANAGER_SOC64_H_
+#define _RESET_MANAGER_SOC64_H_
+
+void reset_deassert_peripherals_handoff(void);
+int cpu_has_been_warmreset(void);
+void print_reset_info(void);
+void socfpga_bridges_reset(int enable);
+
+#define RSTMGR_SOC64_STATUS	0x00
+#define RSTMGR_SOC64_MPUMODRST	0x20
+#define RSTMGR_SOC64_PER0MODRST	0x24
+#define RSTMGR_SOC64_PER1MODRST	0x28
+#define RSTMGR_SOC64_BRGMODRST	0x2c
+
+#define RSTMGR_MPUMODRST_CORE0		0
+#define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK	0X00000040
+#define RSTMGR_BRGMODRST_FPGA2SOC_MASK	0x00000004
+
+/* SDM, Watchdogs and MPU warm reset mask */
+#define RSTMGR_STAT_SDMWARMRST		BIT(1)
+#define RSTMGR_STAT_MPU0RST_BITPOS	8
+#define RSTMGR_STAT_L4WD0RST_BITPOS	16
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK	(RSTMGR_STAT_SDMWARMRST | \
+		GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \
+			RSTMGR_STAT_MPU0RST_BITPOS) | \
+		GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \
+			RSTMGR_STAT_L4WD0RST_BITPOS))
+
+/*
+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ */
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(2, 0)
+#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(2, 4)
+#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
+
+#endif /* _RESET_MANAGER_SOC64_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/scan_manager.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/scan_manager.h
new file mode 100644
index 000000000..4d8d649be
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/scan_manager.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ */
+
+#ifndef	_SCAN_MANAGER_H_
+#define	_SCAN_MANAGER_H_
+
+struct socfpga_scan_manager {
+	u32	stat;
+	u32	en;
+	u32	padding[2];
+	u32	fifo_single_byte;
+	u32	fifo_double_byte;
+	u32	fifo_triple_byte;
+	u32	fifo_quad_byte;
+};
+
+int scan_mgr_configure_iocsr(void);
+u32 scan_mgr_get_fpga_id(void);
+int iocsr_get_config_table(const unsigned int chain_id,
+			   const unsigned long **table,
+			   unsigned int *table_len);
+
+#endif /* _SCAN_MANAGER_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/scu.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/scu.h
new file mode 100644
index 000000000..b684a5501
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/scu.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __SOCFPGA_SCU_H__
+#define __SOCFPGA_SCU_H__
+
+struct scu_registers {
+	u32	ctrl;			/* 0x00 */
+	u32	cfg;
+	u32	cpsr;
+	u32	iassr;
+	u32	_pad_0x10_0x3c[12];	/* 0x10 */
+	u32	fsar;			/* 0x40 */
+	u32	fear;
+	u32	_pad_0x48_0x4c[2];
+	u32	acr;			/* 0x50 */
+	u32	sacr;
+};
+
+#endif	/* __SOCFPGA_SCU_H__ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/sdram.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/sdram.h
new file mode 100644
index 000000000..79cb9e606
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright Altera Corporation (C) 2014-2015
+ */
+#ifndef	_SDRAM_H_
+#define	_SDRAM_H_
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/sdram_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/sdram_arria10.h>
+#endif
+
+#endif
+#endif /* _SDRAM_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
new file mode 100644
index 000000000..ff05994cc
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -0,0 +1,382 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _SOCFPGA_SDRAM_ARRIA10_H_
+#define _SOCFPGA_SDRAM_ARRIA10_H_
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+int ddr_calibration_sequence(void);
+
+struct socfpga_ecc_hmc {
+	u32 ip_rev_id;
+	u32 _pad_0x4_0x7;
+	u32 ddrioctrl;
+	u32 ddrcalstat;
+	u32 mpr_0beat1;
+	u32 mpr_1beat1;
+	u32 mpr_2beat1;
+	u32 mpr_3beat1;
+	u32 mpr_4beat1;
+	u32 mpr_5beat1;
+	u32 mpr_6beat1;
+	u32 mpr_7beat1;
+	u32 mpr_8beat1;
+	u32 mpr_0beat2;
+	u32 mpr_1beat2;
+	u32 mpr_2beat2;
+	u32 mpr_3beat2;
+	u32 mpr_4beat2;
+	u32 mpr_5beat2;
+	u32 mpr_6beat2;
+	u32 mpr_7beat2;
+	u32 mpr_8beat2;
+	u32 _pad_0x58_0x5f[2];
+	u32 auto_precharge;
+	u32 _pad_0x64_0xff[39];
+	u32 eccctrl;
+	u32 eccctrl2;
+	u32 _pad_0x108_0x10f[2];
+	u32 errinten;
+	u32 errintens;
+	u32 errintenr;
+	u32 intmode;
+	u32 intstat;
+	u32 diaginttest;
+	u32 modstat;
+	u32 derraddra;
+	u32 serraddra;
+	u32 _pad_0x134_0x137;
+	u32 autowb_corraddr;
+	u32 serrcntreg;
+	u32 autowb_drop_cntreg;
+	u32 _pad_0x144_0x147;
+	u32 ecc_reg2wreccdatabus;
+	u32 ecc_rdeccdata2regbus;
+	u32 ecc_reg2rdeccdatabus;
+	u32 _pad_0x154_0x15f[3];
+	u32 ecc_diagon;
+	u32 ecc_decstat;
+	u32 _pad_0x168_0x16f[2];
+	u32 ecc_errgenaddr_0;
+	u32 ecc_errgenaddr_1;
+	u32 ecc_errgenaddr_2;
+	u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+	u32 ddr_t_main_scheduler_id_coreid;
+	u32 ddr_t_main_scheduler_id_revisionid;
+	u32 ddr_t_main_scheduler_ddrconf;
+	u32 ddr_t_main_scheduler_ddrtiming;
+	u32 ddr_t_main_scheduler_ddrmode;
+	u32 ddr_t_main_scheduler_readlatency;
+	u32 _pad_0x20_0x34[8];
+	u32 ddr_t_main_scheduler_activate;
+	u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+	u32 enable;
+	u32 enable_set;
+	u32 enable_clear;
+	u32 region0;
+	u32 region1;
+	u32 region2;
+	u32 region3;
+	u32 region4;
+	u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+	u32 enable;
+	u32 enable_set;
+	u32 enable_clear;
+	u32 _pad_0xc_0xf;
+	u32 mpuregion0addr;
+	u32 mpuregion1addr;
+	u32 mpuregion2addr;
+	u32 mpuregion3addr;
+	u32 fpga2sdram0region0addr;
+	u32 fpga2sdram0region1addr;
+	u32 fpga2sdram0region2addr;
+	u32 fpga2sdram0region3addr;
+	u32 fpga2sdram1region0addr;
+	u32 fpga2sdram1region1addr;
+	u32 fpga2sdram1region2addr;
+	u32 fpga2sdram1region3addr;
+	u32 fpga2sdram2region0addr;
+	u32 fpga2sdram2region1addr;
+	u32 fpga2sdram2region2addr;
+	u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+	u32 enable;
+	u32 enable_set;
+	u32 enable_clear;
+	u32 hpsregion0addr;
+	u32 hpsregion1addr;
+	u32 hpsregion2addr;
+	u32 hpsregion3addr;
+	u32 hpsregion4addr;
+	u32 hpsregion5addr;
+	u32 hpsregion6addr;
+	u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+	u32 dbgcfg0;
+	u32 dbgcfg1;
+	u32 dbgcfg2;
+	u32 dbgcfg3;
+	u32 dbgcfg4;
+	u32 dbgcfg5;
+	u32 dbgcfg6;
+	u32 reserve0;
+	u32 reserve1;
+	u32 reserve2;
+	u32 ctrlcfg0;
+	u32 ctrlcfg1;
+	u32 ctrlcfg2;
+	u32 ctrlcfg3;
+	u32 ctrlcfg4;
+	u32 ctrlcfg5;
+	u32 ctrlcfg6;
+	u32 ctrlcfg7;
+	u32 ctrlcfg8;
+	u32 ctrlcfg9;
+	u32 dramtiming0;
+	u32 dramodt0;
+	u32 dramodt1;
+	u32 sbcfg0;
+	u32 sbcfg1;
+	u32 sbcfg2;
+	u32 sbcfg3;
+	u32 sbcfg4;
+	u32 sbcfg5;
+	u32 sbcfg6;
+	u32 sbcfg7;
+	u32 caltiming0;
+	u32 caltiming1;
+	u32 caltiming2;
+	u32 caltiming3;
+	u32 caltiming4;
+	u32 caltiming5;
+	u32 caltiming6;
+	u32 caltiming7;
+	u32 caltiming8;
+	u32 caltiming9;
+	u32 caltiming10;
+	u32 dramaddrw;
+	u32 sideband0;
+	u32 sideband1;
+	u32 sideband2;
+	u32 sideband3;
+	u32 sideband4;
+	u32 sideband5;
+	u32 sideband6;
+	u32 sideband7;
+	u32 sideband8;
+	u32 sideband9;
+	u32 sideband10;
+	u32 sideband11;
+	u32 sideband12;
+	u32 sideband13;
+	u32 sideband14;
+	u32 sideband15;
+	u32 dramsts;
+	u32 dbgdone;
+	u32 dbgsignals;
+	u32 dbgreset;
+	u32 dbgmatch;
+	u32 counter0mask;
+	u32 counter1mask;
+	u32 counter0match;
+	u32 counter1match;
+	u32 niosreserve0;
+	u32 niosreserve1;
+	u32 niosreserve2;
+};
+
+#endif /*__ASSEMBLY__ */
+
+#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK		0x1F000000
+#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_SHIFT	24
+#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK		0x00F80000
+#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_SHIFT	19
+#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK		0x0007C000
+#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_SHIFT	14
+#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK	0x00003E00
+#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT	9
+#define IO48_MMR_CTRLCFG0_AC_POS_MASK			0x00000180
+#define IO48_MMR_CTRLCFG0_AC_POS_SHIFT			7
+#define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK		0x00000070
+#define IO48_MMR_CTRLCFG0_DIM_TYPE_SHIFT		4
+#define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK			0x0000000F
+#define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT		0
+
+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM		BIT(30)
+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM		BIT(29)
+#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM		BIT(28)
+#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM		BIT(27)
+#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_DM		BIT(26)
+#define IO48_MMR_CTRLCFG1_DQSTRK_EN			BIT(25)
+#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK		0x01F80000
+#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_SHIFT		19
+#define IO48_MMR_CTRLCFG1_REORDER_READ			BIT(18)
+#define IO48_MMR_CTRLCFG1_DBC3_REORDER_RDATA		BIT(17)
+#define IO48_MMR_CTRLCFG1_DBC2_REORDER_RDATA		BIT(16)
+#define IO48_MMR_CTRLCFG1_DBC1_REORDER_RDATA		BIT(15)
+#define IO48_MMR_CTRLCFG1_DBC0_REORDER_RDATA		BIT(14)
+#define IO48_MMR_CTRLCFG1_CTRL_REORDER_RDATA		BIT(13)
+#define IO48_MMR_CTRLCFG1_REORDER_DATA			BIT(12)
+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_ECC		BIT(11)
+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_ECC		BIT(10)
+#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_ECC		BIT(9)
+#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_ECC		BIT(8)
+#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC		BIT(7)
+#define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK		0x00000060
+#define IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT		5
+#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_MASK	0x0000001F
+#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_SHIFT	0
+
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_MASK		0x3F000000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_SHIFT	24
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK	0x00FC0000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT	18
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK			0x0003F000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT		12
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_MASK			0x00000FC0
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_SHIFT		6
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK		0x0000003F
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_SHIFT		0
+
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK		0x3F000000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT	24
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK			0x00FC0000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT			18
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_MASK		0x0003F000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_SHIFT		12
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK		0x00000FC0
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT		6
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_MASK			0x0000003F
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_SHIFT			0
+
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_MASK		0x3F000000
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_SHIFT	24
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_MASK			0x00FC0000
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_SHIFT			18
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_MASK		0x0003F000
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_SHIFT		12
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK			0x00000FC0
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT			6
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_MASK		0x0000003F
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_SHIFT		0
+
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_MASK			0x3F000000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_SHIFT			24
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_MASK		0x00FC0000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_SHIFT		18
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK		0x0003F000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT	12
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK			0x00000FC0
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT			6
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_MASK		0x0000003F
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_SHIFT		0
+
+#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_MASK		0xFC000000
+#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_SHIFT		26
+#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_MASK		0x03FC0000
+#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_SHIFT		18
+#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_MASK		0x0003F000
+#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_SHIFT		12
+#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK		0x00000FC0
+#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT		6
+#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_MASK		0x0000003F
+#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_SHIFT		0
+
+#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK		0x000000FF
+#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_SHIFT		0
+
+#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK		0x00070000
+#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT		16
+#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK	0x0000C000
+#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT	14
+#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK		0x00003C00
+#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT		10
+#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK		0x000003E0
+#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT		5
+#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK		0x0000001F
+#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SHIFT		0
+
+#define ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK		0x00000003
+
+#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK	BIT(0)
+#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK	BIT(1)
+#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK	BIT(0)
+#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK	BIT(1)
+#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK		BIT(16)
+#define ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK	BIT(16)
+#define ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK		BIT(8)
+#define ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK		BIT(0)
+#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK		BIT(8)
+#define ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK		BIT(0)
+
+#define ALT_ECC_HMC_OCP_SERRCNTREG_VALUE		8
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB	6
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB	12
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB	18
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB	21
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB	26
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB	31
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB	1
+
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB	4
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB	10
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB	2
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB	4
+
+#define ALT_NOC_FW_DDR_END_ADDR_LSB	16
+#define ALT_NOC_FW_DDR_ADDR_MASK	0xFFFF
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK		BIT(0)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK		BIT(1)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK		BIT(2)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK		BIT(3)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK		BIT(4)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK		BIT(5)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK		BIT(6)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK		BIT(7)
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK		BIT(0)
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK		BIT(1)
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK		BIT(2)
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK		BIT(3)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK	BIT(4)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK	BIT(5)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK	BIT(6)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK	BIT(7)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK	BIT(8)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK	BIT(9)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK	BIT(10)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK	BIT(11)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK	BIT(12)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK	BIT(13)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK	BIT(14)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK	BIT(15)
+
+#define ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK		0x0000003F
+#endif /* _SOCFPGA_SDRAM_ARRIA10_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
new file mode 100644
index 000000000..8818a6b96
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
@@ -0,0 +1,465 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright Altera Corporation (C) 2014-2015
+ */
+#ifndef	_SOCFPGA_SDRAM_GEN5_H_
+#define	_SOCFPGA_SDRAM_GEN5_H_
+
+#ifndef __ASSEMBLY__
+
+const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
+
+void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
+void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
+const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
+
+#define SDR_CTRLGRP_ADDRESS	(SOCFPGA_SDR_ADDRESS | 0x5000)
+
+struct socfpga_sdr_ctrl {
+	u32	ctrl_cfg;
+	u32	dram_timing1;
+	u32	dram_timing2;
+	u32	dram_timing3;
+	u32	dram_timing4;	/* 0x10 */
+	u32	lowpwr_timing;
+	u32	dram_odt;
+	u32	extratime1;
+	u32	__padding0[3];
+	u32	dram_addrw;	/* 0x2c */
+	u32	dram_if_width;	/* 0x30 */
+	u32	dram_dev_width;
+	u32	dram_sts;
+	u32	dram_intr;
+	u32	sbe_count;	/* 0x40 */
+	u32	dbe_count;
+	u32	err_addr;
+	u32	drop_count;
+	u32	drop_addr;	/* 0x50 */
+	u32	lowpwr_eq;
+	u32	lowpwr_ack;
+	u32	static_cfg;
+	u32	ctrl_width;	/* 0x60 */
+	u32	cport_width;
+	u32	cport_wmap;
+	u32	cport_rmap;
+	u32	rfifo_cmap;	/* 0x70 */
+	u32	wfifo_cmap;
+	u32	cport_rdwr;
+	u32	port_cfg;
+	u32	fpgaport_rst;	/* 0x80 */
+	u32	__padding1;
+	u32	fifo_cfg;
+	u32	protport_default;
+	u32	prot_rule_addr;	/* 0x90 */
+	u32	prot_rule_id;
+	u32	prot_rule_data;
+	u32	prot_rule_rdwr;
+	u32	__padding2[3];
+	u32	mp_priority;	/* 0xac */
+	u32	mp_weight0;	/* 0xb0 */
+	u32	mp_weight1;
+	u32	mp_weight2;
+	u32	mp_weight3;
+	u32	mp_pacing0;	/* 0xc0 */
+	u32	mp_pacing1;
+	u32	mp_pacing2;
+	u32	mp_pacing3;
+	u32	mp_threshold0;	/* 0xd0 */
+	u32	mp_threshold1;
+	u32	mp_threshold2;
+	u32	__padding3[29];
+	u32	phy_ctrl0;	/* 0x150 */
+	u32	phy_ctrl1;
+	u32	phy_ctrl2;
+};
+
+/* SDRAM configuration structure for the SPL. */
+struct socfpga_sdram_config {
+	u32	ctrl_cfg;
+	u32	dram_timing1;
+	u32	dram_timing2;
+	u32	dram_timing3;
+	u32	dram_timing4;
+	u32	lowpwr_timing;
+	u32	dram_odt;
+	u32	extratime1;
+	u32	dram_addrw;
+	u32	dram_if_width;
+	u32	dram_dev_width;
+	u32	dram_intr;
+	u32	lowpwr_eq;
+	u32	static_cfg;
+	u32	ctrl_width;
+	u32	cport_width;
+	u32	cport_wmap;
+	u32	cport_rmap;
+	u32	rfifo_cmap;
+	u32	wfifo_cmap;
+	u32	cport_rdwr;
+	u32	port_cfg;
+	u32	fpgaport_rst;
+	u32	fifo_cfg;
+	u32	mp_priority;
+	u32	mp_weight0;
+	u32	mp_weight1;
+	u32	mp_weight2;
+	u32	mp_weight3;
+	u32	mp_pacing0;
+	u32	mp_pacing1;
+	u32	mp_pacing2;
+	u32	mp_pacing3;
+	u32	mp_threshold0;
+	u32	mp_threshold1;
+	u32	mp_threshold2;
+	u32	phy_ctrl0;
+};
+
+struct socfpga_sdram_rw_mgr_config {
+	u8	activate_0_and_1;
+	u8	activate_0_and_1_wait1;
+	u8	activate_0_and_1_wait2;
+	u8	activate_1;
+	u8	clear_dqs_enable;
+	u8	guaranteed_read;
+	u8	guaranteed_read_cont;
+	u8	guaranteed_write;
+	u8	guaranteed_write_wait0;
+	u8	guaranteed_write_wait1;
+	u8	guaranteed_write_wait2;
+	u8	guaranteed_write_wait3;
+	u8	idle;
+	u8	idle_loop1;
+	u8	idle_loop2;
+	u8	init_reset_0_cke_0;
+	u8	init_reset_1_cke_0;
+	u8	lfsr_wr_rd_bank_0;
+	u8	lfsr_wr_rd_bank_0_data;
+	u8	lfsr_wr_rd_bank_0_dqs;
+	u8	lfsr_wr_rd_bank_0_nop;
+	u8	lfsr_wr_rd_bank_0_wait;
+	u8	lfsr_wr_rd_bank_0_wl_1;
+	u8	lfsr_wr_rd_dm_bank_0;
+	u8	lfsr_wr_rd_dm_bank_0_data;
+	u8	lfsr_wr_rd_dm_bank_0_dqs;
+	u8	lfsr_wr_rd_dm_bank_0_nop;
+	u8	lfsr_wr_rd_dm_bank_0_wait;
+	u8	lfsr_wr_rd_dm_bank_0_wl_1;
+	union {
+		u8	mrs0_dll_reset;
+		u8	mr_dll_reset;
+	};
+	union {
+		u8	mrs0_dll_reset_mirr;
+		u8	emr_ocd_enable;
+	};
+	union {
+		u8	mrs0_user;
+		u8	mr_user;
+	};
+	union {
+		u8	mrs0_user_mirr;
+		u8	mr_calib;
+	};
+	union {
+		u8	mrs1;
+		u8	emr;
+	};
+	union {
+		u8	mrs2;
+		u8	emr2;
+	};
+	union {
+		u8	mrs3;
+		u8	emr3;
+	};
+	u8	mrs1_mirr;
+	u8	mrs2_mirr;
+	u8	mrs3_mirr;
+	u8	precharge_all;
+	u8	read_b2b;
+	u8	read_b2b_wait1;
+	u8	read_b2b_wait2;
+	union {
+		u8	refresh;
+		u8	refresh_all;
+	};
+	u8	rreturn;
+	u8	sgle_read;
+	union {
+		u8	zqcl;
+		u8	nop;
+	};
+
+	u8	true_mem_data_mask_width;
+	u8	mem_address_mirroring;
+	u8	mem_data_mask_width;
+	u8	mem_data_width;
+	u8	mem_dq_per_read_dqs;
+	u8	mem_dq_per_write_dqs;
+	u8	mem_if_read_dqs_width;
+	u8	mem_if_write_dqs_width;
+	u8	mem_number_of_cs_per_dimm;
+	u8	mem_number_of_ranks;
+	u8	mem_virtual_groups_per_read_dqs;
+	u8	mem_virtual_groups_per_write_dqs;
+};
+
+struct socfpga_sdram_io_config {
+	u16	delay_per_opa_tap;
+	u8	delay_per_dchain_tap;
+	u8	delay_per_dqs_en_dchain_tap;
+	u8	dll_chain_length;
+	u8	dqdqs_out_phase_max;
+	u8	dqs_en_delay_max;
+	u8	dqs_en_delay_offset;
+	u8	dqs_en_phase_max;
+	u8	dqs_in_delay_max;
+	u8	dqs_in_reserve;
+	u8	dqs_out_reserve;
+	u8	io_in_delay_max;
+	u8	io_out1_delay_max;
+	u8	io_out2_delay_max;
+	u8	shift_dqs_en_when_shift_dqs;
+};
+
+struct socfpga_sdram_misc_config {
+	u32	reg_file_init_seq_signature;
+	u16	afi_clk_freq;
+	u8	afi_rate_ratio;
+	u8	calib_lfifo_offset;
+	u8	calib_vfifo_offset;
+	u8	enable_super_quick_calibration;
+	u8	max_latency_count_width;
+	u8	read_valid_fifo_size;
+	u8	tinit_cntr0_val;
+	u8	tinit_cntr1_val;
+	u8	tinit_cntr2_val;
+	u8	treset_cntr0_val;
+	u8	treset_cntr1_val;
+	u8	treset_cntr2_val;
+};
+
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
+/* Register template: sdr::ctrlgrp::dramtiming1                            */
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming2                            */
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
+/* Register template: sdr::ctrlgrp::dramtiming3                            */
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming4                            */
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::lowpwrtiming                           */
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
+/* Register template: sdr::ctrlgrp::dramaddrw                              */
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
+/* Register template: sdr::ctrlgrp::dramifwidth                            */
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::dramdevwidth                           */
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramintr                               */
+#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
+#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
+/* Register template: sdr::ctrlgrp::staticcfg                              */
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
+#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
+#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::ctrlwidth                              */
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::cportwidth                             */
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::cportwmap                              */
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::cportrmap                              */
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::rfifocmap                              */
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::wfifocmap                              */
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::cportrdwr                              */
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::portcfg                                */
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::fifocfg                                */
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::mppriority                             */
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_0                   */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_1                   */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_2                   */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_3                   */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_0                   */
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_1                   */
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_2                   */
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_3                   */
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0       */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
+#define  \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1       */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2       */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
+0x0000ffff
+/* Register template: sdr::ctrlgrp::remappriority                          */
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0                     */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
+ (((x) << 10) & 0x00000c00)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
+ (((x) << 6) & 0x000000c0)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
+ (((x) << 8) & 0x00000100)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
+ (((x) << 9) & 0x00000200)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
+ (((x) << 4) & 0x00000030)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
+ (((x) << 2) & 0x0000000c)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
+ (((x) << 0) & 0x00000003)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1                     */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2                     */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::dramodt                                */
+#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
+#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
+#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
+#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
+/* Field instance: sdr::ctrlgrp::dramsts                                   */
+#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
+#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
+/* Register template: sdr::ctrlgrp::extratime1                             */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
+
+/* SDRAM width macro for configuration with ECC */
+#define SDRAM_WIDTH_32BIT_WITH_ECC	40
+#define SDRAM_WIDTH_16BIT_WITH_ECC	24
+
+#endif
+#endif /* _SOCFPGA_SDRAM_GEN5_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
new file mode 100644
index 000000000..d5a11122c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_SECURE_REG_HELPER_H_
+#define	_SECURE_REG_HELPER_H_
+
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3
+#define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2 4
+
+int socfpga_secure_reg_read32(u32 id, u32 *val);
+int socfpga_secure_reg_write32(u32 id, u32 val);
+int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val);
+
+#endif /* _SECURE_REG_HELPER_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/secure_vab.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/secure_vab.h
new file mode 100644
index 000000000..42588588e
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/secure_vab.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef	_SECURE_VAB_H_
+#define	_SECURE_VAB_H_
+
+#include <linux/sizes.h>
+#include <linux/stddef.h>
+#include <u-boot/sha512.h>
+
+#define VAB_DATA_SZ			64
+
+#define SDM_CERT_MAGIC_NUM		0x25D04E7F
+#define FCS_HPS_VAB_MAGIC_NUM		0xD0564142
+
+#define MAX_CERT_SIZE			(SZ_4K)
+
+/*
+ * struct fcs_hps_vab_certificate_data
+ * @vab_cert_magic_num: VAB Certificate Magic Word (0xD0564142)
+ * @flags: TBD
+ * @fcs_data: Data words being certificate signed.
+ * @cert_sign_keychain: Certificate Signing Keychain
+ */
+struct fcs_hps_vab_certificate_data {
+	u32 vab_cert_magic_num;		/* offset 0x10 */
+	u32 flags;
+	u8 rsvd0_1[8];
+	u8 fcs_sha384[SHA384_SUM_LEN];	/* offset 0x20 */
+};
+
+/*
+ * struct fcs_hps_vab_certificate_header
+ * @cert_magic_num: Certificate Magic Word (0x25D04E7F)
+ * @cert_data_sz: size of this certificate header (0x80)
+ *	Includes magic number all the way to the certificate
+ *      signing keychain (excludes cert. signing keychain)
+ * @cert_ver: Certificate Version
+ * @cert_type: Certificate Type
+ * @data: VAB HPS Image Certificate data
+ */
+struct fcs_hps_vab_certificate_header {
+	u32 cert_magic_num;		/* offset 0 */
+	u32 cert_data_sz;
+	u32 cert_ver;
+	u32 cert_type;
+	struct fcs_hps_vab_certificate_data d;	/* offset 0x10 */
+	/* keychain starts at offset 0x50 */
+};
+
+#define VAB_CERT_HEADER_SIZE	sizeof(struct fcs_hps_vab_certificate_header)
+#define VAB_CERT_MAGIC_OFFSET	offsetof \
+				(struct fcs_hps_vab_certificate_header, d)
+#define VAB_CERT_FIT_SHA384_OFFSET	offsetof \
+					(struct fcs_hps_vab_certificate_data, \
+					 fcs_sha384[0])
+
+int socfpga_vendor_authentication(void **p_image, size_t *p_size);
+
+#endif /* _SECURE_VAB_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/smc_api.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/smc_api.h
new file mode 100644
index 000000000..6b5b7eadc
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/smc_api.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#ifndef _SMC_API_H_
+#define _SMC_API_H_
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+		     u32 *resp_buf);
+int smc_get_usercode(u32 *usercode);
+
+#endif /* _SMC_API_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager.h
new file mode 100644
index 000000000..5603eaa3d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ */
+
+#ifndef _SYSTEM_MANAGER_H_
+#define _SYSTEM_MANAGER_H_
+
+phys_addr_t socfpga_get_sysmgr_addr(void);
+
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
+#include <asm/arch/system_manager_soc64.h>
+#else
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	BIT(1)
+#define SYSMGR_ECC_OCRAM_EN	BIT(0)
+#define SYSMGR_ECC_OCRAM_SERR	BIT(3)
+#define SYSMGR_ECC_OCRAM_DERR	BIT(4)
+#define SYSMGR_FPGAINTF_USEFPGA	0x1
+#define SYSMGR_FPGAINTF_SPIM0	BIT(0)
+#define SYSMGR_FPGAINTF_SPIM1	BIT(1)
+#define SYSMGR_FPGAINTF_EMAC0	BIT(2)
+#define SYSMGR_FPGAINTF_EMAC1	BIT(3)
+#define SYSMGR_FPGAINTF_NAND	BIT(4)
+#define SYSMGR_FPGAINTF_SDMMC	BIT(5)
+
+#define SYSMGR_SDMMC_DRVSEL_SHIFT	0
+
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
+
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V		0x0
+#define VOLTAGE_SEL_1P8V	0x1
+#define VOLTAGE_SEL_2P5V	0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE	0
+#define INPUT_BUF_1P8V		1
+#define INPUT_BUF_2P5V3V	2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE		0
+#define WK_PU_ENABLE		1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW		0
+#define PU_SLW_RT_FAST		1
+#define PU_SLW_RT_DEFAULT	PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW		0
+#define PD_SLW_RT_FAST		1
+#define PD_SLW_RT_DEFAULT	PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT	0x10
+#define PD_DRV_STRG_DEFAULT	0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB		0
+#define PD_SLW_RT_LSB		5
+#define PU_DRV_STRG_LSB		8
+#define PU_SLW_RT_LSB		13
+#define WK_PU_LSB		16
+#define INPUT_BUF_LSB		17
+#define BIAS_TRIM_LSB		19
+#define VOLTAGE_SEL_LSB		0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK	BIT(0)
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK	BIT(4)
+#define ALT_SYSMGR_NOC_F2H_SET_MSK	BIT(8)
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK	BIT(16)
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK	BIT(20)
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK	BIT(24)
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK	BIT(0)
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK	BIT(1)
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK	BIT(1)
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/system_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/system_manager_arria10.h>
+#endif
+
+#define SYSMGR_GET_BOOTINFO_BSEL(bsel)		\
+		(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
+#include <linux/bitops.h>
+#endif
+#endif /* _SYSTEM_MANAGER_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
new file mode 100644
index 000000000..e4fc6d2e5
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _SYSTEM_MANAGER_ARRIA10_H_
+#define _SYSTEM_MANAGER_ARRIA10_H_
+
+#define SYSMGR_A10_WDDBG			0x08
+#define SYSMGR_A10_BOOTINFO			0x0c
+#define SYSMGR_A10_DMA				0x20
+#define SYSMGR_A10_DMA_PERIPH			0x24
+#define SYSMGR_A10_SDMMC			0x28
+#define SYSMGR_A10_SDMMC_L3MASTER		0x2c
+#define SYSMGR_A10_EMAC_GLOBAL			0x40
+#define SYSMGR_A10_EMAC0			0x44
+#define SYSMGR_A10_EMAC1			0x48
+#define SYSMGR_A10_EMAC2			0x4c
+#define SYSMGR_A10_FPGAINTF_EN_GLOBAL		0x60
+#define SYSMGR_A10_FPGAINTF_EN0			0x64
+#define SYSMGR_A10_FPGAINTF_EN1			0x68
+#define SYSMGR_A10_FPGAINTF_EN2			0x6c
+#define SYSMGR_A10_FPGAINTF_EN3			0x70
+#define SYSMGR_A10_ECC_INTMASK_VAL		0x90
+#define SYSMGR_A10_ECC_INTMASK_SET		0x94
+#define SYSMGR_A10_ECC_INTMASK_CLR		0x98
+#define SYSMGR_A10_NOC_TIMEOUT			0xc0
+#define SYSMGR_A10_NOC_IDLEREQ_SET		0xc4
+#define SYSMGR_A10_NOC_IDLEREQ_CLR		0xc8
+#define SYSMGR_A10_NOC_IDLEREQ_VAL		0xcc
+#define SYSMGR_A10_NOC_IDLEACK			0xd0
+#define SYSMGR_A10_NOC_IDLESTATUS		0xd4
+#define SYSMGR_A10_FPGA2SOC_CTRL		0xd8
+
+#define SYSMGR_SDMMC				SYSMGR_A10_SDMMC
+
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
+#define SYSMGR_BOOTINFO_BSEL_SHIFT	12
+
+#endif /* _SYSTEM_MANAGER_ARRIA10_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
new file mode 100644
index 000000000..a63a4ee27
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ */
+
+#ifndef _SYSTEM_MANAGER_GEN5_H_
+#define _SYSTEM_MANAGER_GEN5_H_
+
+#ifndef __ASSEMBLY__
+
+void sysmgr_pinmux_init(void);
+void sysmgr_config_warmrstcfgio(int enable);
+
+void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
+
+#define SYSMGR_GEN5_WDDBG			0x10
+#define SYSMGR_GEN5_BOOTINFO			0x14
+#define SYSMGR_GEN5_FPGAINFGRP_GBL		0x20
+#define SYSMGR_GEN5_FPGAINFGRP_INDIV		0x24
+#define SYSMGR_GEN5_FPGAINFGRP_MODULE		0x28
+#define SYSMGR_GEN5_SCANMGRGRP_CTRL		0x30
+#define SYSMGR_GEN5_ISWGRP_HANDOFF		0x80
+#define SYSMGR_GEN5_ROMCODEGRP_CTRL		0xc0
+#define SYSMGR_GEN5_WARMRAMGRP_EN		0xe0
+#define SYSMGR_GEN5_SDMMC			0x108
+#define SYSMGR_GEN5_ECCGRP_OCRAM		0x144
+#define SYSMGR_GEN5_EMACIO			0x400
+#define SYSMGR_GEN5_NAND_USEFPGA		0x6f0
+#define SYSMGR_GEN5_RGMII1_USEFPGA		0x6f8
+#define SYSMGR_GEN5_SDMMC_USEFPGA		0x708
+#define SYSMGR_GEN5_RGMII0_USEFPGA		0x714
+#define SYSMGR_GEN5_SPIM1_USEFPGA		0x730
+#define SYSMGR_GEN5_SPIM0_USEFPGA		0x738
+
+#define SYSMGR_SDMMC				SYSMGR_GEN5_SDMMC
+
+#define SYSMGR_ISWGRP_HANDOFF_OFFSET(i)	\
+	SYSMGR_GEN5_ISWGRP_HANDOFF + ((i) * sizeof(u32))
+#endif
+
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	3
+#define SYSMGR_BOOTINFO_BSEL_SHIFT	0
+
+#endif /* _SYSTEM_MANAGER_GEN5_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
new file mode 100644
index 000000000..fc4e17821
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _SYSTEM_MANAGER_SOC64_H_
+#define _SYSTEM_MANAGER_SOC64_H_
+
+#include <linux/bitops.h>
+void sysmgr_pinmux_init(void);
+void populate_sysmgr_fpgaintf_module(void);
+void populate_sysmgr_pinmux(void);
+
+#define SYSMGR_SOC64_WDDBG			0x08
+#define SYSMGR_SOC64_DMA			0x20
+#define SYSMGR_SOC64_DMA_PERIPH			0x24
+#define SYSMGR_SOC64_SDMMC			0x28
+#define SYSMGR_SOC64_SDMMC_L3MASTER		0x2c
+#define SYSMGR_SOC64_EMAC_GLOBAL		0x40
+#define SYSMGR_SOC64_EMAC0			0x44
+#define SYSMGR_SOC64_EMAC1			0x48
+#define SYSMGR_SOC64_EMAC2			0x4c
+#define SYSMGR_SOC64_EMAC0_ACE			0x50
+#define SYSMGR_SOC64_EMAC1_ACE			0x54
+#define SYSMGR_SOC64_EMAC2_ACE			0x58
+#define SYSMGR_SOC64_NAND_AXUSER		0x5c
+#define SYSMGR_SOC64_FPGAINTF_EN1		0x68
+#define SYSMGR_SOC64_FPGAINTF_EN2		0x6c
+#define SYSMGR_SOC64_FPGAINTF_EN3		0x70
+#define SYSMGR_SOC64_DMA_L3MASTER		0x74
+#define SYSMGR_SOC64_HMC_CLK			0xb4
+#define SYSMGR_SOC64_IO_PA_CTRL			0xb8
+#define SYSMGR_SOC64_NOC_TIMEOUT		0xc0
+#define SYSMGR_SOC64_NOC_IDLEREQ_SET		0xc4
+#define SYSMGR_SOC64_NOC_IDLEREQ_CLR		0xc8
+#define SYSMGR_SOC64_NOC_IDLEREQ_VAL		0xcc
+#define SYSMGR_SOC64_NOC_IDLEACK		0xd0
+#define SYSMGR_SOC64_NOC_IDLESTATUS		0xd4
+#define SYSMGR_SOC64_FPGA2SOC_CTRL		0xd8
+#define SYSMGR_SOC64_FPGA_CONFIG		0xdc
+#define SYSMGR_SOC64_IOCSRCLK_GATE		0xe0
+#define SYSMGR_SOC64_GPO			0xe4
+#define SYSMGR_SOC64_GPI			0xe8
+#define SYSMGR_SOC64_MPU			0xf0
+/*
+ * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit
+ * storing qspi ref clock (kHz)
+ */
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0		0x200
+/* store osc1 clock freq */
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1		0x204
+/* store fpga clock freq */
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2		0x208
+/* reserved for customer use */
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3		0x20c
+/* store PSCI_CPU_ON value */
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4		0x210
+/* store PSCI_CPU_ON value */
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5		0x214
+/* store VBAR_EL3 value */
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6		0x218
+/* store VBAR_EL3 value */
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7		0x21c
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8		0x220
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9		0x224
+#define SYSMGR_SOC64_PINSEL0			0x1000
+#define SYSMGR_SOC64_IOCTRL0			0x1130
+#define SYSMGR_SOC64_EMAC0_USEFPGA		0x1300
+#define SYSMGR_SOC64_EMAC1_USEFPGA		0x1304
+#define SYSMGR_SOC64_EMAC2_USEFPGA		0x1308
+#define SYSMGR_SOC64_I2C0_USEFPGA		0x130c
+#define SYSMGR_SOC64_I2C1_USEFPGA		0x1310
+#define SYSMGR_SOC64_I2C_EMAC0_USEFPGA		0x1314
+#define SYSMGR_SOC64_I2C_EMAC1_USEFPGA		0x1318
+#define SYSMGR_SOC64_I2C_EMAC2_USEFPGA		0x131c
+#define SYSMGR_SOC64_NAND_USEFPGA		0x1320
+#define SYSMGR_SOC64_SPIM0_USEFPGA		0x1328
+#define SYSMGR_SOC64_SPIM1_USEFPGA		0x132c
+#define SYSMGR_SOC64_SPIS0_USEFPGA		0x1330
+#define SYSMGR_SOC64_SPIS1_USEFPGA		0x1334
+#define SYSMGR_SOC64_UART0_USEFPGA		0x1338
+#define SYSMGR_SOC64_UART1_USEFPGA		0x133c
+#define SYSMGR_SOC64_MDIO0_USEFPGA		0x1340
+#define SYSMGR_SOC64_MDIO1_USEFPGA		0x1344
+#define SYSMGR_SOC64_MDIO2_USEFPGA		0x1348
+#define SYSMGR_SOC64_JTAG_USEFPGA		0x1350
+#define SYSMGR_SOC64_SDMMC_USEFPGA		0x1354
+#define SYSMGR_SOC64_HPS_OSC_CLK		0x1358
+#define SYSMGR_SOC64_IODELAY0			0x1400
+
+/*
+ * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
+ * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit
+ * storing qspi ref clock (kHz)
+ */
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK		GENMASK(27, 0)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK	BIT(31)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK		BIT(30)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK	(BIT(29) | BIT(28))
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT	28
+
+#define SYSMGR_SDMMC				SYSMGR_SOC64_SDMMC
+
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	BIT(1)
+#define SYSMGR_ECC_OCRAM_EN	BIT(0)
+#define SYSMGR_ECC_OCRAM_SERR	BIT(3)
+#define SYSMGR_ECC_OCRAM_DERR	BIT(4)
+#define SYSMGR_FPGACONFIG_FPGA_COMPLETE		BIT(0)
+#define SYSMGR_FPGACONFIG_EARLY_USERMODE	BIT(1)
+#define SYSMGR_FPGACONFIG_READY_MASK	(SYSMGR_FPGACONFIG_FPGA_COMPLETE | \
+					 SYSMGR_FPGACONFIG_EARLY_USERMODE)
+
+#define SYSMGR_FPGAINTF_USEFPGA	0x1
+#define SYSMGR_FPGAINTF_NAND	BIT(4)
+#define SYSMGR_FPGAINTF_SDMMC	BIT(8)
+#define SYSMGR_FPGAINTF_SPIM0	BIT(16)
+#define SYSMGR_FPGAINTF_SPIM1	BIT(24)
+#define SYSMGR_FPGAINTF_EMAC0	BIT(0)
+#define SYSMGR_FPGAINTF_EMAC1	BIT(8)
+#define SYSMGR_FPGAINTF_EMAC2	BIT(16)
+
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
+#define SYSMGR_SDMMC_DRVSEL_SHIFT	0
+
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
+
+#define SYSMGR_NOC_H2F_MSK		0x00000001
+#define SYSMGR_NOC_LWH2F_MSK		0x00000010
+#define SYSMGR_HMC_CLK_STATUS_MSK	0x00000001
+
+#define SYSMGR_DMA_IRQ_NS		0xFF000000
+#define SYSMGR_DMA_MGR_NS		0x00010000
+
+#define SYSMGR_DMAPERIPH_ALL_NS		0xFFFFFFFF
+
+#define SYSMGR_WDDBG_PAUSE_ALL_CPU	0x0F0F0F0F
+
+#endif /* _SYSTEM_MANAGER_SOC64_H_ */
diff --git a/roms/u-boot/arch/arm/mach-socfpga/include/mach/timer.h b/roms/u-boot/arch/arm/mach-socfpga/include/mach/timer.h
new file mode 100644
index 000000000..82596e412
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/include/mach/timer.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+
+#ifndef _SOCFPGA_TIMER_H_
+#define _SOCFPGA_TIMER_H_
+
+struct socfpga_timer {
+	u32	load_val;
+	u32	curr_val;
+	u32	ctrl;
+	u32	eoi;
+	u32	int_stat;
+};
+
+#endif
diff --git a/roms/u-boot/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/roms/u-boot/arch/arm/mach-socfpga/lowlevel_init_soc64.S
new file mode 100644
index 000000000..612ea8a03
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/lowlevel_init_soc64.S
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+ENTRY(lowlevel_init)
+	mov	x29, lr			/* Save LR */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+wait_for_atf:
+	ldr	x4, =CPU_RELEASE_ADDR
+	ldr	x5, [x4]
+	cbz	x5, slave_wait_atf
+	br	x5
+slave_wait_atf:
+	branch_if_slave x0, wait_for_atf
+#else
+	branch_if_slave x0, 1f
+#endif
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+1:
+#if defined(CONFIG_GICV3)
+	ldr	x0, =GICR_BASE
+	bl	gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+	ldr	x0, =GICD_BASE
+	ldr	x1, =GICC_BASE
+	bl	gic_init_secure_percpu
+#endif
+#endif
+
+#ifdef CONFIG_ARMV8_MULTIENTRY
+	branch_if_master x0, x1, 2f
+
+	/*
+	 * Slave should wait for master clearing spin table.
+	 * This sync prevent slaves observing incorrect
+	 * value of spin table and jumping to wrong place.
+	 */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+	ldr	x0, =GICC_BASE
+#endif
+	bl	gic_wait_for_interrupt
+#endif
+
+	/*
+	 * All slaves will enter EL2 and optionally EL1.
+	 */
+	adr	x4, lowlevel_in_el2
+	ldr	x5, =ES_TO_AARCH64
+	bl	armv8_switch_to_el2
+
+lowlevel_in_el2:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	adr	x4, lowlevel_in_el1
+	ldr	x5, =ES_TO_AARCH64
+	bl	armv8_switch_to_el1
+
+lowlevel_in_el1:
+#endif
+
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+2:
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(lowlevel_init)
diff --git a/roms/u-boot/arch/arm/mach-socfpga/mailbox_s10.c b/roms/u-boot/arch/arm/mach-socfpga/mailbox_s10.c
new file mode 100644
index 000000000..101af2385
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/mailbox_s10.c
@@ -0,0 +1,501 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/secure.h>
+#include <asm/system.h>
+#include <hang.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MBOX_READL(reg)			\
+	 readl(SOCFPGA_MAILBOX_ADDRESS + (reg))
+
+#define MBOX_WRITEL(data, reg)		\
+	writel(data, SOCFPGA_MAILBOX_ADDRESS + (reg))
+
+#define MBOX_READ_RESP_BUF(rout)	\
+	MBOX_READL(MBOX_RESP_BUF + ((rout) * sizeof(u32)))
+
+#define MBOX_WRITE_CMD_BUF(data, cin)	\
+	MBOX_WRITEL(data, MBOX_CMD_BUF + ((cin) * sizeof(u32)))
+
+static __always_inline int mbox_polling_resp(u32 rout)
+{
+	u32 rin;
+	unsigned long i = 2000;
+
+	while (i) {
+		rin = MBOX_READL(MBOX_RIN);
+		if (rout != rin)
+			return 0;
+
+		udelay(1000);
+		i--;
+	}
+
+	return -ETIMEDOUT;
+}
+
+static __always_inline int mbox_is_cmdbuf_full(u32 cin)
+{
+	return (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == MBOX_READL(MBOX_COUT));
+}
+
+static __always_inline int mbox_is_cmdbuf_empty(u32 cin)
+{
+	return (((MBOX_READL(MBOX_COUT) + 1) % MBOX_CMD_BUFFER_SIZE) == cin);
+}
+
+static __always_inline int mbox_wait_for_cmdbuf_empty(u32 cin)
+{
+	int timeout = 2000;
+
+	while (timeout) {
+		if (mbox_is_cmdbuf_empty(cin))
+			return 0;
+		udelay(1000);
+		timeout--;
+	}
+
+	return -ETIMEDOUT;
+}
+
+static __always_inline int mbox_write_cmd_buffer(u32 *cin, u32 data,
+						 int *is_cmdbuf_overflow)
+{
+	int timeout = 1000;
+
+	while (timeout) {
+		if (mbox_is_cmdbuf_full(*cin)) {
+			if (is_cmdbuf_overflow &&
+			    *is_cmdbuf_overflow == 0) {
+				/* Trigger SDM doorbell */
+				MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
+				*is_cmdbuf_overflow = 1;
+			}
+			udelay(1000);
+		} else {
+			/* write header to circular buffer */
+			MBOX_WRITE_CMD_BUF(data, (*cin)++);
+			*cin %= MBOX_CMD_BUFFER_SIZE;
+			MBOX_WRITEL(*cin, MBOX_CIN);
+			break;
+		}
+		timeout--;
+	}
+
+	if (!timeout)
+		return -ETIMEDOUT;
+
+	/* Wait for the SDM to drain the FIFO command buffer */
+	if (is_cmdbuf_overflow && *is_cmdbuf_overflow)
+		return mbox_wait_for_cmdbuf_empty(*cin);
+
+	return 0;
+}
+
+/* Check for available slot and write to circular buffer.
+ * It also update command valid offset (cin) register.
+ */
+static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
+						       u32 *arg)
+{
+	int i, ret;
+	int is_cmdbuf_overflow = 0;
+	u32 cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE;
+
+	ret = mbox_write_cmd_buffer(&cin, header, &is_cmdbuf_overflow);
+	if (ret)
+		return ret;
+
+	/* write arguments */
+	for (i = 0; i < len; i++) {
+		is_cmdbuf_overflow = 0;
+		ret = mbox_write_cmd_buffer(&cin, arg[i], &is_cmdbuf_overflow);
+		if (ret)
+			return ret;
+	}
+
+	/* If SDM doorbell is not triggered after the last data is
+	 * written into mailbox FIFO command buffer, trigger the
+	 * SDM doorbell again to ensure SDM able to read the remaining
+	 * data.
+	 */
+	if (!is_cmdbuf_overflow)
+		MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
+
+	return 0;
+}
+
+/* Check the command and fill it into circular buffer */
+static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
+						 u8 is_indirect, u32 len,
+						 u32 *arg)
+{
+	u32 header;
+	int ret;
+
+	if (cmd > MBOX_MAX_CMD_INDEX)
+		return -EINVAL;
+
+	header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
+				 (is_indirect) ? 1 : 0, cmd);
+
+	ret = mbox_fill_cmd_circular_buff(header, len, arg);
+
+	return ret;
+}
+
+/* Send command only without waiting for responses from SDM */
+static __always_inline int mbox_send_cmd_only_common(u8 id, u32 cmd,
+						     u8 is_indirect, u32 len,
+						     u32 *arg)
+{
+	return mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+}
+
+/* Return number of responses received in buffer */
+static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
+{
+	u32 rin;
+	u32 rout;
+	u32 resp_len = 0;
+
+	/* clear doorbell from SDM if it was SET */
+	if (MBOX_READL(MBOX_DOORBELL_FROM_SDM) & 1)
+		MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
+
+	/* read current response offset */
+	rout = MBOX_READL(MBOX_ROUT);
+	/* read response valid offset */
+	rin = MBOX_READL(MBOX_RIN);
+
+	while (rin != rout && (resp_len < resp_buf_max_len)) {
+		/* Response received */
+		if (resp_buf)
+			resp_buf[resp_len++] = MBOX_READ_RESP_BUF(rout);
+
+		rout++;
+		/* wrapping around when it reach the buffer size */
+		rout %= MBOX_RESP_BUFFER_SIZE;
+		/* update next ROUT */
+		MBOX_WRITEL(rout, MBOX_ROUT);
+	}
+
+	return resp_len;
+}
+
+/* Support one command and up to 31 words argument length only */
+static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect,
+						u32 len, u32 *arg, u8 urgent,
+						u32 *resp_buf_len,
+						u32 *resp_buf)
+{
+	u32 rin;
+	u32 resp;
+	u32 rout;
+	u32 status;
+	u32 resp_len;
+	u32 buf_len;
+	int ret;
+
+	if (urgent) {
+		/* Read status because it is toggled */
+		status = MBOX_READL(MBOX_STATUS) & MBOX_STATUS_UA_MSK;
+		/* Write urgent command to urgent register */
+		MBOX_WRITEL(cmd, MBOX_URG);
+		/* write doorbell */
+		MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
+	} else {
+		ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+		if (ret)
+			return ret;
+	}
+
+	while (1) {
+		ret = 1000;
+
+		/* Wait for doorbell from SDM */
+		do {
+			if (MBOX_READL(MBOX_DOORBELL_FROM_SDM))
+				break;
+			udelay(1000);
+		} while (--ret);
+
+		if (!ret)
+			return -ETIMEDOUT;
+
+		/* clear interrupt */
+		MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
+
+		if (urgent) {
+			u32 new_status = MBOX_READL(MBOX_STATUS);
+
+			/* Urgent ACK is toggled */
+			if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
+				return 0;
+
+			return -ECOMM;
+		}
+
+		/* read current response offset */
+		rout = MBOX_READL(MBOX_ROUT);
+
+		/* read response valid offset */
+		rin = MBOX_READL(MBOX_RIN);
+
+		if (rout != rin) {
+			/* Response received */
+			resp = MBOX_READ_RESP_BUF(rout);
+			rout++;
+			/* wrapping around when it reach the buffer size */
+			rout %= MBOX_RESP_BUFFER_SIZE;
+			/* update next ROUT */
+			MBOX_WRITEL(rout, MBOX_ROUT);
+
+			/* check client ID and ID */
+			if ((MBOX_RESP_CLIENT_GET(resp) ==
+			     MBOX_CLIENT_ID_UBOOT) &&
+			    (MBOX_RESP_ID_GET(resp) == id)) {
+				int resp_err = MBOX_RESP_ERR_GET(resp);
+
+				if (resp_buf_len) {
+					buf_len = *resp_buf_len;
+					*resp_buf_len = 0;
+				} else {
+					buf_len = 0;
+				}
+
+				resp_len = MBOX_RESP_LEN_GET(resp);
+				while (resp_len) {
+					ret = mbox_polling_resp(rout);
+					if (ret)
+						return ret;
+					/* we need to process response buffer
+					 * even caller doesn't need it
+					 */
+					resp = MBOX_READ_RESP_BUF(rout);
+					rout++;
+					resp_len--;
+					rout %= MBOX_RESP_BUFFER_SIZE;
+					MBOX_WRITEL(rout, MBOX_ROUT);
+					if (buf_len) {
+						/* copy response to buffer */
+						resp_buf[*resp_buf_len] = resp;
+						(*resp_buf_len)++;
+						buf_len--;
+					}
+				}
+				return resp_err;
+			}
+		}
+	}
+
+	return -EIO;
+}
+
+static __always_inline int mbox_send_cmd_common_retry(u8 id, u32 cmd,
+						      u8 is_indirect,
+						      u32 len, u32 *arg,
+						      u8 urgent,
+						      u32 *resp_buf_len,
+						      u32 *resp_buf)
+{
+	int ret;
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		ret = mbox_send_cmd_common(id, cmd, is_indirect, len, arg,
+					   urgent, resp_buf_len, resp_buf);
+		if (ret == MBOX_RESP_TIMEOUT || ret == MBOX_RESP_DEVICE_BUSY)
+			udelay(2000); /* wait for 2ms before resend */
+		else
+			break;
+	}
+
+	return ret;
+}
+
+int mbox_init(void)
+{
+	int ret;
+
+	/* enable mailbox interrupts */
+	MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
+
+	/* Ensure urgent request is cleared */
+	MBOX_WRITEL(0, MBOX_URG);
+
+	/* Ensure the Doorbell Interrupt is cleared */
+	MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
+			    NULL, 1, 0, NULL);
+	if (ret)
+		return ret;
+
+	/* Renable mailbox interrupts after MBOX_RESTART */
+	MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
+
+	return 0;
+}
+
+#ifdef CONFIG_CADENCE_QSPI
+int mbox_qspi_close(void)
+{
+	return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
+			     0, NULL, 0, 0, NULL);
+}
+
+int mbox_qspi_open(void)
+{
+	int ret;
+	u32 resp_buf[1];
+	u32 resp_buf_len;
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
+			    0, NULL, 0, 0, NULL);
+	if (ret) {
+		/* retry again by closing and reopen the QSPI again */
+		ret = mbox_qspi_close();
+		if (ret)
+			return ret;
+
+		ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
+				    MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
+		if (ret)
+			return ret;
+	}
+
+	/* HPS will directly control the QSPI controller, no longer mailbox */
+	resp_buf_len = 1;
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
+			    0, NULL, 0, (u32 *)&resp_buf_len,
+			    (u32 *)&resp_buf);
+	if (ret)
+		goto error;
+
+	/* Store QSPI controller ref clock frequency */
+	ret = cm_set_qspi_controller_clk_hz(resp_buf[0]);
+	if (ret)
+		goto error;
+
+	return 0;
+
+error:
+	mbox_qspi_close();
+
+	return ret;
+}
+#endif /* CONFIG_CADENCE_QSPI */
+
+int mbox_reset_cold(void)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	psci_system_reset();
+#else
+	int ret;
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
+			    0, NULL, 0, 0, NULL);
+	if (ret) {
+		/* mailbox sent failure, wait for watchdog to kick in */
+		hang();
+	}
+#endif
+	return 0;
+}
+
+/* Accepted commands: CONFIG_STATUS or RECONFIG_STATUS */
+static __always_inline int mbox_get_fpga_config_status_common(u32 cmd)
+{
+	u32 reconfig_status_resp_len;
+	u32 reconfig_status_resp[RECONFIG_STATUS_RESPONSE_LEN];
+	int ret;
+
+	reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
+	ret = mbox_send_cmd_common_retry(MBOX_ID_UBOOT, cmd,
+					 MBOX_CMD_DIRECT, 0, NULL, 0,
+					 &reconfig_status_resp_len,
+					 reconfig_status_resp);
+
+	if (ret)
+		return ret;
+
+	/* Check for any error */
+	ret = reconfig_status_resp[RECONFIG_STATUS_STATE];
+	if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
+		return ret;
+
+	/* Make sure nStatus is not 0 */
+	ret = reconfig_status_resp[RECONFIG_STATUS_PIN_STATUS];
+	if (!(ret & RCF_PIN_STATUS_NSTATUS))
+		return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+
+	ret = reconfig_status_resp[RECONFIG_STATUS_SOFTFUNC_STATUS];
+	if (ret & RCF_SOFTFUNC_STATUS_SEU_ERROR)
+		return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+
+	if ((ret & RCF_SOFTFUNC_STATUS_CONF_DONE) &&
+	    (ret & RCF_SOFTFUNC_STATUS_INIT_DONE) &&
+	    !reconfig_status_resp[RECONFIG_STATUS_STATE])
+		return 0;	/* configuration success */
+
+	return MBOX_CFGSTAT_STATE_CONFIG;
+}
+
+int mbox_get_fpga_config_status(u32 cmd)
+{
+	return mbox_get_fpga_config_status_common(cmd);
+}
+
+int __secure mbox_get_fpga_config_status_psci(u32 cmd)
+{
+	return mbox_get_fpga_config_status_common(cmd);
+}
+
+int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
+		  u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
+{
+	return mbox_send_cmd_common_retry(id, cmd, is_indirect, len, arg,
+					  urgent, resp_buf_len, resp_buf);
+}
+
+int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
+				u32 *arg, u8 urgent, u32 *resp_buf_len,
+				u32 *resp_buf)
+{
+	return mbox_send_cmd_common_retry(id, cmd, is_indirect, len, arg,
+					  urgent, resp_buf_len, resp_buf);
+}
+
+int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
+{
+	return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
+}
+
+int __secure mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
+				     u32 *arg)
+{
+	return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
+}
+
+int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
+{
+	return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
+}
+
+int __secure mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len)
+{
+	return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/misc.c b/roms/u-boot/arch/arm/mach-socfpga/misc.c
new file mode 100644
index 000000000..64a7c9d65
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/misc.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <asm/cache.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/libfdt.h>
+#include <altera.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/scan_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/nic301.h>
+#include <asm/arch/scu.h>
+#include <asm/pl310.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_addr_t socfpga_clkmgr_base __section(".data");
+phys_addr_t socfpga_rstmgr_base __section(".data");
+phys_addr_t socfpga_sysmgr_base __section(".data");
+
+#ifdef CONFIG_SYS_L2_PL310
+static const struct pl310_regs *const pl310 =
+	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#endif
+
+struct bsel bsel_str[] = {
+	{ "rsvd", "Reserved", },
+	{ "fpga", "FPGA (HPS2FPGA Bridge)", },
+	{ "nand", "NAND Flash (1.8V)", },
+	{ "nand", "NAND Flash (3.0V)", },
+	{ "sd", "SD/MMC External Transceiver (1.8V)", },
+	{ "sd", "SD/MMC Internal Transceiver (3.0V)", },
+	{ "qspi", "QSPI Flash (1.8V)", },
+	{ "qspi", "QSPI Flash (3.0V)", },
+};
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+void enable_caches(void)
+{
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+	icache_enable();
+#endif
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+	dcache_enable();
+#endif
+}
+
+#ifdef CONFIG_SYS_L2_PL310
+void v7_outer_cache_enable(void)
+{
+	struct udevice *dev;
+
+	if (uclass_get_device(UCLASS_CACHE, 0, &dev))
+		pr_err("cache controller driver NOT found!\n");
+}
+
+void v7_outer_cache_disable(void)
+{
+	/* Disable the L2 cache */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void socfpga_pl310_clear(void)
+{
+	u32 mask = 0xff, ena = 0;
+
+	icache_enable();
+
+	/* Disable the L2 cache */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+	writel(0x0, &pl310->pl310_tag_latency_ctrl);
+	writel(0x10, &pl310->pl310_data_latency_ctrl);
+
+	/* enable BRESP, instruction and data prefetch, full line of zeroes */
+	setbits_le32(&pl310->pl310_aux_ctrl,
+		     L310_AUX_CTRL_DATA_PREFETCH_MASK |
+		     L310_AUX_CTRL_INST_PREFETCH_MASK |
+		     L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+	/* Enable the L2 cache */
+	ena = readl(&pl310->pl310_ctrl);
+	ena |= L2X0_CTRL_EN;
+
+	/*
+	 * Invalidate the PL310 L2 cache. Keep the invalidation code
+	 * entirely in L1 I-cache to avoid any bus traffic through
+	 * the L2.
+	 */
+	asm volatile(
+		".align	5			\n"
+		"	b	3f		\n"
+		"1:	str	%1,	[%4]	\n"
+		"	dsb			\n"
+		"	isb			\n"
+		"	str	%0,	[%2]	\n"
+		"	dsb			\n"
+		"	isb			\n"
+		"2:	ldr	%0,	[%2]	\n"
+		"	cmp	%0,	#0	\n"
+		"	bne	2b		\n"
+		"	str	%0,	[%3]	\n"
+		"	dsb			\n"
+		"	isb			\n"
+		"	b	4f		\n"
+		"3:	b	1b		\n"
+		"4:	nop			\n"
+	: "+r"(mask), "+r"(ena)
+	: "r"(&pl310->pl310_inv_way),
+	  "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
+	: "memory", "cc");
+
+	/* Disable the L2 cache */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+#endif
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
+defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FPGA
+/* add device descriptor to FPGA device table */
+void socfpga_fpga_add(void *fpga_desc)
+{
+	fpga_init();
+	fpga_add(fpga_altera, fpga_desc);
+}
+#endif
+
+int arch_cpu_init(void)
+{
+	socfpga_get_managers_addr();
+
+#ifdef CONFIG_HW_WATCHDOG
+	/*
+	 * In case the watchdog is enabled, make sure to (re-)configure it
+	 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
+	 * timeout value is still active which might too short for Linux
+	 * booting.
+	 */
+	hw_watchdog_init();
+#else
+	/*
+	 * If the HW watchdog is NOT enabled, make sure it is not running,
+	 * for example because it was enabled in the preloader. This might
+	 * trigger a watchdog-triggered reboot of Linux kernel later.
+	 * Toggle watchdog reset, so watchdog in not running state.
+	 */
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	unsigned int mask = ~0;
+
+	if (argc < 2 || argc > 3)
+		return CMD_RET_USAGE;
+
+	argv++;
+
+	if (argc == 3)
+		mask = simple_strtoul(argv[1], NULL, 16);
+
+	switch (*argv[0]) {
+	case 'e':	/* Enable */
+		do_bridge_reset(1, mask);
+		break;
+	case 'd':	/* Disable */
+		do_bridge_reset(0, mask);
+		break;
+	default:
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(bridge, 3, 1, do_bridge,
+	   "SoCFPGA HPS FPGA bridge control",
+	   "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	   "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	   ""
+);
+
+#endif
+
+static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
+{
+	const void *blob = gd->fdt_blob;
+	struct fdt_resource r;
+	int node;
+	int ret;
+
+	node = fdt_node_offset_by_compatible(blob, -1, compat);
+	if (node < 0)
+		return node;
+
+	if (!fdtdec_get_is_enabled(blob, node))
+		return -ENODEV;
+
+	ret = fdt_get_resource(blob, node, "reg", 0, &r);
+	if (ret)
+		return ret;
+
+	*base = (phys_addr_t)r.start;
+
+	return 0;
+}
+
+void socfpga_get_managers_addr(void)
+{
+	int ret;
+
+	ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
+	if (ret)
+		hang();
+
+	ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
+	if (ret)
+		hang();
+
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+	ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+				    &socfpga_clkmgr_base);
+#else
+	ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
+#endif
+	if (ret)
+		hang();
+}
+
+phys_addr_t socfpga_get_rstmgr_addr(void)
+{
+	return socfpga_rstmgr_base;
+}
+
+phys_addr_t socfpga_get_sysmgr_addr(void)
+{
+	return socfpga_sysmgr_base;
+}
+
+phys_addr_t socfpga_get_clkmgr_addr(void)
+{
+	return socfpga_clkmgr_base;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/misc_arria10.c b/roms/u-boot/arch/arm/mach-socfpga/misc_arria10.c
new file mode 100644
index 000000000..bf978053c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/misc_arria10.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ */
+
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <ns16550.h>
+#include <watchdog.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/reset_manager_arria10.h>
+#include <asm/arch/sdram_arria10.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/nic301.h>
+#include <asm/io.h>
+#include <asm/pl310.h>
+
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3	0x08
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11	0x58
+#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3	0x68
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7	0x18
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7	0x78
+#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3	0x98
+
+/*
+ * FPGA programming support for SoC FPGA Arria 10
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
+#if defined(CONFIG_SPL_BUILD)
+static struct pl310_regs *const pl310 =
+	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+	(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+void socfpga_init_security_policies(void)
+{
+	/* Put OCRAM in non-secure */
+	writel(0x003f0000, &noc_fw_ocram_base->region0);
+	writel(0x1, &noc_fw_ocram_base->enable);
+
+	/* Put DDR in non-secure */
+	writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc);
+	writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS);
+
+	/* Enable priviledged and non-priviledged access to L4 peripherals */
+	writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST);
+
+	/* Enable secure and non-secure transactions to bridges */
+	writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
+	writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
+
+	writel(0x0007FFFF,
+	       socfpga_get_sysmgr_addr() + SYSMGR_A10_ECC_INTMASK_SET);
+}
+
+void socfpga_sdram_remap_zero(void)
+{
+	/* Configure the L2 controller to make SDRAM start at 0 */
+	writel(0x1, &pl310->pl310_addr_filter_start);
+}
+#endif
+
+int arch_early_init_r(void)
+{
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add(&altera_fpga[0]);
+
+	return 0;
+}
+
+/*
+ * Print CPU information
+ */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
+				   SYSMGR_A10_BOOTINFO);
+	const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
+
+	puts("CPU:   Altera SoCFPGA Arria 10\n");
+
+	printf("BOOT:  %s\n", bsel_str[bsel].name);
+	return 0;
+}
+#endif
+
+void do_bridge_reset(int enable, unsigned int mask)
+{
+	if (enable)
+		socfpga_reset_deassert_bridges_handoff();
+	else
+		socfpga_bridges_reset();
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/misc_gen5.c b/roms/u-boot/arch/arm/mach-socfpga/misc_gen5.c
new file mode 100644
index 000000000..4edf4f9b5
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/misc_gen5.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <env.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/bitops.h>
+#include <linux/libfdt.h>
+#include <altera.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/nic301.h>
+#include <asm/arch/scu.h>
+#include <asm/pl310.h>
+
+#include <dt-bindings/reset/altr,rst-mgr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pl310_regs *const pl310 =
+	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static struct nic301_registers *nic301_regs =
+	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+static struct scu_registers *scu_regs =
+	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
+static const struct {
+	const u16	pn;
+	const char	*name;
+	const char	*var;
+} socfpga_fpga_model[] = {
+	/* Cyclone V E */
+	{ 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
+	{ 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
+	{ 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
+	{ 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
+	{ 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
+	/* Cyclone V GX/GT */
+	{ 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
+	{ 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
+	{ 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
+	{ 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
+	{ 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
+	/* Cyclone V SE/SX/ST */
+	{ 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
+	{ 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
+	{ 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
+	{ 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
+	/* Arria V */
+	{ 0x2d03, "Arria V, D5", "av_d5" },
+	/* Arria V ST/SX */
+	{ 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" },
+};
+
+static int socfpga_fpga_id(const bool print_id)
+{
+	const u32 altera_mi = 0x6e;
+	const u32 id = scan_mgr_get_fpga_id();
+
+	const u32 lsb = id & 0x00000001;
+	const u32 mi = (id >> 1) & 0x000007ff;
+	const u32 pn = (id >> 12) & 0x0000ffff;
+	const u32 version = (id >> 28) & 0x0000000f;
+	int i;
+
+	if ((mi != altera_mi) || (lsb != 1)) {
+		printf("FPGA:  Not Altera chip ID\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
+		if (pn == socfpga_fpga_model[i].pn)
+			break;
+
+	if (i == ARRAY_SIZE(socfpga_fpga_model)) {
+		printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
+		return -EINVAL;
+	}
+
+	if (print_id)
+		printf("FPGA:  Altera %s, version 0x%01x\n",
+		       socfpga_fpga_model[i].name, version);
+	return i;
+}
+
+/*
+ * Print CPU information
+ */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
+				   SYSMGR_GEN5_BOOTINFO);
+	const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
+
+	puts("CPU:   Altera SoCFPGA Platform\n");
+	socfpga_fpga_id(1);
+
+	printf("BOOT:  %s\n", bsel_str[bsel].name);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	const u32 bsel = readl(socfpga_get_sysmgr_addr() +
+			       SYSMGR_GEN5_BOOTINFO) & 0x7;
+	const int fpga_id = socfpga_fpga_id(0);
+	env_set("bootmode", bsel_str[bsel].mode);
+	if (fpga_id >= 0)
+		env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
+	return 0;
+}
+#endif
+
+/*
+ * Convert all NIC-301 AMBA slaves from secure to non-secure
+ */
+static void socfpga_nic301_slave_ns(void)
+{
+	writel(0x1, &nic301_regs->lwhps2fpgaregs);
+	writel(0x1, &nic301_regs->hps2fpgaregs);
+	writel(0x1, &nic301_regs->acp);
+	writel(0x1, &nic301_regs->rom);
+	writel(0x1, &nic301_regs->ocram);
+	writel(0x1, &nic301_regs->sdrdata);
+}
+
+void socfpga_sdram_remap_zero(void)
+{
+	u32 remap;
+
+	socfpga_nic301_slave_ns();
+
+	/*
+	 * Private components security:
+	 * U-Boot : configure private timer, global timer and cpu component
+	 * access as non secure for kernel stage (as required by Linux)
+	 */
+	setbits_le32(&scu_regs->sacr, 0xfff);
+
+	/* Configure the L2 controller to make SDRAM start at 0 */
+	remap = 0x1; /* remap.mpuzero */
+	/* Keep fpga bridge enabled when running from FPGA onchip RAM */
+	if (socfpga_is_booting_from_fpga())
+		remap |= 0x8; /* remap.hps2fpga */
+	writel(remap, &nic301_regs->remap);
+
+	writel(0x1, &pl310->pl310_addr_filter_start);
+}
+
+static u32 iswgrp_handoff[8];
+
+int arch_early_init_r(void)
+{
+	int i;
+
+	/*
+	 * Write magic value into magic register to unlock support for
+	 * issuing warm reset. The ancient kernel code expects this
+	 * value to be written into the register by the bootloader, so
+	 * to support that old code, we write it here instead of in the
+	 * reset_cpu() function just before resetting the CPU.
+	 */
+	writel(0xae9efebc,
+	       socfpga_get_sysmgr_addr() + SYSMGR_GEN5_WARMRAMGRP_EN);
+
+	for (i = 0; i < 8; i++)	/* Cache initial SW setting regs */
+		iswgrp_handoff[i] = readl(socfpga_get_sysmgr_addr() +
+					  SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
+
+	socfpga_bridges_reset(1);
+
+	socfpga_sdram_remap_zero();
+
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add(&altera_fpga[0]);
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+
+void do_bridge_reset(int enable, unsigned int mask)
+{
+	int i;
+
+	if (enable) {
+		socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
+						 !(mask & BIT(1)),
+						 !(mask & BIT(2)));
+		for (i = 0; i < 2; i++) {	/* Reload SW setting cache */
+			iswgrp_handoff[i] =
+				readl(socfpga_get_sysmgr_addr() +
+				      SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
+		}
+
+		writel(iswgrp_handoff[2],
+		       socfpga_get_sysmgr_addr() +
+		       SYSMGR_GEN5_FPGAINFGRP_MODULE);
+		writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+		writel(iswgrp_handoff[0],
+		       socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
+		writel(iswgrp_handoff[1], &nic301_regs->remap);
+
+		writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
+		writel(iswgrp_handoff[0],
+		       socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
+	} else {
+		writel(0, socfpga_get_sysmgr_addr() +
+		       SYSMGR_GEN5_FPGAINFGRP_MODULE);
+		writel(0, &sdr_ctrl->fpgaport_rst);
+		writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
+		writel(1, &nic301_regs->remap);
+	}
+}
+#endif
diff --git a/roms/u-boot/arch/arm/mach-socfpga/misc_s10.c b/roms/u-boot/arch/arm/mach-socfpga/misc_s10.c
new file mode 100644
index 000000000..50c7f19ae
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/misc_s10.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <altera.h>
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * FPGA programming support for SoC FPGA Stratix 10
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Intel_FPGA_SDM_Mailbox,
+		/* Interface type */
+		secure_device_manager_mailbox,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
+
+/*
+ * Print CPU information
+ */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	char qspi_string[13];
+
+	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
+	env_set("qspi_clock", qspi_string);
+
+	return 0;
+}
+#endif
+
+int arch_early_init_r(void)
+{
+	socfpga_fpga_add(&altera_fpga[0]);
+
+	return 0;
+}
+
+/* Return 1 if FPGA is ready otherwise return 0 */
+int is_fpga_config_ready(void)
+{
+	return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
+		SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
+}
+
+void do_bridge_reset(int enable, unsigned int mask)
+{
+	/* Check FPGA status before bridge enable */
+	if (!is_fpga_config_ready()) {
+		puts("FPGA not ready. Bridge reset aborted!\n");
+		return;
+	}
+
+	socfpga_bridges_reset(enable);
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/mmu-arm64_s10.c b/roms/u-boot/arch/arm/mach-socfpga/mmu-arm64_s10.c
new file mode 100644
index 000000000..a55b7b7cf
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region socfpga_stratix10_mem_map[] = {
+	{
+		/* MEM 2GB*/
+		.virt	= 0x0UL,
+		.phys	= 0x0UL,
+		.size	= 0x80000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* FPGA 1.5GB */
+		.virt	= 0x80000000UL,
+		.phys	= 0x80000000UL,
+		.size	= 0x60000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* DEVICE 142MB */
+		.virt	= 0xF7000000UL,
+		.phys	= 0xF7000000UL,
+		.size	= 0x08E00000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* OCRAM 1MB but available 256KB */
+		.virt	= 0xFFE00000UL,
+		.phys	= 0xFFE00000UL,
+		.size	= 0x00100000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* DEVICE 32KB */
+		.virt	= 0xFFFC0000UL,
+		.phys	= 0xFFFC0000UL,
+		.size	= 0x00008000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* MEM 124GB */
+		.virt	= 0x0100000000UL,
+		.phys	= 0x0100000000UL,
+		.size	= 0x1F00000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* DEVICE 4GB */
+		.virt	= 0x2000000000UL,
+		.phys	= 0x2000000000UL,
+		.size	= 0x0100000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* List terminator */
+	},
+};
+
+struct mm_region *mem_map = socfpga_stratix10_mem_map;
diff --git a/roms/u-boot/arch/arm/mach-socfpga/pinmux_arria10.c b/roms/u-boot/arch/arm/mach-socfpga/pinmux_arria10.c
new file mode 100644
index 000000000..f378fce7f
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/pinmux_arria10.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ */
+
+#include <log.h>
+#include <asm/arch/pinmux.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fdtdec.h>
+
+static int do_pinctr_pin(const void *blob, int child, const char *node_name)
+{
+	int len;
+	fdt_addr_t base_addr;
+	fdt_size_t size;
+	const u32 *cell;
+	u32 offset, value;
+
+	base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
+	if (base_addr != FDT_ADDR_T_NONE) {
+		cell = fdt_getprop(blob, child, "pinctrl-single,pins", &len);
+		if (!cell || len <= 0)
+			return -EFAULT;
+
+		debug("%p %d\n", cell, len);
+		for (; len > 0; len -= (2 * sizeof(u32))) {
+			offset = fdt32_to_cpu(*cell++);
+			value = fdt32_to_cpu(*cell++);
+			debug("<0x%x 0x%x>\n", offset, value);
+			writel(value, base_addr + offset);
+		}
+		return 0;
+	}
+	return -EFAULT;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+	int child, len;
+	const char *node_name;
+
+	child = fdt_first_subnode(blob, node);
+
+	if (child < 0)
+		return -EINVAL;
+
+	node_name = fdt_get_name(blob, child, &len);
+
+	while (node_name) {
+		if (!strcmp(child_name, node_name))
+			return do_pinctr_pin(blob, child, node_name);
+
+		child = fdt_next_subnode(blob, child);
+
+		if (child < 0)
+			break;
+
+		node_name = fdt_get_name(blob, child, &len);
+	}
+
+	return -EFAULT;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0,
+			COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+	if (node < 0)
+		return -EINVAL;
+
+	if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+		return -EFAULT;
+
+	if (do_pinctrl_pins(blob, node, "dedicated"))
+		return -EFAULT;
+
+	return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0,
+			COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+	if (node < 0)
+		return -EINVAL;
+
+	if (do_pinctrl_pins(blob, node, pin_grp))
+		return -EFAULT;
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/qts-filter-a10.sh b/roms/u-boot/arch/arm/mach-socfpga/qts-filter-a10.sh
new file mode 100755
index 000000000..57d77e8e1
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/qts-filter-a10.sh
@@ -0,0 +1,141 @@
+#!/bin/bash
+
+#
+# helper function to convert from DOS to Unix, if necessary, and handle
+# lines ending in '\'.
+#
+fix_newlines_in_macros() {
+	sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
+}
+
+#filter out only what we need from a10 hps.xml
+grep_a10_hps_config() {
+	egrep "clk_hz|i_clk_mgr|i_io48_pin_mux|AXI_SLAVE|AXI_MASTER"
+}
+
+#
+# Process hps.xml
+# $1:	hps.xml
+# $2:	Output File
+#
+process_a10_hps_config() {
+	hps_xml="$1"
+	outfile="$2"
+
+	(cat << EOF
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Intel Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+EOF
+
+	echo "/* Clocks */"
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "clk_hz" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/\.[0-9]//' |
+			sed 's/I_CLK_MGR_//' |
+			sort
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "i_clk_mgr_mainpll" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/\.[0-9]//' |
+			sed 's/I_CLK_MGR_//' |
+			sort
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "i_clk_mgr_perpll" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/\.[0-9]//' |
+			sed 's/I_CLK_MGR_//' |
+			sort
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "i_clk_mgr_clkmgr" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/\.[0-9]//' |
+			sed 's/I_CLK_MGR_//' |
+			sort
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "i_clk_mgr_alteragrp" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/\.[0-9]//' |
+			sed 's/I_CLK_MGR_//' |
+			sort
+	echo "#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \\"
+	echo "	(ALTERAGRP_MPUCLK_MAINCNT))"
+	echo "#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \\"
+	echo "	(ALTERAGRP_NOCCLK_MAINCNT))"
+
+	echo
+	echo "/* Pin Mux Configuration */"
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "i_io48_pin_mux" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/I_IO48_PIN_MUX_//' |
+			sed 's/SHARED_3V_IO_GRP_//' |
+			sed 's/FPGA_INTERFACE_GRP_//' |
+			sed 's/DEDICATED_IO_GRP_//' |
+			sed 's/CONFIGURATION_DEDICATED/CONFIG/' |
+			sort
+
+	echo
+	echo "/* Bridge Configuration */"
+	fix_newlines_in_macros \
+		${hps_xml} | egrep "AXI_SLAVE|AXI_MASTER" |
+			awk -F"'" '{ gsub("\\.","_",$2) ; \
+				print "#define" " " toupper($2) " " $4}' |
+			sed 's/true/1/' |
+			sed 's/false/0/' |
+			sort
+
+	echo
+	echo "/* Voltage Select for Config IO */"
+	echo "#define CONFIG_IO_BANK_VSEL \\"
+	echo "	(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\"
+	echo "	(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
+
+	echo
+	echo "/* Macro for Config IO bit mapping */"
+	echo -n "#define CONFIG_IO_MACRO(NAME) "
+	echo "(((NAME ## _RTRIM & 0xff) << 19) | \\"
+	echo "	((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\"
+	echo "	((NAME ## _WK_PU_EN & 0x1) << 16) | \\"
+	echo "	((NAME ## _PU_SLW_RT & 0x1) << 13) | \\"
+	echo "	((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\"
+	echo "	((NAME ## _PD_SLW_RT & 0x1) << 5) | \\"
+	echo "	(NAME ## _PD_DRV_STRG & 0x1f))"
+
+	cat << EOF
+
+#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
+EOF
+	) > "${outfile}"
+}
+
+usage() {
+	echo "$0 [hps_xml] [output_file]"
+	echo "Process QTS-generated hps.xml into devicetree header."
+	echo ""
+	echo "  hps_xml      - hps.xml file from hps_isw_handoff"
+	echo "  output_file  - Output header file for dtsi include"
+	echo ""
+}
+
+hps_xml="$1"
+outfile="$2"
+
+if [ "$#" -ne 2 ] ; then
+	usage
+	exit 1
+fi
+
+process_a10_hps_config "${hps_xml}" "${outfile}"
diff --git a/roms/u-boot/arch/arm/mach-socfpga/qts-filter.sh b/roms/u-boot/arch/arm/mach-socfpga/qts-filter.sh
new file mode 100755
index 000000000..a49cd1b68
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/qts-filter.sh
@@ -0,0 +1,233 @@
+#!/bin/sh
+
+#
+# helper function to convert from DOS to Unix, if necessary, and handle
+# lines ending in '\'.
+#
+fix_newlines_in_macros() {
+	sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
+}
+
+#
+# Process iocsr_config_*.[ch]
+# $1:	SoC type
+# $2:	Input handoff directory
+# $3:	Input BSP Generated directory
+# $4:	Output directory
+#
+process_iocsr_config() {
+	soc="$1"
+	in_qts_dir="$2"
+	in_bsp_dir="$3"
+	out_dir="$4"
+
+	(
+	cat << EOF
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+EOF
+
+	# Retrieve the scan chain lengths
+	fix_newlines_in_macros \
+		${in_bsp_dir}/generated/iocsr_config_${soc}.h |
+	grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH'	| tr -d "()"
+
+	echo ""
+
+	# Retrieve the scan chain config and zap the ad-hoc length encoding
+	fix_newlines_in_macros \
+		${in_bsp_dir}/generated/iocsr_config_${soc}.c |
+	sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'
+
+	cat << EOF
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
+EOF
+	) > "${out_dir}/iocsr_config.h"
+}
+
+#
+# Process pinmux_config_*.c (and ignore pinmux_config.h)
+# $1:	SoC type
+# $2:	Input directory
+# $3:	Output directory
+#
+process_pinmux_config() {
+	soc="$1"
+	in_qts_dir="$2"
+	in_bsp_dir="$3"
+	out_dir="$4"
+
+	(
+	cat << EOF
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+EOF
+
+	# Retrieve the pinmux config and zap the ad-hoc length encoding
+	fix_newlines_in_macros \
+		${in_bsp_dir}/generated/pinmux_config_${soc}.c |
+	sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}'
+
+	cat << EOF
+
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
+EOF
+	) > "${out_dir}/pinmux_config.h"
+}
+
+#
+# Process pll_config.h
+# $1:	SoC type (not used)
+# $2:	Input directory
+# $3:	Output directory
+#
+process_pll_config() {
+	soc="$1"
+	in_qts_dir="$2"
+	in_bsp_dir="$3"
+	out_dir="$4"
+
+	(
+	cat << EOF
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+EOF
+
+	# Retrieve the pll config and zap parenthesis
+	fix_newlines_in_macros \
+		${in_bsp_dir}/generated/pll_config.h |
+	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
+
+	cat << EOF
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
+EOF
+	) > "${out_dir}/pll_config.h"
+}
+
+#
+# Filter out only the macros which are actually used by the code
+#
+grep_sdram_config() {
+	egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
+}
+
+#
+# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h
+# $1:	SoC type (not used)
+# $2:	Input directory
+# $3:	Output directory
+#
+process_sdram_config() {
+	soc="$1"
+	in_qts_dir="$2"
+	in_bsp_dir="$3"
+	out_dir="$4"
+
+	(
+	cat << EOF
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+EOF
+
+	echo "/* SDRAM configuration */"
+	# Retrieve the sdram config, zap broken lines and zap parenthesis
+	fix_newlines_in_macros \
+		${in_bsp_dir}/generated/sdram/sdram_config.h |
+	sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
+	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
+		sort -u | grep_sdram_config
+
+	echo ""
+	echo "/* Sequencer auto configuration */"
+	fix_newlines_in_macros \
+		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
+	sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
+		sort -u | grep_sdram_config
+
+	echo ""
+	echo "/* Sequencer defines configuration */"
+	fix_newlines_in_macros \
+		${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
+	sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
+		sort -u | grep_sdram_config
+
+	echo ""
+	echo "/* Sequencer ac_rom_init configuration */"
+	fix_newlines_in_macros \
+		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c |
+	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
+
+	echo ""
+	echo "/* Sequencer inst_rom_init configuration */"
+	fix_newlines_in_macros \
+		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c |
+	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
+
+	cat << EOF
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
+EOF
+	) > "${out_dir}/sdram_config.h"
+}
+
+usage() {
+	echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
+	echo "Process QTS-generated headers into U-Boot compatible ones."
+	echo ""
+	echo "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."
+	echo "  input_qts_dir - Directory with compiled Quartus project"
+	echo "                  and containing the Quartus project file (QPF)."
+	echo "  input_bsp_dir - Directory with generated bsp containing"
+	echo "                  the settings.bsp file."
+	echo "  output_dir    - Directory to store the U-Boot compatible"
+	echo "                  headers."
+	echo ""
+}
+
+soc="$1"
+in_qts_dir="$2"
+in_bsp_dir="$3"
+out_dir="$4"
+
+if [ "$#" -ne 4 ] ; then
+	usage
+	exit 1
+fi
+
+if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
+	! -d "${out_dir}" -o -z "${soc}" ] ; then
+	usage
+	exit 3
+fi
+
+process_iocsr_config  "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
+process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
+process_pll_config    "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
+process_sdram_config  "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
diff --git a/roms/u-boot/arch/arm/mach-socfpga/reset_manager_arria10.c b/roms/u-boot/arch/arm/mach-socfpga/reset_manager_arria10.c
new file mode 100644
index 000000000..27c030801
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ */
+
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct bridge_cfg {
+	int compat_id;
+	u32  mask_noc;
+	u32  mask_rstmgr;
+};
+
+static const struct bridge_cfg bridge_cfg_tbl[] = {
+	{
+		COMPAT_ALTERA_SOCFPGA_H2F_BRG,
+		ALT_SYSMGR_NOC_H2F_SET_MSK,
+		ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
+	},
+	{
+		COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
+		ALT_SYSMGR_NOC_LWH2F_SET_MSK,
+		ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
+	},
+	{
+		COMPAT_ALTERA_SOCFPGA_F2H_BRG,
+		ALT_SYSMGR_NOC_F2H_SET_MSK,
+		ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
+	},
+	{
+		COMPAT_ALTERA_SOCFPGA_F2SDR0,
+		ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
+		ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
+	},
+	{
+		COMPAT_ALTERA_SOCFPGA_F2SDR1,
+		ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
+		ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
+	},
+	{
+		COMPAT_ALTERA_SOCFPGA_F2SDR2,
+		ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+		ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
+	},
+};
+
+/* Disable the watchdog (toggle reset to watchdog) */
+void socfpga_watchdog_disable(void)
+{
+	/* assert reset for watchdog */
+	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
+		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
+}
+
+/* Release NOC ddr scheduler from reset */
+void socfpga_reset_deassert_noc_ddr_scheduler(void)
+{
+	clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
+		     ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
+}
+
+static int get_bridge_init_val(const void *blob, int compat_id)
+{
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, compat_id);
+	if (node < 0)
+		return 0;
+
+	return fdtdec_get_uint(blob, node, "init-val", 0);
+}
+
+/* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
+int socfpga_reset_deassert_bridges_handoff(void)
+{
+	u32 mask_noc = 0, mask_rstmgr = 0;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
+		if (get_bridge_init_val(gd->fdt_blob,
+					bridge_cfg_tbl[i].compat_id)) {
+			mask_noc |= bridge_cfg_tbl[i].mask_noc;
+			mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
+		}
+	}
+
+	/* clear idle request to all bridges */
+	setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_CLR,
+		     mask_noc);
+
+	/* Release bridges from reset state per handoff value */
+	clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
+		     mask_rstmgr);
+
+	/* Poll until all idleack to 0, timeout at 1000ms */
+	return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
+				 SYSMGR_A10_NOC_IDLEACK),
+				 mask_noc, false, 1000, false);
+}
+
+/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
+void socfpga_reset_deassert_osc1wd0(void)
+{
+	clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
+		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
+}
+
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
+void socfpga_per_reset(u32 reset, int set)
+{
+	unsigned long reg;
+	u32 rstmgr_bank = RSTMGR_BANK(reset);
+
+	switch (rstmgr_bank) {
+	case 0:
+		reg = RSTMGR_A10_MPUMODRST;
+		break;
+	case 1:
+		reg = RSTMGR_A10_PER0MODRST;
+		break;
+	case 2:
+		reg = RSTMGR_A10_PER1MODRST;
+		break;
+	case 3:
+		reg = RSTMGR_A10_BRGMODRST;
+		break;
+	case 4:
+		reg = RSTMGR_A10_SYSMODRST;
+		break;
+
+	default:
+		return;
+	}
+
+	if (set)
+		setbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
+	else
+		clrbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
+}
+
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
+ */
+void socfpga_per_reset_all(void)
+{
+	const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
+			  (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
+	unsigned mask_ecc_ocp =
+		ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
+
+	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
+	writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST);
+	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
+		     ~mask_ecc_ocp);
+
+	/* Finally disable the ECC_OCP */
+	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
+		     mask_ecc_ocp);
+}
+
+int socfpga_bridges_reset(void)
+{
+	int ret;
+
+	/* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
+	   fpga2sdram) */
+	/* set idle request to all bridges */
+	writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
+		ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+		ALT_SYSMGR_NOC_F2H_SET_MSK |
+		ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+		ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+		ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+		socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_SET);
+
+	/* Enable the NOC timeout */
+	writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
+	       socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
+
+	/* Poll until all idleack to 1 */
+	ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
+				SYSMGR_A10_NOC_IDLEACK),
+				ALT_SYSMGR_NOC_H2F_SET_MSK |
+				ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+				ALT_SYSMGR_NOC_F2H_SET_MSK |
+				ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+				ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+				ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+				true, 10000, false);
+	if (ret)
+		return ret;
+
+	/* Poll until all idlestatus to 1 */
+	ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
+				SYSMGR_A10_NOC_IDLESTATUS),
+				ALT_SYSMGR_NOC_H2F_SET_MSK |
+				ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+				ALT_SYSMGR_NOC_F2H_SET_MSK |
+				ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+				ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+				ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+				true, 10000, false);
+	if (ret)
+		return ret;
+
+	/* Put all bridges (except NOR DDR scheduler) into reset state */
+	setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
+		     (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
+		      ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
+
+	/* Disable NOC timeout */
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/reset_manager_gen5.c b/roms/u-boot/arch/arm/mach-socfpga/reset_manager_gen5.c
new file mode 100644
index 000000000..a65860ef0
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <linux/bitops.h>
+
+/* Assert or de-assert SoCFPGA reset manager reset. */
+void socfpga_per_reset(u32 reset, int set)
+{
+	unsigned long reg;
+	u32 rstmgr_bank = RSTMGR_BANK(reset);
+
+	switch (rstmgr_bank) {
+	case 0:
+		reg = RSTMGR_GEN5_MPUMODRST;
+		break;
+	case 1:
+		reg = RSTMGR_GEN5_PERMODRST;
+		break;
+	case 2:
+		reg = RSTMGR_GEN5_PER2MODRST;
+		break;
+	case 3:
+		reg = RSTMGR_GEN5_BRGMODRST;
+		break;
+	case 4:
+		reg = RSTMGR_GEN5_MISCMODRST;
+		break;
+
+	default:
+		return;
+	}
+
+	if (set)
+		setbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
+	else
+		clrbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
+}
+
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+	writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_PERMODRST);
+	writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_PER2MODRST);
+}
+
+#define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
+#define L3REGS_REMAP_HPS2FPGA_MASK	0x08
+#define L3REGS_REMAP_OCRAM_MASK		0x01
+
+void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
+{
+	u32 brgmask = 0x0;
+	u32 l3rmask = L3REGS_REMAP_OCRAM_MASK;
+
+	if (h2f)
+		brgmask |= BIT(0);
+	else
+		l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK;
+
+	if (lwh2f)
+		brgmask |= BIT(1);
+	else
+		l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK;
+
+	if (f2h)
+		brgmask |= BIT(2);
+
+	writel(brgmask,
+	       socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(0));
+	writel(l3rmask,
+	       socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(1));
+}
+
+void socfpga_bridges_reset(int enable)
+{
+	const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
+				L3REGS_REMAP_HPS2FPGA_MASK |
+				L3REGS_REMAP_OCRAM_MASK;
+
+	if (enable) {
+		/* brdmodrst */
+		writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
+		writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
+	} else {
+		socfpga_bridges_set_handoff_regs(false, false, false);
+
+		/* Check signal from FPGA. */
+		if (!fpgamgr_test_fpga_ready()) {
+			/* FPGA not ready, do nothing. We allow system to boot
+			 * without FPGA ready. So, return 0 instead of error. */
+			printf("%s: FPGA not ready, aborting.\n", __func__);
+			return;
+		}
+
+		/* brdmodrst */
+		writel(0, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
+
+		/* Remap the bridges into memory map */
+		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
+	}
+	return;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/reset_manager_s10.c b/roms/u-boot/arch/arm/mach-socfpga/reset_manager_s10.c
new file mode 100644
index 000000000..d2337bd4d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/smc_api.h>
+#include <asm/arch/system_manager.h>
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <linux/iopoll.h>
+#include <linux/intel-smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Assert or de-assert SoCFPGA reset manager reset. */
+void socfpga_per_reset(u32 reset, int set)
+{
+	unsigned long reg;
+
+	if (RSTMGR_BANK(reset) == 0)
+		reg = RSTMGR_SOC64_MPUMODRST;
+	else if (RSTMGR_BANK(reset) == 1)
+		reg = RSTMGR_SOC64_PER0MODRST;
+	else if (RSTMGR_BANK(reset) == 2)
+		reg = RSTMGR_SOC64_PER1MODRST;
+	else if (RSTMGR_BANK(reset) == 3)
+		reg = RSTMGR_SOC64_BRGMODRST;
+	else	/* Invalid reset register, do nothing */
+		return;
+
+	if (set)
+		setbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
+	else
+		clrbits_le32(socfpga_get_rstmgr_addr() + reg,
+			     1 << RSTMGR_RESET(reset));
+}
+
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+	/* disable all except OCP and l4wd0. OCP disable later */
+	writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
+		      socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
+	writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
+	writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
+}
+
+void socfpga_bridges_reset(int enable)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	u64 arg = enable;
+
+	int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
+	if (ret) {
+		printf("SMC call failed with error %d in %s.\n", ret, __func__);
+		return;
+	}
+#else
+	u32 reg;
+
+	if (enable) {
+		/* clear idle request to all bridges */
+		setbits_le32(socfpga_get_sysmgr_addr() +
+			     SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
+
+		/* Release all bridges from reset state */
+		clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
+			     ~0);
+
+		/* Poll until all idleack to 0 */
+		read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
+				  SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
+				  300000);
+	} else {
+		/* set idle request to all bridges */
+		writel(~0,
+		       socfpga_get_sysmgr_addr() +
+		       SYSMGR_SOC64_NOC_IDLEREQ_SET);
+
+		/* Enable the NOC timeout */
+		writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
+
+		/* Poll until all idleack to 1 */
+		read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
+				  SYSMGR_SOC64_NOC_IDLEACK, reg,
+				  reg == (SYSMGR_NOC_H2F_MSK |
+					  SYSMGR_NOC_LWH2F_MSK),
+				  1000, 300000);
+
+		/* Poll until all idlestatus to 1 */
+		read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
+				  SYSMGR_SOC64_NOC_IDLESTATUS, reg,
+				  reg == (SYSMGR_NOC_H2F_MSK |
+					  SYSMGR_NOC_LWH2F_MSK),
+				  1000, 300000);
+
+		/* Reset all bridges (except NOR DDR scheduler & F2S) */
+		setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
+			     ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
+			       RSTMGR_BRGMODRST_FPGA2SOC_MASK));
+
+		/* Disable NOC timeout */
+		writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
+	}
+#endif
+}
+
+/*
+ * Return non-zero if the CPU has been warm reset
+ */
+int cpu_has_been_warmreset(void)
+{
+	return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
+			RSTMGR_L4WD_MPU_WARMRESET_MASK;
+}
+
+void print_reset_info(void)
+{
+	bool iswd;
+	int n;
+	u32 stat = cpu_has_been_warmreset();
+
+	printf("Reset state: %s%s", stat ? "Warm " : "Cold",
+	       (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : "");
+
+	stat &= ~RSTMGR_STAT_SDMWARMRST;
+	if (!stat) {
+		puts("\n");
+		return;
+	}
+
+	n = generic_ffs(stat) - 1;
+	iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);
+	printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU",
+	       iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :
+	       (n - RSTMGR_STAT_MPU0RST_BITPOS));
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/scan_manager.c b/roms/u-boot/arch/arm/mach-socfpga/scan_manager.c
new file mode 100644
index 000000000..36d688014
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/scan_manager.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/scan_manager.h>
+#include <asm/arch/system_manager.h>
+#include <linux/delay.h>
+
+/*
+ * Maximum polling loop to wait for IO scan chain engine becomes idle
+ * to prevent infinite loop. It is important that this is NOT changed
+ * to delay using timer functions, since at the time this function is
+ * called, timer might not yet be inited.
+ */
+#define SCANMGR_MAX_DELAY		100
+
+/*
+ * Maximum length of TDI_TDO packet payload is 128 bits,
+ * represented by (length - 1) in TDI_TDO header.
+ */
+#define TDI_TDO_MAX_PAYLOAD		127
+
+#define SCANMGR_STAT_ACTIVE		(1 << 31)
+#define SCANMGR_STAT_WFIFOCNT_MASK	0x70000000
+
+static const struct socfpga_scan_manager *scan_manager_base =
+		(void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+		(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/**
+ * scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
+ * @max_iter:	Maximum number of iterations to wait for idle
+ *
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static u32 scan_chain_engine_is_idle(u32 max_iter)
+{
+	const u32 mask = SCANMGR_STAT_ACTIVE | SCANMGR_STAT_WFIFOCNT_MASK;
+	u32 status;
+
+	/* Poll the engine until the scan engine is inactive. */
+	do {
+		status = readl(&scan_manager_base->stat);
+		if (!(status & mask))
+			return 0;
+	} while (max_iter--);
+
+	return -ETIMEDOUT;
+}
+
+#define JTAG_BP_INSN		(1 << 0)
+#define JTAG_BP_TMS		(1 << 1)
+#define JTAG_BP_PAYLOAD		(1 << 2)
+#define JTAG_BP_2BYTE		(1 << 3)
+#define JTAG_BP_4BYTE		(1 << 4)
+
+/**
+ * scan_mgr_jtag_io() - Access the JTAG chain
+ * @flags:	Control flags, used to configure the action on the JTAG
+ * @iarg:	Instruction argument
+ * @parg:	Payload argument or data
+ *
+ * Perform I/O on the JTAG chain
+ */
+static void scan_mgr_jtag_io(const u32 flags, const u8 iarg, const u32 parg)
+{
+	u32 data = parg;
+
+	if (flags & JTAG_BP_INSN) {	/* JTAG instruction */
+		/*
+		 * The SCC JTAG register is LSB first, so make
+		 * space for the instruction at the LSB.
+		 */
+		data <<= 8;
+		if (flags & JTAG_BP_TMS) {
+			data |= (0 << 7);	/* TMS instruction. */
+			data |= iarg & 0x3f;	/* TMS arg is 6 bits. */
+			if (flags & JTAG_BP_PAYLOAD)
+				data |= (1 << 6);
+		} else {
+			data |= (1 << 7);	/* TDI/TDO instruction. */
+			data |= iarg & 0xf;	/* TDI/TDO arg is 4 bits. */
+			if (flags & JTAG_BP_PAYLOAD)
+				data |= (1 << 4);
+		}
+	}
+
+	if (flags & JTAG_BP_4BYTE)
+		writel(data, &scan_manager_base->fifo_quad_byte);
+	else if (flags & JTAG_BP_2BYTE)
+		writel(data & 0xffff, &scan_manager_base->fifo_double_byte);
+	else
+		writel(data & 0xff, &scan_manager_base->fifo_single_byte);
+}
+
+/**
+ * scan_mgr_jtag_insn_data() - Send JTAG instruction and data
+ * @iarg:	Instruction argument
+ * @data:	Associated data
+ * @dlen:	Length of data in bits
+ *
+ * This function is used when programming the IO chains to submit the
+ * instruction followed by variable length payload.
+ */
+static int
+scan_mgr_jtag_insn_data(const u8 iarg, const unsigned long *data,
+			const unsigned int dlen)
+{
+	int i, j;
+
+	scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_2BYTE, iarg, dlen - 1);
+
+	/* 32 bits or more remain */
+	for (i = 0; i < dlen / 32; i++)
+		scan_mgr_jtag_io(JTAG_BP_4BYTE, 0x0, data[i]);
+
+	if ((dlen % 32) > 24) {	/* 31...24 bits remain */
+		scan_mgr_jtag_io(JTAG_BP_4BYTE, 0x0, data[i]);
+	} else if (dlen % 32) {	/* 24...1 bit remain */
+		for (j = 0; j < dlen % 32; j += 8)
+			scan_mgr_jtag_io(0, 0x0, data[i] >> j);
+	}
+
+	return scan_chain_engine_is_idle(SCANMGR_MAX_DELAY);
+}
+
+/**
+ * scan_mgr_io_scan_chain_prg() - Program HPS IO Scan Chain
+ * @io_scan_chain_id:		IO scan chain ID
+ */
+static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id)
+{
+	u32 io_scan_chain_len_in_bits;
+	const unsigned long *iocsr_scan_chain;
+	unsigned int rem, idx = 0;
+	int ret;
+
+	ret = iocsr_get_config_table(io_scan_chain_id, &iocsr_scan_chain,
+				     &io_scan_chain_len_in_bits);
+	if (ret)
+		return 1;
+
+	/*
+	 * De-assert reinit if the IO scan chain is intended for HIO. In
+	 * this, its the chain 3.
+	 */
+	if (io_scan_chain_id == 3)
+		clrbits_le32(&freeze_controller_base->hioctrl,
+			     SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+	/*
+	 * Check if the scan chain engine is inactive and the
+	 * WFIFO is empty before enabling the IO scan chain
+	 */
+	ret = scan_chain_engine_is_idle(SCANMGR_MAX_DELAY);
+	if (ret)
+		return ret;
+
+	/*
+	 * Enable IO Scan chain based on scan chain id
+	 * Note: only one chain can be enabled at a time
+	 */
+	setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+	/* Program IO scan chain. */
+	while (io_scan_chain_len_in_bits) {
+		if (io_scan_chain_len_in_bits > 128)
+			rem = 128;
+		else
+			rem = io_scan_chain_len_in_bits;
+
+		ret = scan_mgr_jtag_insn_data(0x0, &iocsr_scan_chain[idx], rem);
+		if (ret)
+			goto error;
+		io_scan_chain_len_in_bits -= rem;
+		idx += 4;
+	}
+
+	/* Disable IO Scan chain when configuration done*/
+	clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+	return 0;
+
+error:
+	/* Disable IO Scan chain when error detected */
+	clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+	return ret;
+}
+
+int scan_mgr_configure_iocsr(void)
+{
+	int status = 0;
+
+	/* configure the IOCSR through scan chain */
+	status |= scan_mgr_io_scan_chain_prg(0);
+	status |= scan_mgr_io_scan_chain_prg(1);
+	status |= scan_mgr_io_scan_chain_prg(2);
+	status |= scan_mgr_io_scan_chain_prg(3);
+	return status;
+}
+
+/**
+ * scan_mgr_get_fpga_id() - Obtain FPGA JTAG ID
+ *
+ * This function obtains JTAG ID from the FPGA TAP controller.
+ */
+u32 scan_mgr_get_fpga_id(void)
+{
+	const unsigned long data = 0;
+	u32 id = 0xffffffff;
+	int ret;
+
+	/* Enable HPS to talk to JTAG in the FPGA through the System Manager */
+	writel(0x1, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SCANMGRGRP_CTRL);
+
+	/* Enable port 7 */
+	writel(0x80, &scan_manager_base->en);
+	/* write to CSW to make s2f_ntrst reset */
+	writel(0x02, &scan_manager_base->stat);
+
+	/* Add a pause */
+	mdelay(1);
+
+	/* write 0x00 to CSW to clear the s2f_ntrst */
+	writel(0, &scan_manager_base->stat);
+
+	/*
+	 * Go to Test-Logic-Reset state.
+	 * This sets TAP controller into IDCODE mode.
+	 */
+	scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_TMS, 0x1f | (1 << 5), 0x0);
+
+	/* Go to Run-Test/Idle -> DR-Scan -> Capture-DR -> Shift-DR state. */
+	scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_TMS, 0x02 | (1 << 4), 0x0);
+
+	/*
+	 * Push 4 bytes of data through TDI->DR->TDO.
+	 *
+	 * Length of TDI data is 32bits (length - 1) and they are only
+	 * zeroes as we care only for TDO data.
+	 */
+	ret = scan_mgr_jtag_insn_data(0x4, &data, 32);
+	/* Read 32 bit from captured JTAG data. */
+	if (!ret)
+		id = readl(&scan_manager_base->fifo_quad_byte);
+
+	/* Disable all port */
+	writel(0, &scan_manager_base->en);
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SCANMGRGRP_CTRL);
+
+	return id;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/secure_reg_helper.c b/roms/u-boot/arch/arm/mach-socfpga/secure_reg_helper.c
new file mode 100644
index 000000000..0d4f45f33
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/secure_reg_helper.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/secure_reg_helper.h>
+#include <asm/arch/smc_api.h>
+#include <asm/arch/system_manager.h>
+#include <linux/errno.h>
+#include <linux/intel-smc.h>
+
+int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t *reg_addr)
+{
+	switch (id) {
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC:
+		*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC;
+		break;
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0:
+		*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0;
+		break;
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1:
+		*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1;
+		break;
+	case SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC2:
+		*reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2;
+		break;
+	default:
+		return -EADDRNOTAVAIL;
+	}
+	return 0;
+}
+
+int socfpga_secure_reg_read32(u32 id, u32 *val)
+{
+	int ret;
+	u64 ret_arg;
+	u64 args[1];
+
+	phys_addr_t reg_addr;
+	ret = socfpga_secure_convert_reg_id_to_addr(id, &reg_addr);
+	if (ret)
+		return ret;
+
+	args[0] = (u64)reg_addr;
+	ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
+	if (ret)
+		return ret;
+
+	*val = (u32)ret_arg;
+
+	return 0;
+}
+
+int socfpga_secure_reg_write32(u32 id, u32 val)
+{
+	int ret;
+	u64 args[2];
+
+	phys_addr_t reg_addr;
+	ret = socfpga_secure_convert_reg_id_to_addr(id, &reg_addr);
+	if (ret)
+		return ret;
+
+	args[0] = (u64)reg_addr;
+	args[1] = val;
+	return invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+}
+
+int socfpga_secure_reg_update32(u32 id, u32 mask, u32 val)
+{
+	int ret;
+	u64 args[3];
+
+	phys_addr_t reg_addr;
+	ret = socfpga_secure_convert_reg_id_to_addr(id, &reg_addr);
+	if (ret)
+		return ret;
+
+	args[0] = (u64)reg_addr;
+	args[1] = mask;
+	args[2] = val;
+	return invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/secure_vab.c b/roms/u-boot/arch/arm/mach-socfpga/secure_vab.c
new file mode 100644
index 000000000..e2db58850
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/secure_vab.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/secure_vab.h>
+#include <asm/arch/smc_api.h>
+#include <asm/unaligned.h>
+#include <common.h>
+#include <exports.h>
+#include <linux/errno.h>
+#include <linux/intel-smc.h>
+#include <log.h>
+
+#define CHUNKSZ_PER_WD_RESET		(256 * SZ_1K)
+
+/*
+ * Read the length of the VAB certificate from the end of image
+ * and calculate the actual image size (excluding the VAB certificate).
+ */
+static size_t get_img_size(u8 *img_buf, size_t img_buf_sz)
+{
+	u8 *img_buf_end = img_buf + img_buf_sz;
+	u32 cert_sz = get_unaligned_le32(img_buf_end - sizeof(u32));
+	u8 *p = img_buf_end - cert_sz - sizeof(u32);
+
+	/* Ensure p is pointing within the img_buf */
+	if (p < img_buf || p > (img_buf_end - VAB_CERT_HEADER_SIZE))
+		return 0;
+
+	if (get_unaligned_le32(p) == SDM_CERT_MAGIC_NUM)
+		return (size_t)(p - img_buf);
+
+	return 0;
+}
+
+/*
+ * Vendor Authorized Boot (VAB) is a security feature for authenticating
+ * the images such as U-Boot, ARM trusted Firmware, Linux kernel,
+ * device tree blob and etc loaded from FIT. User can also trigger
+ * the VAB authentication from U-Boot command.
+ *
+ * This function extracts the VAB certificate and signature block
+ * appended at the end of the image, then send to Secure Device Manager
+ * (SDM) for authentication. This function will validate the SHA384
+ * of the image against the SHA384 hash stored in the VAB certificate
+ * before sending the VAB certificate to SDM for authentication.
+ *
+ * RETURN
+ * 0 if authentication success or
+ *   if authentication is not required and bypassed on a non-secure device
+ * negative error code if authentication fail
+ */
+int socfpga_vendor_authentication(void **p_image, size_t *p_size)
+{
+	int retry_count = 20;
+	u8 hash384[SHA384_SUM_LEN];
+	u64 img_addr, mbox_data_addr;
+	size_t img_sz, mbox_data_sz;
+	u8 *cert_hash_ptr, *mbox_relocate_data_addr;
+	u32 resp = 0, resp_len = 1;
+	int ret;
+
+	img_addr = (uintptr_t)*p_image;
+
+	debug("Authenticating image at address 0x%016llx (%ld bytes)\n",
+	      img_addr, *p_size);
+
+	img_sz = get_img_size((u8 *)img_addr, *p_size);
+	debug("img_sz = %ld\n", img_sz);
+
+	if (!img_sz) {
+		puts("VAB certificate not found in image!\n");
+		return -ENOKEY;
+	}
+
+	if (!IS_ALIGNED(img_sz, sizeof(u32))) {
+		printf("Image size (%ld bytes) not aliged to 4 bytes!\n",
+		       img_sz);
+		return -EBFONT;
+	}
+
+	/* Generate HASH384 from the image */
+	sha384_csum_wd((u8 *)img_addr, img_sz, hash384, CHUNKSZ_PER_WD_RESET);
+
+	cert_hash_ptr = (u8 *)(img_addr + img_sz + VAB_CERT_MAGIC_OFFSET +
+			       VAB_CERT_FIT_SHA384_OFFSET);
+
+	/*
+	 * Compare the SHA384 found in certificate against the SHA384
+	 * calculated from image
+	 */
+	if (memcmp(hash384, cert_hash_ptr, SHA384_SUM_LEN)) {
+		puts("SHA384 not match!\n");
+		return -EKEYREJECTED;
+	}
+
+	mbox_data_addr = img_addr + img_sz - sizeof(u32);
+	/* Size in word (32bits) */
+	mbox_data_sz = (ALIGN(*p_size - img_sz, sizeof(u32))) >> 2;
+
+	debug("mbox_data_addr = 0x%016llx\n", mbox_data_addr);
+	debug("mbox_data_sz = %ld words\n", mbox_data_sz);
+
+	/*
+	 * Relocate certificate to first memory block before trigger SMC call
+	 * to send mailbox command because ATF only able to access first
+	 * memory block.
+	 */
+	mbox_relocate_data_addr = (u8 *)malloc(mbox_data_sz * sizeof(u32));
+	if (!mbox_relocate_data_addr) {
+		puts("Out of memory for VAB certificate relocation!\n");
+		return -ENOMEM;
+	}
+
+	memcpy(mbox_relocate_data_addr, (u8 *)mbox_data_addr, mbox_data_sz * sizeof(u32));
+	*(u32 *)mbox_relocate_data_addr = 0;
+
+	debug("mbox_relocate_data_addr = 0x%p\n", mbox_relocate_data_addr);
+
+	do {
+		if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
+			/* Invoke SMC call to ATF to send the VAB certificate to SDM */
+			ret  = smc_send_mailbox(MBOX_VAB_SRC_CERT, mbox_data_sz,
+						(u32 *)mbox_relocate_data_addr, 0, &resp_len,
+						&resp);
+		} else {
+			/* Send the VAB certficate to SDM for authentication */
+			ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_VAB_SRC_CERT,
+					    MBOX_CMD_DIRECT, mbox_data_sz,
+					    (u32 *)mbox_relocate_data_addr, 0, &resp_len,
+					    &resp);
+		}
+		/* If SDM is not available, just delay 50ms and retry again */
+		if (ret == MBOX_RESP_DEVICE_BUSY)
+			mdelay(50);
+		else
+			break;
+	} while (--retry_count);
+
+	/* Free the relocate certificate memory space */
+	free(mbox_relocate_data_addr);
+
+	/* Exclude the size of the VAB certificate from image size */
+	*p_size = img_sz;
+
+	debug("ret = 0x%08x, resp = 0x%08x, resp_len = %d\n", ret, resp,
+	      resp_len);
+
+	if (ret) {
+		/*
+		 * Unsupported mailbox command or device not in the
+		 * owned/secure state
+		 */
+		if (ret == MBOX_RESP_NOT_ALLOWED_UNDER_SECURITY_SETTINGS) {
+			/* SDM bypass authentication */
+			printf("%s 0x%016llx (%ld bytes)\n",
+			       "Image Authentication bypassed at address",
+			       img_addr, img_sz);
+			return 0;
+		}
+		puts("VAB certificate authentication failed in SDM");
+		if (ret == MBOX_RESP_DEVICE_BUSY) {
+			puts(" (SDM busy timeout)\n");
+			return -ETIMEDOUT;
+		} else if (ret == MBOX_RESP_UNKNOWN) {
+			puts(" (Not supported)\n");
+			return -ESRCH;
+		}
+		puts("\n");
+		return -EKEYREJECTED;
+	} else {
+		/* If Certificate Process Status has error */
+		if (resp) {
+			puts("VAB certificate process failed\n");
+			return -ENOEXEC;
+		}
+	}
+
+	printf("%s 0x%016llx (%ld bytes)\n",
+	       "Image Authentication passed at address", img_addr, img_sz);
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/smc_api.c b/roms/u-boot/arch/arm/mach-socfpga/smc_api.c
new file mode 100644
index 000000000..8ffc7a472
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/smc_api.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <linux/intel-smc.h>
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+	struct pt_regs regs;
+
+	memset(&regs, 0, sizeof(regs));
+	regs.regs[0] = func_id;
+
+	if (args)
+		memcpy(&regs.regs[1], args, arg_len * sizeof(*args));
+
+	smc_call(&regs);
+
+	if (ret_arg)
+		memcpy(ret_arg, &regs.regs[1], ret_len * sizeof(*ret_arg));
+
+	return regs.regs[0];
+}
+
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+		     u32 *resp_buf)
+{
+	int ret;
+	u64 args[6];
+	u64 resp[3];
+
+	args[0] = cmd;
+	args[1] = (u64)arg;
+	args[2] = len;
+	args[3] = urgent;
+	args[4] = (u64)resp_buf;
+	if (resp_buf_len)
+		args[5] = *resp_buf_len;
+	else
+		args[5] = 0;
+
+	ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
+			 resp, ARRAY_SIZE(resp));
+
+	if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) {
+		if (!resp[0])
+			*resp_buf_len = resp[1];
+	}
+
+	return (int)resp[0];
+}
+
+int smc_get_usercode(u32 *usercode)
+{
+	int ret;
+	u64 resp;
+
+	if (!usercode)
+		return -EINVAL;
+
+	ret = invoke_smc(INTEL_SIP_SMC_GET_USERCODE, NULL, 0,
+			 &resp, 1);
+
+	if (ret == INTEL_SIP_SMC_STATUS_OK)
+		*usercode = (u32)resp;
+
+	return ret;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/spl_a10.c b/roms/u-boot/arch/arm/mach-socfpga/spl_a10.c
new file mode 100644
index 000000000..b5f43f09d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/spl_a10.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/pl310.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <image.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/scu.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/fpga_manager.h>
+#include <mmc.h>
+#include <memalign.h>
+
+#define FPGA_BUFSIZ	16 * 1024
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOOTROM_SHARED_MEM_SIZE		0x800	/* 2KB */
+#define BOOTROM_SHARED_MEM_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 SOCFPGA_PHYS_OCRAM_SIZE - \
+					 BOOTROM_SHARED_MEM_SIZE)
+#define RST_STATUS_SHARED_ADDR		(BOOTROM_SHARED_MEM_ADDR + 0x438)
+static u32 rst_mgr_status __section(".data");
+
+/*
+ * Bootrom will clear the status register in reset manager and stores the
+ * reset status value in shared memory. Bootrom stores shared data at last
+ * 2KB of onchip RAM.
+ * This function save reset status provided by BootROM to rst_mgr_status.
+ * More information about reset status register value can be found in reset
+ * manager register description.
+ * When running in debugger without Bootrom, r0 to r3 are random values.
+ * So, skip save the value when r0 is not BootROM shared data address.
+ *
+ * r0 - Contains the pointer to the shared memory block. The shared
+ *	memory block is located in the top 2 KB of on-chip RAM.
+ * r1 - contains the length of the shared memory.
+ * r2 - unused and set to 0x0.
+ * r3 - points to the version block.
+ */
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+		      unsigned long r3)
+{
+	if (r0 == BOOTROM_SHARED_MEM_ADDR)
+		rst_mgr_status = readl(RST_STATUS_SHARED_ADDR);
+
+	save_boot_params_ret();
+}
+
+u32 spl_boot_device(void)
+{
+	const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
+
+	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
+	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
+		return BOOT_DEVICE_RAM;
+	case 0x2:	/* NAND Flash (1.8V) */
+	case 0x3:	/* NAND Flash (3.0V) */
+		socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+		return BOOT_DEVICE_NAND;
+	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
+	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
+		socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+		socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+		return BOOT_DEVICE_MMC1;
+	case 0x6:	/* QSPI Flash (1.8V) */
+	case 0x7:	/* QSPI Flash (3.0V) */
+		socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+		return BOOT_DEVICE_SPI;
+	default:
+		printf("Invalid boot device (bsel=%08x)!\n", bsel);
+		hang();
+	}
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_mmc_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+	return MMCSD_MODE_FS;
+#else
+	return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void spl_board_init(void)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
+
+	/* enable console uart printing */
+	preloader_console_init();
+	WATCHDOG_RESET();
+
+	arch_early_init_r();
+
+	/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
+	if (is_fpgamgr_user_mode()) {
+		int ret = config_pins(gd->fdt_blob, "shared");
+
+		if (ret)
+			return;
+
+		ret = config_pins(gd->fdt_blob, "fpga");
+		if (ret)
+			return;
+	} else if (!is_fpgamgr_early_user_mode()) {
+		/* Program IOSSM(early IO release) or full FPGA */
+		fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+	}
+
+	/* If the IOSSM/full FPGA is already loaded, start DDR */
+	if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+		ddr_calibration_sequence();
+
+	if (!is_fpgamgr_user_mode())
+		fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+}
+
+void board_init_f(ulong dummy)
+{
+	if (spl_early_init())
+		hang();
+
+	socfpga_get_managers_addr();
+
+	dcache_disable();
+
+	socfpga_init_security_policies();
+	socfpga_sdram_remap_zero();
+	socfpga_pl310_clear();
+
+	/* Assert reset to all except L4WD0 and L4TIMER0 */
+	socfpga_per_reset_all();
+	socfpga_watchdog_disable();
+
+	/* Configure the clock based on handoff */
+	cm_basic_init(gd->fdt_blob);
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* release osc1 watchdog timer 0 from reset */
+	socfpga_reset_deassert_osc1wd0();
+
+	/* reconfigure and enable the watchdog */
+	hw_watchdog_init();
+	WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+	config_dedicated_pins(gd->fdt_blob);
+	WATCHDOG_RESET();
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/spl_agilex.c b/roms/u-boot/arch/arm/mach-socfpga/spl_agilex.c
new file mode 100644
index 000000000..ee5a9dc1e
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/spl_agilex.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <spl.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <watchdog.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_managers_addr();
+
+	/* Ensure watchdog is paused when debugging is happening */
+	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* Enable watchdog before initializing the HW */
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+	hw_watchdog_init();
+#endif
+
+	/* ensure all processors are not released prior Linux boot */
+	writeq(0, CPU_RELEASE_ADDR);
+
+	timer_init();
+
+	sysmgr_pinmux_init();
+
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	if (ret) {
+		debug("Clock init failed: %d\n", ret);
+		hang();
+	}
+
+	preloader_console_init();
+	print_reset_info();
+	cm_print_clock_quick_summary();
+
+	firewall_setup();
+	ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
+	if (ret) {
+		debug("CCU init failed: %d\n", ret);
+		hang();
+	}
+
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		hang();
+	}
+#endif
+
+	mbox_init();
+
+#ifdef CONFIG_CADENCE_QSPI
+	mbox_qspi_open();
+#endif
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/spl_gen5.c b/roms/u-boot/arch/arm/mach-socfpga/spl_gen5.c
new file mode 100644
index 000000000..7c7161176
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/spl_gen5.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <image.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/sections.h>
+#include <debug_uart.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#include <dm/uclass.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+	const u32 bsel = readl(socfpga_get_sysmgr_addr() +
+			       SYSMGR_GEN5_BOOTINFO);
+
+	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
+	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
+		return BOOT_DEVICE_RAM;
+	case 0x2:	/* NAND Flash (1.8V) */
+	case 0x3:	/* NAND Flash (3.0V) */
+		return BOOT_DEVICE_NAND;
+	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
+	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
+		return BOOT_DEVICE_MMC1;
+	case 0x6:	/* QSPI Flash (1.8V) */
+	case 0x7:	/* QSPI Flash (3.0V) */
+		return BOOT_DEVICE_SPI;
+	default:
+		printf("Invalid boot device (bsel=%08x)!\n", bsel);
+		hang();
+	}
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_mmc_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+	return MMCSD_MODE_FS;
+#else
+	return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	const struct cm_config *cm_default_cfg = cm_get_default_config();
+	unsigned long reg;
+	int ret;
+	struct udevice *dev;
+
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_managers_addr();
+
+	/*
+	 * Clear fake OCRAM ECC first as SBE
+	 * and DBE might triggered during power on
+	 */
+	reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
+	if (reg & SYSMGR_ECC_OCRAM_SERR)
+		writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
+		       socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
+	if (reg & SYSMGR_ECC_OCRAM_DERR)
+		writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
+		       socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
+
+	socfpga_sdram_remap_zero();
+	socfpga_pl310_clear();
+
+	debug("Freezing all I/O banks\n");
+	/* freeze all IO banks */
+	sys_mgr_frzctrl_freeze_req();
+
+	/* Put everything into reset but L4WD0. */
+	socfpga_per_reset_all();
+
+	if (!socfpga_is_booting_from_fpga()) {
+		/* Put FPGA bridges into reset too. */
+		socfpga_bridges_reset(1);
+	}
+
+	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
+	timer_init();
+
+	debug("Reconfigure Clock Manager\n");
+	/* reconfigure the PLLs */
+	if (cm_basic_init(cm_default_cfg))
+		hang();
+
+	/* Enable bootrom to configure IOs. */
+	sysmgr_config_warmrstcfgio(1);
+
+	/* configure the IOCSR / IO buffer settings */
+	if (scan_mgr_configure_iocsr())
+		hang();
+
+	sysmgr_config_warmrstcfgio(0);
+
+	/* configure the pin muxing through system manager */
+	sysmgr_config_warmrstcfgio(1);
+	sysmgr_pinmux_init();
+	sysmgr_config_warmrstcfgio(0);
+
+	/* Set bridges handoff value */
+	socfpga_bridges_set_handoff_regs(true, true, true);
+
+	debug("Unfreezing/Thaw all I/O banks\n");
+	/* unfreeze / thaw all IO banks */
+	sys_mgr_frzctrl_thaw_req();
+
+#ifdef CONFIG_DEBUG_UART
+	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
+	debug_uart_init();
+#endif
+
+	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+	if (ret)
+		debug("Reset init failed: %d\n", ret);
+
+#ifdef CONFIG_SPL_NAND_DENALI
+	clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4));
+#endif
+
+	/* enable console uart printing */
+	preloader_console_init();
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		hang();
+	}
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/spl_s10.c b/roms/u-boot/arch/arm/mach-socfpga/spl_s10.c
new file mode 100644
index 000000000..c20e87cdb
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/spl_s10.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <common.h>
+#include <debug_uart.h>
+#include <image.h>
+#include <spl.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <watchdog.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+	const struct cm_config *cm_default_cfg = cm_get_default_config();
+	int ret;
+
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_managers_addr();
+
+	/* Ensure watchdog is paused when debugging is happening */
+	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* Enable watchdog before initializing the HW */
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+	hw_watchdog_init();
+#endif
+
+	/* ensure all processors are not released prior Linux boot */
+	writeq(0, CPU_RELEASE_ADDR);
+
+	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
+	timer_init();
+
+	sysmgr_pinmux_init();
+
+	/* configuring the HPS clocks */
+	cm_basic_init(cm_default_cfg);
+
+#ifdef CONFIG_DEBUG_UART
+	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
+	debug_uart_init();
+#endif
+
+	preloader_console_init();
+	print_reset_info();
+	cm_print_clock_quick_summary();
+
+	firewall_setup();
+
+	/* disable ocram security at CCU for non secure access */
+	clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
+		     CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
+		     CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
+
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
+		struct udevice *dev;
+
+		ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+		if (ret) {
+			debug("DRAM init failed: %d\n", ret);
+			hang();
+		}
+#endif
+
+	mbox_init();
+
+#ifdef CONFIG_CADENCE_QSPI
+	mbox_qspi_open();
+#endif
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/spl_soc64.c b/roms/u-boot/arch/arm/mach-socfpga/spl_soc64.c
new file mode 100644
index 000000000..cb98ab39e
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/spl_soc64.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  Copyright (C) 2020 Intel Corporation. All rights reserved
+ *
+ */
+
+#include <common.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}
+
+#if IS_ENABLED(CONFIG_SPL_MMC_SUPPORT)
+u32 spl_boot_mode(const u32 boot_device)
+{
+	if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
+		return MMCSD_MODE_FS;
+	else
+		return MMCSD_MODE_RAW;
+}
+#endif
diff --git a/roms/u-boot/arch/arm/mach-socfpga/system_manager_gen5.c b/roms/u-boot/arch/arm/mach-socfpga/system_manager_gen5.c
new file mode 100644
index 000000000..09caebb3c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/system_manager_gen5.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/fpga_manager.h>
+
+/*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+static void populate_sysmgr_fpgaintf_module(void)
+{
+	u32 handoff_val = 0;
+
+	/* ISWGRP_HANDOFF_FPGAINTF */
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
+
+	/* Enable the signal for those HPS peripherals that use FPGA. */
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_NAND_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_NAND;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_RGMII1_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SDMMC_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_RGMII0_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SPIM0_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SPIM1_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+
+	/* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
+	based on pinmux setting */
+	setbits_le32(socfpga_get_sysmgr_addr() +
+		     SYSMGR_ISWGRP_HANDOFF_OFFSET(2),
+		     handoff_val);
+
+	handoff_val = readl(socfpga_get_sysmgr_addr() +
+			    SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
+	if (fpgamgr_test_fpga_ready()) {
+		/* Enable the required signals only */
+		writel(handoff_val,
+		       socfpga_get_sysmgr_addr() +
+		       SYSMGR_GEN5_FPGAINFGRP_MODULE);
+	}
+}
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+	u32 regs = (u32)socfpga_get_sysmgr_addr() + SYSMGR_GEN5_EMACIO;
+	const u8 *sys_mgr_init_table;
+	unsigned int len;
+	int i;
+
+	sysmgr_get_pinmux_table(&sys_mgr_init_table, &len);
+
+	for (i = 0; i < len; i++) {
+		writel(sys_mgr_init_table[i], regs);
+		regs += sizeof(regs);
+	}
+
+	populate_sysmgr_fpgaintf_module();
+}
+
+/*
+ * This bit allows the bootrom to configure the IOs after a warm reset.
+ */
+void sysmgr_config_warmrstcfgio(int enable)
+{
+	if (enable)
+		setbits_le32(socfpga_get_sysmgr_addr() +
+			     SYSMGR_GEN5_ROMCODEGRP_CTRL,
+			     SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
+	else
+		clrbits_le32(socfpga_get_sysmgr_addr() +
+			     SYSMGR_GEN5_ROMCODEGRP_CTRL,
+			     SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/system_manager_soc64.c b/roms/u-boot/arch/arm/mach-socfpga/system_manager_soc64.c
new file mode 100644
index 000000000..3b5e774e2
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/arch/handoff_soc64.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+	populate_sysmgr_pinmux();
+	populate_sysmgr_fpgaintf_module();
+}
+
+/*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+void populate_sysmgr_fpgaintf_module(void)
+{
+	u32 handoff_val = 0;
+
+	/* Enable the signal for those HPS peripherals that use FPGA. */
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NAND_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_NAND;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM0_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM1_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+	writel(handoff_val,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN2);
+
+	handoff_val = 0;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
+		handoff_val |= SYSMGR_FPGAINTF_EMAC2;
+	writel(handoff_val,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN3);
+}
+
+/*
+ * Configure all the pin muxes
+ */
+void populate_sysmgr_pinmux(void)
+{
+	u32 len, i;
+	u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX, BIG_ENDIAN);
+	u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL, BIG_ENDIAN);
+	u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA, BIG_ENDIAN);
+	u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY, BIG_ENDIAN);
+
+	len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
+	len = (len > len_fpga) ? len : len_fpga;
+	len = (len > len_delay) ? len : len_delay;
+
+	u32 handoff_table[len];
+
+	/* setup the pin sel */
+	len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux : SOC64_HANDOFF_MUX_LEN;
+	socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len, BIG_ENDIAN);
+	for (i = 0; i < len; i = i + 2) {
+		writel(handoff_table[i + 1],
+		       handoff_table[i] +
+		       (u8 *)socfpga_get_sysmgr_addr() +
+		       SYSMGR_SOC64_PINSEL0);
+	}
+
+	/* setup the pin ctrl */
+	len = (len_ioctl < SOC64_HANDOFF_IOCTL_LEN) ? len_ioctl : SOC64_HANDOFF_IOCTL_LEN;
+	socfpga_handoff_read((void *)SOC64_HANDOFF_IOCTL, handoff_table, len, BIG_ENDIAN);
+	for (i = 0; i < len; i = i + 2) {
+		writel(handoff_table[i + 1],
+		       handoff_table[i] +
+		       (u8 *)socfpga_get_sysmgr_addr() +
+		       SYSMGR_SOC64_IOCTRL0);
+	}
+
+	/* setup the fpga use */
+	len = (len_fpga < SOC64_HANDOFF_FPGA_LEN) ? len_fpga : SOC64_HANDOFF_FPGA_LEN;
+	socfpga_handoff_read((void *)SOC64_HANDOFF_FPGA, handoff_table, len, BIG_ENDIAN);
+	for (i = 0; i < len; i = i + 2) {
+		writel(handoff_table[i + 1],
+		       handoff_table[i] +
+		       (u8 *)socfpga_get_sysmgr_addr() +
+		       SYSMGR_SOC64_EMAC0_USEFPGA);
+	}
+
+	/* setup the IO delay */
+	len = (len_delay < SOC64_HANDOFF_DELAY_LEN) ? len_delay : SOC64_HANDOFF_DELAY_LEN;
+	socfpga_handoff_read((void *)SOC64_HANDOFF_DELAY, handoff_table, len, BIG_ENDIAN);
+	for (i = 0; i < len; i = i + 2) {
+		writel(handoff_table[i + 1],
+		       handoff_table[i] +
+		       (u8 *)socfpga_get_sysmgr_addr() +
+		       SYSMGR_SOC64_IODELAY0);
+	}
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/timer.c b/roms/u-boot/arch/arm/mach-socfpga/timer.c
new file mode 100644
index 000000000..a58f1cf9d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/timer.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+#define TIMER_LOAD_VAL		0xFFFFFFFF
+
+static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Timer initialization
+ */
+int timer_init(void)
+{
+	writel(TIMER_LOAD_VAL, &timer_base->load_val);
+	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
+	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
+	return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/timer_s10.c b/roms/u-boot/arch/arm/mach-socfpga/timer_s10.c
new file mode 100644
index 000000000..7d5598e1a
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/timer_s10.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+/*
+ * Timer initialization
+ */
+int timer_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	int enable = 0x3;	/* timer enable + output signal masked */
+	int loadval = ~0;
+
+	/* enable system counter */
+	writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);
+	/* enable processor pysical counter */
+	asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
+	asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
+#endif
+	return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/vab.c b/roms/u-boot/arch/arm/mach-socfpga/vab.c
new file mode 100644
index 000000000..85b3f3021
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/vab.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/arch/secure_vab.h>
+#include <command.h>
+#include <common.h>
+#include <linux/ctype.h>
+
+static int do_vab(struct cmd_tbl *cmdtp, int flag, int argc,
+		  char *const argv[])
+{
+	unsigned long addr, len;
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+	len = simple_strtoul(argv[2], NULL, 16);
+
+	if (socfpga_vendor_authentication((void *)&addr, (size_t *)&len) != 0)
+		return CMD_RET_FAILURE;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	vab,	3,	2,	do_vab,
+	"perform vendor authorization",
+	"addr len   - authorize 'len' bytes starting at\n"
+	"                 'addr' via vendor public key"
+);
diff --git a/roms/u-boot/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/roms/u-boot/arch/arm/mach-socfpga/wrap_handoff_soc64.c
new file mode 100644
index 000000000..a7ad7a18e
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/arch/handoff_soc64.h>
+#include <asm/io.h>
+#include <common.h>
+#include <errno.h>
+#include "log.h"
+
+int socfpga_get_handoff_size(void *handoff_address, enum endianness endian)
+{
+	u32 size;
+
+	size = readl(handoff_address + SOC64_HANDOFF_OFFSET_LENGTH);
+	if (endian == BIG_ENDIAN)
+		size = swab32(size);
+
+	size = (size - SOC64_HANDOFF_OFFSET_DATA) / sizeof(u32);
+
+	debug("%s: handoff address = 0x%p handoff size = 0x%08x\n", __func__,
+	      (u32 *)handoff_address, size);
+
+	return size;
+}
+
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
+			 enum endianness big_endian)
+{
+	u32 temp, i;
+	u32 *table_x32 = table;
+
+	debug("%s: handoff addr = 0x%p ", __func__, (u32 *)handoff_address);
+
+	if (big_endian) {
+		if (swab32(readl(SOC64_HANDOFF_BASE)) == SOC64_HANDOFF_MAGIC_BOOT) {
+			debug("Handoff table address = 0x%p ", table_x32);
+			debug("table length = 0x%x\n", table_len);
+			debug("%s: handoff data =\n{\n", __func__);
+
+			for (i = 0; i < table_len; i++) {
+				temp = readl(handoff_address +
+					     SOC64_HANDOFF_OFFSET_DATA +
+					     (i * sizeof(u32)));
+				*table_x32 = swab32(temp);
+
+				if (!(i % 2))
+					debug(" No.%d Addr 0x%08x: ", i,
+					      *table_x32);
+				else
+					debug(" 0x%08x\n", *table_x32);
+
+				table_x32++;
+			}
+			debug("\n}\n");
+		} else {
+			debug("%s: Cannot find SOC64_HANDOFF_MAGIC_BOOT ", __func__);
+			debug("at addr  0x%p\n", (u32 *)handoff_address);
+			return -EPERM;
+		}
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/wrap_iocsr_config.c b/roms/u-boot/arch/arm/mach-socfpga/wrap_iocsr_config.c
new file mode 100644
index 000000000..f810fade9
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/wrap_iocsr_config.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/clock_manager.h>
+
+/* Board-specific header. */
+#include <qts/iocsr_config.h>
+
+int iocsr_get_config_table(const unsigned int chain_id,
+			   const unsigned long **table,
+			   unsigned int *table_len)
+{
+	switch (chain_id) {
+	case 0:
+		*table = iocsr_scan_chain0_table;
+		*table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
+		break;
+	case 1:
+		*table = iocsr_scan_chain1_table;
+		*table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
+		break;
+	case 2:
+		*table = iocsr_scan_chain2_table;
+		*table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
+		break;
+	case 3:
+		*table = iocsr_scan_chain3_table;
+		*table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/wrap_pinmux_config.c b/roms/u-boot/arch/arm/mach-socfpga/wrap_pinmux_config.c
new file mode 100644
index 000000000..33ca14c9d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/wrap_pinmux_config.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <errno.h>
+
+/* Board-specific header. */
+#include <qts/pinmux_config.h>
+
+void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len)
+{
+	*table = sys_mgr_init_table;
+	*table_len = ARRAY_SIZE(sys_mgr_init_table);
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/wrap_pll_config.c b/roms/u-boot/arch/arm/mach-socfpga/wrap_pll_config.c
new file mode 100644
index 000000000..bd631e0fb
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/wrap_pll_config.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <qts/pll_config.h>
+
+#define MAIN_VCO_BASE (					\
+	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
+		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
+		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+#define PERI_VCO_BASE (					\
+	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
+		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
+	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
+		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
+		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+#define SDR_VCO_BASE (					\
+	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
+		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
+	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
+		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
+		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+static const struct cm_config cm_default_cfg = {
+	/* main group */
+	MAIN_VCO_BASE,
+	(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+		CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
+
+	/* peripheral group */
+	PERI_VCO_BASE,
+	(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+		CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+		CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+		CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+		CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+		CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+		CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
+
+	/* sdram pll group */
+	SDR_VCO_BASE,
+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
+	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
+	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
+	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
+
+	/* altera group */
+	CONFIG_HPS_ALTERAGRP_MPUCLK,
+};
+
+const struct cm_config * const cm_get_default_config(void)
+{
+	return &cm_default_cfg;
+}
+
+const unsigned int cm_get_osc_clk_hz(const int osc)
+{
+	if (osc == 1)
+		return CONFIG_HPS_CLK_OSC1_HZ;
+	else if (osc == 2)
+		return CONFIG_HPS_CLK_OSC2_HZ;
+	else
+		return 0;
+}
+
+const unsigned int cm_get_f2s_per_ref_clk_hz(void)
+{
+	return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+}
+
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
+{
+	return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/wrap_pll_config_soc64.c b/roms/u-boot/arch/arm/mach-socfpga/wrap_pll_config_soc64.c
new file mode 100644
index 000000000..6a0d6b5ea
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/wrap_pll_config_soc64.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/io.h>
+#include <asm/arch/handoff_soc64.h>
+#include <asm/arch/system_manager.h>
+
+const struct cm_config * const cm_get_default_config(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	struct cm_config *cm_handoff_cfg = (struct cm_config *)
+		(SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA);
+	u32 *conversion = (u32 *)cm_handoff_cfg;
+	u32 i;
+	u32 handoff_clk = readl(SOC64_HANDOFF_CLOCK);
+
+	if (swab32(handoff_clk) == SOC64_HANDOFF_MAGIC_CLOCK) {
+		writel(swab32(handoff_clk), SOC64_HANDOFF_CLOCK);
+		for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
+			conversion[i] = swab32(conversion[i]);
+		return cm_handoff_cfg;
+	} else if (handoff_clk == SOC64_HANDOFF_MAGIC_CLOCK) {
+		return cm_handoff_cfg;
+	}
+#endif
+	return NULL;
+}
+
+const unsigned int cm_get_osc_clk_hz(void)
+{
+#ifdef CONFIG_SPL_BUILD
+
+	u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC);
+
+	writel(clock,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
+#endif
+	return readl(socfpga_get_sysmgr_addr() +
+		     SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
+}
+
+const unsigned int cm_get_intosc_clk_hz(void)
+{
+	return CLKMGR_INTOSC_HZ;
+}
+
+const unsigned int cm_get_fpga_clk_hz(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA);
+
+	writel(clock,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
+#endif
+	return readl(socfpga_get_sysmgr_addr() +
+		     SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
+}
diff --git a/roms/u-boot/arch/arm/mach-socfpga/wrap_sdram_config.c b/roms/u-boot/arch/arm/mach-socfpga/wrap_sdram_config.c
new file mode 100644
index 000000000..4ea32e72c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/sdram.h>
+
+/* Board-specific header. */
+#include <qts/sdram_config.h>
+
+static const struct socfpga_sdram_config sdram_config = {
+	.ctrl_cfg =
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+			SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+			SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)			|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
+			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+			SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)			|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+			SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+			SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+			SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+			SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+			SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
+	.dram_timing1 =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+			SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+			SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+			SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+			SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+			SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+			SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
+	.dram_timing2 =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+			SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+			SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+			SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+			SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+			SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
+	.dram_timing3 =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+			SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+			SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+			SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+			SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+			SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
+	.dram_timing4 =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+			SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+			SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
+	.lowpwr_timing =
+		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+			SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)	|
+		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+			SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
+	.dram_odt =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
+			SDR_CTRLGRP_DRAMODT_READ_LSB)			|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
+			SDR_CTRLGRP_DRAMODT_WRITE_LSB),
+#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)	/* DDR3 */
+	.extratime1 =
+		(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+				SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+				SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+				SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
+#endif
+	.dram_addrw =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
+			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)		|
+		((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
+	.dram_if_width =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
+			SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
+	.dram_dev_width =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
+			SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
+	.dram_intr =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
+			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
+	.lowpwr_eq =
+		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
+			SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
+	.static_cfg =
+		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+			SDR_CTRLGRP_STATICCFG_MEMBL_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+			SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
+	.ctrl_width =
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
+			SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
+	.cport_width =
+		(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
+			SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
+	.cport_wmap =
+		(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
+			SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
+	.cport_rmap =
+		(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
+			SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
+	.rfifo_cmap =
+		(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
+			SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
+	.wfifo_cmap =
+		(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
+			SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
+	.cport_rdwr =
+		(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
+			SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
+	.port_cfg =
+		(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
+			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
+	.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
+	.fifo_cfg =
+		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+			SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+			SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
+	.mp_priority =
+		(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
+			SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
+	.mp_weight0 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
+	.mp_weight1 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
+	.mp_weight2 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
+	.mp_weight3 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
+	.mp_pacing0 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+			SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
+	.mp_pacing1 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
+	.mp_pacing2 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+			SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
+	.mp_pacing3 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+			SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
+	.mp_threshold0 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+			SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
+	.mp_threshold1 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
+			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
+	.mp_threshold2 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+			SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
+	.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
+};
+
+static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
+	.activate_0_and_1		= RW_MGR_ACTIVATE_0_AND_1,
+	.activate_0_and_1_wait1		= RW_MGR_ACTIVATE_0_AND_1_WAIT1,
+	.activate_0_and_1_wait2		= RW_MGR_ACTIVATE_0_AND_1_WAIT2,
+	.clear_dqs_enable		= RW_MGR_CLEAR_DQS_ENABLE,
+	.guaranteed_read		= RW_MGR_GUARANTEED_READ,
+	.guaranteed_read_cont		= RW_MGR_GUARANTEED_READ_CONT,
+	.guaranteed_write		= RW_MGR_GUARANTEED_WRITE,
+	.guaranteed_write_wait0		= RW_MGR_GUARANTEED_WRITE_WAIT0,
+	.guaranteed_write_wait1		= RW_MGR_GUARANTEED_WRITE_WAIT1,
+	.guaranteed_write_wait2		= RW_MGR_GUARANTEED_WRITE_WAIT2,
+	.guaranteed_write_wait3		= RW_MGR_GUARANTEED_WRITE_WAIT3,
+	.idle_loop1			= RW_MGR_IDLE_LOOP1,
+	.idle_loop2			= RW_MGR_IDLE_LOOP2,
+#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1)	/* DDR2 */
+	.emr				= RW_MGR_EMR,
+	.emr2				= RW_MGR_EMR2,
+	.emr3				= RW_MGR_EMR3,
+	.init_reset_0_cke_0		= RW_MGR_INIT_CKE_0,
+	.nop				= RW_MGR_NOP,
+	.refresh			= RW_MGR_REFRESH,
+	.mr_calib			= RW_MGR_MR_CALIB,
+	.mr_user			= RW_MGR_MR_USER,
+	.mr_dll_reset			= RW_MGR_MR_DLL_RESET,
+	.emr_ocd_enable			= RW_MGR_EMR_OCD_ENABLE,
+#elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)	/* DDR3 */
+	.activate_1			= RW_MGR_ACTIVATE_1,
+	.idle				= RW_MGR_IDLE,
+	.init_reset_0_cke_0		= RW_MGR_INIT_RESET_0_CKE_0,
+	.init_reset_1_cke_0		= RW_MGR_INIT_RESET_1_CKE_0,
+	.mrs1				= RW_MGR_MRS1,
+	.mrs1_mirr			= RW_MGR_MRS1_MIRR,
+	.mrs2				= RW_MGR_MRS2,
+	.mrs2_mirr			= RW_MGR_MRS2_MIRR,
+	.mrs3				= RW_MGR_MRS3,
+	.mrs3_mirr			= RW_MGR_MRS3_MIRR,
+	.refresh_all			= RW_MGR_REFRESH_ALL,
+	.rreturn			= RW_MGR_RETURN,
+	.sgle_read			= RW_MGR_SGLE_READ,
+	.zqcl				= RW_MGR_ZQCL,
+	.mrs0_dll_reset			= RW_MGR_MRS0_DLL_RESET,
+	.mrs0_dll_reset_mirr		= RW_MGR_MRS0_DLL_RESET_MIRR,
+	.mrs0_user			= RW_MGR_MRS0_USER,
+	.mrs0_user_mirr			= RW_MGR_MRS0_USER_MIRR,
+#else
+#error LPDDR2 and other DRAM types are not yet supported
+#endif
+	.lfsr_wr_rd_bank_0		= RW_MGR_LFSR_WR_RD_BANK_0,
+	.lfsr_wr_rd_bank_0_data		= RW_MGR_LFSR_WR_RD_BANK_0_DATA,
+	.lfsr_wr_rd_bank_0_dqs		= RW_MGR_LFSR_WR_RD_BANK_0_DQS,
+	.lfsr_wr_rd_bank_0_nop		= RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+	.lfsr_wr_rd_bank_0_wait		= RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
+	.lfsr_wr_rd_bank_0_wl_1		= RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
+	.lfsr_wr_rd_dm_bank_0		= RW_MGR_LFSR_WR_RD_DM_BANK_0,
+	.lfsr_wr_rd_dm_bank_0_data	= RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
+	.lfsr_wr_rd_dm_bank_0_dqs	= RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
+	.lfsr_wr_rd_dm_bank_0_nop	= RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+	.lfsr_wr_rd_dm_bank_0_wait	= RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
+	.lfsr_wr_rd_dm_bank_0_wl_1	= RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
+	.precharge_all			= RW_MGR_PRECHARGE_ALL,
+	.read_b2b			= RW_MGR_READ_B2B,
+	.read_b2b_wait1			= RW_MGR_READ_B2B_WAIT1,
+	.read_b2b_wait2			= RW_MGR_READ_B2B_WAIT2,
+
+	.true_mem_data_mask_width	= RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
+	.mem_address_mirroring		= RW_MGR_MEM_ADDRESS_MIRRORING,
+	.mem_data_mask_width		= RW_MGR_MEM_DATA_MASK_WIDTH,
+	.mem_data_width			= RW_MGR_MEM_DATA_WIDTH,
+	.mem_dq_per_read_dqs		= RW_MGR_MEM_DQ_PER_READ_DQS,
+	.mem_dq_per_write_dqs		= RW_MGR_MEM_DQ_PER_WRITE_DQS,
+	.mem_if_read_dqs_width		= RW_MGR_MEM_IF_READ_DQS_WIDTH,
+	.mem_if_write_dqs_width		= RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
+	.mem_number_of_cs_per_dimm	= RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
+	.mem_number_of_ranks		= RW_MGR_MEM_NUMBER_OF_RANKS,
+	.mem_virtual_groups_per_read_dqs =
+		RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
+	.mem_virtual_groups_per_write_dqs =
+		RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
+};
+
+static const struct socfpga_sdram_io_config io_config = {
+	.delay_per_dchain_tap		= IO_DELAY_PER_DCHAIN_TAP,
+	.delay_per_dqs_en_dchain_tap	= IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
+	.delay_per_opa_tap		= IO_DELAY_PER_OPA_TAP,
+	.dll_chain_length		= IO_DLL_CHAIN_LENGTH,
+	.dqdqs_out_phase_max		= IO_DQDQS_OUT_PHASE_MAX,
+	.dqs_en_delay_max		= IO_DQS_EN_DELAY_MAX,
+	.dqs_en_delay_offset		= IO_DQS_EN_DELAY_OFFSET,
+	.dqs_en_phase_max		= IO_DQS_EN_PHASE_MAX,
+	.dqs_in_delay_max		= IO_DQS_IN_DELAY_MAX,
+	.dqs_in_reserve			= IO_DQS_IN_RESERVE,
+	.dqs_out_reserve		= IO_DQS_OUT_RESERVE,
+	.io_in_delay_max		= IO_IO_IN_DELAY_MAX,
+	.io_out1_delay_max		= IO_IO_OUT1_DELAY_MAX,
+	.io_out2_delay_max		= IO_IO_OUT2_DELAY_MAX,
+	.shift_dqs_en_when_shift_dqs	= IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
+};
+
+static const struct socfpga_sdram_misc_config misc_config = {
+#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1)	/* DDR2 */
+	.afi_clk_freq			= AFI_CLK_FREQ,
+#endif
+	.afi_rate_ratio			= AFI_RATE_RATIO,
+	.calib_lfifo_offset		= CALIB_LFIFO_OFFSET,
+	.calib_vfifo_offset		= CALIB_VFIFO_OFFSET,
+	.enable_super_quick_calibration	= ENABLE_SUPER_QUICK_CALIBRATION,
+	.max_latency_count_width	= MAX_LATENCY_COUNT_WIDTH,
+	.read_valid_fifo_size		= READ_VALID_FIFO_SIZE,
+	.reg_file_init_seq_signature	= REG_FILE_INIT_SEQ_SIGNATURE,
+	.tinit_cntr0_val		= TINIT_CNTR0_VAL,
+	.tinit_cntr1_val		= TINIT_CNTR1_VAL,
+	.tinit_cntr2_val		= TINIT_CNTR2_VAL,
+	.treset_cntr0_val		= TRESET_CNTR0_VAL,
+	.treset_cntr1_val		= TRESET_CNTR1_VAL,
+	.treset_cntr2_val		= TRESET_CNTR2_VAL,
+};
+
+const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
+{
+	return &sdram_config;
+}
+
+void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
+{
+	*init = ac_rom_init;
+	*nelem = ARRAY_SIZE(ac_rom_init);
+}
+
+void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
+{
+	*init = inst_rom_init;
+	*nelem = ARRAY_SIZE(inst_rom_init);
+}
+
+const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
+{
+	return &rw_mgr_config;
+}
+
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
+{
+	return &io_config;
+}
+
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
+{
+	return &misc_config;
+}