Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

7 files changed, 786 insertions, 0 deletions

diff --git a/roms/u-boot/arch/nios2/cpu/Makefile b/roms/u-boot/arch/nios2/cpu/Makefile
new file mode 100644
index 000000000..0b675e7c0
--- /dev/null
+++ b/roms/u-boot/arch/nios2/cpu/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+extra-y	= start.o
+obj-y	= exceptions.o
+obj-y	+= cpu.o interrupts.o traps.o
diff --git a/roms/u-boot/arch/nios2/cpu/cpu.c b/roms/u-boot/arch/nios2/cpu/cpu.c
new file mode 100644
index 000000000..b55c8fbc5
--- /dev/null
+++ b/roms/u-boot/arch/nios2/cpu/cpu.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <init.h>
+#include <irq_func.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+	printf("CPU:   Nios-II\n");
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_ALTERA_SYSID
+int checkboard(void)
+{
+	display_sysid();
+	return 0;
+}
+#endif
+
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	disable_interrupts();
+	/* indirect call to go beyond 256MB limitation of toolchain */
+	nios2_callr(gd->arch.reset_addr);
+	return 0;
+}
+
+/*
+ * COPY EXCEPTION TRAMPOLINE -- copy the tramp to the
+ * exception address. Define CONFIG_ROM_STUBS to prevent
+ * the copy (e.g. exception in flash or in other
+ * softare/firmware component).
+ */
+#ifndef CONFIG_ROM_STUBS
+static void copy_exception_trampoline(void)
+{
+	extern int _except_start, _except_end;
+	void *except_target = (void *)gd->arch.exception_addr;
+
+	if (&_except_start != except_target) {
+		memcpy(except_target, &_except_start,
+		       &_except_end - &_except_start);
+		flush_cache(gd->arch.exception_addr,
+			    &_except_end - &_except_start);
+	}
+}
+#endif
+
+int arch_cpu_init_dm(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_CPU, &dev);
+	if (ret)
+		return ret;
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_ROM_STUBS
+	copy_exception_trampoline();
+#endif
+
+	return 0;
+}
+
+static int altera_nios2_get_desc(const struct udevice *dev, char *buf,
+				 int size)
+{
+	const char *cpu_name = "Nios-II";
+
+	if (size < strlen(cpu_name))
+		return -ENOSPC;
+	strcpy(buf, cpu_name);
+
+	return 0;
+}
+
+static int altera_nios2_get_info(const struct udevice *dev,
+				 struct cpu_info *info)
+{
+	info->cpu_freq = gd->cpu_clk;
+	info->features = (1 << CPU_FEAT_L1_CACHE) |
+		(gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0);
+
+	return 0;
+}
+
+static int altera_nios2_get_count(const struct udevice *dev)
+{
+	return 1;
+}
+
+static int altera_nios2_probe(struct udevice *dev)
+{
+	const void *blob = gd->fdt_blob;
+	int node = dev_of_offset(dev);
+
+	gd->cpu_clk = fdtdec_get_int(blob, node,
+		"clock-frequency", 0);
+	gd->arch.dcache_line_size = fdtdec_get_int(blob, node,
+		"dcache-line-size", 0);
+	gd->arch.icache_line_size = fdtdec_get_int(blob, node,
+		"icache-line-size", 0);
+	gd->arch.dcache_size = fdtdec_get_int(blob, node,
+		"dcache-size", 0);
+	gd->arch.icache_size = fdtdec_get_int(blob, node,
+		"icache-size", 0);
+	gd->arch.reset_addr = fdtdec_get_int(blob, node,
+		"altr,reset-addr", 0);
+	gd->arch.exception_addr = fdtdec_get_int(blob, node,
+		"altr,exception-addr", 0);
+	gd->arch.has_initda = fdtdec_get_int(blob, node,
+		"altr,has-initda", 0);
+	gd->arch.has_mmu = fdtdec_get_int(blob, node,
+		"altr,has-mmu", 0);
+	gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000;
+	gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000;
+	gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff;
+
+	return 0;
+}
+
+static const struct cpu_ops altera_nios2_ops = {
+	.get_desc	= altera_nios2_get_desc,
+	.get_info	= altera_nios2_get_info,
+	.get_count	= altera_nios2_get_count,
+};
+
+static const struct udevice_id altera_nios2_ids[] = {
+	{ .compatible = "altr,nios2-1.0" },
+	{ .compatible = "altr,nios2-1.1" },
+	{ }
+};
+
+U_BOOT_DRIVER(altera_nios2) = {
+	.name		= "altera_nios2",
+	.id		= UCLASS_CPU,
+	.of_match	= altera_nios2_ids,
+	.probe		= altera_nios2_probe,
+	.ops		= &altera_nios2_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
+
+/* This is a dummy function on nios2 */
+int dram_init(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/arch/nios2/cpu/exceptions.S b/roms/u-boot/arch/nios2/cpu/exceptions.S
new file mode 100644
index 000000000..95be04cdb
--- /dev/null
+++ b/roms/u-boot/arch/nios2/cpu/exceptions.S
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#include <config.h>
+#include <asm/opcodes.h>
+
+
+	.text
+	.align	4
+
+	.global _exception
+
+	.set noat
+	.set nobreak
+
+_exception:
+	/* SAVE ALL REGS -- this allows trap and unimplemented
+	 * instruction handlers to be coded conveniently in C
+	 */
+	addi	sp, sp, -(33*4)
+	stw	r0, 0(sp)
+	stw	r1, 4(sp)
+	stw	r2, 8(sp)
+	stw	r3, 12(sp)
+	stw	r4, 16(sp)
+	stw	r5, 20(sp)
+	stw	r6, 24(sp)
+	stw	r7, 28(sp)
+	stw	r8, 32(sp)
+	stw	r9, 36(sp)
+	stw	r10, 40(sp)
+	stw	r11, 44(sp)
+	stw	r12, 48(sp)
+	stw	r13, 52(sp)
+	stw	r14, 56(sp)
+	stw	r15, 60(sp)
+	stw	r16, 64(sp)
+	stw	r17, 68(sp)
+	stw	r19, 72(sp)
+	stw	r19, 76(sp)
+	stw	r20, 80(sp)
+	stw	r21, 84(sp)
+	stw	r22, 88(sp)
+	stw	r23, 92(sp)
+	stw	r24, 96(sp)
+	stw	r25, 100(sp)
+	stw	r26, 104(sp)
+	stw	r27, 108(sp)
+	stw	r28, 112(sp)
+	stw	r29, 116(sp)
+	stw	r30, 120(sp)
+	stw	r31, 124(sp)
+	rdctl	et, estatus
+	stw	et, 128(sp)
+
+	/* If interrupts are disabled -- software interrupt */
+	rdctl	et, estatus
+	andi	et, et, 1
+	beq	et, r0, 0f
+
+	/* If no interrupts are pending -- software interrupt */
+	rdctl	et, ipending
+	beq	et, r0, 0f
+
+	/* HARDWARE INTERRUPT: Call interrupt handler */
+	movhi	r3, %hi(external_interrupt)
+	ori	r3, r3, %lo(external_interrupt)
+	mov	r4, sp		/* ptr to regs */
+	callr	r3
+
+	/* Return address fixup: execution resumes by re-issue of
+	 * interrupted instruction at ea-4 (ea == r29). Here we do
+	 * simple fixup to allow common exception return.
+	 */
+	ldw	r3, 116(sp)
+	addi	r3, r3, -4
+	stw	r3, 116(sp)
+	br	_exception_return
+
+0:
+	/* TRAP EXCEPTION */
+	movhi	r3, %hi(OPC_TRAP)
+	ori	r3, r3, %lo(OPC_TRAP)
+	addi	r1, ea, -4
+	ldw	r1, 0(r1)
+	bne	r1, r3, 1f
+	movhi	r3, %hi(trap_handler)
+	ori	r3, r3, %lo(trap_handler)
+	mov	r4, sp		/* ptr to regs */
+	callr	r3
+	br	_exception_return
+
+1:
+	/* UNIMPLEMENTED INSTRUCTION EXCEPTION */
+	movhi	r3, %hi(soft_emulation)
+	ori	r3, r3, %lo(soft_emulation)
+	mov	r4, sp		/* ptr to regs */
+	callr	r3
+
+	/* Restore regsisters and return from exception*/
+_exception_return:
+	ldw	r1, 4(sp)
+	ldw	r2, 8(sp)
+	ldw	r3, 12(sp)
+	ldw	r4, 16(sp)
+	ldw	r5, 20(sp)
+	ldw	r6, 24(sp)
+	ldw	r7, 28(sp)
+	ldw	r8, 32(sp)
+	ldw	r9, 36(sp)
+	ldw	r10, 40(sp)
+	ldw	r11, 44(sp)
+	ldw	r12, 48(sp)
+	ldw	r13, 52(sp)
+	ldw	r14, 56(sp)
+	ldw	r15, 60(sp)
+	ldw	r16, 64(sp)
+	ldw	r17, 68(sp)
+	ldw	r19, 72(sp)
+	ldw	r19, 76(sp)
+	ldw	r20, 80(sp)
+	ldw	r21, 84(sp)
+	ldw	r22, 88(sp)
+	ldw	r23, 92(sp)
+	ldw	r24, 96(sp)
+	ldw	r25, 100(sp)
+	ldw	r26, 104(sp)
+	ldw	r27, 108(sp)
+	ldw	r28, 112(sp)
+	ldw	r29, 116(sp)
+	ldw	r30, 120(sp)
+	ldw	r31, 124(sp)
+	addi	sp, sp, (33*4)
+	eret
+/*-------------------------------------------------------------*/
diff --git a/roms/u-boot/arch/nios2/cpu/interrupts.c b/roms/u-boot/arch/nios2/cpu/interrupts.c
new file mode 100644
index 000000000..90cabb675
--- /dev/null
+++ b/roms/u-boot/arch/nios2/cpu/interrupts.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <irq_func.h>
+#include <asm/nios2.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/ptrace.h>
+
+/*************************************************************************/
+struct	irq_action {
+	interrupt_handler_t *handler;
+	void *arg;
+	int count;
+};
+
+static struct irq_action vecs[32];
+
+int disable_interrupts(void)
+{
+	int val = rdctl (CTL_STATUS);
+	wrctl (CTL_STATUS, val & ~STATUS_IE);
+	return (val & STATUS_IE);
+}
+
+void enable_interrupts( void )
+{
+	int val = rdctl (CTL_STATUS);
+	wrctl (CTL_STATUS, val | STATUS_IE);
+}
+
+void external_interrupt(struct pt_regs *regs)
+{
+	unsigned irqs;
+	struct irq_action *act;
+
+	/* Evaluate only irqs that are both enabled AND pending */
+	irqs = rdctl (CTL_IENABLE) & rdctl (CTL_IPENDING);
+	act = vecs;
+
+	/* Assume (as does the Nios2 HAL) that bit 0 is highest
+	 * priority. NOTE: There is ALWAYS a handler assigned
+	 * (the default if no other).
+	 */
+	while (irqs) {
+		if (irqs & 1) {
+			act->handler (act->arg);
+			act->count++;
+		}
+		irqs >>=1;
+		act++;
+	}
+}
+
+static void def_hdlr (void *arg)
+{
+	unsigned irqs = rdctl (CTL_IENABLE);
+
+	/* Disable the individual interrupt -- with gratuitous
+	 * warning.
+	 */
+	irqs &= ~(1 << (int)arg);
+	wrctl (CTL_IENABLE, irqs);
+	printf ("WARNING: Disabling unhandled interrupt: %d\n",
+			(int)arg);
+}
+
+/*************************************************************************/
+void irq_install_handler(int irq, interrupt_handler_t *hdlr, void *arg)
+{
+
+	int flag;
+	struct irq_action *act;
+	unsigned ena = rdctl (CTL_IENABLE);
+
+	if ((irq < 0) || (irq > 31))
+		return;
+	act = &vecs[irq];
+
+	flag = disable_interrupts();
+	if (hdlr) {
+		act->handler = hdlr;
+		act->arg = arg;
+		ena |= (1 << irq);		/* enable */
+	} else {
+		act->handler = def_hdlr;
+		act->arg = (void *)irq;
+		ena &= ~(1 << irq);		/* disable */
+	}
+	wrctl (CTL_IENABLE, ena);
+	if (flag) enable_interrupts();
+}
+
+
+int interrupt_init(void)
+{
+	int i;
+
+	/* Assign the default handler to all */
+	for (i = 0; i < 32; i++) {
+		vecs[i].handler = def_hdlr;
+		vecs[i].arg = (void *)i;
+		vecs[i].count = 0;
+	}
+
+	enable_interrupts();
+	return (0);
+}
+
+
+/*************************************************************************/
+#if defined(CONFIG_CMD_IRQ)
+int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int i;
+	struct irq_action *act = vecs;
+
+	printf ("\nInterrupt-Information:\n\n");
+	printf ("Nr  Routine   Arg       Count\n");
+	printf ("-----------------------------\n");
+
+	for (i=0; i<32; i++) {
+		if (act->handler != def_hdlr) {
+			printf ("%02d  %08lx  %08lx  %d\n",
+				i,
+				(ulong)act->handler,
+				(ulong)act->arg,
+				act->count);
+		}
+		act++;
+	}
+	printf ("\n");
+
+	return (0);
+}
+#endif
diff --git a/roms/u-boot/arch/nios2/cpu/start.S b/roms/u-boot/arch/nios2/cpu/start.S
new file mode 100644
index 000000000..f5ad184e8
--- /dev/null
+++ b/roms/u-boot/arch/nios2/cpu/start.S
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+
+/*
+ * icache and dcache configuration used only for start.S.
+ * the values are chosen so that it will work for all configuration.
+ */
+#define ICACHE_LINE_SIZE	32 /* fixed 32 */
+#define ICACHE_SIZE_MAX		0x10000 /* 64k max */
+#define DCACHE_LINE_SIZE_MIN	4 /* 4, 16, 32 */
+#define DCACHE_SIZE_MAX		0x10000 /* 64k max */
+
+	/* RESTART */
+	.text
+	.global _start, _except_start, _except_end
+
+_start:
+	wrctl	status, r0		/* Disable interrupts */
+	/*
+	 * ICACHE INIT -- only the icache line at the reset address
+	 * is invalidated at reset. So the init must stay within
+	 * the cache line size (8 words). If GERMS is used, we'll
+	 * just be invalidating the cache a second time. If cache
+	 * is not implemented initi behaves as nop.
+	 */
+	ori	r4, r0, %lo(ICACHE_LINE_SIZE)
+	movhi	r5, %hi(ICACHE_SIZE_MAX)
+	ori	r5, r5, %lo(ICACHE_SIZE_MAX)
+0:	initi	r5
+	sub	r5, r5, r4
+	bgt	r5, r0, 0b
+	br	_except_end	/* Skip the tramp */
+
+	/*
+	 * EXCEPTION TRAMPOLINE -- the following gets copied
+	 * to the exception address (below), but is otherwise at the
+	 * default exception vector offset (0x0020).
+	 */
+_except_start:
+	movhi	et, %hi(_exception)
+	ori	et, et, %lo(_exception)
+	jmp	et
+_except_end:
+
+	/*
+	 * INTERRUPTS -- for now, all interrupts masked and globally
+	 * disabled.
+	 */
+	wrctl	ienable, r0		/* All disabled	*/
+
+	/*
+	 * DCACHE INIT -- if dcache not implemented, initd behaves as
+	 * nop.
+	 */
+	ori	r4, r0, %lo(DCACHE_LINE_SIZE_MIN)
+	movhi	r5, %hi(DCACHE_SIZE_MAX)
+	ori	r5, r5, %lo(DCACHE_SIZE_MAX)
+	mov	r6, r0
+1:	initd	0(r6)
+	add	r6, r6, r4
+	bltu	r6, r5, 1b
+
+	/*
+	 * RELOCATE CODE, DATA & COMMAND TABLE -- the following code
+	 * assumes code, data and the command table are all
+	 * contiguous. This lets us relocate everything as a single
+	 * block. Make sure the linker script matches this ;-)
+	 */
+	nextpc	r4
+_cur:	movhi	r5, %hi(_cur - _start)
+	ori	r5, r5, %lo(_cur - _start)
+	sub	r4, r4, r5		/* r4 <- cur _start */
+	mov	r8, r4
+	movhi	r5, %hi(_start)
+	ori	r5, r5, %lo(_start)	/* r5 <- linked _start */
+	mov	sp, r5		/* initial stack below u-boot code */
+	beq	r4, r5, 3f
+
+	movhi	r6, %hi(CONFIG_SYS_MONITOR_LEN)
+	ori	r6, r6, %lo(CONFIG_SYS_MONITOR_LEN)
+	add	r6, r6, r5
+2:	ldwio	r7, 0(r4)
+	addi	r4, r4, 4
+	stwio	r7, 0(r5)
+	addi	r5, r5, 4
+	bne	r5, r6, 2b
+3:
+
+	/* JUMP TO RELOC ADDR */
+	movhi	r4, %hi(_reloc)
+	ori	r4, r4, %lo(_reloc)
+	jmp	r4
+_reloc:
+
+	/* STACK INIT -- zero top two words for call back chain. */
+	addi	sp, sp, -8
+	stw	r0, 0(sp)
+	stw	r0, 4(sp)
+	mov	fp, sp
+
+#ifdef CONFIG_DEBUG_UART
+	/* Set up the debug UART */
+	movhi	r2, %hi(debug_uart_init@h)
+	ori	r2, r2, %lo(debug_uart_init@h)
+	callr	r2
+#endif
+
+	/* Allocate and initialize reserved area, update SP */
+	mov	r4, sp
+	movhi	r2, %hi(board_init_f_alloc_reserve@h)
+	ori	r2, r2, %lo(board_init_f_alloc_reserve@h)
+	callr	r2
+	mov	sp, r2
+	mov	r4, sp
+	movhi	r2, %hi(board_init_f_init_reserve@h)
+	ori	r2, r2, %lo(board_init_f_init_reserve@h)
+	callr	r2
+
+	/* Update frame-pointer */
+	mov	fp, sp
+
+	/* Call board_init_f -- never returns */
+	mov	r4, r0
+	movhi	r2, %hi(board_init_f@h)
+	ori	r2, r2, %lo(board_init_f@h)
+	callr	r2
+
+	/*
+	 * NEVER RETURNS -- but branch to the _start just
+	 * in case ;-)
+	 */
+	br	_start
+
+	/*
+	 * relocate_code -- Nios2 handles the relocation above. But
+	 * the generic board code monkeys with the heap, stack, etc.
+	 * (it makes some assumptions that may not be appropriate
+	 * for Nios). Nevertheless, we capitulate here.
+	 *
+	 * We'll call the board_init_r from here since this isn't
+	 * supposed to return.
+	 *
+	 * void relocate_code(ulong sp, gd_t *global_data,
+	 *			ulong reloc_addr)
+	 *			__attribute__ ((noreturn));
+	 */
+	.text
+	.global relocate_code
+
+relocate_code:
+	mov	sp, r4		/* Set the new sp */
+	mov	r4, r5
+
+	/*
+	 * ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
+	 * and between __bss_start and __bss_end.
+	 */
+	movhi	r5, %hi(__bss_start)
+	ori	r5, r5, %lo(__bss_start)
+	movhi	r6, %hi(__bss_end)
+	ori	r6, r6, %lo(__bss_end)
+	beq	r5, r6, 5f
+
+4:	stw	r0, 0(r5)
+	addi	r5, r5, 4
+	bne	r5, r6, 4b
+5:
+
+	movhi	r8, %hi(board_init_r@h)
+	ori	r8, r8, %lo(board_init_r@h)
+	callr	r8
+	ret
diff --git a/roms/u-boot/arch/nios2/cpu/traps.c b/roms/u-boot/arch/nios2/cpu/traps.c
new file mode 100644
index 000000000..087a05097
--- /dev/null
+++ b/roms/u-boot/arch/nios2/cpu/traps.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <asm/ptrace.h>
+
+void trap_handler (struct pt_regs *regs)
+{
+	/* Just issue warning */
+	printf ("\n\n*** WARNING: unimplemented trap @ %08x\n\n",
+			regs->reg[29] - 4);
+}
+
+void soft_emulation (struct pt_regs *regs)
+{
+	/* TODO: Software emulation of mul/div etc. Until this is
+	 * implemented, generate warning and hang.
+	 */
+	printf ("\n\n*** ERROR: unimplemented instruction @ %08x\n",
+			regs->reg[29] - 4);
+	hang();
+}
diff --git a/roms/u-boot/arch/nios2/cpu/u-boot.lds b/roms/u-boot/arch/nios2/cpu/u-boot.lds
new file mode 100644
index 000000000..cbf54b461
--- /dev/null
+++ b/roms/u-boot/arch/nios2/cpu/u-boot.lds
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#include <config.h>
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = CONFIG_SYS_MONITOR_BASE;
+	.text :
+	{
+	  arch/nios2/cpu/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	/*
+	 * gp - Since we don't use gp for small data with option "-G0",
+	 * we will use gp as global data pointer. The _gp location is
+	 * not needed.
+	 */
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/*
+	 * _end - This is end of u-boot.bin image.
+	 * dtb will be appended here to make u-boot-dtb.bin
+	 */
+	_end = .;
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss (NOLOAD) :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss (NOLOAD) :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	__bss_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}