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| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/riscv/cpu/ax25/Kconfig | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/riscv/cpu/ax25/Kconfig')
| -rw-r--r-- | roms/u-boot/arch/riscv/cpu/ax25/Kconfig | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/roms/u-boot/arch/riscv/cpu/ax25/Kconfig b/roms/u-boot/arch/riscv/cpu/ax25/Kconfig new file mode 100644 index 000000000..941d963ec --- /dev/null +++ b/roms/u-boot/arch/riscv/cpu/ax25/Kconfig @@ -0,0 +1,24 @@ +config RISCV_NDS + bool + select ARCH_EARLY_INIT_R + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) + imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT + help + Run U-Boot on AndeStar V5 platforms and use some specific features + which are provided by Andes Technology AndeStar V5 families. + +if RISCV_NDS + +config RISCV_NDS_CACHE + bool "AndeStar V5 families specific cache support" + depends on RISCV_MMODE || SPL_RISCV_MMODE + help + Provide Andes Technology AndeStar V5 families specific cache support. + +endif |