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| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/riscv/include/asm/cache.h | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/riscv/include/asm/cache.h')
| -rw-r--r-- | roms/u-boot/arch/riscv/include/asm/cache.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/roms/u-boot/arch/riscv/include/asm/cache.h b/roms/u-boot/arch/riscv/include/asm/cache.h new file mode 100644 index 000000000..ec8fe201d --- /dev/null +++ b/roms/u-boot/arch/riscv/include/asm/cache.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <rick@andestech.com> + */ + +#ifndef _ASM_RISCV_CACHE_H +#define _ASM_RISCV_CACHE_H + +/* cache */ +void cache_flush(void); + +/* + * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. + * We use that value for aligning DMA buffers unless the board config has + * specified an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 32 +#endif + +#endif /* _ASM_RISCV_CACHE_H */ |