Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

1 files changed, 72 insertions, 0 deletions

diff --git a/roms/u-boot/arch/riscv/lib/cache.c b/roms/u-boot/arch/riscv/lib/cache.c
new file mode 100644
index 000000000..b1d42bcc2
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/cache.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+
+void invalidate_icache_all(void)
+{
+	asm volatile ("fence.i" ::: "memory");
+}
+
+__weak void flush_dcache_all(void)
+{
+}
+
+__weak void flush_dcache_range(unsigned long start, unsigned long end)
+{
+}
+
+void invalidate_icache_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * RISC-V does not have an instruction for invalidating parts of the
+	 * instruction cache. Invalidate all of it instead.
+	 */
+	invalidate_icache_all();
+}
+
+__weak void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+}
+
+void cache_flush(void)
+{
+	invalidate_icache_all();
+	flush_dcache_all();
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	invalidate_icache_range(addr, addr + size);
+	flush_dcache_range(addr, addr + size);
+}
+
+__weak void icache_enable(void)
+{
+}
+
+__weak void icache_disable(void)
+{
+}
+
+__weak int icache_status(void)
+{
+	return 0;
+}
+
+__weak void dcache_enable(void)
+{
+}
+
+__weak void dcache_disable(void)
+{
+}
+
+__weak int dcache_status(void)
+{
+	return 0;
+}