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| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c')
| -rw-r--r-- | roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c b/roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c new file mode 100644 index 000000000..805bf81f6 --- /dev/null +++ b/roms/u-boot/board/ti/ks2_evm/ddr3_k2l.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + */ + +#include <common.h> +#include "ddr3_cfg.h" +#include <asm/arch/ddr3.h> + +static struct pll_init_data ddr3_400 = DDR3_PLL_400; + +u32 ddr3_init(void) +{ + init_pll(&ddr3_400); + + /* No SO-DIMM, 2GB discreet DDR */ + printf("DRAM: 2 GiB\n"); + + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g); + + return 2; +} |