Add submodule dependency filesHEAD master

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
author: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> 2023-10-10 14:33:42 +0000
committer: Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> 2023-10-10 14:33:42 +0000
commit: af1a266670d040d2f4083ff309d732d648afba2a (patch)
tree: 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/doc/board
parent: e02cda008591317b1625707ff8e115a4841aa889 (diff)
98 files changed, 11908 insertions, 0 deletions
diff --git a/roms/u-boot/doc/board/AndesTech/adp-ag101p.rst b/roms/u-boot/doc/board/AndesTech/adp-ag101p.rst
new file mode 100644
index 000000000..879eba029
--- /dev/null
+++ b/roms/u-boot/doc/board/AndesTech/adp-ag101p.rst
@@ -0,0 +1,40 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+ADP-AG101P
+==========
+
+ADP-AG101P is the SoC with AG101 hardcore CPU.
+
+AG101P SoC
+----------
+
+AG101P is the mainline SoC produced by Andes Technology using N1213 CPU core
+with FPU and DDR contoller support.
+AG101P has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+
+Configurations
+--------------
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from SPI ROM and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag101p.h".
+
+Build and boot steps
+--------------------
+
+Build:
+
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101p_defconfig` in u-boot root to build the image.
+
+Burn U-Boot to SPI ROM
+----------------------
+
+This section will be added later.
diff --git a/roms/u-boot/doc/board/AndesTech/ax25-ae350.rst b/roms/u-boot/doc/board/AndesTech/ax25-ae350.rst
new file mode 100644
index 000000000..b46f427f4
--- /dev/null
+++ b/roms/u-boot/doc/board/AndesTech/ax25-ae350.rst
@@ -0,0 +1,524 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+AX25-AE350
+==========
+
+AE350 is the mainline SoC produced by Andes Technology using AX25 CPU core
+base on RISC-V architecture.
+
+AE350 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+AX25-AE350 is the SoC with AE350 hardcore CPU.
+
+AX25 is Andes CPU IP to adopt RISC-V architecture.
+
+AX25 Features
+-------------
+
+CPU Core
+ - 5-stage in-order execution pipeline
+ - Hardware Multiplier
+      - radix-2/radix-4/radix-16/radix-256/fast
+ - Hardware Divider
+ - Optional branch prediction
+ - Machine mode and optional user mode
+ - Optional performance monitoring
+
+ISA
+ - RV64I base integer instructions
+ - RVC for 16-bit compressed instructions
+ - RVM for multiplication and division instructions
+
+Memory subsystem
+ - I & D local memory
+      - Size: 4KB to 16MB
+ - Memory subsyetem soft-error protection
+      - Protection scheme: parity-checking or error-checking-and-correction (ECC)
+      - Automatic hardware error correction
+
+Bus
+ - Interface Protocol
+      - Synchronous AHB (32-bit/64-bit data-width), or
+      - Synchronous AXI4 (64-bit data-width)
+
+Power management
+ - Wait for interrupt (WFI) mode
+
+Debug
+ - Configurable number of breakpoints: 2/4/8
+ - External Debug Module
+      - AHB slave port
+ - External JTAG debug transport module
+
+Platform Level Interrupt Controller (PLIC)
+ - AHB slave port
+ - Configurable number of interrupts: 1-1023
+ - Configurable number of interrupt priorities: 3/7/15/63/127/255
+ - Configurable number of targets:  1-16
+ - Preempted interrupt priority stack
+
+Build and boot steps
+--------------------
+
+Build:
+
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make ae350_rv[32|64]_defconfig` in u-boot root to build the image for
+   32 or 64 bit.
+
+Verification:
+
+1. startup
+2. relocation
+3. timer driver
+4. uart driver
+5. mac driver
+6. mmc driver
+7. spi driver
+
+Steps
+-----
+
+1. Ping a server by mac driver
+2. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver
+3. Burn this u-boot image to spi rom by spi driver
+4. Re-boot u-boot from spi flash with power off and power on
+
+Messages of U-Boot boot on AE350 board
+--------------------------------------
+
+.. code-block:: none
+
+   U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800)
+
+   DRAM:  1 GiB
+   MMC:   mmc@f0e00000: 0
+   SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+   In:    serial@f0300000
+   Out:   serial@f0300000
+   Err:   serial@f0300000
+   Net:
+   Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10
+   eth0: mac@e0100000
+
+   RISC-V # version
+   U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800)
+
+   riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0
+   GNU ld (GNU Binutils) 2.29
+
+   RISC-V # setenv ipaddr 10.0.4.200 ;
+   RISC-V # setenv serverip 10.0.4.97 ;
+   RISC-V # ping 10.0.4.97 ;
+   Using mac@e0100000 device
+   host 10.0.4.97 is alive
+
+   RISC-V # mmc rescan
+   RISC-V # fatls mmc 0:1
+      318907   u-boot-ae350-64.bin
+        1252   hello_world_ae350_32.bin
+      328787   u-boot-ae350-32.bin
+
+   3 file(s), 0 dir(s)
+
+   RISC-V # sf probe 0:0 50000000 0
+   SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+
+   RISC-V # sf test 0x100000 0x1000
+   SPI flash test:
+   0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
+   1 check: 29 ticks, 137 KiB/s 1.096 Mbps
+   2 write: 40 ticks, 100 KiB/s 0.800 Mbps
+   3 read: 20 ticks, 200 KiB/s 1.600 Mbps
+   Test passed
+   0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
+   1 check: 29 ticks, 137 KiB/s 1.096 Mbps
+   2 write: 40 ticks, 100 KiB/s 0.800 Mbps
+   3 read: 20 ticks, 200 KiB/s 1.600 Mbps
+
+   RISC-V # fatload mmc 0:1 0x600000 u-boot-ae350-32.bin
+   reading u-boot-ae350-32.bin
+   328787 bytes read in 324 ms (990.2 KiB/s)
+
+   RISC-V # sf erase 0x0 0x51000
+   SF: 331776 bytes @ 0x0 Erased: OK
+
+   RISC-V # sf write 0x600000 0x0 0x50453
+   device 0 offset 0x0, size 0x50453
+   SF: 328787 bytes @ 0x0 Written: OK
+
+   RISC-V # crc32 0x600000 0x50453
+   crc32 for 00600000 ... 00650452 ==> 692dc44a
+
+   RISC-V # crc32 0x80000000 0x50453
+   crc32 for 80000000 ... 80050452 ==> 692dc44a
+   RISC-V #
+
+   *** power-off and power-on, this U-Boot is booted from spi flash ***
+
+   U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800)
+
+   DRAM:  1 GiB
+   MMC:   mmc@f0e00000: 0
+   SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+   In:    serial@f0300000
+   Out:   serial@f0300000
+   Err:   serial@f0300000
+   Net:
+   Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5
+   eth0: mac@e0100000
+   RISC-V #
+
+
+Boot bbl and riscv-linux via U-Boot on QEMU
+-------------------------------------------
+
+1. Build riscv-linux
+2. Build bbl and riscv-linux with --with-payload
+3. Prepare ae350.dtb
+4. Creating OS-kernel images
+
+.. code-block:: none
+
+   ./mkimage -A riscv -O linux -T kernel -C none -a 0x0000 -e 0x0000 -d bbl.bin bootmImage-bbl.bin
+   Image Name:
+   Created:      Tue Mar 13 10:06:42 2018
+   Image Type:   RISC-V Linux Kernel Image (uncompressed)
+   Data Size:    17901204 Bytes = 17481.64 KiB = 17.07 MiB
+   Load Address: 00000000
+   Entry Point:  00000000
+
+5. Copy bootmImage-bbl.bin and ae350.dtb to qemu sd card image
+6. Message of booting riscv-linux from bbl via u-boot on qemu
+
+.. code-block:: none
+
+   U-Boot 2018.03-rc4-00031-g2631273 (Mar 13 2018 - 15:02:55 +0800)
+
+   DRAM:  1 GiB
+   main-loop: WARNING: I/O thread spun for 1000 iterations
+   MMC:   mmc@f0e00000: 0
+   Loading Environment from SPI Flash... *** Warning - spi_flash_probe_bus_cs() failed, using default environment
+
+   Failed (-22)
+   In:    serial@f0300000
+   Out:   serial@f0300000
+   Err:   serial@f0300000
+   Net:
+   Warning: mac@e0100000 (eth0) using random MAC address - 02:00:00:00:00:00
+   eth0: mac@e0100000
+   RISC-V # mmc rescan
+   RISC-V # mmc part
+
+   Partition Map for MMC device 0  --   Partition Type: DOS
+
+   Part    Start Sector    Num Sectors     UUID            Type
+   RISC-V # fatls mmc 0:0
+    17901268   bootmImage-bbl.bin
+        1954   ae2xx.dtb
+
+   2 file(s), 0 dir(s)
+
+   RISC-V # fatload mmc 0:0 0x00600000 bootmImage-bbl.bin
+   17901268 bytes read in 4642 ms (3.7 MiB/s)
+   RISC-V # fatload mmc 0:0 0x2000000 ae350.dtb
+   1954 bytes read in 1 ms (1.9 MiB/s)
+   RISC-V # setenv bootm_size 0x2000000
+   RISC-V # setenv fdt_high 0x1f00000
+   RISC-V # bootm 0x00600000 - 0x2000000
+   ## Booting kernel from Legacy Image at 00600000 ...
+      Image Name:
+      Image Type:   RISC-V Linux Kernel Image (uncompressed)
+      Data Size:    17901204 Bytes = 17.1 MiB
+      Load Address: 00000000
+      Entry Point:  00000000
+      Verifying Checksum ... OK
+   ## Flattened Device Tree blob at 02000000
+      Booting using the fdt blob at 0x2000000
+      Loading Kernel Image ... OK
+      Loading Device Tree to 0000000001efc000, end 0000000001eff7a1 ... OK
+   [    0.000000] OF: fdt: Ignoring memory range 0x0 - 0x200000
+   [    0.000000] Linux version 4.14.0-00046-gf3e439f-dirty (rick@atcsqa06) (gcc version 7.1.1 20170509 (GCC)) #1 Tue Jan 9 16:34:25 CST 2018
+   [    0.000000] bootconsole [early0] enabled
+   [    0.000000] Initial ramdisk at: 0xffffffe000016a98 (12267008 bytes)
+   [    0.000000] Zone ranges:
+   [    0.000000]   DMA      [mem 0x0000000000200000-0x000000007fffffff]
+   [    0.000000]   Normal   empty
+   [    0.000000] Movable zone start for each node
+   [    0.000000] Early memory node ranges
+   [    0.000000]   node   0: [mem 0x0000000000200000-0x000000007fffffff]
+   [    0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x000000007fffffff]
+   [    0.000000] elf_hwcap is 0x112d
+   [    0.000000] random: fast init done
+   [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 516615
+   [    0.000000] Kernel command line: console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7
+   [    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
+   [    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
+   [    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
+   [    0.000000] Sorting __ex_table...
+   [    0.000000] Memory: 2047832K/2095104K available (1856K kernel code, 204K rwdata, 532K rodata, 12076K init, 756K bss, 47272K reserved, 0K cma-reserved)
+   [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
+   [    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+   [    0.000000] riscv,cpu_intc,0: 64 local interrupts mapped
+   [    0.000000] riscv,plic0,e4000000: mapped 31 interrupts to 1/2 handlers
+   [    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns
+   [    0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000)
+   [    0.000000] pid_max: default: 32768 minimum: 301
+   [    0.004000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
+   [    0.004000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
+   [    0.056000] devtmpfs: initialized
+   [    0.060000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+   [    0.064000] futex hash table entries: 256 (order: 0, 6144 bytes)
+   [    0.068000] NET: Registered protocol family 16
+   [    0.080000] vgaarb: loaded
+   [    0.084000] clocksource: Switched to clocksource riscv_clocksource
+   [    0.088000] NET: Registered protocol family 2
+   [    0.092000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
+   [    0.096000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)
+   [    0.096000] TCP: Hash tables configured (established 16384 bind 16384)
+   [    0.100000] UDP hash table entries: 1024 (order: 3, 32768 bytes)
+   [    0.100000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
+   [    0.104000] NET: Registered protocol family 1
+   [    0.616000] Unpacking initramfs...
+   [    1.220000] workingset: timestamp_bits=62 max_order=19 bucket_order=0
+   [    1.244000] io scheduler noop registered
+   [    1.244000] io scheduler cfq registered (default)
+   [    1.244000] io scheduler mq-deadline registered
+   [    1.248000] io scheduler kyber registered
+   [    1.360000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+   [    1.368000] console [ttyS0] disabled
+   [    1.372000] f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 10, base_baud = 1228800) is a 16550A
+   [    1.392000] console [ttyS0] enabled
+   [    1.392000] ftmac100: Loading version 0.2 ...
+   [    1.396000] ftmac100 e0100000.mac eth0: irq 8, mapped at ffffffd002005000
+   [    1.400000] ftmac100 e0100000.mac eth0: generated random MAC address 6e:ac:c3:92:36:c0
+   [    1.404000] IR NEC protocol handler initialized
+   [    1.404000] IR RC5(x/sz) protocol handler initialized
+   [    1.404000] IR RC6 protocol handler initialized
+   [    1.404000] IR JVC protocol handler initialized
+   [    1.408000] IR Sony protocol handler initialized
+   [    1.408000] IR SANYO protocol handler initialized
+   [    1.408000] IR Sharp protocol handler initialized
+   [    1.408000] IR MCE Keyboard/mouse protocol handler initialized
+   [    1.412000] IR XMP protocol handler initialized
+   [    1.456000] ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ
+   [    1.464000] bootconsole [early0] uses init memory and must be disabled even before the real one is ready
+   [    1.464000] bootconsole [early0] disabled
+   [    1.508000] Freeing unused kernel memory: 12076K
+   [    1.512000] This architecture does not have kernel memory protection.
+   [    1.520000] mmc0: new SD card at address 4567
+   [    1.524000] mmcblk0: mmc0:4567 QEMU! 20.0 MiB
+   [    1.844000]  mmcblk0:
+   Wed Dec  1 10:00:00 CST 2010
+   / #
+
+
+Running U-Boot SPL
+------------------
+The U-Boot SPL will boot in M mode and load the FIT image which include
+OpenSBI and U-Boot proper images. After loading progress, it will jump
+to OpenSBI first and then U-Boot proper which will run in S mode.
+
+
+How to build U-Boot SPL
+-----------------------
+Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be
+cloned and build for AE350 as below:
+
+.. code-block:: none
+
+        git clone https://github.com/riscv/opensbi.git
+        cd opensbi
+        make PLATFORM=andes/ae350
+
+Copy OpenSBI FW_DYNAMIC image (build/platform/andes/ae350/firmware/fw_dynamic.bin)
+into U-Boot root directory
+
+
+How to build U-Boot SPL booting from RAM
+----------------------------------------
+With ae350_rv[32|64]_spl_defconfigs:
+
+U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode
+and then load FIT image from RAM device on AE350.
+
+
+How to build U-Boot SPL booting from ROM
+----------------------------------------
+With ae350_rv[32|64]_spl_xip_defconfigs:
+
+U-Boot SPL can be burned into SPI flash and run in flash in machine mode
+and then load FIT image from SPI flash or MMC device on AE350.
+
+
+Messages of U-Boot SPL boots Kernel on AE350 board
+--------------------------------------------------
+
+.. code-block:: none
+
+    U-Boot SPL 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800)
+    Trying to boot from RAM
+
+    OpenSBI v0.5-1-gdd8ef28 (Nov 14 2019 11:08:39)
+       ____                    _____ ____ _____
+      / __ \                  / ____|  _ \_   _|
+     | |  | |_ __   ___ _ __ | (___ | |_) || |
+     | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
+     | |__| | |_) |  __/ | | |____) | |_) || |_
+      \____/| .__/ \___|_| |_|_____/|____/_____|
+            | |
+            |_|
+
+    Platform Name          : Andes AE350
+    Platform HART Features : RV64ACIMSUX
+    Platform Max HARTs     : 4
+    Current Hart           : 0
+    Firmware Base          : 0x0
+    Firmware Size          : 84 KB
+    Runtime SBI Version    : 0.2
+
+    PMP0: 0x0000000000000000-0x000000000001ffff (A)
+    PMP1: 0x0000000000000000-0x00000001ffffffff (A,R,W,X)
+
+
+    U-Boot 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800)
+
+    DRAM:  1 GiB
+    Flash: 64 MiB
+    MMC:   mmc@f0e00000: 0
+    Loading Environment from SPI Flash... SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+    OK
+    In:    serial@f0300000
+    Out:   serial@f0300000
+    Err:   serial@f0300000
+    Net:   no alias for ethernet0
+
+    Warning: mac@e0100000 (eth0) using random MAC address - a2:ae:93:7b:cc:8f
+    eth0: mac@e0100000
+    Hit any key to stop autoboot:  0
+    6455 bytes read in 31 ms (203.1 KiB/s)
+    20421684 bytes read in 8647 ms (2.3 MiB/s)
+    ## Booting kernel from Legacy Image at 00600000 ...
+       Image Name:
+       Image Type:   RISC-V Linux Kernel Image (uncompressed)
+       Data Size:    20421620 Bytes = 19.5 MiB
+       Load Address: 00200000
+       Entry Point:  00200000
+       Verifying Checksum ... OK
+    ## Flattened Device Tree blob at 20000000
+       Booting using the fdt blob at 0x20000000
+       Loading Kernel Image
+       Loading Device Tree to 000000001effb000, end 000000001efff936 ... OK
+
+    Starting kernel ...
+
+    OF: fdt: Ignoring memory range 0x0 - 0x200000
+    Linux version 4.17.0-00253-g49136e10bcb2 (sqa@atcsqa07) (gcc version 7.3.0 (2019-04-06_nds64le-linux-glibc-v5_experimental)) #1 SMP PREEMPT Sat Apr 6 23:41:49 CST 2019
+    bootconsole [early0] enabled
+    Initial ramdisk at: 0x        (ptrval) (13665712 bytes)
+    Zone ranges:
+      DMA32    [mem 0x0000000000200000-0x000000003fffffff]
+      Normal   empty
+    Movable zone start for each node
+    Early memory node ranges
+      node   0: [mem 0x0000000000200000-0x000000003fffffff]
+    Initmem setup node 0 [mem 0x0000000000200000-0x000000003fffffff]
+    software IO TLB [mem 0x3b1f8000-0x3f1f8000] (64MB) mapped at [        (ptrval)-        (ptrval)]
+    elf_platform is rv64i2p0m2p0a2p0c2p0xv5-0p0
+    compatible privileged spec version 1.10
+    percpu: Embedded 16 pages/cpu @        (ptrval) s28184 r8192 d29160 u65536
+    Built 1 zonelists, mobility grouping on.  Total pages: 258055
+    Kernel command line: console=ttyS0,38400n8 debug loglevel=7
+    log_buf_len individual max cpu contribution: 4096 bytes
+    log_buf_len total cpu_extra contributions: 12288 bytes
+    log_buf_len min size: 16384 bytes
+    log_buf_len: 32768 bytes
+    early log buf free: 14608(89%)
+    Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
+    Inode-cache hash table entries: 65536 (order: 7, 524288 bytes)
+    Sorting __ex_table...
+    Memory: 944428K/1046528K available (3979K kernel code, 246K rwdata, 1490K rodata, 13523K init, 688K bss, 102100K reserved, 0K cma-reserved)
+    SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+    Preemptible hierarchical RCU implementation.
+            Tasks RCU enabled.
+    NR_IRQS: 72, nr_irqs: 72, preallocated irqs: 0
+    riscv,cpu_intc,0: 64 local interrupts mapped
+    riscv,cpu_intc,1: 64 local interrupts mapped
+    riscv,cpu_intc,2: 64 local interrupts mapped
+    riscv,cpu_intc,3: 64 local interrupts mapped
+    riscv,plic0,e4000000: mapped 71 interrupts to 8/8 handlers
+    clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1bacf917bf, max_idle_ns: 881590412290 ns
+    sched_clock: 64 bits at 60MHz, resolution 16ns, wraps every 4398046511098ns
+    Console: colour dummy device 40x30
+    Calibrating delay loop (skipped), value calculated using timer frequency.. 120.00 BogoMIPS (lpj=600000)
+    pid_max: default: 32768 minimum: 301
+    Mount-cache hash table entries: 2048 (order: 2, 16384 bytes)
+    Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes)
+    Hierarchical SRCU implementation.
+    smp: Bringing up secondary CPUs ...
+    CPU0: online
+    CPU2: online
+    CPU3: online
+    smp: Brought up 1 node, 4 CPUs
+    devtmpfs: initialized
+    random: get_random_u32 called from bucket_table_alloc+0x198/0x1d8 with crng_init=0
+    clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
+    futex hash table entries: 1024 (order: 4, 65536 bytes)
+    NET: Registered protocol family 16
+    Advanced Linux Sound Architecture Driver Initialized.
+    clocksource: Switched to clocksource riscv_clocksource
+    NET: Registered protocol family 2
+    tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes)
+    TCP established hash table entries: 8192 (order: 4, 65536 bytes)
+    TCP bind hash table entries: 8192 (order: 5, 131072 bytes)
+    TCP: Hash tables configured (established 8192 bind 8192)
+    UDP hash table entries: 512 (order: 2, 16384 bytes)
+    UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
+    NET: Registered protocol family 1
+    RPC: Registered named UNIX socket transport module.
+    RPC: Registered udp transport module.
+    RPC: Registered tcp transport module.
+    RPC: Registered tcp NFSv4.1 backchannel transport module.
+    Unpacking initramfs...
+    workingset: timestamp_bits=62 max_order=18 bucket_order=0
+    NFS: Registering the id_resolver key type
+    Key type id_resolver registered
+    Key type id_legacy registered
+    nfs4filelayout_init: NFSv4 File Layout Driver Registering...
+    io scheduler noop registered
+    io scheduler cfq registered (default)
+    io scheduler mq-deadline registered
+    io scheduler kyber registered
+    Console: switching to colour frame buffer device 40x30
+    Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+    console [ttyS0] disabled
+    f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 20, base_baud = 1228800) is a 16550A
+    console [ttyS0] enabled
+    console [ttyS0] enabled
+    bootconsole [early0] disabled
+    bootconsole [early0] disabled
+    loop: module loaded
+    tun: Universal TUN/TAP device driver, 1.6
+    ftmac100: Loading version 0.2 ...
+    ftmac100 e0100000.mac eth0: irq 21, mapped at         (ptrval)
+    ftmac100 e0100000.mac eth0: generated random MAC address 4e:fd:bd:f3:04:fc
+    ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ
+    mmc0: new SDHC card at address d555
+    ftssp010 card registered!
+    mmcblk0: mmc0:d555 SD04G 3.79 GiB
+    NET: Registered protocol family 10
+     mmcblk0: p1
+    Segment Routing with IPv6
+    sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+    NET: Registered protocol family 17
+    NET: Registered protocol family 15
+    ALSA device list:
+      #0: ftssp_ac97 controller
+    Freeing unused kernel memory: 13520K
+    This architecture does not have kernel memory protection.
+    Sysinit starting
+    Sat Apr  6 23:33:53 CST 2019
+    nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
+
+    ~ #
diff --git a/roms/u-boot/doc/board/AndesTech/index.rst b/roms/u-boot/doc/board/AndesTech/index.rst
new file mode 100644
index 000000000..d8f7d155f
--- /dev/null
+++ b/roms/u-boot/doc/board/AndesTech/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Andes Tech
+==========
+
+.. toctree::
+   :maxdepth: 2
+
+   adp-ag101p
+   ax25-ae350
diff --git a/roms/u-boot/doc/board/actions/cubieboard7.rst b/roms/u-boot/doc/board/actions/cubieboard7.rst
new file mode 100644
index 000000000..74f2b12e4
--- /dev/null
+++ b/roms/u-boot/doc/board/actions/cubieboard7.rst
@@ -0,0 +1,114 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
+
+CUBIEBOARD7
+===========
+
+About this
+----------
+
+This document describes build and flash steps for Actions S700 SoC based Cubieboard7
+board.
+
+Cubieboard7 initial configuration
+---------------------------------
+
+Default Cubieboard7 comes with pre-installed Android where U-Boot is configured with
+a bootdelay of 0, entering a prompt by pressing keys does not seem to work.
+
+Though, one can enter ADFU mode and flash debian image(from host machine) where
+getting into u-boot prompt is easy.
+
+Enter ADFU Mode
+----------------
+
+Before write the firmware, let the development board entering the ADFU mode: insert
+one end of the USB cable to the PC, press and hold the ADFU button, and then connect
+the other end of the USB cable to the Mini USB port of the development board, release
+the ADFU button, after connecting it will enter the ADFU mode.
+
+Check whether entered ADFU Mode
+--------------------------------
+
+The user needs to run the following command on the PC side to check if the ADFU
+device is detected. ID realted to "Actions Semiconductor Co., Ltd"  means that
+the PC side has been correctly detected ADFU device, the development board
+also enter into the ADFU mode.
+
+.. code-block:: none
+
+   $ lsusb
+   Bus 001 Device 005: ID 04f2:b2eb Chicony Electronics Co., Ltd
+   Bus 001 Device 004: ID 0a5c:21e6 Broadcom Corp. BCM20702 Bluetooth 4.0 [ThinkPad]
+   Bus 001 Device 003: ID 046d:c534 Logitech, Inc. Unifying Receiver
+   Bus 001 Device 002: ID 8087:0024 Intel Corp. Integrated Rate Matching Hub
+   Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
+   Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
+   Bus 003 Device 013: ID 10d6:10d6 Actions Semiconductor Co., Ltd
+   Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
+
+Flashing debian image
+---------------------
+
+.. code-block:: none
+
+   $ sudo ./ActionsFWU.py --fw=debian-stretch-desktop-cb7-emmc-v2.0.fw
+   ActionsFWU.py	: 1.0.150828.0830
+   libScript.so    : 2.3.150825.0951
+   libFileSystem.so: 2.3.150825.0952
+   libProduction.so: 2.3.150915.1527
+   =====burn all partition====
+   FW_VER: 3.10.37.180608
+   3% DOWNLOAD ADFUDEC ...
+   5% DOWNLOAD BOOT PARA ...
+   7% SWITCH ADFUDEC ...
+   12% DOWNLOAD BL31 ...
+   13% DOWNLOAD BL32 ...
+   15% DOWNLOAD VMLINUX ...
+   20% DOWNLOAD INITRD ...
+   24% DOWNLOAD FDT ...
+   27% DOWNLOAD ADFUS ...
+   30% SWITCH ADFUS ...
+   32% DOWNLOAD MBR ...
+   35% DOWNLOAD PARTITIONS ...
+   WRITE_MBRC_PARTITION
+   35% write p0 size = 2048 : ok
+   WRITE_BOOT_PARTITION
+   35% write p1 size = 2048 : ok
+   WRITE_MISC_PARTITION
+   36% write p2 size = 98304 : ok
+   WRITE_SYSTEM_PARTITION
+   94% write p3 size = 4608000 : ok
+   FORMAT_SWAP_PARTITION
+   94% write p4 size = 20480 : ok
+   95% TRANSFER OVER ...
+   Firmware upgrade successfully!
+
+Debian image can be downloaded from here[1].
+
+Once debian image is flashed, one can get into u-boot prompt by pressing any key and from
+there run ums command(make sure, usb cable is connected between host and target):
+
+.. code-block:: none
+
+   owl> ums 0 mmc 1
+
+Above command would mount debian image partition on host machine.
+
+Building U-BOOT proper image
+----------------------------
+
+.. code-block:: none
+
+   $ make clean
+   $ export CROSS_COMPILE=aarch64-linux-gnu-
+   $ make cubieboard7_defconfig
+   $ make u-boot-dtb.img -j16
+
+u-boot-dtb.img can now be flashed to debian image partition mounted on host machine.
+
+.. code-block:: none
+
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdb bs=1024 seek=3072
+
+[1]: https://pan.baidu.com/s/1uawPr0Jao2HgWFLZCLzHAg#list/path=%2FCubieBoard_Download%2FBoard%2FCubieBoard7%2F%E6%96%B9%E7%B3%96%E6%96%B9%E6%A1%88%E5%BC%80%E5%8F%91%E8%B5%84%E6%96%99%2FImage%2FDebian%2FV2.1-test&parentPath=%2F
diff --git a/roms/u-boot/doc/board/actions/index.rst b/roms/u-boot/doc/board/actions/index.rst
new file mode 100644
index 000000000..c59687915
--- /dev/null
+++ b/roms/u-boot/doc/board/actions/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
+
+Actions
+========
+
+.. toctree::
+   :maxdepth: 2
+
+   cubieboard7
diff --git a/roms/u-boot/doc/board/advantech/imx8qm-rom7720-a1.rst b/roms/u-boot/doc/board/advantech/imx8qm-rom7720-a1.rst
new file mode 100644
index 000000000..bd4be1dbe
--- /dev/null
+++ b/roms/u-boot/doc/board/advantech/imx8qm-rom7720-a1.rst
@@ -0,0 +1,75 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the NXP i.MX8QM ROM 7720a1 board
+===========================================
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Get imx-mkimage
+- Build U-Boot
+- Build imx-mkimage
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+.. code-block:: bash
+
+     $ git clone https://source.codeaurora.org/external/imx/imx-atf
+     $ cd imx-atf/
+     $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
+     $ make PLAT=imx8qm bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
+     $ chmod +x imx-sc-firmware-1.1.bin
+     $ ./imx-sc-firmware-1.1.bin
+     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+     $ chmod +x firmware-imx-8.0.bin
+     $ ./firmware-imx-8.0.bin
+
+Or use this to avoid running random scripts from the internet,
+but note that you must agree to the license the script displays:
+
+.. code-block:: bash
+
+     $ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1
+     $ tar -xf imx-sc-firmware-1.1.tar.bz2
+     $ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir)
+
+     $ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1
+     $ tar -xf firmware-imx-8.0.tar.bz2
+     $ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+     $ export ATF_LOAD_ADDR=0x80000000
+     $ export BL33_LOAD_ADDR=0x80020000
+     $ make imx8qm_rom7720_a1_4G_defconfig
+     $ make u-boot.bin
+     $ make flash.bin
+
+Flash the binary into the SD card
+---------------------------------
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+.. code-block:: bash
+
+    $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
+
+Boot
+----
+
+Set Boot switch SW2: 1100.
diff --git a/roms/u-boot/doc/board/advantech/index.rst b/roms/u-boot/doc/board/advantech/index.rst
new file mode 100644
index 000000000..e9b198c5c
--- /dev/null
+++ b/roms/u-boot/doc/board/advantech/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Advantech
+=========
+
+.. toctree::
+   :maxdepth: 2
+
+   imx8qm-rom7720-a1.rst
diff --git a/roms/u-boot/doc/board/amlogic/beelink-gtking.rst b/roms/u-boot/doc/board/amlogic/beelink-gtking.rst
new file mode 100644
index 000000000..56ce2cb27
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/beelink-gtking.rst
@@ -0,0 +1,115 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Beelink GT-King
+==========================
+
+The Shenzen AZW (Beelink) GT-King is based on the Amlogic W400 reference
+board with an S922X-H chip.
+
+- 4GB LPDDR4 RAM
+- 64GB eMMC storage
+- 10/100/1000 Base-T Ethernet
+- AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.1)
+- HDMI 2.1 video
+- S/PDIF optical output
+- Analogue audio output
+- 1x USB 2.0 port
+- 2x USB 3.0 ports
+- IR receiver
+- 1x micro SD card slot
+
+Beelink do not provide public schematics, but have been willing
+to share them with known distro developers on request.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make beelink-gtking_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic does not provide sources for the firmware and for tools needed
+to create the bootloader image. Beelink have provided the Amlogic "SDK"
+in their forums, but the u-boot sources included result in 2GB RAM being
+detected. The following FIPs were generated with newer private sources
+and give correct (4GB) RAM detection:
+
+https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+
+NB: Beelink use a common board config for GT-King, GT-King Pro and the
+GS-King-X model, hence the "beelink-s922x" name.
+
+.. code-block:: bash
+
+    $ wget https://github.com/LibreELEC/amlogic-boot-fip/archive/master.zip
+    $ unzip master.zip
+    $ export FIPDIR=$PWD/amlogic-boot-fip/beelink-s922x
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+    $ cp $FIPDIR/* fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl2.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/acs.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+    				--output fip/bl30_new.bin.g12a.enc \
+    				--level v3
+    $ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+    				--output fip/bl30_new.bin.enc \
+    				--level v3 --type bl30
+    $ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+    				--output fip/bl31.img.enc \
+    				--level v3 --type bl31
+    $ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+    				--output fip/bl33.bin.enc \
+    				--level v3 --type bl33
+    $ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+    				--output fip/bl2.n.bin.sig
+    $ fip/aml_encrypt_g12b --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc \
+    		--ddrfw1 fip/ddr4_1d.fw \
+    		--ddrfw2 fip/ddr4_2d.fw \
+    		--ddrfw3 fip/ddr3_1d.fw \
+    		--ddrfw4 fip/piei.fw \
+    		--ddrfw5 fip/lpddr4_1d.fw \
+    		--ddrfw6 fip/lpddr4_2d.fw \
+    		--ddrfw7 fip/diag_lpddr4.fw \
+    		--ddrfw8 fip/aml_ddr.fw \
+    		--level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/beelink-gtkingpro.rst b/roms/u-boot/doc/board/amlogic/beelink-gtkingpro.rst
new file mode 100644
index 000000000..d75035136
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/beelink-gtkingpro.rst
@@ -0,0 +1,116 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Beelink GT-King Pro
+==============================
+
+The Shenzen AZW (Beelink) GT-King Pro is based on the Amlogic W400 reference
+board with an S922X-H chip.
+
+- 4GB LPDDR4 RAM
+- 64GB eMMC storage
+- 10/100/1000 Base-T Ethernet
+- AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.1)
+- HDMI 2.1 video
+- Analogue audio output
+- 1x RS232 port
+- 2x USB 2.0 port
+- 2x USB 3.0 ports
+- IR receiver
+- 1x SD card slot
+- 1x Power on/off button
+
+Beelink do not provide public schematics, but have been willing
+to share them with known distro developers on request.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make beelink-gtkingpro_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic does not provide sources for the firmware and for tools needed
+to create the bootloader image. Beelink have provided the Amlogic "SDK"
+in their forums, but the u-boot sources included result in 2GB RAM being
+detected. The following FIPs were generated with newer private sources
+and give correct (4GB) RAM detection:
+
+https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+
+NB: Beelink use a common board config for GT-King, GT-King Pro and the
+GS-King-X model, hence the "beelink-s922x" name.
+
+.. code-block:: bash
+
+    $ wget https://github.com/LibreELEC/amlogic-boot-fip/archive/master.zip
+    $ unzip master.zip
+    $ export FIPDIR=$PWD/amlogic-boot-fip/beelink-s922x
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+    $ cp $FIPDIR/* fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl2.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/acs.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+    				--output fip/bl30_new.bin.g12a.enc \
+    				--level v3
+    $ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+    				--output fip/bl30_new.bin.enc \
+    				--level v3 --type bl30
+    $ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+    				--output fip/bl31.img.enc \
+    				--level v3 --type bl31
+    $ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+    				--output fip/bl33.bin.enc \
+    				--level v3 --type bl33
+    $ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+    				--output fip/bl2.n.bin.sig
+    $ fip/aml_encrypt_g12b --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc \
+    		--ddrfw1 fip/ddr4_1d.fw \
+    		--ddrfw2 fip/ddr4_2d.fw \
+    		--ddrfw3 fip/ddr3_1d.fw \
+    		--ddrfw4 fip/piei.fw \
+    		--ddrfw5 fip/lpddr4_1d.fw \
+    		--ddrfw6 fip/lpddr4_2d.fw \
+    		--ddrfw7 fip/diag_lpddr4.fw \
+    		--ddrfw8 fip/aml_ddr.fw \
+    		--level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/index.rst b/roms/u-boot/doc/board/amlogic/index.rst
new file mode 100644
index 000000000..8da7afddb
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/index.rst
@@ -0,0 +1,103 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Amlogic
+=======
+
+Hardware Support Matrix
+-----------------------
+
+An up-do-date matrix is also available on: http://linux-meson.com
+
+This matrix concerns the actual source code version.
+
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+|                            	| S905      | S905X           | S912         | A113X      | S905X2     | S922X       | S905X3       |
+|        			|	    | S805X   	      | S905D        |	          | S905D2     | A311D       | S905D3       |
+|        			|	    |		      |	             |            | S905Y2     |	     |              |
++===============================+===========+=================+==============+============+============+=============+==============+
+| Boards                       	| Odroid-C2 | P212            | Khadas VIM2  | S400       | U200       | Odroid-N2   | SEI610       |
+|        			| Nanopi-K2 | Khadas-VIM      | Libretech-PC |	          | SEI510     | Khadas-VIM3 | Khadas-VIM3L |
+|        			| P200	    | LibreTech-CC v1 |	WeTek Core2  |	          |            | GT-King/Pro | Odroid-C4    |
+|        			| P201	    | LibreTech-AC v2 |	             |	          |            |             |              |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| UART                       	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Pinctrl/GPIO               	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Clock Control              	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| PWM                        	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Reset Control              	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Infrared Decoder           	| No        | No              | No           | No         | No         | No          | No           |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Ethernet                   	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Multi-core                 	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Fuse access                	| **Yes**   | **Yes**         |**Yes**       |**Yes**     |**Yes**     |**Yes**      | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| SPI (FC)                  	| **Yes**   | **Yes**         | **Yes**      | **Yes**    |**Yes**     | **Yes**     | No           |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| SPI (CC)                   	| No        | No              | No           | No         | No         | No          | No           |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| I2C                       	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| USB                       	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| USB OTG                  	| No        | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| eMMC                      	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| SDCard                    	| **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| NAND                      	| No        | No              | No           | No         | No         | No          | No           |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| ADC                       	| **Yes**   | **Yes**         | **Yes**      | No         | No         | No          | No           |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| CVBS Output                	| **Yes**   | **Yes**         | **Yes**      | *N/A*      | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| HDMI Output                	| **Yes**   | **Yes**         | **Yes**      | *N/A*      | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| CEC                        	| No        | No              | No           | *N/A*      | No         | No          | No           |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Thermal Sensor             	| No        | No              | No           | No         | No         | No          | No           |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| LCD/LVDS Output            	| No        | *N/A*           | No           | No         | No         | No          | No           |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| MIPI DSI Output            	| *N/A*     | *N/A*           | *N/A*        | No         | No         | No          | No           |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| SoC (version) information     | **Yes**   | **Yes**         | **Yes**      | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| PCIe (+NVMe)                  | *N/A*     | *N/A*           | *N/A*        | **Yes**    | **Yes**    | **Yes**     | **Yes**      |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+
+Board Documentation
+-------------------
+
+.. toctree::
+   :maxdepth: 1
+
+   beelink-gtking
+   beelink-gtkingpro
+   khadas-vim2
+   khadas-vim3l
+   khadas-vim3
+   khadas-vim
+   libretech-ac
+   libretech-cc
+   nanopi-k2
+   odroid-c2
+   odroid-c4
+   odroid-n2
+   p200
+   p201
+   p212
+   q200
+   s400
+   sei510
+   sei610
+   u200
+   wetek-core2
+   w400
diff --git a/roms/u-boot/doc/board/amlogic/khadas-vim.rst b/roms/u-boot/doc/board/amlogic/khadas-vim.rst
new file mode 100644
index 000000000..bbb61c29e
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/khadas-vim.rst
@@ -0,0 +1,101 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Khadas VIM
+======================
+
+Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion
+Technology Co., Ltd with the following specifications:
+
+ - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 10/100 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
+ - 8GB/16GBeMMC
+ - microSD
+ - SDIO Wifi Module, Bluetooth
+ - Two channels IR receiver
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make khadas-vim_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/khadas/u-boot -b Vim vim-u-boot
+    $ cd vim-u-boot
+    $ make kvim_defconfig
+    $ make CROSS_COMPILE=aarch64-none-elf-
+    $ export FIPDIR=$PWD/fip
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/gxl/bl2.bin fip/
+    $ cp $FIPDIR/gxl/acs.bin fip/
+    $ cp $FIPDIR/gxl/bl21.bin fip/
+    $ cp $FIPDIR/gxl/bl30.bin fip/
+    $ cp $FIPDIR/gxl/bl301.bin fip/
+    $ cp $FIPDIR/gxl/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl2_acs.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/bl21.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/khadas-vim2.rst b/roms/u-boot/doc/board/amlogic/khadas-vim2.rst
new file mode 100644
index 000000000..c57d96d8b
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/khadas-vim2.rst
@@ -0,0 +1,102 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Khadas VIM2
+=======================
+
+Khadas VIM2 is an Open Source DIY Box manufactured by Shenzhen Wesion
+Technology Co., Ltd with the following specifications:
+
+ - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
+ - ARM Mali T860 GPU
+ - 2/3GB DDR4 SDRAM
+ - 10/100/1000 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
+ - 16GB/32GB/64GB eMMC
+ - 2MB SPI Flash
+ - microSD
+ - SDIO Wifi Module, Bluetooth
+ - Two channels IR receiver
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make khadas-vim2_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/khadas/u-boot -b khadas-vim-v2015.01 vim-u-boot
+    $ cd vim-u-boot
+    $ make kvim2_defconfig
+    $ make
+    $ export FIPDIR=$PWD/fip
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/gxl/bl2.bin fip/
+    $ cp $FIPDIR/gxl/acs.bin fip/
+    $ cp $FIPDIR/gxl/bl21.bin fip/
+    $ cp $FIPDIR/gxl/bl30.bin fip/
+    $ cp $FIPDIR/gxl/bl301.bin fip/
+    $ cp $FIPDIR/gxl/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl2_acs.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/bl21.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/khadas-vim3.rst b/roms/u-boot/doc/board/amlogic/khadas-vim3.rst
new file mode 100644
index 000000000..8b7196d98
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/khadas-vim3.rst
@@ -0,0 +1,160 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Khadas VIM3
+======================
+
+Khadas VIM3 is a single board computer manufactured by Shenzhen Wesion
+Technology Co., Ltd. with the following specifications:
+
+ - Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC
+ - 4GB LPDDR4 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.1 display
+ - 40-pin GPIO header
+ - 1 x USB 3.0 Host, 1 x USB 2.0 Host
+ - eMMC, microSD
+ - M.2
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+PCIe Setup
+----------
+The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
+lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
+an USB3.0 Type A connector and a M.2 Key M slot.
+The PHY driving these differential lines is shared between
+the USB3.0 controller and the PCIe Controller, thus only
+a single controller can use it.
+
+To setup for PCIe, run the following commands from U-Boot:
+
+.. code-block:: none
+
+    i2c dev i2c@5000
+    i2c mw 0x18 0x33 1
+
+Then power-cycle the board.
+
+To set back to USB3.0, run the following commands from U-Boot:
+
+.. code-block:: none
+
+    i2c dev i2c@5000
+    i2c mw 0x18 0x33 0
+
+Then power-cycle the board.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make khadas-vim3_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+    $ DIR=vim3-u-boot
+    $ git clone --depth 1 \
+       https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
+       $DIR
+
+    $ cd vim3-u-boot
+    $ make kvim3_defconfig
+    $ make CROSS_COMPILE=aarch64-none-elf-
+    $ export UBOOTDIR=$PWD
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/khadas/kvim3/firmware/acs.bin fip/
+    $ cp $UBOOTDIR/fip/g12b/bl2.bin fip/
+    $ cp $UBOOTDIR/fip/g12b/bl30.bin fip/
+    $ cp $UBOOTDIR/fip/g12b/bl31.img fip/
+    $ cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/lpddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/piei.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ bash fip/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ bash fip/blx_fix.sh \
+    	fip/bl2.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/acs.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+    					--output fip/bl30_new.bin.g12a.enc \
+    					--level v3
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+    					--output fip/bl30_new.bin.enc \
+    					--level v3 --type bl30
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+    					--output fip/bl31.img.enc \
+    					--level v3 --type bl31
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+    					--output fip/bl33.bin.enc \
+    					--level v3 --type bl33 --compress lz4
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+    					--output fip/bl2.n.bin.sig
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc \
+    		--ddrfw1 fip/ddr4_1d.fw \
+    		--ddrfw2 fip/ddr4_2d.fw \
+    		--ddrfw3 fip/ddr3_1d.fw \
+    		--ddrfw4 fip/piei.fw \
+    		--ddrfw5 fip/lpddr4_1d.fw \
+    		--ddrfw6 fip/lpddr4_2d.fw \
+    		--ddrfw7 fip/diag_lpddr4.fw \
+    		--ddrfw8 fip/aml_ddr.fw \
+    		--ddrfw9 fip/lpddr3_1d.fw \
+    		--level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/khadas-vim3l.rst b/roms/u-boot/doc/board/amlogic/khadas-vim3l.rst
new file mode 100644
index 000000000..aed895539
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/khadas-vim3l.rst
@@ -0,0 +1,160 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Khadas VIM3L
+=======================
+
+Khadas VIM3L is a single board computer manufactured by Shenzhen Wesion
+Technology Co., Ltd. with the following specifications:
+
+ - Amlogic S905D3 Arm Cortex-A55 quad-core SoC
+ - 2GB LPDDR4 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.1 display
+ - 40-pin GPIO header
+ - 1 x USB 3.0 Host, 1 x USB 2.0 Host
+ - eMMC, microSD
+ - M.2
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+PCIe Setup
+----------
+The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
+lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
+an USB3.0 Type A connector and a M.2 Key M slot.
+The PHY driving these differential lines is shared between
+the USB3.0 controller and the PCIe Controller, thus only
+a single controller can use it.
+
+To setup for PCIe, run the following commands from U-Boot:
+
+.. code-block:: none
+
+    i2c dev i2c@5000
+    i2c mw 0x18 0x33 1
+
+Then power-cycle the board.
+
+To set back to USB3.0, run the following commands from U-Boot:
+
+.. code-block:: none
+
+    i2c dev i2c@5000
+    i2c mw 0x18 0x33 0
+
+Then power-cycle the board.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make khadas-vim3l_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+    $ DIR=vim3l-u-boot
+    $ git clone --depth 1 \
+       https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
+       $DIR
+
+    $ cd vim3l-u-boot
+    $ make kvim3l_defconfig
+    $ make CROSS_COMPILE=aarch64-none-elf-
+    $ export UBOOTDIR=$PWD
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/khadas/kvim3l/firmware/acs.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ bash fip/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ bash fip/blx_fix.sh \
+    	fip/bl2.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/acs.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+    					--output fip/bl30_new.bin.g12a.enc \
+    					--level v3
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+    					--output fip/bl30_new.bin.enc \
+    					--level v3 --type bl30
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+    					--output fip/bl31.img.enc \
+    					--level v3 --type bl31
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+    					--output fip/bl33.bin.enc \
+    					--level v3 --type bl33 --compress lz4
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+    					--output fip/bl2.n.bin.sig
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc \
+    		--ddrfw1 fip/ddr4_1d.fw \
+    		--ddrfw2 fip/ddr4_2d.fw \
+    		--ddrfw3 fip/ddr3_1d.fw \
+    		--ddrfw4 fip/piei.fw \
+    		--ddrfw5 fip/lpddr4_1d.fw \
+    		--ddrfw6 fip/lpddr4_2d.fw \
+    		--ddrfw7 fip/diag_lpddr4.fw \
+    		--ddrfw8 fip/aml_ddr.fw \
+    		--ddrfw9 fip/lpddr3_1d.fw \
+    		--level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/libretech-ac.rst b/roms/u-boot/doc/board/amlogic/libretech-ac.rst
new file mode 100644
index 000000000..39bae86d3
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/libretech-ac.rst
@@ -0,0 +1,110 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for LibreTech AC
+=======================
+
+LibreTech AC is a single board computer manufactured by Libre Technology
+with the following specifications:
+
+ - Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz
+ - ARM Mali 450 GPU
+ - 512MiB DDR4 SDRAM
+ - 10/100 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host
+ - eMMC, SPI NOR Flash
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make libretech-ac_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b libretech-ac amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ wget https://raw.githubusercontent.com/BayLibre/u-boot/libretech-cc/fip/blx_fix.sh
+    $ make libretech_ac_defconfig
+    $ make
+    $ export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+
+.. code-block:: bash
+
+    $ wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz
+    $ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader
+    $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/bl21.bin fip/
+    $ cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/acs.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl2/bin/gxl/bl2.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl30/bin/gxl/bl30.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl31/bin/gxl/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh $UBOOTDIR/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ sh $UBOOTDIR/blx_fix.sh \
+    	fip/bl2_acs.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/bl21.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+    $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+    $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+    $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+    $ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/libretech-cc.rst b/roms/u-boot/doc/board/amlogic/libretech-cc.rst
new file mode 100644
index 000000000..94c74c5a8
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/libretech-cc.rst
@@ -0,0 +1,146 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for LibreTech CCs
+========================
+
+LibreTech CC is a single board computer manufactured by Libre Technology
+with the following specifications:
+
+V1:
+
+ - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 10/100 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host
+ - eMMC, microSD
+ - Infrared receiver
+ - Jack for CVBS and Audio
+
+V2:
+
+ - Added SPI NOR
+ - Removed Jack
+
+Schematics are available on the manufacturer website.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make libretech-cc_defconfig
+    $ make
+
+Use libretech-cc_v2_defconfig for v2.
+
+Image creation
+--------------
+
+To boot the system, u-boot must be combined with several earlier stage
+bootloaders:
+
+* bl2.bin: vendor-provided binary blob
+* bl21.bin: built from vendor u-boot source
+* bl30.bin: vendor-provided binary blob
+* bl301.bin: built from vendor u-boot source
+* bl31.bin: vendor-provided binary blob
+* acs.bin: built from vendor u-boot source
+
+These binaries and the tools required below have been collected and prebuilt
+for convenience at <https://github.com/BayLibre/u-boot/releases/>. These
+apply to both v1 and v2.
+
+Download and extract the libretech-cc release from there, and set FIPDIR to
+point to the `fip` subdirectory.
+
+.. code-block:: bash
+
+    $ export FIPDIR=/path/to/extracted/fip
+
+Alternatively, you can obtain the original vendor u-boot tree which
+contains the required blobs and sources, and build yourself.
+Note that old compilers are required for this to build. The compilers here
+are suggested by Amlogic, and they are 32-bit x86 binaries.
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ make libretech_cc_defconfig
+    $ make
+    $ export FIPDIR=$PWD/fip
+
+Once you have the binaries available (either through the prebuilt download,
+or having built the vendor u-boot yourself), you can then proceed to glue
+everything together. Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/gxl/bl2.bin fip/
+    $ cp $FIPDIR/gxl/acs.bin fip/
+    $ cp $FIPDIR/gxl/bl21.bin fip/
+    $ cp $FIPDIR/gxl/bl30.bin fip/
+    $ cp $FIPDIR/gxl/bl301.bin fip/
+    $ cp $FIPDIR/gxl/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl2_acs.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/bl21.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+
+Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no
+source code. Should you prefer to avoid that, there are open source reverse
+engineered versions available:
+
+1. gxlimg <https://github.com/repk/gxlimg>, which comes with a handy
+   Makefile that automates the whole process.
+2. meson-tools <https://github.com/afaerber/meson-tools>
+
+However, these community-developed alternatives are not endorsed by or
+supported by Amlogic.
diff --git a/roms/u-boot/doc/board/amlogic/nanopi-k2.rst b/roms/u-boot/doc/board/amlogic/nanopi-k2.rst
new file mode 100644
index 000000000..1222ee4e8
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/nanopi-k2.rst
@@ -0,0 +1,104 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for NanoPi-K2
+====================
+
+NanoPi-K2 is a single board computer manufactured by FriendlyElec
+with the following specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make nanopi-k2_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot
+    $ git clone https://github.com/friendlyarm/u-boot.git -b nanopi-k2-v2015.01 amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ sed -i 's/aarch64-linux-gnu-/aarch64-none-elf-/' Makefile
+    $ sed -i 's/arm-linux-/arm-none-eabi-/' arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile
+    $ make nanopi-k2_defconfig
+    $ make
+    $ export FIPDIR=$PWD/fip
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/gxb/bl2.bin fip/
+    $ cp $FIPDIR/gxb/acs.bin fip/
+    $ cp $FIPDIR/gxb/bl21.bin fip/
+    $ cp $FIPDIR/gxb/bl30.bin fip/
+    $ cp $FIPDIR/gxb/bl301.bin fip/
+    $ cp $FIPDIR/gxb/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ $FIPDIR/fip_create \
+    	 --bl30 fip/bl30_new.bin \
+    	 --bl31 fip/bl31.img \
+    	 --bl33 fip/bl33.bin \
+    	 fip/fip.bin
+
+    $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl2_acs.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/bl21.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
+
+    $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
+    		--input fip/boot_new.bin
+    		--output fip/u-boot.bin
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1
diff --git a/roms/u-boot/doc/board/amlogic/odroid-c2.rst b/roms/u-boot/doc/board/amlogic/odroid-c2.rst
new file mode 100644
index 000000000..966c18b36
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/odroid-c2.rst
@@ -0,0 +1,63 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for ODROID-C2
+====================
+
+ODROID-C2 is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make odroid-c2_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ DIR=odroid-c2
+    $ git clone --depth 1 \
+       https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
+       $DIR
+    $ $DIR/fip/fip_create --bl30  $DIR/fip/gxb/bl30.bin \
+                       --bl301 $DIR/fip/gxb/bl301.bin \
+                       --bl31  $DIR/fip/gxb/bl31.bin \
+                       --bl33  u-boot.bin \
+                       $DIR/fip.bin
+    $ $DIR/fip/fip_create --dump $DIR/fip.bin
+    $ cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
+    $ $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
+                                --input $DIR/boot_new.bin \
+                                --output $DIR/u-boot.img
+    $ dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ BL1=$DIR/sd_fuse/bl1.bin.hardkernel
+    $ dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
+    $ dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1
+    $ dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97
diff --git a/roms/u-boot/doc/board/amlogic/odroid-c4.rst b/roms/u-boot/doc/board/amlogic/odroid-c4.rst
new file mode 100644
index 000000000..5a5a8688b
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/odroid-c4.rst
@@ -0,0 +1,134 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for ODROID-C4
+====================
+
+ODROID-C4 is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.1 display
+ - 40-pin GPIO header
+ - 4x USB 3.0 Host
+ - 1x USB 2.0 Host/OTG (micro)
+ - eMMC, microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make odroid-c4_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+    $ DIR=odroid-c4
+    $ git clone --depth 1 \
+       https://github.com/hardkernel/u-boot.git -b odroidg12-v2015.01 \
+       $DIR
+
+    $ cd odroid-c4
+    $ make odroidc4_defconfig
+    $ make
+    $ export UBOOTDIR=$PWD
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/hardkernel/odroidc4/firmware/acs.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+    $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+    $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl2.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/acs.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+    					--output fip/bl30_new.bin.g12a.enc \
+    					--level v3
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+    					--output fip/bl30_new.bin.enc \
+    					--level v3 --type bl30
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+    					--output fip/bl31.img.enc \
+    					--level v3 --type bl31
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+    					--output fip/bl33.bin.enc \
+    					--level v3 --type bl33 --compress lz4
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+    					--output fip/bl2.n.bin.sig
+    $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc \
+    		--ddrfw1 fip/ddr4_1d.fw \
+    		--ddrfw2 fip/ddr4_2d.fw \
+    		--ddrfw3 fip/ddr3_1d.fw \
+    		--ddrfw4 fip/piei.fw \
+    		--ddrfw5 fip/lpddr4_1d.fw \
+    		--ddrfw6 fip/lpddr4_2d.fw \
+    		--ddrfw7 fip/diag_lpddr4.fw \
+    		--ddrfw8 fip/aml_ddr.fw \
+    		--ddrfw9 fip/lpddr3_1d.fw \
+    		--level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/odroid-n2.rst b/roms/u-boot/doc/board/amlogic/odroid-n2.rst
new file mode 100644
index 000000000..fe6311323
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/odroid-n2.rst
@@ -0,0 +1,130 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for ODROID-N2
+====================
+
+ODROID-N2 is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.1 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 3.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make odroid-n2_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+    $ DIR=odroid-n2
+    $ git clone --depth 1 \
+       https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \
+       $DIR
+
+    $ cd odroid-n2
+    $ make odroidn2_defconfig
+    $ make
+    $ export UBOOTDIR=$PWD
+
+ Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/hardkernel/odroidn2/firmware/acs.bin fip/
+    $ cp $UBOOTDIR/fip/g12b/bl2.bin fip/
+    $ cp $UBOOTDIR/fip/g12b/bl30.bin fip/
+    $ cp $UBOOTDIR/fip/g12b/bl31.img fip/
+    $ cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/piei.fw fip/
+    $ cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl2.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/acs.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+    					--output fip/bl30_new.bin.g12a.enc \
+    					--level v3
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+    					--output fip/bl30_new.bin.enc \
+    					--level v3 --type bl30
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+    					--output fip/bl31.img.enc \
+    					--level v3 --type bl31
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+    					--output fip/bl33.bin.enc \
+    					--level v3 --type bl33 --compress lz4
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+    					--output fip/bl2.n.bin.sig
+    $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc \
+    		--ddrfw1 fip/ddr4_1d.fw \
+    		--ddrfw2 fip/ddr4_2d.fw \
+    		--ddrfw3 fip/ddr3_1d.fw \
+    		--ddrfw4 fip/piei.fw \
+    		--ddrfw5 fip/lpddr4_1d.fw \
+    		--ddrfw6 fip/lpddr4_2d.fw \
+    		--ddrfw7 fip/diag_lpddr4.fw \
+    		--ddrfw8 fip/aml_ddr.fw \
+    		--level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/p200.rst b/roms/u-boot/doc/board/amlogic/p200.rst
new file mode 100644
index 000000000..c3d6441fd
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/p200.rst
@@ -0,0 +1,102 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Amlogic P200
+=======================
+
+P200 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 2 x USB 2.0 Host
+ - eMMC, microSD
+ - Infrared receiver
+ - SDIO WiFi Module
+ - CVBS+Stereo Audio Jack
+
+Schematics are available from Amlogic on demand.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make p200_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ make gxb_p200_v1_defconfig
+    $ make
+    $ export FIPDIR=$PWD/fip
+
+Go back to mainline U-boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/gxl/bl2.bin fip/
+    $ cp $FIPDIR/gxl/acs.bin fip/
+    $ cp $FIPDIR/gxl/bl21.bin fip/
+    $ cp $FIPDIR/gxl/bl30.bin fip/
+    $ cp $FIPDIR/gxl/bl301.bin fip/
+    $ cp $FIPDIR/gxl/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl2_acs.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/bl21.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/p201.rst b/roms/u-boot/doc/board/amlogic/p201.rst
new file mode 100644
index 000000000..06da933a2
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/p201.rst
@@ -0,0 +1,102 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Amlogic P201
+=======================
+
+P201 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 10/100 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 2 x USB 2.0 Host
+ - eMMC, microSD
+ - Infrared receiver
+ - SDIO WiFi Module
+ - CVBS+Stereo Audio Jack
+
+Schematics are available from Amlogic on demand.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make p201_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ make gxb_p201_v1_defconfig
+    $ make
+    $ export FIPDIR=$PWD/fip
+
+Go back to mainline U-boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/gxl/bl2.bin fip/
+    $ cp $FIPDIR/gxl/acs.bin fip/
+    $ cp $FIPDIR/gxl/bl21.bin fip/
+    $ cp $FIPDIR/gxl/bl30.bin fip/
+    $ cp $FIPDIR/gxl/bl301.bin fip/
+    $ cp $FIPDIR/gxl/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl2_acs.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/bl21.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/p212.rst b/roms/u-boot/doc/board/amlogic/p212.rst
new file mode 100644
index 000000000..e2f3fe313
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/p212.rst
@@ -0,0 +1,102 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Amlogic P212
+=======================
+
+P212 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 10/100 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 2 x USB 2.0 Host
+ - eMMC, microSD
+ - Infrared receiver
+ - SDIO WiFi Module
+ - CVBS+Stereo Audio Jack
+
+Schematics are available from Amlogic on demand.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make p212_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ make gxl_p212_v1_defconfig
+    $ make
+    $ export FIPDIR=$PWD/fip
+
+Go back to mainline U-boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/gxl/bl2.bin fip/
+    $ cp $FIPDIR/gxl/acs.bin fip/
+    $ cp $FIPDIR/gxl/bl21.bin fip/
+    $ cp $FIPDIR/gxl/bl30.bin fip/
+    $ cp $FIPDIR/gxl/bl301.bin fip/
+    $ cp $FIPDIR/gxl/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl2_acs.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/bl21.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/q200.rst b/roms/u-boot/doc/board/amlogic/q200.rst
new file mode 100644
index 000000000..3ac4116be
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/q200.rst
@@ -0,0 +1,101 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Amlogic Q200
+=======================
+
+Q200 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
+ - ARM Mali T860 GPU
+ - 2/3GB DDR4 SDRAM
+ - 10/100/1000 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 2 x USB 2.0 Host, 1 x USB 2.0 Device
+ - 16GB/32GB/64GB eMMC
+ - 2MB SPI Flash
+ - microSD
+ - SDIO Wifi Module, Bluetooth
+ - IR receiver
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make khadas-vim2_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ make gxm_q200_v1_defconfig
+    $ make
+    $ export FIPDIR=$PWD/fip
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/gxl/bl2.bin fip/
+    $ cp $FIPDIR/gxl/acs.bin fip/
+    $ cp $FIPDIR/gxl/bl21.bin fip/
+    $ cp $FIPDIR/gxl/bl30.bin fip/
+    $ cp $FIPDIR/gxl/bl301.bin fip/
+    $ cp $FIPDIR/gxl/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl2_acs.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/bl21.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/s400.rst b/roms/u-boot/doc/board/amlogic/s400.rst
new file mode 100644
index 000000000..52c7b2733
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/s400.rst
@@ -0,0 +1,109 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Amlogic S400
+=======================
+
+S400 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
+ - 1GB DDR4 SDRAM
+ - 10/100 Ethernet
+ - 2 x USB 2.0 Host
+ - eMMC
+ - Infrared receiver
+ - SDIO WiFi Module
+ - MIPI DSI Connector
+ - Audio HAT Connector
+ - PCI-E M.2 Connectors
+
+Schematics are available from Amlogic on demand.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make s400_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ make axg_s400_v1_defconfig
+    $ make
+    $ export FIPDIR=$PWD/fip
+
+Go back to mainline U-boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ cp $FIPDIR/axg/bl2.bin fip/
+    $ cp $FIPDIR/axg/acs.bin fip/
+    $ cp $FIPDIR/axg/bl21.bin fip/
+    $ cp $FIPDIR/axg/bl30.bin fip/
+    $ cp $FIPDIR/axg/bl301.bin fip/
+    $ cp $FIPDIR/axg/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+    $ $FIPDIR/blx_fix.sh \
+    	fip/bl2_acs.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/bl21.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
+    					--output fip/bl30_new.bin.enc \
+    					--level v3 --type bl30
+    $ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \
+    					--output fip/bl31.img.enc \
+    					--level v3 --type bl31
+    $ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
+    					--output fip/bl33.bin.enc \
+    					--level v3 --type bl33
+    $ $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
+    					--output fip/bl2.n.bin.sig
+    $ $FIPDIR/axg/aml_encrypt_axg --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc --level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/sei510.rst b/roms/u-boot/doc/board/amlogic/sei510.rst
new file mode 100644
index 000000000..2d296b1c3
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/sei510.rst
@@ -0,0 +1,130 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Amlogic SEI510
+=========================
+
+SEI510 is a customer board manufactured by SEI Robotics with the following
+specifications:
+
+ - Amlogic S905X2 ARM Cortex-A53 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 10/100 Ethernet (Internal PHY)
+ - 1 x USB 3.0 Host
+ - eMMC
+ - SDcard
+ - Infrared receiver
+ - SDIO WiFi Module
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make sei510_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ make g12a_u200_v1_defconfig
+    $ make
+    $ export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+
+.. code-block:: bash
+
+    $ wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
+    $ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
+    $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
+    $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/
+    $ cp $FIPDIR/g12a/ddr3_1d.fw fip/
+    $ cp $FIPDIR/g12a/ddr4_1d.fw fip/
+    $ cp $FIPDIR/g12a/ddr4_2d.fw fip/
+    $ cp $FIPDIR/g12a/diag_lpddr4.fw fip/
+    $ cp $FIPDIR/g12a/lpddr4_1d.fw fip/
+    $ cp $FIPDIR/g12a/lpddr4_2d.fw fip/
+    $ cp $FIPDIR/g12a/piei.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl2.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/acs.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+    					--output fip/bl30_new.bin.g12a.enc \
+    					--level v3
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+    					--output fip/bl30_new.bin.enc \
+    					--level v3 --type bl30
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+    					--output fip/bl31.img.enc \
+    					--level v3 --type bl31
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+    					--output fip/bl33.bin.enc \
+    					--level v3 --type bl33
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+    					--output fip/bl2.n.bin.sig
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc \
+    		--ddrfw1 fip/ddr4_1d.fw \
+    		--ddrfw2 fip/ddr4_2d.fw \
+    		--ddrfw3 fip/ddr3_1d.fw \
+    		--ddrfw4 fip/piei.fw \
+    		--ddrfw5 fip/lpddr4_1d.fw \
+    		--ddrfw6 fip/lpddr4_2d.fw \
+    		--ddrfw7 fip/diag_lpddr4.fw \
+    		--level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/sei610.rst b/roms/u-boot/doc/board/amlogic/sei610.rst
new file mode 100644
index 000000000..9434e6f02
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/sei610.rst
@@ -0,0 +1,133 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Amlogic SEI610
+=========================
+
+SEI610 is a customer board manufactured by SEI Robotics with the following
+specifications:
+
+ - Amlogic S905X3 ARM Cortex-A55 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 10/100 Ethernet (Internal PHY)
+ - 1 x USB 3.0 Host
+ - 1 x USB Type-C DRD
+ - 1 x FTDI USB Serial Debug Interface
+ - eMMC
+ - SDcard
+ - Infrared receiver
+ - SDIO WiFi Module
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make sei610_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-4.9-g12a-201904 amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ make sm1_ac200_v1_defconfig
+    $ make
+    $ export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+
+.. code-block:: bash
+
+    $ wget http://openlinux2.amlogic.com:8000/ARM/filesystem/buildroot-openlinux-A113-201901.tgz
+    $ tar xfz buildroot-openlinux-A113-201901.tgz buildroot-openlinux-A113-201901/bootloader
+    $ export BRDIR=$PWD/buildroot-openlinux-A113-201901
+    $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
+
+Go back to mainline U-Boot source tree then :
+
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/
+    $ cp $FIPDIR/g12a/ddr3_1d.fw fip/
+    $ cp $FIPDIR/g12a/ddr4_1d.fw fip/
+    $ cp $FIPDIR/g12a/ddr4_2d.fw fip/
+    $ cp $FIPDIR/g12a/diag_lpddr4.fw fip/
+    $ cp $FIPDIR/g12a/lpddr4_1d.fw fip/
+    $ cp $FIPDIR/g12a/lpddr4_2d.fw fip/
+    $ cp $FIPDIR/g12a/piei.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl2.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/acs.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+    					--output fip/bl30_new.bin.g12a.enc \
+    					--level v3
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+    					--output fip/bl30_new.bin.enc \
+    					--level v3 --type bl30
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+    					--output fip/bl31.img.enc \
+    					--level v3 --type bl31
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+    					--output fip/bl33.bin.enc \
+    					--level v3 --type bl33
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+    					--output fip/bl2.n.bin.sig
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc \
+    		--ddrfw1 fip/ddr4_1d.fw \
+    		--ddrfw2 fip/ddr4_2d.fw \
+    		--ddrfw3 fip/ddr3_1d.fw \
+    		--ddrfw4 fip/piei.fw \
+    		--ddrfw5 fip/lpddr4_1d.fw \
+    		--ddrfw6 fip/lpddr4_2d.fw \
+    		--ddrfw7 fip/diag_lpddr4.fw \
+    		--level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/u200.rst b/roms/u-boot/doc/board/amlogic/u200.rst
new file mode 100644
index 000000000..5aa3936c2
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/u200.rst
@@ -0,0 +1,135 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Amlogic U200
+=======================
+
+U200 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S905D2 ARM Cortex-A53 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 10/100 Ethernet (Internal PHY)
+ - 1 x USB 3.0 Host
+ - eMMC
+ - SDcard
+ - Infrared receiver
+ - SDIO WiFi Module
+ - MIPI DSI Connector
+ - Audio HAT Connector
+ - PCI-E M.2 Connector
+
+Schematics are available from Amlogic on demand.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make u200_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ make g12a_u200_v1_defconfig
+    $ make
+    $ export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+
+.. code-block:: bash
+
+    $ wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
+    $ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
+    $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
+    $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/
+    $ cp $FIPDIR/g12a/ddr3_1d.fw fip/
+    $ cp $FIPDIR/g12a/ddr4_1d.fw fip/
+    $ cp $FIPDIR/g12a/ddr4_2d.fw fip/
+    $ cp $FIPDIR/g12a/diag_lpddr4.fw fip/
+    $ cp $FIPDIR/g12a/lpddr4_1d.fw fip/
+    $ cp $FIPDIR/g12a/lpddr4_2d.fw fip/
+    $ cp $FIPDIR/g12a/piei.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl2.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/acs.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+    					--output fip/bl30_new.bin.g12a.enc \
+    					--level v3
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+    					--output fip/bl30_new.bin.enc \
+    					--level v3 --type bl30
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+    					--output fip/bl31.img.enc \
+    					--level v3 --type bl31
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+    					--output fip/bl33.bin.enc \
+    					--level v3 --type bl33
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+    					--output fip/bl2.n.bin.sig
+    $ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc \
+    		--ddrfw1 fip/ddr4_1d.fw \
+    		--ddrfw2 fip/ddr4_2d.fw \
+    		--ddrfw3 fip/ddr3_1d.fw \
+    		--ddrfw4 fip/piei.fw \
+    		--ddrfw5 fip/lpddr4_1d.fw \
+    		--ddrfw6 fip/lpddr4_2d.fw \
+    		--ddrfw7 fip/diag_lpddr4.fw \
+    		--level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/w400.rst b/roms/u-boot/doc/board/amlogic/w400.rst
new file mode 100644
index 000000000..38dbf52fb
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/w400.rst
@@ -0,0 +1,137 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Amlogic W400
+=======================
+
+U200 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 10/100 Ethernet (Internal PHY)
+ - 1 x USB 3.0 Host
+ - eMMC
+ - SDcard
+ - Infrared receiver
+ - SDIO WiFi Module
+ - MIPI DSI Connector
+ - Audio HAT Connector
+ - PCI-E M.2 Connector
+
+Schematics are available from Amlogic on demand.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make w400_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
+    $ cd amlogic-u-boot
+    $ make g12b_w400_v1_defconfig
+    $ make
+    $ export UBOOTDIR=$PWD
+
+Download the latest Amlogic Buildroot package, and extract it :
+
+.. code-block:: bash
+
+    $ wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
+    $ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
+    $ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
+    $ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
+
+Go back to mainline U-Boot source tree then :
+
+.. code-block:: bash
+
+    $ mkdir fip
+
+    $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+    $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+    $ cp $UBOOTDIR/build/board/amlogic/g12b_w400_v1/firmware/acs.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12b/bl2.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12b/bl30.bin fip/
+    $ cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12b/bl31.img fip/
+    $ cp $FIPDIR/g12b/ddr3_1d.fw fip/
+    $ cp $FIPDIR/g12b/ddr4_1d.fw fip/
+    $ cp $FIPDIR/g12b/ddr4_2d.fw fip/
+    $ cp $FIPDIR/g12b/diag_lpddr4.fw fip/
+    $ cp $FIPDIR/g12b/lpddr4_1d.fw fip/
+    $ cp $FIPDIR/g12b/lpddr4_2d.fw fip/
+    $ cp $FIPDIR/g12b/piei.fw fip/
+    $ cp $FIPDIR/g12b/aml_ddr.fw fip/
+    $ cp u-boot.bin fip/bl33.bin
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl30.bin \
+    	fip/zero_tmp \
+    	fip/bl30_zero.bin \
+    	fip/bl301.bin \
+    	fip/bl301_zero.bin \
+    	fip/bl30_new.bin \
+    	bl30
+
+    $ sh fip/blx_fix.sh \
+    	fip/bl2.bin \
+    	fip/zero_tmp \
+    	fip/bl2_zero.bin \
+    	fip/acs.bin \
+    	fip/bl21_zero.bin \
+    	fip/bl2_new.bin \
+    	bl2
+
+    $ $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+    					--output fip/bl30_new.bin.g12a.enc \
+    					--level v3
+    $ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+    					--output fip/bl30_new.bin.enc \
+    					--level v3 --type bl30
+    $ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+    					--output fip/bl31.img.enc \
+    					--level v3 --type bl31
+    $ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+    					--output fip/bl33.bin.enc \
+    					--level v3 --type bl33
+    $ $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+    					--output fip/bl2.n.bin.sig
+    $ $FIPDIR/g12b/aml_encrypt_g12b --bootmk \
+    		--output fip/u-boot.bin \
+    		--bl2 fip/bl2.n.bin.sig \
+    		--bl30 fip/bl30_new.bin.enc \
+    		--bl31 fip/bl31.img.enc \
+    		--bl33 fip/bl33.bin.enc \
+    		--ddrfw1 fip/ddr4_1d.fw \
+    		--ddrfw2 fip/ddr4_2d.fw \
+    		--ddrfw3 fip/ddr3_1d.fw \
+    		--ddrfw4 fip/piei.fw \
+    		--ddrfw5 fip/lpddr4_1d.fw \
+    		--ddrfw6 fip/lpddr4_2d.fw \
+    		--ddrfw7 fip/diag_lpddr4.fw \
+    		--ddrfw8 fip/aml_ddr.fw \
+    		--level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/amlogic/wetek-core2.rst b/roms/u-boot/doc/board/amlogic/wetek-core2.rst
new file mode 100644
index 000000000..1012079de
--- /dev/null
+++ b/roms/u-boot/doc/board/amlogic/wetek-core2.rst
@@ -0,0 +1,96 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for WeTek Core2
+======================
+
+WeTek Core2 is an Android STB based on the Q200 reference design with
+the following specifications:
+
+ - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
+ - ARM Mali T820 GPU
+ - 3GB DDR4 SDRAM
+ - 10/100 Realtek RTL8152 Ethernet (internal USB)
+ - HDMI 2.0 4K/60Hz display
+ - 2x USB 2.0 Host, 1x USB 2.0 OTG (internal)
+ - 32GB eMMC
+ - microSD
+ - SDIO Wifi Module, Bluetooth
+ - Two channel IR receiver
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-none-elf-
+    $ make wetek-core2_defconfig
+    $ make
+
+Image creation
+--------------
+
+Amlogic does not provide sources for the firmware or the tools needed
+to create the bootloader image, and WeTek has not publicly shared the
+precompiled FIP binaries. However the public Khadas VIM2 sources also
+work with the Core2 box so we can use the Khadas git tree:
+
+.. code-block:: bash
+
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+    $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+    $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+    $ git clone https://github.com/khadas/u-boot -b khadas-vim-v2015.01 vim-u-boot
+    $ cd vim-u-boot
+    $ make kvim2_defconfig
+    $ make
+    $ export FIPDIR=$PWD/fip
+
+Go back to mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+    $ mkdir fip
+    $ cp $FIPDIR/gxl/bl2.bin fip/
+    $ cp $FIPDIR/gxl/acs.bin fip/
+    $ cp $FIPDIR/gxl/bl21.bin fip/
+    $ cp $FIPDIR/gxl/bl30.bin fip/
+    $ cp $FIPDIR/gxl/bl301.bin fip/
+    $ cp $FIPDIR/gxl/bl31.img fip/
+    $ cp u-boot.bin fip/bl33.bin
+    $ $FIPDIR/blx_fix.sh \
+        fip/bl30.bin \
+        fip/zero_tmp \
+        fip/bl30_zero.bin \
+        fip/bl301.bin \
+        fip/bl301_zero.bin \
+        fip/bl30_new.bin \
+        bl30
+    $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+    $ $FIPDIR/blx_fix.sh \
+        fip/bl2_acs.bin \
+        fip/zero_tmp \
+        fip/bl2_zero.bin \
+        fip/bl21.bin \
+        fip/bl21_zero.bin \
+        fip/bl2_new.bin \
+        bl2
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+    $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+        --output fip/u-boot.bin \
+        --bl2 fip/bl2.n.bin.sig \
+        --bl30 fip/bl30_new.bin.enc \
+        --bl31 fip/bl31.img.enc \
+        --bl33 fip/bl33.bin.enc
+
+then write the image to SD with:
+
+.. code-block:: bash
+
+    $ DEV=/dev/your_sd_device
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+    $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/roms/u-boot/doc/board/atmel/at91ek.rst b/roms/u-boot/doc/board/atmel/at91ek.rst
new file mode 100644
index 000000000..6185b1dfb
--- /dev/null
+++ b/roms/u-boot/doc/board/atmel/at91ek.rst
@@ -0,0 +1,192 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+AT91 Evaluation kits
+====================
+
+Board mapping & boot media
+--------------------------
+
+AT91SAM9260EK, AT91SAM9G20EK & AT91SAM9XEEK
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Memory map::
+
+	0x20000000 - 23FFFFFF	SDRAM (64 MB)
+	0xC0000000 - Cxxxxxxx	Atmel Dataflash card (J13)
+	0xD0000000 - D07FFFFF	Soldered Atmel Dataflash (AT45DB642)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+	- Dataflash on SPI chip select 1 (default)
+	- Dataflash on SPI chip select 0 (dataflash card)
+	- Nand flash
+
+You can choose your storage location at config step (here for at91sam9260ek)::
+
+	make at91sam9260ek_nandflash_config	- use nand flash
+	make at91sam9260ek_dataflash_cs0_config	- use data flash (spi cs0)
+	make at91sam9260ek_dataflash_cs1_config	- use data flash (spi cs1)
+
+
+AT91SAM9261EK, AT91SAM9G10EK
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Memory map::
+
+	0x20000000 - 23FFFFFF	SDRAM (64 MB)
+	0xC0000000 - C07FFFFF	Soldered Atmel Dataflash (AT45DB642)
+	0xD0000000 - Dxxxxxxx	Atmel Dataflash card (J22)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+	- Dataflash on SPI chip select 0 (default)
+	- Dataflash on SPI chip select 3 (dataflash card)
+	- Nand flash
+
+You can choose your storage location at config step (here for at91sam9260ek)::
+
+	make at91sam9261ek_nandflash_config	- use nand flash
+	make at91sam9261ek_dataflash_cs0_config	- use data flash (spi cs0)
+	make at91sam9261ek_dataflash_cs3_config	- use data flash (spi cs3)
+
+
+AT91SAM9263EK
+^^^^^^^^^^^^^
+
+Memory map::
+
+	0x20000000 - 23FFFFFF	SDRAM (64 MB)
+	0xC0000000 - Cxxxxxxx	Atmel Dataflash card (J9)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+	- Dataflash on SPI chip select 0 (dataflash card)
+	- Nand flash
+	- Nor flash (not populate by default)
+
+You can choose your storage location at config step (here for at91sam9260ek)::
+
+	make at91sam9263ek_nandflash_config	- use nand flash
+	make at91sam9263ek_dataflash_cs0_config	- use data flash (spi cs0)
+	make at91sam9263ek_norflash_config	- use nor flash
+
+You can choose to boot directly from U-Boot at config step::
+
+	make at91sam9263ek_norflash_boot_config	- boot from nor flash
+
+
+AT91SAM9M10G45EK
+^^^^^^^^^^^^^^^^
+
+Memory map::
+
+	0x70000000 - 77FFFFFF	SDRAM (128 MB)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+	- Nand flash
+
+You can choose your storage location at config step (here for at91sam9m10g45ek)::
+
+	make at91sam9m10g45ek_nandflash_config		- use nand flash
+
+
+AT91SAM9RLEK
+^^^^^^^^^^^^
+
+Memory map::
+
+	0x20000000 - 23FFFFFF	SDRAM (64 MB)
+	0xC0000000 - C07FFFFF   Soldered Atmel Dataflash (AT45DB642)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+	- Dataflash on SPI chip select 0
+	- Nand flash.
+
+You can choose your storage location at config step (here for at91sam9rlek)::
+
+	make at91sam9rlek_nandflash_config	- use nand flash
+
+
+AT91SAM9N12EK, AT91SAM9X5EK
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Memory map::
+
+	0x20000000 - 27FFFFFF	SDRAM (128 MB)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+	- Nand flash
+	- SD/MMC card
+	- Serialflash/Dataflash on SPI chip select 0
+
+You can choose your storage location at config step (here for at91sam9x5ek)::
+
+	make at91sam9x5ek_dataflash_config	- use data flash
+	make at91sam9x5ek_mmc_config		- use sd/mmc card
+	make at91sam9x5ek_nandflash_config	- use nand flash
+	make at91sam9x5ek_spiflash_config	- use serial flash
+
+
+SAMA5D3XEK
+^^^^^^^^^^
+
+Memory map::
+
+	0x20000000 - 3FFFFFFF	SDRAM (512 MB)
+
+Environment variables
+
+U-Boot environment variables can be stored at different places:
+
+	- Nand flash
+	- SD/MMC card
+	- Serialflash on SPI chip select 0
+
+You can choose your storage location at config step (here for sama5d3xek)::
+
+	make sama5d3xek_mmc_config		- use SD/MMC card
+	make sama5d3xek_nandflash_config	- use nand flash
+	make sama5d3xek_serialflash_config	- use serial flash
+
+
+NAND partition table
+--------------------
+
+All the board support boot from NAND flash will use the following NAND
+partition table::
+
+	0x00000000 - 0x0003FFFF	bootstrap	(256 KiB)
+	0x00040000 - 0x000BFFFF u-boot		(512 KiB)
+	0x000C0000 - 0x000FFFFF env		(256 KiB)
+	0x00100000 - 0x0013FFFF env_redundant	(256 KiB)
+	0x00140000 - 0x0017FFFF spare		(256 KiB)
+	0x00180000 - 0x001FFFFF dtb		(512 KiB)
+	0x00200000 - 0x007FFFFF kernel		(6 MiB)
+	0x00800000 - 0xxxxxxxxx rootfs		(All left)
+
+
+Watchdog support
+----------------
+
+For security reasons, the at91 watchdog is running at boot time and,
+if deactivated, cannot be used anymore.
+If you want to use the watchdog, you will need to keep it running in
+your code (make sure not to disable it in AT91Bootstrap for instance).
+
+In the U-Boot configuration, the AT91 watchdog support is enabled using
+the CONFIG_WDT and CONFIG_WDT_AT91 options.
diff --git a/roms/u-boot/doc/board/atmel/index.rst b/roms/u-boot/doc/board/atmel/index.rst
new file mode 100644
index 000000000..8ba00fc22
--- /dev/null
+++ b/roms/u-boot/doc/board/atmel/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Atmel
+=====
+
+.. toctree::
+   :maxdepth: 2
+
+   at91ek
diff --git a/roms/u-boot/doc/board/congatec/cgtqmx8.rst b/roms/u-boot/doc/board/congatec/cgtqmx8.rst
new file mode 100644
index 000000000..bccdef2f1
--- /dev/null
+++ b/roms/u-boot/doc/board/congatec/cgtqmx8.rst
@@ -0,0 +1,70 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Congatec conga-QMX8 board
+========================================
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Get imx-mkimage
+- Build U-Boot
+- Build imx-mkimage
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+.. code-block:: bash
+
+     $ git clone https://source.codeaurora.org/external/imx/imx-atf
+     $ cd imx-atf/
+     $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
+     $ make PLAT=imx8qm bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
+     $ chmod +x imx-sc-firmware-1.1.bin
+     $ ./imx-sc-firmware-1.1.bin
+     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+     $ chmod +x firmware-imx-8.0.bin
+     $ ./firmware-imx-8.0.bin
+
+Or use this to avoid running random scripts from the internet,
+but note that you must agree to the license the script displays:
+
+.. code-block:: bash
+
+     $ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1
+     $ tar -xf imx-sc-firmware-1.1.tar.bz2
+     $ cp imx-sc-firmware-1.1/mx8qx-val-scfw-tcm.bin $(builddir)
+
+     $ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1
+     $ tar -xf firmware-imx-8.0.tar.bz2
+     $ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+     $ export ATF_LOAD_ADDR=0x80000000
+     $ export BL33_LOAD_ADDR=0x80020000
+     $ make cgtqmx8_defconfig
+     $ make u-boot.bin
+     $ make flash.bin
+
+Flash the binary into the SD card
+---------------------------------
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+.. code-block:: bash
+
+     $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
diff --git a/roms/u-boot/doc/board/congatec/index.rst b/roms/u-boot/doc/board/congatec/index.rst
new file mode 100644
index 000000000..cc57b36b2
--- /dev/null
+++ b/roms/u-boot/doc/board/congatec/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Congatec
+========
+
+.. toctree::
+   :maxdepth: 2
+
+   cgtqmx8.rst
diff --git a/roms/u-boot/doc/board/coreboot/coreboot.rst b/roms/u-boot/doc/board/coreboot/coreboot.rst
new file mode 100644
index 000000000..9c44c025a
--- /dev/null
+++ b/roms/u-boot/doc/board/coreboot/coreboot.rst
@@ -0,0 +1,52 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Coreboot
+========
+
+Build Instructions for U-Boot as coreboot payload
+-------------------------------------------------
+Building U-Boot as a coreboot payload is just like building U-Boot for targets
+on other architectures, like below::
+
+   $ make coreboot_defconfig
+   $ make all
+
+Test with coreboot
+------------------
+For testing U-Boot as the coreboot payload, there are things that need be paid
+attention to. coreboot supports loading an ELF executable and a 32-bit plain
+binary, as well as other supported payloads. With the default configuration,
+U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
+generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
+provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
+this capability yet. The command is as follows::
+
+   # in the coreboot root directory
+   $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
+     -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
+
+Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
+of _x86boot_start (in arch/x86/cpu/start.S).
+
+If you want to use ELF as the coreboot payload, change U-Boot configuration to
+use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
+
+To enable video you must enable these options in coreboot:
+
+   - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
+   - Keep VESA framebuffer
+
+At present it seems that for Minnowboard Max, coreboot does not pass through
+the video information correctly (it always says the resolution is 0x0). This
+works correctly for link though.
+
+64-bit U-Boot
+-------------
+
+In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This
+produces an image which can be booted from coreboot (32-bit). Internally it
+works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It
+can be useful for running UEFI applications, for example.
+
+This has only been lightly tested.
diff --git a/roms/u-boot/doc/board/coreboot/index.rst b/roms/u-boot/doc/board/coreboot/index.rst
new file mode 100644
index 000000000..d148db95f
--- /dev/null
+++ b/roms/u-boot/doc/board/coreboot/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Coreboot
+========
+
+.. toctree::
+   :maxdepth: 2
+
+   coreboot
diff --git a/roms/u-boot/doc/board/emulation/index.rst b/roms/u-boot/doc/board/emulation/index.rst
new file mode 100644
index 000000000..be66b6bb6
--- /dev/null
+++ b/roms/u-boot/doc/board/emulation/index.rst
@@ -0,0 +1,14 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Emulation
+=========
+
+.. toctree::
+   :maxdepth: 2
+
+   qemu-arm
+   qemu-mips
+   qemu-ppce500
+   qemu-riscv
+   qemu-x86
+   qemu_capsule_update
diff --git a/roms/u-boot/doc/board/emulation/qemu-arm.rst b/roms/u-boot/doc/board/emulation/qemu-arm.rst
new file mode 100644
index 000000000..8d7fda10f
--- /dev/null
+++ b/roms/u-boot/doc/board/emulation/qemu-arm.rst
@@ -0,0 +1,92 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2017, Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
+
+QEMU ARM
+========
+
+QEMU for ARM supports a special 'virt' machine designed for emulation and
+virtualization purposes. This document describes how to run U-Boot under it.
+Both 32-bit ARM and AArch64 are supported.
+
+The 'virt' platform provides the following as the basic functionality:
+
+    - A freely configurable amount of CPU cores
+    - U-Boot loaded and executing in the emulated flash at address 0x0
+    - A generated device tree blob placed at the start of RAM
+    - A freely configurable amount of RAM, described by the DTB
+    - A PL011 serial port, discoverable via the DTB
+    - An ARMv7/ARMv8 architected timer
+    - PSCI for rebooting the system
+    - A generic ECAM-based PCI host controller, discoverable via the DTB
+
+Additionally, a number of optional peripherals can be added to the PCI bus.
+
+Building U-Boot
+---------------
+Set the CROSS_COMPILE environment variable as usual, and run:
+
+- For ARM::
+
+    make qemu_arm_defconfig
+    make
+
+- For AArch64::
+
+    make qemu_arm64_defconfig
+    make
+
+Running U-Boot
+--------------
+The minimal QEMU command line to get U-Boot up and running is:
+
+- For ARM::
+
+    qemu-system-arm -machine virt -bios u-boot.bin
+
+- For AArch64::
+
+    qemu-system-aarch64 -machine virt -cpu cortex-a57 -bios u-boot.bin
+
+Note that for some odd reason qemu-system-aarch64 needs to be explicitly
+told to use a 64-bit CPU or it will boot in 32-bit mode.
+
+Additional persistent U-boot environment support can be added as follows:
+
+- Create envstore.img using qemu-img::
+
+    qemu-img create -f raw envstore.img 64M
+
+- Add a pflash drive parameter to the command line::
+
+    -drive if=pflash,format=raw,index=1,file=envstore.img
+
+Additional peripherals that have been tested to work in both U-Boot and Linux
+can be enabled with the following command line parameters:
+
+- To add a Serial ATA disk via an Intel ICH9 AHCI controller, pass e.g.::
+
+    -drive if=none,file=disk.img,id=mydisk -device ich9-ahci,id=ahci -device ide-drive,drive=mydisk,bus=ahci.0
+
+- To add an Intel E1000 network adapter, pass e.g.::
+
+    -netdev user,id=net0 -device e1000,netdev=net0
+
+- To add an EHCI-compliant USB host controller, pass e.g.::
+
+    -device usb-ehci,id=ehci
+
+- To add a NVMe disk, pass e.g.::
+
+    -drive if=none,file=disk.img,id=mydisk -device nvme,drive=mydisk,serial=foo
+
+These have been tested in QEMU 2.9.0 but should work in at least 2.5.0 as well.
+
+Debug UART
+----------
+
+The debug UART on the ARM virt board uses these settings::
+
+    CONFIG_DEBUG_UART=y
+    CONFIG_DEBUG_UART_PL010=y
+    CONFIG_DEBUG_UART_BASE=0x9000000
+    CONFIG_DEBUG_UART_CLOCK=0
diff --git a/roms/u-boot/doc/board/emulation/qemu-mips.rst b/roms/u-boot/doc/board/emulation/qemu-mips.rst
new file mode 100644
index 000000000..5fd8a0a23
--- /dev/null
+++ b/roms/u-boot/doc/board/emulation/qemu-mips.rst
@@ -0,0 +1,129 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+
+QEMU MIPS
+=========
+
+Qemu for MIPS is based on the MIPS Malta board. The built Malta U-Boot
+images can be used for Qemu and on physical hardware. The Malta board
+supports all combinations of Little and Big Endian as well as 32 bit
+and 64 bit.
+
+Limitations & comments
+----------------------
+The memory size for Qemu is hard-coded to 256 MiB. For Malta Little Endian
+targets an extra endianness swapped image named *u-boot-swap.bin* is
+generated and required for Qemu.
+
+Example usage
+-------------
+
+Build for 32 bit, big endian:
+
+.. code-block:: bash
+
+  make malta_defconfig
+  make
+  UBOOT_BIN=u-boot.bin
+  QEMU_BIN=qemu-system-mips
+  QEMU_CPU=24Kc
+
+Build for 32 bit, little endian:
+
+.. code-block:: bash
+
+  make maltael_defconfig
+  make
+  UBOOT_BIN=u-boot-swap.bin
+  QEMU_BIN=qemu-system-mipsel
+  QEMU_CPU=24Kc
+
+Build for 64 bit, big endian:
+
+.. code-block:: bash
+
+  make malta64_defconfig
+  make
+  UBOOT_BIN=u-boot.bin
+  QEMU_BIN=qemu-system-mips64
+  QEMU_CPU=MIPS64R2-generic
+
+Build for 64 bit, little endian:
+
+.. code-block:: bash
+
+  make malta64el_defconfig
+  make
+  UBOOT_BIN=u-boot-swap.bin
+  QEMU_BIN=qemu-system-mips64el
+  QEMU_CPU=MIPS64R2-generic
+
+Generate NOR flash image with U-Boot binary:
+
+.. code-block:: bash
+
+  dd if=/dev/zero bs=1M count=4 | tr '\000' '\377' > pflash.img
+  dd if=${UBOOT_BIN} of=pflash.img conv=notrunc
+
+Start Qemu:
+
+.. code-block:: bash
+
+  mkdir tftproot
+  ${QEMU_BIN} -nographic -cpu ${QEMU_CPU} -m 256 -drive if=pflash,file="$(pwd)/pflash.img",format=raw -netdev user,id=net0,tftp="$(pwd)/tftproot" -device pcnet,netdev=net0
+
+.. code-block:: bash
+
+  U-Boot 2021.04-00963-g60279a2b1d (Apr 21 2021 - 19:54:32 +0200)
+
+  Board: MIPS Malta CoreLV
+  DRAM:  256 MiB
+  Flash: 4 MiB
+  Loading Environment from Flash... *** Warning - bad CRC, using default environment
+
+  In:    serial@3f8
+  Out:   serial@3f8
+  Err:   serial@3f8
+  Net:   pcnet#0
+  IDE:   Bus 0: not available
+  maltael #
+
+How to debug U-Boot
+-------------------
+
+In order to debug U-Boot you need to start qemu with gdb server support (-s)
+and waiting the connection to start the CPU (-S). Start Qemu in the first console:
+
+.. code-block:: bash
+
+  mkdir tftproot
+  ${QEMU_BIN} -s -S -nographic -cpu ${QEMU_CPU} -m 256 -drive if=pflash,file="$(pwd)/pflash.img",format=raw -netdev user,id=net0,tftp="$(pwd)/tftproot" -device pcnet,netdev=net0
+
+In the second console start gdb:
+
+.. code-block:: bash
+
+  gdb-multiarch --eval-command "target remote :1234" u-boot
+
+.. code-block:: bash
+
+  GNU gdb (Ubuntu 9.2-0ubuntu1~20.04) 9.2
+  Copyright (C) 2020 Free Software Foundation, Inc.
+  License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
+  This is free software: you are free to change and redistribute it.
+  There is NO WARRANTY, to the extent permitted by law.
+  Type "show copying" and "show warranty" for details.
+  This GDB was configured as "x86_64-linux-gnu".
+  Type "show configuration" for configuration details.
+  For bug reporting instructions, please see:
+  <http://www.gnu.org/software/gdb/bugs/>.
+  Find the GDB manual and other documentation resources online at:
+      <http://www.gnu.org/software/gdb/documentation/>.
+
+  For help, type "help".
+  Type "apropos word" to search for commands related to "word"...
+  Reading symbols from u-boot...
+  Remote debugging using :1234
+  0xbfc00000 in ?? ()
+  (gdb) c
+  Continuing.
diff --git a/roms/u-boot/doc/board/emulation/qemu-ppce500.rst b/roms/u-boot/doc/board/emulation/qemu-ppce500.rst
new file mode 100644
index 000000000..5de0aaf55
--- /dev/null
+++ b/roms/u-boot/doc/board/emulation/qemu-ppce500.rst
@@ -0,0 +1,93 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+
+QEMU PPC E500
+=============
+
+QEMU for PPC supports a special 'ppce500' machine designed for emulation and
+virtualization purposes. This document describes how to run U-Boot under it.
+
+The QEMU ppce500 machine models a generic PowerPC E500 virtual machine with
+support for the VirtIO standard networking device connected to the built-in
+PCI host controller. Some common devices in the CCSBAR space are modeled,
+including MPIC, 16550A UART devices, GPIO, I2C and PCI host controller with
+MSI delivery to MPIC. It uses device-tree to pass configuration information
+to guest software.
+
+Building U-Boot
+---------------
+Set the CROSS_COMPILE environment variable as usual, and run::
+
+    $ make qemu-ppce500_defconfig
+    $ make
+
+Running U-Boot
+--------------
+The minimal QEMU command line to get U-Boot up and running is::
+
+    $ qemu-system-ppc -nographic -machine ppce500 -bios u-boot
+
+You can also run U-Boot using 'qemu-system-ppc64'::
+
+    $ qemu-system-ppc64 -nographic -machine ppce500 -bios u-boot
+
+The commands above create a target with 128 MiB memory by default. A freely
+configurable amount of RAM can be created via the '-m' parameter. For example,
+'-m 2G' creates 2 GiB memory for the target, and the memory node in the
+embedded DTB created by QEMU reflects the new setting.
+
+Both qemu-system-ppc and qemu-system-ppc64 provide emulation for the following
+32-bit PowerPC CPUs:
+
+* e500v2
+* e500mc
+
+Additionally qemu-system-ppc64 provides support for the following 64-bit CPUs:
+
+* e5500
+* e6500
+
+The CPU type can be specified via the '-cpu' command line. If not specified,
+it creates a machine with e500v2 core. The following example shows an e6500
+based machine creation::
+
+    $ qemu-system-ppc64 -nographic -machine ppce500 -cpu e6500 -bios u-boot
+
+When U-Boot boots, you will notice the following::
+
+    CPU:   Unknown, Version: 0.0, (0x00000000)
+    Core:  e6500, Version: 2.0, (0x80400020)
+
+This is because we only specified a core name to QEMU and it does not have a
+meaningful SVR value which represents an actual SoC that integrates such core.
+You can specify a real world SoC device that QEMU has built-in support but all
+these SoCs are e500v2 based MPC85xx series, hence you cannot test anything
+built for P4080 (e500mc), P5020 (e5500) and T2080 (e6500).
+
+By default a VirtIO standard PCI networking device is connected as an ethernet
+interface at PCI address 0.1.0, but we can switch that to an e1000 NIC by::
+
+    $ qemu-system-ppc -nographic -machine ppce500 -bios u-boot \
+                      -nic tap,ifname=tap0,script=no,downscript=no,model=e1000
+
+The QEMU ppce500 machine can also dynamically instantiate an eTSEC device if
+"-device eTSEC" is given to QEMU::
+
+    -netdev tap,ifname=tap0,script=no,downscript=no,id=net0 -device eTSEC,netdev=net0
+
+VirtIO BLK driver is also enabled to support booting from a disk image where
+a kernel image is stored. Append the following to QEMU::
+
+    -drive file=disk.img,format=raw,id=disk0 -device virtio-blk-pci,drive=disk0
+
+Pericom pt7c4338 RTC is supported so we can use the 'date' command::
+
+    => date
+    Date: 2021-02-18 (Thursday)    Time: 15:33:20
+
+Additionally, 'poweroff' command is supported to shut down the QEMU session::
+
+    => poweroff
+    poweroff ...
+
+These have been tested in QEMU 5.2.0.
diff --git a/roms/u-boot/doc/board/emulation/qemu-riscv.rst b/roms/u-boot/doc/board/emulation/qemu-riscv.rst
new file mode 100644
index 000000000..4b8e104a2
--- /dev/null
+++ b/roms/u-boot/doc/board/emulation/qemu-riscv.rst
@@ -0,0 +1,115 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+QEMU RISC-V
+===========
+
+QEMU for RISC-V supports a special 'virt' machine designed for emulation and
+virtualization purposes. This document describes how to run U-Boot under it.
+Both 32-bit and 64-bit targets are supported, running in either machine or
+supervisor mode.
+
+The QEMU virt machine models a generic RISC-V virtual machine with support for
+the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
+16550A UART devices in addition to VirtIO and it also uses device-tree to pass
+configuration information to guest software. It implements RISC-V privileged
+architecture spec v1.10.
+
+Building U-Boot
+---------------
+Set the CROSS_COMPILE environment variable as usual, and run:
+
+- For 32-bit RISC-V::
+
+    make qemu-riscv32_defconfig
+    make
+
+- For 64-bit RISC-V::
+
+    make qemu-riscv64_defconfig
+    make
+
+This will compile U-Boot for machine mode. To build supervisor mode binaries,
+use the configurations qemu-riscv32_smode_defconfig and
+qemu-riscv64_smode_defconfig instead. Note that U-Boot running in supervisor
+mode requires a supervisor binary interface (SBI), such as RISC-V OpenSBI.
+
+Running U-Boot
+--------------
+The minimal QEMU command line to get U-Boot up and running is:
+
+- For 32-bit RISC-V::
+
+    qemu-system-riscv32 -nographic -machine virt -bios u-boot
+
+- For 64-bit RISC-V::
+
+    qemu-system-riscv64 -nographic -machine virt -bios u-boot
+
+The commands above create targets with 128MiB memory by default.
+A freely configurable amount of RAM can be created via the '-m'
+parameter. For example, '-m 2G' creates 2GiB memory for the target,
+and the memory node in the embedded DTB created by QEMU reflects
+the new setting.
+
+For instructions on how to run U-Boot in supervisor mode on QEMU
+with OpenSBI, see the documentation available with OpenSBI:
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
+These have been tested in QEMU 5.0.0.
+
+Running U-Boot SPL
+------------------
+In the default SPL configuration, U-Boot SPL starts in machine mode. U-Boot
+proper and OpenSBI (FW_DYNAMIC firmware) are bundled as FIT image and made
+available to U-Boot SPL. Both are then loaded by U-Boot SPL and the location
+of U-Boot proper is passed to OpenSBI. After initialization, U-Boot proper is
+started in supervisor mode by OpenSBI.
+
+OpenSBI must be compiled before compiling U-Boot. Version 0.4 and higher is
+supported by U-Boot. Clone the OpenSBI repository and run the following command.
+
+.. code-block:: console
+
+    git clone https://github.com/riscv/opensbi.git
+    cd opensbi
+    make PLATFORM=generic
+
+See the OpenSBI documentation for full details:
+https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
+
+To make the FW_DYNAMIC binary (build/platform/qemu/virt/firmware/fw_dynamic.bin)
+available to U-Boot, either copy it into the U-Boot root directory or specify
+its location with the OPENSBI environment variable. Afterwards, compile U-Boot
+with the following commands.
+
+- For 32-bit RISC-V::
+
+    make qemu-riscv32_spl_defconfig
+    make
+
+- For 64-bit RISC-V::
+
+    make qemu-riscv64_spl_defconfig
+    make
+
+The minimal QEMU commands to run U-Boot SPL in both 32-bit and 64-bit
+configurations are:
+
+- For 32-bit RISC-V::
+
+    qemu-system-riscv32 -nographic -machine virt -bios spl/u-boot-spl \
+    -device loader,file=u-boot.itb,addr=0x80200000
+
+- For 64-bit RISC-V::
+
+    qemu-system-riscv64 -nographic -machine virt -bios spl/u-boot-spl \
+    -device loader,file=u-boot.itb,addr=0x80200000
+
+An attached disk can be emulated by adding::
+
+    -device ich9-ahci,id=ahci \
+    -drive if=none,file=riscv64.img,format=raw,id=mydisk \
+    -device ide-hd,drive=mydisk,bus=ahci.0
+
+You will have to run 'scsi scan' to use it.
diff --git a/roms/u-boot/doc/board/emulation/qemu-x86.rst b/roms/u-boot/doc/board/emulation/qemu-x86.rst
new file mode 100644
index 000000000..db842f2ec
--- /dev/null
+++ b/roms/u-boot/doc/board/emulation/qemu-x86.rst
@@ -0,0 +1,118 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+QEMU x86
+========
+
+Build instructions for bare mode
+--------------------------------
+
+To build u-boot.rom for QEMU x86 targets, just simply run::
+
+   $ make qemu-x86_defconfig (for 32-bit)
+   $ make qemu-x86_64_defconfig (for 64-bit)
+   $ make all
+
+Note this default configuration will build a U-Boot for the QEMU x86 i440FX
+board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
+configuration during the 'make menuconfig' process like below::
+
+   Device Tree Control  --->
+       ...
+       (qemu-x86_q35) Default Device Tree for DT control
+
+Test with QEMU for bare mode
+----------------------------
+
+QEMU is a fancy emulator that can enable us to test U-Boot without access to
+a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
+U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows::
+
+   $ qemu-system-i386 -nographic -bios path/to/u-boot.rom
+
+This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
+also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
+also supported by U-Boot. To instantiate such a machine, call QEMU with::
+
+   $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
+
+Note by default QEMU instantiated boards only have 128 MiB system memory. But
+it is enough to have U-Boot boot and function correctly. You can increase the
+system memory by pass '-m' parameter to QEMU if you want more memory::
+
+   $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
+
+This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
+supports 3 GiB maximum system memory and reserves the last 1 GiB address space
+for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
+would be 3072.
+
+QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
+show QEMU's VGA console window. Note this will disable QEMU's serial output.
+If you want to check both consoles, use '-serial stdio'.
+
+Multicore is also supported by QEMU via '-smp n' where n is the number of cores
+to instantiate. Note, the maximum supported CPU number in QEMU is 255.
+
+U-Boot uses 'distro_bootcmd' by default when booting on x86 QEMU. This tries to
+load a boot script, kernel, and ramdisk from several different interfaces. For
+the default boot order, see 'qemu-x86.h'. For more information, see
+'README.distro'. Most Linux distros can be booted by writing a uboot script.
+For example, Debian (stretch) can be booted by creating a script file named
+'boot.txt' with the contents::
+
+   setenv bootargs root=/dev/sda1 ro
+   load ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} /vmlinuz
+   load ${devtype} ${devnum}:${distro_bootpart} ${ramdisk_addr_r} /initrd.img
+   zboot ${kernel_addr_r} - ${ramdisk_addr_r} ${filesize}
+
+Then compile and install it with::
+
+   $ apt install u-boot-tools && \
+     mkimage -T script -C none -n "Boot script" -d boot.txt /boot/boot.scr
+
+The fw_cfg interface in QEMU also provides information about kernel data,
+initrd, command-line arguments and more. U-Boot supports directly accessing
+these informtion from fw_cfg interface, which saves the time of loading them
+from hard disk or network again, through emulated devices. To use it , simply
+providing them in QEMU command line::
+
+   $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 \
+     -kernel /path/to/bzImage -append 'root=/dev/ram console=ttyS0' \
+     -initrd /path/to/initrd -smp 8
+
+Note: -initrd and -smp are both optional
+
+Then start QEMU, in U-Boot command line use the following U-Boot command to
+setup kernel::
+
+   => qfw
+   qfw - QEMU firmware interface
+
+   Usage:
+   qfw <command>
+       - list                             : print firmware(s) currently loaded
+       - cpus                             : print online cpu number
+       - load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot
+
+   => qfw load
+   loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
+
+Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
+'zboot' can be used to boot the kernel::
+
+   => zboot 01000000 - 04000000 1b1ab50
+
+To run 64-bit U-Boot, qemu-system-x86_64 should be used instead, e.g.::
+
+   $ qemu-system-x86_64 -nographic -bios path/to/u-boot.rom
+
+A specific CPU can be specified via the '-cpu' parameter but please make
+sure the specified CPU supports 64-bit like '-cpu core2duo'. Conversely
+'-cpu pentium' won't work for obvious reasons that the processor only
+supports 32-bit.
+
+Note 64-bit support is very preliminary at this point. Lots of features
+are missing in the 64-bit world. One notable feature is the VGA console
+support which is currently missing, so that you must specify '-nographic'
+to get 64-bit U-Boot up and running.
diff --git a/roms/u-boot/doc/board/emulation/qemu_capsule_update.rst b/roms/u-boot/doc/board/emulation/qemu_capsule_update.rst
new file mode 100644
index 000000000..33ce4bcd3
--- /dev/null
+++ b/roms/u-boot/doc/board/emulation/qemu_capsule_update.rst
@@ -0,0 +1,210 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020, Linaro Limited
+
+Enabling UEFI Capsule Update feature
+------------------------------------
+
+Support has been added for the UEFI capsule update feature which
+enables updating the U-Boot image using the UEFI firmware management
+protocol (fmp). The capsules are not passed to the firmware through
+the UpdateCapsule runtime service. Instead, capsule-on-disk
+functionality is used for fetching the capsule from the EFI System
+Partition (ESP) by placing the capsule file under the
+\EFI\UpdateCapsule directory.
+
+Currently, support has been added on the QEMU ARM64 virt platform for
+updating the U-Boot binary as a raw image when the platform is booted
+in non-secure mode, i.e. with CONFIG_TFABOOT disabled. For this
+configuration, the QEMU platform needs to be booted with
+'secure=off'. The U-Boot binary placed on the first bank of the NOR
+flash at offset 0x0. The U-Boot environment is placed on the second
+NOR flash bank at offset 0x4000000.
+
+The capsule update feature is enabled with the following configuration
+settings::
+
+    CONFIG_MTD=y
+    CONFIG_FLASH_CFI_MTD=y
+    CONFIG_CMD_MTDPARTS=y
+    CONFIG_CMD_DFU=y
+    CONFIG_DFU_MTD=y
+    CONFIG_PCI_INIT_R=y
+    CONFIG_EFI_CAPSULE_ON_DISK=y
+    CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y
+    CONFIG_EFI_CAPSULE_FIRMWARE=y
+    CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+    CONFIG_EFI_CAPSULE_FMP_HEADER=y
+
+In addition, the following config needs to be disabled(QEMU ARM specific)::
+
+    CONFIG_TFABOOT
+
+The capsule file can be generated by using the GenerateCapsule.py
+script in EDKII::
+
+    $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \
+    <capsule_file_name> --fw-version <val> --lsv <val> --guid \
+    e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose --update-image-index \
+    <val> --verbose <u-boot.bin>
+
+The above is a wrapper script(GenerateCapsule) which eventually calls
+the actual GenerateCapsule.py script.
+
+As per the UEFI specification, the capsule file needs to be placed on
+the EFI System Partition, under the \EFI\UpdateCapsule directory. The
+EFI System Partition can be a virtio-blk-device.
+
+Before initiating the firmware update, the efi variables BootNext,
+BootXXXX and OsIndications need to be set. The BootXXXX variable needs
+to be pointing to the EFI System Partition which contains the capsule
+file. The BootNext, BootXXXX and OsIndications variables can be set
+using the following commands::
+
+    => efidebug boot add -b 0 Boot0000 virtio 0:1 <capsule_file_name>
+    => efidebug boot next 0
+    => setenv -e -nv -bs -rt -v OsIndications =0x04
+    => saveenv
+
+Finally, the capsule update can be initiated with the following
+command::
+
+    => efidebug capsule disk-update
+
+The updated U-Boot image will be booted on subsequent boot.
+
+Enabling Capsule Authentication
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The UEFI specification defines a way of authenticating the capsule to
+be updated by verifying the capsule signature. The capsule signature
+is computed and prepended to the capsule payload at the time of
+capsule generation. This signature is then verified by using the
+public key stored as part of the X509 certificate. This certificate is
+in the form of an efi signature list (esl) file, which is embedded as
+part of the platform's device tree blob using the mkeficapsule
+utility.
+
+On the QEMU virt platforms, the device-tree is generated on the fly
+based on the devices configured. This device tree is then passed on to
+the various software components booting on the platform, including
+U-Boot. Therefore, on the QEMU virt platform, the signatute is
+embedded on an overlay. This overlay is then applied at runtime to the
+base platform device-tree. Steps needed for embedding the esl file in
+the overlay are highlighted below.
+
+The capsule authentication feature can be enabled through the
+following config, in addition to the configs listed above for capsule
+update::
+
+    CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+
+The public and private keys used for the signing process are generated
+and used by the steps highlighted below::
+
+    1. Install utility commands on your host
+       * OPENSSL
+       * efitools
+
+    2. Create signing keys and certificate files on your host
+
+        $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ \
+            -keyout CRT.key -out CRT.crt -nodes -days 365
+        $ cert-to-efi-sig-list CRT.crt CRT.esl
+
+        $ openssl x509 -in CRT.crt -out CRT.cer -outform DER
+        $ openssl x509 -inform DER -in CRT.cer -outform PEM -out CRT.pub.pem
+
+        $ openssl pkcs12 -export -out CRT.pfx -inkey CRT.key -in CRT.crt
+        $ openssl pkcs12 -in CRT.pfx -nodes -out CRT.pem
+
+The capsule file can be generated by using the GenerateCapsule.py
+script in EDKII::
+
+    $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \
+      <capsule_file_name> --monotonic-count <val> --fw-version \
+      <val> --lsv <val> --guid \
+      e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose \
+      --update-image-index <val> --signer-private-cert \
+      /path/to/CRT.pem --trusted-public-cert \
+      /path/to/CRT.pub.pem --other-public-cert /path/to/CRT.pub.pem \
+      <u-boot.bin>
+
+Place the capsule generated in the above step on the EFI System
+Partition under the EFI/UpdateCapsule directory
+
+For embedding the public key certificate, the following steps need to
+be followed::
+
+    1. Generate a skeleton overlay dts file, with a single fragment
+       node and an empty __overlay__ node
+
+       A typical skeleton overlay file will look like this
+
+       /dts-v1/;
+       /plugin/;
+
+       / {
+               fragment@0 {
+                       target-path = "/";
+                       __overlay__ {
+                       };
+               };
+       };
+
+
+    2. Convert the dts to a corresponding dtb with the following
+       command
+        ./scripts/dtc/dtc -@ -I dts -O dtb -o <ov_dtb_file_name> \
+        <dts_file>
+
+    3. Run the dtb file generated above through the mkeficapsule tool
+       in U-Boot
+        ./tools/mkeficapsule -O <pub_key.esl> -D <ov_dtb>
+
+Running the above command results in the creation of a 'signature'
+node in the dtb, under which the public key is stored as a
+'capsule-key' property. The '-O' option is to be used since the
+public key certificate(esl) file is being embedded in an overlay.
+
+The dtb file embedded with the certificate is now to be placed on an
+EFI System Partition. This would then be loaded and "merged" with the
+base platform flattened device-tree(dtb) at runtime.
+
+Build U-Boot with the following steps(QEMU ARM64)::
+
+    $ make qemu_arm64_defconfig
+    $ make menuconfig
+        Disable CONFIG_TFABOOT
+        Enable CONFIG_EFI_CAPSULE_AUTHENTICATE
+        Enable all configs needed for capsule update(listed above)
+    $ make all
+
+Boot the platform and perform the following steps on the U-Boot
+command line::
+
+    1. Enable capsule authentication by setting the following env
+       variable
+
+        => setenv capsule_authentication_enabled 1
+        => saveenv
+
+    2. Load the overlay dtb to memory and merge it with the base fdt
+
+        => fatload virtio 0:1 <$fdtovaddr> EFI/<ov_dtb_file>
+        => fdt addr $fdtcontroladdr
+        => fdt resize <size_of_ov_dtb_file>
+        => fdt apply <$fdtovaddr>
+
+    3. Set the following environment and UEFI boot variables
+
+        => setenv -e -nv -bs -rt -v OsIndications =0x04
+        => efidebug boot add -b 0 Boot0000 virtio 0:1 <capsule_file_name>
+        => efidebug boot next 0
+        => saveenv
+
+    4. Finally, the capsule update can be initiated with the following
+       command
+
+        => efidebug capsule disk-update
+
+On subsequent reboot, the platform should boot the updated U-Boot binary.
diff --git a/roms/u-boot/doc/board/freescale/b4860qds.rst b/roms/u-boot/doc/board/freescale/b4860qds.rst
new file mode 100644
index 000000000..de14d857b
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/b4860qds.rst
@@ -0,0 +1,453 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+B4860QDS
+========
+
+The B4860QDS is a Freescale reference board that hosts the B4860 SoC
+(and variants).
+
+B4860 Overview
+--------------
+The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
+StarCore and Power Architecture® cores. It targets the broadband wireless
+infrastructure and builds upon the proven success of the existing multicore
+DSPs and Power CPUs. It is designed to bolster the rapidly changing and
+expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
+
+The B4860 is a highly-integrated StarCore and Power Architecture processor that
+contains:
+
+* Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
+  clusters-each core runs up to 1.2 GHz, with an architecture highly optimized
+  for wireless base station applications
+* Four dual-thread e6500 Power Architecture processors organized in one
+  cluster-each core runs up to 1.8 GHz
+* Two DDR3/3L controllers for high-speed, industry-standard memory interface
+  each runs at up to 1866.67 MHz
+* MAPLE-B3 hardware acceleration-for forward error correction schemes including
+  Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
+  equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
+  FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
+  acceleration
+* CoreNet fabric that fully supports coherency using MESI protocol between the
+  e6500 cores, SC3900 FVP cores, memories and external interfaces.
+  CoreNet fabric interconnect runs at 667 MHz and supports coherent and
+  non-coherent out of order transactions with prioritization and bandwidth
+  allocation amongst CoreNet endpoints.
+* Data Path Acceleration Architecture, which includes the following:
+
+     * Frame Manager (FMan), which supports in-line packet parsing and general
+       classification to enable policing and QoS-based packet distribution
+     * Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
+       of queue management, task management, load distribution, flow ordering,
+       buffer management, and allocation tasks from the cores
+     * Security engine (SEC 5.3)-crypto-acceleration for protocols such as
+       IPsec, SSL, and 802.16
+     * RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound
+       and outbound). Supports types 5, 6 (outbound only)
+
+* Large internal cache memory with snooping and stashing capabilities for
+  bandwidth saving and high utilization of processor elements. The 9856-Kbyte
+  internal memory space includes the following:
+
+     * 32 Kbyte L1 ICache per e6500/SC3900 core
+     * 32 Kbyte L1 DCache per e6500/SC3900 core
+     * 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
+     * 2048 Kbyte unified L2 cache for the e6500 cluster
+     * Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
+
+* Sixteen 10-GHz SerDes lanes serving:
+
+     * Two Serial RapidIO interfaces
+     * Each supports up to 4 lanes and a total of up to 8 lanes
+
+* Up to 8-lanes Common Public Radio Interface (CPRI) controller for
+  glue-less antenna connection
+* Two 10-Gbit Ethernet controllers (10GEC)
+* Six 1G/2.5-Gbit Ethernet controllers for network communications
+* PCI Express controller
+* Debug (Aurora)
+* Two OCeaN DMAs
+* Various system peripherals
+* 182 32-bit timers
+
+B4860QDS Overview
+-----------------
+- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
+  ECC, 4 GB of memory in two ranks of 2 GB.
+- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
+  ECC, 2 GB of memory. Single rank.
+- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
+  16x16 switch VSC3316
+- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
+  8x8 switch VSC3308
+- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
+  B4860 UART port is available over USB-to-UART translator USB2SER or over
+  RS232 flat cable.
+- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45
+  copper connectors for Stand-alone mode and to the 1000Base-X over AMC
+  MicroTCA connector ports 0 and 2 for AMC mode.
+- The B4860 configuration may be loaded from nine bits coded reset configuration
+  reset source. The RCW source is set by appropriate DIP-switches.
+- 16-bit NOR Flash / PROMJet
+- QIXIS 8-bit NOR Flash Emulator
+- 8-bit NAND Flash
+- 24-bit SPI Flash
+- Long address I2C EEPROM
+- Available debug interfaces are:
+
+     - On-board eCWTAP controller with ETH and USB I/F
+     - JTAG/COP 16-pin header for any external TAP controller
+     - External JTAG source over AMC to support B2B configuration
+     - 70-pin Aurora debug connector
+
+- QIXIS (FPGA) logic:
+     - 2 KB internal memory space including
+
+- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
+  DDRCLK1,2 and RTCCLK.
+- Two 8T49N222A SerDes ref clock devices support two SerDes port clock
+  frequency - total four refclk, including CPRI clock scheme.
+
+
+B4420 Personality
+-----------------
+
+B4420 is a reduced personality of B4860 with less core/clusters(both SC3900
+and e6500), less DDR controllers, less serdes lanes, less SGMII interfaces
+and reduced target frequencies.
+
+Key differences between B4860 and B4420
+---------------------------------------
+
+B4420 has:
+
+1. Less e6500 cores: 1 cluster with 2 e6500 cores
+2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
+3. Single DDRC
+4. 2X 4 lane serdes
+5. 3 SGMII interfaces
+6. no sRIO
+7. no 10G
+
+B4860QDS Default Settings
+-------------------------
+
+Switch Settings
+^^^^^^^^^^^^^^^
+
+.. code-block:: none
+
+   SW1	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]
+   SW2	ON	ON	ON	ON	ON	ON	OFF	OFF
+   SW3	OFF	OFF	OFF	ON	OFF	OFF	ON	OFF
+   SW5	OFF	OFF	OFF	OFF	OFF	OFF	ON	ON
+
+Note:
+
+- PCIe slots modes: All the PCIe devices work as Root Complex.
+- Boot location: NOR flash.
+
+SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
+66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
+
+NAND boot::
+
+	SW1 [1.1] = 0
+	SW2 [1.1] = 1
+	SW3 [1:4] = 0001
+
+NOR boot::
+
+	SW1 [1.1] = 1
+	SW2 [1.1] = 0
+	SW3 [1:4] = 1000
+
+B4420QDS Default Settings
+-------------------------
+
+Switch Settings
+^^^^^^^^^^^^^^^
+
+.. code-block:: none
+
+   SW1	OFF[0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]
+   SW2	ON	OFF	ON	OFF	ON	ON	OFF	OFF
+   SW3	OFF	OFF	OFF	ON	OFF	OFF	ON	OFF
+   SW5	OFF	OFF	OFF	OFF	OFF	OFF	ON	ON
+
+Note:
+
+- PCIe slots modes: All the PCIe devices work as Root Complex.
+- Boot location: NOR flash.
+
+SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
+66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
+
+NAND boot::
+
+	SW1 [1.1] = 0
+	SW2 [1.1] = 1
+	SW3 [1:4] = 0001
+
+NOR boot::
+
+	SW1 [1.1] = 1
+	SW2 [1.1] = 0
+	SW3 [1:4] = 1000
+
+Memory map on B4860QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+=============   =============   =============== =======
+Start Address	End Address	Description	Size
+=============   =============   =============== =======
+0xF_FFDF_1000 	0xF_FFFF_FFFF	Free		2 MB
+0xF_FFDF_0000 	0xF_FFDF_0FFF	IFC - FPGA 	4 KB
+0xF_FF81_0000 	0xF_FFDE_FFFF	Free		5 MB
+0xF_FF80_0000	0xF_FF80_FFFF	IFC NAND Flash	64 KB
+0xF_FF00_0000	0xF_FF7F_FFFF	Free		8 MB
+0xF_FE00_0000 	0xF_FEFF_FFFF	CCSRBAR		16 MB
+0xF_F801_0000 	0xF_FDFF_FFFF	Free		95 MB
+0xF_F800_0000	0xF_F800_FFFF	PCIe I/O Space 	64 KB
+0xF_F600_0000 	0xF_F7FF_FFFF	QMAN s/w portal	32 MB
+0xF_F400_0000 	0xF_F5FF_FFFF	BMAN s/w portal	32 MB
+0xF_F000_0000 	0xF_F3FF_FFFF	Free		64 MB
+0xF_E800_0000 	0xF_EFFF_FFFF	IFC  NOR Flash 	128 MB
+0xF_E000_0000	0xF_E7FF_FFFF	Promjet		128 MB
+0xF_A0C0_0000 	0xF_DFFF_FFFF	Free		1012 MB
+0xF_A000_0000 	0xF_A0BF_FFFF	MAPLE0/1/2	12 MB
+0xF_0040_0000 	0xF_9FFF_FFFF	Free		12 GB
+0xF_0000_0000 	0xF_01FF_FFFF	DCSR		32 MB
+0xC_4000_0000 	0xE_FFFF_FFFF	Free		11 GB
+0xC_3000_0000 	0xC_3FFF_FFFF	sRIO-2 I/O 	256 MB
+0xC_2000_0000 	0xC_2FFF_FFFF	sRIO-1 I/O  	256 MB
+0xC_0000_0000	0xC_1FFF_FFFF	PCIe Mem Space 	512 MB
+0x1_0000_0000 	0xB_FFFF_FFFF	Free		44 GB
+0x0_8000_0000 	0x0_FFFF_FFFF	DDRC1		2 GB
+0x0_0000_0000 	0x0_7FFF_FFFF	DDRC2	  	2 GB
+=============   =============   =============== =======
+
+Memory map on B4420QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+=============   =============   =============== =======
+Start Address	End Address	Description	Size
+=============   =============   =============== =======
+0xF_FFDF_1000 	0xF_FFFF_FFFF	Free		2 MB
+0xF_FFDF_0000 	0xF_FFDF_0FFF	IFC - FPGA 	4 KB
+0xF_FF81_0000 	0xF_FFDE_FFFF	Free		5 MB
+0xF_FF80_0000	0xF_FF80_FFFF	IFC NAND Flash	64 KB
+0xF_FF00_0000	0xF_FF7F_FFFF	Free		8 MB
+0xF_FE00_0000 	0xF_FEFF_FFFF	CCSRBAR		16 MB
+0xF_F801_0000 	0xF_FDFF_FFFF	Free		95 MB
+0xF_F800_0000	0xF_F800_FFFF	PCIe I/O Space 	64 KB
+0xF_F600_0000 	0xF_F7FF_FFFF	QMAN s/w portal	32 MB
+0xF_F400_0000 	0xF_F5FF_FFFF	BMAN s/w portal	32 MB
+0xF_F000_0000 	0xF_F3FF_FFFF	Free		64 MB
+0xF_E800_0000 	0xF_EFFF_FFFF	IFC  NOR Flash 	128 MB
+0xF_E000_0000	0xF_E7FF_FFFF	Promjet		128 MB
+0xF_A0C0_0000 	0xF_DFFF_FFFF	Free		1012 MB
+0xF_A000_0000 	0xF_A0BF_FFFF	MAPLE0/1/2	12 MB
+0xF_0040_0000 	0xF_9FFF_FFFF	Free		12 GB
+0xF_0000_0000 	0xF_01FF_FFFF	DCSR		32 MB
+0xC_4000_0000 	0xE_FFFF_FFFF	Free		11 GB
+0xC_3000_0000 	0xC_3FFF_FFFF	sRIO-2 I/O 	256 MB
+0xC_2000_0000 	0xC_2FFF_FFFF	sRIO-1 I/O  	256 MB
+0xC_0000_0000	0xC_1FFF_FFFF	PCIe Mem Space 	512 MB
+0x1_0000_0000 	0xB_FFFF_FFFF	Free		44 GB
+0x0_0000_0000 	0x0_FFFF_FFFF	DDRC1		4 GB
+=============   =============   =============== =======
+
+NOR Flash memory Map on B4860 and B4420QDS
+------------------------------------------
+
+=============   =============   ==============================  =========
+ Start		 End		Definition			Size
+=============   =============   ==============================  =========
+0xEFF40000	0xEFFFFFFF	U-Boot (current bank)		768KB
+0xEFF20000	0xEFF3FFFF	U-Boot env (current bank)	128KB
+0xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
+0xEF300000	0xEFEFFFFF	rootfs (alternate bank)		12MB
+0xEE800000	0xEE8FFFFF	device tree (alternate bank)	1MB
+0xEE020000	0xEE6FFFFF	Linux.uImage (alternate bank)	6MB+896KB
+0xEE000000	0xEE01FFFF	RCW (alternate bank)		128KB
+0xEDF40000	0xEDFFFFFF	U-Boot (alternate bank)		768KB
+0xEDF20000	0xEDF3FFFF	U-Boot env (alternate bank)	128KB
+0xEDF00000	0xEDF1FFFF	FMAN ucode (alternate bank)	128KB
+0xED300000	0xEDEFFFFF	rootfs (current bank)		12MB
+0xEC800000	0xEC8FFFFF	device tree (current bank)	1MB
+0xEC020000	0xEC6FFFFF	Linux.uImage (current bank)	6MB+896KB
+0xEC000000	0xEC01FFFF	RCW (current bank)		128KB
+=============   =============   ==============================  =========
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to both B4860QDS and B4420QDS.
+
+U-Boot environment variable hwconfig
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The default hwconfig is:
+
+.. code-block:: none
+
+   hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=ulpi
+
+Note: For USB gadget set "dr_mode=peripheral"
+
+FMAN Ucode versions
+^^^^^^^^^^^^^^^^^^^
+
+fsl_fman_ucode_B4860_106_3_6.bin
+
+Switching to alternate bank
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Commands for switching to alternate bank.
+
+1. To change from vbank0 to vbank2
+
+.. code-block:: none
+
+   => qixis_reset altbank (it will boot using vbank2)
+
+2. To change from vbank2 to vbank0
+
+.. code-block:: none
+
+   => qixis reset (it will boot using vbank0)
+
+To change personality of board
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+For changing personality from B4860 to B4420
+
+1. Boot from vbank0
+2. Flash vbank2 with b4420 rcw and U-Boot
+3. Give following commands to uboot prompt
+
+.. code-block:: none
+
+   => mw.b ffdf0040 0x30;
+   => mw.b ffdf0010 0x00;
+   => mw.b ffdf0062 0x02;
+   => mw.b ffdf0050 0x02;
+   => mw.b ffdf0010 0x30;
+   => reset
+
+Note:
+
+- Power off cycle will lead to default switch settings.
+- 0xffdf0000 is the address of the QIXIS FPGA.
+
+Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+To change from NOR to NAND boot give following command on uboot prompt
+
+.. code-block:: none
+
+   => mw.b ffdf0040 0x30
+   => mw.b ffdf0010 0x00
+   => mw.b 0xffdf0050 0x08
+   => mw.b 0xffdf0060 0x82
+   => mw.b ffdf0061 0x00
+   => mw.b ffdf0010 0x30
+   => reset
+
+To change from NAND to NOR boot give following command on uboot prompt:
+
+.. code-block:: none
+
+   => mw.b ffdf0040 0x30
+   => mw.b ffdf0010 0x00
+   => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
+   => mw.b 0xffdf0060 0x12
+   => mw.b ffdf0061 0x01
+   => mw.b ffdf0010 0x30
+   => reset
+
+Note:
+
+- Power off cycle will lead to default switch settings.
+- 0xffdf0000 is the address of the QIXIS FPGA.
+
+Ethernet interfaces for B4860QDS
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Serdes protocosl tested:
+* 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
+* 0x2a, 0xb2 (serdes1, serdes2)
+
+When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
+SGMII on SGMII riser card.
+
+Under U-Boot these network interfaces are recognized as::
+
+   FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
+
+On Linux the interfaces are renamed as::
+
+   eth2 -> fm1-gb2
+   eth3 -> fm1-gb3
+   eth4 -> fm1-gb4
+   eth5 -> fm1-gb5
+
+RCW and Ethernet interfaces for B4420QDS
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Serdes protocosl tested:
+* 0x18, 0x9e (serdes1, serdes2)
+
+Under U-Boot these network interfaces are recognized as::
+
+   FM1@DTSEC3, FM1@DTSEC4 and  e1000#0.
+
+On Linux the interfaces are renamed as::
+
+   eth2 -> fm1-gb2
+   eth3 -> fm1-gb3
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+U-Boot(768 KB) from flash to DDR.
+Finally SPL transer control to U-Boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework during  boot:
+
++----------------------------------------------+
+|Area        | Address                         |
++----------------------------------------------+
+|Secure boot | 0xFFFC0000 (32KB)               |
+|headers     |                                 |
++----------------------------------------------+
+|GD, BD      | 0xFFFC8000 (4KB)                |
++----------------------------------------------+
+|ENV         | 0xFFFC9000 (8KB)                |
++----------------------------------------------+
+|HEAP        | 0xFFFCB000 (30KB)               |
++----------------------------------------------+
+|STACK       | 0xFFFD8000 (22KB)               |
++----------------------------------------------+
+|U-Boot SPL  | 0xFFFD8000 (160KB)              |
++----------------------------------------------+
+
+NAND Flash memory Map on B4860 and B4420QDS
+-------------------------------------------
+
+=============   =============   =============================   =====
+Start		End		Definition			Size
+=============   =============   =============================   =====
+0x000000	0x0FFFFF	U-Boot                          1MB
+0x140000	0x15FFFF	U-Boot env                      128KB
+0x1A0000	0x1BFFFF	FMAN Ucode                      128KB
+=============   =============   =============================   =====
diff --git a/roms/u-boot/doc/board/freescale/imx8mm_evk.rst b/roms/u-boot/doc/board/freescale/imx8mm_evk.rst
new file mode 100644
index 000000000..7fd3d7256
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imx8mm_evk.rst
@@ -0,0 +1,57 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mm_evk
+==========
+
+U-Boot for the NXP i.MX8MM EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.47_2.2.0
+
+.. code-block:: bash
+
+   $ make PLAT=imx8mm bl31
+   $ cp build/imx8mm/release/bl31.bin $(builddir)
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+   $ chmod +x firmware-imx-8.9.bin
+   $ ./firmware-imx-8.9
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ make imx8mm_evk_defconfig
+   $ export ATF_LOAD_ADDR=0x920000
+   $ make
+
+Burn the flash.bin to MicroSD card offset 33KB:
+
+.. code-block:: bash
+
+   $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=notrunc
+   $sudo dd if=u-boot.itb of=/dev/sdc bs=1024 seek=384 conv=sync
+
+Boot
+----
+Set Boot switch to SD boot
diff --git a/roms/u-boot/doc/board/freescale/imx8mn_evk.rst b/roms/u-boot/doc/board/freescale/imx8mn_evk.rst
new file mode 100644
index 000000000..9fbb94703
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imx8mn_evk.rst
@@ -0,0 +1,58 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mn_evk
+==========
+
+U-Boot for the NXP i.MX8MN EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get firmware-imx package
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.47_2.2.0
+
+.. code-block:: bash
+
+   $ make PLAT=imx8mn bl31
+   $ cp build/imx8mn/release/bl31.bin $(srctree)
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+   $ chmod +x firmware-imx-8.9.bin
+   $ ./firmware-imx-8.9
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/ddr4*.bin $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ make imx8mn_ddr4_evk_defconfig
+   $ export ATF_LOAD_ADDR=0x960000
+   $ make
+
+Burn the flash.bin to MicroSD card offset 32KB:
+
+.. code-block:: bash
+
+   $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+   $sudo dd if=u-boot.itb of=/dev/sd[x] bs=1024 seek=384 conv=notrunc
+
+Boot
+----
+
+Set Boot switch to SD boot
diff --git a/roms/u-boot/doc/board/freescale/imx8mp_evk.rst b/roms/u-boot/doc/board/freescale/imx8mp_evk.rst
new file mode 100644
index 000000000..609a29f3e
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imx8mp_evk.rst
@@ -0,0 +1,61 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mp_evk
+==========
+
+U-Boot for the NXP i.MX8MP EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get the firmware-imx package
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.70_2.3.0
+
+.. code-block:: bash
+
+   $ make PLAT=imx8mp bl31
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.10.bin
+   $ chmod +x firmware-imx-8.10.bin
+   $ ./firmware-imx-8.10.bin
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ make O=build imx8mp_evk_defconfig
+   $ cp ../imx-atf/build/imx8mp/release/bl31.bin ./build/bl31.bin
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin ./build/
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin ./build/
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin ./build/
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin ./build/
+   $ export ATF_LOAD_ADDR=0x970000
+   $ make O=build
+
+Burn the flash.bin to the MicroSD card at offset 32KB:
+
+.. code-block:: bash
+
+   $sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
+   $sudo dd if=build/u-boot.itb of=/dev/sd[x] bs=1K seek=384 conv=notrunc; sync
+
+Boot
+----
+
+Set Boot switch to SD boot
+Use /dev/ttyUSB2 for U-Boot console
diff --git a/roms/u-boot/doc/board/freescale/imx8mq_evk.rst b/roms/u-boot/doc/board/freescale/imx8mq_evk.rst
new file mode 100644
index 000000000..c269fdebe
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imx8mq_evk.rst
@@ -0,0 +1,56 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mq_evk
+==========
+
+U-Boot for the NXP i.MX8MQ EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get ddr and hdmi fimware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.47_2.2.0
+
+.. code-block:: bash
+
+   $ make PLAT=imx8mq bl31
+   $ cp build/imx8mq/release/bl31.bin $(builddir)
+
+Get the ddr and hdmi firmware
+-----------------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+   $ chmod +x firmware-imx-8.9.bin
+   $ ./firmware-imx-8.9.bin
+   $ cp firmware-imx-8.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ make imx8mq_evk_defconfig
+   $ make flash.bin
+
+Burn the flash.bin to MicroSD card offset 33KB:
+
+.. code-block:: bash
+
+   $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=notrunc
+
+Boot
+----
+Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
diff --git a/roms/u-boot/doc/board/freescale/imx8qxp_mek.rst b/roms/u-boot/doc/board/freescale/imx8qxp_mek.rst
new file mode 100644
index 000000000..215627cfa
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imx8qxp_mek.rst
@@ -0,0 +1,66 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8qxp_mek
+===========
+
+U-Boot for the NXP i.MX8QXP EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+.. code-block:: bash
+
+   $ git clone https://source.codeaurora.org/external/imx/imx-atf
+   $ cd imx-atf/
+   $ git checkout origin/imx_4.19.35_1.1.0 -b imx_4.19.35_1.1.0
+   $ make PLAT=imx8qx bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.2.7.1.bin
+   $ chmod +x imx-sc-firmware-1.2.7.1.bin
+   $ ./imx-sc-firmware-1.2.7.1.bin
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-2.3.1.bin
+   $ chmod +x imx-seco-2.3.1.bin
+   $ ./imx-seco-2.3.1.bin
+
+Copy the following binaries to U-Boot folder:
+
+.. code-block:: bash
+
+  $ cp imx-atf/build/imx8qx/release/bl31.bin .
+  $ cp imx-seco-2.3.1/firmware/seco/mx8qx-ahab-container.img ./ahab-container.img
+  $ cp imx-sc-firmware-1.2.7.1/mx8qx-mek-scfw-tcm.bin	.
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+  $ make imx8qxp_mek_defconfig
+  $ make flash.bin
+
+Flash the binary into the SD card
+---------------------------------
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+.. code-block:: bash
+
+   $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+
+Boot
+----
+Set Boot switch SW2: 1100.
diff --git a/roms/u-boot/doc/board/freescale/imxrt1020-evk.rst b/roms/u-boot/doc/board/freescale/imxrt1020-evk.rst
new file mode 100644
index 000000000..267f80c51
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imxrt1020-evk.rst
@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imxrt1020-evk
+=============
+
+How to use U-Boot on NXP i.MXRT1020 EVK
+---------------------------------------
+
+- Build U-Boot for i.MXRT1020 EVK:
+
+.. code-block:: bash
+
+   $ make mrproper
+   $ make imxrt1020-evk_defconfig
+   $ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+.. code-block:: bash
+
+   $sudo dd if=SPL of=/dev/sdX bs=1k seek=1 conv=notrunc; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+.. code-block:: bash
+
+   $sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128 conv=notrunc; sync
+
+- Jumper settings::
+
+   SW8: 0 1 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+  The USB console connector is the one close the ethernet connector
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
diff --git a/roms/u-boot/doc/board/freescale/imxrt1050-evk.rst b/roms/u-boot/doc/board/freescale/imxrt1050-evk.rst
new file mode 100644
index 000000000..c1fb48f0c
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imxrt1050-evk.rst
@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imxrt1050-evk
+=============
+
+How to use U-Boot on NXP i.MXRT1050 EVK
+---------------------------------------
+
+- Build U-Boot for i.MXRT1050 EVK:
+
+.. code-block:: bash
+
+   $ make mrproper
+   $ make imxrt1050-evk_defconfig
+   $ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+.. code-block:: bash
+
+   $sudo dd if=SPL of=/dev/sdX bs=1k seek=1 conv=notrunc; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+.. code-block:: bash
+
+   $sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128 conv=notrunc; sync
+
+- Jumper settings::
+
+   SW7: 1 0 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+  The USB console connector is the one close the ethernet connector
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
diff --git a/roms/u-boot/doc/board/freescale/index.rst b/roms/u-boot/doc/board/freescale/index.rst
new file mode 100644
index 000000000..313cf409a
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/index.rst
@@ -0,0 +1,20 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Freescale
+=========
+
+.. toctree::
+   :maxdepth: 2
+
+   b4860qds
+   imx8mm_evk
+   imx8mn_evk
+   imx8mp_evk
+   imx8mq_evk
+   imx8qxp_mek
+   imxrt1020-evk
+   imxrt1050-evk
+   mx6sabreauto
+   mx6sabresd
+   mx6ul_14x14_evk
+   mx6ullevk
diff --git a/roms/u-boot/doc/board/freescale/mx6sabreauto.rst b/roms/u-boot/doc/board/freescale/mx6sabreauto.rst
new file mode 100644
index 000000000..fe4cd9d21
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/mx6sabreauto.rst
@@ -0,0 +1,100 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6sabreauto
+============
+
+How to use and build U-Boot on mx6sabreauto
+-------------------------------------------
+
+mx6sabreauto_defconfig target supports mx6q/mx6dl/mx6qp sabreauto variants.
+
+In order to build it:
+
+.. code-block:: bash
+
+   $ make mx6sabreauto_defconfig
+   $ make
+
+This will generate the SPL and u-boot-dtb.img binaries.
+
+- Flash the SPL binary into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 conv=notrunc && sync
+
+- Flash the u-boot-dtb.img binary into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 conv=notrunc && sync
+
+Booting via Falcon mode
+-----------------------
+
+Write in mx6sabreauto_defconfig the following define below:
+
+CONFIG_SPL_OS_BOOT=y
+
+In order to build it:
+
+.. code-block:: bash
+
+   $ make mx6sabreauto_defconfig
+   $ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 conv=notrunc && sync
+
+- Flash the u-boot-dtb.img image into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdb bs=1K seek=69 conv=notrunc && sync
+
+Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there:
+
+.. code-block:: bash
+
+   $ sudo cp uImage /media/boot
+   $ sudo cp imx6dl-sabreauto.dtb /media/boot
+
+Create a partition for root file system and extract it there:
+
+.. code-block:: bash
+
+   $ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Load dtb file from boot partition::
+
+   # load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
+
+- Load kernel image from boot partition::
+
+   # load mmc 0:1 ${loadaddr} uImage
+
+- Write kernel at 2MB offset::
+
+   # mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs::
+
+   # setenv bootargs "console=ttymxc3,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args::
+
+   # spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)::
+
+   # mmc write 18000000 0x800 0x800
+
+- Restart the board and then SPL binary will launch the kernel directly.
diff --git a/roms/u-boot/doc/board/freescale/mx6sabresd.rst b/roms/u-boot/doc/board/freescale/mx6sabresd.rst
new file mode 100644
index 000000000..fe15ba7b7
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/mx6sabresd.rst
@@ -0,0 +1,132 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6sabresd
+==========
+
+How to use and build U-Boot on mx6sabresd
+-----------------------------------------
+
+The following methods can be used for booting mx6sabresd boards:
+
+1. Booting from SD card
+
+2. Booting from eMMC
+
+3. Booting via Falcon mode (SPL launches the kernel directly)
+
+
+1. Booting from SD card via SPL
+-------------------------------
+
+mx6sabresd_defconfig target supports mx6q/mx6dl/mx6qp sabresd variants.
+
+In order to build it:
+
+.. code-block:: bash
+
+   $ make mx6sabresd_defconfig
+   $ make
+
+This will generate the SPL and u-boot-dtb.img binaries.
+
+- Flash the SPL binary into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 conv=notrunc && sync
+
+- Flash the u-boot-dtb.img binary into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 conv=notrunc && sync
+
+2. Booting from eMMC
+--------------------
+
+.. code-block:: bash
+
+   $ make mx6sabresd_defconfig
+   $ make
+
+This will generate the SPL and u-boot-dtb.img binaries.
+
+- Boot first from SD card as shown in the previous section
+
+In U-boot change the eMMC partition config::
+
+   => mmc partconf 2 1 0 0
+
+Mount the eMMC in the host PC::
+
+   => ums 0 mmc 2
+
+- Flash SPL and u-boot-dtb.img binaries into the eMMC:
+
+.. code-block:: bash
+
+   $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 conv=notrunc && sync
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 conv=notrunc && sync
+
+Set SW6 to eMMC 8-bit boot: 11010110
+
+3. Booting via Falcon mode
+--------------------------
+
+.. code-block:: bash
+
+  $ make mx6sabresd_defconfig
+  $ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the SD card
+
+.. code-block:: bash
+
+   $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none conv=notrunc && sync
+
+- Flash the u-boot-dtb.img image into the SD card
+
+.. code-block:: bash
+
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none conv=notrunc && sync
+
+Create a partition for root file system and extract it there
+
+.. code-block:: bash
+
+   $ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Setup the IP server::
+
+   # setenv serverip <server_ip_address>
+
+- Download dtb file::
+
+   # dhcp ${fdt_addr} imx6q-sabresd.dtb
+
+- Download kernel image::
+
+   # dhcp ${loadaddr} uImage
+
+- Write kernel at 2MB offset::
+
+   # mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs::
+
+   # setenv bootargs "console=ttymxc0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args::
+
+   # spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)::
+
+   # mmc write 18000000 0x800 0x800
+
+- Press KEY_VOL_UP key, power up the board and then SPL binary will launch the kernel directly.
diff --git a/roms/u-boot/doc/board/freescale/mx6ul_14x14_evk.rst b/roms/u-boot/doc/board/freescale/mx6ul_14x14_evk.rst
new file mode 100644
index 000000000..8298bf8e1
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/mx6ul_14x14_evk.rst
@@ -0,0 +1,98 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6ul_14x14_evk
+===============
+
+How to use U-Boot on Freescale MX6UL 14x14 EVK
+-----------------------------------------------
+
+- Build U-Boot for MX6UL 14x14 EVK:
+
+.. code-block:: bash
+
+   $ make mrproper
+   $ make mx6ul_14x14_evk_defconfig
+   $ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+1. Booting via SDCard
+---------------------
+
+- Flash the SPL image into the micro SD card:
+
+.. code-block:: bash
+
+   sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1 conv=notrunc; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+.. code-block:: bash
+
+   sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69 conv=notrunc; sync
+
+- Jumper settings::
+
+   SW601: 0 0 1 0
+   Sw602: 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+  The USB console connector is the one close the push buttons
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
+
+2. Booting via Serial Download Protocol (SDP)
+---------------------------------------------
+
+The mx6ulevk board can boot from USB OTG port using the SDP, target will
+enter in SDP mode in case an SD Card is not connect or boot switches are
+set as below::
+
+   Sw602: 0 1
+   SW601: x x x x
+
+The following tools can be used to boot via SDP, for both tools you must
+connect an USB cable in USB OTG port.
+
+- Method 1: Universal Update Utility (uuu)
+
+The UUU binary can be downloaded in release tab from link below:
+https://github.com/NXPmicro/mfgtools
+
+The following script should be created to boot SPL + u-boot-dtb.img binaries:
+
+.. code-block:: bash
+
+   $ cat uuu_script
+     uuu_version 1.1.4
+
+     SDP: boot -f SPL
+     SDPU: write -f u-boot-dtb.img -addr 0x877fffc0
+     SDPU: jump -addr 0x877fffc0
+     SDPU: done
+
+Please note that the address above is calculated based on SYS_TEXT_BASE address:
+
+0x877fffc0 = 0x87800000 (SYS_TEXT_BASE) - 0x40 (U-Boot proper Header size)
+
+Power on the target and run the following command from U-Boot root directory:
+
+.. code-block:: bash
+
+   $ sudo ./uuu uuu_script
+
+- Method 2: imx usb loader tool (imx_usb):
+
+The imx_usb_loader tool can be downloaded in link below:
+https://github.com/boundarydevices/imx_usb_loader
+
+Build the source code and run the following commands from U-Boot root
+directory:
+
+.. code-block:: bash
+
+   $ sudo ./imx_usb SPL
+   $ sudo ./imx_usb u-boot-dtb.img
diff --git a/roms/u-boot/doc/board/freescale/mx6ullevk.rst b/roms/u-boot/doc/board/freescale/mx6ullevk.rst
new file mode 100644
index 000000000..a26248a1e
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/mx6ullevk.rst
@@ -0,0 +1,47 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6ullevk
+=========
+
+How to use U-Boot on Freescale MX6ULL 14x14 EVK
+-----------------------------------------------
+
+- First make sure you have installed the dtc package (device tree compiler):
+
+.. code-block:: bash
+
+   $ sudo apt-get install device-tree-compiler
+
+- Build U-Boot for MX6ULL 14x14 EVK:
+
+.. code-block:: bash
+
+   $ make mrproper
+   $ make mx6ull_14x14_evk_defconfig
+   $ make
+
+This generates the u-boot-dtb.imx image in the current directory.
+
+- Flash the u-boot-dtb.imx image into the micro SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=u-boot-dtb.imx of=/dev/sdb bs=1K seek=1 conv=notrunc && sync
+
+- Jumper settings::
+
+   SW601: 0 0 1 0
+   Sw602: 1 0
+
+Where 0 means bottom position and 1 means top position (from the switch label
+numbers reference).
+
+Connect the USB cable between the EVK and the PC for the console.
+(The USB console connector is the one close the push buttons)
+
+Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
+
+The link for the board: http://www.nxp.com/products/microcontrollers-and- \
+processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/ \
+i.mx6qp/evaluation-kit-for-the-i.mx-6ull-applications-processor:MCIMX6ULL-EVK
diff --git a/roms/u-boot/doc/board/google/chromebook_coral.rst b/roms/u-boot/doc/board/google/chromebook_coral.rst
new file mode 100644
index 000000000..4b585678d
--- /dev/null
+++ b/roms/u-boot/doc/board/google/chromebook_coral.rst
@@ -0,0 +1,442 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Chromebook Coral
+================
+
+Coral is a Chromebook (or really about 20 different Chromebooks) which use the
+Intel Apollo Lake platform (APL). The 'reef' Chromebooks use the same APL SoC so
+should also work. Some later ones based on Glacier Lake (GLK) need various
+changes in GPIOs, etc. but are very similar.
+
+It is hoped that this port can enable ports to embedded APL boards which are
+starting to appear.
+
+Note that booting U-Boot on APL is already supported by coreboot and
+Slim Bootloader. This documentation refers to a 'bare metal' port.
+
+
+Building
+--------
+
+First, you need the following binary blobs:
+
+   * descriptor.bin - Intel flash descriptor
+   * fitimage.bin - Base flash image structure
+   * fsp_m.bin - FSP-M, for setting up SDRAM
+   * fsp_s.bin - FSP-S, for setting up Silicon
+   * vbt.bin - for setting up display
+
+These binaries do not seem to be available publicly. If you have a ROM image,
+such as santa.bin then you can do this::
+
+  cbfstool santa.bin extract -n fspm.bin -f fsp-m.bin
+  cbfstool santa.bin extract -n fsps.bin -f fsp-s.bin
+  cbfstool santa.bin extract -n vbt-santa.bin -f vbt.bin
+  mkdir tmp
+  cd tmp
+  dump_fmap -x ../santa.bin
+  mv SI_DESC ../descriptor.bin
+  mv IFWI ../fitimage.bin
+
+Put all of these files in `board/google/chromebook_coral` so they can be found
+by the build.
+
+To build::
+
+  make O=/tmp/b/chromebook_coral chromebook_coral_defconfig
+  make O=/tmp/b/chromebook_coral -s -j30 all
+
+That should produce `/tmp/b/chrombook_coral/u-boot.rom` which you can use with
+a Dediprog em100::
+
+  em100 -s -c w25q128fw -d /tmp/b/chromebook_coral/u-boot.rom -r
+
+or you can use flashrom to write it to the board. If you do that, make sure you
+have a way to restore the old ROM without booting the board. Otherwise you may
+brick it. Having said that, you may find these instructions useful if you want
+to unbrick your device:
+
+  https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging.md
+
+You can buy Suzy-Q from Sparkfun:
+
+  https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/main/docs/ccd.md#suzyq-suzyqable
+
+Note that it will hang at the SPL prompt for 21 seconds. When booting into
+Chrome OS it will always select developer mode, so will wipe anything you have
+on the device if you let it proceed. You have two seconds in U-Boot to stop the
+auto-boot prompt and several seconds at the 'developer wipe' screen to stop it
+wiping the disk.
+
+Here is the console output::
+
+  U-Boot TPL 2021.04-rc1-00128-g344eefcdfec-dirty (Feb 11 2021 - 20:13:08 -0700)
+  Trying to boot from Mapped SPI
+
+  U-Boot SPL 2021.04-rc1-00128-g344eefcdfec-dirty (Feb 11 2021 - 20:13:08 -0700)
+  Trying to boot from Mapped SPI
+
+
+  U-Boot 2021.04-rc1-00128-g344eefcdfec-dirty (Feb 11 2021 - 20:13:08 -0700)
+
+  CPU:   Intel(R) Celeron(R) CPU N3450 @ 1.10GHz
+  DRAM:  3.9 GiB
+  MMC:   sdmmc@1b,0: 1, emmc@1c,0: 2
+  Video: 1024x768x32 @ b0000000
+  Model: Google Coral
+  Net:   No ethernet found.
+  SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+  Hit any key to stop autoboot:  0
+  cmdline=console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=${uuid}/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=${uuid} add_efi_memmap boot=local noresume noswap i915.modeset=1 Kernel command line: "console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=35c775e7-3735-d745-93e5-d9e0238f7ed0 add_efi_memmap boot=local noresume noswap i915.modeset=1 tpm_tis.force=1 tpm_tis.interrupts=0 nmi_watchdog=panic,lapic disablevmx=off  "
+  Setup located at 00090000:
+
+  ACPI RSDP addr      : 7991f000
+  E820: 14 entries
+                Addr              Size  Type
+      d0000000     1000000  <NULL>
+             0       a0000  RAM
+         a0000       60000  Reserved
+      7b000000      800000  Reserved
+      7b800000     4800000  Reserved
+      7ac00000      400000  Reserved
+        100000     ff00000  RAM
+      10000000     2151000  Reserved
+      12151000    68aaf000  RAM
+     100000000    80000000  RAM
+      e0000000    10000000  Reserved
+      7991bfd0     12e4030  Reserved
+      d0000000    10000000  Reserved
+      fed10000        8000  Reserved
+  Setup sectors       : 1e
+  Root flags          : 1
+  Sys size            : 63420
+  RAM size            : 0
+  Video mode          : ffff
+  Root dev            : 0
+  Boot flag           : 0
+  Jump                : 66eb
+  Header              : 53726448
+                        Kernel V2
+  Version             : 20d
+  Real mode switch    : 0
+  Start sys           : 1000
+  Kernel version      : 38cc
+     @00003acc:
+  Type of loader      : 80
+                        U-Boot, version 0
+  Load flags          : 81
+                      : loaded-high can-use-heap
+  Setup move size     : 8000
+  Code32 start        : 100000
+  Ramdisk image       : 0
+  Ramdisk size        : 0
+  Bootsect kludge     : 0
+  Heap end ptr        : 8e00
+  Ext loader ver      : 0
+  Ext loader type     : 0
+  Command line ptr    : 99000
+     console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=35c775e7-3735-d745-93e5-d9e0238f7ed0 add_efi_memmap boot=local noresume noswap i915.modeset=1 tpm_tis.force=1 tpm_tis.interrupts=0 nmi_watchdog=panic,lapic disablevmx=off
+  Initrd addr max     : 7fffffff
+  Kernel alignment    : 200000
+  Relocatable kernel  : 1
+  Min alignment       : 15
+                      : 200000
+  Xload flags         : 3
+                      : 64-bit-entry can-load-above-4gb
+  Cmdline size        : 7ff
+  Hardware subarch    : 0
+  HW subarch data     : 0
+  Payload offset      : 26e
+  Payload length      : 612045
+  Setup data          : 0
+  Pref address        : 1000000
+  Init size           : 1383000
+  Handover offset     : 0
+
+  Starting kernel ...
+
+  Timer summary in microseconds (17 records):
+         Mark    Elapsed  Stage
+            0          0  reset
+      155,279    155,279  TPL
+      237,088     81,809  end phase
+      237,533        445  SPL
+      816,456    578,923  end phase
+      817,357        901  board_init_f
+    1,061,751    244,394  board_init_r
+    1,402,435    340,684  id=64
+    1,430,071     27,636  main_loop
+    5,532,057  4,101,986  start_kernel
+
+  Accumulated time:
+                     685  dm_r
+                   2,817  fast_spi
+                  33,095  dm_spl
+                  52,468  dm_f
+                 208,242  fsp-m
+                 242,221  fsp-s
+                 332,710  mmap_spi
+
+
+Boot flow - TPL
+---------------
+
+Apollo Lake boots via an IFWI (Integrated Firmware Image). TPL is placed in
+this, in the IBBL entry.
+
+On boot, an on-chip microcontroller called the CSE (Converged Security Engine)
+sets up some SDRAM at ffff8000 and loads the TPL image to that address. The
+SRAM extends up to the top of 32-bit address space, but the last 2KB is the
+start16 region, so the TPL image must be 30KB at most, and CONFIG_TPL_TEXT_BASE
+must be ffff8000. Actually the start16 region is small and it could probably
+move from f800 to fe00, providing another 1.5KB, but TPL is only about 19KB so
+there is no need to change it at present. The size limit is enforced by
+CONFIG_TPL_SIZE_LIMIT to avoid producing images that won't boot.
+
+TPL (running from start.S) first sets up CAR (Cache-as-RAM) which provides
+larger area of RAM for use while booting. CAR is mapped at CONFIG_SYS_CAR_ADDR
+(fef00000) and is 768KB in size. It then sets up the stack in the botttom 64KB
+of this space (i.e. below fef10000). This means that the stack and early
+malloc() region in TPL can be 64KB at most.
+
+TPL operates without CONFIG_TPL_PCI enabled so PCI config access must use the
+x86-specific functions pci_x86_write_config(), etc. SPL creates a simple-bus
+device so that PCI devices are bound by driver model. Then arch_cpu_init_tpl()
+is called to early init on various devices. This includes placing PCI devices
+at hard-coded addresses in the memory map. PCI auto-config is not used.
+
+Most of the 16KB ROM is mapped into the very top of memory, except for the
+Intel descriptor (first 4KB) and the space for SRAM as above.
+
+TPL does not set up a bloblist since at present it does not have anything to
+pass to SPL.
+
+Once TPL is done it loads SPL from ROM using either the memory-mapped SPI or by
+using the Intel fast SPI driver. SPL is loaded into CAR, at the address given
+by CONFIG_SPL_TEXT_BASE, which is normally fef10000.
+
+Note that booting using the SPI driver results in an TPL image that is about
+26KB in size instead of 19KB. Also boot speed is worse by about 340ms. If you
+really want to use the driver, enable CONFIG_APL_SPI_FLASH_BOOT and set
+BOOT_FROM_FAST_SPI_FLASH to true[2].
+
+
+Boot flow - SPL
+---------------
+
+SPL (running from start_from_tpl.S) continues to use the same stack as TPL.
+It calls arch_cpu_init_spl() to set up a few devices, then init_dram() loads
+the FSP-M binary into CAR and runs to, to set up SDRAM. The address of the
+output 'HOB' list (Hand-off-block) is stored into gd->arch.hob_list for parsing.
+There is a 2GB chunk of SDRAM starting at 0 and the rest is at 4GB.
+
+PCI auto-config is not used in SPL either, but CONFIG_SPL_PCI is defined, so
+proper PCI access is available and normal dm_pci_read_config() calls can be
+used. However PCI auto-config is not used so the same static memory mapping set
+up by TPL is still active.
+
+SPL on x86 always runs with CONFIG_SPL_SEPARATE_BSS=y and BSS is at 120000
+(see u-boot-spl.lds). This works because SPL doesn't access BSS until after
+board_init_r(), as per the rules, and DRAM is available then.
+
+SPL sets up a bloblist and passes the SPL hand-off information to U-Boot proper.
+This includes a pointer to the HOB list as well as DRAM information. See
+struct arch_spl_handoff. The bloblist address is set by CONFIG_BLOBLIST_ADDR,
+normally 100000.
+
+SPL uses SPI flash to update the MRC caches in ROM. This speeds up subsequent
+boots. Be warned that SPL can take 30 seconds without this cache! This is a
+known issue with Intel SoCs with modern DRAM and apparently cannot be improved.
+The MRC caches are used to work around this.
+
+Once SPL is finished it loads U-Boot into SDRAM at CONFIG_SYS_TEXT_BASE, which
+is normally 1110000. Note that CAR is still active.
+
+
+Boot flow - U-Boot pre-relocation
+---------------------------------
+
+U-Boot (running from start_from_spl.S) starts running in RAM and uses the same
+stack as SPL. It does various init activities before relocation. Notably
+arch_cpu_init_dm() sets up the pin muxing for the chip using a very large table
+in the device tree.
+
+PCI auto-config is not used before relocation, but CONFIG_PCI of course is
+defined, so proper PCI access is available. The same static memory mapping set
+up by TPL is still active until relocation.
+
+As per usual, U-Boot allocates memory at the top of available RAM (a bit below
+2GB in this case) and copies things there ready to relocate itself. Notably
+reserve_arch() does not reserve space for the HOB list returned by FSP-M since
+this is already located in RAM.
+
+U-Boot then shuts down CAR and jumps to its relocated version.
+
+
+Boot flow - U-Boot post-relocation
+----------------------------------
+
+U-Boot starts up normally, running near the top of RAM. After driver model is
+running, arch_fsp_init_r() is called which loads and runs the FSP-S binary.
+This updates the HOB list to include graphics information, used by the fsp_video
+driver.
+
+PCI autoconfig is done and a few devices are probed to complete init. Most
+others are started only when they are used.
+
+Note that FSP-S is supposed to run after CAR has been shut down, which happens
+immediately before U-Boot starts up in its relocated position. Therefore we
+cannot run FSP-S before relocation. On the other hand we must run it before
+PCI auto-config is done, since FSP-S may show or hide devices. The first device
+that probes PCI after relocation is the serial port, in initr_serial(), so FSP-S
+must run before that. A corollary is that loading FSP-S must be done without
+using the SPI driver, to avoid probing PCI and causing an autoconfig, so
+memory-mapped reading is always used for FSP-S.
+
+It would be possible to tear down CAR in SPL instead of U-Boot. The SPL handoff
+information could make sure it does not include any pointers into CAR (in fact
+it doesn't). But tearing down CAR in U-Boot allows the initial state used by TPL
+and SPL to be read by U-Boot, which seems useful. It also matches how older
+platforms start up (those that don't use SPL).
+
+
+Performance
+-----------
+
+Bootstage is used through all phases of U-Boot to keep accurate timimgs for
+boot. Use 'bootstage report' in U-Boot to see the report, e.g.::
+
+    Timer summary in microseconds (16 records):
+           Mark    Elapsed  Stage
+              0          0  reset
+        155,325    155,325  TPL
+        204,014     48,689  end TPL
+        204,385        371  SPL
+        738,633    534,248  end SPL
+        739,161        528  board_init_f
+        842,764    103,603  board_init_r
+      1,166,233    323,469  main_loop
+      1,166,283         50  id=175
+
+    Accumulated time:
+                        62  fast_spi
+                       202  dm_r
+                     7,779  dm_spl
+                    15,555  dm_f
+                   208,357  fsp-m
+                   239,847  fsp-s
+                   292,143  mmap_spi
+
+CPU performance is about 3500 DMIPS::
+
+    => dhry
+    1000000 iterations in 161 ms: 6211180/s, 3535 DMIPS
+
+
+Partial memory map
+------------------
+
+::
+
+    ffffffff       Top of ROM (and last byte of 32-bit address space)
+    ffff8000       TPL loaded here (from IFWI)
+    ff000000       Bottom of ROM
+    fefc0000       Top of CAR region
+    fef96000       Stack for FSP-M
+    fef40000 59000 FSP-M (also VPL loads here)
+    fef11000       SPL loaded here
+    fef10000       CONFIG_BLOBLIST_ADDR
+    fef10000       Stack top in TPL, SPL and U-Boot before relocation
+    fef00000  1000 CONFIG_BOOTSTAGE_STASH_ADDR
+    fef00000       Base of CAR region
+
+       30000       AP_DEFAULT_BASE (used to start up additional CPUs)
+       f0000       CONFIG_ROM_TABLE_ADDR
+      120000       BSS (defined in u-boot-spl.lds)
+      200000       FSP-S (which is run after U-Boot is relocated)
+     1110000       CONFIG_SYS_TEXT_BASE
+
+
+Speeding up SPL for development
+-------------------------------
+
+The 21-second wait for memory training is annoying during development, since
+every new image incurs this cost when booting. There is no cache to fall back on
+since that area of the image is empty on start-up.
+
+You can add suitable cache contents to the image to fix this, for development
+purposes only, like this::
+
+   # Read the image back after booting through SPL
+   em100 -s -c w25q128fw -u image.bin
+
+   # Extract the two cache regions
+   binman extract -i image.bin extra *cache
+
+   # Move them into the source directory
+   mv *cache board/google/chromebook_coral
+
+Then add something like this to the devicetree::
+
+  #if IS_ENABLED(CONFIG_HAVE_MRC) || IS_ENABLED(CONFIG_FSP_VERSION2)
+     /* Provide initial contents of the MRC data for faster development */
+     rw-mrc-cache {
+        type = "blob";
+        /* Mirror the offset in spi-flash@0 */
+        offset = <0xff8e0000>;
+        size = <0x10000>;
+        filename = "board/google/chromebook_coral/rw-mrc-cache";
+     };
+     rw-var-mrc-cache {
+        type = "blob";
+        size = <0x1000>;
+        filename = "board/google/chromebook_coral/rw-var-mrc-cache";
+     };
+  #endif
+
+This tells binman to put the cache contents in the same place as the
+`rw-mrc-cache` and `rw-var-mrc-cache` regions defined by the SPI-flash driver.
+
+
+Supported peripherals
+---------------------
+
+The following have U-Boot drivers:
+
+   - UART
+   - SPI flash
+   - Video
+   - MMC (dev 0) and micro-SD (dev 1)
+   - Chrome OS EC
+   - Cr50 (security chip)
+   - Keyboard
+   - USB
+
+
+To do
+-----
+
+- Finish peripherals
+   - Sound (Intel I2S support exists, but need da7219 driver)
+- Use FSP-T binary instead of our own CAR implementation
+- Use the official FSP package instead of the coreboot one
+- Suspend / resume
+- Fix MMC which seems to try to read even though the card is empty
+- Fix USB3 crash "WARN halted endpoint, queueing URB anyway."
+
+
+Credits
+-------
+
+This is a spare-time project conducted slowly over a long period of time.
+
+Much of the code for this port came from Coreboot, an open-source firmware
+project similar to U-Boot's SPL in terms of features.
+
+Also see [2] for information about the boot flow used by coreboot. It is
+similar, but has an extra postcar stage. U-Boot doesn't need this since it
+supports relocating itself in memory.
+
+
+[2] Intel PDF https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf
diff --git a/roms/u-boot/doc/board/google/chromebook_link.rst b/roms/u-boot/doc/board/google/chromebook_link.rst
new file mode 100644
index 000000000..16080304d
--- /dev/null
+++ b/roms/u-boot/doc/board/google/chromebook_link.rst
@@ -0,0 +1,34 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Chromebook Link
+===============
+
+First, you need the following binary blobs:
+
+   * descriptor.bin - Intel flash descriptor
+   * me.bin - Intel Management Engine
+   * mrc.bin - Memory Reference Code, which sets up SDRAM
+   * video ROM - sets up the display
+
+You can get these binary blobs by::
+
+   $ git clone http://review.coreboot.org/p/blobs.git
+   $ cd blobs
+
+Find the following files:
+
+   * ./mainboard/google/link/descriptor.bin
+   * ./mainboard/google/link/me.bin
+   * ./northbridge/intel/sandybridge/systemagent-r6.bin
+
+The 3rd one should be renamed to mrc.bin.
+As for the video ROM, you can get it `here`_ and rename it to vga.bin.
+Make sure all these binary blobs are put in the board directory.
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+   $ make chromebook_link_defconfig
+   $ make all
+
+.. _here: http://www.coreboot.org/~stepan/pci8086,0166.rom
diff --git a/roms/u-boot/doc/board/google/chromebook_samus.rst b/roms/u-boot/doc/board/google/chromebook_samus.rst
new file mode 100644
index 000000000..eab1128e4
--- /dev/null
+++ b/roms/u-boot/doc/board/google/chromebook_samus.rst
@@ -0,0 +1,101 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Chromebook Samus
+================
+
+First, you need the following binary blobs:
+
+   * descriptor.bin - Intel flash descriptor
+   * me.bin - Intel Management Engine
+   * mrc.bin - Memory Reference Code, which sets up SDRAM
+   * refcode.elf - Additional Reference code
+   * vga.bin - video ROM, which sets up the display
+
+If you have a samus you can obtain them from your flash, for example, in
+developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
+log in as 'root')::
+
+   cd /tmp
+   flashrom -w samus.bin
+   scp samus.bin username@ip_address:/path/to/somewhere
+
+If not see the coreboot tree where you can use::
+
+   bash crosfirmware.sh samus
+
+to get the image. There is also an 'extract_blobs.sh' scripts that you can use
+on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
+
+Then 'ifdtool -x samus.bin' on your development machine will produce::
+
+   flashregion_0_flashdescriptor.bin
+   flashregion_1_bios.bin
+   flashregion_2_intel_me.bin
+
+Rename flashregion_0_flashdescriptor.bin to descriptor.bin
+Rename flashregion_2_intel_me.bin to me.bin
+You can ignore flashregion_1_bios.bin - it is not used.
+
+To get the rest, use 'cbfstool samus.bin print'::
+
+   samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
+   alignment: 64 bytes, architecture: x86
+
+============================   ========   ===========  ======
+Name                           Offset     Type         Size
+============================   ========   ===========  ======
+cmos_layout.bin                0x700000   cmos_layout  1164
+pci8086,0406.rom               0x7004c0   optionrom    65536
+spd.bin                        0x710500   (unknown)    4096
+cpu_microcode_blob.bin         0x711540   microcode    70720
+fallback/romstage              0x722a00   stage        54210
+fallback/ramstage              0x72fe00   stage        96382
+config                         0x7476c0   raw          6075
+fallback/vboot                 0x748ec0   stage        15980
+fallback/refcode               0x74cd80   stage        75578
+fallback/payload               0x75f500   payload      62878
+u-boot.dtb                     0x76eb00   (unknown)    5318
+(empty)                        0x770000   null         196504
+mrc.bin                        0x79ffc0   (unknown)    222876
+(empty)                        0x7d66c0   null         167320
+============================   ========   ===========  ======
+
+You can extract what you need::
+
+   cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
+   cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
+   cbfstool samus.bin extract -n mrc.bin -f mrc.bin
+   cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
+
+Note that the -U flag is only supported by the latest cbfstool. It unpacks
+and decompresses the stage to produce a coreboot rmodule. This is a simple
+representation of an ELF file. You need the patch "Support decoding a stage
+with compression".
+
+Put all 5 files into board/google/chromebook_samus.
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+   $ make chromebook_samus_defconfig
+   $ make all
+
+If you are using em100, then this command will flash write -Boot::
+
+   em100 -s -d filename.rom -c W25Q64CV -r
+
+Flash map for samus / broadwell:
+
+   :fffff800:	SYS_X86_START16
+   :ffff0000:	RESET_SEG_START
+   :fffd8000:	TPL_TEXT_BASE
+   :fffa0000:	X86_MRC_ADDR
+   :fff90000:	VGA_BIOS_ADDR
+   :ffed0000:	SYS_TEXT_BASE
+   :ffea0000:	X86_REFCODE_ADDR
+   :ffe70000:	SPL_TEXT_BASE
+   :ffbf8000:	CONFIG_ENV_OFFSET (environemnt offset)
+   :ffbe0000:	rw-mrc-cache (Memory-reference-code cache)
+   :ffa00000:	<spare>
+   :ff801000:	intel-me (address set by descriptor.bin)
+   :ff800000:	intel-descriptor
diff --git a/roms/u-boot/doc/board/google/index.rst b/roms/u-boot/doc/board/google/index.rst
new file mode 100644
index 000000000..061c79771
--- /dev/null
+++ b/roms/u-boot/doc/board/google/index.rst
@@ -0,0 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Google
+======
+
+.. toctree::
+   :maxdepth: 2
+
+   chromebook_coral
+   chromebook_link
+   chromebook_samus
diff --git a/roms/u-boot/doc/board/index.rst b/roms/u-boot/doc/board/index.rst
new file mode 100644
index 000000000..747511f7d
--- /dev/null
+++ b/roms/u-boot/doc/board/index.rst
@@ -0,0 +1,29 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Board-specific doc
+==================
+
+.. toctree::
+   :maxdepth: 2
+
+   actions/index
+   advantech/index
+   AndesTech/index
+   amlogic/index
+   atmel/index
+   congatec/index
+   coreboot/index
+   emulation/index
+   freescale/index
+   google/index
+   intel/index
+   kontron/index
+   microchip/index
+   rockchip/index
+   sifive/index
+   sipeed/index
+   st/index
+   tbs/index
+   toradex/index
+   xen/index
+   xilinx/index
diff --git a/roms/u-boot/doc/board/intel/bayleybay.rst b/roms/u-boot/doc/board/intel/bayleybay.rst
new file mode 100644
index 000000000..db97f645f
--- /dev/null
+++ b/roms/u-boot/doc/board/intel/bayleybay.rst
@@ -0,0 +1,29 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Bayley Bay CRB
+==============
+
+This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
+Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
+the time of writing). Put it in the corresponding board directory and rename
+it to fsp.bin.
+
+Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
+board directory as vga.bin.
+
+You still need two more binary blobs. For Bayley Bay, they can be extracted
+from the sample SPI image provided in the FSP (SPI.bin at the time of writing)::
+
+   $ ./tools/ifdtool -x BayleyBay/SPI.bin
+   $ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin
+   $ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+   $ make bayleybay_defconfig
+   $ make all
+
+Note that the debug version of the FSP is bigger in size. If this version
+is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
+the default value 0xfffc0000.
diff --git a/roms/u-boot/doc/board/intel/cherryhill.rst b/roms/u-boot/doc/board/intel/cherryhill.rst
new file mode 100644
index 000000000..151f0613f
--- /dev/null
+++ b/roms/u-boot/doc/board/intel/cherryhill.rst
@@ -0,0 +1,30 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Cherry Hill CRB
+===============
+
+This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
+put the .fd file to the board directory and rename it to fsp.bin.
+
+Extract descriptor.bin and me.bin from the original BIOS on the board using
+ifdtool and put them to the board directory as well.
+
+Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
+image for the integrated graphics device. Instead a new binary called Video
+BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
+vbt.bin if you want graphics support in U-Boot.
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+   $ make cherryhill_defconfig
+   $ make all
+
+An important note for programming u-boot.rom to the on-board SPI flash is that
+you need make sure the SPI flash's 'quad enable' bit in its status register
+matches the settings in the descriptor.bin, otherwise the board won't boot.
+
+For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
+status register by DediProg in: Config > Modify Status Register > Write Status
+Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
+persists in SPI flash part regardless of the u-boot.rom image burned.
diff --git a/roms/u-boot/doc/board/intel/cougarcanyon2.rst b/roms/u-boot/doc/board/intel/cougarcanyon2.rst
new file mode 100644
index 000000000..5e3e7a182
--- /dev/null
+++ b/roms/u-boot/doc/board/intel/cougarcanyon2.rst
@@ -0,0 +1,24 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Cougar Canyon 2 CRB
+===================
+
+This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
+with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
+website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
+time of writing) in the board directory and rename it to fsp.bin.
+
+Now build U-Boot and obtain u-boot.rom::
+
+   $ make cougarcanyon2_defconfig
+   $ make all
+
+The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
+the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
+and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
+flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
+this image to the SPI-0 flash according to the board manual just once and we are
+all set. For programming U-Boot we just need to program SPI-1 flash. Since the
+default u-boot.rom image for this board is set to 2MB, it should be programmed
+to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
diff --git a/roms/u-boot/doc/board/intel/crownbay.rst b/roms/u-boot/doc/board/intel/crownbay.rst
new file mode 100644
index 000000000..4fcf9811c
--- /dev/null
+++ b/roms/u-boot/doc/board/intel/crownbay.rst
@@ -0,0 +1,43 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Crown Bay CRB
+=============
+
+U-Boot support of Intel `Crown Bay`_ board relies on a binary blob called
+Firmware Support Package (`FSP`_) to perform all the necessary initialization
+steps as documented in the BIOS Writer Guide, including initialization of the
+CPU, memory controller, chipset and certain bus interfaces.
+
+Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
+install it on your host and locate the FSP binary blob. Note this platform
+also requires a Chipset Micro Code (CMC) state machine binary to be present in
+the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
+in this FSP package too.
+
+   * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
+   * ./Microcode/C0_22211.BIN
+
+Rename the first one to fsp.bin and second one to cmc.bin and put them in the
+board directory.
+
+Note the FSP release version 001 has a bug which could cause random endless
+loop during the FspInit call. This bug was published by Intel although Intel
+did not describe any details. We need manually apply the patch to the FSP
+binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
+binary, change the following five bytes values from orginally E8 42 FF FF FF
+to B8 00 80 0B 00.
+
+As for the video ROM, you need manually extract it from the Intel provided
+BIOS for Crown Bay `here`_, using the AMI `MMTool`_. Check PCI option
+ROM ID 8086:4108, extract and save it as vga.bin in the board directory.
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+   $ make crownbay_defconfig
+   $ make all
+
+.. _`Crown Bay`: http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
+.. _`FSP`: http://www.intel.com/fsp
+.. _`here`: http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html
+.. _`MMTool`: http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/
diff --git a/roms/u-boot/doc/board/intel/edison.rst b/roms/u-boot/doc/board/intel/edison.rst
new file mode 100644
index 000000000..5a65673d1
--- /dev/null
+++ b/roms/u-boot/doc/board/intel/edison.rst
@@ -0,0 +1,170 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+Edison
+======
+
+Build Instructions for U-Boot as main bootloader
+------------------------------------------------
+
+Simple you can build U-Boot and obtain u-boot.bin::
+
+   $ make edison_defconfig
+   $ make all
+
+Updating U-Boot on Edison
+-------------------------
+
+By default Intel Edison boards are shipped with preinstalled heavily
+patched U-Boot v2014.04. Though it supports DFU which we may be able to
+use.
+
+1. Prepare u-boot.bin as described in chapter above. You still need one
+   more step (if and only if you have original U-Boot), i.e. run the
+   following command::
+
+     $ truncate -s %4096 u-boot.bin
+
+2. Run your board and interrupt booting to U-Boot console. In the console
+   call::
+
+     => run do_force_flash_os
+
+3. Wait for few seconds, it will prepare environment variable and runs
+   DFU. Run DFU command from the host system::
+
+     $ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin
+
+4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and
+   reset the board::
+
+     => reset
+
+Updating U-Boot using xFSTK
+---------------------------
+
+You can also update U-Boot using the xfstk-dldr-solo tool if you can build it.
+One way to do that is to follow the `xFSTK`_ instructions. In short, after you
+install all necessary dependencies and clone repository, it will look like this:
+
+.. code-block:: sh
+
+  cd xFSTK
+  export DISTRIBUTION_NAME=ubuntu20.04
+  export BUILD_VERSION=1.8.5
+  git checkout v$BUILD_VERSION
+  ...
+
+Once you have built it, you can copy xfstk-dldr-solo to /usr/local/bin and
+libboost_program_options.so.1.54.0 to /usr/lib/i386-linux-gnu/ and with luck
+it will work. You might find this `drive`_ helpful.
+
+If it does, then you can download and unpack the Edison recovery image,
+install dfu-util, reset your board and flash U-Boot like this:
+
+.. code-block:: sh
+
+  xfstk-dldr-solo --gpflags 0x80000007 \
+      --osimage u-boot-edison.img \
+      --fwdnx recover/edison_dnx_fwr.bin \
+      --fwimage recover/edison_ifwi-dbg-00.bin \
+      --osdnx recover/edison_dnx_osr.bin
+
+This should show the following
+
+.. code-block:: none
+
+  XFSTK Downloader Solo 1.8.5
+  Copyright (c) 2015 Intel Corporation
+  Build date and time: Aug 15 2020 15:07:13
+
+  .Intel SoC Device Detection Found
+  Parsing Commandline....
+  Registering Status Callback....
+  .Initiating Download Process....
+  .......(lots of dots)........XFSTK-STATUS--Reconnecting to device - Attempt #1
+  .......(even more dots)......................
+
+You have about 10 seconds after resetting the board to type the above command.
+If you want to check if the board is ready, type:
+
+.. code-block:: none
+
+  lsusb | egrep "8087|8086"
+  Bus 001 Device 004: ID 8086:e005 Intel Corp.
+
+If you see a device with the same ID as above, the board is waiting for your
+command.
+
+After about 5 seconds you should see some console output from the board:
+
+.. code-block:: none
+
+  ******************************
+  PSH KERNEL VERSION: b0182b2b
+  		WR: 20104000
+  ******************************
+
+  SCU IPC: 0x800000d0  0xfffce92c
+
+  PSH miaHOB version: TNG.B0.VVBD.0000000c
+
+  microkernel built 11:24:08 Feb  5 2015
+
+  ******* PSH loader *******
+  PCM page cache size = 192 KB
+  Cache Constraint = 0 Pages
+  Arming IPC driver ..
+  Adding page store pool ..
+  PagestoreAddr(IMR Start Address) = 0x04899000
+  pageStoreSize(IMR Size)          = 0x00080000
+
+  *** Ready to receive application ***
+
+After another 10 seconds the xFSTK tool completes and the board resets. About
+10 seconds after that should see the above message again and then within a few
+seconds U-Boot should start on your board:
+
+.. code-block:: none
+
+  U-Boot 2020.10-rc3 (Sep 03 2020 - 18:44:28 -0600)
+
+  CPU:   Genuine Intel(R) CPU   4000  @  500MHz
+  DRAM:  980.6 MiB
+  WDT:   Started with servicing (60s timeout)
+  MMC:   mmc@ff3fc000: 0, mmc@ff3fa000: 1
+  Loading Environment from MMC... OK
+  In:    serial
+  Out:   serial
+  Err:   serial
+  Saving Environment to MMC... Writing to redundant MMC(0)... OK
+  Saving Environment to MMC... Writing to MMC(0)... OK
+  Net:   No ethernet found.
+  Hit any key to stop autoboot:  0
+  Target:blank
+  Partitioning using GPT
+  Writing GPT: success!
+  Saving Environment to MMC... Writing to redundant MMC(0)... OK
+  Flashing already done...
+  5442816 bytes read in 238 ms (21.8 MiB/s)
+  Valid Boot Flag
+  Setup Size = 0x00003c00
+  Magic signature found
+  Using boot protocol version 2.0c
+  Linux kernel version 3.10.17-poky-edison+ (ferry@kalamata) #1 SMP PREEMPT Mon Jan 11 14:54:18 CET 2016
+  Building boot_params at 0x00090000
+  Loading bzImage at address 100000 (5427456 bytes)
+  Magic signature found
+  Kernel command line: "rootwait ..."
+  Magic signature found
+
+  Starting kernel ...
+
+  ...
+
+  Poky (Yocto Project Reference Distro) 1.7.2 edison ttyMFD2
+
+  edison login:
+
+.. _xFSTK: https://github.com/edison-fw/xFSTK
+.. _drive: https://drive.google.com/drive/u/0/folders/1URPHrOk9-UBsh8hjv-7WwC0W6Fy61uAJ
diff --git a/roms/u-boot/doc/board/intel/galileo.rst b/roms/u-boot/doc/board/intel/galileo.rst
new file mode 100644
index 000000000..f51a06bb9
--- /dev/null
+++ b/roms/u-boot/doc/board/intel/galileo.rst
@@ -0,0 +1,22 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
+
+Galileo
+=======
+
+Only one binary blob is needed for Remote Management Unit (RMU) within Intel
+Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
+needed by the Quark SoC itself.
+
+You can get the binary blob from Quark Board Support Package from Intel website:
+
+   * ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
+
+Rename the file and put it to the board directory by::
+
+   $ cp RMU.bin board/intel/galileo/rmu.bin
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+   $ make galileo_defconfig
+   $ make all
diff --git a/roms/u-boot/doc/board/intel/index.rst b/roms/u-boot/doc/board/intel/index.rst
new file mode 100644
index 000000000..f545dee87
--- /dev/null
+++ b/roms/u-boot/doc/board/intel/index.rst
@@ -0,0 +1,16 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Intel
+=====
+
+.. toctree::
+   :maxdepth: 2
+
+   bayleybay
+   cherryhill
+   cougarcanyon2
+   crownbay
+   edison
+   galileo
+   minnowmax
+   slimbootloader
diff --git a/roms/u-boot/doc/board/intel/minnowmax.rst b/roms/u-boot/doc/board/intel/minnowmax.rst
new file mode 100644
index 000000000..028121735
--- /dev/null
+++ b/roms/u-boot/doc/board/intel/minnowmax.rst
@@ -0,0 +1,70 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Minnowboard MAX
+===============
+
+This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
+Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
+the time of writing). Put it in the corresponding board directory and rename
+it to fsp.bin.
+
+Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
+board directory as vga.bin.
+
+You still need two more binary blobs. For Minnowboard MAX, we can reuse the
+same ME firmware above, but for flash descriptor, we need get that somewhere
+else, as the one above does not seem to work, probably because it is not
+designed for the Minnowboard MAX. Now download the original firmware image
+for this board from:
+
+   * http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
+
+Unzip it::
+
+   $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
+
+Use ifdtool in the U-Boot tools directory to extract the images from that
+file, for example::
+
+   $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
+
+This will provide the descriptor file - copy this into the correct place::
+
+   $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
+
+Now you can build U-Boot and obtain u-boot.rom::
+
+   $ make minnowmax_defconfig
+   $ make all
+
+Checksums are as follows (but note that newer versions will invalidate this)::
+
+   $ md5sum -b board/intel/minnowmax/*.bin
+   ffda9a3b94df5b74323afb328d51e6b4  board/intel/minnowmax/descriptor.bin
+   69f65b9a580246291d20d08cbef9d7c5  board/intel/minnowmax/fsp.bin
+   894a97d371544ec21de9c3e8e1716c4b  board/intel/minnowmax/me.bin
+   a2588537da387da592a27219d56e9962  board/intel/minnowmax/vga.bin
+
+The ROM image is broken up into these parts:
+
+======   ==================  ============================
+Offset   Description         Controlling config
+======   ==================  ============================
+000000   descriptor.bin      Hard-coded to 0 in ifdtool
+001000   me.bin              Set by the descriptor
+500000   <spare>
+6ef000   Environment         CONFIG_ENV_OFFSET
+6f0000   MRC cache           CONFIG_ENABLE_MRC_CACHE
+700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
+7b0000   vga.bin             CONFIG_VGA_BIOS_ADDR
+7c0000   fsp.bin             CONFIG_FSP_ADDR
+7f8000   <spare>             (depends on size of fsp.bin)
+7ff800   U-Boot 16-bit boot  CONFIG_SYS_X86_START16
+======   ==================  ============================
+
+Overall ROM image size is controlled by CONFIG_ROM_SIZE.
+
+Note that the debug version of the FSP is bigger in size. If this version
+is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
+the default value 0xfffc0000.
diff --git a/roms/u-boot/doc/board/intel/slimbootloader.rst b/roms/u-boot/doc/board/intel/slimbootloader.rst
new file mode 100644
index 000000000..18f1cc056
--- /dev/null
+++ b/roms/u-boot/doc/board/intel/slimbootloader.rst
@@ -0,0 +1,177 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Aiden Park <aiden.park@intel.com>
+
+Slim Bootloader
+===============
+
+Introduction
+------------
+
+This target is to enable U-Boot_ as a payload of `Slim Bootloader`_ (a.k.a SBL)
+boot firmware which currently supports QEMU, Apollolake, Whiskeylake,
+Coffeelake-R platforms.
+
+The `Slim Bootloader`_ is designed with multi-stages (Stage1A/B, Stage2, Payload)
+architecture to cover from reset vector to OS booting and it consumes
+`Intel FSP`_ for silicon initialization.
+
+* Stage1A: Reset vector, CAR init with FSP-T
+* Stage1B: Memory init with FSP-M, CAR teardown, Continue execution in memory
+* Stage2 : Rest of Silicon init with FSP-S, Create HOB, Hand-off to Payload
+* Payload: Payload init with HOB, Load OS from media, Booting OS
+
+The Slim Bootloader stages (Stage1A/B, Stage2) focus on chipset, hardware and
+platform specific initialization, and it provides useful information to a
+payload in a HOB (Hand-Off Block) which has serial port, memory map, performance
+data info and so on. This is Slim Bootloader architectural design to make a
+payload light-weight, platform independent and more generic across different
+boot solutions or payloads, and to minimize hardware re-initialization in a
+payload.
+
+Build Instruction for U-Boot as a Slim Bootloader payload
+---------------------------------------------------------
+
+Build U-Boot and obtain u-boot-dtb.bin::
+
+   $ make distclean
+   $ make slimbootloader_defconfig
+   $ make all
+
+Prepare Slim Bootloader
+-----------------------
+
+1. Setup Build Environment for Slim Bootloader.
+
+   Refer to `Getting Started`_ page in `Slim Bootloader`_ document site.
+
+2. Get source code. Let's simply clone the repo::
+
+   $ git clone https://github.com/slimbootloader/slimbootloader.git
+
+3. Copy u-boot-dtb.bin to Slim Bootloader.
+   Slim Bootloader looks for a payload from the specific location.
+   Copy the build u-boot-dtb.bin to the expected location::
+
+   $ mkdir -p <Slim Bootloader Dir>/PayloadPkg/PayloadBins/
+   $ cp <U-Boot Dir>/u-boot-dtb.bin <Slim Bootloader Dir>/PayloadPkg/PayloadBins/u-boot-dtb.bin
+
+Build Instruction for Slim Bootloader for QEMU target
+-----------------------------------------------------
+
+Slim Bootloader supports multiple payloads, and a board of Slim Bootloader
+detects its target payload by PayloadId in board configuration.
+The PayloadId can be any 4 Bytes value.
+
+1. Update PayloadId. Let's use 'U-BT' as an example::
+
+    $ vi Platform/QemuBoardPkg/CfgData/CfgDataExt_Brd1.dlt
+    -GEN_CFG_DATA.PayloadId                     | 'AUTO'
+    +GEN_CFG_DATA.PayloadId                     | 'U-BT'
+
+2. Update payload text base. PAYLOAD_EXE_BASE must be the same as U-Boot
+   CONFIG_SYS_TEXT_BASE in board/intel/slimbootloader/Kconfig.
+   PAYLOAD_LOAD_HIGH must be 0::
+
+    $ vi Platform/QemuBoardPkg/BoardConfig.py
+    +               self.PAYLOAD_LOAD_HIGH    = 0
+    +               self.PAYLOAD_EXE_BASE     = 0x00100000
+
+3. Build QEMU target. Make sure u-boot-dtb.bin and U-BT PayloadId
+   in build command. The output is Outputs/qemu/SlimBootloader.bin::
+
+   $ python BuildLoader.py build qemu -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma"
+
+4. Launch Slim Bootloader on QEMU.
+   You should reach at U-Boot serial console::
+
+   $ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin
+
+Test Linux booting on QEMU target
+---------------------------------
+
+Let's use LeafHill (APL) Yocto image for testing.
+Download it from http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/machines/leafhill/.
+
+1. Prepare Yocto hard disk image::
+
+   $ wget http://downloads.yoctoproject.org/releases/yocto/yocto-2.0/machines/leafhill/leafhill-4.0-jethro-2.0.tar.bz2
+   $ tar -xvf leafhill-4.0-jethro-2.0.tar.bz2
+   $ ls -l leafhill-4.0-jethro-2.0/binary/core-image-sato-intel-corei7-64.hddimg
+
+2. Launch Slim Bootloader on QEMU with disk image::
+
+   $ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin -drive id=mydrive,if=none,file=/path/to/core-image-sato-intel-corei7-64.hddimg,format=raw -device ide-hd,drive=mydrive
+
+3. Update boot environment values on shell::
+
+   => setenv bootfile vmlinuz
+   => setenv bootdev scsi
+   => boot
+
+Build Instruction for Slim Bootloader for LeafHill (APL) target
+---------------------------------------------------------------
+
+Prepare U-Boot and Slim Bootloader as described at the beginning of this page.
+Also, the PayloadId needs to be set for APL board.
+
+1. Update PayloadId. Let's use 'U-BT' as an example::
+
+    $ vi Platform/ApollolakeBoardPkg/CfgData/CfgData_Int_LeafHill.dlt
+    -GEN_CFG_DATA.PayloadId                     | 'AUTO
+    +GEN_CFG_DATA.PayloadId                     | 'U-BT'
+
+2. Update payload text base.
+
+* PAYLOAD_EXE_BASE must be the same as U-Boot CONFIG_SYS_TEXT_BASE
+  in board/intel/slimbootloader/Kconfig.
+* PAYLOAD_LOAD_HIGH must be 0::
+
+    $ vi Platform/ApollolakeBoardPkg/BoardConfig.py
+    +               self.PAYLOAD_LOAD_HIGH    = 0
+    +               self.PAYLOAD_EXE_BASE     = 0x00100000
+
+3. Build APL target. Make sure u-boot-dtb.bin and U-BT PayloadId
+   in build command. The output is Outputs/apl/Stitch_Components.zip::
+
+   $ python BuildLoader.py build apl -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma"
+
+4. Stitch IFWI.
+
+   Refer to Apollolake_ page in Slim Bootloader document site::
+
+   $ python Platform/ApollolakeBoardPkg/Script/StitchLoader.py -i <Existing IFWI> -s Outputs/apl/Stitch_Components.zip -o <Output IFWI>
+
+5. Flash IFWI.
+
+   Use DediProg to flash IFWI. You should reach at U-Boot serial console.
+
+
+Build Instruction to use ELF U-Boot
+-----------------------------------
+
+1. Enable CONFIG_OF_EMBED::
+
+    $ vi configs/slimbootloader_defconfig
+    +CONFIG_OF_EMBED=y
+
+2. Build U-Boot::
+
+   $ make distclean
+   $ make slimbootloader_defconfig
+   $ make all
+   $ strip u-boot (removing symbol for reduced size)
+
+3. Do same steps as above
+
+* Copy u-boot (ELF) to PayloadBins directory
+* Update PayloadId 'U-BT' as above.
+* No need to set PAYLOAD_LOAD_HIGH and PAYLOAD_EXE_BASE.
+* Build Slim Bootloader. Use u-boot instead of u-boot-dtb.bin::
+
+   $ python BuildLoader.py build <qemu or apl> -p "OsLoader.efi:LLDR:Lz4;u-boot:U-BT:Lzma"
+
+.. _U-Boot: https://source.denx.de/
+.. _`Slim Bootloader`: https://github.com/slimbootloader/
+.. _`Intel FSP`: https://github.com/IntelFsp/
+.. _`Getting Started`: https://slimbootloader.github.io/getting-started/
+.. _Apollolake: https://slimbootloader.github.io/supported-hardware/apollo-lake-crb.html#stitching
diff --git a/roms/u-boot/doc/board/kontron/index.rst b/roms/u-boot/doc/board/kontron/index.rst
new file mode 100644
index 000000000..543b22e2f
--- /dev/null
+++ b/roms/u-boot/doc/board/kontron/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Kontron
+=======
+
+.. toctree::
+   :maxdepth: 2
+
+   sl28
diff --git a/roms/u-boot/doc/board/kontron/sl28.rst b/roms/u-boot/doc/board/kontron/sl28.rst
new file mode 100644
index 000000000..e458fbc60
--- /dev/null
+++ b/roms/u-boot/doc/board/kontron/sl28.rst
@@ -0,0 +1,160 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Summary
+=======
+
+The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72
+processor module with an on-chip 6-port TSN switch and a 3D GPU.
+
+
+Quickstart
+==========
+
+Compile U-Boot
+--------------
+
+Configure and compile the binary::
+
+ $ make kontron_sl28_defconfig
+ $ CROSS_COMPILE=aarch64-linux-gnu make
+
+Copy u-boot.rom to a TFTP server.
+
+Install the bootloader on the board
+-----------------------------------
+
+Please note, this bootloader doesn't support the builtin watchdog (yet),
+therefore you have to disable it, see below. Otherwise you'll end up in
+the failsafe bootloader on every reset::
+
+ > tftp path/to/u-boot.rom
+ > sf probe 0
+ > sf update $fileaddr 0x210000 $filesize
+
+The board is fully failsafe, you can't break anything. But because you've
+disabled the builtin watchdog you might have to manually enter failsafe
+mode by asserting the ``FORCE_RECOV#`` line during board reset.
+
+Disable the builtin watchdog
+----------------------------
+
+- boot into the failsafe bootloader, either by asserting the
+  ``FORCE_RECOV#`` line or if you still have the original bootloader
+  installed you can use the command::
+
+  > wdt dev cpld_watchdog@4a; wdt expire 1
+
+- in the failsafe bootloader use the "sl28 nvm" command to disable
+  the automatic start of the builtin watchdog::
+
+  > sl28 nvm 0008
+
+- power-cycle the board
+
+
+Useful I2C tricks
+=================
+
+The board has a board management controller which is not supported in
+u-boot (yet). But you can use the i2c command to access it.
+
+- reset into failsafe bootloader::
+
+  > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42
+
+- read board management controller version::
+
+  > i2c md 4a 3.1 1
+
+
+Non-volatile Board Configuration Bits
+=====================================
+
+The board has 16 configuration bits which are stored in the CPLD and are
+non-volatile. These can be changed by the `sl28 nvm` command.
+
+===  ===============================================================
+Bit  Description
+===  ===============================================================
+  0  Power-on inhibit
+  1  Enable eMMC boot
+  2  Enable watchdog by default
+  3  Disable failsafe watchdog by default
+  4  Clock generator selection bit 0
+  5  Clock generator selection bit 1
+  6  Disable CPU SerDes clock #2 and PCIe-A clock output
+  7  Disable PCIe-B and PCIe-C clock output
+  8  Keep onboard PHYs in reset
+  9  Keep USB hub in reset
+ 10  Keep eDP-to-LVDS converter in reset
+ 11  Enable I2C stuck recovery on I2C PM and I2C GP busses
+ 12  Enable automatic onboard PHY H/W reset
+ 13  reserved
+ 14  Used by the RCW to determine boot source
+ 15  Used by the RCW to determine boot source
+===  ===============================================================
+
+Please note, that if the board is in failsafe mode, the bits will have the
+factory defaults, ie. all bits are off.
+
+Power-On Inhibit
+----------------
+
+If this is set, the board doesn't automatically turn on when power is
+applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or
+use any other wake-up source such as RTC alarm or Wake-on-LAN.
+
+eMMC Boot
+---------
+
+If this is set, the RCW will be fetched from the on-board eMMC at offset
+1MiB. For further details, have a look at the `Reset Configuration Word
+Documentation`_.
+
+Watchdog
+--------
+
+By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and
+3, the user can change its mode or disable it altogether.
+
+=====  =====  ===============================
+Bit 2  Bit 3  Description
+=====  =====  ===============================
+    0      0  Watchdog enabled, failsafe mode
+    0      1  Watchdog disabled
+    1      0  Watchdog enabled, failsafe mode
+    1      1  Watchdog enabled, normal mode
+=====  =====  ===============================
+
+Clock Generator Select
+----------------------
+
+The board is prepared to supply different SerDes clock speeds. But for now,
+only setting 0 is supported, otherwise the CPU will hang because the PLL
+will not lock.
+
+Clock Output Disable And Keep Devices In Reset
+----------------------------------------------
+
+To safe power, the user might disable different devices and clock output of
+the board. It is not supported to disable the "CPU SerDes clock #2" for
+now, otherwise the CPU will hang because the PLL will not lock.
+
+Automatic reset of the onboard PHYs
+-----------------------------------
+
+By default, there is no hardware reset of the onboard PHY. This is because
+for Wake-on-LAN, some registers have to retain their values. If you don't
+use the WOL feature and a soft reset of the PHY is not enough you can
+enable the hardware reset. The onboard PHY hardware reset follows the
+power-on reset.
+
+
+Further documentation
+=====================
+
+- `Vendor Documentation`_
+- `Reset Configuration Word Documentation`_
+
+.. _Reset Configuration Word Documentation: https://raw.githubusercontent.com/kontron/rcw-smarc-sal28/master/README.md
+.. _Vendor Documentation: https://raw.githubusercontent.com/kontron/u-boot-smarc-sal28/master/board/kontron/sl28/README.md
diff --git a/roms/u-boot/doc/board/microchip/index.rst b/roms/u-boot/doc/board/microchip/index.rst
new file mode 100644
index 000000000..affc5a9e0
--- /dev/null
+++ b/roms/u-boot/doc/board/microchip/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip
+=========
+
+.. toctree::
+   :maxdepth: 2
+
+   mpfs_icicle
diff --git a/roms/u-boot/doc/board/microchip/mpfs_icicle.rst b/roms/u-boot/doc/board/microchip/mpfs_icicle.rst
new file mode 100644
index 000000000..c71c2f3ca
--- /dev/null
+++ b/roms/u-boot/doc/board/microchip/mpfs_icicle.rst
@@ -0,0 +1,825 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip PolarFire SoC Icicle Kit
+==================================
+
+RISC-V PolarFire SoC
+--------------------
+
+The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
+
+The Icicle Kit development platform is based on PolarFire SoC and capable
+of running Linux.
+
+Mainline support
+----------------
+
+The support for following drivers are already enabled:
+
+1. NS16550 UART Driver.
+2. Microchip Clock Driver.
+3. Cadence MACB ethernet driver for networking support.
+4. Cadence MMC Driver for eMMC/SD support.
+
+Booting from eMMC using HSS
+---------------------------
+
+Building U-Boot
+~~~~~~~~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+   export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+3. make microchip_mpfs_icicle_defconfig
+4. make
+
+Flashing
+~~~~~~~~
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to
+boot the u-boot.bin in S-mode.
+
+Currently, the u-boot.bin is used as a payload of the HSS firmware (Microchip
+boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin embedded)
+as HSS payload (Custom boot-flow)
+
+Microchip boot-flow
+~~~~~~~~~~~~~~~~~~~
+
+HSS with OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux (S-Mode)
+
+Build the HSS (Hart Software Services) - Microchip boot-flow
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+(Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services)
+
+1. Configure
+
+.. code-block:: none
+
+   make BOARD=icicle-kit-es config
+
+Alternatively, copy the default config for Microchip boot-flow.
+
+.. code-block:: none
+
+   cp boards/icicle-kit-es/def_config .config
+
+2. make BOARD=icicle-kit-es
+3. In the Default subdirectory, the standard build will create hss.elf and
+   various binary formats (hss.hex and hss.bin).
+
+The FPGA design will use the hss.hex or hss.bin.
+
+FPGA design with HSS programming file
+'''''''''''''''''''''''''''''''''''''
+
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+Creating the HSS payload - Microchip boot-flow
+''''''''''''''''''''''''''''''''''''''''''''''
+
+1. You will be creating a payload from `u-boot-dtb.bin`.
+   Copy this file to the HSS/tools/hss-payload-generator/test directory.
+2. Go to hss-payload-generator source directory.
+
+.. code-block:: none
+
+   cd hart-software-services/tools/hss-payload-generator
+
+3. Edit test/uboot.yaml file for hart entry points and correct name of the binary file.
+
+	hart-entry-points: {u54_1: '0x80200000', u54_2: '0x80200000', u54_3: '0x80200000', u54_4: '0x80200000'}
+
+	payloads:
+	test/u-boot-dtb.bin: {exec-addr: '0x80200000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode: prv_s}
+
+4. Generate payload
+
+.. code-block:: none
+
+   ./hss-payload-generator -c test/uboot.yaml payload.bin
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+Please refer to HSS documenation to build the HSS firmware for payload.
+(Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md)
+
+Custom boot-flow
+~~~~~~~~~~~~~~~~
+
+HSS without OpenSBI (M-Mode) -> OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux (S-Mode)
+
+Build OpenSBI
+'''''''''''''
+
+1. Get the OpenSBI source
+
+.. code-block:: none
+
+   git clone https://github.com/riscv/opensbi.git
+   cd opensbi
+
+2. Build
+
+.. code-block:: none
+
+   make PLATFORM=generic FW_PAYLOAD_PATH=<u-boot-directory>/u-boot.bin
+   FW_FDT_PATH=<u-boot-directory>/arch/riscv/dts/microchip-mpfs-icicle-kit-.dtb
+
+3. Output "fw_payload.bin" file available at
+   "<opensbi-directory>/build/platform/generic/firmware/fw_payload.bin"
+
+Build the HSS (Hart Software Services)- Custom boot-flow
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+(Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services)
+
+1. Configure
+
+.. code-block:: none
+
+   make BOARD=icicle-kit-es config
+
+Alternatively, copy the default custom config for Custom boot-flow.
+
+.. code-block:: none
+
+   cp boards/icicle-kit-es/def_config_custom .config
+
+2. make BOARD=icicle-kit-es
+3. In the Default subdirectory, the standard build will create hss.elf and
+   various binary formats (hss.hex and hss.bin).
+
+The FPGA design will use the hss.hex or hss.bin.
+
+Creating the HSS payload - Custom boot-flow
+'''''''''''''''''''''''''''''''''''''''''''
+
+1. You will be creating a payload from `fw_payload.bin`.
+   Copy this file to the HSS/tools/hss-payload-generator/test directory.
+2. Go to hss-payload-generator source directory.
+
+.. code-block:: none
+
+   cd hart-software-services/tools/hss-payload-generator
+
+3. Edit test/uboot.yaml file for hart entry points and correct name of the binary file.
+
+	hart-entry-points: {u54_1: '0x80000000', u54_2: '0x80000000', u54_3: '0x80000000', u54_4: '0x80000000'}
+
+	payloads:
+	test/fw_payload.bin: {exec-addr: '0x80000000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode: prv_m}
+
+4. Generate payload
+
+.. code-block:: none
+
+   ./hss-payload-generator -c test/uboot.yaml payload.bin
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+Please refer to HSS documenation to build the HSS firmware for payload.
+(Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md
+and also refer the HSS payload generator at https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/software-development/hss-payloads.md)
+
+eMMC
+~~~~
+
+Program eMMC with payload binary is explained in the PolarFire SoC documentation.
+(Note: PolarFire SoC Documentation git repo is at https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC)
+
+Once the payload image is copied to the eMMC, press CTRL+C in the HSS command
+line interface, then type 'boot' and enter to boot the newly copied image.
+
+.. code-block:: none
+
+    sudo dd if=<payload_binary> of=/dev/sdX bs=512
+
+GUID type
+~~~~~~~~~
+
+The HSS always picks up HSS payload from a GPT partition with
+GIUD type "21686148-6449-6E6F-744E-656564454649" or sector '0' of the eMMC if no
+GPT partition.
+
+Booting
+~~~~~~~
+
+You should see the U-Boot prompt on UART0.
+
+Sample boot log from MPFS Icicle Kit
+''''''''''''''''''''''''''''''''''''
+
+.. code-block:: none
+
+   U-Boot 2021.01-00314-g7303332537-dirty (Jan 14 2021 - 10:09:43 +0530)
+
+   CPU:   rv64imafdc
+   Model: Microchip MPFS Icicle Kit
+   DRAM:  1 GiB
+   MMC:   sdhc@20008000: 0
+   In:    serial@20100000
+   Out:   serial@20100000
+   Err:   serial@20100000
+   Net:   eth0: ethernet@20112000
+   Hit any key to stop autoboot:  0
+
+Now you can configure your networking, tftp server and use tftp boot method to
+load uImage (with initramfs).
+
+.. code-block:: none
+
+   RISC-V # setenv kernel_addr_r 0x80200000
+   RISC-V # setenv fdt_addr_r 0x82200000
+
+   RISC-V # setenv ipaddr 192.168.1.5
+   RISC-V # setenv netmask 255.255.255.0
+   RISC-V # setenv serverip 192.168.1.3
+   RISC-V # setenv gateway 192.168.1.1
+
+   RISC-V # tftpboot ${kernel_addr_r} uImage
+   ethernet@20112000: PHY present at 9
+   ethernet@20112000: Starting autonegotiation...
+   ethernet@20112000: Autonegotiation complete
+   ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800)
+   Using ethernet@20112000 device
+   TFTP from server 192.168.1.3; our IP address is 192.168.1.5
+   Filename 'uImage'.
+   Load address: 0x80200000
+   Loading: #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    #################################################################
+	    ############
+	    6.4 MiB/s
+   done
+   Bytes transferred = 14482480 (dcfc30 hex)
+
+   RISC-V # tftpboot ${fdt_addr_r} microchip-mpfs-icicle-kit.dtb
+   ethernet@20112000: PHY present at 9
+   ethernet@20112000: Starting autonegotiation...
+   ethernet@20112000: Autonegotiation complete
+   ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800)
+   Using ethernet@20112000 device
+   TFTP from server 192.168.1.3; our IP address is 192.168.1.5
+   Filename 'microchip-mpfs-icicle-kit.dtb'.
+   Load address: 0x82200000
+   Loading: #
+			2.5 MiB/s
+   done
+   Bytes transferred = 10282 (282a hex)
+
+   RISC-V # bootm ${kernel_addr_r} - ${fdt_addr_r}
+   ## Booting kernel from Legacy Image at 80200000 ...
+		Image Name:   Linux
+		Image Type:   RISC-V Linux Kernel Image (uncompressed)
+		Data Size:    14482416 Bytes = 13.8 MiB
+		Load Address: 80200000
+		Entry Point:  80200000
+		Verifying Checksum ... OK
+   ## Flattened Device Tree blob at 82200000
+		Booting using the fdt blob at 0x82200000
+		Loading Kernel Image
+		Using Device Tree in place at 000000008fffa000, end 000000008ffff829 ... OK
+
+   Starting kernel ...
+
+   [    0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
+   [    0.000000] Linux version 5.6.17 (padmarao@padmarao-VirtualBox) (gcc version 7.2.0 (GCC)) #2 SMP Tue Jun 16 21:27:50 IST 2020
+   [    0.000000] initrd not found or empty - disabling initrd
+   [    0.000000] Zone ranges:
+   [    0.000000]   DMA32    [mem 0x0000000080200000-0x00000000bfffffff]
+   [    0.000000]   Normal   empty
+   [    0.000000] Movable zone start for each node
+   [    0.000000] Early memory node ranges
+   [    0.000000]   node   0: [mem 0x0000000080200000-0x00000000bfffffff]
+   [    0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff]
+   [    0.000000] software IO TLB: mapped [mem 0xbb1f5000-0xbf1f5000] (64MB)
+   [    0.000000] elf_hwcap is 0x112d
+   [    0.000000] percpu: Embedded 14 pages/cpu s24856 r0 d32488 u57344
+   [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 258055
+   [    0.000000] Kernel command line: console=ttyS0,115200n8
+   [    0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
+   [    0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
+   [    0.000000] Sorting __ex_table...
+   [    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+   [    0.000000] Memory: 950308K/1046528K available (3289K kernel code, 212K rwdata, 900K rodata, 9476K init, 250K bss, 96220K reserved, 0K cma-reserved)
+   [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+   [    0.000000] rcu: Hierarchical RCU implementation.
+   [    0.000000] rcu: 	RCU event tracing is enabled.
+   [    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+   [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
+   [    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+   [    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+   [    0.000000] plic: mapped 186 interrupts with 4 handlers for 9 contexts.
+   [    0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
+   [    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
+   [    0.000015] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
+   [    0.000311] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=10000)
+   [    0.000349] pid_max: default: 32768 minimum: 301
+   [    0.000846] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
+   [    0.000964] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
+   [    0.005630] rcu: Hierarchical SRCU implementation.
+   [    0.006901] smp: Bringing up secondary CPUs ...
+   [    0.012545] smp: Brought up 1 node, 4 CPUs
+   [    0.014431] devtmpfs: initialized
+   [    0.020526] random: get_random_bytes called from setup_net+0x36/0x192 with crng_init=0
+   [    0.020928] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
+   [    0.020999] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
+   [    0.022768] NET: Registered protocol family 16
+   [    0.035478] microchip-pfsoc-clkcfg 20002000.clkcfg: Registered PFSOC core clocks
+   [    0.048429] SCSI subsystem initialized
+   [    0.049694] pps_core: LinuxPPS API ver. 1 registered
+   [    0.049719] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+   [    0.049780] PTP clock support registered
+   [    0.051781] clocksource: Switched to clocksource riscv_clocksource
+   [    0.055326] NET: Registered protocol family 2
+   [    0.056922] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
+   [    0.057053] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
+   [    0.057648] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear)
+   [    0.058579] TCP: Hash tables configured (established 8192 bind 8192)
+   [    0.059648] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
+   [    0.059837] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
+   [    0.060707] NET: Registered protocol family 1
+   [    0.266229] workingset: timestamp_bits=62 max_order=18 bucket_order=0
+   [    0.287107] io scheduler mq-deadline registered
+   [    0.287140] io scheduler kyber registered
+   [    0.429601] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+   [    0.433979] printk: console [ttyS0] disabled
+   [    0.434154] 20000000.serial: ttyS0 at MMIO 0x20000000 (irq = 18, base_baud = 9375000) is a 16550A
+   [    0.928039] printk: console [ttyS0] enabled
+   [    0.939804] libphy: Fixed MDIO Bus: probed
+   [    0.948702] libphy: MACB_mii_bus: probed
+   [    0.993698] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 21 (56:34:12:00:fc:00)
+   [    1.006751] mousedev: PS/2 mouse device common for all mice
+   [    1.013803] i2c /dev entries driver
+   [    1.019451] sdhci: Secure Digital Host Controller Interface driver
+   [    1.027242] sdhci: Copyright(c) Pierre Ossman
+   [    1.032731] sdhci-pltfm: SDHCI platform and OF driver helper
+   [    1.091826] mmc0: SDHCI controller on 20008000.sdhc [20008000.sdhc] using ADMA 64-bit
+   [    1.102738] NET: Registered protocol family 17
+   [    1.170326] Freeing unused kernel memory: 9476K
+   [    1.176067] This architecture does not have kernel memory protection.
+   [    1.184157] Run /init as init process
+   Starting logging: OK
+   Starting mdev...
+   /etc/init.d/S10mdev: line 21: can't create /proc/sys/kernel/hotplug: nonexiste[    1.331981] mmc0: mmc_select_hs200 failed, error -74
+   nt directory
+   [    1.355011] mmc0: new MMC card at address 0001
+   [    1.363981] mmcblk0: mmc0:0001 DG4008 7.28 GiB
+   [    1.372248] mmcblk0boot0: mmc0:0001 DG4008 partition 1 4.00 MiB
+   [    1.382292] mmcblk0boot1: mmc0:0001 DG4008 partition 2 4.00 MiB
+   [    1.390265] mmcblk0rpmb: mmc0:0001 DG4008 partition 3 4.00 MiB, chardev (251:0)
+   [    1.425234] GPT:Primary header thinks Alt. header is not at the end of the disk.
+   [    1.434656] GPT:2255809 != 15273599
+   [    1.439038] GPT:Alternate GPT header not at the end of the disk.
+   [    1.446671] GPT:2255809 != 15273599
+   [    1.451048] GPT: Use GNU Parted to correct GPT errors.
+   [    1.457755]  mmcblk0: p1 p2 p3
+   sort: /sys/devices/platform/Fixed: No such file or directory
+   modprobe: can't change directory to '/lib/modules': No such file or directory
+   Initializing random number generator... [    2.830198] random: dd: uninitialized urandom read (512 bytes read)
+   done.
+   Starting network...
+   [    3.061867] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL)
+   [    3.074674] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode
+   [    3.084263] pps pps0: new PPS source ptp0
+   [    3.089710] macb 20112000.ethernet: gem-ptp-timer ptp clock registered.
+   udhcpc (v1.24.2) started
+   Sending discover...
+   Sending discover...
+   [    6.380169] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx
+   Sending discover...
+   Sending select for 192.168.1.2...
+   Lease of 192.168.1.2 obtained, lease time 86400
+   deleting routers
+   adding dns 192.168.1.1
+   Starting dropbear sshd: [   11.385619] random: dropbear: uninitialized urandom read (32 bytes read)
+   OK
+
+   Welcome to Buildroot
+   buildroot login: root
+   Password:
+   #
+
+Booting U-Boot and Linux from eMMC
+----------------------------------
+
+FPGA design with HSS programming file and Linux Image
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+eMMC
+~~~~
+
+Program eMMC with payload binary and Linux image is explained in the
+PolarFire SoC documentation.
+The payload binary should be copied to partition 2 of the eMMC.
+
+(Note: PolarFire SoC Documentation git repo is at https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC)
+
+Once the Linux image and payload binary is copied to the eMMC, press CTRL+C
+in the HSS command line interface, then type 'boot' and enter to boot the newly
+copied payload and Linux image.
+
+.. code-block:: none
+
+    zcat <linux-image>.wic.gz | sudo dd of=/dev/sdX bs=4096 iflag=fullblock oflag=direct conv=fsync status=progress
+
+    sudo dd if=<payload_binary> of=/dev/sdX2 bs=512
+
+You should see the U-Boot prompt on UART0.
+
+GUID type
+~~~~~~~~~
+
+The HSS always picks up the HSS payload from a GPT partition with
+GIUD type "21686148-6449-6E6F-744E-656564454649" or sector '0' of the eMMC if no
+GPT partition.
+
+Sample boot log from MPFS Icicle Kit
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: none
+
+   U-Boot 2021.01-00314-g7303332537-dirty (Jan 14 2021 - 10:09:43 +0530)
+
+   CPU:   rv64imafdc
+   Model: Microchip MPFS Icicle Kit
+   DRAM:  1 GiB
+   MMC:   sdhc@20008000: 0
+   In:    serial@20100000
+   Out:   serial@20100000
+   Err:   serial@20100000
+   Net:   eth0: ethernet@20112000
+   Hit any key to stop autoboot:  0
+
+   RISC-V # mmc info
+   Device: sdhc@20008000
+   Manufacturer ID: 45
+   OEM: 100
+   Name: DG400
+   Bus Speed: 52000000
+   Mode: MMC High Speed (52MHz)
+   Rd Block Len: 512
+   MMC version 5.1
+   High Capacity: Yes
+   Capacity: 7.3 GiB
+   Bus Width: 4-bit
+   Erase Group Size: 512 KiB
+   HC WP Group Size: 8 MiB
+   User Capacity: 7.3 GiB WRREL
+   Boot Capacity: 4 MiB ENH
+   RPMB Capacity: 4 MiB ENH
+
+   RISC-V # mmc part
+   Partition Map for MMC device 0  --   Partition Type: EFI
+
+   Part	Start LBA	End LBA		Name
+		Attributes
+		Type GUID
+		Partition GUID
+	1	0x00002000	0x0000b031	"boot"
+		attrs:	0x0000000000000004
+		type:	ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+		guid:	99ff6a94-f2e7-44dd-a7df-f3a2da106ef9
+	2	0x0000b032	0x0000f031	"primary"
+		attrs:	0x0000000000000000
+		type:	21686148-6449-6e6f-744e-656564454649
+		guid:	12006052-e64b-4423-beb0-b956ea00f1ba
+	3	0x00010000	0x00226b9f	"root"
+		attrs:	0x0000000000000000
+		type:	0fc63daf-8483-4772-8e79-3d69d8477de4
+		guid:	dd2c5619-2272-4c3c-8dc2-e21942e17ce6
+
+   RISC-V # load mmc 0 ${ramdisk_addr_r} fitimage
+   RISC-V # bootm ${ramdisk_addr_r}
+   ## Loading kernel from FIT Image at 88300000 ...
+   Using 'conf@microchip_icicle-kit-es-a000-microchip.dtb' configuration
+   Trying 'kernel@1' kernel subimage
+     Description:  Linux kernel
+     Type:         Kernel Image
+     Compression:  gzip compressed
+     Data Start:   0x883000fc
+     Data Size:    3574555 Bytes = 3.4 MiB
+     Architecture: RISC-V
+     OS:           Linux
+     Load Address: 0x80200000
+     Entry Point:  0x80200000
+     Hash algo:    sha256
+     Hash value:   21f18d72cf2f0a7192220abb577ad25c77c26960052d779aa02bf55dbf0a6403
+   Verifying Hash Integrity ... sha256+ OK
+   ## Loading fdt from FIT Image at 88300000 ...
+   Using 'conf@microchip_icicle-kit-es-a000-microchip.dtb' configuration
+   Trying 'fdt@microchip_icicle-kit-es-a000-microchip.dtb' fdt subimage
+     Description:  Flattened Device Tree blob
+     Type:         Flat Device Tree
+     Compression:  uncompressed
+     Data Start:   0x88668d44
+     Data Size:    9760 Bytes = 9.5 KiB
+     Architecture: RISC-V
+     Load Address: 0x82200000
+     Hash algo:    sha256
+     Hash value:   5c3a9f30d41b6b8e53b47916e1f339b3a4d454006554d1f7e1f552ed62409f4b
+   Verifying Hash Integrity ... sha256+ OK
+   Loading fdt from 0x88668d48 to 0x82200000
+   Booting using the fdt blob at 0x82200000
+   Uncompressing Kernel Image
+   Loading Device Tree to 000000008fffa000, end 000000008ffff61f ... OK
+
+   Starting kernel ...
+
+   [    0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
+   [    0.000000] Linux version 5.6.16 (oe-user@oe-host) (gcc version 9.3.0 (GCC)) #1 SMP Fri Oct 9 11:49:47 UTC 2020
+   [    0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
+   [    0.000000] printk: bootconsole [sbi0] enabled
+   [    0.000000] Zone ranges:
+   [    0.000000]   DMA32    [mem 0x0000000080200000-0x00000000bfffffff]
+   [    0.000000]   Normal   empty
+   [    0.000000] Movable zone start for each node
+   [    0.000000] Early memory node ranges
+   [    0.000000]   node   0: [mem 0x0000000080200000-0x00000000bfffffff]
+   [    0.000000] Zeroed struct page in unavailable ranges: 512 pages
+   [    0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff]
+   [    0.000000] software IO TLB: mapped [mem 0xb9e00000-0xbde00000] (64MB)
+   [    0.000000] CPU with hartid=0 is not available
+   [    0.000000] CPU with hartid=0 is not available
+   [    0.000000] elf_hwcap is 0x112d
+   [    0.000000] percpu: Embedded 17 pages/cpu s29784 r8192 d31656 u69632
+   [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 258055
+   [    0.000000] Kernel command line: earlycon=sbi root=/dev/mmcblk0p3 rootwait console=ttyS0,115200n8 uio_pdrv_genirq.of_id=generic-uio
+   [    0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
+   [    0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
+   [    0.000000] Sorting __ex_table...
+   [    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+   [    0.000000] Memory: 941440K/1046528K available (4118K kernel code, 280K rwdata, 1687K rodata, 169K init, 273K bss, 105088K reserved, 0K cma-reserved)
+   [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+   [    0.000000] rcu: Hierarchical RCU implementation.
+   [    0.000000] rcu: 	RCU event tracing is enabled.
+   [    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=5 to nr_cpu_ids=4.
+   [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
+   [    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+   [    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+   [    0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts.
+   [    0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
+   [    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
+   [    0.000015] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
+   [    0.008679] Console: colour dummy device 80x25
+   [    0.013112] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=10000)
+   [    0.023368] pid_max: default: 32768 minimum: 301
+   [    0.028314] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
+   [    0.035766] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
+   [    0.047099] rcu: Hierarchical SRCU implementation.
+   [    0.052813] smp: Bringing up secondary CPUs ...
+   [    0.061581] smp: Brought up 1 node, 4 CPUs
+   [    0.067069] devtmpfs: initialized
+   [    0.073621] random: get_random_u32 called from bucket_table_alloc.isra.0+0x4e/0x150 with crng_init=0
+   [    0.074409] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
+   [    0.093399] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
+   [    0.101879] NET: Registered protocol family 16
+   [    0.110336] microchip-pfsoc-clkcfg 20002000.clkcfg: Registered PFSOC core clocks
+   [    0.132717] usbcore: registered new interface driver usbfs
+   [    0.138225] usbcore: registered new interface driver hub
+   [    0.143813] usbcore: registered new device driver usb
+   [    0.148939] pps_core: LinuxPPS API ver. 1 registered
+   [    0.153929] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+   [    0.163071] PTP clock support registered
+   [    0.168521] clocksource: Switched to clocksource riscv_clocksource
+   [    0.174927] VFS: Disk quotas dquot_6.6.0
+   [    0.179016] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
+   [    0.205536] NET: Registered protocol family 2
+   [    0.210944] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
+   [    0.219393] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
+   [    0.227497] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear)
+   [    0.235440] TCP: Hash tables configured (established 8192 bind 8192)
+   [    0.242537] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
+   [    0.249285] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
+   [    0.256690] NET: Registered protocol family 1
+   [    0.262585] workingset: timestamp_bits=62 max_order=18 bucket_order=0
+   [    0.281036] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
+   [    0.288481] io scheduler mq-deadline registered
+   [    0.292983] io scheduler kyber registered
+   [    0.298895] microsemi,mss-gpio 20122000.gpio: Microsemi MSS GPIO registered 32 GPIOs
+   [    0.453723] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+   [    0.462911] printk: console [ttyS0] disabled
+   [    0.467216] 20100000.serial: ttyS0 at MMIO 0x20100000 (irq = 12, base_baud = 9375000) is a 16550A
+   [    0.476201] printk: console [ttyS0] enabled
+   [    0.476201] printk: console [ttyS0] enabled
+   [    0.484576] printk: bootconsole [sbi0] disabled
+   [    0.484576] printk: bootconsole [sbi0] disabled
+   [    0.494920] 20102000.serial: ttyS1 at MMIO 0x20102000 (irq = 13, base_baud = 9375000) is a 16550A
+   [    0.505068] 20104000.serial: ttyS2 at MMIO 0x20104000 (irq = 14, base_baud = 9375000) is a 16550A
+   [    0.533336] loop: module loaded
+   [    0.572284] Rounding down aligned max_sectors from 4294967295 to 4294967288
+   [    0.580000] db_root: cannot open: /etc/target
+   [    0.585413] libphy: Fixed MDIO Bus: probed
+   [    0.591526] libphy: MACB_mii_bus: probed
+   [    0.598060] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (56:34:12:00:fc:00)
+   [    0.608352] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+   [    0.615001] ehci-platform: EHCI generic platform driver
+   [    0.620446] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
+   [    0.626632] ohci-platform: OHCI generic platform driver
+   [    0.632326] usbcore: registered new interface driver cdc_acm
+   [    0.637996] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
+   [    0.646459] i2c /dev entries driver
+   [    0.650852] microsemi-mss-i2c 2010b000.i2c: Microsemi I2C Probe Complete
+   [    0.658010] sdhci: Secure Digital Host Controller Interface driver
+   [    0.664326] sdhci: Copyright(c) Pierre Ossman
+   [    0.668754] sdhci-pltfm: SDHCI platform and OF driver helper
+   [    0.706845] mmc0: SDHCI controller on 20008000.sdhc [20008000.sdhc] using ADMA 64-bit
+   [    0.715052] usbcore: registered new interface driver usbhid
+   [    0.720722] usbhid: USB HID core driver
+   [    0.725174] pac193x 0-0010: Chip revision: 0x03
+   [    0.733339] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 0 active
+   [    0.740127] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 1 active
+   [    0.746881] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 2 active
+   [    0.753686] pac193x 0-0010: :pac193x_prep_iio_channels: Channel 3 active
+   [    0.760495] pac193x 0-0010: :pac193x_prep_iio_channels: Active chip channels: 25
+   [    0.778006] NET: Registered protocol family 10
+   [    0.784929] Segment Routing with IPv6
+   [    0.788875] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+   [    0.795743] NET: Registered protocol family 17
+   [    0.801191] hctosys: unable to open rtc device (rtc0)
+   [    0.807774] Waiting for root device /dev/mmcblk0p3...
+   [    0.858506] mmc0: mmc_select_hs200 failed, error -74
+   [    0.865764] mmc0: new MMC card at address 0001
+   [    0.872564] mmcblk0: mmc0:0001 DG4008 7.28 GiB
+   [    0.878777] mmcblk0boot0: mmc0:0001 DG4008 partition 1 4.00 MiB
+   [    0.886182] mmcblk0boot1: mmc0:0001 DG4008 partition 2 4.00 MiB
+   [    0.892633] mmcblk0rpmb: mmc0:0001 DG4008 partition 3 4.00 MiB, chardev (247:0)
+   [    0.919029] GPT:Primary header thinks Alt. header is not at the end of the disk.
+   [    0.926448] GPT:2255841 != 15273599
+   [    0.930019] GPT:Alternate GPT header not at the end of the disk.
+   [    0.936029] GPT:2255841 != 15273599
+   [    0.939583] GPT: Use GNU Parted to correct GPT errors.
+   [    0.944800]  mmcblk0: p1 p2 p3
+   [    0.966696] EXT4-fs (mmcblk0p3): INFO: recovery required on readonly filesystem
+   [    0.974105] EXT4-fs (mmcblk0p3): write access will be enabled during recovery
+   [    1.052362] random: fast init done
+   [    1.057961] EXT4-fs (mmcblk0p3): recovery complete
+   [    1.065734] EXT4-fs (mmcblk0p3): mounted filesystem with ordered data mode. Opts: (null)
+   [    1.074002] VFS: Mounted root (ext4 filesystem) readonly on device 179:3.
+   [    1.081654] Freeing unused kernel memory: 168K
+   [    1.086108] This architecture does not have kernel memory protection.
+   [    1.092629] Run /sbin/init as init process
+   [    1.702217] systemd[1]: System time before build time, advancing clock.
+   [    1.754192] systemd[1]: systemd 244.3+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid)
+   [    1.776361] systemd[1]: Detected architecture riscv64.
+
+   Welcome to OpenEmbedded nodistro.0!
+
+   [    1.829651] systemd[1]: Set hostname to <icicle-kit-es>.
+   [    2.648597] random: systemd: uninitialized urandom read (16 bytes read)
+   [    2.657485] systemd[1]: Created slice system-getty.slice.
+   [  OK  ] Created slice system-getty.slice.
+   [    2.698779] random: systemd: uninitialized urandom read (16 bytes read)
+   [    2.706317] systemd[1]: Created slice system-serial\x2dgetty.slice.
+   [  OK  ] Created slice system-serial\x2dgetty.slice.
+   [    2.748716] random: systemd: uninitialized urandom read (16 bytes read)
+   [    2.756098] systemd[1]: Created slice User and Session Slice.
+   [  OK  ] Created slice User and Session Slice.
+   [    2.789065] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
+   [  OK  ] Started Dispatch Password …ts to Console Directory Watch.
+   [    2.828974] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
+   [  OK  ] Started Forward Password R…uests to Wall Directory Watch.
+   [    2.869009] systemd[1]: Reached target Paths.
+   [  OK  ] Reached target Paths.
+   [    2.898808] systemd[1]: Reached target Remote File Systems.
+   [  OK  ] Reached target Remote File Systems.
+   [    2.938771] systemd[1]: Reached target Slices.
+   [  OK  ] Reached target Slices.
+   [    2.968754] systemd[1]: Reached target Swap.
+   [  OK  ] Reached target Swap.
+   [    2.999283] systemd[1]: Listening on initctl Compatibility Named Pipe.
+   [  OK  ] Listening on initctl Compatibility Named Pipe.
+   [    3.060458] systemd[1]: Condition check resulted in Journal Audit Socket being skipped.
+   [    3.069826] systemd[1]: Listening on Journal Socket (/dev/log).
+   [  OK  ] Listening on Journal Socket (/dev/log).
+   [    3.109601] systemd[1]: Listening on Journal Socket.
+   [  OK  ] Listening on Journal Socket.
+   [    3.149868] systemd[1]: Listening on Network Service Netlink Socket.
+   [  OK  ] Listening on Network Service Netlink Socket.
+   [    3.189419] systemd[1]: Listening on udev Control Socket.
+   [  OK  ] Listening on udev Control Socket.
+   [    3.229179] systemd[1]: Listening on udev Kernel Socket.
+   [  OK  ] Listening on udev Kernel Socket.
+   [    3.269520] systemd[1]: Condition check resulted in Huge Pages File System being skipped.
+   [    3.278477] systemd[1]: Condition check resulted in POSIX Message Queue File System being skipped.
+   [    3.288200] systemd[1]: Condition check resulted in Kernel Debug File System being skipped.
+   [    3.302570] systemd[1]: Mounting Temporary Directory (/tmp)...
+            Mounting Temporary Directory (/tmp)...
+   [    3.339226] systemd[1]: Condition check resulted in Create list of static device nodes for the current kernel being skipped.
+   [    3.355883] systemd[1]: Starting File System Check on Root Device...
+            Starting File System Check on Root Device...
+   [    3.407220] systemd[1]: Starting Journal Service...
+            Starting Journal Service...
+   [    3.422441] systemd[1]: Condition check resulted in Load Kernel Modules being skipped.
+   [    3.431770] systemd[1]: Condition check resulted in FUSE Control File System being skipped.
+   [    3.446415] systemd[1]: Mounting Kernel Configuration File System...
+            Mounting Kernel Configuration File System...
+   [    3.458983] systemd[1]: Starting Apply Kernel Variables...
+            Starting Apply Kernel Variables...
+   [    3.471368] systemd[1]: Starting udev Coldplug all Devices...
+            Starting udev Coldplug all Devices...
+   [    3.491071] systemd[1]: Mounted Temporary Directory (/tmp).
+   [  OK      3.498114] systemd[1]: Mounted Kernel Configuration File System.
+   0m] Mounted Temporary Directory (/tmp).
+   [  OK  ] Mounted Kernel Configuration File System.
+   [    3.550853] systemd[1]: Started Apply Kernel Variables.
+   [  OK      3.557535] systemd[1]: Started Journal Service.
+   0m] Started Apply Kernel Variables.
+   [  OK  ] Started Journal Service.
+   [  OK  ] Started udev Coldplug all Devices.
+   [  OK  ] Started File System Check on Root Device.
+            Starting Remount Root and Kernel File Systems...
+   [    8.133469] EXT4-fs (mmcblk0p3): re-mounted. Opts: (null)
+   [  OK  ] Started Remount Root and Kernel File Systems.
+            Starting Flush Journal to Persistent Storage...
+   [    8.215327] systemd-journald[77]: Received client request to flush runtime journal.
+            Starting Create Static Device Nodes in /dev...
+   [  OK  ] Started Flush Journal to Persistent Storage.
+   [  OK  ] Started Create Static Device Nodes in /dev.
+   [  OK  ] Reached target Local File Systems (Pre).
+            Mounting /var/volatile...
+            Starting udev Kernel Device Manager...
+   [  OK  ] Mounted /var/volatile.
+            Starting Load/Save Random Seed...
+   [  OK  ] Reached target Local File Systems.
+            Starting Create Volatile Files and Directories...
+   [  OK  ] Started udev Kernel Device Manager.
+   [  OK  ] Started Create Volatile Files and Directories.
+            Starting Network Time Synchronization...
+            Starting Update UTMP about System Boot/Shutdown...
+   [  OK  ] Started Update UTMP about System Boot/Shutdown.
+   [  OK  ] Started Network Time Synchronization.
+   [   11.618575] random: crng init done
+   [   11.622007] random: 7 urandom warning(s) missed due to ratelimiting
+   [  OK  ] Started Load/Save Random Seed.
+   [  OK  ] Reached target System Initialization.
+   [  OK  ] Started Daily Cleanup of Temporary Directories.
+   [  OK  ] Reached target System Time Set.
+   [  OK  ] Reached target System Time Synchronized.
+   [  OK  ] Reached target Timers.
+   [  OK  ] Listening on D-Bus System Message Bus Socket.
+   [  OK  ] Listening on dropbear.socket.
+   [  OK  ] Reached target Sockets.
+   [  OK  ] Reached target Basic System.
+   [  OK  ] Started D-Bus System Message Bus.
+            Starting IPv6 Packet Filtering Framework...
+            Starting IPv4 Packet Filtering Framework...
+            Starting Login Service...
+   [  OK  ] Started IPv6 Packet Filtering Framework.
+   [  OK  ] Started IPv4 Packet Filtering Framework.
+   [  OK  ] Reached target Network (Pre).
+            Starting Network Service...
+   [  OK  ] Started Login Service.
+   [   12.602455] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL)
+   [   12.612795] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode
+   [   12.622153] pps pps0: new PPS source ptp0
+   [  OK     12.626725] macb 20112000.ethernet: gem-ptp-timer ptp clock registered.
+   0m] Started Network Service.
+            Starting Network Name Resolution...
+   [  OK  ] Started Network Name Resolution.
+   [  OK  ] Reached target Network.
+   [  OK  ] Reached target Host and Network Name Lookups.
+   [  OK  ] Started Collectd.
+   [  OK  ] Started Collectd.
+            Starting Permit User Sessions...
+   [  OK  ] Started Permit User Sessions.
+   [  OK  ] Started Getty on tty1.
+   [  OK  ] Started Serial Getty on ttyS0.
+   [  OK  ] Reached target Login Prompts.
+   [  OK  ] Reached target Multi-User System.
+            Starting Update UTMP about System Runlevel Changes...
+   [  OK  ] Started Update UTMP about System Runlevel Changes.
+
+   OpenEmbedded nodistro.0 icicle-kit-es ttyS0
+
+   icicle-kit-es login: [   15.795564] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control tx
+   [   15.803306] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
+
+   icicle-kit-es login: root
+   root@icicle-kit-es:~#
diff --git a/roms/u-boot/doc/board/rockchip/index.rst b/roms/u-boot/doc/board/rockchip/index.rst
new file mode 100644
index 000000000..0c377e9bb
--- /dev/null
+++ b/roms/u-boot/doc/board/rockchip/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+
+Rockchip
+========
+
+.. toctree::
+   :maxdepth: 2
+
+   rockchip
diff --git a/roms/u-boot/doc/board/rockchip/rockchip.rst b/roms/u-boot/doc/board/rockchip/rockchip.rst
new file mode 100644
index 000000000..fbb998398
--- /dev/null
+++ b/roms/u-boot/doc/board/rockchip/rockchip.rst
@@ -0,0 +1,238 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+
+ROCKCHIP
+========
+
+About this
+----------
+
+This document describes the information about Rockchip supported boards
+and it's usage steps.
+
+Rockchip boards
+---------------
+
+Rockchip is SoC solutions provider for tablets & PCs, streaming media
+TV boxes, AI audio & vision, IoT hardware.
+
+A wide range of Rockchip SoCs with associated boardsare supported in
+mainline U-Boot.
+
+List of mainline supported rockchip boards:
+
+* rk3036
+     - Rockchip Evb-RK3036 (evb-rk3036)
+     - Kylin (kylin_rk3036)
+* rk3128
+     - Rockchip Evb-RK3128 (evb-rk3128)
+* rk3229
+     - Rockchip Evb-RK3229 (evb-rk3229)
+* rk3288
+     - Rockchip Evb-RK3288 (evb-rk3288)
+     - Firefly-RK3288 (firefly-rk3288)
+     - MQmaker MiQi (miqi-rk3288)
+     - Phytec RK3288 PCM-947 (phycore-rk3288)
+     - PopMetal-RK3288 (popmetal-rk3288)
+     - Radxa Rock 2 Square (rock2)
+     - Tinker-RK3288 (tinker-rk3288)
+     - Google Jerry (chromebook_jerry)
+     - Google Mickey (chromebook_mickey)
+     - Google Minnie (chromebook_minnie)
+     - Google Speedy (chromebook_speedy)
+     - Amarula Vyasa-RK3288 (vyasa-rk3288)
+* rk3308
+     - Rockchip Evb-RK3308 (evb-rk3308)
+     - Roc-cc-RK3308 (roc-cc-rk3308)
+* rk3328
+     - Rockchip Evb-RK3328 (evb-rk3328)
+     - Pine64 Rock64 (rock64-rk3328)
+     - Firefly-RK3328 (roc-cc-rk3328)
+     - Radxa Rockpi E (rock-pi-e-rk3328)
+* rk3368
+     - GeekBox (geekbox)
+     - PX5 EVB (evb-px5)
+     - Rockchip Sheep (sheep-rk3368)
+     - Theobroma Systems RK3368-uQ7 SoM - Lion (lion-rk3368)
+* rk3399
+     - 96boards RK3399 Ficus (ficus-rk3399)
+     - 96boards Rock960 (rock960-rk3399)
+     - Firefly-RK3399 (firefly_rk3399)
+     - Firefly ROC-RK3399-PC
+     - FriendlyElec NanoPC-T4 (nanopc-t4-rk3399)
+     - FriendlyElec NanoPi M4 (nanopi-m4-rk3399)
+     - FriendlyElec NanoPi M4B (nanopi-m4b-rk3399)
+     - FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399)
+     - Google Bob (chromebook_bob)
+     - Khadas Edge (khadas-edge-rk3399)
+     - Khadas Edge-Captain (khadas-edge-captain-rk3399)
+     - Khadas Edge-V (hadas-edge-v-rk3399)
+     - Orange Pi RK3399 (orangepi-rk3399)
+     - Pine64 RockPro64 (rockpro64-rk3399)
+     - Radxa ROCK Pi 4 (rock-pi-4-rk3399)
+     - Rockchip Evb-RK3399 (evb_rk3399)
+     - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
+* rv1108
+     - Rockchip Evb-rv1108 (evb-rv1108)
+     - Elgin-R1 (elgin-rv1108)
+* rv3188
+     - Radxa Rock (rock)
+
+Building
+--------
+
+TF-A
+^^^^
+
+TF-A would require to build for ARM64 Rockchip SoCs platforms.
+
+To build TF-A::
+
+        git clone https://github.com/ARM-software/arm-trusted-firmware.git
+        cd arm-trusted-firmware
+        make realclean
+        make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
+
+Specify the PLAT= with desired rockchip platform to build TF-A for.
+
+U-Boot
+^^^^^^
+
+To build rk3328 boards::
+
+        export BL31=/path/to/arm-trusted-firmware/to/bl31.elf
+        make evb-rk3328_defconfig
+        make
+
+To build rk3288 boards::
+
+        make evb-rk3288_defconfig
+        make
+
+To build rk3368 boards::
+
+        export BL31=/path/to/arm-trusted-firmware/to/bl31.elf
+        make evb-px5_defconfig
+        make
+
+To build rk3399 boards::
+
+        export BL31=/path/to/arm-trusted-firmware/to/bl31.elf
+        make evb-rk3399_defconfig
+        make
+
+Flashing
+--------
+
+1. Package the image with U-Boot TPL/SPL
+-----------------------------------------
+
+SD Card
+^^^^^^^
+
+All rockchip platforms, except rk3128 (which doesn't use SPL) are now
+supporting single boot image using binman and pad_cat.
+
+To write an image that boots from an SD card (assumed to be /dev/sda)::
+
+        sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64
+        sync
+
+eMMC
+^^^^
+
+eMMC flash would probe on mmc0 in most of the rockchip platforms.
+
+Create GPT partition layout as defined in configurations::
+
+        mmc dev 0
+        gpt write mmc 0 $partitions
+
+Connect the USB-OTG cable between host and target device.
+
+Launch fastboot at target::
+
+        fastboot 0
+
+Upon successful gadget connection,host show the USB device like::
+
+        lsusb
+        Bus 001 Device 020: ID 2207:330c Fuzhou Rockchip Electronics Company RK3399 in Mask ROM mode
+
+Program the flash::
+
+        sudo fastboot -i 0x2207 flash loader1 idbloader.img
+        sudo fastboot -i 0x2207 flash loader2 u-boot.itb
+
+Note: for rockchip 32-bit platforms the U-Boot proper image
+is u-boot-dtb.img
+
+SPI
+^^^
+
+Generating idbloader for SPI boot would require to input a multi image
+image format to mkimage tool instead of concerting (like for MMC boot).
+
+SPL-alone SPI boot image::
+
+        ./tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader.img
+
+TPL+SPL SPI boot image::
+
+        ./tools/mkimage -n rk3399 -T rkspi -d tpl/u-boot-tpl.bin:spl/u-boot-spl.bin idbloader.img
+
+Copy SPI boot images into SD card and boot from SD::
+
+        sf probe
+        load mmc 1:1 $kernel_addr_r idbloader.img
+        sf erase 0 +$filesize
+        sf write $kernel_addr_r 0 ${filesize}
+        load mmc 1:1 ${kernel_addr_r} u-boot.itb
+        sf erase 0x60000 +$filesize
+        sf write $kernel_addr_r 0x60000 ${filesize}
+
+2. Package the image with Rockchip miniloader
+---------------------------------------------
+
+Image package with Rockchip miniloader requires robin [1].
+
+Create idbloader.img
+
+.. code-block:: none
+
+  cd u-boot
+  ./tools/mkimage -n px30 -T rksd -d rkbin/bin/rk33/px30_ddr_333MHz_v1.15.bin idbloader.img
+  cat rkbin/bin/rk33/px30_miniloader_v1.22.bin >> idbloader.img
+  sudo dd if=idbloader.img of=/dev/sda seek=64
+
+Create trust.img
+
+.. code-block:: none
+
+  cd rkbin
+  ./tools/trust_merger RKTRUST/PX30TRUST.ini
+  sudo dd if=trust.img of=/dev/sda seek=24576
+
+Create uboot.img
+
+.. code-block:: none
+
+  rbink/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x200000
+  sudo dd if=uboot.img of=/dev/sda seek=16384
+
+Note:
+1. 0x200000 is load address and it's an optional in some platforms.
+2. rkbin binaries are kept on updating, so would recommend to use the latest versions.
+
+TODO
+----
+
+- Add rockchip idbloader image building
+- Add rockchip TPL image building
+- Document SPI flash boot
+- Add missing SoC's with it boards list
+
+[1] https://github.com/rockchip-linux/rkbin
+
+.. Jagan Teki <jagan@amarulasolutions.com>
+.. Wednesday 28 October 2020 06:47:26 PM IST
diff --git a/roms/u-boot/doc/board/sifive/index.rst b/roms/u-boot/doc/board/sifive/index.rst
new file mode 100644
index 000000000..a43937a3e
--- /dev/null
+++ b/roms/u-boot/doc/board/sifive/index.rst
@@ -0,0 +1,10 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+SiFive
+======
+
+.. toctree::
+   :maxdepth: 2
+
+   unleashed
+   unmatched
diff --git a/roms/u-boot/doc/board/sifive/unleashed.rst b/roms/u-boot/doc/board/sifive/unleashed.rst
new file mode 100644
index 000000000..4e4c852ff
--- /dev/null
+++ b/roms/u-boot/doc/board/sifive/unleashed.rst
@@ -0,0 +1,579 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+HiFive Unleashed
+================
+
+FU540-C000 RISC-V SoC
+---------------------
+The FU540-C000 is the world’s first 4+1 64-bit RISC-V SoC from SiFive.
+
+The HiFive Unleashed development platform is based on FU540-C000 and capable
+of running Linux.
+
+Mainline support
+----------------
+
+The support for following drivers are already enabled:
+
+1. SiFive UART Driver.
+2. SiFive PRCI Driver for clock.
+3. Cadence MACB ethernet driver for networking support.
+4. SiFive SPI Driver.
+5. MMC SPI Driver for MMC/SD support.
+
+Booting from MMC using FSBL
+---------------------------
+
+Building
+~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+   export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+3. make sifive_fu540_defconfig
+4. make
+
+Flashing
+~~~~~~~~
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to
+boot the u-boot.bin in S-mode and provide M-mode runtime services.
+
+Currently, the u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD
+firmware. We need to compile OpenSBI with below command:
+
+.. code-block:: none
+
+	make PLATFORM=generic FW_PAYLOAD_PATH=<path to u-boot-dtb.bin>
+
+More detailed description of steps required to build FW_PAYLOAD firmware
+is beyond the scope of this document. Please refer OpenSBI documenation.
+(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
+
+Once the prior stage firmware/bootloader binary is generated, it should be
+copied to the first partition of the sdcard.
+
+.. code-block:: none
+
+    sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
+
+Booting
+~~~~~~~
+
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from HiFive Unleashed board
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: none
+
+   U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
+
+   CPU:   rv64imafdc
+   Model: SiFive HiFive Unleashed A00
+   DRAM:  8 GiB
+   MMC:   spi@10050000:mmc@0: 0
+   In:    serial@10010000
+   Out:   serial@10010000
+   Err:   serial@10010000
+   Net:   eth0: ethernet@10090000
+   Hit any key to stop autoboot:  0
+   => version
+   U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
+
+   riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9) 8.2.0
+   GNU ld (GNU Binutils) 2.31.1
+   => mmc info
+   Device: spi@10050000:mmc@0
+   Manufacturer ID: 3
+   OEM: 5344
+   Name: SU08G
+   Bus Speed: 20000000
+   Mode: SD Legacy
+   Rd Block Len: 512
+   SD version 2.0
+   High Capacity: Yes
+   Capacity: 7.4 GiB
+   Bus Width: 1-bit
+   Erase Group Size: 512 Bytes
+   => mmc part
+
+   Partition Map for MMC device 0  --   Partition Type: EFI
+
+   Part    Start LBA       End LBA         Name
+           Attributes
+           Type GUID
+           Partition GUID
+     1     0x00000800      0x000107ff      "bootloader"
+           attrs:  0x0000000000000000
+           type:   2e54b353-1271-4842-806f-e436d6af6985
+           guid:   393bbd36-7111-491c-9869-ce24008f6403
+     2     0x00040800      0x00ecdfde      ""
+           attrs:  0x0000000000000000
+           type:   0fc63daf-8483-4772-8e79-3d69d8477de4
+           guid:   7fc9a949-5480-48c7-b623-04923080757f
+
+Now you can configure your networking, tftp server and use tftp boot method to
+load uImage.
+
+.. code-block:: none
+
+   => setenv ipaddr 10.206.7.133
+   => setenv netmask 255.255.252.0
+   => setenv serverip 10.206.4.143
+   => setenv gateway 10.206.4.1
+
+If you want to use a flat kernel image such as Image file
+
+.. code-block:: none
+
+   => tftpboot ${kernel_addr_r} /sifive/fu540/Image
+   ethernet@10090000: PHY present at 0
+   ethernet@10090000: Starting autonegotiation...
+   ethernet@10090000: Autonegotiation complete
+   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
+   Using ethernet@10090000 device
+   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+   Filename '/sifive/fu540/Image'.
+   Load address: 0x84000000
+   Loading: #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            ##########################################
+            1.2 MiB/s
+   done
+   Bytes transferred = 8867100 (874d1c hex)
+
+Or if you want to use a compressed kernel image file such as Image.gz
+
+.. code-block:: none
+
+   => tftpboot ${kernel_addr_r} /sifive/fu540/Image.gz
+   ethernet@10090000: PHY present at 0
+   ethernet@10090000: Starting autonegotiation...
+   ethernet@10090000: Autonegotiation complete
+   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
+   Using ethernet@10090000 device
+   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+   Filename '/sifive/fu540/Image.gz'.
+   Load address: 0x84000000
+   Loading: #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            ##########################################
+            1.2 MiB/s
+   done
+   Bytes transferred = 4809458 (4962f2 hex)
+   =>setenv kernel_comp_addr_r 0x90000000
+   =>setenv kernel_comp_size 0x500000
+
+By this time, correct kernel image is loaded and required environment variables
+are set. You can proceed to load the ramdisk and device tree from the tftp server
+as well.
+
+.. code-block:: none
+
+   => tftpboot ${ramdisk_addr_r} /sifive/fu540/uRamdisk
+   ethernet@10090000: PHY present at 0
+   ethernet@10090000: Starting autonegotiation...
+   ethernet@10090000: Autonegotiation complete
+   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
+   Using ethernet@10090000 device
+   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+   Filename '/sifive/fu540/uRamdisk'.
+   Load address: 0x88300000
+   Loading: #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            ##############
+            418.9 KiB/s
+   done
+   Bytes transferred = 2398272 (249840 hex)
+   => tftpboot ${fdt_addr_r} /sifive/fu540/hifive-unleashed-a00.dtb
+   ethernet@10090000: PHY present at 0
+   ethernet@10090000: Starting autonegotiation...
+   ethernet@10090000: Autonegotiation complete
+   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x7c00)
+   Using ethernet@10090000 device
+   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+   Filename '/sifive/fu540/hifive-unleashed-a00.dtb'.
+   Load address: 0x88000000
+   Loading: ##
+            1000 Bytes/s
+   done
+   Bytes transferred = 5614 (15ee hex)
+   => setenv bootargs "root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi"
+   => booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
+   ## Loading init Ramdisk from Legacy Image at 88300000 ...
+      Image Name:   Linux RootFS
+      Image Type:   RISC-V Linux RAMDisk Image (uncompressed)
+      Data Size:    2398208 Bytes = 2.3 MiB
+      Load Address: 00000000
+      Entry Point:  00000000
+      Verifying Checksum ... OK
+   ## Flattened Device Tree blob at 88000000
+      Booting using the fdt blob at 0x88000000
+      Using Device Tree in place at 0000000088000000, end 00000000880045ed
+
+   Starting kernel ...
+
+   [    0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
+   [    0.000000] Linux version 5.3.0-rc1-00003-g460ac558152f (anup@anup-lab-machine) (gcc version 8.2.0 (Buildroot 2018.11-rc2-00003-ga0787e9)) #6 SMP Mon Jul 22 10:01:01 IST 2019
+   [    0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
+   [    0.000000] printk: bootconsole [sbi0] enabled
+   [    0.000000] Initial ramdisk at: 0x(____ptrval____) (2398208 bytes)
+   [    0.000000] Zone ranges:
+   [    0.000000]   DMA32    [mem 0x0000000080200000-0x00000000ffffffff]
+   [    0.000000]   Normal   [mem 0x0000000100000000-0x000000027fffffff]
+   [    0.000000] Movable zone start for each node
+   [    0.000000] Early memory node ranges
+   [    0.000000]   node   0: [mem 0x0000000080200000-0x000000027fffffff]
+   [    0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
+   [    0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
+   [    0.000000] CPU with hartid=0 is not available
+   [    0.000000] CPU with hartid=0 is not available
+   [    0.000000] elf_hwcap is 0x112d
+   [    0.000000] percpu: Embedded 18 pages/cpu s34584 r8192 d30952 u73728
+   [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2067975
+   [    0.000000] Kernel command line: root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi
+   [    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
+   [    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
+   [    0.000000] Sorting __ex_table...
+   [    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+   [    0.000000] Memory: 8182308K/8386560K available (5916K kernel code, 368K rwdata, 1840K rodata, 213K init, 304K bss, 204252K reserved, 0K cma-reserved)
+   [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+   [    0.000000] rcu: Hierarchical RCU implementation.
+   [    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+   [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+   [    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+   [    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+   [    0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts.
+   [    0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
+   [    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
+   [    0.000006] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
+   [    0.008559] Console: colour dummy device 80x25
+   [    0.012989] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000)
+   [    0.023104] pid_max: default: 32768 minimum: 301
+   [    0.028273] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+   [    0.035765] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+   [    0.045307] rcu: Hierarchical SRCU implementation.
+   [    0.049875] smp: Bringing up secondary CPUs ...
+   [    0.055729] smp: Brought up 1 node, 4 CPUs
+   [    0.060599] devtmpfs: initialized
+   [    0.064819] random: get_random_u32 called from bucket_table_alloc.isra.10+0x4e/0x160 with crng_init=0
+   [    0.073720] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+   [    0.083176] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
+   [    0.090721] NET: Registered protocol family 16
+   [    0.106319] vgaarb: loaded
+   [    0.108670] SCSI subsystem initialized
+   [    0.112515] usbcore: registered new interface driver usbfs
+   [    0.117758] usbcore: registered new interface driver hub
+   [    0.123167] usbcore: registered new device driver usb
+   [    0.128905] clocksource: Switched to clocksource riscv_clocksource
+   [    0.141239] NET: Registered protocol family 2
+   [    0.145506] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
+   [    0.153754] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
+   [    0.163466] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear)
+   [    0.173468] TCP: Hash tables configured (established 65536 bind 65536)
+   [    0.179739] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
+   [    0.186627] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
+   [    0.194117] NET: Registered protocol family 1
+   [    0.198417] RPC: Registered named UNIX socket transport module.
+   [    0.203887] RPC: Registered udp transport module.
+   [    0.208664] RPC: Registered tcp transport module.
+   [    0.213429] RPC: Registered tcp NFSv4.1 backchannel transport module.
+   [    0.219944] PCI: CLS 0 bytes, default 64
+   [    0.224170] Unpacking initramfs...
+   [    0.262347] Freeing initrd memory: 2336K
+   [    0.266531] workingset: timestamp_bits=62 max_order=21 bucket_order=0
+   [    0.280406] NFS: Registering the id_resolver key type
+   [    0.284798] Key type id_resolver registered
+   [    0.289048] Key type id_legacy registered
+   [    0.293114] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
+   [    0.300262] NET: Registered protocol family 38
+   [    0.304432] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
+   [    0.311862] io scheduler mq-deadline registered
+   [    0.316461] io scheduler kyber registered
+   [    0.356421] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+   [    0.363004] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 4, base_baud = 0) is a SiFive UART v0
+   [    0.371468] printk: console [ttySIF0] enabled
+   [    0.371468] printk: console [ttySIF0] enabled
+   [    0.380223] printk: bootconsole [sbi0] disabled
+   [    0.380223] printk: bootconsole [sbi0] disabled
+   [    0.389589] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 1, base_baud = 0) is a SiFive UART v0
+   [    0.398680] [drm] radeon kernel modesetting enabled.
+   [    0.412395] loop: module loaded
+   [    0.415214] sifive_spi 10040000.spi: mapped; irq=3, cs=1
+   [    0.420628] sifive_spi 10050000.spi: mapped; irq=5, cs=1
+   [    0.425897] libphy: Fixed MDIO Bus: probed
+   [    0.429964] macb 10090000.ethernet: Registered clk switch 'sifive-gemgxl-mgmt'
+   [    0.436743] macb: GEM doesn't support hardware ptp.
+   [    0.441621] libphy: MACB_mii_bus: probed
+   [    0.601316] Microsemi VSC8541 SyncE 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541 SyncE] (mii_bus:phy_addr=10090000.ethernet-ffffffff:00, irq=POLL)
+   [    0.615857] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 6 (70:b3:d5:92:f2:f3)
+   [    0.625634] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
+   [    0.631381] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
+   [    0.637382] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+   [    0.643799] ehci-pci: EHCI PCI platform driver
+   [    0.648261] ehci-platform: EHCI generic platform driver
+   [    0.653497] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
+   [    0.659599] ohci-pci: OHCI PCI platform driver
+   [    0.664055] ohci-platform: OHCI generic platform driver
+   [    0.669448] usbcore: registered new interface driver uas
+   [    0.674575] usbcore: registered new interface driver usb-storage
+   [    0.680642] mousedev: PS/2 mouse device common for all mice
+   [    0.709493] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no poweroff, cd polling
+   [    0.716615] usbcore: registered new interface driver usbhid
+   [    0.722023] usbhid: USB HID core driver
+   [    0.726738] NET: Registered protocol family 10
+   [    0.731359] Segment Routing with IPv6
+   [    0.734332] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+   [    0.740687] NET: Registered protocol family 17
+   [    0.744660] Key type dns_resolver registered
+   [    0.806775] mmc0: host does not support reading read-only switch, assuming write-enable
+   [    0.814020] mmc0: new SDHC card on SPI
+   [    0.820137] mmcblk0: mmc0:0000 SU08G 7.40 GiB
+   [    0.850220]  mmcblk0: p1 p2
+   [    3.821524] macb 10090000.ethernet eth0: link up (1000/Full)
+   [    3.828938] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
+   [    3.848919] Sending DHCP requests .., OK
+   [    6.252076] IP-Config: Got DHCP answer from 10.206.4.1, my address is 10.206.7.133
+   [    6.259624] IP-Config: Complete:
+   [    6.262831]      device=eth0, hwaddr=70:b3:d5:92:f2:f3, ipaddr=10.206.7.133, mask=255.255.252.0, gw=10.206.4.1
+   [    6.272809]      host=dhcp-10-206-7-133, domain=sdcorp.global.sandisk.com, nis-domain=(none)
+   [    6.281228]      bootserver=10.206.126.11, rootserver=10.206.126.11, rootpath=
+   [    6.281232]      nameserver0=10.86.1.1, nameserver1=10.86.2.1
+   [    6.294179]      ntpserver0=10.86.1.1, ntpserver1=10.86.2.1
+   [    6.301026] Freeing unused kernel memory: 212K
+   [    6.304683] This architecture does not have kernel memory protection.
+   [    6.311121] Run /init as init process
+              _  _
+             | ||_|
+             | | _ ____  _   _  _  _
+             | || |  _ \| | | |\ \/ /
+             | || | | | | |_| |/    \
+             |_||_|_| |_|\____|\_/\_/
+
+                  Busybox Rootfs
+
+   Please press Enter to activate this console.
+   / #
+
+Booting from MMC using U-Boot SPL
+---------------------------------
+
+Building
+~~~~~~~~
+
+Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
+cloned and built for FU540 as below:
+
+.. code-block:: console
+
+	git clone https://github.com/riscv/opensbi.git
+	cd opensbi
+	make PLATFORM=generic
+	export OPENSBI=<path to opensbi/build/platform/generic/firmware/fw_dynamic.bin>
+
+Now build the U-Boot SPL and U-Boot proper
+
+.. code-block:: console
+
+	cd <U-Boot-dir>
+	make sifive_fu540_defconfig
+	make
+
+This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
+
+
+Flashing
+~~~~~~~~
+
+ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type
+5B193300-FC78-40CD-8002-E86C45580B47
+
+U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition with GUID
+type 2E54B353-1271-4842-806F-E436D6AF6985
+
+FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
+device tree blob (hifive-unleashed-a00.dtb)
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: none
+
+	# sudo sgdisk --clear \
+	> --set-alignment=2 \
+	> --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
+	> --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
+	> --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \
+	> /dev/sda
+
+Program the SD card
+
+.. code-block:: none
+
+	sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
+	sudo dd if=u-boot.itb of=/dev/sda seek=2082
+
+Booting
+~~~~~~~
+
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from HiFive Unleashed board
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: none
+
+	U-Boot SPL 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530)
+	Trying to boot from MMC1
+
+
+	U-Boot 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530)
+
+	CPU:   rv64imafdc
+	Model: SiFive HiFive Unleashed A00
+	DRAM:  8 GiB
+	MMC:   spi@10050000:mmc@0: 0
+	In:    serial@10010000
+	Out:   serial@10010000
+	Err:   serial@10010000
+	Net:   eth0: ethernet@10090000
+	Hit any key to stop autoboot:  0
+	=> version
+	U-Boot 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530)
+
+	riscv64-unknown-linux-gnu-gcc (crosstool-NG 1.24.0.37-3f461da) 9.2.0
+	GNU ld (crosstool-NG 1.24.0.37-3f461da) 2.32
+	=> mmc info
+	Device: spi@10050000:mmc@0
+	Manufacturer ID: 3
+	OEM: 5344
+	Name: SC16G
+	Bus Speed: 20000000
+	Mode: SD Legacy
+	Rd Block Len: 512
+	SD version 2.0
+	High Capacity: Yes
+	Capacity: 14.8 GiB
+	Bus Width: 1-bit
+	Erase Group Size: 512 Bytes
+	=> mmc part
+
+	Partition Map for MMC device 0  --   Partition Type: EFI
+
+	Part    Start LBA       End LBA         Name
+	Attributes
+	Type GUID
+	Partition GUID
+	1     0x00000022      0x00000821      "loader1"
+	attrs:  0x0000000000000000
+	type:   5b193300-fc78-40cd-8002-e86c45580b47
+	guid:   66e2b5d2-74db-4df8-ad6f-694b3617f87f
+	2     0x00000822      0x00002821      "loader2"
+	attrs:  0x0000000000000000
+	type:   2e54b353-1271-4842-806f-e436d6af6985
+	guid:   8befaeaf-bca0-435d-b002-e201f37c0a2f
+	3     0x00002822      0x01dacbde      "rootfs"
+	attrs:  0x0000000000000000
+	type:   0fc63daf-8483-4772-8e79-3d69d8477de4
+	type:   linux
+	guid:   9faa81b6-39b1-4418-af5e-89c48f29c20d
+
+Booting from SPI
+----------------
+
+Use Building steps from "Booting from MMC using U-Boot SPL" section.
+
+Partition the SPI in Linux via mtdblock. (Require to boot the board in
+SD boot mode by enabling MTD block in Linux)
+
+Use prebuilt image from here [1], which support to partition the SPI flash.
+
+.. code-block:: none
+
+  # sgdisk --clear \
+  > --set-alignment=2 \
+  > --new=1:40:2087 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
+  > --new=2:2088:10279 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
+  > --new=3:10536:65494 --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \
+  > /dev/mtdblock0
+
+Program the SPI (Require to boot the board in SD boot mode)
+
+Execute below steps on U-Boot proper,
+
+.. code-block:: none
+
+  tftpboot $kernel_addr_r u-boot-spl.bin
+  sf erase 0x5000 $filesize
+  sf write $kernel_addr_r 0x5000 $filesize
+
+  tftpboot $kernel_addr_r u-boot.itb
+  sf erase 0x105000 $filesize
+  sf write $kernel_addr_r 0x105000 $filesize
+
+Power off the board
+
+Change DIP switches MSEL[3:0] are set to 0110
+
+Power up the board.
+
+[1] https://github.com/amarula/bsp-sifive
diff --git a/roms/u-boot/doc/board/sifive/unmatched.rst b/roms/u-boot/doc/board/sifive/unmatched.rst
new file mode 100644
index 000000000..e65b0d320
--- /dev/null
+++ b/roms/u-boot/doc/board/sifive/unmatched.rst
@@ -0,0 +1,536 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+HiFive Unmatched
+================
+
+FU740-C000 RISC-V SoC
+---------------------
+The FU740-C000 is a 4+1 64-bit RISC-V core SoC from SiFive.
+
+The HiFive Unmatched development platform is based on FU740-C000 and capable
+of running Linux.
+
+Mainline support
+----------------
+The support for following drivers are already enabled:
+
+1. SiFive UART Driver.
+2. SiFive PRCI Driver for clock.
+3. Cadence MACB ethernet driver for networking support.
+4. SiFive SPI Driver.
+5. MMC SPI Driver for MMC/SD support.
+
+Booting from uSD using U-Boot SPL
+---------------------------------
+
+Building
+--------
+
+Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
+cloned and built for FU740 as below:
+
+.. code-block:: console
+
+	git clone https://github.com/riscv/opensbi.git
+	cd opensbi
+	make PLATFORM=generic
+	export OPENSBI=<path to opensbi/build/platform/generic/firmware/fw_dynamic.bin>
+
+Now build the U-Boot SPL and U-Boot proper
+
+.. code-block:: console
+
+	cd <U-Boot-dir>
+	make sifive_unmatched_defconfig
+	make
+
+This will generate spl/u-boot-spl.bin and u-boot.itb
+
+
+Flashing
+--------
+
+ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type
+5B193300-FC78-40CD-8002-E86C45580B47
+
+U-Boot SPL expects u-boot.itb from a partition with GUID
+type 2E54B353-1271-4842-806F-E436D6AF6985
+
+u-boot.itb is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
+device tree blob (hifive-unmatched-a00.dtb)
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: none
+
+	# sudo sgdisk -g --clear -a 1 \
+	> --new=1:34:2081         --change-name=1:spl --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
+	> --new=2:2082:10273      --change-name=2:uboot  --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
+	> --new=3:16384:282623    --change-name=3:boot --typecode=3:0x0700 \
+	> --new=4:286720:13918207 --change-name=4:root --typecode=4:0x8300 \
+	> /dev/sdb
+
+Copy linux Image.gz and hifive-unmatched-a00.dtb to boot partition
+
+.. code-block:: none
+
+	sudo mkfs.vfat /dev/sdb3
+	sudo mkfs.ext4 /dev/sdb4
+
+	sudo mount /dev/sdb3 /media/sdb3
+	sudo cp Image.gz hifive-unmatched-a00.dtb /media/sdb3/
+
+Program the SD card
+
+.. code-block:: none
+
+	sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
+	sudo dd if=u-boot.itb of=/dev/sda seek=2082
+
+Booting
+-------
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+
+Loading the kernel and dtb
+
+.. code-block:: none
+
+	fatload mmc 0:3 ${kernel_addr_r} Image.gz
+	fatload mmc 0:3 ${fdt_addr_r} hifive-unmatched-a00.dtb
+	booti ${kernel_addr_r} - ${fdt_addr_r}
+
+
+Sample boot log from HiFive Unmatched board
+-------------------------------------------
+
+.. code-block:: none
+
+	U-Boot SPL 2021.04-rc4-00009-g7d70643cc3-dirty (Mar 16 2021 - 18:03:14 +0800)
+	Trying to boot from MMC1
+
+	U-Boot 2021.04-rc4-00009-g7d70643cc3-dirty (Mar 16 2021 - 18:03:14 +0800)
+
+	CPU:   rv64imafdc
+	Model: SiFive HiFive Unmatched A00
+	DRAM:  16 GiB
+	MMC:   spi@10050000:mmc@0: 0
+	In:    serial@10010000
+	Out:   serial@10010000
+	Err:   serial@10010000
+	Model: SiFive HiFive Unmatched A00
+	Net:
+	Error: ethernet@10090000 address not set.
+	No ethernet found.
+
+	Hit any key to stop autoboot:  0
+	PCIe Link up, Gen1
+
+	Device 0: Vendor: 0x126f Rev: S1111A0L Prod: AA000000000000001995
+		    Type: Hard Disk
+		    Capacity: 488386.3 MB = 476.9 GB (1000215216 x 512)
+	... is now current device
+	Scanning nvme 0:1...
+	libfdt fdt_check_header(): FDT_ERR_BADMAGIC
+	Scanning disk mmc@0.blk...
+	** Unrecognized filesystem type **
+	** Unrecognized filesystem type **
+	Scanning disk nvme#0.blk#0...
+	Found 8 disks
+	No EFI system partition
+
+	Error: ethernet@10090000 address not set.
+	BootOrder not defined
+	EFI boot manager: Cannot load any image
+	starting USB...
+	Bus xhci_pci: Register 4000840 NbrPorts 4
+	Starting the controller
+	USB XHCI 1.00
+	scanning bus xhci_pci for devices... 3 USB Device(s) found
+	       scanning usb for storage devices... 0 Storage Device(s) found
+
+	Device 0: unknown device
+	switch to partitions #0, OK
+	mmc0 is current device
+	Scanning mmc 0:3...
+	Found /extlinux/extlinux.conf
+	Retrieving file: /extlinux/extlinux.conf
+	205 bytes read in 9 ms (21.5 KiB/s)
+	1:      OpenEmbedded-SiFive-HiFive-Unmatched
+	Retrieving file: /Image.gz
+	7225919 bytes read in 4734 ms (1.5 MiB/s)
+	append: root=/dev/mmcblk0p4 rootfstype=ext4 rootwait console=ttySIF0,115200 earlycon=sbi
+	Retrieving file: /hifive-unmatched-a00.dtb
+	10445 bytes read in 13 ms (784.2 KiB/s)
+	   Uncompressing Kernel Image
+	Moving Image from 0x84000000 to 0x80200000, end=81629000
+	## Flattened Device Tree blob at 88000000
+	   Booting using the fdt blob at 0x88000000
+	   Using Device Tree in place at 0000000088000000, end 00000000880058cc
+
+	Starting kernel ...
+
+	[    0.000000] Linux version 5.10.15 (oe-user@oe-host) (riscv64-oe-linux-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.0.201
+	[    0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
+	[    0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
+	[    0.000000] printk: bootconsole [sbi0] enabled
+	[    0.000000] efi: UEFI not found.
+	[    0.000000] Zone ranges:
+	[    0.000000]   DMA32    [mem 0x0000000080200000-0x00000000ffffffff]
+	[    0.000000]   Normal   [mem 0x0000000100000000-0x000000027fffffff]
+	[    0.000000] Movable zone start for each node
+	[    0.000000] Early memory node ranges
+	[    0.000000]   node   0: [mem 0x0000000080200000-0x000000027fffffff]
+	[    0.000000] Zeroed struct page in unavailable ranges: 512 pages
+	[    0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
+	[    0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
+	[    0.000000] SBI specification v0.3 detected
+	[    0.000000] SBI implementation ID=0x1 Version=0x9
+	[    0.000000] SBI v0.2 TIME extension detected
+	[    0.000000] SBI v0.2 IPI extension detected
+	[    0.000000] SBI v0.2 RFENCE extension detected
+	[    0.000000] SBI v0.2 HSM extension detected
+	[    0.000000] CPU with hartid=0 is not available
+	[    0.000000] CPU with hartid=0 is not available
+	[    0.000000] riscv: ISA extensions acdfim
+	[    0.000000] riscv: ELF capabilities acdfim
+	[    0.000000] percpu: Embedded 26 pages/cpu s66904 r8192 d31400 u106496
+	[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2067975
+	[    0.000000] Kernel command line: root=/dev/mmcblk0p4 rootfstype=ext4 rootwait console=ttySIF0,115200 earlycon=sbi
+	[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
+	[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
+	[    0.000000] Sorting __ex_table...
+	[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+	[    0.000000] Memory: 8155880K/8386560K available (8490K kernel code, 5515K rwdata, 4096K rodata, 285K init, 383K bss, 23)
+	[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+	[    0.000000] rcu: Hierarchical RCU implementation.
+	[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+	[    0.000000]  Tracing variant of Tasks RCU enabled.
+	[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+	[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+	[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
+	[    0.000000] CPU with hartid=0 is not available
+	[    0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
+	[    0.000000] riscv-intc: 64 local interrupts mapped
+	[    0.000000] plic: interrupt-controller@c000000: mapped 69 interrupts with 4 handlers for 9 contexts.
+	[    0.000000] random: get_random_bytes called from 0xffffffe000002a6a with crng_init=0
+	[    0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
+	[    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 352636161696s
+	[    0.000007] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
+	[    0.008626] Console: colour dummy device 80x25
+	[    0.013049] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000)
+	[    0.023115] pid_max: default: 32768 minimum: 301
+	[    0.028423] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+	[    0.035919] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+	[    0.045957] rcu: Hierarchical SRCU implementation.
+	[    0.050393] EFI services will not be available.
+	[    0.055132] smp: Bringing up secondary CPUs ...
+	[    0.061824] smp: Brought up 1 node, 4 CPUs
+	[    0.067458] devtmpfs: initialized
+	[    0.072700] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+	[    0.081789] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
+	[    0.089738] NET: Registered protocol family 16
+	[    0.093999] thermal_sys: Registered thermal governor 'step_wise'
+	[    0.109208] iommu: Default domain type: Translated
+	[    0.119694] vgaarb: loaded
+	[    0.122571] SCSI subsystem initialized
+	[    0.126499] usbcore: registered new interface driver usbfs
+	[    0.131686] usbcore: registered new interface driver hub
+	[    0.137071] usbcore: registered new device driver usb
+	[    0.142286] EDAC MC: Ver: 3.0.0
+	[    0.145760] Advanced Linux Sound Architecture Driver Initialized.
+	[    0.152205] clocksource: Switched to clocksource riscv_clocksource
+	[    1.046286] VFS: Disk quotas dquot_6.6.0
+	[    1.049651] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
+	[    1.062844] NET: Registered protocol family 2
+	[    1.067172] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
+	[    1.075455] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
+	[    1.085428] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear)
+	[    1.096548] TCP: Hash tables configured (established 65536 bind 65536)
+	[    1.103043] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
+	[    1.109879] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
+	[    1.117413] NET: Registered protocol family 1
+	[    1.121881] RPC: Registered named UNIX socket transport module.
+	[    1.127139] RPC: Registered udp transport module.
+	[    1.131901] RPC: Registered tcp transport module.
+	[    1.136677] RPC: Registered tcp NFSv4.1 backchannel transport module.
+	[    1.143194] PCI: CLS 0 bytes, default 64
+	[    1.148359] Initialise system trusted keyrings
+	[    1.152364] workingset: timestamp_bits=62 max_order=21 bucket_order=0
+	[    1.165382] NFS: Registering the id_resolver key type
+	[    1.169781] Key type id_resolver registered
+	[    1.174011] Key type id_legacy registered
+	[    1.178179] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
+	[    1.184874] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+	[    1.192453] 9p: Installing v9fs 9p2000 file system support
+	[    1.198116] NET: Registered protocol family 38
+	[    1.201886] Key type asymmetric registered
+	[    1.206046] Asymmetric key parser 'x509' registered
+	[    1.211029] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
+	[    1.218468] io scheduler mq-deadline registered
+	[    1.223072] io scheduler kyber registered
+	[    1.228803] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
+	[    1.235017] fu740-pcie e00000000.pcie: FPGA PCIE PROBE
+	[    1.281706] fu740-pcie e00000000.pcie: PCIE-PERSTN is GPIO 504
+	[    1.286922] fu740-pcie e00000000.pcie: PWREN is GPIO 501
+	[    1.292377] fu740-pcie e00000000.pcie: host bridge /soc/pcie@e00000000 ranges:
+	[    1.299603] fu740-pcie e00000000.pcie:       IO 0x0060080000..0x006008ffff -> 0x0060080000
+	[    1.307922] fu740-pcie e00000000.pcie:      MEM 0x0060090000..0x0070ffffff -> 0x0060090000
+	[    1.316244] fu740-pcie e00000000.pcie:      MEM 0x2000000000..0x3fffffffff -> 0x2000000000
+	[    1.432223] fu740-pcie e00000000.pcie: PWREN enabling
+	[    1.436607] fu740-pcie e00000000.pcie: PWREN valid
+	[    1.560226] fu740-pcie e00000000.pcie: invalid resource
+	[    1.664802] fu740-pcie e00000000.pcie: Link up
+	[    1.768582] fu740-pcie e00000000.pcie: Link up
+	[    1.872369] fu740-pcie e00000000.pcie: Link up
+	[    1.876116] fu740-pcie e00000000.pcie: Link up, Gen3
+	[    1.881352] fu740-pcie e00000000.pcie: PCI host bridge to bus 0000:00
+	[    1.887700] pci_bus 0000:00: root bus resource [bus 00-ff]
+	[    1.893247] pci_bus 0000:00: root bus resource [io  0x0000-0xffff] (bus address [0x60080000-0x6008ffff])
+	[    1.902807] pci_bus 0000:00: root bus resource [mem 0x60090000-0x70ffffff]
+	[    1.909748] pci_bus 0000:00: root bus resource [mem 0x2000000000-0x3fffffffff pref]
+	[    1.917517] pci 0000:00:00.0: [f15e:0000] type 01 class 0x060400
+	[    1.923569] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
+	[    1.929902] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
+	[    1.936723] pci 0000:00:00.0: supports D1
+	[    1.940755] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
+	[    1.947619] pci 0000:01:00.0: [1b21:2824] type 01 class 0x060400
+	[    1.953052] pci 0000:01:00.0: enabling Extended Tags
+	[    1.958165] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
+	[    1.976890] pci 0000:01:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+	[    1.984425] pci 0000:02:00.0: [1b21:2824] type 01 class 0x060400
+	[    1.990396] pci 0000:02:00.0: enabling Extended Tags
+	[    1.995509] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
+	[    2.001938] pci 0000:02:02.0: [1b21:2824] type 01 class 0x060400
+	[    2.007682] pci 0000:02:02.0: enabling Extended Tags
+	[    2.012793] pci 0000:02:02.0: PME# supported from D0 D3hot D3cold
+	[    2.019167] pci 0000:02:03.0: [1b21:2824] type 01 class 0x060400
+	[    2.024966] pci 0000:02:03.0: enabling Extended Tags
+	[    2.030075] pci 0000:02:03.0: PME# supported from D0 D3hot D3cold
+	[    2.036468] pci 0000:02:04.0: [1b21:2824] type 01 class 0x060400
+	[    2.042250] pci 0000:02:04.0: enabling Extended Tags
+	[    2.047359] pci 0000:02:04.0: PME# supported from D0 D3hot D3cold
+	[    2.053811] pci 0000:02:08.0: [1b21:2824] type 01 class 0x060400
+	[    2.059534] pci 0000:02:08.0: enabling Extended Tags
+	[    2.064647] pci 0000:02:08.0: PME# supported from D0 D3hot D3cold
+	[    2.071499] pci 0000:02:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+	[    2.078837] pci 0000:02:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+	[    2.086911] pci 0000:02:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+	[    2.094987] pci 0000:02:04.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+	[    2.103075] pci 0000:02:08.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+	[    2.111901] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
+	[    2.118031] pci 0000:04:00.0: [1b21:1142] type 00 class 0x0c0330
+	[    2.123968] pci 0000:04:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]
+	[    2.131038] pci 0000:04:00.0: PME# supported from D3cold
+	[    2.148888] pci_bus 0000:04: busn_res: [bus 04-ff] end is updated to 04
+	[    2.155588] pci_bus 0000:05: busn_res: [bus 05-ff] end is updated to 05
+	[    2.162286] pci_bus 0000:06: busn_res: [bus 06-ff] end is updated to 06
+	[    2.168408] pci 0000:07:00.0: [126f:2263] type 00 class 0x010802
+	[    2.174351] pci 0000:07:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit]
+	[    2.192890] pci_bus 0000:07: busn_res: [bus 07-ff] end is updated to 07
+	[    2.198837] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 07
+	[    2.205522] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 07
+	[    2.212241] pci 0000:00:00.0: BAR 0: assigned [mem 0x60100000-0x601fffff]
+	[    2.219067] pci 0000:00:00.0: BAR 14: assigned [mem 0x60200000-0x603fffff]
+	[    2.226010] pci 0000:00:00.0: BAR 6: assigned [mem 0x60090000-0x6009ffff pref]
+	[    2.233308] pci 0000:01:00.0: BAR 14: assigned [mem 0x60200000-0x603fffff]
+	[    2.240259] pci 0000:02:02.0: BAR 14: assigned [mem 0x60200000-0x602fffff]
+	[    2.247203] pci 0000:02:08.0: BAR 14: assigned [mem 0x60300000-0x603fffff]
+	[    2.254150] pci 0000:02:00.0: PCI bridge to [bus 03]
+	[    2.259217] pci 0000:04:00.0: BAR 0: assigned [mem 0x60200000-0x60207fff 64bit]
+	[    2.266594] pci 0000:02:02.0: PCI bridge to [bus 04]
+	[    2.271615] pci 0000:02:02.0:   bridge window [mem 0x60200000-0x602fffff]
+	[    2.278485] pci 0000:02:03.0: PCI bridge to [bus 05]
+	[    2.283529] pci 0000:02:04.0: PCI bridge to [bus 06]
+	[    2.288572] pci 0000:07:00.0: BAR 0: assigned [mem 0x60300000-0x60303fff 64bit]
+	[    2.295952] pci 0000:02:08.0: PCI bridge to [bus 07]
+	[    2.300973] pci 0000:02:08.0:   bridge window [mem 0x60300000-0x603fffff]
+	[    2.307842] pci 0000:01:00.0: PCI bridge to [bus 02-07]
+	[    2.313133] pci 0000:01:00.0:   bridge window [mem 0x60200000-0x603fffff]
+	[    2.320009] pci 0000:00:00.0: PCI bridge to [bus 01-07]
+	[    2.325288] pci 0000:00:00.0:   bridge window [mem 0x60200000-0x603fffff]
+	[    2.332808] pcieport 0000:00:00.0: AER: enabled with IRQ 51
+	[    2.337946] pcieport 0000:01:00.0: enabling device (0000 -> 0002)
+	[    2.344786] pcieport 0000:02:02.0: enabling device (0000 -> 0002)
+	[    2.351328] pcieport 0000:02:08.0: enabling device (0000 -> 0002)
+	[    2.357091] pci 0000:04:00.0: enabling device (0000 -> 0002)
+	[    2.362751] switchtec: loaded.
+	[    2.365933] L2CACHE: DataError @ 0x00000003.00964470
+	[    2.365992] L2CACHE: No. of Banks in the cache: 4
+	[    2.375414] L2CACHE: No. of ways per bank: 16
+	[    2.379846] L2CACHE: Sets per bank: 512
+	[    2.383751] L2CACHE: Bytes per cache block: 64
+	[    2.388267] L2CACHE: Index of the largest way enabled: 15
+	[    2.434865] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+	[    2.441695] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 1, base_baud = 115200) is a SiFive UART v0
+	[    2.450625] printk: console [ttySIF0] enabled
+	[    2.450625] printk: console [ttySIF0] enabled
+	[    2.459360] printk: bootconsole [sbi0] disabled
+	[    2.459360] printk: bootconsole [sbi0] disabled
+	[    2.468824] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 2, base_baud = 115200) is a SiFive UART v0
+	[    2.493853] loop: module loaded
+	[    2.526475] nvme nvme0: pci function 0000:07:00.0
+	[    2.530852] nvme 0000:07:00.0: enabling device (0000 -> 0002)
+	[    2.537716] Rounding down aligned max_sectors from 4294967295 to 4294967288
+	[    2.544470] db_root: cannot open: /etc/target
+	[    2.545926] nvme nvme0: allocated 64 MiB host memory buffer.
+	[    2.549020] sifive_spi 10040000.spi: mapped; irq=4, cs=1
+	[    2.559941] spi-nor spi0.0: is25wp256 (32768 Kbytes)
+	[    2.566431] sifive_spi 10050000.spi: mapped; irq=6, cs=1
+	[    2.566707] nvme nvme0: 4/0/0 default/read/poll queues
+	[    2.571935] libphy: Fixed MDIO Bus: probed
+	[    2.580950] macb 10090000.ethernet: Registered clk switch 'sifive-gemgxl-mgmt'
+	[    2.587536] macb 10090000.ethernet: invalid hw address, using random
+	[    2.588100]  nvme0n1: p1 p2
+	[    2.593875] BEU: Load or Store TILINK BUS ERR occurred
+	[    2.594342] libphy: MACB_mii_bus: probed
+	[    2.599312] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 7 (5e:57:b8:ab:24:4a)
+	[    2.615501] e1000e: Intel(R) PRO/1000 Network Driver
+	[    2.620251] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
+	[    2.626463] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+	[    2.632684] ehci-pci: EHCI PCI platform driver
+	[    2.637144] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
+	[    2.643273] ohci-pci: OHCI PCI platform driver
+	[    2.647731] uhci_hcd: USB Universal Host Controller Interface driver
+	[    2.654315] xhci_hcd 0000:04:00.0: xHCI Host Controller
+	[    2.659450] xhci_hcd 0000:04:00.0: new USB bus registered, assigned bus number 1
+	[    2.807373] xhci_hcd 0000:04:00.0: hcc params 0x0200e081 hci version 0x100 quirks 0x0000000010000410
+	[    2.816609] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
+	[    2.824115] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+	[    2.831312] usb usb1: Product: xHCI Host Controller
+	[    2.836174] usb usb1: Manufacturer: Linux 5.10.15 xhci-hcd
+	[    2.841652] usb usb1: SerialNumber: 0000:04:00.0
+	[    2.846639] hub 1-0:1.0: USB hub found
+	[    2.850037] hub 1-0:1.0: 2 ports detected
+	[    2.854306] xhci_hcd 0000:04:00.0: xHCI Host Controller
+	[    2.859335] xhci_hcd 0000:04:00.0: new USB bus registered, assigned bus number 2
+	[    2.866599] xhci_hcd 0000:04:00.0: Host supports USB 3.0 SuperSpeed
+	[    2.873638] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
+	[    2.881074] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.10
+	[    2.889212] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+	[    2.896422] usb usb2: Product: xHCI Host Controller
+	[    2.901282] usb usb2: Manufacturer: Linux 5.10.15 xhci-hcd
+	[    2.906752] usb usb2: SerialNumber: 0000:04:00.0
+	[    2.911671] hub 2-0:1.0: USB hub found
+	[    2.915130] hub 2-0:1.0: 2 ports detected
+	[    2.919486] usbcore: registered new interface driver usb-storage
+	[    2.925212] usbcore: registered new interface driver usbserial_generic
+	[    2.931620] usbserial: USB Serial support registered for generic
+	[    2.937771] mousedev: PS/2 mouse device common for all mice
+	[    2.943220] usbcore: registered new interface driver usbtouchscreen
+	[    2.949466] i2c /dev entries driver
+	[    2.954218] lm90 0-004c: supply vcc not found, using dummy regulator
+	[    2.961629] EDAC DEVICE0: Giving out device to module Sifive ECC Manager controller sifive_edac.0: DEV sifive_edac.0 (I)
+	[    2.997874] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no poweroff, cd polling
+	[    3.005138] ledtrig-cpu: registered to indicate activity on CPUs
+	[    3.010980] usbcore: registered new interface driver usbhid
+	[    3.016407] usbhid: USB HID core driver
+	[    3.020540] usbcore: registered new interface driver snd-usb-audio
+	[    3.027209] NET: Registered protocol family 10
+	[    3.031878] Segment Routing with IPv6
+	[    3.034864] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+	[    3.041232] NET: Registered protocol family 17
+	[    3.045324] 9pnet: Installing 9P2000 support
+	[    3.049397] Key type dns_resolver registered
+	[    3.053786] Loading compiled-in X.509 certificates
+	[    3.059729] ALSA device list:
+	[    3.061943]   No soundcards found.
+	[    3.066057] Waiting for root device /dev/mmcblk0p4...
+	[    3.077319] mmc0: host does not support reading read-only switch, assuming write-enable
+	[    3.084564] mmc0: new SDHC card on SPI
+	[    3.089699] mmcblk0: mmc0:0000 SD32G 29.7 GiB
+	[    3.126488] GPT:Primary header thinks Alt. header is not at the end of the disk.
+	[    3.133144] GPT:13918241 != 62333951
+	[    3.136679] GPT:Alternate GPT header not at the end of the disk.
+	[    3.142673] GPT:13918241 != 62333951
+	[    3.146231] GPT: Use GNU Parted to correct GPT errors.
+	[    3.151398]  mmcblk0: p1 p2 p3 p4
+	[    3.212226] usb 1-2: new high-speed USB device number 2 using xhci_hcd
+	[    3.258310] EXT4-fs (mmcblk0p4): INFO: recovery required on readonly filesystem
+	[    3.264855] EXT4-fs (mmcblk0p4): write access will be enabled during recovery
+	[    3.458247] usb 1-2: New USB device found, idVendor=174c, idProduct=2074, bcdDevice= 0.01
+	[    3.465662] usb 1-2: New USB device strings: Mfr=2, Product=3, SerialNumber=1
+	[    3.472775] usb 1-2: Product: AS2107
+	[    3.476336] usb 1-2: Manufacturer: ASMedia
+	[    3.480419] usb 1-2: SerialNumber: USB2.0 Hub
+	[    3.533583] EXT4-fs (mmcblk0p4): recovery complete
+	[    3.543756] EXT4-fs (mmcblk0p4): mounted filesystem with ordered data mode. Opts: (null)
+	[    3.551132] VFS: Mounted root (ext4 filesystem) readonly on device 179:4.
+	[    3.554682] hub 1-2:1.0: USB hub found
+	[    3.561105] devtmpfs: mounted
+	[    3.561778] hub 1-2:1.0: 4 ports detected
+	[    3.565546] Freeing unused kernel memory: 284K
+	[    3.572964] Kernel memory protection not selected by kernel config.
+	[    3.579225] Run /sbin/init as init process
+	[    3.613136] usb 2-2: new SuperSpeed Gen 1 USB device number 2 using xhci_hcd
+	[    3.643539] usb 2-2: New USB device found, idVendor=174c, idProduct=3074, bcdDevice= 0.01
+	[    3.650948] usb 2-2: New USB device strings: Mfr=2, Product=3, SerialNumber=1
+	[    3.658072] usb 2-2: Product: AS2107
+	[    3.661630] usb 2-2: Manufacturer: ASMedia
+	[    3.665709] usb 2-2: SerialNumber: USB2.0 Hub
+	[    3.762380] hub 2-2:1.0: USB hub found
+	[    3.766074] hub 2-2:1.0: 4 ports detected
+	[    7.487226] systemd[1]: System time before build time, advancing clock.
+	[    7.788093] systemd[1]: systemd 247.2+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +U)
+	[    7.809694] systemd[1]: Detected architecture riscv64.
+
+	Welcome to OpenEmbedded nodistro.0!
+
+	[    7.832648] systemd[1]: Set hostname to <unmatched>.
+	[    9.397499] systemd[1]: Queued start job for default target Multi-User System.
+	[    9.408518] random: systemd: uninitialized urandom read (16 bytes read)
+	[    9.429329] systemd[1]: Created slice system-getty.slice.
+	[  OK  ] Created slice system-getty.slice.
+	[    9.440400] random: systemd: uninitialized urandom read (16 bytes read)
+	[    9.447086] systemd[1]: Created slice system-modprobe.slice.
+	[  OK  ] Created slice system-modprobe.slice.
+	[    9.458480] random: systemd: uninitialized urandom read (16 bytes read)
+	[    9.465436] systemd[1]: Created slice system-serial\x2dgetty.slice.
+	[  OK  ] Created slice system-serial\x2dgetty.slice.
+	[    9.478594] systemd[1]: Created slice User and Session Slice.
+	[  OK  ] Created slice User and Session Slice.
+	[    9.490225] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
+	[  OK  ] Started Dispatch Password ��…ts to Console Directory Watch.
+	[    9.506407] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
+	[  OK  ] Started Forward Password R��…uests to Wall Directory Watch.
+	[    9.522312] systemd[1]: Reached target Paths.
+	[  OK  ] Reached target Paths.
+	[    9.531078] systemd[1]: Reached target Remote File Systems.
+	[  OK  ] Reached target Remote File Systems.
+	[    9.542855] systemd[1]: Reached target Slices.
+	[  OK  ] Reached target Slices.
+	[    9.552712] systemd[1]: Reached target Swap.
+	[  OK  ] Reached target Swap.
+	[    9.561566] systemd[1]: Listening on initctl Compatibility Named Pipe.
+	[  OK  ] Listening on initctl Compatibility Named Pipe.
+	[    9.578686] systemd[1]: Condition check resulted in Journal Audit Socket being skipped.
+	[    9.586545] systemd[1]: Listening on Journal Socket (/dev/log).
+	[  OK  ] Listening on Journal Socket (/dev/log).
+
+	[snip]
+
+	[  OK  ] Reached target System Time Synchronized.
+	[  OK  ] Reached target Timers.
+	[  OK  ] Listening on D-Bus System Message Bus Socket.
+	[  OK  ] Reached target Sockets.
+	[  OK  ] Reached target Basic System.
+	[  OK  ] Started D-Bus System Message Bus.
+		 Starting User Login Management...
+		 Starting Permit User Sessions...
+	[  OK  ] Started Xinetd A Powerful Replacement For Inetd.
+	[  OK  ] Finished Permit User Sessions.
+	[  OK  ] Started Getty on tty1.
+	[  OK  ] Started Serial Getty on hvc0.
+	[  OK  ] Started Serial Getty on ttySIF0.
+	[  OK  ] Reached target Login Prompts.
+	[  OK  ] Started User Login Management.
+	[  OK  ] Reached target Multi-User System.
+		 Starting Update UTMP about System Runlevel Changes...
+	[  OK  ] Finished Update UTMP about System Runlevel Changes.
+
+	OpenEmbedded nodistro.0 unmatched hvc0
+
+	unmatched login:
+	OpenEmbedded nodistro.0 unmatched ttySIF0
+
+	unmatched login:
diff --git a/roms/u-boot/doc/board/sipeed/index.rst b/roms/u-boot/doc/board/sipeed/index.rst
new file mode 100644
index 000000000..3518e2d8f
--- /dev/null
+++ b/roms/u-boot/doc/board/sipeed/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sipeed
+======
+
+.. toctree::
+   :maxdepth: 2
+
+   maix
diff --git a/roms/u-boot/doc/board/sipeed/maix.rst b/roms/u-boot/doc/board/sipeed/maix.rst
new file mode 100644
index 000000000..ef79297ef
--- /dev/null
+++ b/roms/u-boot/doc/board/sipeed/maix.rst
@@ -0,0 +1,697 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+
+MAIX
+====
+
+Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor,
+a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate
+neural network processing and other "ai" tasks. This includes a "KPU" neural
+network processor, an audio processor supporting beamforming reception, and a
+digital video port supporting capture and output at VGA resolution. Other
+peripherals include 8M of SRAM (accessible with and without caching); remappable
+pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller;
+and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash;
+on-board usb-serial bridges; ports for cameras, displays, and sd cards; and
+ESP32 chips.
+
+Currently, only the Sipeed MAIX BiT V2.0 (bitm) and Sipeed MAIXDUINO are
+supported, but the boards are fairly similar.
+
+Documentation for Maix boards is available from
+`Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_.
+Documentation for the Kendryte K210 is available from
+`Kendryte's website <https://kendryte.com/downloads/>`_. However, hardware
+details are rather lacking, so most technical reference has been taken from the
+`standalone sdk <https://github.com/kendryte/kendryte-standalone-sdk>`_.
+
+Build and boot steps
+--------------------
+
+To build U-Boot, run
+
+.. code-block:: none
+
+    make <defconfig>
+    make CROSS_COMPILE=<your cross compile prefix>
+
+To flash U-Boot, run
+
+.. code-block:: none
+
+    kflash -tp /dev/<your tty here> -B <board_id> u-boot-dtb.bin
+
+The board provides two serial devices, e.g.
+
+* /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if00-port0
+* /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if01-port0
+
+Which one is used for flashing depends on the board.
+
+Currently only a small subset of the board features are supported. So we can
+use the same default configuration and device tree. In the long run we may need
+separate settings.
+
+======================== ========================== ========== ==========
+Board                    defconfig                  board_id   TTY device
+======================== ========================== ========== ==========
+Sipeed MAIX BiT          sipeed_maix_bitm_defconfig bit        first
+Sipeed MAIX BiT with Mic sipeed_maix_bitm_defconfig bit_mic    first
+Sipeed MAIXDUINO         sipeed_maix_bitm_defconfig maixduino  first
+Sipeed MAIX GO                                      goE        second
+Sipeed MAIX ONE DOCK                                dan        first
+======================== ========================== ========== ==========
+
+Flashing causes a reboot of the device. Parameter -t specifies that the serial
+console shall be opened immediately. Boot output should look like the following:
+
+.. code-block:: none
+
+    U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
+
+    DRAM:  8 MiB
+    MMC:   spi@53000000:slot@0: 0
+    In:    serial@38000000
+    Out:   serial@38000000
+    Err:   serial@38000000
+    =>
+
+OpenSBI
+^^^^^^^
+
+OpenSBI is an open source supervisor execution environment implementing the
+RISC-V Supervisor Binary Interface Specification [1]. One of its features is
+to intercept run-time exceptions, e.g. for unaligned access or illegal
+instructions, and to emulate the failing instructions.
+
+The OpenSBI source can be downloaded via:
+
+.. code-block:: bash
+
+    git clone https://github.com/riscv/opensbi
+
+As OpenSBI will be loaded at 0x80000000 we have to adjust the U-Boot text base.
+Furthermore we have to enable building U-Boot for S-mode::
+
+    CONFIG_SYS_TEXT_BASE=0x80020000
+    CONFIG_RISCV_SMODE=y
+
+Both settings are contained in sipeed_maix_smode_defconfig so we can build
+U-Boot with:
+
+.. code-block:: bash
+
+    make sipeed_maix_smode_defconfig
+    make
+
+To build OpenSBI with U-Boot as a payload:
+
+.. code-block:: bash
+
+    cd opensbi
+    make \
+    PLATFORM=kendryte/k210 \
+    FW_PAYLOAD=y \
+    FW_PAYLOAD_OFFSET=0x20000 \
+    FW_PAYLOAD_PATH=<path to U-Boot>/u-boot-dtb.bin
+
+The value of FW_PAYLOAD_OFFSET must match CONFIG_SYS_TEXT_BASE - 0x80000000.
+
+The file to flash is build/platform/kendryte/k210/firmware/fw_payload.bin.
+
+Booting
+^^^^^^^
+
+The default boot process is to load and boot the files ``/uImage`` and
+``/k210.dtb`` off of the first partition of the MMC. For Linux, this will result
+in an output like
+
+.. code-block:: none
+
+    U-Boot 2020.10-00691-gd1d651d988-dirty (Oct 16 2020 - 17:05:24 -0400)
+
+    DRAM:  8 MiB
+    MMC:   spi@53000000:slot@0: 0
+    Loading Environment from SPIFlash... SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+    OK
+    In:    serial@38000000
+    Out:   serial@38000000
+    Err:   serial@38000000
+    Hit any key to stop autoboot:  0
+    1827380 bytes read in 1044 ms (1.7 MiB/s)
+    13428 bytes read in 10 ms (1.3 MiB/s)
+    ## Booting kernel from Legacy Image at 80060000 ...
+       Image Name:   linux
+       Image Type:   RISC-V Linux Kernel Image (uncompressed)
+       Data Size:    1827316 Bytes = 1.7 MiB
+       Load Address: 80000000
+       Entry Point:  80000000
+       Verifying Checksum ... OK
+    ## Flattened Device Tree blob at 80400000
+       Booting using the fdt blob at 0x80400000
+       Loading Kernel Image
+       Loading Device Tree to 00000000803f9000, end 00000000803ff473 ... OK
+
+    Starting kernel ...
+
+    [    0.000000] Linux version 5.9.0-00021-g6dcc2f0814c6-dirty (sean@godwin) (riscv64-linux-gnu-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #34 SMP Fri Oct 16 14:40:57 EDT 2020
+    [    0.000000] earlycon: sifive0 at MMIO 0x0000000038000000 (options '115200n8')
+    [    0.000000] printk: bootconsole [sifive0] enabled
+    [    0.000000] Zone ranges:
+    [    0.000000]   DMA32    [mem 0x0000000080000000-0x00000000807fffff]
+    [    0.000000]   Normal   empty
+    [    0.000000] Movable zone start for each node
+    [    0.000000] Early memory node ranges
+    [    0.000000]   node   0: [mem 0x0000000080000000-0x00000000807fffff]
+    [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000807fffff]
+    [    0.000000] riscv: ISA extensions acdfgim
+    [    0.000000] riscv: ELF capabilities acdfim
+    [    0.000000] percpu: max_distance=0x18000 too large for vmalloc space 0x0
+    [    0.000000] percpu: Embedded 12 pages/cpu s18848 r0 d30304 u49152
+    [    0.000000] Built 1 zonelists, mobility grouping off.  Total pages: 2020
+    [    0.000000] Kernel command line: earlycon console=ttySIF0
+    [    0.000000] Dentry cache hash table entries: 1024 (order: 1, 8192 bytes, linear)
+    [    0.000000] Inode-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
+    [    0.000000] Sorting __ex_table...
+    [    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+    [    0.000000] Memory: 6004K/8192K available (1139K kernel code, 126K rwdata, 198K rodata, 90K init, 81K bss, 2188K reserved, 0K cma-reserved)
+    [    0.000000] rcu: Hierarchical RCU implementation.
+    [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+    [    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
+    [    0.000000] riscv-intc: 64 local interrupts mapped
+    [    0.000000] plic: interrupt-controller@C000000: mapped 65 interrupts with 2 handlers for 2 contexts.
+    [    0.000000] random: get_random_bytes called from 0x00000000800019a8 with crng_init=0
+    [    0.000000] k210-clk: clock-controller
+    [    0.000000] k210-clk: clock-controller: fixed-rate 26 MHz osc base clock
+    [    0.000000] clint: clint@2000000: timer running at 7800000 Hz
+    [    0.000000] clocksource: clint_clocksource: mask: 0xffffffffffffffff max_cycles: 0x3990be68b, max_idle_ns: 881590404272 ns
+    [    0.000014] sched_clock: 64 bits at 7MHz, resolution 128ns, wraps every 4398046511054ns
+    [    0.008450] Console: colour dummy device 80x25
+    [    0.012494] Calibrating delay loop (skipped), value calculated using timer frequency.. 15.60 BogoMIPS (lpj=31200)
+    [    0.022693] pid_max: default: 4096 minimum: 301
+    [    0.027352] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
+    [    0.034428] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
+    [    0.045099] rcu: Hierarchical SRCU implementation.
+    [    0.050048] smp: Bringing up secondary CPUs ...
+    [    0.055417] smp: Brought up 1 node, 2 CPUs
+    [    0.059602] devtmpfs: initialized
+    [    0.082796] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+    [    0.091820] futex hash table entries: 16 (order: -2, 1024 bytes, linear)
+    [    0.098507] pinctrl core: initialized pinctrl subsystem
+    [    0.140938] clocksource: Switched to clocksource clint_clocksource
+    [    0.247216] workingset: timestamp_bits=62 max_order=11 bucket_order=0
+    [    0.277392] k210-fpioa 502b0000.pinmux: K210 FPIOA pin controller
+    [    0.291724] k210-sysctl 50440000.syscon: K210 system controller
+    [    0.305317] k210-rst 50440000.syscon:reset-controller: K210 reset controller
+    [    0.313808] 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 115200) is a SiFive UART v0
+    [    0.322712] printk: console [ttySIF0] enabled
+    [    0.322712] printk: console [ttySIF0] enabled
+    [    0.331328] printk: bootconsole [sifive0] disabled
+    [    0.331328] printk: bootconsole [sifive0] disabled
+    [    0.353347] Freeing unused kernel memory: 88K
+    [    0.357004] This architecture does not have kernel memory protection.
+    [    0.363397] Run /init as init process
+
+Loading, Booting, and Storing Images
+------------------------------------
+
+.. _loading:
+
+Loading Images
+^^^^^^^^^^^^^^
+
+Serial
+""""""
+
+Use the ``loady`` command to load images over serial.
+
+.. code-block:: none
+
+    => loady $loadaddr 1500000
+    ## Switch baudrate to 1500000 bps and press ENTER ...
+
+    *** baud: 1500000
+
+    *** baud: 1500000 ***
+    ## Ready for binary (ymodem) download to 0x80000000 at 1500000 bps...
+    C
+    *** file: loader.bin
+    $ sz -vv loader.bin
+    Sending: loader.bin
+    Bytes Sent:2478208   BPS:72937
+    Sending:
+    Ymodem sectors/kbytes sent:   0/ 0k
+    Transfer complete
+
+    *** exit status: 0 ***
+    ## Total Size      = 0x0025d052 = 2478162 Bytes
+    ## Switch baudrate to 115200 bps and press ESC ...
+
+    *** baud: 115200
+
+    *** baud: 115200 ***
+    =>
+
+This command does not set ``$filesize``, so it may need to be set manually.
+
+SPI Flash
+"""""""""
+
+To load an image off of SPI flash, first set up a partition as described in
+:ref:`k210_partitions`. Then, use ``mtd`` to load that partition
+
+.. code-block:: none
+
+    => sf probe
+    SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+    => mtd read linux $loadaddr
+    Reading 2097152 byte(s) at offset 0x00000000
+
+This command does not set ``$filesize``, so it may need to be set manually.
+
+MMC
+"""
+
+The MMC device number is 0. To list partitions on the device, use ``part``:
+
+.. code-block:: none
+
+    => part list mmc 0
+
+    Partition Map for MMC device 0  --   Partition Type: EFI
+
+    Part    Start LBA       End LBA          Name
+            Attributes
+            Type GUID
+            Partition GUID
+      1     0x00000800      0x039effde      "boot"
+            attrs:  0x0000000000000000
+            type:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
+            guid:   96161f7d-7113-4cc7-9a24-08ab7fc5cb72
+
+To list files, use ``ls``:
+
+.. code-block:: none
+
+    => ls mmc 0:1
+    <DIR>       4096 .
+    <DIR>       4096 ..
+    <DIR>      16384 lost+found
+               13428 k210.dtb
+             1827380 uImage
+
+To load a file, use ``load``:
+
+.. code-block:: none
+
+    => load mmc 0:1 $loadaddr uImage
+    1827380 bytes read in 1049 ms (1.7 MiB/s)
+
+Running Programs
+^^^^^^^^^^^^^^^^
+
+Binaries
+""""""""
+
+To run a bare binary, use the ``go`` command:
+
+.. code-block:: none
+
+    => go 80000000
+    ## Starting application at 0x80000000 ...
+    Example expects ABI version 9
+    Actual U-Boot ABI version 9
+    Hello World
+    argc = 1
+    argv[0] = "80000000"
+    argv[1] = "<NULL>"
+    Hit any key to exit ...
+
+Note that this will only start a program on one hart. As-of this writing it is
+only possible to start a program on multiple harts using the ``bootm`` command.
+
+Legacy Images
+"""""""""""""
+
+To create a legacy image, use ``tools/mkimage``:
+
+.. code-block:: none
+
+    $ tools/mkimage -A riscv -O linux -T kernel -C none -a 0x80000000 -e 0x80000000 -n linux -d ../linux-git/arch/riscv/boot/Image uImage
+    Image Name:   linux
+    Created:      Fri Oct 16 17:36:32 2020
+    Image Type:   RISC-V Linux Kernel Image (uncompressed)
+    Data Size:    1827316 Bytes = 1784.49 KiB = 1.74 MiB
+    Load Address: 80000000
+    Entry Point:  80000000
+
+The ``bootm`` command also requires an FDT, even if the image doesn't require
+one. After loading the image to ``$loadaddr`` and the FDT to ``$fdt_addr_r``,
+boot with:
+
+.. code-block:: none
+
+    => bootm $loadaddr - $fdt_addr_r
+    ## Booting kernel from Legacy Image at 80060000 ...
+       Image Name:   linux
+       Image Type:   RISC-V Linux Kernel Image (uncompressed)
+       Data Size:    1827316 Bytes = 1.7 MiB
+       Load Address: 80000000
+       Entry Point:  80000000
+       Verifying Checksum ... OK
+    ## Flattened Device Tree blob at 80400000
+       Booting using the fdt blob at 0x80400000
+       Loading Kernel Image
+       Loading Device Tree to 00000000803f9000, end 00000000803ff473 ... OK
+
+    Starting kernel ...
+
+The FDT is verified after the kernel is relocated, so it must be loaded high
+enough so that it won't be overwritten. The default values for ``$loadaddr``
+and ``$fdt_addr_r`` should provide ample headroom for most use-cases.
+
+Flashing Images
+^^^^^^^^^^^^^^^
+
+SPI Flash
+"""""""""
+
+To flash data to SPI flash, first load it using one of the methods in
+:ref:`loading`. Addiotionally, create some partitions as described in
+:ref:`partitions`. Then use the ``mtd`` command:
+
+.. code-block:: none
+
+    => sf probe
+    SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+    => mtd write linux $loadaddr 0 $filesize
+    Writing 2478162 byte(s) at offset 0x00000000
+
+Note that in order to write a bootable image, a header and tailer must be added.
+
+MMC
+"""
+
+MMC writes are unsupported for now.
+
+SPI Flash
+^^^^^^^^^
+
+Sipeed MAIX boards typically provide around 16 MiB of SPI NOR flash. U-Boot is
+stored in the first 1 MiB or so of this flash. U-Boot's environment is stored at
+the end of flash.
+
+.. _k210_partitions:
+
+Partitions
+""""""""""
+
+There is no set data layout. The default partition layout only allocates
+partitions for U-Boot and its default environment
+
+.. code-block:: none
+
+    => mtd list
+    List of MTD devices:
+    * nor0
+      - type: NOR flash
+      - block size: 0x1000 bytes
+      - min I/O: 0x1 bytes
+      - 0x000000000000-0x000001000000 : "nor0"
+          - 0x000000000000-0x000000100000 : "u-boot"
+          - 0x000000fff000-0x000001000000 : "env"
+
+As an example, to allocate 2MiB for Linux and (almost) 13 MiB for other data,
+set the ``mtdparts`` like:
+
+.. code-block:: none
+
+    => env set mtdparts nor0:1M(u-boot),2M(linux),0xcff000(data),0x1000@0xfff000(env)
+    => mtd list
+    List of MTD devices:
+    * nor0
+      - type: NOR flash
+      - block size: 0x1000 bytes
+      - min I/O: 0x1 bytes
+      - 0x000000000000-0x000001000000 : "nor0"
+          - 0x000000000000-0x000000100000 : "u-boot"
+          - 0x000000100000-0x000000300000 : "linux"
+          - 0x000000300000-0x000000fff000 : "data"
+          - 0x000000fff000-0x000001000000 : "env"
+
+To make these changes permanent, save the environment:
+
+.. code-block:: none
+
+    => env save
+    Saving Environment to SPIFlash... Erasing SPI flash...Writing to SPI flash...done
+    OK
+
+U-Boot will always load the environment from the last 4 KiB of flash.
+
+Pin Assignment
+--------------
+
+The K210 contains a Fully Programmable I/O Array (FPIOA), which can remap any of
+its 256 input functions to any any of 48 output pins. The following table has
+the default pin assignments for the BitM.
+
+===== ========== =======
+Pin   Function   Comment
+===== ========== =======
+IO_0  JTAG_TCLK
+IO_1  JTAG_TDI
+IO_2  JTAG_TMS
+IO_3  JTAG_TDO
+IO_4  UARTHS_RX
+IO_5  UARTHS_TX
+IO_6             Not set
+IO_7             Not set
+IO_8  GPIO_0
+IO_9  GPIO_1
+IO_10 GPIO_2
+IO_11 GPIO_3
+IO_12 GPIO_4     Green LED
+IO_13 GPIO_5     Red LED
+IO_14 GPIO_6     Blue LED
+IO_15 GPIO_7
+IO_16 GPIOHS_0   ISP
+IO_17 GPIOHS_1
+IO_18 I2S0_SCLK  MIC CLK
+IO_19 I2S0_WS    MIC WS
+IO_20 I2S0_IN_D0 MIC SD
+IO_21 GPIOHS_5
+IO_22 GPIOHS_6
+IO_23 GPIOHS_7
+IO_24 GPIOHS_8
+IO_25 GPIOHS_9
+IO_26 SPI1_D1    MMC MISO
+IO_27 SPI1_SCLK  MMC CLK
+IO_28 SPI1_D0    MMC MOSI
+IO_29 GPIOHS_13  MMC CS
+IO_30 GPIOHS_14
+IO_31 GPIOHS_15
+IO_32 GPIOHS_16
+IO_33 GPIOHS_17
+IO_34 GPIOHS_18
+IO_35 GPIOHS_19
+IO_36 GPIOHS_20  Panel CS
+IO_37 GPIOHS_21  Panel RST
+IO_38 GPIOHS_22  Panel DC
+IO_39 SPI0_SCK   Panel WR
+IO_40 SCCP_SDA
+IO_41 SCCP_SCLK
+IO_42 DVP_RST
+IO_43 DVP_VSYNC
+IO_44 DVP_PWDN
+IO_45 DVP_HSYNC
+IO_46 DVP_XCLK
+IO_47 DVP_PCLK
+===== ========== =======
+
+Over- and Under-clocking
+------------------------
+
+To change the clock speed of the K210, you will need to enable
+``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a
+section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following:
+
+.. code-block:: none
+
+    &sysclk {
+	assigned-clocks = <&sysclk K210_CLK_PLL0>;
+	assigned-clock-rates = <800000000>;
+    };
+
+There are three PLLs on the K210: PLL0 is the parent of most of the components,
+including the CPU and RAM. PLL1 is the parent of the neural network coprocessor.
+PLL2 is the parent of the sound processing devices. Note that child clocks of
+PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is
+running at 800 MHz, then the CPU will run at 400 MHz. This is the example given
+above. The CPU can be overclocked to around 600 MHz, and underclocked to 26 MHz.
+
+It is possible to set PLL2's parent to PLL0. The plls are more accurate when
+converting between similar frequencies. This makes it easier to get an accurate
+frequency for I2S. As an example, consider sampling an I2S device at 44.1 kHz.
+On this device, the I2S serial clock runs at 64 times the sample rate.
+Therefore, we would like to run PLL2 at an even multiple of 2.8224 MHz. If
+PLL2's parent is IN0, we could use a frequency of 390 MHz (the same as the CPU's
+default speed).  Dividing by 138 yields a serial clock of about 2.8261 MHz. This
+results in a sample rate of 44.158 kHz---around 50 Hz or .1% too fast. If,
+instead, we set PLL2's parent to PLL1 running at 390 MHz, and request a rate of
+2.8224 * 136 = 383.8464 MHz, the achieved rate is 383.90625 MHz. Dividing by 136
+yields a serial clock of about 2.8228 MHz. This results in a sample rate of
+44.107 kHz---just 7 Hz or .02% too fast. This configuration is shown in the
+following example:
+
+.. code-block:: none
+
+    &sysclk {
+	assigned-clocks = <&sysclk K210_CLK_PLL1>, <&sysclk K210_CLK_PLL2>;
+	assigned-clock-parents = <0>, <&sysclk K210_CLK_PLL1>;
+	assigned-clock-rates = <390000000>, <383846400>;
+    };
+
+There are a couple of quirks to the PLLs. First, there are more frequency ratios
+just above and below 1.0, but there is a small gap around 1.0. To be explicit,
+if the input frequency is 100 MHz, it would be impossible to have an output of
+99 or 101 MHz. In addition, there is a maximum frequency for the internal VCO,
+so higher input/output frequencies will be less accurate than lower ones.
+
+Technical Details
+-----------------
+
+Boot Sequence
+^^^^^^^^^^^^^
+
+1. ``RESET`` pin is deasserted. The pin is connected to the ``RESET`` button. It
+   can also be set to low via either the ``DTR`` or the ``RTS`` line of the
+   serial interface (depending on the board).
+2. Both harts begin executing at ``0x00001000``.
+3. Both harts jump to firmware at ``0x88000000``.
+4. One hart is chosen as a boot hart.
+5. Firmware reads the value of pin ``IO_16`` (ISP). This pin is connected to the
+   ``BOOT`` button. The pin can equally be set to low via either the ``DTR`` or
+   ``RTS`` line of the serial interface (depending on the board).
+
+   * If the pin is low, enter ISP mode. This mode allows loading data to ram,
+     writing it to flash, and booting from specific addresses.
+   * If the pin is high, continue boot.
+6. Firmware reads the next stage from flash (SPI3) to address ``0x80000000``.
+
+   * If byte 0 is 1, the next stage is decrypted using the built-in AES
+     accelerator and the one-time programmable, 128-bit AES key.
+   * Bytes 1 to 4 hold the length of the next stage.
+   * The SHA-256 sum of the next stage is automatically calculated, and verified
+     against the 32 bytes following the next stage.
+7. The boot hart sends an IPI to the other hart telling it to jump to the next
+   stage.
+8. The boot hart jumps to ``0x80000000``.
+
+Debug UART
+^^^^^^^^^^
+
+The Debug UART is provided with the following settings::
+
+    CONFIG_DEBUG_UART=y
+    CONFIG_DEBUG_UART_SIFIVE=y
+    CONFIG_DEBUG_UART_BASE=0x38000000
+    CONFIG_DEBUG_UART_CLOCK=390000000
+
+Resetting the board
+^^^^^^^^^^^^^^^^^^^
+
+The MAIX boards can be reset using the DTR and RTS lines of the serial console.
+How the lines are used depends on the specific board. See the code of kflash.py
+for details.
+
+This is the reset sequence for the MAXDUINO and MAIX BiT with Mic:
+
+.. code-block:: python
+
+   def reset(self):
+        self.device.setDTR(False)
+        self.device.setRTS(False)
+        time.sleep(0.1)
+        self.device.setDTR(True)
+        time.sleep(0.1)
+        self.device.setDTR(False)
+        time.sleep(0.1)
+
+and this for the MAIX Bit:
+
+.. code-block:: python
+
+   def reset(self):
+        self.device.setDTR(False)
+        self.device.setRTS(False)
+        time.sleep(0.1)
+        self.device.setRTS(True)
+        time.sleep(0.1)
+        self.device.setRTS(False)
+        time.sleep(0.1)
+
+Memory Map
+^^^^^^^^^^
+
+========== ========= ===========
+Address    Size      Description
+========== ========= ===========
+0x00000000 0x1000    debug
+0x00001000 0x1000    rom
+0x02000000 0xC000    clint
+0x0C000000 0x4000000 plic
+0x38000000 0x1000    uarths
+0x38001000 0x1000    gpiohs
+0x40000000 0x400000  sram0 (non-cached)
+0x40400000 0x200000  sram1 (non-cached)
+0x40600000 0x200000  airam (non-cached)
+0x40800000 0xC00000  kpu
+0x42000000 0x400000  fft
+0x50000000 0x1000    dmac
+0x50200000 0x200000  apb0
+0x50200000 0x80      gpio
+0x50210000 0x100     uart0
+0x50220000 0x100     uart1
+0x50230000 0x100     uart2
+0x50240000 0x100     spi slave
+0x50250000 0x200     i2s0
+0x50250200 0x200     apu
+0x50260000 0x200     i2s1
+0x50270000 0x200     i2s2
+0x50280000 0x100     i2c0
+0x50290000 0x100     i2c1
+0x502A0000 0x100     i2c2
+0x502B0000 0x100     fpioa
+0x502C0000 0x100     sha256
+0x502D0000 0x100     timer0
+0x502E0000 0x100     timer1
+0x502F0000 0x100     timer2
+0x50400000 0x200000  apb1
+0x50400000 0x100     wdt0
+0x50410000 0x100     wdt1
+0x50420000 0x100     otp control
+0x50430000 0x100     dvp
+0x50440000 0x100     sysctl
+0x50450000 0x100     aes
+0x50460000 0x100     rtc
+0x52000000 0x4000000 apb2
+0x52000000 0x100     spi0
+0x53000000 0x100     spi1
+0x54000000 0x200     spi3
+0x80000000 0x400000  sram0 (cached)
+0x80400000 0x200000  sram1 (cached)
+0x80600000 0x200000  airam (cached)
+0x88000000 0x20000   otp
+0x88000000 0xC200    firmware
+0x8801C000 0x1000    riscv priv spec 1.9 config
+0x8801D000 0x2000    flattened device tree (contains only addresses and
+                     interrupts)
+0x8801F000 0x1000    credits
+========== ========= ===========
+
+Links
+-----
+
+[1] https://github.com/riscv/riscv-sbi-doc
+    RISC-V Supervisor Binary Interface Specification
diff --git a/roms/u-boot/doc/board/st/index.rst b/roms/u-boot/doc/board/st/index.rst
new file mode 100644
index 000000000..91f1d51b4
--- /dev/null
+++ b/roms/u-boot/doc/board/st/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+STMicroelectronics
+==================
+
+.. toctree::
+   :maxdepth: 2
+
+   stm32mp1
diff --git a/roms/u-boot/doc/board/st/stm32mp1.rst b/roms/u-boot/doc/board/st/stm32mp1.rst
new file mode 100644
index 000000000..f0c2b09b9
--- /dev/null
+++ b/roms/u-boot/doc/board/st/stm32mp1.rst
@@ -0,0 +1,614 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Patrick Delaunay <patrick.delaunay@foss.st.com>
+
+STM32MP15x boards
+=================
+
+This is a quick instruction for setup STM32MP15x boards.
+
+Supported devices
+-----------------
+
+U-Boot supports STMP32MP15x SoCs:
+
+ - STM32MP157
+ - STM32MP153
+ - STM32MP151
+
+The STM32MP15x is a Cortex-A MPU aimed at various applications.
+
+It features:
+
+ - Dual core Cortex-A7 application core (Single on STM32MP151)
+ - 2D/3D image composition with GPU (only on STM32MP157)
+ - Standard memories interface support
+ - Standard connectivity, widely inherited from the STM32 MCU family
+ - Comprehensive security support
+
+Each line comes with a security option (cryptography & secure boot) and
+a Cortex-A frequency option:
+
+ - A : Cortex-A7 @ 650 MHz
+ - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
+ - D : Cortex-A7 @ 800 MHz
+ - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
+
+Everything is supported in Linux but U-Boot is limited to:
+
+ 1. UART
+ 2. SD card/MMC controller (SDMMC)
+ 3. NAND controller (FMC)
+ 4. NOR controller (QSPI)
+ 5. USB controller (OTG DWC2)
+ 6. Ethernet controller
+
+And the necessary drivers
+
+ 1. I2C
+ 2. STPMIC1 (PMIC and regulator)
+ 3. Clock, Reset, Sysreset
+ 4. Fuse
+
+Currently the following boards are supported:
+
+ + stm32mp157a-dk1.dts
+ + stm32mp157c-dk2.dts
+ + stm32mp157c-ed1.dts
+ + stm32mp157c-ev1.dts
+ + stm32mp15xx-dhcor-avenger96.dts
+
+Boot Sequences
+--------------
+
+3 boot configurations are supported with:
+
++----------+------------------------+-------------------------+--------------+
+| **ROM**  | **FSBL**               | **SSBL**                | **OS**       |
++ **code** +------------------------+-------------------------+--------------+
+|          | First Stage Bootloader | Second Stage Bootloader | Linux Kernel |
++          +------------------------+-------------------------+--------------+
+|          | embedded RAM           | DDR                                    |
++----------+------------------------+-------------------------+--------------+
+
+The **Trusted** boot chain
+``````````````````````````
+
+defconfig_file : stm32mp15_trusted_defconfig
+
+    +-------------+-------------------------+------------+-------+
+    |  ROM code   | FSBL                    | SSBL       | OS    |
+    +             +-------------------------+------------+-------+
+    |             |Trusted Firmware-A (TF-A)| U-Boot     | Linux |
+    +-------------+-------------------------+------------+-------+
+    | TrustZone   |secure monitor                                |
+    +-------------+-------------------------+------------+-------+
+
+TF-A performs a full initialization of Secure peripherals and installs a
+secure monitor, BL32:
+
+  * SPMin provided by TF-A or
+  * OP-TEE from specific partitions (teeh, teed, teex).
+
+U-Boot is running in normal world and uses the secure monitor to access
+to secure resources.
+
+The **Basic** boot chain
+````````````````````````
+
+defconfig_file : stm32mp15_basic_defconfig
+
+    +-------------+------------+------------+-------+
+    |  ROM code   | FSBL       | SSBL       | OS    |
+    +             +------------+------------+-------+
+    |             |U-Boot SPL  | U-Boot     | Linux |
+    +-------------+------------+------------+-------+
+    | TrustZone   |            | PSCI from U-Boot   |
+    +-------------+------------+------------+-------+
+
+SPL has limited security initialization
+
+U-Boot is running in secure mode and provide a secure monitor to the kernel
+with only PSCI support (Power State Coordination Interface defined by ARM).
+
+All the STM32MP15x boards supported by U-Boot use the same generic board
+stm32mp1 which support all the bootable devices.
+
+Each board is configured only with the associated device tree.
+
+Device Tree Selection
+---------------------
+
+You need to select the appropriate device tree for your board,
+the supported device trees for STM32MP15x are:
+
++ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)
+
+   + stm32mp157c-ev1
+
++ ed1: daughter board with pmic stpmic1
+
+   + stm32mp157c-ed1
+
++ dk1: Discovery board
+
+   + stm32mp157a-dk1
+
++ dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel
+
+   + stm32mp157c-dk2
+
++ avenger96: Avenger96 board from Arrow Electronics based on DH Elec. DHCOR SoM
+
+   + stm32mp15xx-dhcor-avenger96
+
+Build Procedure
+---------------
+
+1. Install the required tools for U-Boot
+
+   * install package needed in U-Boot makefile
+     (libssl-dev, swig, libpython-dev...)
+
+   * install ARMv7 toolchain for 32bit Cortex-A (from Linaro,
+     from SDK for STM32MP15x, or any crosstoolchains from your distribution)
+     (you can use any gcc cross compiler compatible with U-Boot)
+
+2. Set the cross compiler::
+
+    # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi-
+
+3. Select the output directory (optional)::
+
+   # export KBUILD_OUTPUT=/path/to/output
+
+   for example: use one output directory for each configuration::
+
+   # export KBUILD_OUTPUT=stm32mp15_trusted
+   # export KBUILD_OUTPUT=stm32mp15_basic
+
+   you can build outside of code directory::
+
+   # export KBUILD_OUTPUT=../build/stm32mp15_trusted
+
+4. Configure U-Boot::
+
+   # make <defconfig_file>
+
+   with <defconfig_file>:
+
+   - For **trusted** boot mode : **stm32mp15_trusted_defconfig**
+   - For basic boot mode: stm32mp15_basic_defconfig
+
+5. Configure the device-tree and build the U-Boot image::
+
+   # make DEVICE_TREE=<name> all
+
+   Examples:
+
+  a) trusted boot on ev1::
+
+     # export KBUILD_OUTPUT=stm32mp15_trusted
+     # make stm32mp15_trusted_defconfig
+     # make DEVICE_TREE=stm32mp157c-ev1 all
+
+  b) trusted with OP-TEE boot on dk2::
+
+      # export KBUILD_OUTPUT=stm32mp15_trusted
+      # make stm32mp15_trusted_defconfig
+      # make DEVICE_TREE=stm32mp157c-dk2 all
+
+  c) basic boot on ev1::
+
+      # export KBUILD_OUTPUT=stm32mp15_basic
+      # make stm32mp15_basic_defconfig
+      # make DEVICE_TREE=stm32mp157c-ev1 all
+
+  d) basic boot on ed1::
+
+      # export KBUILD_OUTPUT=stm32mp15_basic
+      # make stm32mp15_basic_defconfig
+      # make DEVICE_TREE=stm32mp157c-ed1 all
+
+  e) basic boot on dk1::
+
+     # export KBUILD_OUTPUT=stm32mp15_basic
+     # make stm32mp15_basic_defconfig
+     # make DEVICE_TREE=stm32mp157a-dk1 all
+
+  f) basic boot on avenger96::
+
+     # export KBUILD_OUTPUT=stm32mp15_basic
+     # make stm32mp15_basic_defconfig
+     # make DEVICE_TREE=stm32mp15xx-dhcor-avenger96 all
+
+6. Output files
+
+   BootRom and TF-A expect binaries with STM32 image header
+   SPL expects file with U-Boot uImage header
+
+   So in the output directory (selected by KBUILD_OUTPUT),
+   you can found the needed files:
+
+  - For **Trusted** boot (with or without OP-TEE)
+
+     - FSBL = **tf-a.stm32** (provided by TF-A compilation)
+     - SSBL = **u-boot.stm32**
+
+  - For Basic boot
+
+     - FSBL = spl/u-boot-spl.stm32
+     - SSBL = u-boot.img (without CONFIG_SPL_LOAD_FIT) or
+              u-boot.itb (with CONFIG_SPL_LOAD_FIT=y)
+
+Switch Setting for Boot Mode
+----------------------------
+
+You can select the boot mode, on the board with one switch, to select
+the boot pin values = BOOT0, BOOT1, BOOT2
+
+  +-------------+---------+---------+---------+
+  |*Boot Mode*  | *BOOT2* | *BOOT1* | *BOOT0* |
+  +=============+=========+=========+=========+
+  | Recovery    |  0      |  0      |  0      |
+  +-------------+---------+---------+---------+
+  | NOR         |  0      |  0      |  1      |
+  +-------------+---------+---------+---------+
+  | eMMC        |  0      |  1      |  0      |
+  +-------------+---------+---------+---------+
+  | NAND        |  0      |  1      |  1      |
+  +-------------+---------+---------+---------+
+  | Reserved    |  1      |  0      |  0      |
+  +-------------+---------+---------+---------+
+  | SD-Card     |  1      |  0      |  1      |
+  +-------------+---------+---------+---------+
+  | Recovery    |  1      |  1      |  0      |
+  +-------------+---------+---------+---------+
+  | SPI-NAND    |  1      |  1      |  1      |
+  +-------------+---------+---------+---------+
+
+- on the **daugther board ed1 = MB1263** with the switch SW1
+- on **Avenger96** with switch S3 (NOR and SPI-NAND are not applicable)
+- on board **DK1/DK2** with the switch SW1 = BOOT0, BOOT2
+  with only 2 pins available (BOOT1 is forced to 0 and NOR not supported),
+  the possible value becomes:
+
+    +-------------+---------+---------+
+    |*Boot Mode*  | *BOOT2* | *BOOT0* |
+    +=============+=========+=========+
+    | Recovery    |  0      |  0      |
+    +-------------+---------+---------+
+    | NOR     (NA)|  0      |  1      |
+    +-------------+---------+---------+
+    | Reserved    |  1      |  0      |
+    +-------------+---------+---------+
+    | SD-Card     |  1      |  1      |
+    +-------------+---------+---------+
+
+Recovery is a boot from serial link (UART/USB) and it is used with
+STM32CubeProgrammer tool to load executable in RAM and to update the flash
+devices available on the board (NOR/NAND/eMMC/SD card).
+
+The communication between HOST and board is based on
+
+  - for UARTs : the uart protocol used with all MCU STM32
+  - for USB : based on USB DFU 1.1 (without the ST extensions used on MCU STM32)
+
+Prepare an SD card
+------------------
+
+The minimal requirements for STMP32MP15x boot up to U-Boot are:
+
+- GPT partitioning (with gdisk or with sgdisk)
+- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB
+- one ssbl partition for U-Boot
+
+Then the minimal GPT partition is:
+
+  +-------+--------+---------+-------------+
+  | *Num* | *Name* | *Size*  | *Content*   |
+  +=======+========+=========+=============+
+  | 1     | fsbl1  | 256 KiB | TF-A or SPL |
+  +-------+--------+---------+-------------+
+  | 2     | fsbl2  | 256 KiB | TF-A or SPL |
+  +-------+--------+---------+-------------+
+  | 3     | ssbl   | enought | U-Boot      |
+  +-------+--------+---------+-------------+
+  | 4     | <any>  | <any>   | Rootfs      |
+  +-------+--------+---------+-------------+
+
+Add a 4th partition (Rootfs) marked bootable with a file extlinux.conf
+following the Generic Distribution feature (doc/README.distro for use).
+
+According the used card reader select the correct block device
+(for example /dev/sdx or /dev/mmcblk0).
+
+In the next example, it is /dev/mmcblk0
+
+For example: with gpt table with 128 entries
+
+a) remove previous formatting::
+
+     # sgdisk -o /dev/<SD card dev>
+
+b) create minimal image::
+
+    # sgdisk --resize-table=128 -a 1 \
+    -n 1:34:545		-c 1:fsbl1 \
+    -n 2:546:1057		-c 2:fsbl2 \
+    -n 3:1058:5153		-c 3:ssbl \
+    -n 4:5154:		    -c 4:rootfs \
+    -p /dev/<SD card dev>
+
+  With other partition for kernel one partition rootfs for kernel.
+
+c) copy the FSBL (2 times) and SSBL file on the correct partition.
+   in this example in partition 1 to 3
+
+   for basic boot mode : <SD card dev> = /dev/mmcblk0::
+
+    # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1
+    # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2
+    # dd if=u-boot.img of=/dev/mmcblk0p3 # Without CONFIG_SPL_LOAD_FIT
+      OR
+      dd if=u-boot.itb of=/dev/mmcblk0p3 # With CONFIG_SPL_LOAD_FIT=y
+
+   for trusted boot mode: ::
+
+    # dd if=tf-a.stm32 of=/dev/mmcblk0p1
+    # dd if=tf-a.stm32 of=/dev/mmcblk0p2
+    # dd if=u-boot.stm32 of=/dev/mmcblk0p3
+
+To boot from SD card, select BootPinMode = 1 0 1 and reset.
+
+Prepare eMMC
+------------
+
+You can use U-Boot to copy binary in eMMC.
+
+In the next example, you need to boot from SD card and the images
+(u-boot-spl.stm32, u-boot.img for systems without CONFIG_SPL_LOAD_FIT
+or u-boot.itb for systems with CONFIG_SPL_LOAD_FIT=y) are presents on
+SD card (mmc 0) in ext4 partition 4 (bootfs).
+
+To boot from SD card, select BootPinMode = 1 0 1 and reset.
+
+Then you update the eMMC with the next U-Boot command :
+
+a) prepare GPT on eMMC,
+   example with 2 partitions, bootfs and roots::
+
+    # setenv emmc_part "name=ssbl,size=2MiB;name=bootfs,type=linux,bootable,size=64MiB;name=rootfs,type=linux,size=512"
+    # gpt write mmc 1 ${emmc_part}
+
+b) copy SPL on eMMC on firts boot partition
+   (SPL max size is 256kB, with LBA 512, 0x200)::
+
+    # ext4load mmc 0:4 0xC0000000 u-boot-spl.stm32
+    # mmc dev 1
+    # mmc partconf 1 1 1 1
+    # mmc write ${fileaddr} 0 200
+    # mmc partconf 1 1 1 0
+
+c) copy U-Boot in first GPT partition of eMMC::
+
+    # ext4load mmc 0:4 0xC0000000 u-boot.img # Without CONFIG_SPL_LOAD_FIT
+      OR
+      ext4load mmc 0:4 0xC0000000 u-boot.itb # With CONFIG_SPL_LOAD_FIT=y
+    # mmc dev 1
+    # part start mmc 1 1 partstart
+    # mmc write ${fileaddr} ${partstart} ${filesize}
+
+To boot from eMMC, select BootPinMode = 0 1 0 and reset.
+
+MAC Address
+-----------
+
+Please read doc/README.enetaddr for the implementation guidelines for mac id
+usage. Basically, environment has precedence over board specific storage.
+
+For STMicroelectonics board, it is retrieved in STM32MP15x OTP :
+
+ - OTP_57[31:0] = MAC_ADDR[31:0]
+ - OTP_58[15:0] = MAC_ADDR[47:32]
+
+To program a MAC address on virgin OTP words above, you can use the fuse command
+on bank 0 to access to internal OTP and lock them:
+
+Prerequisite: check if a MAC address isn't yet programmed in OTP
+
+1) check OTP: their value must be equal to 0::
+
+    STM32MP> fuse sense 0 57 2
+    Sensing bank 0:
+    Word 0x00000039: 00000000 00000000
+
+2) check environment variable::
+
+    STM32MP> env print ethaddr
+    ## Error: "ethaddr" not defined
+
+3) check lock status of fuse 57 & 58 (at 0x39, 0=unlocked, 1=locked)::
+
+    STM32MP> fuse sense 0 0x10000039 2
+    Sensing bank 0:
+       Word 0x10000039: 00000000 00000000
+
+Example to set mac address "12:34:56:78:9a:bc"
+
+1) Write OTP::
+
+    STM32MP> fuse prog -y 0 57 0x78563412 0x0000bc9a
+
+2) Read OTP::
+
+    STM32MP> fuse sense 0 57 2
+    Sensing bank 0:
+    Word 0x00000039: 78563412 0000bc9a
+
+3) Lock OTP::
+
+    STM32MP> fuse prog 0 0x10000039 1 1
+
+    STM32MP> fuse sense 0 0x10000039 2
+    Sensing bank 0:
+       Word 0x10000039: 00000001 00000001
+
+4) next REBOOT, in the trace::
+
+    ### Setting environment from OTP MAC address = "12:34:56:78:9a:bc"
+
+5) check env update::
+
+    STM32MP> env print ethaddr
+    ethaddr=12:34:56:78:9a:bc
+
+.. warning:: This command can't be executed twice on the same board as
+             OTP are protected. It is already done for the board
+             provided by STMicroelectronics.
+
+Coprocessor firmware
+--------------------
+
+U-Boot can boot the coprocessor before the kernel (coprocessor early boot).
+
+a) Manuallly by using rproc commands (update the bootcmd)
+
+   Configurations::
+
+	# env set name_copro "rproc-m4-fw.elf"
+	# env set dev_copro 0
+	# env set loadaddr_copro 0xC1000000
+
+   Load binary from bootfs partition (number 4) on SD card (mmc 0)::
+
+	# ext4load mmc 0:4 ${loadaddr_copro} ${name_copro}
+
+   => ${filesize} variable is updated with the size of the loaded file.
+
+   Start M4 firmware with remote proc command::
+
+	# rproc init
+	# rproc load ${dev_copro} ${loadaddr_copro} ${filesize}
+	# rproc start ${dev_copro}"00270033
+
+b) Automatically by using FIT feature and generic DISTRO bootcmd
+
+   see examples in the board stm32mp1 directory: fit_copro_kernel_dtb.its
+
+   Generate FIT including kernel + device tree + M4 firmware with cfg with M4 boot::
+
+   $> mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb
+
+   Then using DISTRO configuration file: see extlinux.conf to select the correct
+   configuration:
+
+   - stm32mp157c-ev1-m4
+   - stm32mp157c-dk2-m4
+
+DFU support
+-----------
+
+The DFU is supported on ST board.
+
+The env variable dfu_alt_info is automatically build, and all
+the memory present on the ST boards are exported.
+
+The dfu mode is started by the command::
+
+  STM32MP> dfu 0
+
+On EV1 board, booting from SD card, without OP-TEE::
+
+  STM32MP> dfu 0 list
+  DFU alt settings list:
+  dev: RAM alt: 0 name: uImage layout: RAM_ADDR
+  dev: RAM alt: 1 name: devicetree.dtb layout: RAM_ADDR
+  dev: RAM alt: 2 name: uramdisk.image.gz layout: RAM_ADDR
+  dev: eMMC alt: 3 name: mmc0_fsbl1 layout: RAW_ADDR
+  dev: eMMC alt: 4 name: mmc0_fsbl2 layout: RAW_ADDR
+  dev: eMMC alt: 5 name: mmc0_ssbl layout: RAW_ADDR
+  dev: eMMC alt: 6 name: mmc0_bootfs layout: RAW_ADDR
+  dev: eMMC alt: 7 name: mmc0_vendorfs layout: RAW_ADDR
+  dev: eMMC alt: 8 name: mmc0_rootfs layout: RAW_ADDR
+  dev: eMMC alt: 9 name: mmc0_userfs layout: RAW_ADDR
+  dev: eMMC alt: 10 name: mmc1_boot1 layout: RAW_ADDR
+  dev: eMMC alt: 11 name: mmc1_boot2 layout: RAW_ADDR
+  dev: eMMC alt: 12 name: mmc1_ssbl layout: RAW_ADDR
+  dev: eMMC alt: 13 name: mmc1_bootfs layout: RAW_ADDR
+  dev: eMMC alt: 14 name: mmc1_vendorfs layout: RAW_ADDR
+  dev: eMMC alt: 15 name: mmc1_rootfs layout: RAW_ADDR
+  dev: eMMC alt: 16 name: mmc1_userfs layout: RAW_ADDR
+  dev: MTD alt: 17 name: nor0 layout: RAW_ADDR
+  dev: MTD alt: 18 name: nand0 layout: RAW_ADDR
+  dev: VIRT alt: 19 name: OTP layout: RAW_ADDR
+  dev: VIRT alt: 20 name: PMIC layout: RAW_ADDR
+
+All the supported device are exported for dfu-util tool::
+
+  $> dfu-util -l
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="PMIC", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="OTP", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nand0", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=17, name="nor0", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=16, name="mmc1_userfs", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="mmc1_rootfs", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=14, name="mmc1_vendorfs", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=13, name="mmc1_bootfs", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=12, name="mmc1_ssbl", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=11, name="mmc1_boot2", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=10, name="mmc1_boot1", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=9, name="mmc0_userfs", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=8, name="mmc0_rootfs", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=7, name="mmc0_vendorfs", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=6, name="mmc0_bootfs", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=5, name="mmc0_ssbl", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=4, name="mmc0_fsbl2", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=3, name="mmc0_fsbl1", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=2, name="uramdisk.image.gz", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=1, name="devicetree.dtb", serial="002700333338511934383330"
+  Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=0, name="uImage", serial="002700333338511934383330"
+
+You can update the boot device:
+
+- SD card (mmc0) ::
+
+  $> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1-trusted.stm32
+  $> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1-trusted.stm32
+  $> dfu-util -d 0483:5720 -a 5 -D u-boot-stm32mp157c-ev1-trusted.img
+  $> dfu-util -d 0483:5720 -a 6 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4
+  $> dfu-util -d 0483:5720 -a 7 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4
+  $> dfu-util -d 0483:5720 -a 8 -D st-image-weston-openstlinux-weston-stm32mp1.ext4
+  $> dfu-util -d 0483:5720 -a 9 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4
+
+- EMMC (mmc1)::
+
+  $> dfu-util -d 0483:5720 -a 10 -D tf-a-stm32mp157c-ev1-trusted.stm32
+  $> dfu-util -d 0483:5720 -a 11 -D tf-a-stm32mp157c-ev1-trusted.stm32
+  $> dfu-util -d 0483:5720 -a 12 -D u-boot-stm32mp157c-ev1-trusted.img
+  $> dfu-util -d 0483:5720 -a 13 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4
+  $> dfu-util -d 0483:5720 -a 14 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4
+  $> dfu-util -d 0483:5720 -a 15 -D st-image-weston-openstlinux-weston-stm32mp1.ext4
+  $> dfu-util -d 0483:5720 -a 16 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4
+
+- you can also dump the OTP and the PMIC NVM with::
+
+  $> dfu-util -d 0483:5720 -a 19 -U otp.bin
+  $> dfu-util -d 0483:5720 -a 20 -U pmic.bin
+
+
+When the board is booting for nor0 or nand0,
+only the MTD partition on the boot devices are available, for example:
+
+- NOR (nor0 = alt 20) & NAND (nand0 = alt 26) ::
+
+  $> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1-trusted.stm32
+  $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1-trusted.stm32
+  $> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img
+  $> dfu-util -d 0483:5720 -a 27 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi
+
+- NAND (nand0 = alt 21)::
+
+  $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1-trusted.stm32
+  $> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img
+  $> dfu-util -d 0483:5720 -a 24 -D u-boot-stm32mp157c-ev1-trusted.img
+  $> dfu-util -d 0483:5720 -a 25 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi
diff --git a/roms/u-boot/doc/board/tbs/index.rst b/roms/u-boot/doc/board/tbs/index.rst
new file mode 100644
index 000000000..b677bc624
--- /dev/null
+++ b/roms/u-boot/doc/board/tbs/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+TBS
+===
+
+.. toctree::
+   :maxdepth: 2
+
+   tbs2910
diff --git a/roms/u-boot/doc/board/tbs/tbs2910.rst b/roms/u-boot/doc/board/tbs/tbs2910.rst
new file mode 100644
index 000000000..e97f2b6e6
--- /dev/null
+++ b/roms/u-boot/doc/board/tbs/tbs2910.rst
@@ -0,0 +1,191 @@
+TBS2910 Matrix ARM miniPC
+=========================
+
+Building
+--------
+To build u-boot for the TBS2910 Matrix ARM miniPC, you can use the following
+procedure:
+
+First add the ARM toolchain to your PATH
+
+Then setup the ARCH and cross compilation environment variables.
+
+When this is done you can then build u-boot for the TBS2910 Matrix ARM miniPC
+with the following commands:
+
+.. code-block:: none
+
+   make mrproper
+   make tbs2910_defconfig
+   make
+
+Once the build is complete, you can find the resulting image as u-boot.imx in
+the current directory.
+
+UART
+----
+The UART voltage is at 3.3V and its settings are 115200bps 8N1
+
+BOOT/UPDATE boot switch:
+------------------------
+The BOOT/UPDATE switch (SW11) is connected to the BOOT_MODE0 and
+BOOT_MODE1 SoC pins. It has "BOOT" and "UPDATE" markings both on
+the PCB and on the plastic case.
+
+When set to the "UPDATE" position, the SoC will use the "Boot From Fuses"
+configuration, and since BT_FUSE_SEL is 0, this makes the SOC jump to serial
+downloader.
+
+When set in the "BOOT" position, the SoC will use the "Internal boot"
+configuration, and since BT_FUSE_SEL is 0, it will then use the GPIO pins
+for the boot configuration.
+
+SW6 binary DIP switch array on the PCB revision 2.1:
+----------------------------------------------------
+On that PCB revision, SW6 has 8 positions.
+
+Switching a position to ON sets the corresponding
+register to 1.
+
+See the following table for a correspondence between the switch positions and
+registers:
+
+===============    ============
+Switch position    Register
+===============    ============
+1                  BOOT_CFG2[3]
+2                  BOOT_CFG2[4]
+3                  BOOT_CFG2[5]
+4                  BOOT_CFG2[6]
+5                  BOOT_CFG1[4]
+6                  BOOT_CFG1[5]
+7                  BOOT_CFG1[6]
+8                  BOOT_CFG1[7]
+===============    ============
+
+For example:
+
+  - To boot from the eMMC: 1:ON , 2:ON, 3:ON, 4:OFF, 5:OFF, 6:ON, 7:ON, 8:OFF
+  - To boot from the microSD slot: 1: ON, 2: OFF, 3: OFF, 4: OFF, 5:OFF, 6:OFF,
+    7:ON, 8:OFF
+  - To boot from the SD slot: 1: OFF, 2: ON, 3: OFF, 4: OFF, 5:OFF, 6:OFF, 7:ON,
+    8:OFF
+  - To boot from SATA: 1: OFF, 2: OFF, 3: OFF, 4: OFF, 5:OFF, 6:ON, 7:OFF, 8:OFF
+
+You can refer to the BOOT_CFG registers in the I.MX6Q reference manual for
+additional details.
+
+SW6 binary DIP switch array on the PCB revision 2.3:
+----------------------------------------------------
+On that PCB revision, SW6 has only 4 positions.
+
+Switching a position to ON sets the corresponding
+register to 1.
+
+See the following table for a correspondence between the switch positions and
+registers:
+
+===============    ============
+Switch position    Register
+===============    ============
+1                  BOOT_CFG2[3]
+2                  BOOT_CFG2[4]
+3                  BOOT_CFG2[5]
+4                  BOOT_CFG1[5]
+===============    ============
+
+For example:
+
+- To boot from the eMMC: 1:ON, 2:ON, 3:ON, 4:ON
+- To boot from the microSD slot: 1:ON, 2:OFF, 3:OFF, 4:OFF
+- To boot from the SD slot: 1:OFF, 2:ON, 3:OFF, 4:OFF
+
+You can refer to the BOOT_CFG registers in the I.MX6Q reference manual for
+additional details.
+
+Loading u-boot from USB:
+------------------------
+If you need to load u-boot from USB, you can use the following instructions:
+
+First build imx_usb_loader, as we will need it to load u-boot from USB. This
+can be done with the following commands:
+
+.. code-block:: none
+
+   git clone git://github.com/boundarydevices/imx_usb_loader.git
+   cd imx_usb_loader
+   make
+
+This will create the resulting imx_usb binary.
+
+When this is done, you can copy the u-boot.imx image that you built earlier
+in in the imx_usb_loader directory.
+
+You will then need to power off the TBS2910 Matrix ARM miniPC and make sure that
+the boot switch is set to "UPDATE"
+
+Once this is done you can connect an USB cable between the computer that will
+run imx_usb and the TBS2910 Matrix ARM miniPC.
+
+If you also need to access the u-boot console, you will also need to connect an
+UART cable between the computer running imx_usb and the TBS2910 Matrix ARM
+miniPC.
+
+Once everything is connected you can finally power on the TBS2910 Matrix ARM
+miniPC. The SoC will then jump to the serial download and wait for you.
+
+Finlay, you can load u-boot through USB with with the following command:
+
+.. code-block:: none
+
+   sudo ./imx_usb -v u-boot.imx
+
+The u-boot boot messages will then appear in the serial console.
+
+Install u-boot on the eMMC:
+---------------------------
+To install u-boot on the eMMC, you first need to boot the TBS2910 Matrix ARM
+miniPC.
+
+Once booted, you can flash u-boot.imx to mmcblk0boot0 with the
+following commands:
+
+.. code-block:: none
+
+   sudo echo 0 >/sys/block/mmcblk0boot0/force_ro
+   sudo dd if=u-boot.imx of=/dev/mmcblk0boot0 bs=1k seek=1; sync
+
+Note that the eMMC card node may vary, so adjust this as needed.
+
+Once the new u-boot version is installed, to boot on it you then need to power
+off the TBS2910 Matrix ARM miniPC.
+
+Once it is off, you need make sure that the boot switch is set to "BOOT" and
+that the SW6 switch is set to boot on the eMMC as described in the previous
+sections.
+
+If you also need to access the u-boot console, you will also need to connect an
+UART cable between the computer running imx_usb and the TBS2910 Matrix ARM
+miniPC.
+
+You can then power up the TBS2910 Matrix ARM miniPC and U-Boot messages will
+appear in the serial console.
+
+Booting a distribution:
+-----------------------
+When booting on the TBS2910 Matrix ARM miniPC, by default U-Boot will first try
+to boot from hardcoded offsets from the start of the eMMC. This is for
+compatibility with the stock GNU/Linux distribution.
+
+If that fails it will then try to boot from several interfaces using
+'distro_bootcmd': It will first try to boot from the microSD slot, then the
+SD slot, then the internal eMMC, then the SATA interface and finally the USB
+interface. For more information on how to configure your distribution to boot,
+see 'README.distro'.
+
+Links:
+------
+  - https://www.tbsdtv.com/download/document/tbs2910/TBS2910-Matrix-ARM-mini-PC-SCH_rev2.1.pdf
+    - The schematics for the revision 2.1 of the TBS2910 Matrix ARM miniPC.
+  - https://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf - The
+    SoC reference manual for additional details on the BOOT_CFG registers.
diff --git a/roms/u-boot/doc/board/toradex/apalix-imx8.rst b/roms/u-boot/doc/board/toradex/apalix-imx8.rst
new file mode 100644
index 000000000..29593faf1
--- /dev/null
+++ b/roms/u-boot/doc/board/toradex/apalix-imx8.rst
@@ -0,0 +1,82 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Apalis iMX8QM V1.0B Module
+==========================
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Load U-Boot binary using uuu
+- Flash U-Boot binary into the eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
+    $ cd imx-atf/
+    $ make PLAT=imx8qm bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+    $ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-
+      bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true
+    $ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin
+    $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+    $ chmod +x firmware-imx-8.0.bin
+    $ ./firmware-imx-8.0.bin
+
+Copy the following binaries to the U-Boot folder:
+
+.. code-block:: bash
+
+    $ cp imx-atf/build/imx8qm/release/bl31.bin .
+    $ cp u-boot/u-boot.bin .
+
+Copy the following firmware to the U-Boot folder:
+
+.. code-block:: bash
+
+    $ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
+
+Build U-Boot
+------------
+.. code-block:: bash
+
+    $ make apalis-imx8_defconfig
+    $ make u-boot-dtb.imx
+
+Load the U-Boot Binary Using UUU
+--------------------------------
+
+Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``:
+
+https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
+
+Put the module into USB recovery aka serial downloader mode, connect USB device
+to your host and execute uuu:
+
+.. code-block:: bash
+
+    sudo ./uuu u-boot/u-boot-dtb.imx
+
+Flash the U-Boot Binary into the eMMC
+-------------------------------------
+
+Burn the ``u-boot-dtb.imx`` binary to the primary eMMC hardware boot area
+partition and boot:
+
+.. code-block:: bash
+
+    load mmc 1:1 $loadaddr u-boot-dtb.imx
+    setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+    mmc dev 0 1
+    mmc write ${loadaddr} 0x0 ${blkcnt}
diff --git a/roms/u-boot/doc/board/toradex/apalix-imx8x.rst b/roms/u-boot/doc/board/toradex/apalix-imx8x.rst
new file mode 100644
index 000000000..e62578b15
--- /dev/null
+++ b/roms/u-boot/doc/board/toradex/apalix-imx8x.rst
@@ -0,0 +1,77 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Apalis iMX8X V1.1A Module (SoC NXP i.MX8QXP RevB)
+=================================================
+
+Quick Start
+-----------
+
+- Get and Build the ARM trusted firmware
+- Get System Controller firmware
+- Get SECO container
+- Build U-Boot
+- Load U-Boot binary using uuu
+- Flash U-Boot binary into the eMMC
+- Boot
+
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+.. code-block:: bash
+
+    $ cd $(builddir)
+    $ git clone -b toradex_imx_5.4.70_2.3.0 http://git.toradex.com/cgit/imx-atf.git
+    $ make PLAT=imx8qx bl31 -C imx-atf
+    $ cp imx-atf/build/imx8qx/release/bl31.bin $(builddir)
+
+Get System Controller firmware
+---------------------------------------
+
+.. code-block:: bash
+
+    $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/raw/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-apalis-scfw-tcm.bin
+
+Get SECO container
+---------------------------------------
+
+.. code-block:: bash
+
+    $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.7.4.bin
+    $ sh imx-seco-3.7.4.bin
+    $ cp imx-seco-3.7.4/firmware/seco/mx8qxb0-ahab-container.img $(builddir)/mx8qx-ahab-container.img
+
+Build U-Boot
+------------
+.. code-block:: bash
+
+    $ make apalis-imx8x_defconfig
+    $ make u-boot-dtb.imx
+
+Load the U-Boot Binary Using UUU
+--------------------------------
+
+Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``:
+
+https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
+
+Put the module into USB recovery aka serial downloader mode, connect USB device
+to your host and execute uuu:
+
+.. code-block:: bash
+
+    sudo ./uuu $(builddir)/u-boot-dtb.imx
+
+Flash the U-Boot Binary into the eMMC
+-------------------------------------
+
+Burn the ``u-boot-dtb.imx`` binary to the primary eMMC hardware boot area
+partition and boot:
+
+.. code-block:: bash
+
+    load mmc 1:1 $loadaddr u-boot-dtb.imx
+    setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+    mmc dev 0 1
+    mmc write ${loadaddr} 0x0 ${blkcnt}
diff --git a/roms/u-boot/doc/board/toradex/colibri-imx8x.rst b/roms/u-boot/doc/board/toradex/colibri-imx8x.rst
new file mode 100644
index 000000000..616f40ae0
--- /dev/null
+++ b/roms/u-boot/doc/board/toradex/colibri-imx8x.rst
@@ -0,0 +1,82 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Colibri iMX8QXP V1.0B Module
+============================
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Load U-Boot binary using uuu
+- Flash U-Boot binary into the eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+.. code-block:: bash
+
+    $ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
+    $ cd imx-atf/
+    $ make PLAT=imx8qxp bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+.. code-block:: bash
+
+    $ wget https://github.com/toradex/meta-fsl-bsp-release/blob/
+           toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-
+           bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
+    $ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin
+    $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+    $ chmod +x firmware-imx-8.0.bin
+    $ ./firmware-imx-8.0.bin
+
+Copy the following binaries to the U-Boot folder:
+
+.. code-block:: bash
+
+    $ cp imx-atf/build/imx8qxp/release/bl31.bin .
+    $ cp u-boot/u-boot.bin .
+
+Copy the following firmware to the U-Boot folder:
+
+.. code-block:: bash
+
+    $ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ make colibri-imx8x_defconfig
+   $ make u-boot-dtb.imx
+
+Load the U-Boot Binary Using UUU
+--------------------------------
+
+Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``:
+
+https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
+
+Put the module into USB recovery aka serial downloader mode, connect USB device
+to your host and execute ``uuu``:
+
+.. code-block:: bash
+
+    sudo ./uuu u-boot/u-boot-dtb.imx
+
+Flash the U-Boot Binary into the eMMC
+-------------------------------------
+
+Burn the ``u-boot-dtb.imx`` binary to the primary eMMC hardware boot area partition:
+
+.. code-block:: bash
+
+    load mmc 1:1 $loadaddr u-boot-dtb.imx
+    setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+    mmc dev 0 1
+    mmc write ${loadaddr} 0x0 ${blkcnt}
diff --git a/roms/u-boot/doc/board/toradex/colibri_imx7.rst b/roms/u-boot/doc/board/toradex/colibri_imx7.rst
new file mode 100644
index 000000000..a30e72137
--- /dev/null
+++ b/roms/u-boot/doc/board/toradex/colibri_imx7.rst
@@ -0,0 +1,126 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Colibri iMX7
+============
+
+Quick Start
+-----------
+
+- Build U-Boot
+- NAND IMX image adjustments before flashing
+- Flashing manually U-Boot to eMMC
+- Flashing manually U-Boot to NAND
+- Using ``update_uboot`` script
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=arm-linux-gnueabi-
+    $ make colibri_imx7_emmc_defconfig # For NAND: colibri_imx7_defconfig
+    $ make
+
+After build succeeds, you will obtain final ``u-boot-dtb.imx`` IMX specific
+image, ready for flashing (but check next section for additional
+adjustments).
+
+Final IMX program image includes (section ``6.6.7`` from `IMX7DRM
+<https://www.nxp.com/webapp/Download?colCode=IMX7DRM>`_):
+
+* **Image vector table** (IVT) for BootROM
+* **Boot data** -indicates the program image location, program image size
+  in bytes, and the plugin flag.
+* **Device configuration data**
+* **User image**: U-Boot image (``u-boot-dtb.bin``)
+
+
+IMX image adjustments prior to flashing
+---------------------------------------
+
+1. U-Boot for both Colibri iMX7 NAND and eMMC versions
+is built with HABv4 support (`AN4581.pdf
+<https://www.nxp.com/docs/en/application-note/AN4581.pdf>`_)
+enabled by default, which requires to generate a proper
+Command Sequence File (CSF) by srktool from NXP (not included in the
+U-Boot tree, check additional details in introduction_habv4.txt)
+and concatenate it to the final ``u-boot-dtb.imx``.
+
+2. In case if you don't want to generate a proper ``CSF`` (for any reason),
+you still need to pad the IMX image so i has the same size as specified in
+in **Boot Data** section of IMX image.
+To obtain this value, run:
+
+.. code-block:: bash
+
+    $ od -X -N 0x30 u-boot-dtb.imx
+    0000000    402000d1 87800000 00000000 877ff42c
+    0000020    877ff420 877ff400 878a5000 00000000
+                        ^^^^^^^^
+    0000040    877ff000 000a8060 00000000 40b401d2
+               ^^^^^^^^ ^^^^^^^^
+
+Where:
+
+* ``877ff400`` - IVT self address
+* ``877ff000`` - Program image address
+* ``000a8060`` - Program image size
+
+To calculate the padding:
+
+* IVT offset = ``0x877ff400`` - ``0x877ff000`` = ``0x400``
+* Program image size = ``0xa8060`` - ``0x400`` = ``0xa7c60``
+
+and then pad the image:
+
+.. code-block:: bash
+
+    $ objcopy -I binary -O binary --pad-to 0xa7c60 --gap-fill=0x00 \
+        u-boot-dtb.imx u-boot-dtb.imx.zero-padded
+
+3. Also, according to requirement from ``6.6.7.1``, the final image
+should have ``0x400`` offset for initial IVT table.
+
+For eMMC setup we handle this by flashing it to ``0x400``, howewer
+for NAND setup we adjust the image prior to flashing, adding padding in the
+beginning of the image.
+
+.. code-block:: bash
+
+    $ dd if=u-boot-dtb.imx.zero-padded of=u-boot-dtb.imx.ready bs=1024 seek=1
+
+Flash U-Boot IMX image to eMMC
+------------------------------
+
+Flash the ``u-boot-dtb.imx.zero-padded`` binary to the primary eMMC hardware
+boot area partition:
+
+.. code-block:: bash
+
+
+    => load mmc 1:1 $loadaddr u-boot-dtb.imx.zero-padded
+    => setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+    => mmc dev 0 1
+    => mmc write ${loadaddr} 0x2 ${blkcnt}
+
+Flash U-Boot IMX image to NAND
+------------------------------
+
+.. code-block:: bash
+
+    => load mmc 1:1 $loadaddr u-boot-dtb.imx.ready
+    => nand erase.part u-boot1
+    => nand write ${loadaddr} u-boot1 ${filesize}
+    => nand erase.part u-boot2
+    => nand write ${loadaddr} u-boot2 ${filesize}
+
+Using update_uboot script
+-------------------------
+
+You can also usb U-Boot env update_uboot script,
+which wraps all eMMC/NAND specific command invocation:
+
+.. code-block:: bash
+
+    => load mmc 1:1 $loadaddr u-boot-dtb.imx.ready
+    => run update_uboot
diff --git a/roms/u-boot/doc/board/toradex/index.rst b/roms/u-boot/doc/board/toradex/index.rst
new file mode 100644
index 000000000..abba648f8
--- /dev/null
+++ b/roms/u-boot/doc/board/toradex/index.rst
@@ -0,0 +1,13 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Toradex
+=======
+
+.. toctree::
+   :maxdepth: 2
+
+   apalix-imx8
+   apalix-imx8x
+   colibri_imx7
+   colibri-imx8x
+   verdin-imx8mm
diff --git a/roms/u-boot/doc/board/toradex/verdin-imx8mm.rst b/roms/u-boot/doc/board/toradex/verdin-imx8mm.rst
new file mode 100644
index 000000000..b9f7dc39c
--- /dev/null
+++ b/roms/u-boot/doc/board/toradex/verdin-imx8mm.rst
@@ -0,0 +1,98 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Verdin iMX8M Mini Module
+========================
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get the DDR firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware (Trusted Firmware A)
+-----------------------------------------------------------
+
+.. code-block:: bash
+
+    $ echo "Downloading and building TF-A..."
+    $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+    $ cd trusted-firmware-a
+
+Then build ATF (TF-A):
+
+.. code-block:: bash
+
+    $ make PLAT=imx8mm IMX_BOOT_UART_BASE=0x30860000 bl31
+    $ cp build/imx8mm/release/bl31.bin ../
+
+Get the DDR Firmware
+--------------------
+
+.. code-block:: bash
+
+    $ cd ..
+    $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.4.1.bin
+    $ chmod +x firmware-imx-8.4.1.bin
+    $ ./firmware-imx-8.4.1.bin
+    $ cp firmware-imx-8.4.1/firmware/ddr/synopsys/lpddr4*.bin ./
+
+Build U-Boot
+------------
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=aarch64-linux-gnu-
+    $ export ATF_LOAD_ADDR=0x920000
+    $ make verdin-imx8mm_defconfig
+    $ make flash.bin
+
+Flash to eMMC
+-------------
+
+.. code-block:: bash
+
+    > tftpboot ${loadaddr} flash.bin
+    > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+    > mmc dev 0 1 && mmc write ${loadaddr} 0x2 ${blkcnt}
+
+As a convenience, instead of the last two commands one may also use the update
+U-Boot wrapper:
+
+.. code-block:: bash
+
+    > run update_uboot
+
+Boot
+----
+
+ATF, U-Boot proper and u-boot.dtb images are packed into FIT image,
+which is loaded and parsed by SPL.
+
+Boot sequence is:
+
+* SPL ---> ATF (TF-A) ---> U-Boot proper
+
+Output:
+
+.. code-block:: bash
+
+    U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
+    Normal Boot
+    Trying to boot from MMC1
+
+    U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
+
+    CPU:   Freescale i.MX8MMQ rev1.0 at 0 MHz
+    Reset cause: POR
+    DRAM:  2 GiB
+    MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
+    Loading Environment from MMC... OK
+    In:    serial
+    Out:   serial
+    Err:   serial
+    Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial:
+    Net:   eth0: ethernet@30be0000
+    Hit any key to stop autoboot:  0
+    Verdin iMX8MM #
diff --git a/roms/u-boot/doc/board/xen/index.rst b/roms/u-boot/doc/board/xen/index.rst
new file mode 100644
index 000000000..e58fe9e35
--- /dev/null
+++ b/roms/u-boot/doc/board/xen/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+XenGuestARM64
+=============
+
+.. toctree::
+   :maxdepth: 2
+
+   xenguest_arm64
diff --git a/roms/u-boot/doc/board/xen/xenguest_arm64.rst b/roms/u-boot/doc/board/xen/xenguest_arm64.rst
new file mode 100644
index 000000000..1327f88f9
--- /dev/null
+++ b/roms/u-boot/doc/board/xen/xenguest_arm64.rst
@@ -0,0 +1,81 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Xen guest ARM64 board
+=====================
+
+This board specification
+------------------------
+
+This board is to be run as a virtual Xen [1] guest with U-boot as its primary
+bootloader. Xen is a type 1 hypervisor that allows multiple operating systems
+to run simultaneously on a single physical server. Xen is capable of running
+virtual machines in both full virtualization and para-virtualization (PV)
+modes. Xen runs virtual machines, which are called “domains”.
+
+Paravirtualized drivers are a special type of device drivers that are used in
+a guest system in the Xen domain and perform I/O operations using a special
+interface provided by the virtualization system and the host system.
+
+Xen support for U-boot is implemented by introducing a new Xen guest ARM64
+board and porting essential drivers from MiniOS [3] as well as some of the work
+previously done by NXP [4]:
+
+- PV block device frontend driver with XenStore based device enumeration and
+  UCLASS_PVBLOCK class;
+- PV serial console device frontend driver;
+- Xen hypervisor support with minimal set of the essential headers adapted from
+  the Linux kernel;
+- Xen grant table support;
+- Xen event channel support in polling mode;
+- XenBus support;
+- dynamic RAM size as defined in the device tree instead of the statically
+  defined values;
+- position-independent pre-relocation code is used as we cannot statically
+  define any start addresses at compile time which is up to Xen to choose at
+  run-time;
+- new defconfig introduced: xenguest_arm64_defconfig.
+
+
+Board limitations
+-----------------
+
+1. U-boot runs without MMU enabled at the early stages.
+   According to Xen on ARM ABI (xen/include/public/arch-arm.h): all memory
+   which is shared with other entities in the system (including the hypervisor
+   and other guests) must reside in memory which is mapped as Normal Inner
+   Write-Back Outer Write-Back Inner-Shareable.
+   Thus, page attributes must be equally set for all the entities working with
+   that page.
+   Before MMU is set up the data cache is turned off and pages are seen by the
+   vCPU and Xen in different ways - cacheable by Xen and non-cacheable by vCPU.
+   So it means that manual data cache maintenance is required at the early
+   stages.
+
+2. No serial console until MMU is up.
+   Because data cache maintenance is required until the MMU setup the
+   early/debug serial console is not implemented. Therefore, we do not have
+   usual prints like U-boot’s banner etc. until the serial driver is
+   initialized.
+
+3. Single RAM bank supported.
+   If a Xen guest is given much memory it is possible that Xen allocates two
+   memory banks for it. The first one is allocated under 4GB address space and
+   in some cases may represent the whole guest’s memory. It is assumed that
+   U-boot most likely won’t require high memory bank for its work andlaunching
+   OS, so it is enough to take the first one.
+
+
+Board default configuration
+---------------------------
+
+One can select the configuration as follows:
+
+ - make xenguest_arm64_defconfig
+
+[1] - https://xenproject.org/
+
+[2] - https://wiki.xenproject.org/wiki/Paravirtualization_(PV)
+
+[3] - https://wiki.xenproject.org/wiki/Mini-OS
+
+[4] - https://source.codeaurora.org/external/imx/uboot-imx/tree/?h=imx_v2018.03_4.14.98_2.0.0_ga
diff --git a/roms/u-boot/doc/board/xilinx/index.rst b/roms/u-boot/doc/board/xilinx/index.rst
new file mode 100644
index 000000000..2e31fe3f3
--- /dev/null
+++ b/roms/u-boot/doc/board/xilinx/index.rst
@@ -0,0 +1,12 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Xilinx
+======
+
+.. toctree::
+   :maxdepth: 2
+
+   xilinx
+   zynq
+   zynqmp
+   zynqmp-r5
diff --git a/roms/u-boot/doc/board/xilinx/xilinx.rst b/roms/u-boot/doc/board/xilinx/xilinx.rst
new file mode 100644
index 000000000..8c9afb482
--- /dev/null
+++ b/roms/u-boot/doc/board/xilinx/xilinx.rst
@@ -0,0 +1,48 @@
+.. SPDX-License-Identifier: GPL-2.0+
+..  (C) Copyright 2019 Xilinx, Inc.
+
+U-Boot device tree bindings
+----------------------------
+
+All the device tree bindings used in U-Boot are specified in Linux
+kernel. Please refer dt bindings from below specified paths in Linux
+kernel.
+
+* ata
+	- Documentation/devicetree/bindings/ata/ahci-ceva.txt
+* clock
+	- Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
+* firmware
+	- Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+* fpga
+	- Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
+* gpio
+	- Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
+	- Documentation/devicetree/bindings/gpio/gpio-zynq.txt
+* i2c
+	- Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
+	- Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
+* mmc
+	- Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
+* net
+	- Documentation/devicetree/bindings/net/macb.txt
+	- Documentation/devicetree/bindings/net/xilinx_axienet.txt
+	- Documentation/devicetree/bindings/net/xilinx_emaclite.txt
+* nvmem
+	- Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
+* power
+	- Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
+* serial
+	- Documentation/devicetree/bindings/serial/cdns,uart.txt
+	- Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt
+* spi
+	- Documentation/devicetree/bindings/spi/spi-cadence.txt
+	- Documentation/devicetree/bindings/spi/spi-xilinx.txt
+	- Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
+	- Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
+* usb
+	- Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
+	- Documentation/devicetree/bindings/usb/dwc3.txt
+	- Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
+* wdt
+	- Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
diff --git a/roms/u-boot/doc/board/xilinx/zynq.rst b/roms/u-boot/doc/board/xilinx/zynq.rst
new file mode 100644
index 000000000..438912fe4
--- /dev/null
+++ b/roms/u-boot/doc/board/xilinx/zynq.rst
@@ -0,0 +1,110 @@
+.. SPDX-License-Identifier: GPL-2.0+
+..  (C) Copyright 2013 Xilinx, Inc.
+
+ZYNQ
+====
+
+About this
+----------
+
+This document describes the information about Xilinx Zynq U-Boot -
+like supported boards, ML status and TODO list.
+
+Zynq boards
+-----------
+
+Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
+differentiation, integration, and flexibility through hardware, software,
+and I/O programmability.
+
+* zc702 (single qspi, gem0, mmc) [1]
+* zc706 (dual parallel qspi, gem0, mmc) [2]
+* zed (single qspi, gem0, mmc) [3]
+* microzed (single qspi, gem0, mmc) [4]
+* zc770
+     - zc770-xm010 (single qspi, gem0, mmc)
+     - zc770-xm011 (8 or 16 bit nand)
+     - zc770-xm012 (nor)
+     - zc770-xm013 (dual parallel qspi, gem1)
+
+Building
+--------
+
+configure and build for zc702 board::
+
+   $ export DEVICE_TREE=zynq-zc702
+   $ make xilinx_zynq_virt_defconfig
+   $ make
+
+Bootmode
+--------
+
+Zynq has a facility to read the bootmode from the slcr bootmode register
+once user is setting through jumpers on the board - see page no:1546 on [5]
+
+All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins
+on [5].
+
+board_late_init() will read the bootmode values using slcr bootmode register
+at runtime and assign the modeboot variable to specific bootmode string which
+is intern used in autoboot.
+
+SLCR bootmode register Bit[3:0] values
+
+.. code-block:: c
+
+   #define ZYNQ_BM_NOR		0x02
+   #define ZYNQ_BM_SD		0x05
+   #define ZYNQ_BM_JTAG		0x0
+
+"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot"
+bootmode strings at runtime.
+
+Flashing
+--------
+
+SD Card
+^^^^^^^
+
+To write an image that boots from a SD card first create a FAT32 partition
+and a FAT32 filesystem on the SD card::
+
+        sudo fdisk /dev/sdx
+        sudo mkfs.vfat -F 32 /dev/sdx1
+
+Mount the SD card and copy the SPL and U-Boot to the root directory of the
+SD card::
+
+        sudo mount -t vfat /dev/sdx1 /mnt
+        sudo cp spl/boot.bin /mnt
+        sudo cp u-boot.img /mnt
+
+Mainline status
+---------------
+
+- Added basic board configurations support.
+- Added zynq u-boot bsp code - arch/arm/mach-zynq
+- Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013
+- Added zynq drivers:
+
+  :serial: drivers/serial/serial_zynq.c
+  :net: drivers/net/zynq_gem.c
+  :mmc: drivers/mmc/zynq_sdhci.c
+  :spi: drivers/spi/zynq_spi.c
+  :qspi: drivers/spi/zynq_qspi.c
+  :i2c: drivers/i2c/zynq_i2c.c
+  :nand: drivers/mtd/nand/raw/zynq_nand.c
+
+- Done proper cleanups on board configurations
+- Added basic FDT support for zynq boards
+- d-cache support for zynq_gem.c
+
+* [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
+* [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
+* [3] http://zedboard.org/product/zedboard
+* [4] http://zedboard.org/product/microzed
+* [5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+
+
+.. Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+.. Sun Dec 15 14:52:41 IST 2013
diff --git a/roms/u-boot/doc/board/xilinx/zynqmp-r5.rst b/roms/u-boot/doc/board/xilinx/zynqmp-r5.rst
new file mode 100644
index 000000000..2cd368b03
--- /dev/null
+++ b/roms/u-boot/doc/board/xilinx/zynqmp-r5.rst
@@ -0,0 +1,137 @@
+.. SPDX-License-Identifier: GPL-2.0
+..  (C) Copyright 2020 Xilinx, Inc.
+
+ZYNQMP-R5
+=========
+
+About this
+----------
+
+This document describes the information about Xilinx Zynq UltraScale+ MPSOC
+U-Boot Cortex R5 support.
+
+ZynqMP R5 boards
+----------------
+
+* zynqmp-r5 - U-Boot running on RPU Cortex-R5
+
+Building
+--------
+
+configure and build armv7 toolchain::
+
+   $ make xilinx_zynqmp_r5_defconfig
+   $ make
+
+Notes
+^^^^^
+
+Output fragment is u-boot.
+
+Loading
+-------
+
+ZynqMP R5 U-Boot was created for supporting loading OS on RPU. There are two
+ways how to start U-Boot on R5.
+
+Bootgen
+^^^^^^^
+
+The first way is to use Xilinx FSBL (First stage
+bootloader) to load u-boot and start it. The following bif can be used for boot
+image generation via Xilinx bootgen utility::
+
+
+  the_ROM_image:
+  {
+  	[bootloader,destination_cpu=r5-0] fsbl_rpu.elf
+  	[destination_cpu=r5-0]u-boot.elf
+  }
+
+Bootgen command for building boot.bin::
+
+  bootgen -image <bif>.bif -r -w -o i boot.bin
+
+
+U-Boot cpu command
+^^^^^^^^^^^^^^^^^^
+
+The second way to load U-Boot to Cortex R5 is from U-Boot running on A53 as is
+visible from the following log::
+
+  U-Boot SPL 2020.10-rc4-00090-g801b3d5c5757 (Sep 15 2020 - 14:07:24 +0200)
+  PMUFW:	v1.1
+  Loading new PMUFW cfg obj (2024 bytes)
+  EL Level:	EL3
+  Multiboot:	0
+  Trying to boot from MMC2
+  spl: could not initialize mmc. error: -19
+  Trying to boot from MMC1
+  spl_load_image_fat_os: error reading image u-boot.bin, err - -2
+  NOTICE:  ATF running on XCZU7EG/EV/silicon v4/RTL5.1 at 0xfffea000
+  NOTICE:  BL31: v2.2(release):v2.2-614-ged9dc512fb9c
+  NOTICE:  BL31: Built : 09:32:09, Mar 13 2020
+
+
+  U-Boot 2020.10-rc4-00090-g801b3d5c5757 (Sep 15 2020 - 14:07:24 +0200)
+
+  Model: ZynqMP ZCU104 RevC
+  Board: Xilinx ZynqMP
+  DRAM:  2 GiB
+  PMUFW:	v1.1
+  EL Level:	EL2
+  Chip ID:	zu7e
+  WDT:   Started with servicing (60s timeout)
+  NAND:  0 MiB
+  MMC:   mmc@ff170000: 0
+  Loading Environment from FAT... *** Warning - bad CRC, using default environment
+
+  In:    serial
+  Out:   serial
+  Err:   serial
+  Bootmode: LVL_SHFT_SD_MODE1
+  Reset reason:	SOFT
+  Net:
+  ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id
+  eth0: ethernet@ff0e0000
+  Hit any key to stop autoboot:  0
+  ZynqMP> setenv autoload no
+  ZynqMP> dhcp
+  BOOTP broadcast 1
+  DHCP client bound to address 192.168.0.167 (8 ms)
+  ZynqMP> tftpboot 20000000 192.168.0.105:u-boot-r5-2.elf
+  Using ethernet@ff0e0000 device
+  TFTP from server 192.168.0.105; our IP address is 192.168.0.167
+  Filename 'u-boot-r5-2.elf'.
+  Load address: 0x20000000
+  Loading: #################################################################
+  	 #################################################################
+  	 #################################################################
+  	 #################################################################
+  	 #################################################################
+  	 #################################################################
+  	 ################
+  	 376 KiB/s
+  done
+  Bytes transferred = 2075464 (1fab48 hex)
+  ZynqMP> setenv autostart no
+  ZynqMP> bootelf -p 20000000
+  ZynqMP> cpu 4 release 10000000 lockstep
+  Using TCM jump trampoline for address 0x10000000
+  R5 lockstep mode
+  ZynqMP>
+
+Then on second uart you can see U-Boot up and running on R5::
+
+  U-Boot 2020.10-rc4-00071-g7045622cc9ba (Sep 16 2020 - 13:38:53 +0200)
+
+  Model: Xilinx ZynqMP R5
+  DRAM:  512 MiB
+  MMC:
+  In:    serial@ff010000
+  Out:   serial@ff010000
+  Err:   serial@ff010000
+  Net:   No ethernet found.
+  ZynqMP r5>
+
+Please make sure MIO pins for uart are properly configured to see output.
diff --git a/roms/u-boot/doc/board/xilinx/zynqmp.rst b/roms/u-boot/doc/board/xilinx/zynqmp.rst
new file mode 100644
index 000000000..a035cff1a
--- /dev/null
+++ b/roms/u-boot/doc/board/xilinx/zynqmp.rst
@@ -0,0 +1,115 @@
+.. SPDX-License-Identifier: GPL-2.0
+..  (C) Copyright 2020 Xilinx, Inc.
+
+ZYNQMP
+======
+
+About this
+----------
+
+This document describes the information about Xilinx Zynq UltraScale+ MPSOC
+U-Boot support. Core support is available in arch/arm/mach-zynqmp folder.
+
+ZynqMP boards
+-------------
+
+* zcu100 (ultra96 v1), zcu102, zcu104, zcu106 - Evaluation boards
+* zc1232 - Characterization boards
+* zcu111, zcu208, zcu216 - RFSOC evaluation boards
+* zcu1254, zcu1275, zcu1285 - RFSOC characterization boards
+* a2197 - System Controller on Versal boards
+* mini - Mini U-Boot running out of OCM
+* zc1751 - Characterization Processor boards
+     - zc1751-xm015-dc1
+     - zc1751-xm016-dc2
+     - zc1751-xm017-dc3
+     - zc1751-xm018-dc4
+     - zc1751-xm019-dc5
+
+Building
+--------
+
+Configure and build for zcu102 board::
+
+   $ source arm64 toolchain
+   $ export DEVICE_TREE=zynqmp-zcu102-revA
+   $ make xilinx_zynqmp_virt_defconfig
+   $ make
+
+U-Boot SPL flow
+---------------
+
+For getting U-Boot SPL flow up and running it is necessary to do some additional
+steps because booting device requires external images which are not the part of
+U-Boot repository.
+
+PMU firmware
+^^^^^^^^^^^^
+The Platform Management Unit (PMU) RAM can be loaded with a firmware (PMU
+Firmware) at run-time and can be used to extend or customize the functionality
+of PMU. The PMU firmware is the part of boot image (boot.bin) and it is
+automatically loaded by BootROM. boot.bin can be directly generated by mkimage
+tool as the part of make. If you want to create boot.bin with PMU Firmware
+include please point CONFIG_PMUFW_INIT_FILE to PMU firmware binary. For example:::
+
+  CONFIG_PMUFW_INIT_FILE="<path>/pmu.bin"
+
+If you see below message you need to load PMU Firmware::
+
+  PMUFW is not found - Please load it!
+
+The second external blob is PMU Configuration object which is object which is
+passed from U-Boot SPL to PMU Firmware for initial system configuration. PMU
+configuration object is the part of U-Boot SPL image. For pointing to this
+object please use CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE symbol. For example:::
+
+  CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE="<path>/pmu_obj.bin"
+
+
+PMU configuration object
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+Object can be obtain in several ways. The easiest way is to take pm_cfg_obj.c
+from SDK/Vitis design and build it:::
+
+  $ git clone https://github.com/Xilinx/embeddedsw.git
+  $ export EMBEDDED_SW=$PWD/embeddedsw
+  $ gcc -c pm_cfg_obj.c -I ${EMBEDDED_SW}/lib/bsp/standalone/src/common/ -I ${EMBEDDED_SW}/lib/sw_services/xilpm/src/zynqmp/client/common/
+  $ objcopy -O binary pm_cfg_obj.o pmu_obj.bin
+
+The second way is to use tools/zynqmp_pm_cfg_obj_convert.py. For more
+information about this tool please run it with -h parameter.
+
+The third way is to extract it from Xilinx FSBL elf file. Object is starting at
+XPm_ConfigObject symbol.
+
+
+Arm Trusted Firmware (ATF)
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+U-Boot itself can run from EL3 to EL1. Without ATF U-Boot runs in EL3. Boot flow
+is U-Boot SPL->U-Boot in EL3. When ATF is used U-Boot normally runs in EL2. Boot
+flow is U-Boot SPL->ATF->U-Boot in EL2. As the part of build process u-boot.itb
+is generated. When BL31 shell variable is present u-boot.itb is generated with
+ATF included. You can point to it by:::
+
+  $ export BL31=<path>/bl31.bin
+
+Flashing
+--------
+
+SD Card
+^^^^^^^
+
+To write an image that boots from a SD card first create a FAT32 partition
+and a FAT32 filesystem on the SD card::
+
+        sudo fdisk /dev/sdx
+        sudo mkfs.vfat -F 32 /dev/sdx1
+
+Mount the SD card and copy the SPL and U-Boot to the root directory of the
+SD card::
+
+        sudo mount -t vfat /dev/sdx1 /mnt
+        sudo cp spl/boot.bin /mnt
+        sudo cp u-boot.itb /mnt
author	Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>	2023-10-10 14:33:42 +0000
committer	Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com>	2023-10-10 14:33:42 +0000
commit	af1a266670d040d2f4083ff309d732d648afba2a (patch)
tree	2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/doc/board
parent	e02cda008591317b1625707ff8e115a4841aa889 (diff)