Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

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diff --git a/roms/u-boot/doc/board/freescale/b4860qds.rst b/roms/u-boot/doc/board/freescale/b4860qds.rst
new file mode 100644
index 000000000..de14d857b
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/b4860qds.rst
@@ -0,0 +1,453 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+B4860QDS
+========
+
+The B4860QDS is a Freescale reference board that hosts the B4860 SoC
+(and variants).
+
+B4860 Overview
+--------------
+The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
+StarCore and Power Architecture® cores. It targets the broadband wireless
+infrastructure and builds upon the proven success of the existing multicore
+DSPs and Power CPUs. It is designed to bolster the rapidly changing and
+expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
+
+The B4860 is a highly-integrated StarCore and Power Architecture processor that
+contains:
+
+* Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
+  clusters-each core runs up to 1.2 GHz, with an architecture highly optimized
+  for wireless base station applications
+* Four dual-thread e6500 Power Architecture processors organized in one
+  cluster-each core runs up to 1.8 GHz
+* Two DDR3/3L controllers for high-speed, industry-standard memory interface
+  each runs at up to 1866.67 MHz
+* MAPLE-B3 hardware acceleration-for forward error correction schemes including
+  Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
+  equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
+  FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
+  acceleration
+* CoreNet fabric that fully supports coherency using MESI protocol between the
+  e6500 cores, SC3900 FVP cores, memories and external interfaces.
+  CoreNet fabric interconnect runs at 667 MHz and supports coherent and
+  non-coherent out of order transactions with prioritization and bandwidth
+  allocation amongst CoreNet endpoints.
+* Data Path Acceleration Architecture, which includes the following:
+
+     * Frame Manager (FMan), which supports in-line packet parsing and general
+       classification to enable policing and QoS-based packet distribution
+     * Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
+       of queue management, task management, load distribution, flow ordering,
+       buffer management, and allocation tasks from the cores
+     * Security engine (SEC 5.3)-crypto-acceleration for protocols such as
+       IPsec, SSL, and 802.16
+     * RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound
+       and outbound). Supports types 5, 6 (outbound only)
+
+* Large internal cache memory with snooping and stashing capabilities for
+  bandwidth saving and high utilization of processor elements. The 9856-Kbyte
+  internal memory space includes the following:
+
+     * 32 Kbyte L1 ICache per e6500/SC3900 core
+     * 32 Kbyte L1 DCache per e6500/SC3900 core
+     * 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
+     * 2048 Kbyte unified L2 cache for the e6500 cluster
+     * Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
+
+* Sixteen 10-GHz SerDes lanes serving:
+
+     * Two Serial RapidIO interfaces
+     * Each supports up to 4 lanes and a total of up to 8 lanes
+
+* Up to 8-lanes Common Public Radio Interface (CPRI) controller for
+  glue-less antenna connection
+* Two 10-Gbit Ethernet controllers (10GEC)
+* Six 1G/2.5-Gbit Ethernet controllers for network communications
+* PCI Express controller
+* Debug (Aurora)
+* Two OCeaN DMAs
+* Various system peripherals
+* 182 32-bit timers
+
+B4860QDS Overview
+-----------------
+- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
+  ECC, 4 GB of memory in two ranks of 2 GB.
+- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
+  ECC, 2 GB of memory. Single rank.
+- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
+  16x16 switch VSC3316
+- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
+  8x8 switch VSC3308
+- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
+  B4860 UART port is available over USB-to-UART translator USB2SER or over
+  RS232 flat cable.
+- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45
+  copper connectors for Stand-alone mode and to the 1000Base-X over AMC
+  MicroTCA connector ports 0 and 2 for AMC mode.
+- The B4860 configuration may be loaded from nine bits coded reset configuration
+  reset source. The RCW source is set by appropriate DIP-switches.
+- 16-bit NOR Flash / PROMJet
+- QIXIS 8-bit NOR Flash Emulator
+- 8-bit NAND Flash
+- 24-bit SPI Flash
+- Long address I2C EEPROM
+- Available debug interfaces are:
+
+     - On-board eCWTAP controller with ETH and USB I/F
+     - JTAG/COP 16-pin header for any external TAP controller
+     - External JTAG source over AMC to support B2B configuration
+     - 70-pin Aurora debug connector
+
+- QIXIS (FPGA) logic:
+     - 2 KB internal memory space including
+
+- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
+  DDRCLK1,2 and RTCCLK.
+- Two 8T49N222A SerDes ref clock devices support two SerDes port clock
+  frequency - total four refclk, including CPRI clock scheme.
+
+
+B4420 Personality
+-----------------
+
+B4420 is a reduced personality of B4860 with less core/clusters(both SC3900
+and e6500), less DDR controllers, less serdes lanes, less SGMII interfaces
+and reduced target frequencies.
+
+Key differences between B4860 and B4420
+---------------------------------------
+
+B4420 has:
+
+1. Less e6500 cores: 1 cluster with 2 e6500 cores
+2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
+3. Single DDRC
+4. 2X 4 lane serdes
+5. 3 SGMII interfaces
+6. no sRIO
+7. no 10G
+
+B4860QDS Default Settings
+-------------------------
+
+Switch Settings
+^^^^^^^^^^^^^^^
+
+.. code-block:: none
+
+   SW1	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]
+   SW2	ON	ON	ON	ON	ON	ON	OFF	OFF
+   SW3	OFF	OFF	OFF	ON	OFF	OFF	ON	OFF
+   SW5	OFF	OFF	OFF	OFF	OFF	OFF	ON	ON
+
+Note:
+
+- PCIe slots modes: All the PCIe devices work as Root Complex.
+- Boot location: NOR flash.
+
+SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
+66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
+
+NAND boot::
+
+	SW1 [1.1] = 0
+	SW2 [1.1] = 1
+	SW3 [1:4] = 0001
+
+NOR boot::
+
+	SW1 [1.1] = 1
+	SW2 [1.1] = 0
+	SW3 [1:4] = 1000
+
+B4420QDS Default Settings
+-------------------------
+
+Switch Settings
+^^^^^^^^^^^^^^^
+
+.. code-block:: none
+
+   SW1	OFF[0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]
+   SW2	ON	OFF	ON	OFF	ON	ON	OFF	OFF
+   SW3	OFF	OFF	OFF	ON	OFF	OFF	ON	OFF
+   SW5	OFF	OFF	OFF	OFF	OFF	OFF	ON	ON
+
+Note:
+
+- PCIe slots modes: All the PCIe devices work as Root Complex.
+- Boot location: NOR flash.
+
+SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
+66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
+
+NAND boot::
+
+	SW1 [1.1] = 0
+	SW2 [1.1] = 1
+	SW3 [1:4] = 0001
+
+NOR boot::
+
+	SW1 [1.1] = 1
+	SW2 [1.1] = 0
+	SW3 [1:4] = 1000
+
+Memory map on B4860QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+=============   =============   =============== =======
+Start Address	End Address	Description	Size
+=============   =============   =============== =======
+0xF_FFDF_1000 	0xF_FFFF_FFFF	Free		2 MB
+0xF_FFDF_0000 	0xF_FFDF_0FFF	IFC - FPGA 	4 KB
+0xF_FF81_0000 	0xF_FFDE_FFFF	Free		5 MB
+0xF_FF80_0000	0xF_FF80_FFFF	IFC NAND Flash	64 KB
+0xF_FF00_0000	0xF_FF7F_FFFF	Free		8 MB
+0xF_FE00_0000 	0xF_FEFF_FFFF	CCSRBAR		16 MB
+0xF_F801_0000 	0xF_FDFF_FFFF	Free		95 MB
+0xF_F800_0000	0xF_F800_FFFF	PCIe I/O Space 	64 KB
+0xF_F600_0000 	0xF_F7FF_FFFF	QMAN s/w portal	32 MB
+0xF_F400_0000 	0xF_F5FF_FFFF	BMAN s/w portal	32 MB
+0xF_F000_0000 	0xF_F3FF_FFFF	Free		64 MB
+0xF_E800_0000 	0xF_EFFF_FFFF	IFC  NOR Flash 	128 MB
+0xF_E000_0000	0xF_E7FF_FFFF	Promjet		128 MB
+0xF_A0C0_0000 	0xF_DFFF_FFFF	Free		1012 MB
+0xF_A000_0000 	0xF_A0BF_FFFF	MAPLE0/1/2	12 MB
+0xF_0040_0000 	0xF_9FFF_FFFF	Free		12 GB
+0xF_0000_0000 	0xF_01FF_FFFF	DCSR		32 MB
+0xC_4000_0000 	0xE_FFFF_FFFF	Free		11 GB
+0xC_3000_0000 	0xC_3FFF_FFFF	sRIO-2 I/O 	256 MB
+0xC_2000_0000 	0xC_2FFF_FFFF	sRIO-1 I/O  	256 MB
+0xC_0000_0000	0xC_1FFF_FFFF	PCIe Mem Space 	512 MB
+0x1_0000_0000 	0xB_FFFF_FFFF	Free		44 GB
+0x0_8000_0000 	0x0_FFFF_FFFF	DDRC1		2 GB
+0x0_0000_0000 	0x0_7FFF_FFFF	DDRC2	  	2 GB
+=============   =============   =============== =======
+
+Memory map on B4420QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+=============   =============   =============== =======
+Start Address	End Address	Description	Size
+=============   =============   =============== =======
+0xF_FFDF_1000 	0xF_FFFF_FFFF	Free		2 MB
+0xF_FFDF_0000 	0xF_FFDF_0FFF	IFC - FPGA 	4 KB
+0xF_FF81_0000 	0xF_FFDE_FFFF	Free		5 MB
+0xF_FF80_0000	0xF_FF80_FFFF	IFC NAND Flash	64 KB
+0xF_FF00_0000	0xF_FF7F_FFFF	Free		8 MB
+0xF_FE00_0000 	0xF_FEFF_FFFF	CCSRBAR		16 MB
+0xF_F801_0000 	0xF_FDFF_FFFF	Free		95 MB
+0xF_F800_0000	0xF_F800_FFFF	PCIe I/O Space 	64 KB
+0xF_F600_0000 	0xF_F7FF_FFFF	QMAN s/w portal	32 MB
+0xF_F400_0000 	0xF_F5FF_FFFF	BMAN s/w portal	32 MB
+0xF_F000_0000 	0xF_F3FF_FFFF	Free		64 MB
+0xF_E800_0000 	0xF_EFFF_FFFF	IFC  NOR Flash 	128 MB
+0xF_E000_0000	0xF_E7FF_FFFF	Promjet		128 MB
+0xF_A0C0_0000 	0xF_DFFF_FFFF	Free		1012 MB
+0xF_A000_0000 	0xF_A0BF_FFFF	MAPLE0/1/2	12 MB
+0xF_0040_0000 	0xF_9FFF_FFFF	Free		12 GB
+0xF_0000_0000 	0xF_01FF_FFFF	DCSR		32 MB
+0xC_4000_0000 	0xE_FFFF_FFFF	Free		11 GB
+0xC_3000_0000 	0xC_3FFF_FFFF	sRIO-2 I/O 	256 MB
+0xC_2000_0000 	0xC_2FFF_FFFF	sRIO-1 I/O  	256 MB
+0xC_0000_0000	0xC_1FFF_FFFF	PCIe Mem Space 	512 MB
+0x1_0000_0000 	0xB_FFFF_FFFF	Free		44 GB
+0x0_0000_0000 	0x0_FFFF_FFFF	DDRC1		4 GB
+=============   =============   =============== =======
+
+NOR Flash memory Map on B4860 and B4420QDS
+------------------------------------------
+
+=============   =============   ==============================  =========
+ Start		 End		Definition			Size
+=============   =============   ==============================  =========
+0xEFF40000	0xEFFFFFFF	U-Boot (current bank)		768KB
+0xEFF20000	0xEFF3FFFF	U-Boot env (current bank)	128KB
+0xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
+0xEF300000	0xEFEFFFFF	rootfs (alternate bank)		12MB
+0xEE800000	0xEE8FFFFF	device tree (alternate bank)	1MB
+0xEE020000	0xEE6FFFFF	Linux.uImage (alternate bank)	6MB+896KB
+0xEE000000	0xEE01FFFF	RCW (alternate bank)		128KB
+0xEDF40000	0xEDFFFFFF	U-Boot (alternate bank)		768KB
+0xEDF20000	0xEDF3FFFF	U-Boot env (alternate bank)	128KB
+0xEDF00000	0xEDF1FFFF	FMAN ucode (alternate bank)	128KB
+0xED300000	0xEDEFFFFF	rootfs (current bank)		12MB
+0xEC800000	0xEC8FFFFF	device tree (current bank)	1MB
+0xEC020000	0xEC6FFFFF	Linux.uImage (current bank)	6MB+896KB
+0xEC000000	0xEC01FFFF	RCW (current bank)		128KB
+=============   =============   ==============================  =========
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to both B4860QDS and B4420QDS.
+
+U-Boot environment variable hwconfig
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The default hwconfig is:
+
+.. code-block:: none
+
+   hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=ulpi
+
+Note: For USB gadget set "dr_mode=peripheral"
+
+FMAN Ucode versions
+^^^^^^^^^^^^^^^^^^^
+
+fsl_fman_ucode_B4860_106_3_6.bin
+
+Switching to alternate bank
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Commands for switching to alternate bank.
+
+1. To change from vbank0 to vbank2
+
+.. code-block:: none
+
+   => qixis_reset altbank (it will boot using vbank2)
+
+2. To change from vbank2 to vbank0
+
+.. code-block:: none
+
+   => qixis reset (it will boot using vbank0)
+
+To change personality of board
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+For changing personality from B4860 to B4420
+
+1. Boot from vbank0
+2. Flash vbank2 with b4420 rcw and U-Boot
+3. Give following commands to uboot prompt
+
+.. code-block:: none
+
+   => mw.b ffdf0040 0x30;
+   => mw.b ffdf0010 0x00;
+   => mw.b ffdf0062 0x02;
+   => mw.b ffdf0050 0x02;
+   => mw.b ffdf0010 0x30;
+   => reset
+
+Note:
+
+- Power off cycle will lead to default switch settings.
+- 0xffdf0000 is the address of the QIXIS FPGA.
+
+Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+To change from NOR to NAND boot give following command on uboot prompt
+
+.. code-block:: none
+
+   => mw.b ffdf0040 0x30
+   => mw.b ffdf0010 0x00
+   => mw.b 0xffdf0050 0x08
+   => mw.b 0xffdf0060 0x82
+   => mw.b ffdf0061 0x00
+   => mw.b ffdf0010 0x30
+   => reset
+
+To change from NAND to NOR boot give following command on uboot prompt:
+
+.. code-block:: none
+
+   => mw.b ffdf0040 0x30
+   => mw.b ffdf0010 0x00
+   => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
+   => mw.b 0xffdf0060 0x12
+   => mw.b ffdf0061 0x01
+   => mw.b ffdf0010 0x30
+   => reset
+
+Note:
+
+- Power off cycle will lead to default switch settings.
+- 0xffdf0000 is the address of the QIXIS FPGA.
+
+Ethernet interfaces for B4860QDS
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Serdes protocosl tested:
+* 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
+* 0x2a, 0xb2 (serdes1, serdes2)
+
+When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
+SGMII on SGMII riser card.
+
+Under U-Boot these network interfaces are recognized as::
+
+   FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
+
+On Linux the interfaces are renamed as::
+
+   eth2 -> fm1-gb2
+   eth3 -> fm1-gb3
+   eth4 -> fm1-gb4
+   eth5 -> fm1-gb5
+
+RCW and Ethernet interfaces for B4420QDS
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Serdes protocosl tested:
+* 0x18, 0x9e (serdes1, serdes2)
+
+Under U-Boot these network interfaces are recognized as::
+
+   FM1@DTSEC3, FM1@DTSEC4 and  e1000#0.
+
+On Linux the interfaces are renamed as::
+
+   eth2 -> fm1-gb2
+   eth3 -> fm1-gb3
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+U-Boot(768 KB) from flash to DDR.
+Finally SPL transer control to U-Boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework during  boot:
+
++----------------------------------------------+
+|Area        | Address                         |
++----------------------------------------------+
+|Secure boot | 0xFFFC0000 (32KB)               |
+|headers     |                                 |
++----------------------------------------------+
+|GD, BD      | 0xFFFC8000 (4KB)                |
++----------------------------------------------+
+|ENV         | 0xFFFC9000 (8KB)                |
++----------------------------------------------+
+|HEAP        | 0xFFFCB000 (30KB)               |
++----------------------------------------------+
+|STACK       | 0xFFFD8000 (22KB)               |
++----------------------------------------------+
+|U-Boot SPL  | 0xFFFD8000 (160KB)              |
++----------------------------------------------+
+
+NAND Flash memory Map on B4860 and B4420QDS
+-------------------------------------------
+
+=============   =============   =============================   =====
+Start		End		Definition			Size
+=============   =============   =============================   =====
+0x000000	0x0FFFFF	U-Boot                          1MB
+0x140000	0x15FFFF	U-Boot env                      128KB
+0x1A0000	0x1BFFFF	FMAN Ucode                      128KB
+=============   =============   =============================   =====
diff --git a/roms/u-boot/doc/board/freescale/imx8mm_evk.rst b/roms/u-boot/doc/board/freescale/imx8mm_evk.rst
new file mode 100644
index 000000000..7fd3d7256
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imx8mm_evk.rst
@@ -0,0 +1,57 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mm_evk
+==========
+
+U-Boot for the NXP i.MX8MM EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.47_2.2.0
+
+.. code-block:: bash
+
+   $ make PLAT=imx8mm bl31
+   $ cp build/imx8mm/release/bl31.bin $(builddir)
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+   $ chmod +x firmware-imx-8.9.bin
+   $ ./firmware-imx-8.9
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ make imx8mm_evk_defconfig
+   $ export ATF_LOAD_ADDR=0x920000
+   $ make
+
+Burn the flash.bin to MicroSD card offset 33KB:
+
+.. code-block:: bash
+
+   $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=notrunc
+   $sudo dd if=u-boot.itb of=/dev/sdc bs=1024 seek=384 conv=sync
+
+Boot
+----
+Set Boot switch to SD boot
diff --git a/roms/u-boot/doc/board/freescale/imx8mn_evk.rst b/roms/u-boot/doc/board/freescale/imx8mn_evk.rst
new file mode 100644
index 000000000..9fbb94703
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imx8mn_evk.rst
@@ -0,0 +1,58 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mn_evk
+==========
+
+U-Boot for the NXP i.MX8MN EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get firmware-imx package
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.47_2.2.0
+
+.. code-block:: bash
+
+   $ make PLAT=imx8mn bl31
+   $ cp build/imx8mn/release/bl31.bin $(srctree)
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+   $ chmod +x firmware-imx-8.9.bin
+   $ ./firmware-imx-8.9
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/ddr4*.bin $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ make imx8mn_ddr4_evk_defconfig
+   $ export ATF_LOAD_ADDR=0x960000
+   $ make
+
+Burn the flash.bin to MicroSD card offset 32KB:
+
+.. code-block:: bash
+
+   $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+   $sudo dd if=u-boot.itb of=/dev/sd[x] bs=1024 seek=384 conv=notrunc
+
+Boot
+----
+
+Set Boot switch to SD boot
diff --git a/roms/u-boot/doc/board/freescale/imx8mp_evk.rst b/roms/u-boot/doc/board/freescale/imx8mp_evk.rst
new file mode 100644
index 000000000..609a29f3e
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imx8mp_evk.rst
@@ -0,0 +1,61 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mp_evk
+==========
+
+U-Boot for the NXP i.MX8MP EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get the firmware-imx package
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.70_2.3.0
+
+.. code-block:: bash
+
+   $ make PLAT=imx8mp bl31
+
+Get the ddr firmware
+--------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.10.bin
+   $ chmod +x firmware-imx-8.10.bin
+   $ ./firmware-imx-8.10.bin
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ make O=build imx8mp_evk_defconfig
+   $ cp ../imx-atf/build/imx8mp/release/bl31.bin ./build/bl31.bin
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin ./build/
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin ./build/
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin ./build/
+   $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin ./build/
+   $ export ATF_LOAD_ADDR=0x970000
+   $ make O=build
+
+Burn the flash.bin to the MicroSD card at offset 32KB:
+
+.. code-block:: bash
+
+   $sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
+   $sudo dd if=build/u-boot.itb of=/dev/sd[x] bs=1K seek=384 conv=notrunc; sync
+
+Boot
+----
+
+Set Boot switch to SD boot
+Use /dev/ttyUSB2 for U-Boot console
diff --git a/roms/u-boot/doc/board/freescale/imx8mq_evk.rst b/roms/u-boot/doc/board/freescale/imx8mq_evk.rst
new file mode 100644
index 000000000..c269fdebe
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imx8mq_evk.rst
@@ -0,0 +1,56 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8mq_evk
+==========
+
+U-Boot for the NXP i.MX8MQ EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get ddr and hdmi fimware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.47_2.2.0
+
+.. code-block:: bash
+
+   $ make PLAT=imx8mq bl31
+   $ cp build/imx8mq/release/bl31.bin $(builddir)
+
+Get the ddr and hdmi firmware
+-----------------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+   $ chmod +x firmware-imx-8.9.bin
+   $ ./firmware-imx-8.9.bin
+   $ cp firmware-imx-8.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
+   $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ make imx8mq_evk_defconfig
+   $ make flash.bin
+
+Burn the flash.bin to MicroSD card offset 33KB:
+
+.. code-block:: bash
+
+   $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=notrunc
+
+Boot
+----
+Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
diff --git a/roms/u-boot/doc/board/freescale/imx8qxp_mek.rst b/roms/u-boot/doc/board/freescale/imx8qxp_mek.rst
new file mode 100644
index 000000000..215627cfa
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imx8qxp_mek.rst
@@ -0,0 +1,66 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx8qxp_mek
+===========
+
+U-Boot for the NXP i.MX8QXP EVK board
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+.. code-block:: bash
+
+   $ git clone https://source.codeaurora.org/external/imx/imx-atf
+   $ cd imx-atf/
+   $ git checkout origin/imx_4.19.35_1.1.0 -b imx_4.19.35_1.1.0
+   $ make PLAT=imx8qx bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.2.7.1.bin
+   $ chmod +x imx-sc-firmware-1.2.7.1.bin
+   $ ./imx-sc-firmware-1.2.7.1.bin
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-2.3.1.bin
+   $ chmod +x imx-seco-2.3.1.bin
+   $ ./imx-seco-2.3.1.bin
+
+Copy the following binaries to U-Boot folder:
+
+.. code-block:: bash
+
+  $ cp imx-atf/build/imx8qx/release/bl31.bin .
+  $ cp imx-seco-2.3.1/firmware/seco/mx8qx-ahab-container.img ./ahab-container.img
+  $ cp imx-sc-firmware-1.2.7.1/mx8qx-mek-scfw-tcm.bin	.
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+  $ make imx8qxp_mek_defconfig
+  $ make flash.bin
+
+Flash the binary into the SD card
+---------------------------------
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+.. code-block:: bash
+
+   $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
+
+Boot
+----
+Set Boot switch SW2: 1100.
diff --git a/roms/u-boot/doc/board/freescale/imxrt1020-evk.rst b/roms/u-boot/doc/board/freescale/imxrt1020-evk.rst
new file mode 100644
index 000000000..267f80c51
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imxrt1020-evk.rst
@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imxrt1020-evk
+=============
+
+How to use U-Boot on NXP i.MXRT1020 EVK
+---------------------------------------
+
+- Build U-Boot for i.MXRT1020 EVK:
+
+.. code-block:: bash
+
+   $ make mrproper
+   $ make imxrt1020-evk_defconfig
+   $ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+.. code-block:: bash
+
+   $sudo dd if=SPL of=/dev/sdX bs=1k seek=1 conv=notrunc; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+.. code-block:: bash
+
+   $sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128 conv=notrunc; sync
+
+- Jumper settings::
+
+   SW8: 0 1 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+  The USB console connector is the one close the ethernet connector
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
diff --git a/roms/u-boot/doc/board/freescale/imxrt1050-evk.rst b/roms/u-boot/doc/board/freescale/imxrt1050-evk.rst
new file mode 100644
index 000000000..c1fb48f0c
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/imxrt1050-evk.rst
@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imxrt1050-evk
+=============
+
+How to use U-Boot on NXP i.MXRT1050 EVK
+---------------------------------------
+
+- Build U-Boot for i.MXRT1050 EVK:
+
+.. code-block:: bash
+
+   $ make mrproper
+   $ make imxrt1050-evk_defconfig
+   $ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+.. code-block:: bash
+
+   $sudo dd if=SPL of=/dev/sdX bs=1k seek=1 conv=notrunc; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+.. code-block:: bash
+
+   $sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=128 conv=notrunc; sync
+
+- Jumper settings::
+
+   SW7: 1 0 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+  The USB console connector is the one close the ethernet connector
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
diff --git a/roms/u-boot/doc/board/freescale/index.rst b/roms/u-boot/doc/board/freescale/index.rst
new file mode 100644
index 000000000..313cf409a
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/index.rst
@@ -0,0 +1,20 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Freescale
+=========
+
+.. toctree::
+   :maxdepth: 2
+
+   b4860qds
+   imx8mm_evk
+   imx8mn_evk
+   imx8mp_evk
+   imx8mq_evk
+   imx8qxp_mek
+   imxrt1020-evk
+   imxrt1050-evk
+   mx6sabreauto
+   mx6sabresd
+   mx6ul_14x14_evk
+   mx6ullevk
diff --git a/roms/u-boot/doc/board/freescale/mx6sabreauto.rst b/roms/u-boot/doc/board/freescale/mx6sabreauto.rst
new file mode 100644
index 000000000..fe4cd9d21
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/mx6sabreauto.rst
@@ -0,0 +1,100 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6sabreauto
+============
+
+How to use and build U-Boot on mx6sabreauto
+-------------------------------------------
+
+mx6sabreauto_defconfig target supports mx6q/mx6dl/mx6qp sabreauto variants.
+
+In order to build it:
+
+.. code-block:: bash
+
+   $ make mx6sabreauto_defconfig
+   $ make
+
+This will generate the SPL and u-boot-dtb.img binaries.
+
+- Flash the SPL binary into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 conv=notrunc && sync
+
+- Flash the u-boot-dtb.img binary into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 conv=notrunc && sync
+
+Booting via Falcon mode
+-----------------------
+
+Write in mx6sabreauto_defconfig the following define below:
+
+CONFIG_SPL_OS_BOOT=y
+
+In order to build it:
+
+.. code-block:: bash
+
+   $ make mx6sabreauto_defconfig
+   $ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 conv=notrunc && sync
+
+- Flash the u-boot-dtb.img image into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdb bs=1K seek=69 conv=notrunc && sync
+
+Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there:
+
+.. code-block:: bash
+
+   $ sudo cp uImage /media/boot
+   $ sudo cp imx6dl-sabreauto.dtb /media/boot
+
+Create a partition for root file system and extract it there:
+
+.. code-block:: bash
+
+   $ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Load dtb file from boot partition::
+
+   # load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
+
+- Load kernel image from boot partition::
+
+   # load mmc 0:1 ${loadaddr} uImage
+
+- Write kernel at 2MB offset::
+
+   # mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs::
+
+   # setenv bootargs "console=ttymxc3,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args::
+
+   # spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)::
+
+   # mmc write 18000000 0x800 0x800
+
+- Restart the board and then SPL binary will launch the kernel directly.
diff --git a/roms/u-boot/doc/board/freescale/mx6sabresd.rst b/roms/u-boot/doc/board/freescale/mx6sabresd.rst
new file mode 100644
index 000000000..fe15ba7b7
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/mx6sabresd.rst
@@ -0,0 +1,132 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6sabresd
+==========
+
+How to use and build U-Boot on mx6sabresd
+-----------------------------------------
+
+The following methods can be used for booting mx6sabresd boards:
+
+1. Booting from SD card
+
+2. Booting from eMMC
+
+3. Booting via Falcon mode (SPL launches the kernel directly)
+
+
+1. Booting from SD card via SPL
+-------------------------------
+
+mx6sabresd_defconfig target supports mx6q/mx6dl/mx6qp sabresd variants.
+
+In order to build it:
+
+.. code-block:: bash
+
+   $ make mx6sabresd_defconfig
+   $ make
+
+This will generate the SPL and u-boot-dtb.img binaries.
+
+- Flash the SPL binary into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 conv=notrunc && sync
+
+- Flash the u-boot-dtb.img binary into the SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 conv=notrunc && sync
+
+2. Booting from eMMC
+--------------------
+
+.. code-block:: bash
+
+   $ make mx6sabresd_defconfig
+   $ make
+
+This will generate the SPL and u-boot-dtb.img binaries.
+
+- Boot first from SD card as shown in the previous section
+
+In U-boot change the eMMC partition config::
+
+   => mmc partconf 2 1 0 0
+
+Mount the eMMC in the host PC::
+
+   => ums 0 mmc 2
+
+- Flash SPL and u-boot-dtb.img binaries into the eMMC:
+
+.. code-block:: bash
+
+   $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 conv=notrunc && sync
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 conv=notrunc && sync
+
+Set SW6 to eMMC 8-bit boot: 11010110
+
+3. Booting via Falcon mode
+--------------------------
+
+.. code-block:: bash
+
+  $ make mx6sabresd_defconfig
+  $ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the SD card
+
+.. code-block:: bash
+
+   $ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none conv=notrunc && sync
+
+- Flash the u-boot-dtb.img image into the SD card
+
+.. code-block:: bash
+
+   $ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none conv=notrunc && sync
+
+Create a partition for root file system and extract it there
+
+.. code-block:: bash
+
+   $ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Setup the IP server::
+
+   # setenv serverip <server_ip_address>
+
+- Download dtb file::
+
+   # dhcp ${fdt_addr} imx6q-sabresd.dtb
+
+- Download kernel image::
+
+   # dhcp ${loadaddr} uImage
+
+- Write kernel at 2MB offset::
+
+   # mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs::
+
+   # setenv bootargs "console=ttymxc0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args::
+
+   # spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)::
+
+   # mmc write 18000000 0x800 0x800
+
+- Press KEY_VOL_UP key, power up the board and then SPL binary will launch the kernel directly.
diff --git a/roms/u-boot/doc/board/freescale/mx6ul_14x14_evk.rst b/roms/u-boot/doc/board/freescale/mx6ul_14x14_evk.rst
new file mode 100644
index 000000000..8298bf8e1
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/mx6ul_14x14_evk.rst
@@ -0,0 +1,98 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6ul_14x14_evk
+===============
+
+How to use U-Boot on Freescale MX6UL 14x14 EVK
+-----------------------------------------------
+
+- Build U-Boot for MX6UL 14x14 EVK:
+
+.. code-block:: bash
+
+   $ make mrproper
+   $ make mx6ul_14x14_evk_defconfig
+   $ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+1. Booting via SDCard
+---------------------
+
+- Flash the SPL image into the micro SD card:
+
+.. code-block:: bash
+
+   sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1 conv=notrunc; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+.. code-block:: bash
+
+   sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69 conv=notrunc; sync
+
+- Jumper settings::
+
+   SW601: 0 0 1 0
+   Sw602: 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+  The USB console connector is the one close the push buttons
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should come up.
+
+2. Booting via Serial Download Protocol (SDP)
+---------------------------------------------
+
+The mx6ulevk board can boot from USB OTG port using the SDP, target will
+enter in SDP mode in case an SD Card is not connect or boot switches are
+set as below::
+
+   Sw602: 0 1
+   SW601: x x x x
+
+The following tools can be used to boot via SDP, for both tools you must
+connect an USB cable in USB OTG port.
+
+- Method 1: Universal Update Utility (uuu)
+
+The UUU binary can be downloaded in release tab from link below:
+https://github.com/NXPmicro/mfgtools
+
+The following script should be created to boot SPL + u-boot-dtb.img binaries:
+
+.. code-block:: bash
+
+   $ cat uuu_script
+     uuu_version 1.1.4
+
+     SDP: boot -f SPL
+     SDPU: write -f u-boot-dtb.img -addr 0x877fffc0
+     SDPU: jump -addr 0x877fffc0
+     SDPU: done
+
+Please note that the address above is calculated based on SYS_TEXT_BASE address:
+
+0x877fffc0 = 0x87800000 (SYS_TEXT_BASE) - 0x40 (U-Boot proper Header size)
+
+Power on the target and run the following command from U-Boot root directory:
+
+.. code-block:: bash
+
+   $ sudo ./uuu uuu_script
+
+- Method 2: imx usb loader tool (imx_usb):
+
+The imx_usb_loader tool can be downloaded in link below:
+https://github.com/boundarydevices/imx_usb_loader
+
+Build the source code and run the following commands from U-Boot root
+directory:
+
+.. code-block:: bash
+
+   $ sudo ./imx_usb SPL
+   $ sudo ./imx_usb u-boot-dtb.img
diff --git a/roms/u-boot/doc/board/freescale/mx6ullevk.rst b/roms/u-boot/doc/board/freescale/mx6ullevk.rst
new file mode 100644
index 000000000..a26248a1e
--- /dev/null
+++ b/roms/u-boot/doc/board/freescale/mx6ullevk.rst
@@ -0,0 +1,47 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+mx6ullevk
+=========
+
+How to use U-Boot on Freescale MX6ULL 14x14 EVK
+-----------------------------------------------
+
+- First make sure you have installed the dtc package (device tree compiler):
+
+.. code-block:: bash
+
+   $ sudo apt-get install device-tree-compiler
+
+- Build U-Boot for MX6ULL 14x14 EVK:
+
+.. code-block:: bash
+
+   $ make mrproper
+   $ make mx6ull_14x14_evk_defconfig
+   $ make
+
+This generates the u-boot-dtb.imx image in the current directory.
+
+- Flash the u-boot-dtb.imx image into the micro SD card:
+
+.. code-block:: bash
+
+   $ sudo dd if=u-boot-dtb.imx of=/dev/sdb bs=1K seek=1 conv=notrunc && sync
+
+- Jumper settings::
+
+   SW601: 0 0 1 0
+   Sw602: 1 0
+
+Where 0 means bottom position and 1 means top position (from the switch label
+numbers reference).
+
+Connect the USB cable between the EVK and the PC for the console.
+(The USB console connector is the one close the push buttons)
+
+Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
+
+The link for the board: http://www.nxp.com/products/microcontrollers-and- \
+processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/ \
+i.mx6qp/evaluation-kit-for-the-i.mx-6ull-applications-processor:MCIMX6ULL-EVK