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Diffstat (limited to 'capstone/arch/ARM')
21 files changed, 75370 insertions, 0 deletions
diff --git a/capstone/arch/ARM/ARMAddressingModes.h b/capstone/arch/ARM/ARMAddressingModes.h new file mode 100644 index 000000000..c4a2f98ab --- /dev/null +++ b/capstone/arch/ARM/ARMAddressingModes.h @@ -0,0 +1,698 @@ +//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the ARM addressing mode implementation stuff. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +#ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H +#define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H + +#include "capstone/platform.h" +#include "../../MathExtras.h" + +/// ARM_AM - ARM Addressing Mode Stuff +typedef enum ARM_AM_ShiftOpc { + ARM_AM_no_shift = 0, + ARM_AM_asr, + ARM_AM_lsl, + ARM_AM_lsr, + ARM_AM_ror, + ARM_AM_rrx +} ARM_AM_ShiftOpc; + +typedef enum ARM_AM_AddrOpc { + ARM_AM_sub = 0, + ARM_AM_add +} ARM_AM_AddrOpc; + +static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op) +{ + return Op == ARM_AM_sub ? "-" : ""; +} + +static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op) +{ + switch (Op) { + default: return ""; //llvm_unreachable("Unknown shift opc!"); + case ARM_AM_asr: return "asr"; + case ARM_AM_lsl: return "lsl"; + case ARM_AM_lsr: return "lsr"; + case ARM_AM_ror: return "ror"; + case ARM_AM_rrx: return "rrx"; + } +} + +static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op) +{ + switch (Op) { + default: return (unsigned int)-1; //llvm_unreachable("Unknown shift opc!"); + case ARM_AM_asr: return 2; + case ARM_AM_lsl: return 0; + case ARM_AM_lsr: return 1; + case ARM_AM_ror: return 3; + } +} + +typedef enum ARM_AM_AMSubMode { + ARM_AM_bad_am_submode = 0, + ARM_AM_ia, + ARM_AM_ib, + ARM_AM_da, + ARM_AM_db +} ARM_AM_AMSubMode; + +static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode) +{ + switch (Mode) { + default: return ""; + case ARM_AM_ia: return "ia"; + case ARM_AM_ib: return "ib"; + case ARM_AM_da: return "da"; + case ARM_AM_db: return "db"; + } +} + +/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. +/// +static inline unsigned rotr32(unsigned Val, unsigned Amt) +{ + //assert(Amt < 32 && "Invalid rotate amount"); + return (Val >> Amt) | (Val << ((32-Amt)&31)); +} + +/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. +/// +static inline unsigned rotl32(unsigned Val, unsigned Amt) +{ + //assert(Amt < 32 && "Invalid rotate amount"); + return (Val << Amt) | (Val >> ((32-Amt)&31)); +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #1: shift_operand with registers +//===--------------------------------------------------------------------===// +// +// This 'addressing mode' is used for arithmetic instructions. It can +// represent things like: +// reg +// reg [asr|lsl|lsr|ror|rrx] reg +// reg [asr|lsl|lsr|ror|rrx] imm +// +// This is stored three operands [rega, regb, opc]. The first is the base +// reg, the second is the shift amount (or reg0 if not present or imm). The +// third operand encodes the shift opcode and the imm if a reg isn't present. +// +static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm) +{ + return ShOp | (Imm << 3); +} + +static inline unsigned getSORegOffset(unsigned Op) +{ + return Op >> 3; +} + +static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op) +{ + return (ARM_AM_ShiftOpc)(Op & 7); +} + +/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return +/// the 8-bit imm value. +static inline unsigned getSOImmValImm(unsigned Imm) +{ + return Imm & 0xFF; +} + +/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return +/// the rotate amount. +static inline unsigned getSOImmValRot(unsigned Imm) +{ + return (Imm >> 8) * 2; +} + +/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, +/// computing the rotate amount to use. If this immediate value cannot be +/// handled with a single shifter-op, determine a good rotate amount that will +/// take a maximal chunk of bits out of the immediate. +static inline unsigned getSOImmValRotate(unsigned Imm) +{ + unsigned TZ, RotAmt; + // 8-bit (or less) immediates are trivially shifter_operands with a rotate + // of zero. + if ((Imm & ~255U) == 0) return 0; + + // Use CTZ to compute the rotate amount. + TZ = CountTrailingZeros_32(Imm); + + // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, + // not 9. + RotAmt = TZ & ~1; + + // If we can handle this spread, return it. + if ((rotr32(Imm, RotAmt) & ~255U) == 0) + return (32-RotAmt)&31; // HW rotates right, not left. + + // For values like 0xF000000F, we should ignore the low 6 bits, then + // retry the hunt. + if (Imm & 63U) { + unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); + unsigned RotAmt2 = TZ2 & ~1; + if ((rotr32(Imm, RotAmt2) & ~255U) == 0) + return (32-RotAmt2)&31; // HW rotates right, not left. + } + + // Otherwise, we have no way to cover this span of bits with a single + // shifter_op immediate. Return a chunk of bits that will be useful to + // handle. + return (32-RotAmt)&31; // HW rotates right, not left. +} + +/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit +/// into an shifter_operand immediate operand, return the 12-bit encoding for +/// it. If not, return -1. +static inline int getSOImmVal(unsigned Arg) +{ + unsigned RotAmt; + // 8-bit (or less) immediates are trivially shifter_operands with a rotate + // of zero. + if ((Arg & ~255U) == 0) return Arg; + + RotAmt = getSOImmValRotate(Arg); + + // If this cannot be handled with a single shifter_op, bail out. + if (rotr32(~255U, RotAmt) & Arg) + return -1; + + // Encode this correctly. + return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); +} + +/// isSOImmTwoPartVal - Return true if the specified value can be obtained by +/// or'ing together two SOImmVal's. +static inline bool isSOImmTwoPartVal(unsigned V) +{ + // If this can be handled with a single shifter_op, bail out. + V = rotr32(~255U, getSOImmValRotate(V)) & V; + if (V == 0) + return false; + + // If this can be handled with two shifter_op's, accept. + V = rotr32(~255U, getSOImmValRotate(V)) & V; + return V == 0; +} + +/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, +/// return the first chunk of it. +static inline unsigned getSOImmTwoPartFirst(unsigned V) +{ + return rotr32(255U, getSOImmValRotate(V)) & V; +} + +/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, +/// return the second chunk of it. +static inline unsigned getSOImmTwoPartSecond(unsigned V) +{ + // Mask out the first hunk. + V = rotr32(~255U, getSOImmValRotate(V)) & V; + + // Take what's left. + //assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); + return V; +} + +/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed +/// by a left shift. Returns the shift amount to use. +static inline unsigned getThumbImmValShift(unsigned Imm) +{ + // 8-bit (or less) immediates are trivially immediate operand with a shift + // of zero. + if ((Imm & ~255U) == 0) return 0; + + // Use CTZ to compute the shift amount. + return CountTrailingZeros_32(Imm); +} + +/// isThumbImmShiftedVal - Return true if the specified value can be obtained +/// by left shifting a 8-bit immediate. +static inline bool isThumbImmShiftedVal(unsigned V) +{ + // If this can be handled with + V = (~255U << getThumbImmValShift(V)) & V; + return V == 0; +} + +/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed +/// by a left shift. Returns the shift amount to use. +static inline unsigned getThumbImm16ValShift(unsigned Imm) +{ + // 16-bit (or less) immediates are trivially immediate operand with a shift + // of zero. + if ((Imm & ~65535U) == 0) return 0; + + // Use CTZ to compute the shift amount. + return CountTrailingZeros_32(Imm); +} + +/// isThumbImm16ShiftedVal - Return true if the specified value can be +/// obtained by left shifting a 16-bit immediate. +static inline bool isThumbImm16ShiftedVal(unsigned V) +{ + // If this can be handled with + V = (~65535U << getThumbImm16ValShift(V)) & V; + return V == 0; +} + +/// getThumbImmNonShiftedVal - If V is a value that satisfies +/// isThumbImmShiftedVal, return the non-shiftd value. +static inline unsigned getThumbImmNonShiftedVal(unsigned V) +{ + return V >> getThumbImmValShift(V); +} + + +/// getT2SOImmValSplat - Return the 12-bit encoded representation +/// if the specified value can be obtained by splatting the low 8 bits +/// into every other byte or every byte of a 32-bit value. i.e., +/// 00000000 00000000 00000000 abcdefgh control = 0 +/// 00000000 abcdefgh 00000000 abcdefgh control = 1 +/// abcdefgh 00000000 abcdefgh 00000000 control = 2 +/// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 +/// Return -1 if none of the above apply. +/// See ARM Reference Manual A6.3.2. +static inline int getT2SOImmValSplatVal(unsigned V) +{ + unsigned u, Vs, Imm; + // control = 0 + if ((V & 0xffffff00) == 0) + return V; + + // If the value is zeroes in the first byte, just shift those off + Vs = ((V & 0xff) == 0) ? V >> 8 : V; + // Any passing value only has 8 bits of payload, splatted across the word + Imm = Vs & 0xff; + // Likewise, any passing values have the payload splatted into the 3rd byte + u = Imm | (Imm << 16); + + // control = 1 or 2 + if (Vs == u) + return (((Vs == V) ? 1 : 2) << 8) | Imm; + + // control = 3 + if (Vs == (u | (u << 8))) + return (3 << 8) | Imm; + + return -1; +} + +/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the +/// specified value is a rotated 8-bit value. Return -1 if no rotation +/// encoding is possible. +/// See ARM Reference Manual A6.3.2. +static inline int getT2SOImmValRotateVal(unsigned V) +{ + unsigned RotAmt = CountLeadingZeros_32(V); + if (RotAmt >= 24) + return -1; + + // If 'Arg' can be handled with a single shifter_op return the value. + if ((rotr32(0xff000000U, RotAmt) & V) == V) + return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); + + return -1; +} + +/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit +/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit +/// encoding for it. If not, return -1. +/// See ARM Reference Manual A6.3.2. +static inline int getT2SOImmVal(unsigned Arg) +{ + int Rot; + // If 'Arg' is an 8-bit splat, then get the encoded value. + int Splat = getT2SOImmValSplatVal(Arg); + if (Splat != -1) + return Splat; + + // If 'Arg' can be handled with a single shifter_op return the value. + Rot = getT2SOImmValRotateVal(Arg); + if (Rot != -1) + return Rot; + + return -1; +} + +static inline unsigned getT2SOImmValRotate(unsigned V) +{ + unsigned RotAmt; + + if ((V & ~255U) == 0) + return 0; + + // Use CTZ to compute the rotate amount. + RotAmt = CountTrailingZeros_32(V); + return (32 - RotAmt) & 31; +} + +static inline bool isT2SOImmTwoPartVal (unsigned Imm) +{ + unsigned V = Imm; + // Passing values can be any combination of splat values and shifter + // values. If this can be handled with a single shifter or splat, bail + // out. Those should be handled directly, not with a two-part val. + if (getT2SOImmValSplatVal(V) != -1) + return false; + V = rotr32 (~255U, getT2SOImmValRotate(V)) & V; + if (V == 0) + return false; + + // If this can be handled as an immediate, accept. + if (getT2SOImmVal(V) != -1) return true; + + // Likewise, try masking out a splat value first. + V = Imm; + if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) + V &= ~0xff00ff00U; + else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) + V &= ~0x00ff00ffU; + // If what's left can be handled as an immediate, accept. + if (getT2SOImmVal(V) != -1) return true; + + // Otherwise, do not accept. + return false; +} + +static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) +{ + //assert (isT2SOImmTwoPartVal(Imm) && + // "Immedate cannot be encoded as two part immediate!"); + // Try a shifter operand as one part + unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm; + // If the rest is encodable as an immediate, then return it. + if (getT2SOImmVal(V) != -1) return V; + + // Try masking out a splat value first. + if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) + return Imm & 0xff00ff00U; + + // The other splat is all that's left as an option. + //assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1); + return Imm & 0x00ff00ffU; +} + +static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) +{ + // Mask out the first hunk + Imm ^= getT2SOImmTwoPartFirst(Imm); + // Return what's left + //assert (getT2SOImmVal(Imm) != -1 && + // "Unable to encode second part of T2 two part SO immediate"); + return Imm; +} + + +//===--------------------------------------------------------------------===// +// Addressing Mode #2 +//===--------------------------------------------------------------------===// +// +// This is used for most simple load/store instructions. +// +// addrmode2 := reg +/- reg shop imm +// addrmode2 := reg +/- imm12 +// +// The first operand is always a Reg. The second operand is a reg if in +// reg/reg form, otherwise it's reg#0. The third field encodes the operation +// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The +// fourth operand 16-17 encodes the index mode. +// +// If this addressing mode is a frame index (before prolog/epilog insertion +// and code rewriting), this operand will have the form: FI#, reg0, <offs> +// with no shift amount for the frame offset. +// +static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO, + unsigned IdxMode) +{ + //assert(Imm12 < (1 << 12) && "Imm too large!"); + bool isSub = Opc == ARM_AM_sub; + return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ; +} + +static inline unsigned getAM2Offset(unsigned AM2Opc) +{ + return AM2Opc & ((1 << 12)-1); +} + +static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc) +{ + return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add; +} + +static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) +{ + return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7); +} + +static inline unsigned getAM2IdxMode(unsigned AM2Opc) +{ + return (AM2Opc >> 16); +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #3 +//===--------------------------------------------------------------------===// +// +// This is used for sign-extending loads, and load/store-pair instructions. +// +// addrmode3 := reg +/- reg +// addrmode3 := reg +/- imm8 +// +// The first operand is always a Reg. The second operand is a reg if in +// reg/reg form, otherwise it's reg#0. The third field encodes the operation +// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the +// index mode. + +/// getAM3Opc - This function encodes the addrmode3 opc field. +static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset, + unsigned IdxMode) +{ + bool isSub = Opc == ARM_AM_sub; + return ((int)isSub << 8) | Offset | (IdxMode << 9); +} + +static inline unsigned char getAM3Offset(unsigned AM3Opc) +{ + return AM3Opc & 0xFF; +} + +static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc) +{ + return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; +} + +static inline unsigned getAM3IdxMode(unsigned AM3Opc) +{ + return (AM3Opc >> 9); +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #4 +//===--------------------------------------------------------------------===// +// +// This is used for load / store multiple instructions. +// +// addrmode4 := reg, <mode> +// +// The four modes are: +// IA - Increment after +// IB - Increment before +// DA - Decrement after +// DB - Decrement before +// For VFP instructions, only the IA and DB modes are valid. + +static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode) +{ + return (ARM_AM_AMSubMode)(Mode & 0x7); +} + +static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode) +{ + return (int)SubMode; +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #5 +//===--------------------------------------------------------------------===// +// +// This is used for coprocessor instructions, such as FP load/stores. +// +// addrmode5 := reg +/- imm8*4 +// +// The first operand is always a Reg. The second operand encodes the +// operation in bit 8 and the immediate in bits 0-7. + +/// getAM5Opc - This function encodes the addrmode5 opc field. +static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset) +{ + bool isSub = Opc == ARM_AM_sub; + return ((int)isSub << 8) | Offset; +} +static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc) +{ + return AM5Opc & 0xFF; +} +static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc) +{ + return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #5 FP16 +//===--------------------------------------------------------------------===// +// +// This is used for coprocessor instructions, such as 16-bit FP load/stores. +// +// addrmode5fp16 := reg +/- imm8*2 +// +// The first operand is always a Reg. The second operand encodes the +// operation (add or subtract) in bit 8 and the immediate in bits 0-7. + +/// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field. +static inline unsigned getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset) +{ + bool isSub = Opc == ARM_AM_sub; + return ((int)isSub << 8) | Offset; +} + +static inline unsigned char getAM5FP16Offset(unsigned AM5Opc) +{ + return AM5Opc & 0xFF; +} + +static inline ARM_AM_AddrOpc getAM5FP16Op(unsigned AM5Opc) +{ + return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #6 +//===--------------------------------------------------------------------===// +// +// This is used for NEON load / store instructions. +// +// addrmode6 := reg with optional alignment +// +// This is stored in two operands [regaddr, align]. The first is the +// address register. The second operand is the value of the alignment +// specifier in bytes or zero if no explicit alignment. +// Valid alignments depend on the specific instruction. + +//===--------------------------------------------------------------------===// +// NEON Modified Immediates +//===--------------------------------------------------------------------===// +// +// Several NEON instructions (e.g., VMOV) take a "modified immediate" +// vector operand, where a small immediate encoded in the instruction +// specifies a full NEON vector value. These modified immediates are +// represented here as encoded integers. The low 8 bits hold the immediate +// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold +// the "Cmode" field of the instruction. The interfaces below treat the +// Op and Cmode values as a single 5-bit value. + +static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) +{ + return (OpCmode << 8) | Val; +} +static inline unsigned getNEONModImmOpCmode(unsigned ModImm) +{ + return (ModImm >> 8) & 0x1f; +} +static inline unsigned getNEONModImmVal(unsigned ModImm) +{ + return ModImm & 0xff; +} + +/// decodeNEONModImm - Decode a NEON modified immediate value into the +/// element value and the element size in bits. (If the element size is +/// smaller than the vector, it is splatted into all the elements.) +static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits) +{ + unsigned OpCmode = getNEONModImmOpCmode(ModImm); + unsigned Imm8 = getNEONModImmVal(ModImm); + uint64_t Val = 0; + unsigned ByteNum; + + if (OpCmode == 0xe) { + // 8-bit vector elements + Val = Imm8; + *EltBits = 8; + } else if ((OpCmode & 0xc) == 0x8) { + // 16-bit vector elements + ByteNum = (OpCmode & 0x6) >> 1; + Val = (uint64_t)Imm8 << (8 * ByteNum); + *EltBits = 16; + } else if ((OpCmode & 0x8) == 0) { + // 32-bit vector elements, zero with one byte set + ByteNum = (OpCmode & 0x6) >> 1; + Val = (uint64_t)Imm8 << (8 * ByteNum); + *EltBits = 32; + } else if ((OpCmode & 0xe) == 0xc) { + // 32-bit vector elements, one byte with low bits set + ByteNum = 1 + (OpCmode & 0x1); + Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); + *EltBits = 32; + } else if (OpCmode == 0x1e) { + // 64-bit vector elements + for (ByteNum = 0; ByteNum < 8; ++ByteNum) { + if ((ModImm >> ByteNum) & 1) + Val |= (uint64_t)0xff << (8 * ByteNum); + } + *EltBits = 64; + } else { + //llvm_unreachable("Unsupported NEON immediate"); + } + return Val; +} + +ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode); + +//===--------------------------------------------------------------------===// +// Floating-point Immediates +// +static inline float getFPImmFloat(unsigned Imm) +{ + // We expect an 8-bit binary encoding of a floating-point number here. + union { + uint32_t I; + float F; + } FPUnion; + + uint8_t Sign = (Imm >> 7) & 0x1; + uint8_t Exp = (Imm >> 4) & 0x7; + uint8_t Mantissa = Imm & 0xf; + + // 8-bit FP iEEEE Float Encoding + // abcd efgh aBbbbbbc defgh000 00000000 00000000 + // + // where B = NOT(b); + + FPUnion.I = 0; + FPUnion.I |= ((uint32_t) Sign) << 31; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; + FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; + FPUnion.I |= (Exp & 0x3) << 23; + FPUnion.I |= Mantissa << 19; + return FPUnion.F; +} + +#endif + diff --git a/capstone/arch/ARM/ARMBaseInfo.h b/capstone/arch/ARM/ARMBaseInfo.h new file mode 100644 index 000000000..b7279569f --- /dev/null +++ b/capstone/arch/ARM/ARMBaseInfo.h @@ -0,0 +1,486 @@ +//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone helper functions and enum definitions for +// the ARM target useful for the compiler back-end and the MC libraries. +// As such, it deliberately does not include references to LLVM core +// code gen types, passes, etc.. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +#ifndef CS_ARMBASEINFO_H +#define CS_ARMBASEINFO_H + +#include "capstone/arm.h" + +// Defines symbolic names for ARM registers. This defines a mapping from +// register name to register number. +// +#define GET_REGINFO_ENUM +#include "ARMGenRegisterInfo.inc" + +// Enums corresponding to ARM condition codes +// The CondCodes constants map directly to the 4-bit encoding of the +// condition field for predicated instructions. +typedef enum ARMCC_CondCodes { // Meaning (integer) Meaning (floating-point) + ARMCC_EQ, // Equal Equal + ARMCC_NE, // Not equal Not equal, or unordered + ARMCC_HS, // Carry set >, ==, or unordered + ARMCC_LO, // Carry clear Less than + ARMCC_MI, // Minus, negative Less than + ARMCC_PL, // Plus, positive or zero >, ==, or unordered + ARMCC_VS, // Overflow Unordered + ARMCC_VC, // No overflow Not unordered + ARMCC_HI, // Unsigned higher Greater than, or unordered + ARMCC_LS, // Unsigned lower or same Less than or equal + ARMCC_GE, // Greater than or equal Greater than or equal + ARMCC_LT, // Less than Less than, or unordered + ARMCC_GT, // Greater than Greater than + ARMCC_LE, // Less than or equal <, ==, or unordered + ARMCC_AL // Always (unconditional) Always (unconditional) +} ARMCC_CondCodes; + +inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC) +{ + switch (CC) { + case ARMCC_EQ: return ARMCC_NE; + case ARMCC_NE: return ARMCC_EQ; + case ARMCC_HS: return ARMCC_LO; + case ARMCC_LO: return ARMCC_HS; + case ARMCC_MI: return ARMCC_PL; + case ARMCC_PL: return ARMCC_MI; + case ARMCC_VS: return ARMCC_VC; + case ARMCC_VC: return ARMCC_VS; + case ARMCC_HI: return ARMCC_LS; + case ARMCC_LS: return ARMCC_HI; + case ARMCC_GE: return ARMCC_LT; + case ARMCC_LT: return ARMCC_GE; + case ARMCC_GT: return ARMCC_LE; + case ARMCC_LE: return ARMCC_GT; + default: return ARMCC_AL; + } +} + +inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC) +{ + switch (CC) { + case ARMCC_EQ: return "eq"; + case ARMCC_NE: return "ne"; + case ARMCC_HS: return "hs"; + case ARMCC_LO: return "lo"; + case ARMCC_MI: return "mi"; + case ARMCC_PL: return "pl"; + case ARMCC_VS: return "vs"; + case ARMCC_VC: return "vc"; + case ARMCC_HI: return "hi"; + case ARMCC_LS: return "ls"; + case ARMCC_GE: return "ge"; + case ARMCC_LT: return "lt"; + case ARMCC_GT: return "gt"; + case ARMCC_LE: return "le"; + case ARMCC_AL: return "al"; + default: return ""; + } +} + +inline static const char *ARM_PROC_IFlagsToString(unsigned val) +{ + switch (val) { + case ARM_CPSFLAG_F: return "f"; + case ARM_CPSFLAG_I: return "i"; + case ARM_CPSFLAG_A: return "a"; + default: return ""; + } +} + +inline static const char *ARM_PROC_IModToString(unsigned val) +{ + switch (val) { + case ARM_CPSMODE_IE: return "ie"; + case ARM_CPSMODE_ID: return "id"; + default: return ""; + } +} + +inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8) +{ + // TODO: add details + switch (val + 1) { + default: return "BUGBUG"; + case ARM_MB_SY: return "sy"; + case ARM_MB_ST: return "st"; + case ARM_MB_LD: return HasV8 ? "ld" : "#0xd"; + case ARM_MB_RESERVED_12: return "#0xc"; + case ARM_MB_ISH: return "ish"; + case ARM_MB_ISHST: return "ishst"; + case ARM_MB_ISHLD: return HasV8 ? "ishld" : "#9"; + case ARM_MB_RESERVED_8: return "#8"; + case ARM_MB_NSH: return "nsh"; + case ARM_MB_NSHST: return "nshst"; + case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#5"; + case ARM_MB_RESERVED_4: return "#4"; + case ARM_MB_OSH: return "osh"; + case ARM_MB_OSHST: return "oshst"; + case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#1"; + case ARM_MB_RESERVED_0: return "#0"; + } +} + +enum ARM_ISB_InstSyncBOpt { + ARM_ISB_RESERVED_0 = 0, + ARM_ISB_RESERVED_1 = 1, + ARM_ISB_RESERVED_2 = 2, + ARM_ISB_RESERVED_3 = 3, + ARM_ISB_RESERVED_4 = 4, + ARM_ISB_RESERVED_5 = 5, + ARM_ISB_RESERVED_6 = 6, + ARM_ISB_RESERVED_7 = 7, + ARM_ISB_RESERVED_8 = 8, + ARM_ISB_RESERVED_9 = 9, + ARM_ISB_RESERVED_10 = 10, + ARM_ISB_RESERVED_11 = 11, + ARM_ISB_RESERVED_12 = 12, + ARM_ISB_RESERVED_13 = 13, + ARM_ISB_RESERVED_14 = 14, + ARM_ISB_SY = 15 +}; + +inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val) +{ + switch (val) { + default: // never reach + case ARM_ISB_RESERVED_0: return "#0x0"; + case ARM_ISB_RESERVED_1: return "#0x1"; + case ARM_ISB_RESERVED_2: return "#0x2"; + case ARM_ISB_RESERVED_3: return "#0x3"; + case ARM_ISB_RESERVED_4: return "#0x4"; + case ARM_ISB_RESERVED_5: return "#0x5"; + case ARM_ISB_RESERVED_6: return "#0x6"; + case ARM_ISB_RESERVED_7: return "#0x7"; + case ARM_ISB_RESERVED_8: return "#0x8"; + case ARM_ISB_RESERVED_9: return "#0x9"; + case ARM_ISB_RESERVED_10: return "#0xa"; + case ARM_ISB_RESERVED_11: return "#0xb"; + case ARM_ISB_RESERVED_12: return "#0xc"; + case ARM_ISB_RESERVED_13: return "#0xd"; + case ARM_ISB_RESERVED_14: return "#0xe"; + case ARM_ISB_SY: return "sy"; + } +} + +/// isARMLowRegister - Returns true if the register is a low register (r0-r7). +/// +static inline bool isARMLowRegister(unsigned Reg) +{ + //using namespace ARM; + switch (Reg) { + case ARM_R0: case ARM_R1: case ARM_R2: case ARM_R3: + case ARM_R4: case ARM_R5: case ARM_R6: case ARM_R7: + return true; + default: + return false; + } +} + +/// ARMII - This namespace holds all of the target specific flags that +/// instruction info tracks. +/// +/// ARM Index Modes +enum ARMII_IndexMode { + ARMII_IndexModeNone = 0, + ARMII_IndexModePre = 1, + ARMII_IndexModePost = 2, + ARMII_IndexModeUpd = 3 +}; + +/// ARM Addressing Modes +typedef enum ARMII_AddrMode { + ARMII_AddrModeNone = 0, + ARMII_AddrMode1 = 1, + ARMII_AddrMode2 = 2, + ARMII_AddrMode3 = 3, + ARMII_AddrMode4 = 4, + ARMII_AddrMode5 = 5, + ARMII_AddrMode6 = 6, + ARMII_AddrModeT1_1 = 7, + ARMII_AddrModeT1_2 = 8, + ARMII_AddrModeT1_4 = 9, + ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data + ARMII_AddrModeT2_i12 = 11, + ARMII_AddrModeT2_i8 = 12, + ARMII_AddrModeT2_so = 13, + ARMII_AddrModeT2_pc = 14, // +/- i12 for pc relative data + ARMII_AddrModeT2_i8s4 = 15, // i8 * 4 + ARMII_AddrMode_i12 = 16 +} ARMII_AddrMode; + +inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode) +{ + switch (addrmode) { + case ARMII_AddrModeNone: return "AddrModeNone"; + case ARMII_AddrMode1: return "AddrMode1"; + case ARMII_AddrMode2: return "AddrMode2"; + case ARMII_AddrMode3: return "AddrMode3"; + case ARMII_AddrMode4: return "AddrMode4"; + case ARMII_AddrMode5: return "AddrMode5"; + case ARMII_AddrMode6: return "AddrMode6"; + case ARMII_AddrModeT1_1: return "AddrModeT1_1"; + case ARMII_AddrModeT1_2: return "AddrModeT1_2"; + case ARMII_AddrModeT1_4: return "AddrModeT1_4"; + case ARMII_AddrModeT1_s: return "AddrModeT1_s"; + case ARMII_AddrModeT2_i12: return "AddrModeT2_i12"; + case ARMII_AddrModeT2_i8: return "AddrModeT2_i8"; + case ARMII_AddrModeT2_so: return "AddrModeT2_so"; + case ARMII_AddrModeT2_pc: return "AddrModeT2_pc"; + case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4"; + case ARMII_AddrMode_i12: return "AddrMode_i12"; + } +} + +/// Target Operand Flag enum. +enum ARMII_TOF { + //===------------------------------------------------------------------===// + // ARM Specific MachineOperand flags. + + ARMII_MO_NO_FLAG, + + /// MO_LO16 - On a symbol operand, this represents a relocation containing + /// lower 16 bit of the address. Used only via movw instruction. + ARMII_MO_LO16, + + /// MO_HI16 - On a symbol operand, this represents a relocation containing + /// higher 16 bit of the address. Used only via movt instruction. + ARMII_MO_HI16, + + /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a + /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, + /// i.e. "FOO$non_lazy_ptr". + /// Used only via movw instruction. + ARMII_MO_LO16_NONLAZY, + + /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a + /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, + /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction. + ARMII_MO_HI16_NONLAZY, + + /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a + /// relocation containing lower 16 bit of the PC relative address of the + /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". + /// Used only via movw instruction. + ARMII_MO_LO16_NONLAZY_PIC, + + /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a + /// relocation containing lower 16 bit of the PC relative address of the + /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". + /// Used only via movt instruction. + ARMII_MO_HI16_NONLAZY_PIC, + + /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a + /// call operand. + ARMII_MO_PLT +}; + +enum { + //===------------------------------------------------------------------===// + // Instruction Flags. + + //===------------------------------------------------------------------===// + // This four-bit field describes the addressing mode used. + ARMII_AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h + + // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load + // and store ops only. Generic "updating" flag is used for ld/st multiple. + // The index mode enums are declared in ARMBaseInfo.h + ARMII_IndexModeShift = 5, + ARMII_IndexModeMask = 3 << ARMII_IndexModeShift, + + //===------------------------------------------------------------------===// + // Instruction encoding formats. + // + ARMII_FormShift = 7, + ARMII_FormMask = 0x3f << ARMII_FormShift, + + // Pseudo instructions + ARMII_Pseudo = 0 << ARMII_FormShift, + + // Multiply instructions + ARMII_MulFrm = 1 << ARMII_FormShift, + + // Branch instructions + ARMII_BrFrm = 2 << ARMII_FormShift, + ARMII_BrMiscFrm = 3 << ARMII_FormShift, + + // Data Processing instructions + ARMII_DPFrm = 4 << ARMII_FormShift, + ARMII_DPSoRegFrm = 5 << ARMII_FormShift, + + // Load and Store + ARMII_LdFrm = 6 << ARMII_FormShift, + ARMII_StFrm = 7 << ARMII_FormShift, + ARMII_LdMiscFrm = 8 << ARMII_FormShift, + ARMII_StMiscFrm = 9 << ARMII_FormShift, + ARMII_LdStMulFrm = 10 << ARMII_FormShift, + + ARMII_LdStExFrm = 11 << ARMII_FormShift, + + // Miscellaneous arithmetic instructions + ARMII_ArithMiscFrm = 12 << ARMII_FormShift, + ARMII_SatFrm = 13 << ARMII_FormShift, + + // Extend instructions + ARMII_ExtFrm = 14 << ARMII_FormShift, + + // VFP formats + ARMII_VFPUnaryFrm = 15 << ARMII_FormShift, + ARMII_VFPBinaryFrm = 16 << ARMII_FormShift, + ARMII_VFPConv1Frm = 17 << ARMII_FormShift, + ARMII_VFPConv2Frm = 18 << ARMII_FormShift, + ARMII_VFPConv3Frm = 19 << ARMII_FormShift, + ARMII_VFPConv4Frm = 20 << ARMII_FormShift, + ARMII_VFPConv5Frm = 21 << ARMII_FormShift, + ARMII_VFPLdStFrm = 22 << ARMII_FormShift, + ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift, + ARMII_VFPMiscFrm = 24 << ARMII_FormShift, + + // Thumb format + ARMII_ThumbFrm = 25 << ARMII_FormShift, + + // Miscelleaneous format + ARMII_MiscFrm = 26 << ARMII_FormShift, + + // NEON formats + ARMII_NGetLnFrm = 27 << ARMII_FormShift, + ARMII_NSetLnFrm = 28 << ARMII_FormShift, + ARMII_NDupFrm = 29 << ARMII_FormShift, + ARMII_NLdStFrm = 30 << ARMII_FormShift, + ARMII_N1RegModImmFrm= 31 << ARMII_FormShift, + ARMII_N2RegFrm = 32 << ARMII_FormShift, + ARMII_NVCVTFrm = 33 << ARMII_FormShift, + ARMII_NVDupLnFrm = 34 << ARMII_FormShift, + ARMII_N2RegVShLFrm = 35 << ARMII_FormShift, + ARMII_N2RegVShRFrm = 36 << ARMII_FormShift, + ARMII_N3RegFrm = 37 << ARMII_FormShift, + ARMII_N3RegVShFrm = 38 << ARMII_FormShift, + ARMII_NVExtFrm = 39 << ARMII_FormShift, + ARMII_NVMulSLFrm = 40 << ARMII_FormShift, + ARMII_NVTBLFrm = 41 << ARMII_FormShift, + + //===------------------------------------------------------------------===// + // Misc flags. + + // UnaryDP - Indicates this is a unary data processing instruction, i.e. + // it doesn't have a Rn operand. + ARMII_UnaryDP = 1 << 13, + + // Xform16Bit - Indicates this Thumb2 instruction may be transformed into + // a 16-bit Thumb instruction if certain conditions are met. + ARMII_Xform16Bit = 1 << 14, + + // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb + // instruction. Used by the parser to determine whether to require the 'S' + // suffix on the mnemonic (when not in an IT block) or preclude it (when + // in an IT block). + ARMII_ThumbArithFlagSetting = 1 << 18, + + //===------------------------------------------------------------------===// + // Code domain. + ARMII_DomainShift = 15, + ARMII_DomainMask = 7 << ARMII_DomainShift, + ARMII_DomainGeneral = 0 << ARMII_DomainShift, + ARMII_DomainVFP = 1 << ARMII_DomainShift, + ARMII_DomainNEON = 2 << ARMII_DomainShift, + ARMII_DomainNEONA8 = 4 << ARMII_DomainShift, + + //===------------------------------------------------------------------===// + // Field shifts - such shifts are used to set field while generating + // machine instructions. + // + // FIXME: This list will need adjusting/fixing as the MC code emitter + // takes shape and the ARMCodeEmitter.cpp bits go away. + ARMII_ShiftTypeShift = 4, + + ARMII_M_BitShift = 5, + ARMII_ShiftImmShift = 5, + ARMII_ShiftShift = 7, + ARMII_N_BitShift = 7, + ARMII_ImmHiShift = 8, + ARMII_SoRotImmShift = 8, + ARMII_RegRsShift = 8, + ARMII_ExtRotImmShift = 10, + ARMII_RegRdLoShift = 12, + ARMII_RegRdShift = 12, + ARMII_RegRdHiShift = 16, + ARMII_RegRnShift = 16, + ARMII_S_BitShift = 20, + ARMII_W_BitShift = 21, + ARMII_AM3_I_BitShift = 22, + ARMII_D_BitShift = 22, + ARMII_U_BitShift = 23, + ARMII_P_BitShift = 24, + ARMII_I_BitShift = 25, + ARMII_CondShift = 28 +}; + +typedef struct MClassSysReg { + const char *Name; + arm_sysreg sysreg; + uint16_t M1Encoding12; + uint16_t M2M3Encoding8; + uint16_t Encoding; + int FeaturesRequired[2]; // 2 is enough for MClassSysRegsList +} MClassSysReg; + +enum TraceSyncBOpt { + CSYNC = 0 +}; + +const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding); +const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12); + +// returns APSR with _<bits> qualifier. +// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier +static inline const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) +{ + return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF)); +} + +static inline const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) +{ + return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF)); +} + +// returns true if TestFeatures are all present in FeaturesRequired +static inline bool MClassSysReg_isInRequiredFeatures(const MClassSysReg *TheReg, int TestFeatures) +{ + return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures); +} + +// lookup system register using 12-bit SYSm value. +// Note: the search is uniqued using M1 mask +static inline const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) +{ + return lookupMClassSysRegByM1Encoding12(SYSm); +} + +static inline const char *ARM_TSB_TraceSyncBOptToString(unsigned val) +{ + switch (val) { + default: + // llvm_unreachable("Unknown trace synchronization barrier operation"); + return NULL; + + case CSYNC: + return "csync"; + } +} + +#endif diff --git a/capstone/arch/ARM/ARMDisassembler.c b/capstone/arch/ARM/ARMDisassembler.c new file mode 100644 index 000000000..b2e5723af --- /dev/null +++ b/capstone/arch/ARM/ARMDisassembler.c @@ -0,0 +1,5764 @@ +//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +#ifdef CAPSTONE_HAS_ARM + +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <capstone/platform.h> + +#include "ARMAddressingModes.h" +#include "ARMBaseInfo.h" +#include "../../MCFixedLenDisassembler.h" +#include "../../MCInst.h" +#include "../../MCInstrDesc.h" +#include "../../MCRegisterInfo.h" +#include "../../LEB128.h" +#include "../../MCDisassembler.h" +#include "../../cs_priv.h" +#include "../../utils.h" + +#include "ARMDisassembler.h" +#include "ARMMapping.h" + +#define GET_SUBTARGETINFO_ENUM +#include "ARMGenSubtargetInfo.inc" + +#define GET_INSTRINFO_MC_DESC +#include "ARMGenInstrInfo.inc" + +#define GET_INSTRINFO_ENUM +#include "ARMGenInstrInfo.inc" + +static bool ITStatus_push_back(ARM_ITStatus *it, char v) +{ + if (it->size >= sizeof(it->ITStates)) { + // TODO: consider warning user. + it->size = 0; + } + it->ITStates[it->size] = v; + it->size++; + + return true; +} + +// Returns true if the current instruction is in an IT block +static bool ITStatus_instrInITBlock(ARM_ITStatus *it) +{ + //return !ITStates.empty(); + return (it->size > 0); +} + +// Returns true if current instruction is the last instruction in an IT block +static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it) +{ + return (it->size == 1); +} + +// Handles the condition code status of instructions in IT blocks + +// Returns the condition code for instruction in IT block +static unsigned ITStatus_getITCC(ARM_ITStatus *it) +{ + unsigned CC = ARMCC_AL; + + if (ITStatus_instrInITBlock(it)) + //CC = ITStates.back(); + CC = it->ITStates[it->size-1]; + + return CC; +} + +// Advances the IT block state to the next T or E +static void ITStatus_advanceITState(ARM_ITStatus *it) +{ + //ITStates.pop_back(); + it->size--; +} + +// Called when decoding an IT instruction. Sets the IT state for the following +// instructions that for the IT block. Firstcond and Mask correspond to the +// fields in the IT instruction encoding. +static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask) +{ + // (3 - the number of trailing zeros) is the number of then / else. + unsigned CondBit0 = Firstcond & 1; + unsigned NumTZ = CountTrailingZeros_32(Mask); + unsigned char CCBits = (unsigned char)Firstcond & 0xf; + unsigned Pos; + + //assert(NumTZ <= 3 && "Invalid IT mask!"); + // push condition codes onto the stack the correct order for the pops + for (Pos = NumTZ + 1; Pos <= 3; ++Pos) { + bool T = ((Mask >> Pos) & 1) == (int)CondBit0; + + if (T) + ITStatus_push_back(it, CCBits); + else + ITStatus_push_back(it, CCBits ^ 1); + } + + ITStatus_push_back(it, CCBits); +} + +/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. + +static bool Check(DecodeStatus *Out, DecodeStatus In) +{ + switch (In) { + case MCDisassembler_Success: + // Out stays the same. + return true; + case MCDisassembler_SoftFail: + *Out = In; + return true; + case MCDisassembler_Fail: + *Out = In; + return false; + default: // never reached + return false; + } +} + +// Forward declare these because the autogenerated code will reference them. +// Definitions are further down. +static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, + unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst, + unsigned Insn, uint64_t Adddress, const void *Decoder); +static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, + uint64_t Address, const void* Decoder); +static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, + uint64_t Address, const void* Decoder); +static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, + uint64_t Address, const void* Decoder); +static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, + uint64_t Address, const void* Decoder); +static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); + +// Hacky: enable all features for disassembler +bool ARM_getFeatureBits(unsigned int mode, unsigned int feature) +{ + if ((mode & CS_MODE_V8) == 0) { + // not V8 mode + if (feature == ARM_HasV8Ops || feature == ARM_HasV8_1aOps || + feature == ARM_HasV8_4aOps || feature == ARM_HasV8_3aOps) + // HasV8MBaselineOps + return false; + } else { + if (feature == ARM_FeatureVFPOnlySP) + return false; + } + + if ((mode & CS_MODE_MCLASS) == 0) { + if (feature == ARM_FeatureMClass) + return false; + } + + if ((mode & CS_MODE_THUMB) == 0) { + // not Thumb + if (feature == ARM_FeatureThumb2 || feature == ARM_ModeThumb) + return false; + // FIXME: what mode enables D16? + if (feature == ARM_FeatureD16) + return false; + } else { + // Thumb + if (feature == ARM_FeatureD16) + return false; + } + + if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0) + return false; + + // we support everything + return true; +} + +#include "ARMGenDisassemblerTables.inc" + +static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (Val == 0xF) return MCDisassembler_Fail; + + // AL predicate is not allowed on Thumb1 branches. + if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Val); + + if (Val == ARMCC_AL) { + MCOperand_CreateReg0(Inst, 0); + } else + MCOperand_CreateReg0(Inst, ARM_CPSR); + + return MCDisassembler_Success; +} + +#define GET_REGINFO_MC_DESC +#include "ARMGenRegisterInfo.inc" +void ARM_init(MCRegisterInfo *MRI) +{ + /* + InitMCRegisterInfo(ARMRegDesc, 289, + RA, PC, + ARMMCRegisterClasses, 103, + ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings, + ARMSubRegIdxLists, 57, + ARMSubRegIdxRanges, ARMRegEncodingTable); + */ + + MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289, + 0, 0, + ARMMCRegisterClasses, 103, + 0, 0, ARMRegDiffLists, 0, + ARMSubRegIdxLists, 57, + 0); +} + +// Post-decoding checks +static DecodeStatus checkDecodedInstruction(MCInst *MI, + uint32_t Insn, + DecodeStatus Result) +{ + switch (MCInst_getOpcode(MI)) { + case ARM_HVC: { + // HVC is undefined if condition = 0xf otherwise upredictable + // if condition != 0xe + uint32_t Cond = (Insn >> 28) & 0xF; + + if (Cond == 0xF) + return MCDisassembler_Fail; + + if (Cond != 0xE) + return MCDisassembler_SoftFail; + + return Result; + } + default: + return Result; + } +} + +static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, + uint16_t *Size, uint64_t Address) +{ + uint32_t insn; + DecodeStatus result; + + *Size = 0; + + if (code_len < 4) + // not enough data + return MCDisassembler_Fail; + + if (MI->flat_insn->detail) { + unsigned int i; + + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm) + sizeof(cs_arm)); + + for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { + MI->flat_insn->detail->arm.operands[i].vector_index = -1; + MI->flat_insn->detail->arm.operands[i].neon_lane = -1; + } + } + + if (MODE_IS_BIG_ENDIAN(ud->mode)) + insn = (code[3] << 0) | (code[2] << 8) | + (code[1] << 16) | ((uint32_t) code[0] << 24); + else + insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | + (code[1] << 8) | (code[0] << 0); + + // Calling the auto-generated decoder function. + result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address); + if (result != MCDisassembler_Fail) { + result = checkDecodedInstruction(MI, insn, result); + if (result != MCDisassembler_Fail) + *Size = 4; + + return result; + } + + // VFP and NEON instructions, similarly, are shared between ARM + // and Thumb modes. + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + // Add a fake predicate operand, because we share these instruction + // definitions with Thumb2 where these instructions are predicable. + if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) + return MCDisassembler_Fail; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + // Add a fake predicate operand, because we share these instruction + // definitions with Thumb2 where these instructions are predicable. + if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) + return MCDisassembler_Fail; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + // Add a fake predicate operand, because we share these instruction + // definitions with Thumb2 where these instructions are predicable. + if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) + return MCDisassembler_Fail; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + result = decodeInstruction_4(DecoderTableCoProc32, MI, insn, Address); + if (result != MCDisassembler_Fail) { + result = checkDecodedInstruction(MI, insn, result); + if (result != MCDisassembler_Fail) + *Size = 4; + + return result; + } + + MCInst_clear(MI); + *Size = 0; + return MCDisassembler_Fail; +} + +// Thumb1 instructions don't have explicit S bits. Rather, they +// implicitly set CPSR. Since it's not represented in the encoding, the +// auto-generated decoder won't inject the CPSR operand. We need to fix +// that as a post-pass. +static void AddThumb1SBit(MCInst *MI, bool InITBlock) +{ + const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; + unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; + unsigned i; + + for (i = 0; i < NumOps; ++i) { + if (i == MCInst_getNumOperands(MI)) break; + + if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) { + if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i - 1])) continue; + MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); + return; + } + } + + //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR)); + MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); +} + +// Most Thumb instructions don't have explicit predicates in the +// encoding, but rather get their predicates from IT context. We need +// to fix up the predicate operands using this context information as a +// post-pass. +static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) +{ + DecodeStatus S = MCDisassembler_Success; + const MCOperandInfo *OpInfo; + unsigned short NumOps; + unsigned int i; + unsigned CC; + + // A few instructions actually have predicates encoded in them. Don't + // try to overwrite it if we're seeing one of those. + switch (MCInst_getOpcode(MI)) { + case ARM_tBcc: + case ARM_t2Bcc: + case ARM_tCBZ: + case ARM_tCBNZ: + case ARM_tCPS: + case ARM_t2CPS3p: + case ARM_t2CPS2p: + case ARM_t2CPS1p: + case ARM_tMOVSr: + case ARM_tSETEND: + // Some instructions (mostly conditional branches) are not + // allowed in IT blocks. + if (ITStatus_instrInITBlock(&(ud->ITBlock))) + S = MCDisassembler_SoftFail; + else + return MCDisassembler_Success; + break; + + case ARM_t2HINT: + if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0x10) + S = MCDisassembler_SoftFail; + break; + + case ARM_tB: + case ARM_t2B: + case ARM_t2TBB: + case ARM_t2TBH: + // Some instructions (mostly unconditional branches) can + // only appears at the end of, or outside of, an IT. + // if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) + if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock))) + S = MCDisassembler_SoftFail; + break; + default: + break; + } + + // If we're in an IT block, base the predicate on that. Otherwise, + // assume a predicate of AL. + CC = ITStatus_getITCC(&(ud->ITBlock)); + if (CC == 0xF) + CC = ARMCC_AL; + + if (ITStatus_instrInITBlock(&(ud->ITBlock))) + ITStatus_advanceITState(&(ud->ITBlock)); + + OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; + NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; + + for (i = 0; i < NumOps; ++i) { + if (i == MCInst_getNumOperands(MI)) break; + + if (MCOperandInfo_isPredicate(&OpInfo[i])) { + MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); + + if (CC == ARMCC_AL) + MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); + else + MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); + + return S; + } + } + + MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); + + if (CC == ARMCC_AL) + MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, 0)); + else + MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, ARM_CPSR)); + + return S; +} + +// Thumb VFP instructions are a special case. Because we share their +// encodings between ARM and Thumb modes, and they are predicable in ARM +// mode, the auto-generated decoder will give them an (incorrect) +// predicate operand. We need to rewrite these operands based on the IT +// context as a post-pass. +static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI) +{ + unsigned CC; + unsigned short NumOps; + const MCOperandInfo *OpInfo; + unsigned i; + + CC = ITStatus_getITCC(&(ud->ITBlock)); + if (ITStatus_instrInITBlock(&(ud->ITBlock))) + ITStatus_advanceITState(&(ud->ITBlock)); + + OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; + NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; + + for (i = 0; i < NumOps; ++i) { + if (MCOperandInfo_isPredicate(&OpInfo[i])) { + MCOperand_setImm(MCInst_getOperand(MI, i), CC); + + if (CC == ARMCC_AL) + MCOperand_setReg(MCInst_getOperand(MI, i + 1), 0); + else + MCOperand_setReg(MCInst_getOperand(MI, i + 1), ARM_CPSR); + + return; + } + } +} + +static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, + uint16_t *Size, uint64_t Address) +{ + uint16_t insn16; + DecodeStatus result; + bool InITBlock; + unsigned Firstcond, Mask; + uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn; + size_t i; + + // We want to read exactly 2 bytes of data. + if (code_len < 2) + // not enough data + return MCDisassembler_Fail; + + if (MI->flat_insn->detail) { + memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm)); + for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { + MI->flat_insn->detail->arm.operands[i].vector_index = -1; + MI->flat_insn->detail->arm.operands[i].neon_lane = -1; + } + } + + if (MODE_IS_BIG_ENDIAN(ud->mode)) + insn16 = (code[0] << 8) | code[1]; + else + insn16 = (code[1] << 8) | code[0]; + + result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address); + if (result != MCDisassembler_Fail) { + *Size = 2; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address); + if (result) { + *Size = 2; + InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); + Check(&result, AddThumbPredicate(ud, MI)); + AddThumb1SBit(MI, InITBlock); + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address); + if (result != MCDisassembler_Fail) { + *Size = 2; + + // Nested IT blocks are UNPREDICTABLE. Must be checked before we add + // the Thumb predicate. + if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock))) + return MCDisassembler_SoftFail; + + Check(&result, AddThumbPredicate(ud, MI)); + + // If we find an IT instruction, we need to parse its condition + // code and mask operands so that we can apply them correctly + // to the subsequent instructions. + if (MCInst_getOpcode(MI) == ARM_t2IT) { + Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0)); + Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1)); + ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask); + + // An IT instruction that would give a 'NV' predicate is unpredictable. + // if (Firstcond == ARMCC_AL && !isPowerOf2_32(Mask)) + // CS << "unpredictable IT predicate sequence"; + } + + return result; + } + + // We want to read exactly 4 bytes of data. + if (code_len < 4) + // not enough data + return MCDisassembler_Fail; + + if (MODE_IS_BIG_ENDIAN(ud->mode)) + insn32 = (code[3] << 0) | (code[2] << 8) | + (code[1] << 16) | ((uint32_t) code[0] << 24); + else + insn32 = (code[3] << 8) | (code[2] << 0) | + ((uint32_t) code[1] << 24) | (code[0] << 16); + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); + Check(&result, AddThumbPredicate(ud, MI)); + AddThumb1SBit(MI, InITBlock); + + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + + if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + UpdateThumbVFPPredicate(ud, MI); + return result; + } + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + } + + if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) { + MCInst_clear(MI); + NEONLdStInsn = insn32; + NEONLdStInsn &= 0xF0FFFFFF; + NEONLdStInsn |= 0x04000000; + result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + } + + if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) { + MCInst_clear(MI); + NEONDataInsn = insn32; + NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 + NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 + NEONDataInsn |= 0x12000000; // Set bits 28 and 25 + result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + } + + MCInst_clear(MI); + NEONCryptoInsn = insn32; + NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 + NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 + NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 + result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + NEONv8Insn = insn32; + NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 + result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + return result; + } + + MCInst_clear(MI); + result = decodeInstruction_4(DecoderTableThumb2CoProc32, MI, insn32, Address); + if (result != MCDisassembler_Fail) { + *Size = 4; + Check(&result, AddThumbPredicate(ud, MI)); + return result; + } + + MCInst_clear(MI); + *Size = 0; + + return MCDisassembler_Fail; +} + +bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, + uint16_t *size, uint64_t address, void *info) +{ + DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); + + // TODO: fix table gen to eliminate these special cases + if (instr->Opcode == ARM_t__brkdiv0) + return false; + + //return status == MCDisassembler_Success; + return status != MCDisassembler_Fail; +} + +bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, + uint16_t *size, uint64_t address, void *info) +{ + DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); + + //return status == MCDisassembler_Success; + return status != MCDisassembler_Fail; +} + +static const uint16_t GPRDecoderTable[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, + ARM_R4, ARM_R5, ARM_R6, ARM_R7, + ARM_R8, ARM_R9, ARM_R10, ARM_R11, + ARM_R12, ARM_SP, ARM_LR, ARM_PC +}; + +static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Register; + + if (RegNo > 15) + return MCDisassembler_Fail; + + Register = GPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (RegNo == 15) + S = MCDisassembler_SoftFail; + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + + return S; +} + +static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (RegNo == 15) { + MCOperand_CreateReg0(Inst, ARM_APSR_NZCV); + + return MCDisassembler_Success; + } + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + return S; +} + +static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + if (RegNo > 7) + return MCDisassembler_Fail; + + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static const uint16_t GPRPairDecoderTable[] = { + ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, + ARM_R8_R9, ARM_R10_R11, ARM_R12_SP +}; + +static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned RegisterPair; + DecodeStatus S = MCDisassembler_Success; + + if (RegNo > 13) + return MCDisassembler_Fail; + + if ((RegNo & 1) || RegNo == 0xe) + S = MCDisassembler_SoftFail; + + RegisterPair = GPRPairDecoderTable[RegNo / 2]; + MCOperand_CreateReg0(Inst, RegisterPair); + + return S; +} + +static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Register = 0; + + switch (RegNo) { + case 0: + Register = ARM_R0; + break; + case 1: + Register = ARM_R1; + break; + case 2: + Register = ARM_R2; + break; + case 3: + Register = ARM_R3; + break; + case 9: + Register = ARM_R9; + break; + case 12: + Register = ARM_R12; + break; + default: + return MCDisassembler_Fail; + } + + MCOperand_CreateReg0(Inst, Register); + + return MCDisassembler_Success; +} + +static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if ((RegNo == 13 && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) || RegNo == 15) + S = MCDisassembler_SoftFail; + + Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + + return S; +} + +static const uint16_t SPRDecoderTable[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, + ARM_S4, ARM_S5, ARM_S6, ARM_S7, + ARM_S8, ARM_S9, ARM_S10, ARM_S11, + ARM_S12, ARM_S13, ARM_S14, ARM_S15, + ARM_S16, ARM_S17, ARM_S18, ARM_S19, + ARM_S20, ARM_S21, ARM_S22, ARM_S23, + ARM_S24, ARM_S25, ARM_S26, ARM_S27, + ARM_S28, ARM_S29, ARM_S30, ARM_S31 +}; + +static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31) + return MCDisassembler_Fail; + + Register = SPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static const uint16_t DPRDecoderTable[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, + ARM_D4, ARM_D5, ARM_D6, ARM_D7, + ARM_D8, ARM_D9, ARM_D10, ARM_D11, + ARM_D12, ARM_D13, ARM_D14, ARM_D15, + ARM_D16, ARM_D17, ARM_D18, ARM_D19, + ARM_D20, ARM_D21, ARM_D22, ARM_D23, + ARM_D24, ARM_D25, ARM_D26, ARM_D27, + ARM_D28, ARM_D29, ARM_D30, ARM_D31 +}; + +static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31 || (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureD16) && RegNo > 15)) + return MCDisassembler_Fail; + + Register = DPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + if (RegNo > 7) + return MCDisassembler_Fail; + + return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + if (RegNo > 15) + return MCDisassembler_Fail; + + return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); +} + +static const uint16_t QPRDecoderTable[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, + ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, + ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, + ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15 +}; + +static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Register; + + if (RegNo > 31 || (RegNo & 1) != 0) + return MCDisassembler_Fail; + + RegNo >>= 1; + + Register = QPRDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + + return MCDisassembler_Success; +} + +static const uint16_t DPairDecoderTable[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, + ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, + ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, + ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, + ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, + ARM_Q15 +}; + +static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) +{ + unsigned Register; + + if (RegNo > 30) + return MCDisassembler_Fail; + + Register = DPairDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + + return MCDisassembler_Success; +} + +static const uint16_t DPairSpacedDecoderTable[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, + ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, + ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, + ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, + ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, + ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, + ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, + ARM_D28_D30, ARM_D29_D31 +}; + +static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, + unsigned RegNo, uint64_t Address, const void *Decoder) +{ + unsigned Register; + + if (RegNo > 29) + return MCDisassembler_Fail; + + Register = DPairSpacedDecoderTable[RegNo]; + MCOperand_CreateReg0(Inst, Register); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (Val) + MCOperand_CreateReg0(Inst, ARM_CPSR); + else + MCOperand_CreateReg0(Inst, 0); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + ARM_AM_ShiftOpc Shift; + unsigned Op; + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned type = fieldFromInstruction_4(Val, 5, 2); + unsigned imm = fieldFromInstruction_4(Val, 7, 5); + + // Register-immediate + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + Shift = ARM_AM_lsl; + switch (type) { + case 0: + Shift = ARM_AM_lsl; + break; + case 1: + Shift = ARM_AM_lsr; + break; + case 2: + Shift = ARM_AM_asr; + break; + case 3: + Shift = ARM_AM_ror; + break; + } + + if (Shift == ARM_AM_ror && imm == 0) + Shift = ARM_AM_rrx; + + Op = Shift | (imm << 3); + MCOperand_CreateImm0(Inst, Op); + + return S; +} + +static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + ARM_AM_ShiftOpc Shift; + + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned type = fieldFromInstruction_4(Val, 5, 2); + unsigned Rs = fieldFromInstruction_4(Val, 8, 4); + + // Register-register + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) + return MCDisassembler_Fail; + + Shift = ARM_AM_lsl; + switch (type) { + case 0: + Shift = ARM_AM_lsl; + break; + case 1: + Shift = ARM_AM_lsr; + break; + case 2: + Shift = ARM_AM_asr; + break; + case 3: + Shift = ARM_AM_ror; + break; + } + + MCOperand_CreateImm0(Inst, Shift); + + return S; +} + +static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + unsigned i; + DecodeStatus S = MCDisassembler_Success; + unsigned opcode; + bool NeedDisjointWriteback = false; + unsigned WritebackReg = 0; + + opcode = MCInst_getOpcode(Inst); + switch (opcode) { + default: + break; + + case ARM_LDMIA_UPD: + case ARM_LDMDB_UPD: + case ARM_LDMIB_UPD: + case ARM_LDMDA_UPD: + case ARM_t2LDMIA_UPD: + case ARM_t2LDMDB_UPD: + case ARM_t2STMIA_UPD: + case ARM_t2STMDB_UPD: + NeedDisjointWriteback = true; + WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0)); + break; + } + + // Empty register lists are not allowed. + if (Val == 0) return MCDisassembler_Fail; + + for (i = 0; i < 16; ++i) { + if (Val & (1 << i)) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) + return MCDisassembler_Fail; + + // Writeback not allowed if Rn is in the target list. + if (NeedDisjointWriteback && WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size - 1]))) + Check(&S, MCDisassembler_SoftFail); + } + } + + return S; +} + +static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned i; + unsigned Vd = fieldFromInstruction_4(Val, 8, 5); + unsigned regs = fieldFromInstruction_4(Val, 0, 8); + + // In case of unpredictable encoding, tweak the operands. + if (regs == 0 || (Vd + regs) > 32) { + regs = Vd + regs > 32 ? 32 - Vd : regs; + regs = (1u > regs? 1u : regs); + S = MCDisassembler_SoftFail; + } + + if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + + for (i = 0; i < (regs - 1); ++i) { + if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned i; + unsigned Vd = fieldFromInstruction_4(Val, 8, 5); + unsigned regs = fieldFromInstruction_4(Val, 1, 7); + + // In case of unpredictable encoding, tweak the operands. + if (regs == 0 || regs > 16 || (Vd + regs) > 32) { + regs = Vd + regs > 32 ? 32 - Vd : regs; + regs = (1u > regs? 1u : regs); + regs = (16u > regs? regs : 16u); + S = MCDisassembler_SoftFail; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + + for (i = 0; i < (regs - 1); ++i) { + if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + // This operand encodes a mask of contiguous zeros between a specified MSB + // and LSB. To decode it, we create the mask of all bits MSB-and-lower, + // the mask of all bits LSB-and-lower, and then xor them to create + // the mask of that's all ones on [msb, lsb]. Finally we not it to + // create the final mask. + unsigned msb = fieldFromInstruction_4(Val, 5, 5); + unsigned lsb = fieldFromInstruction_4(Val, 0, 5); + uint32_t lsb_mask, msb_mask; + + DecodeStatus S = MCDisassembler_Success; + if (lsb > msb) { + Check(&S, MCDisassembler_SoftFail); + // The check above will cause the warning for the "potentially undefined + // instruction encoding" but we can't build a bad MCOperand value here + // with a lsb > msb or else printing the MCInst will cause a crash. + lsb = msb; + } + + msb_mask = 0xFFFFFFFF; + if (msb != 31) msb_mask = (1U << (msb + 1)) - 1; + lsb_mask = (1U << lsb) - 1; + + MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask)); + return S; +} + +static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned CRd = fieldFromInstruction_4(Insn, 12, 4); + unsigned coproc = fieldFromInstruction_4(Insn, 8, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + + switch (MCInst_getOpcode(Inst)) { + case ARM_LDC_OFFSET: + case ARM_LDC_PRE: + case ARM_LDC_POST: + case ARM_LDC_OPTION: + case ARM_LDCL_OFFSET: + case ARM_LDCL_PRE: + case ARM_LDCL_POST: + case ARM_LDCL_OPTION: + case ARM_STC_OFFSET: + case ARM_STC_PRE: + case ARM_STC_POST: + case ARM_STC_OPTION: + case ARM_STCL_OFFSET: + case ARM_STCL_PRE: + case ARM_STCL_POST: + case ARM_STCL_OPTION: + case ARM_t2LDC_OFFSET: + case ARM_t2LDC_PRE: + case ARM_t2LDC_POST: + case ARM_t2LDC_OPTION: + case ARM_t2LDCL_OFFSET: + case ARM_t2LDCL_PRE: + case ARM_t2LDCL_POST: + case ARM_t2LDCL_OPTION: + case ARM_t2STC_OFFSET: + case ARM_t2STC_PRE: + case ARM_t2STC_POST: + case ARM_t2STC_OPTION: + case ARM_t2STCL_OFFSET: + case ARM_t2STCL_PRE: + case ARM_t2STCL_POST: + case ARM_t2STCL_OPTION: + if (coproc == 0xA || coproc == 0xB) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (coproc != 14)) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, coproc); + MCOperand_CreateImm0(Inst, CRd); + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDC2_OFFSET: + case ARM_t2LDC2L_OFFSET: + case ARM_t2LDC2_PRE: + case ARM_t2LDC2L_PRE: + case ARM_t2STC2_OFFSET: + case ARM_t2STC2L_OFFSET: + case ARM_t2STC2_PRE: + case ARM_t2STC2L_PRE: + case ARM_LDC2_OFFSET: + case ARM_LDC2L_OFFSET: + case ARM_LDC2_PRE: + case ARM_LDC2L_PRE: + case ARM_STC2_OFFSET: + case ARM_STC2L_OFFSET: + case ARM_STC2_PRE: + case ARM_STC2L_PRE: + case ARM_t2LDC_OFFSET: + case ARM_t2LDCL_OFFSET: + case ARM_t2LDC_PRE: + case ARM_t2LDCL_PRE: + case ARM_t2STC_OFFSET: + case ARM_t2STCL_OFFSET: + case ARM_t2STC_PRE: + case ARM_t2STCL_PRE: + case ARM_LDC_OFFSET: + case ARM_LDCL_OFFSET: + case ARM_LDC_PRE: + case ARM_LDCL_PRE: + case ARM_STC_OFFSET: + case ARM_STCL_OFFSET: + case ARM_STC_PRE: + case ARM_STCL_PRE: + imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm); + MCOperand_CreateImm0(Inst, imm); + break; + case ARM_t2LDC2_POST: + case ARM_t2LDC2L_POST: + case ARM_t2STC2_POST: + case ARM_t2STC2L_POST: + case ARM_LDC2_POST: + case ARM_LDC2L_POST: + case ARM_STC2_POST: + case ARM_STC2L_POST: + case ARM_t2LDC_POST: + case ARM_t2LDCL_POST: + case ARM_t2STC_POST: + case ARM_t2STCL_POST: + case ARM_LDC_POST: + case ARM_LDCL_POST: + case ARM_STC_POST: + case ARM_STCL_POST: + imm |= U << 8; + // fall through. + default: + // The 'option' variant doesn't encode 'U' in the immediate since + // the immediate is unsigned [0,255]. + MCOperand_CreateImm0(Inst, imm); + break; + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_LDC_OFFSET: + case ARM_LDC_PRE: + case ARM_LDC_POST: + case ARM_LDC_OPTION: + case ARM_LDCL_OFFSET: + case ARM_LDCL_PRE: + case ARM_LDCL_POST: + case ARM_LDCL_OPTION: + case ARM_STC_OFFSET: + case ARM_STC_PRE: + case ARM_STC_POST: + case ARM_STC_OPTION: + case ARM_STCL_OFFSET: + case ARM_STCL_PRE: + case ARM_STCL_POST: + case ARM_STCL_OPTION: + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + return S; +} + +static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + ARM_AM_AddrOpc Op; + ARM_AM_ShiftOpc Opc; + bool writeback; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned reg = fieldFromInstruction_4(Insn, 25, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned idx_mode = 0, amt, tmp; + + // On stores, the writeback operand precedes Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_STR_POST_IMM: + case ARM_STR_POST_REG: + case ARM_STRB_POST_IMM: + case ARM_STRB_POST_REG: + case ARM_STRT_POST_REG: + case ARM_STRT_POST_IMM: + case ARM_STRBT_POST_REG: + case ARM_STRBT_POST_IMM: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + // On loads, the writeback operand comes after Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_LDR_POST_IMM: + case ARM_LDR_POST_REG: + case ARM_LDRB_POST_IMM: + case ARM_LDRB_POST_REG: + case ARM_LDRBT_POST_REG: + case ARM_LDRBT_POST_IMM: + case ARM_LDRT_POST_REG: + case ARM_LDRT_POST_IMM: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + Op = ARM_AM_add; + if (!fieldFromInstruction_4(Insn, 23, 1)) + Op = ARM_AM_sub; + + writeback = (P == 0) || (W == 1); + if (P && writeback) + idx_mode = ARMII_IndexModePre; + else if (!P && writeback) + idx_mode = ARMII_IndexModePost; + + if (writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; // UNPREDICTABLE + + if (reg) { + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + Opc = ARM_AM_lsl; + switch(fieldFromInstruction_4(Insn, 5, 2)) { + case 0: + Opc = ARM_AM_lsl; + break; + case 1: + Opc = ARM_AM_lsr; + break; + case 2: + Opc = ARM_AM_asr; + break; + case 3: + Opc = ARM_AM_ror; + break; + default: + return MCDisassembler_Fail; + } + + amt = fieldFromInstruction_4(Insn, 7, 5); + if (Opc == ARM_AM_ror && amt == 0) + Opc = ARM_AM_rrx; + + imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); + + MCOperand_CreateImm0(Inst, imm); + } else { + MCOperand_CreateReg0(Inst, 0); + tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode); + MCOperand_CreateImm0(Inst, tmp); + } + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + ARM_AM_ShiftOpc ShOp; + unsigned shift; + unsigned Rn = fieldFromInstruction_4(Val, 13, 4); + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned type = fieldFromInstruction_4(Val, 5, 2); + unsigned imm = fieldFromInstruction_4(Val, 7, 5); + unsigned U = fieldFromInstruction_4(Val, 12, 1); + + ShOp = ARM_AM_lsl; + switch (type) { + case 0: + ShOp = ARM_AM_lsl; + break; + case 1: + ShOp = ARM_AM_lsr; + break; + case 2: + ShOp = ARM_AM_asr; + break; + case 3: + ShOp = ARM_AM_ror; + break; + } + + if (ShOp == ARM_AM_ror && imm == 0) + ShOp = ARM_AM_rrx; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + if (U) + shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); + else + shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); + + MCOperand_CreateImm0(Inst, shift); + + return S; +} + +static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned type = fieldFromInstruction_4(Insn, 22, 1); + unsigned imm = fieldFromInstruction_4(Insn, 8, 4); + unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8; + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + unsigned Rt2 = Rt + 1; + + bool writeback = (W == 1) | (P == 0); + + // For {LD,ST}RD, Rt must be even, else undefined. + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + if (Rt & 0x1) + S = MCDisassembler_SoftFail; + break; + default: + break; + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + if (P == 0 && W == 1) + S = MCDisassembler_SoftFail; + + if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) + S = MCDisassembler_SoftFail; + + if (type && Rm == 15) + S = MCDisassembler_SoftFail; + + if (Rt2 == 15) + S = MCDisassembler_SoftFail; + + if (!type && fieldFromInstruction_4(Insn, 8, 4)) + S = MCDisassembler_SoftFail; + + break; + + case ARM_STRH: + case ARM_STRH_PRE: + case ARM_STRH_POST: + if (Rt == 15) + S = MCDisassembler_SoftFail; + + if (writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; + + if (!type && Rm == 15) + S = MCDisassembler_SoftFail; + + break; + + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + if (type && Rn == 15) { + if (Rt2 == 15) + S = MCDisassembler_SoftFail; + break; + } + + if (P == 0 && W == 1) + S = MCDisassembler_SoftFail; + + if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) + S = MCDisassembler_SoftFail; + + if (!type && writeback && Rn == 15) + S = MCDisassembler_SoftFail; + + if (writeback && (Rn == Rt || Rn == Rt2)) + S = MCDisassembler_SoftFail; + + break; + + case ARM_LDRH: + case ARM_LDRH_PRE: + case ARM_LDRH_POST: + if (type && Rn == 15) { + if (Rt == 15) + S = MCDisassembler_SoftFail; + break; + } + + if (Rt == 15) + S = MCDisassembler_SoftFail; + + if (!type && Rm == 15) + S = MCDisassembler_SoftFail; + + if (!type && writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; + break; + + case ARM_LDRSH: + case ARM_LDRSH_PRE: + case ARM_LDRSH_POST: + case ARM_LDRSB: + case ARM_LDRSB_PRE: + case ARM_LDRSB_POST: + if (type && Rn == 15){ + if (Rt == 15) + S = MCDisassembler_SoftFail; + break; + } + + if (type && (Rt == 15 || (writeback && Rn == Rt))) + S = MCDisassembler_SoftFail; + + if (!type && (Rt == 15 || Rm == 15)) + S = MCDisassembler_SoftFail; + + if (!type && writeback && (Rn == 15 || Rn == Rt)) + S = MCDisassembler_SoftFail; + + break; + + default: + break; + } + + if (writeback) { // Writeback + Inst->writeback = true; + + if (P) + U |= ARMII_IndexModePre << 9; + else + U |= ARMII_IndexModePost << 9; + + // On stores, the writeback operand precedes Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + case ARM_STRH: + case ARM_STRH_PRE: + case ARM_STRH_POST: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + switch (MCInst_getOpcode(Inst)) { + case ARM_STRD: + case ARM_STRD_PRE: + case ARM_STRD_POST: + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt + 1, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + if (writeback) { + // On loads, the writeback operand comes after Rt. + switch (MCInst_getOpcode(Inst)) { + case ARM_LDRD: + case ARM_LDRD_PRE: + case ARM_LDRD_POST: + case ARM_LDRH: + case ARM_LDRH_PRE: + case ARM_LDRH_POST: + case ARM_LDRSH: + case ARM_LDRSH_PRE: + case ARM_LDRSH_POST: + case ARM_LDRSB: + case ARM_LDRSB_PRE: + case ARM_LDRSB_POST: + case ARM_LDRHTr: + case ARM_LDRSBTr: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (type) { + MCOperand_CreateReg0(Inst, 0); + MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm); + } else { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, U); + } + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned mode = fieldFromInstruction_4(Insn, 23, 2); + + switch (mode) { + case 0: + mode = ARM_AM_da; + break; + case 1: + mode = ARM_AM_ia; + break; + case 2: + mode = ARM_AM_db; + break; + case 3: + mode = ARM_AM_ib; + break; + } + + MCOperand_CreateImm0(Inst, mode); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (pred == 0xF) + return DecodeCPSInstruction(Inst, Insn, Address, Decoder); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, + unsigned Insn, uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); + + if (pred == 0xF) { + // Ambiguous with RFE and SRS + switch (MCInst_getOpcode(Inst)) { + case ARM_LDMDA: + MCInst_setOpcode(Inst, ARM_RFEDA); + break; + case ARM_LDMDA_UPD: + MCInst_setOpcode(Inst, ARM_RFEDA_UPD); + break; + case ARM_LDMDB: + MCInst_setOpcode(Inst, ARM_RFEDB); + break; + case ARM_LDMDB_UPD: + MCInst_setOpcode(Inst, ARM_RFEDB_UPD); + break; + case ARM_LDMIA: + MCInst_setOpcode(Inst, ARM_RFEIA); + break; + case ARM_LDMIA_UPD: + MCInst_setOpcode(Inst, ARM_RFEIA_UPD); + break; + case ARM_LDMIB: + MCInst_setOpcode(Inst, ARM_RFEIB); + break; + case ARM_LDMIB_UPD: + MCInst_setOpcode(Inst, ARM_RFEIB_UPD); + break; + case ARM_STMDA: + MCInst_setOpcode(Inst, ARM_SRSDA); + break; + case ARM_STMDA_UPD: + MCInst_setOpcode(Inst, ARM_SRSDA_UPD); + break; + case ARM_STMDB: + MCInst_setOpcode(Inst, ARM_SRSDB); + break; + case ARM_STMDB_UPD: + MCInst_setOpcode(Inst, ARM_SRSDB_UPD); + break; + case ARM_STMIA: + MCInst_setOpcode(Inst, ARM_SRSIA); + break; + case ARM_STMIA_UPD: + MCInst_setOpcode(Inst, ARM_SRSIA_UPD); + break; + case ARM_STMIB: + MCInst_setOpcode(Inst, ARM_SRSIB); + break; + case ARM_STMIB_UPD: + MCInst_setOpcode(Inst, ARM_SRSIB_UPD); + break; + default: + return MCDisassembler_Fail; + } + + // For stores (which become SRS's, the only operand is the mode. + if (fieldFromInstruction_4(Insn, 20, 1) == 0) { + // Check SRS encoding constraints + if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 && + fieldFromInstruction_4(Insn, 20, 1) == 0)) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4)); + return S; + } + + return DecodeRFEInstruction(Inst, Insn, Address, Decoder); + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; // Tied + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +// Check for UNPREDICTABLE predicated ESB instruction +static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned imm8 = fieldFromInstruction_4(Insn, 0, 8); + DecodeStatus result = MCDisassembler_Success; + + MCOperand_CreateImm0(Inst, imm8); + + if (!Check(&result, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, + // so all predicates should be allowed. + if (imm8 == 0x10 && pred != 0xe && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureRAS)) + result = MCDisassembler_SoftFail; + + return result; +} + +static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + unsigned imod = fieldFromInstruction_4(Insn, 18, 2); + unsigned M = fieldFromInstruction_4(Insn, 17, 1); + unsigned iflags = fieldFromInstruction_4(Insn, 6, 3); + unsigned mode = fieldFromInstruction_4(Insn, 0, 5); + + DecodeStatus S = MCDisassembler_Success; + + // This decoder is called from multiple location that do not check + // the full encoding is valid before they do. + if (fieldFromInstruction_4(Insn, 5, 1) != 0 || + fieldFromInstruction_4(Insn, 16, 1) != 0 || + fieldFromInstruction_4(Insn, 20, 8) != 0x10) + return MCDisassembler_Fail; + + // imod == '01' --> UNPREDICTABLE + // NOTE: Even though this is technically UNPREDICTABLE, we choose to + // return failure here. The '01' imod value is unprintable, so there's + // nothing useful we could do even if we returned UNPREDICTABLE. + + if (imod == 1) return MCDisassembler_Fail; + + if (imod && M) { + MCInst_setOpcode(Inst, ARM_CPS3p); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); + MCOperand_CreateImm0(Inst, mode); + } else if (imod && !M) { + MCInst_setOpcode(Inst, ARM_CPS2p); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); + if (mode) S = MCDisassembler_SoftFail; + } else if (!imod && M) { + MCInst_setOpcode(Inst, ARM_CPS1p); + MCOperand_CreateImm0(Inst, mode); + if (iflags) S = MCDisassembler_SoftFail; + } else { + // imod == '00' && M == '0' --> UNPREDICTABLE + MCInst_setOpcode(Inst, ARM_CPS1p); + MCOperand_CreateImm0(Inst, mode); + S = MCDisassembler_SoftFail; + } + + return S; +} + +static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + unsigned imod = fieldFromInstruction_4(Insn, 9, 2); + unsigned M = fieldFromInstruction_4(Insn, 8, 1); + unsigned iflags = fieldFromInstruction_4(Insn, 5, 3); + unsigned mode = fieldFromInstruction_4(Insn, 0, 5); + + DecodeStatus S = MCDisassembler_Success; + + // imod == '01' --> UNPREDICTABLE + // NOTE: Even though this is technically UNPREDICTABLE, we choose to + // return failure here. The '01' imod value is unprintable, so there's + // nothing useful we could do even if we returned UNPREDICTABLE. + + if (imod == 1) return MCDisassembler_Fail; + + if (imod && M) { + MCInst_setOpcode(Inst, ARM_t2CPS3p); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); + MCOperand_CreateImm0(Inst, mode); + } else if (imod && !M) { + MCInst_setOpcode(Inst, ARM_t2CPS2p); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); + if (mode) S = MCDisassembler_SoftFail; + } else if (!imod && M) { + MCInst_setOpcode(Inst, ARM_t2CPS1p); + MCOperand_CreateImm0(Inst, mode); + if (iflags) S = MCDisassembler_SoftFail; + } else { + // imod == '00' && M == '0' --> this is a HINT instruction + int imm = fieldFromInstruction_4(Insn, 0, 8); + // HINT are defined only for immediate in [0..4] + if (imm > 4) return MCDisassembler_Fail; + + MCInst_setOpcode(Inst, ARM_t2HINT); + MCOperand_CreateImm0(Inst, imm); + } + + return S; +} + +static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); + unsigned imm = 0; + + imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0); + imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8); + imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); + imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11); + + if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16) + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned imm = 0; + + imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0); + imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); + + if (MCInst_getOpcode(Inst) == ARM_MOVTi16) + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, imm); + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 8, 4); + unsigned Ra = fieldFromInstruction_4(Insn, 12, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (pred == 0xF) + return DecodeCPSInstruction(Inst, Insn, Address, Decoder); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + if (Pred == 0xF) + return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Imm = fieldFromInstruction_4(Insn, 9, 1); + + if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps) || !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) + return MCDisassembler_Fail; + + // Decoder can be called from DecodeTST, which does not check the full + // encoding is valid. + if (fieldFromInstruction_4(Insn, 20, 12) != 0xf11 || + fieldFromInstruction_4(Insn, 4, 4) != 0) + return MCDisassembler_Fail; + + if (fieldFromInstruction_4(Insn, 10, 10) != 0 || + fieldFromInstruction_4(Insn, 0, 4) != 0) + S = MCDisassembler_SoftFail; + + MCInst_setOpcode(Inst, ARM_SETPAN); + MCOperand_CreateImm0(Inst, Imm); + + return S; +} + +static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned add = fieldFromInstruction_4(Val, 12, 1); + unsigned imm = fieldFromInstruction_4(Val, 0, 12); + unsigned Rn = fieldFromInstruction_4(Val, 13, 4); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!add) imm *= (unsigned int)-1; + if (imm == 0 && !add) imm = (unsigned int)INT32_MIN; + + MCOperand_CreateImm0(Inst, imm); + //if (Rn == 15) + // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); + + return S; +} + +static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + // U == 1 to add imm, 0 to subtract it. + unsigned U = fieldFromInstruction_4(Val, 8, 1); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (U) + MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm)); + else + MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm)); + + return S; +} + +static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + // U == 1 to add imm, 0 to subtract it. + unsigned U = fieldFromInstruction_4(Val, 8, 1); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (U) + MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_add, imm)); + else + MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_sub, imm)); + + return S; +} + +static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); +} + +static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus Status = MCDisassembler_Success; + + // Note the J1 and J2 values are from the encoded instruction. So here + // change them to I1 and I2 values via as documented: + // I1 = NOT(J1 EOR S); + // I2 = NOT(J2 EOR S); + // and build the imm32 with one trailing zero as documented: + // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); + unsigned S = fieldFromInstruction_4(Insn, 26, 1); + unsigned J1 = fieldFromInstruction_4(Insn, 13, 1); + unsigned J2 = fieldFromInstruction_4(Insn, 11, 1); + unsigned I1 = !(J1 ^ S); + unsigned I2 = !(J2 ^ S); + unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); + unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11); + unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; + int imm32 = SignExtend32(tmp << 1, 25); + + MCOperand_CreateImm0(Inst, imm32); + + return Status; +} + +static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2; + + if (pred == 0xF) { + MCInst_setOpcode(Inst, ARM_BLXi); + imm |= fieldFromInstruction_4(Insn, 24, 1) << 1; + MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); + return S; + } + + MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + + +static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + unsigned align = fieldFromInstruction_4(Val, 4, 2); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + if (!align) + MCOperand_CreateImm0(Inst, 0); + else + MCOperand_CreateImm0(Inst, 4 << align); + + return S; +} + +static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned wb, Rn, Rm; + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + wb = fieldFromInstruction_4(Insn, 16, 4); + Rn = fieldFromInstruction_4(Insn, 16, 4); + Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; + Rm = fieldFromInstruction_4(Insn, 0, 4); + + // First output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD1q16: case ARM_VLD1q32: case ARM_VLD1q64: case ARM_VLD1q8: + case ARM_VLD1q16wb_fixed: case ARM_VLD1q16wb_register: + case ARM_VLD1q32wb_fixed: case ARM_VLD1q32wb_register: + case ARM_VLD1q64wb_fixed: case ARM_VLD1q64wb_register: + case ARM_VLD1q8wb_fixed: case ARM_VLD1q8wb_register: + case ARM_VLD2d16: case ARM_VLD2d32: case ARM_VLD2d8: + case ARM_VLD2d16wb_fixed: case ARM_VLD2d16wb_register: + case ARM_VLD2d32wb_fixed: case ARM_VLD2d32wb_register: + case ARM_VLD2d8wb_fixed: case ARM_VLD2d8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + + case ARM_VLD2b16: + case ARM_VLD2b32: + case ARM_VLD2b8: + case ARM_VLD2b16wb_fixed: + case ARM_VLD2b16wb_register: + case ARM_VLD2b32wb_fixed: + case ARM_VLD2b32wb_register: + case ARM_VLD2b8wb_fixed: + case ARM_VLD2b8wb_register: + if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + + default: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } + + // Second output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD3d8: + case ARM_VLD3d16: + case ARM_VLD3d32: + case ARM_VLD3d8_UPD: + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD4d8: + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + + case ARM_VLD3q8: + case ARM_VLD3q16: + case ARM_VLD3q32: + case ARM_VLD3q8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD4q8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) + return MCDisassembler_Fail; + + default: + break; + } + + // Third output register + switch(MCInst_getOpcode(Inst)) { + case ARM_VLD3d8: + case ARM_VLD3d16: + case ARM_VLD3d32: + case ARM_VLD3d8_UPD: + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD4d8: + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD3q8: + case ARM_VLD3q16: + case ARM_VLD3q32: + case ARM_VLD3q8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD4q8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Fourth output register + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD4d8: + case ARM_VLD4d16: + case ARM_VLD4d32: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VLD4q8: + case ARM_VLD4q16: + case ARM_VLD4q32: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Writeback operand + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD1d8wb_fixed: + case ARM_VLD1d16wb_fixed: + case ARM_VLD1d32wb_fixed: + case ARM_VLD1d64wb_fixed: + case ARM_VLD1d8wb_register: + case ARM_VLD1d16wb_register: + case ARM_VLD1d32wb_register: + case ARM_VLD1d64wb_register: + case ARM_VLD1q8wb_fixed: + case ARM_VLD1q16wb_fixed: + case ARM_VLD1q32wb_fixed: + case ARM_VLD1q64wb_fixed: + case ARM_VLD1q8wb_register: + case ARM_VLD1q16wb_register: + case ARM_VLD1q32wb_register: + case ARM_VLD1q64wb_register: + case ARM_VLD1d8Twb_fixed: + case ARM_VLD1d8Twb_register: + case ARM_VLD1d16Twb_fixed: + case ARM_VLD1d16Twb_register: + case ARM_VLD1d32Twb_fixed: + case ARM_VLD1d32Twb_register: + case ARM_VLD1d64Twb_fixed: + case ARM_VLD1d64Twb_register: + case ARM_VLD1d8Qwb_fixed: + case ARM_VLD1d8Qwb_register: + case ARM_VLD1d16Qwb_fixed: + case ARM_VLD1d16Qwb_register: + case ARM_VLD1d32Qwb_fixed: + case ARM_VLD1d32Qwb_register: + case ARM_VLD1d64Qwb_fixed: + case ARM_VLD1d64Qwb_register: + case ARM_VLD2d8wb_fixed: + case ARM_VLD2d16wb_fixed: + case ARM_VLD2d32wb_fixed: + case ARM_VLD2q8wb_fixed: + case ARM_VLD2q16wb_fixed: + case ARM_VLD2q32wb_fixed: + case ARM_VLD2d8wb_register: + case ARM_VLD2d16wb_register: + case ARM_VLD2d32wb_register: + case ARM_VLD2q8wb_register: + case ARM_VLD2q16wb_register: + case ARM_VLD2q32wb_register: + case ARM_VLD2b8wb_fixed: + case ARM_VLD2b16wb_fixed: + case ARM_VLD2b32wb_fixed: + case ARM_VLD2b8wb_register: + case ARM_VLD2b16wb_register: + case ARM_VLD2b32wb_register: + MCOperand_CreateImm0(Inst, 0); + break; + + case ARM_VLD3d8_UPD: + case ARM_VLD3d16_UPD: + case ARM_VLD3d32_UPD: + case ARM_VLD3q8_UPD: + case ARM_VLD3q16_UPD: + case ARM_VLD3q32_UPD: + case ARM_VLD4d8_UPD: + case ARM_VLD4d16_UPD: + case ARM_VLD4d32_UPD: + case ARM_VLD4q8_UPD: + case ARM_VLD4q16_UPD: + case ARM_VLD4q32_UPD: + if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) + return MCDisassembler_Fail; + break; + + default: + break; + } + + // AddrMode6 Base (register+alignment) + if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + // AddrMode6 Offset (register) + switch (MCInst_getOpcode(Inst)) { + default: + // The below have been updated to have explicit am6offset split + // between fixed and register offset. For those instructions not + // yet updated, we need to add an additional reg0 operand for the + // fixed variant. + // + // The fixed offset encodes as Rm == 0xd, so we check for that. + if (Rm == 0xd) { + MCOperand_CreateReg0(Inst, 0); + break; + } + // Fall through to handle the register offset variant. + + case ARM_VLD1d8wb_fixed: + case ARM_VLD1d16wb_fixed: + case ARM_VLD1d32wb_fixed: + case ARM_VLD1d64wb_fixed: + case ARM_VLD1d8Twb_fixed: + case ARM_VLD1d16Twb_fixed: + case ARM_VLD1d32Twb_fixed: + case ARM_VLD1d64Twb_fixed: + case ARM_VLD1d8Qwb_fixed: + case ARM_VLD1d16Qwb_fixed: + case ARM_VLD1d32Qwb_fixed: + case ARM_VLD1d64Qwb_fixed: + case ARM_VLD1d8wb_register: + case ARM_VLD1d16wb_register: + case ARM_VLD1d32wb_register: + case ARM_VLD1d64wb_register: + case ARM_VLD1q8wb_fixed: + case ARM_VLD1q16wb_fixed: + case ARM_VLD1q32wb_fixed: + case ARM_VLD1q64wb_fixed: + case ARM_VLD1q8wb_register: + case ARM_VLD1q16wb_register: + case ARM_VLD1q32wb_register: + case ARM_VLD1q64wb_register: + // The fixed offset post-increment encodes Rm == 0xd. The no-writeback + // variant encodes Rm == 0xf. Anything else is a register offset post- + // increment and we need to add the register operand to the instruction. + if (Rm != 0xD && Rm != 0xF && + !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + break; + + case ARM_VLD2d8wb_fixed: + case ARM_VLD2d16wb_fixed: + case ARM_VLD2d32wb_fixed: + case ARM_VLD2b8wb_fixed: + case ARM_VLD2b16wb_fixed: + case ARM_VLD2b32wb_fixed: + case ARM_VLD2q8wb_fixed: + case ARM_VLD2q16wb_fixed: + case ARM_VLD2q32wb_fixed: + break; + } + + return S; +} + +static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + unsigned load; + unsigned type = fieldFromInstruction_4(Insn, 8, 4); + unsigned align = fieldFromInstruction_4(Insn, 4, 2); + if (type == 6 && (align & 2)) return MCDisassembler_Fail; + if (type == 7 && (align & 2)) return MCDisassembler_Fail; + if (type == 10 && align == 3) return MCDisassembler_Fail; + + load = fieldFromInstruction_4(Insn, 21, 1); + + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) + : DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + unsigned type, align, load; + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + if (size == 3) return MCDisassembler_Fail; + + type = fieldFromInstruction_4(Insn, 8, 4); + align = fieldFromInstruction_4(Insn, 4, 2); + if (type == 8 && align == 3) return MCDisassembler_Fail; + if (type == 9 && align == 3) return MCDisassembler_Fail; + + load = fieldFromInstruction_4(Insn, 21, 1); + + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) + : DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + unsigned align, load; + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + if (size == 3) return MCDisassembler_Fail; + + align = fieldFromInstruction_4(Insn, 4, 2); + if (align & 2) return MCDisassembler_Fail; + + load = fieldFromInstruction_4(Insn, 21, 1); + + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) + : DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + unsigned load; + unsigned size = fieldFromInstruction_4(Insn, 6, 2); + if (size == 3) return MCDisassembler_Fail; + + load = fieldFromInstruction_4(Insn, 21, 1); + + return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) + : DecodeVSTInstruction(Inst, Insn, Address, Decoder); +} + +static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned wb, Rn, Rm; + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + wb = fieldFromInstruction_4(Insn, 16, 4); + Rn = fieldFromInstruction_4(Insn, 16, 4); + Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; + Rm = fieldFromInstruction_4(Insn, 0, 4); + + // Writeback Operand + switch (MCInst_getOpcode(Inst)) { + case ARM_VST1d8wb_fixed: + case ARM_VST1d16wb_fixed: + case ARM_VST1d32wb_fixed: + case ARM_VST1d64wb_fixed: + case ARM_VST1d8wb_register: + case ARM_VST1d16wb_register: + case ARM_VST1d32wb_register: + case ARM_VST1d64wb_register: + case ARM_VST1q8wb_fixed: + case ARM_VST1q16wb_fixed: + case ARM_VST1q32wb_fixed: + case ARM_VST1q64wb_fixed: + case ARM_VST1q8wb_register: + case ARM_VST1q16wb_register: + case ARM_VST1q32wb_register: + case ARM_VST1q64wb_register: + case ARM_VST1d8Twb_fixed: + case ARM_VST1d16Twb_fixed: + case ARM_VST1d32Twb_fixed: + case ARM_VST1d64Twb_fixed: + case ARM_VST1d8Twb_register: + case ARM_VST1d16Twb_register: + case ARM_VST1d32Twb_register: + case ARM_VST1d64Twb_register: + case ARM_VST1d8Qwb_fixed: + case ARM_VST1d16Qwb_fixed: + case ARM_VST1d32Qwb_fixed: + case ARM_VST1d64Qwb_fixed: + case ARM_VST1d8Qwb_register: + case ARM_VST1d16Qwb_register: + case ARM_VST1d32Qwb_register: + case ARM_VST1d64Qwb_register: + case ARM_VST2d8wb_fixed: + case ARM_VST2d16wb_fixed: + case ARM_VST2d32wb_fixed: + case ARM_VST2d8wb_register: + case ARM_VST2d16wb_register: + case ARM_VST2d32wb_register: + case ARM_VST2q8wb_fixed: + case ARM_VST2q16wb_fixed: + case ARM_VST2q32wb_fixed: + case ARM_VST2q8wb_register: + case ARM_VST2q16wb_register: + case ARM_VST2q32wb_register: + case ARM_VST2b8wb_fixed: + case ARM_VST2b16wb_fixed: + case ARM_VST2b32wb_fixed: + case ARM_VST2b8wb_register: + case ARM_VST2b16wb_register: + case ARM_VST2b32wb_register: + if (Rm == 0xF) + return MCDisassembler_Fail; + MCOperand_CreateImm0(Inst, 0); + break; + case ARM_VST3d8_UPD: + case ARM_VST3d16_UPD: + case ARM_VST3d32_UPD: + case ARM_VST3q8_UPD: + case ARM_VST3q16_UPD: + case ARM_VST3q32_UPD: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // AddrMode6 Base (register+alignment) + if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + // AddrMode6 Offset (register) + switch (MCInst_getOpcode(Inst)) { + default: + if (Rm == 0xD) + MCOperand_CreateReg0(Inst, 0); + else if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + break; + + case ARM_VST1d8wb_fixed: + case ARM_VST1d16wb_fixed: + case ARM_VST1d32wb_fixed: + case ARM_VST1d64wb_fixed: + case ARM_VST1q8wb_fixed: + case ARM_VST1q16wb_fixed: + case ARM_VST1q32wb_fixed: + case ARM_VST1q64wb_fixed: + case ARM_VST1d8Twb_fixed: + case ARM_VST1d16Twb_fixed: + case ARM_VST1d32Twb_fixed: + case ARM_VST1d64Twb_fixed: + case ARM_VST1d8Qwb_fixed: + case ARM_VST1d16Qwb_fixed: + case ARM_VST1d32Qwb_fixed: + case ARM_VST1d64Qwb_fixed: + case ARM_VST2d8wb_fixed: + case ARM_VST2d16wb_fixed: + case ARM_VST2d32wb_fixed: + case ARM_VST2q8wb_fixed: + case ARM_VST2q16wb_fixed: + case ARM_VST2q32wb_fixed: + case ARM_VST2b8wb_fixed: + case ARM_VST2b16wb_fixed: + case ARM_VST2b32wb_fixed: + break; + } + + + // First input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST1q16: + case ARM_VST1q32: + case ARM_VST1q64: + case ARM_VST1q8: + case ARM_VST1q16wb_fixed: + case ARM_VST1q16wb_register: + case ARM_VST1q32wb_fixed: + case ARM_VST1q32wb_register: + case ARM_VST1q64wb_fixed: + case ARM_VST1q64wb_register: + case ARM_VST1q8wb_fixed: + case ARM_VST1q8wb_register: + case ARM_VST2d16: + case ARM_VST2d32: + case ARM_VST2d8: + case ARM_VST2d16wb_fixed: + case ARM_VST2d16wb_register: + case ARM_VST2d32wb_fixed: + case ARM_VST2d32wb_register: + case ARM_VST2d8wb_fixed: + case ARM_VST2d8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + + case ARM_VST2b16: + case ARM_VST2b32: + case ARM_VST2b8: + case ARM_VST2b16wb_fixed: + case ARM_VST2b16wb_register: + case ARM_VST2b32wb_fixed: + case ARM_VST2b32wb_register: + case ARM_VST2b8wb_fixed: + case ARM_VST2b8wb_register: + if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + + default: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } + + // Second input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST3d8: + case ARM_VST3d16: + case ARM_VST3d32: + case ARM_VST3d8_UPD: + case ARM_VST3d16_UPD: + case ARM_VST3d32_UPD: + case ARM_VST4d8: + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + + case ARM_VST3q8: + case ARM_VST3q16: + case ARM_VST3q32: + case ARM_VST3q8_UPD: + case ARM_VST3q16_UPD: + case ARM_VST3q32_UPD: + case ARM_VST4q8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Third input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST3d8: + case ARM_VST3d16: + case ARM_VST3d32: + case ARM_VST3d8_UPD: + case ARM_VST3d16_UPD: + case ARM_VST3d32_UPD: + case ARM_VST4d8: + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + + case ARM_VST3q8: + case ARM_VST3q16: + case ARM_VST3q32: + case ARM_VST3q8_UPD: + case ARM_VST3q16_UPD: + case ARM_VST3q32_UPD: + case ARM_VST4q8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Fourth input register + switch (MCInst_getOpcode(Inst)) { + case ARM_VST4d8: + case ARM_VST4d16: + case ARM_VST4d32: + case ARM_VST4d8_UPD: + case ARM_VST4d16_UPD: + case ARM_VST4d32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + + case ARM_VST4q8: + case ARM_VST4q16: + case ARM_VST4q32: + case ARM_VST4q8_UPD: + case ARM_VST4q16_UPD: + case ARM_VST4q32_UPD: + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + return S; +} + +static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn, Rm, align, size; + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + Rn = fieldFromInstruction_4(Insn, 16, 4); + Rm = fieldFromInstruction_4(Insn, 0, 4); + align = fieldFromInstruction_4(Insn, 4, 1); + size = fieldFromInstruction_4(Insn, 6, 2); + + if (size == 0 && align == 1) + return MCDisassembler_Fail; + + align *= (1 << size); + + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD1DUPq16: case ARM_VLD1DUPq32: case ARM_VLD1DUPq8: + case ARM_VLD1DUPq16wb_fixed: case ARM_VLD1DUPq16wb_register: + case ARM_VLD1DUPq32wb_fixed: case ARM_VLD1DUPq32wb_register: + case ARM_VLD1DUPq8wb_fixed: case ARM_VLD1DUPq8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + + default: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + } + + if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + // The fixed offset post-increment encodes Rm == 0xd. The no-writeback + // variant encodes Rm == 0xf. Anything else is a register offset post- + // increment and we need to add the register operand to the instruction. + if (Rm != 0xD && Rm != 0xF && + !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn, Rm, align, size; + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + Rn = fieldFromInstruction_4(Insn, 16, 4); + Rm = fieldFromInstruction_4(Insn, 0, 4); + align = fieldFromInstruction_4(Insn, 4, 1); + size = 1 << fieldFromInstruction_4(Insn, 6, 2); + align *= 2 * size; + + switch (MCInst_getOpcode(Inst)) { + case ARM_VLD2DUPd16: case ARM_VLD2DUPd32: case ARM_VLD2DUPd8: + case ARM_VLD2DUPd16wb_fixed: case ARM_VLD2DUPd16wb_register: + case ARM_VLD2DUPd32wb_fixed: case ARM_VLD2DUPd32wb_register: + case ARM_VLD2DUPd8wb_fixed: case ARM_VLD2DUPd8wb_register: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + + case ARM_VLD2DUPd16x2: case ARM_VLD2DUPd32x2: case ARM_VLD2DUPd8x2: + case ARM_VLD2DUPd16x2wb_fixed: case ARM_VLD2DUPd16x2wb_register: + case ARM_VLD2DUPd32x2wb_fixed: case ARM_VLD2DUPd32x2wb_register: + case ARM_VLD2DUPd8x2wb_fixed: case ARM_VLD2DUPd8x2wb_register: + if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + + default: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + } + + if (Rm != 0xF) + MCOperand_CreateImm0(Inst, 0); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + if (Rm != 0xD && Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn, Rm, inc; + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + Rn = fieldFromInstruction_4(Insn, 16, 4); + Rm = fieldFromInstruction_4(Insn, 0, 4); + inc = fieldFromInstruction_4(Insn, 5, 1) + 1; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2*inc) % 32, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, 0); + + if (Rm == 0xD) + MCOperand_CreateReg0(Inst, 0); + else if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn, Rm, size, inc, align; + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + Rn = fieldFromInstruction_4(Insn, 16, 4); + Rm = fieldFromInstruction_4(Insn, 0, 4); + size = fieldFromInstruction_4(Insn, 6, 2); + inc = fieldFromInstruction_4(Insn, 5, 1) + 1; + align = fieldFromInstruction_4(Insn, 4, 1); + + if (size == 0x3) { + if (align == 0) + return MCDisassembler_Fail; + align = 16; + } else { + if (size == 2) { + align *= 8; + } else { + size = 1 << size; + align *= 4 * size; + } + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2*inc) % 32, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3*inc) % 32, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + if (Rm == 0xD) + MCOperand_CreateReg0(Inst, 0); + else if (Rm != 0xF) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned imm, Q; + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + imm = fieldFromInstruction_4(Insn, 0, 4); + imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; + imm |= fieldFromInstruction_4(Insn, 24, 1) << 7; + imm |= fieldFromInstruction_4(Insn, 8, 4) << 8; + imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; + Q = fieldFromInstruction_4(Insn, 6, 1); + + if (Q) { + if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } else { + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + } + + MCOperand_CreateImm0(Inst, imm); + + switch (MCInst_getOpcode(Inst)) { + case ARM_VORRiv4i16: + case ARM_VORRiv2i32: + case ARM_VBICiv4i16: + case ARM_VBICiv2i32: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + case ARM_VORRiv8i16: + case ARM_VORRiv4i32: + case ARM_VBICiv8i16: + case ARM_VBICiv4i32: + if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + break; + } + + return S; +} + +static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rm, size; + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + Rm = fieldFromInstruction_4(Insn, 0, 4); + Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; + size = fieldFromInstruction_4(Insn, 18, 2); + + if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, 8 << size); + + return S; +} + +static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, 8 - Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, 16 - Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, 32 - Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, 64 - Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn, Rm, op; + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + Rn = fieldFromInstruction_4(Insn, 16, 4); + Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4; + Rm = fieldFromInstruction_4(Insn, 0, 4); + Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; + op = fieldFromInstruction_4(Insn, 6, 1); + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (op) { + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; // Writeback + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_VTBL2: + case ARM_VTBX2: + if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned dst = fieldFromInstruction_2(Insn, 8, 3); + unsigned imm = fieldFromInstruction_2(Insn, 0, 8); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) + return MCDisassembler_Fail; + + switch(MCInst_getOpcode(Inst)) { + default: + return MCDisassembler_Fail; + case ARM_tADR: + break; // tADR does not explicitly represent the PC as an operand. + case ARM_tADDrSPi: + MCOperand_CreateReg0(Inst, ARM_SP); + break; + } + + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, SignExtend32(Val, 21)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, Val << 1); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Val, 0, 3); + unsigned Rm = fieldFromInstruction_4(Val, 3, 3); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Val, 0, 3); + unsigned imm = fieldFromInstruction_4(Val, 3, 5); + + if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + unsigned imm = Val << 2; + + MCOperand_CreateImm0(Inst, imm); + //tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateImm0(Inst, Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Val, 6, 4); + unsigned Rm = fieldFromInstruction_4(Val, 2, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 2); + + // Thumb stores cannot use PC as dest register. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2STRHs: + case ARM_t2STRBs: + case ARM_t2STRs: + if (Rn == 15) + return MCDisassembler_Fail; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned addrmode; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); + bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRBs: + MCInst_setOpcode(Inst, ARM_t2LDRBpci); + break; + case ARM_t2LDRHs: + MCInst_setOpcode(Inst, ARM_t2LDRHpci); + break; + case ARM_t2LDRSHs: + MCInst_setOpcode(Inst, ARM_t2LDRSHpci); + break; + case ARM_t2LDRSBs: + MCInst_setOpcode(Inst, ARM_t2LDRSBpci); + break; + case ARM_t2LDRs: + MCInst_setOpcode(Inst, ARM_t2LDRpci); + break; + case ARM_t2PLDs: + MCInst_setOpcode(Inst, ARM_t2PLDpci); + break; + case ARM_t2PLIs: + MCInst_setOpcode(Inst, ARM_t2PLIpci); + break; + default: + return MCDisassembler_Fail; + } + + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRSHs: + return MCDisassembler_Fail; + case ARM_t2LDRHs: + MCInst_setOpcode(Inst, ARM_t2PLDWs); + break; + case ARM_t2LDRSBs: + MCInst_setOpcode(Inst, ARM_t2PLIs); + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDs: + break; + case ARM_t2PLIs: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + case ARM_t2PLDWs: + if (!hasV7Ops || !hasMP) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + addrmode = fieldFromInstruction_4(Insn, 4, 2); + addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2; + addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6; + + if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, + uint64_t Address, const void* Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned U = fieldFromInstruction_4(Insn, 9, 1); + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + unsigned add = fieldFromInstruction_4(Insn, 9, 1); + bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); + bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); + + imm |= (U << 8); + imm |= (Rn << 9); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRi8: + MCInst_setOpcode(Inst, ARM_t2LDRpci); + break; + case ARM_t2LDRBi8: + MCInst_setOpcode(Inst, ARM_t2LDRBpci); + break; + case ARM_t2LDRSBi8: + MCInst_setOpcode(Inst, ARM_t2LDRSBpci); + break; + case ARM_t2LDRHi8: + MCInst_setOpcode(Inst, ARM_t2LDRHpci); + break; + case ARM_t2LDRSHi8: + MCInst_setOpcode(Inst, ARM_t2LDRSHpci); + break; + case ARM_t2PLDi8: + MCInst_setOpcode(Inst, ARM_t2PLDpci); + break; + case ARM_t2PLIi8: + MCInst_setOpcode(Inst, ARM_t2PLIpci); + break; + default: + return MCDisassembler_Fail; + } + + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRSHi8: + return MCDisassembler_Fail; + case ARM_t2LDRHi8: + if (!add) + MCInst_setOpcode(Inst, ARM_t2PLDWi8); + break; + case ARM_t2LDRSBi8: + MCInst_setOpcode(Inst, ARM_t2PLIi8); + break; + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDi8: + break; + case ARM_t2PLIi8: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + case ARM_t2PLDWi8: + if (!hasV7Ops || !hasMP) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, + uint64_t Address, const void* Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); + bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); + + imm |= (Rn << 13); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRi12: + MCInst_setOpcode(Inst, ARM_t2LDRpci); + break; + case ARM_t2LDRHi12: + MCInst_setOpcode(Inst, ARM_t2LDRHpci); + break; + case ARM_t2LDRSHi12: + MCInst_setOpcode(Inst, ARM_t2LDRSHpci); + break; + case ARM_t2LDRBi12: + MCInst_setOpcode(Inst, ARM_t2LDRBpci); + break; + case ARM_t2LDRSBi12: + MCInst_setOpcode(Inst, ARM_t2LDRSBpci); + break; + case ARM_t2PLDi12: + MCInst_setOpcode(Inst, ARM_t2PLDpci); + break; + case ARM_t2PLIi12: + MCInst_setOpcode(Inst, ARM_t2PLIpci); + break; + default: + return MCDisassembler_Fail; + } + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRSHi12: + return MCDisassembler_Fail; + case ARM_t2LDRHi12: + MCInst_setOpcode(Inst, ARM_t2PLDWi12); + break; + case ARM_t2LDRSBi12: + MCInst_setOpcode(Inst, ARM_t2PLIi12); + break; + default: + break; + } + } + + switch (MCInst_getOpcode(Inst)) { + case ARM_t2PLDi12: + break; + case ARM_t2PLIi12: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + case ARM_t2PLDWi12: + if (!hasV7Ops || !hasMP) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, + uint64_t Address, const void* Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 8); + imm |= (Rn << 9); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRT: + MCInst_setOpcode(Inst, ARM_t2LDRpci); + break; + case ARM_t2LDRBT: + MCInst_setOpcode(Inst, ARM_t2LDRBpci); + break; + case ARM_t2LDRHT: + MCInst_setOpcode(Inst, ARM_t2LDRHpci); + break; + case ARM_t2LDRSBT: + MCInst_setOpcode(Inst, ARM_t2LDRSBpci); + break; + case ARM_t2LDRSHT: + MCInst_setOpcode(Inst, ARM_t2LDRSHpci); + break; + default: + return MCDisassembler_Fail; + } + + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, + uint64_t Address, const void* Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + int imm = fieldFromInstruction_4(Insn, 0, 12); + bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); + + if (Rt == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRBpci: + case ARM_t2LDRHpci: + MCInst_setOpcode(Inst, ARM_t2PLDpci); + break; + case ARM_t2LDRSBpci: + MCInst_setOpcode(Inst, ARM_t2PLIpci); + break; + case ARM_t2LDRSHpci: + return MCDisassembler_Fail; + default: + break; + } + } + + switch(MCInst_getOpcode(Inst)) { + case ARM_t2PLDpci: + break; + case ARM_t2PLIpci: + if (!hasV7Ops) + return MCDisassembler_Fail; + break; + default: + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!U) { + // Special case for #-0. + if (imm == 0) + imm = INT32_MIN; + else + imm = -imm; + } + + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (Val == 0) + MCOperand_CreateImm0(Inst, INT32_MIN); + else { + int imm = Val & 0xFF; + + if (!(Val & 0x100)) imm *= -1; + + MCOperand_CreateImm0(Inst, imm * 4); + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 9); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Val, 8, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + int imm = Val & 0xFF; + + if (Val == 0) + imm = INT32_MIN; + else if (!(Val & 0x100)) + imm *= -1; + + MCOperand_CreateImm0(Inst, imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + unsigned Rn = fieldFromInstruction_4(Val, 9, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 9); + + // Thumb stores cannot use PC as dest register. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2STRT: + case ARM_t2STRBT: + case ARM_t2STRHT: + case ARM_t2STRi8: + case ARM_t2STRHi8: + case ARM_t2STRBi8: + if (Rn == 15) + return MCDisassembler_Fail; + break; + default: + break; + } + + // Some instructions always use an additive offset. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDRT: + case ARM_t2LDRBT: + case ARM_t2LDRHT: + case ARM_t2LDRSBT: + case ARM_t2LDRSHT: + case ARM_t2STRT: + case ARM_t2STRBT: + case ARM_t2STRHT: + imm |= 0x100; + break; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned load; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned addr = fieldFromInstruction_4(Insn, 0, 8); + addr |= fieldFromInstruction_4(Insn, 9, 1) << 8; + addr |= Rn << 9; + load = fieldFromInstruction_4(Insn, 20, 1); + + if (Rn == 15) { + switch (MCInst_getOpcode(Inst)) { + case ARM_t2LDR_PRE: + case ARM_t2LDR_POST: + MCInst_setOpcode(Inst, ARM_t2LDRpci); + break; + case ARM_t2LDRB_PRE: + case ARM_t2LDRB_POST: + MCInst_setOpcode(Inst, ARM_t2LDRBpci); + break; + case ARM_t2LDRH_PRE: + case ARM_t2LDRH_POST: + MCInst_setOpcode(Inst, ARM_t2LDRHpci); + break; + case ARM_t2LDRSB_PRE: + case ARM_t2LDRSB_POST: + if (Rt == 15) + MCInst_setOpcode(Inst, ARM_t2PLIpci); + else + MCInst_setOpcode(Inst, ARM_t2LDRSBpci); + break; + case ARM_t2LDRSH_PRE: + case ARM_t2LDRSH_POST: + MCInst_setOpcode(Inst, ARM_t2LDRSHpci); + break; + default: + return MCDisassembler_Fail; + } + + return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); + } + + if (!load) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (load) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Val, 13, 4); + unsigned imm = fieldFromInstruction_4(Val, 0, 12); + + // Thumb stores cannot use PC as dest register. + switch (MCInst_getOpcode(Inst)) { + case ARM_t2STRi12: + case ARM_t2STRBi12: + case ARM_t2STRHi12: + if (Rn == 15) + return MCDisassembler_Fail; + default: + break; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, imm); + + return S; +} + +static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned imm = fieldFromInstruction_2(Insn, 0, 7); + + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateImm0(Inst, imm); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (MCInst_getOpcode(Inst) == ARM_tADDrSP) { + unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3); + Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateReg0(Inst, ARM_SP); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) + return MCDisassembler_Fail; + } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) { + unsigned Rm = fieldFromInstruction_2(Insn, 3, 4); + + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateReg0(Inst, ARM_SP); + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } + + return S; +} + +static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2; + unsigned flags = fieldFromInstruction_2(Insn, 0, 3); + + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, flags); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned add = fieldFromInstruction_4(Insn, 4, 1); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, add); + + return S; +} + +static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + // Val is passed in as S:J1:J2:imm10H:imm10L:'0' + // Note only one trailing zero not two. Also the J1 and J2 values are from + // the encoded instruction. So here change to I1 and I2 values via: + // I1 = NOT(J1 EOR S); + // I2 = NOT(J2 EOR S); + // and build the imm32 with two trailing zeros as documented: + // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); + unsigned S = (Val >> 23) & 1; + unsigned J1 = (Val >> 22) & 1; + unsigned J2 = (Val >> 21) & 1; + unsigned I1 = !(J1 ^ S); + unsigned I2 = !(J2 ^ S); + unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); + int imm32 = SignExtend32(tmp << 1, 25); + + MCOperand_CreateImm0(Inst, imm32); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (Val == 0xA || Val == 0xB) + return MCDisassembler_Fail; + + if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && !(Val == 14 || Val == 15)) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + + if (Rn == ARM_SP) S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned brtarget; + unsigned pred = fieldFromInstruction_4(Insn, 22, 4); + + if (pred == 0xE || pred == 0xF) { + unsigned imm; + unsigned opc = fieldFromInstruction_4(Insn, 4, 28); + switch (opc) { + default: + return MCDisassembler_Fail; + case 0xf3bf8f4: + MCInst_setOpcode(Inst, ARM_t2DSB); + break; + case 0xf3bf8f5: + MCInst_setOpcode(Inst, ARM_t2DMB); + break; + case 0xf3bf8f6: + MCInst_setOpcode(Inst, ARM_t2ISB); + break; + } + + imm = fieldFromInstruction_4(Insn, 0, 4); + return DecodeMemBarrierOption(Inst, imm, Address, Decoder); + } + + brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1; + brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19; + brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18; + brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12; + brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20; + + if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +// Decode a shifted immediate operand. These basically consist +// of an 8-bit value, and a 4-bit directive that specifies either +// a splat operation or a rotation. +static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + unsigned ctrl = fieldFromInstruction_4(Val, 10, 2); + + if (ctrl == 0) { + unsigned byte = fieldFromInstruction_4(Val, 8, 2); + unsigned imm = fieldFromInstruction_4(Val, 0, 8); + + switch (byte) { + case 0: + MCOperand_CreateImm0(Inst, imm); + break; + case 1: + MCOperand_CreateImm0(Inst, (imm << 16) | imm); + break; + case 2: + MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8)); + break; + case 3: + MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm); + break; + } + } else { + unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80; + unsigned rot = fieldFromInstruction_4(Val, 7, 5); + unsigned imm = (unrot >> rot) | (unrot << ((32 - rot) & 31)); + + MCOperand_CreateImm0(Inst, imm); + } + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + // Val is passed in as S:J1:J2:imm10:imm11 + // Note no trailing zero after imm11. Also the J1 and J2 values are from + // the encoded instruction. So here change to I1 and I2 values via: + // I1 = NOT(J1 EOR S); + // I2 = NOT(J2 EOR S); + // and build the imm32 with one trailing zero as documented: + // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); + unsigned S = (Val >> 23) & 1; + unsigned J1 = (Val >> 22) & 1; + unsigned J2 = (Val >> 21) & 1; + unsigned I1 = !(J1 ^ S); + unsigned I2 = !(J2 ^ S); + unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); + int imm32 = SignExtend32(tmp << 1, 25); + + MCOperand_CreateImm0(Inst, imm32); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (Val & ~0xf) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + if (Val & ~0xf) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + + if (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass)) { + unsigned ValLow = Val & 0xff; + + // Validate the SYSm value first. + switch (ValLow) { + case 0: // apsr + case 1: // iapsr + case 2: // eapsr + case 3: // xpsr + case 5: // ipsr + case 6: // epsr + case 7: // iepsr + case 8: // msp + case 9: // psp + case 16: // primask + case 20: // control + break; + case 17: // basepri + case 18: // basepri_max + case 19: // faultmask + if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)) + // Values basepri, basepri_max and faultmask are only valid for v7m. + return MCDisassembler_Fail; + break; + case 0x8a: // msplim_ns + case 0x8b: // psplim_ns + case 0x91: // basepri_ns + case 0x93: // faultmask_ns + if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8MMainlineOps)) + return MCDisassembler_Fail; + // LLVM_FALLTHROUGH; + case 10: // msplim + case 11: // psplim + case 0x88: // msp_ns + case 0x89: // psp_ns + case 0x90: // primask_ns + case 0x94: // control_ns + case 0x98: // sp_ns + if (!ARM_getFeatureBits(Inst->csh->mode, ARM_Feature8MSecExt)) + return MCDisassembler_Fail; + break; + default: + return MCDisassembler_SoftFail; + } + + if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) { + unsigned Mask = fieldFromInstruction_4(Val, 10, 2); + if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)) { + // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are + // unpredictable. + if (Mask != 2) + S = MCDisassembler_SoftFail; + } else { + // The ARMv7-M architecture stores an additional 2-bit mask value in + // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and + // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if + // the NZCVQ bits should be moved by the instruction. Bit mask{0} + // indicates the move for the GE{3:0} bits, the mask{0} bit can be set + // only if the processor includes the DSP extension. + if (Mask == 0 || (Mask != 2 && ValLow > 3) || + (!ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDSP) && (Mask & 1))) + S = MCDisassembler_SoftFail; + } + } + } else { + // A/R class + if (Val == 0) + return MCDisassembler_Fail; + } + + MCOperand_CreateImm0(Inst, Val); + return S; +} + +static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + unsigned R = fieldFromInstruction_4(Val, 5, 1); + unsigned SysM = fieldFromInstruction_4(Val, 0, 5); + + // The table of encodings for these banked registers comes from B9.2.3 of the + // ARM ARM. There are patterns, but nothing regular enough to make this logic + // neater. So by fiat, these values are UNPREDICTABLE: + if (!lookupBankedRegByEncoding((R << 5) | SysM)) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt + 1) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned pred; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned pred, Rm; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + pred = fieldFromInstruction_4(Insn, 28, 4); + Rm = fieldFromInstruction_4(Insn, 0, 4); + + if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; + if (Rm == 0xF) S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned pred; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned pred; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned imm = fieldFromInstruction_4(Insn, 0, 12); + imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; + imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; + pred = fieldFromInstruction_4(Insn, 28, 4); + + if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned size, align = 0, index = 0; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + size = fieldFromInstruction_4(Insn, 10, 2); + + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 6, 1)) + return MCDisassembler_Fail; // UNDEFINED + + index = fieldFromInstruction_4(Insn, 7, 1); + + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0 : + align = 0; break; + case 3: + align = 4; break; + default: + return MCDisassembler_Fail; + } + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned size, align = 0, index = 0; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + size = fieldFromInstruction_4(Insn, 10, 2); + + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 6, 1)) + return MCDisassembler_Fail; // UNDEFINED + + index = fieldFromInstruction_4(Insn, 7, 1); + + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; break; + case 3: + align = 4; break; + default: + return MCDisassembler_Fail; + } + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned size, align = 0, index = 0, inc = 1; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + size = fieldFromInstruction_4(Insn, 10, 2); + + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + index = fieldFromInstruction_4(Insn, 5, 3); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 1: + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 4, 1) != 0) + align = 8; + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned size, align = 0, index = 0, inc = 1; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + size = fieldFromInstruction_4(Insn, 10, 2); + + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + index = fieldFromInstruction_4(Insn, 5, 3); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 2; + break; + case 1: + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 5, 1)) + return MCDisassembler_Fail; // UNDEFINED + + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 4, 1) != 0) + align = 8; + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned size, align = 0, index = 0, inc = 1; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + size = fieldFromInstruction_4(Insn, 10, 2); + + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 4, 2)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned size, align = 0, index = 0, inc = 1; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + size = fieldFromInstruction_4(Insn, 10, 2); + + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + if (fieldFromInstruction_4(Insn, 4, 2)) + return MCDisassembler_Fail; // UNDEFINED + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned size, align = 0, index = 0, inc = 1; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + size = fieldFromInstruction_4(Insn, 10, 2); + + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 8; + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; break; + case 3: + return MCDisassembler_Fail; + default: + align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; + } + + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned size, align = 0, index = 0, inc = 1; + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); + Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; + size = fieldFromInstruction_4(Insn, 10, 2); + + switch (size) { + default: + return MCDisassembler_Fail; + case 0: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 4; + index = fieldFromInstruction_4(Insn, 5, 3); + break; + case 1: + if (fieldFromInstruction_4(Insn, 4, 1)) + align = 8; + index = fieldFromInstruction_4(Insn, 6, 2); + if (fieldFromInstruction_4(Insn, 5, 1)) + inc = 2; + break; + case 2: + switch (fieldFromInstruction_4(Insn, 4, 2)) { + case 0: + align = 0; break; + case 3: + return MCDisassembler_Fail; + default: + align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; + } + + index = fieldFromInstruction_4(Insn, 7, 1); + if (fieldFromInstruction_4(Insn, 6, 1)) + inc = 2; + break; + } + + if (Rm != 0xF) { // Writeback + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, align); + + if (Rm != 0xF) { + if (Rm != 0xD) { + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + } else + MCOperand_CreateReg0(Inst, 0); + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, index); + + return S; +} + +static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; + + if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); + unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; + + if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned pred = fieldFromInstruction_4(Insn, 4, 4); + unsigned mask = fieldFromInstruction_4(Insn, 0, 4); + + if (pred == 0xF) { + pred = 0xE; + S = MCDisassembler_SoftFail; + } + + if (mask == 0x0) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, pred); + MCOperand_CreateImm0(Inst, mask); + + return S; +} + +static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned addr = fieldFromInstruction_4(Insn, 0, 8); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + bool writeback = (W == 1) | (P == 0); + + addr |= (U << 8) | (Rn << 9); + + if (writeback && (Rn == Rt || Rn == Rt2)) + Check(&S, MCDisassembler_SoftFail); + + if (Rt == Rt2) + Check(&S, MCDisassembler_SoftFail); + + // Rt + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + // Rt2 + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + + // Writeback operand + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + // addr + if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned addr = fieldFromInstruction_4(Insn, 0, 8); + unsigned W = fieldFromInstruction_4(Insn, 21, 1); + unsigned U = fieldFromInstruction_4(Insn, 23, 1); + unsigned P = fieldFromInstruction_4(Insn, 24, 1); + bool writeback = (W == 1) | (P == 0); + + addr |= (U << 8) | (Rn << 9); + + if (writeback && (Rn == Rt || Rn == Rt2)) + Check(&S, MCDisassembler_SoftFail); + + // Writeback operand + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + // Rt + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + // Rt2 + if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + + // addr + if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, + uint64_t Address, const void *Decoder) +{ + unsigned Val; + unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); + unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); + + if (sign1 != sign2) return MCDisassembler_Fail; + + Val = fieldFromInstruction_4(Insn, 0, 8); + Val |= fieldFromInstruction_4(Insn, 12, 3) << 8; + Val |= fieldFromInstruction_4(Insn, 26, 1) << 11; + Val |= sign1 << 12; + + MCOperand_CreateImm0(Inst, SignExtend32(Val, 13)); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, + uint64_t Address, const void *Decoder) +{ + // Shift of "asr #32" is not allowed in Thumb2 mode. + if (Val == 0x20) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, Val); + + return MCDisassembler_Success; +} + +static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S; + unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); + unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); + unsigned pred = fieldFromInstruction_4(Insn, 28, 4); + + if (pred == 0xF) + return DecodeCPSInstruction(Inst, Insn, Address, Decoder); + + S = MCDisassembler_Success; + + if (Rt == Rn || Rn == Rt2) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16); + unsigned Vm, imm, cmode, op; + unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); + + Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); + Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); + Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); + imm = fieldFromInstruction_4(Insn, 16, 6); + cmode = fieldFromInstruction_4(Insn, 8, 4); + op = fieldFromInstruction_4(Insn, 5, 1); + + // If the top 3 bits of imm are clear, this is a VMOV (immediate) + if (!(imm & 0x38)) { + if (cmode == 0xF) { + if (op == 1) return MCDisassembler_Fail; + MCInst_setOpcode(Inst, ARM_VMOVv2f32); + } + + if (hasFullFP16) { + if (cmode == 0xE) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMOVv1i64); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv8i8); + } + } + + if (cmode == 0xD) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMVNv2i32); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv2i32); + } + } + + if (cmode == 0xC) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMVNv2i32); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv2i32); + } + } + } + + return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); + } + + if (!(imm & 0x20)) return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, 64 - imm); + + return S; +} + +static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16); + unsigned Vm, imm, cmode, op; + unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); + + Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); + Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); + Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); + imm = fieldFromInstruction_4(Insn, 16, 6); + cmode = fieldFromInstruction_4(Insn, 8, 4); + op = fieldFromInstruction_4(Insn, 5, 1); + + // VMOVv4f32 is ambiguous with these decodings. + if (!(imm & 0x38) && cmode == 0xF) { + if (op == 1) return MCDisassembler_Fail; + MCInst_setOpcode(Inst, ARM_VMOVv4f32); + return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); + } + + // If the top 3 bits of imm are clear, this is a VMOV (immediate) + if (!(imm & 0x38)) { + if (cmode == 0xF) { + if (op == 1) return MCDisassembler_Fail; + MCInst_setOpcode(Inst, ARM_VMOVv4f32); + } + + if (hasFullFP16) { + if (cmode == 0xE) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMOVv2i64); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv16i8); + } + } + + if (cmode == 0xD) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMVNv4i32); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv4i32); + } + } + + if (cmode == 0xC) { + if (op == 1) { + MCInst_setOpcode(Inst, ARM_VMVNv4i32); + } else { + MCInst_setOpcode(Inst, ARM_VMOVv4i32); + } + } + } + + return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); + } + + if (!(imm & 0x20)) return MCDisassembler_Fail; + + if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) + return MCDisassembler_Fail; + + MCOperand_CreateImm0(Inst, 64 - imm); + + return S; +} + +static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); + unsigned Vn = (fieldFromInstruction_4(Insn, 16, 4) << 0); + unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); + unsigned q = (fieldFromInstruction_4(Insn, 6, 1) << 0); + unsigned rotate = (fieldFromInstruction_4(Insn, 20, 2) << 0); + + Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); + Vn |= (fieldFromInstruction_4(Insn, 7, 1) << 4); + Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); + + if (q) { + if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeQPRRegisterClass(Inst, Vn, Address, Decoder))) + return MCDisassembler_Fail; + } else { + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vn, Address, Decoder))) + return MCDisassembler_Fail; + } + + if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) + return MCDisassembler_Fail; + + // The lane index does not have any bits in the encoding, because it can only + // be 0. + MCOperand_CreateImm0(Inst, 0); + MCOperand_CreateImm0(Inst, rotate); + + return S; +} + +static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus S = MCDisassembler_Success; + unsigned Cond; + unsigned Rn = fieldFromInstruction_4(Val, 16, 4); + unsigned Rt = fieldFromInstruction_4(Val, 12, 4); + unsigned Rm = fieldFromInstruction_4(Val, 0, 4); + + Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4); + Cond = fieldFromInstruction_4(Val, 28, 4); + + if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt) + S = MCDisassembler_SoftFail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) + return MCDisassembler_Fail; + + return S; +} + +static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus result = MCDisassembler_Success; + unsigned CRm = fieldFromInstruction_4(Val, 0, 4); + unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); + unsigned cop = fieldFromInstruction_4(Val, 8, 4); + unsigned Rt = fieldFromInstruction_4(Val, 12, 4); + unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4); + + if ((cop & ~0x1) == 0xa) + return MCDisassembler_Fail; + + if (Rt == Rt2) + result = MCDisassembler_SoftFail; + + // We have to check if the instruction is MRRC2 + // or MCRR2 when constructing the operands for + // Inst. Reason is because MRRC2 stores to two + // registers so it's tablegen desc has has two + // outputs whereas MCRR doesn't store to any + // registers so all of it's operands are listed + // as inputs, therefore the operand order for + // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] + // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] + + if (MCInst_getOpcode(Inst) == ARM_MRRC2) { + if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + } + + MCOperand_CreateImm0(Inst, cop); + MCOperand_CreateImm0(Inst, opc1); + + if (MCInst_getOpcode(Inst) == ARM_MCRR2) { + if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler_Fail; + + if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler_Fail; + } + + MCOperand_CreateImm0(Inst, CRm); + + return result; +} + +static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, + uint64_t Address, const void *Decoder) +{ + DecodeStatus result = MCDisassembler_Success; + bool HasV8Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops); + unsigned Rt = fieldFromInstruction_4(Val, 12, 4); + + if ((Inst->csh->mode & CS_MODE_THUMB) && !HasV8Ops) { + if (Rt == 13 || Rt == 15) + result = MCDisassembler_SoftFail; + + Check(&result, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); + } else + Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); + + if (Inst->csh->mode & CS_MODE_THUMB) { + MCOperand_CreateImm0(Inst, ARMCC_AL); + MCOperand_CreateReg0(Inst, 0); + } else { + unsigned pred = fieldFromInstruction_4(Val, 28, 4); + if (!Check(&result, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler_Fail; + } + + return result; +} + +#endif diff --git a/capstone/arch/ARM/ARMDisassembler.h b/capstone/arch/ARM/ARMDisassembler.h new file mode 100644 index 000000000..35e75c9c9 --- /dev/null +++ b/capstone/arch/ARM/ARMDisassembler.h @@ -0,0 +1,18 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +#ifndef CS_ARMDISASSEMBLER_H +#define CS_ARMDISASSEMBLER_H + +#include "capstone/capstone.h" +#include "../../MCRegisterInfo.h" + +void ARM_init(MCRegisterInfo *MRI); + +bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); + +bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); + +bool ARM_getFeatureBits(unsigned int mode, unsigned int feature); + +#endif diff --git a/capstone/arch/ARM/ARMGenAsmWriter.inc b/capstone/arch/ARM/ARMGenAsmWriter.inc new file mode 100644 index 000000000..78ea52ff4 --- /dev/null +++ b/capstone/arch/ARM/ARMGenAsmWriter.inc @@ -0,0 +1,9545 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Assembly Writer Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +/// printInstruction - This method is automatically generated by tablegen +/// from the instruction set description. +static void printInstruction(MCInst *MI, SStream *O) +{ +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', '.', '3', '2', 9, 0, + /* 12 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', '.', '3', '2', 9, 0, + /* 26 */ 's', 'h', 'a', '1', 's', 'u', '1', '.', '3', '2', 9, 0, + /* 38 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', '.', '3', '2', 9, 0, + /* 52 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', '.', '3', '2', 9, 0, + /* 65 */ 's', 'h', 'a', '1', 'c', '.', '3', '2', 9, 0, + /* 75 */ 's', 'h', 'a', '1', 'h', '.', '3', '2', 9, 0, + /* 85 */ 's', 'h', 'a', '2', '5', '6', 'h', '.', '3', '2', 9, 0, + /* 97 */ 's', 'h', 'a', '1', 'm', '.', '3', '2', 9, 0, + /* 107 */ 's', 'h', 'a', '1', 'p', '.', '3', '2', 9, 0, + /* 117 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, + /* 132 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, + /* 147 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, + /* 162 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, + /* 177 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, + /* 192 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, + /* 207 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, + /* 222 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, + /* 237 */ 'v', 'c', 'm', 'l', 'a', '.', 'f', '3', '2', 9, 0, + /* 248 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '3', '2', 9, 0, + /* 260 */ 'v', 'c', 'a', 'd', 'd', '.', 'f', '3', '2', 9, 0, + /* 271 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '3', '2', 9, 0, + /* 283 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '3', '2', 9, 0, + /* 295 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '3', '2', 9, 0, + /* 307 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '3', '2', 9, 0, + /* 319 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '3', '2', 9, 0, + /* 331 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '3', '2', 9, 0, + /* 343 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '3', '2', 9, 0, + /* 355 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '3', '2', 9, 0, + /* 367 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '3', '2', 9, 0, + /* 379 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '3', '2', 9, 0, + /* 391 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '3', '2', 9, 0, + /* 403 */ 'l', 'd', 'c', '2', 9, 0, + /* 409 */ 'm', 'r', 'c', '2', 9, 0, + /* 415 */ 'm', 'r', 'r', 'c', '2', 9, 0, + /* 422 */ 's', 't', 'c', '2', 9, 0, + /* 428 */ 'c', 'd', 'p', '2', 9, 0, + /* 434 */ 'm', 'c', 'r', '2', 9, 0, + /* 440 */ 'm', 'c', 'r', 'r', '2', 9, 0, + /* 447 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, + /* 462 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, + /* 477 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, + /* 492 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, + /* 507 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, + /* 522 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, + /* 537 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, + /* 552 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, + /* 567 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '6', '4', 9, 0, + /* 579 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '6', '4', 9, 0, + /* 591 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '6', '4', 9, 0, + /* 603 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '6', '4', 9, 0, + /* 615 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '6', '4', 9, 0, + /* 627 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '6', '4', 9, 0, + /* 639 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '6', '4', 9, 0, + /* 651 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '6', '4', 9, 0, + /* 663 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '6', '4', 9, 0, + /* 675 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '6', '4', 9, 0, + /* 687 */ 'v', 'm', 'u', 'l', 'l', '.', 'p', '6', '4', 9, 0, + /* 698 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, + /* 713 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, + /* 728 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, + /* 743 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, + /* 758 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, + /* 773 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, + /* 788 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, + /* 803 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, + /* 818 */ 'v', 'c', 'v', 't', 'a', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, + /* 833 */ 'v', 'c', 'v', 't', 'm', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, + /* 848 */ 'v', 'c', 'v', 't', 'n', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, + /* 863 */ 'v', 'c', 'v', 't', 'p', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, + /* 878 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, + /* 893 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, + /* 908 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, + /* 923 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, + /* 938 */ 'v', 'c', 'm', 'l', 'a', '.', 'f', '1', '6', 9, 0, + /* 949 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '1', '6', 9, 0, + /* 961 */ 'v', 'c', 'a', 'd', 'd', '.', 'f', '1', '6', 9, 0, + /* 972 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '1', '6', 9, 0, + /* 984 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '1', '6', 9, 0, + /* 996 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '1', '6', 9, 0, + /* 1008 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '1', '6', 9, 0, + /* 1020 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '1', '6', 9, 0, + /* 1032 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '1', '6', 9, 0, + /* 1044 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '1', '6', 9, 0, + /* 1056 */ 'v', 'i', 'n', 's', '.', 'f', '1', '6', 9, 0, + /* 1066 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '1', '6', 9, 0, + /* 1078 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '1', '6', 9, 0, + /* 1090 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '1', '6', 9, 0, + /* 1102 */ 'v', 'm', 'o', 'v', 'x', '.', 'f', '1', '6', 9, 0, + /* 1113 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '1', '6', 9, 0, + /* 1125 */ 'a', 'e', 's', 'i', 'm', 'c', '.', '8', 9, 0, + /* 1135 */ 'a', 'e', 's', 'm', 'c', '.', '8', 9, 0, + /* 1144 */ 'a', 'e', 's', 'd', '.', '8', 9, 0, + /* 1152 */ 'a', 'e', 's', 'e', '.', '8', 9, 0, + /* 1160 */ 'v', 's', 'd', 'o', 't', '.', 's', '8', 9, 0, + /* 1170 */ 'v', 'u', 'd', 'o', 't', '.', 'u', '8', 9, 0, + /* 1180 */ 'r', 'f', 'e', 'd', 'a', 9, 0, + /* 1187 */ 'r', 'f', 'e', 'i', 'a', 9, 0, + /* 1194 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, + /* 1202 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, + /* 1211 */ 'r', 'f', 'e', 'd', 'b', 9, 0, + /* 1218 */ 'r', 'f', 'e', 'i', 'b', 9, 0, + /* 1225 */ 'd', 'm', 'b', 9, 0, + /* 1230 */ 'd', 's', 'b', 9, 0, + /* 1235 */ 'i', 's', 'b', 9, 0, + /* 1240 */ 't', 's', 'b', 9, 0, + /* 1245 */ 'h', 'v', 'c', 9, 0, + /* 1250 */ 'p', 'l', 'd', 9, 0, + /* 1255 */ 's', 'e', 't', 'e', 'n', 'd', 9, 0, + /* 1263 */ 'u', 'd', 'f', 9, 0, + /* 1268 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, + /* 1276 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, + /* 1285 */ 'p', 'l', 'i', 9, 0, + /* 1290 */ 'l', 'd', 'c', '2', 'l', 9, 0, + /* 1297 */ 's', 't', 'c', '2', 'l', 9, 0, + /* 1304 */ 'b', 'l', 9, 0, + /* 1308 */ 's', 'e', 't', 'p', 'a', 'n', 9, 0, + /* 1316 */ 'c', 'p', 's', 9, 0, + /* 1321 */ 'm', 'o', 'v', 's', 9, 0, + /* 1327 */ 'h', 'l', 't', 9, 0, + /* 1332 */ 'b', 'k', 'p', 't', 9, 0, + /* 1338 */ 'h', 'v', 'c', '.', 'w', 9, 0, + /* 1345 */ 'u', 'd', 'f', '.', 'w', 9, 0, + /* 1352 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, + /* 1360 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, + /* 1369 */ 'p', 'l', 'd', 'w', 9, 0, + /* 1375 */ 'b', 'x', 9, 0, + /* 1379 */ 'b', 'l', 'x', 9, 0, + /* 1384 */ 'c', 'b', 'z', 9, 0, + /* 1389 */ 'c', 'b', 'n', 'z', 9, 0, + /* 1395 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', '!', ',', 32, 0, + /* 1407 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', '!', ',', 32, 0, + /* 1419 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', '!', ',', 32, 0, + /* 1431 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', '!', ',', 32, 0, + /* 1443 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', ',', 32, 0, + /* 1454 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', ',', 32, 0, + /* 1465 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', ',', 32, 0, + /* 1476 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', ',', 32, 0, + /* 1487 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, + /* 1518 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 1542 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 1567 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, + /* 1590 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, + /* 1613 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, + /* 1635 */ '_', '_', 'b', 'r', 'k', 'd', 'i', 'v', '0', 0, + /* 1645 */ 'v', 'l', 'd', '1', 0, + /* 1650 */ 'd', 'c', 'p', 's', '1', 0, + /* 1656 */ 'v', 's', 't', '1', 0, + /* 1661 */ 'v', 'r', 'e', 'v', '3', '2', 0, + /* 1668 */ 'l', 'd', 'c', '2', 0, + /* 1673 */ 'm', 'r', 'c', '2', 0, + /* 1678 */ 'm', 'r', 'r', 'c', '2', 0, + /* 1684 */ 's', 't', 'c', '2', 0, + /* 1689 */ 'v', 'l', 'd', '2', 0, + /* 1694 */ 'c', 'd', 'p', '2', 0, + /* 1699 */ 'm', 'c', 'r', '2', 0, + /* 1704 */ 'm', 'c', 'r', 'r', '2', 0, + /* 1710 */ 'd', 'c', 'p', 's', '2', 0, + /* 1716 */ 'v', 's', 't', '2', 0, + /* 1721 */ 'v', 'l', 'd', '3', 0, + /* 1726 */ 'd', 'c', 'p', 's', '3', 0, + /* 1732 */ 'v', 's', 't', '3', 0, + /* 1737 */ 'v', 'r', 'e', 'v', '6', '4', 0, + /* 1744 */ 'v', 'l', 'd', '4', 0, + /* 1749 */ 'v', 's', 't', '4', 0, + /* 1754 */ 's', 'x', 't', 'a', 'b', '1', '6', 0, + /* 1762 */ 'u', 'x', 't', 'a', 'b', '1', '6', 0, + /* 1770 */ 's', 'x', 't', 'b', '1', '6', 0, + /* 1777 */ 'u', 'x', 't', 'b', '1', '6', 0, + /* 1784 */ 's', 'h', 's', 'u', 'b', '1', '6', 0, + /* 1792 */ 'u', 'h', 's', 'u', 'b', '1', '6', 0, + /* 1800 */ 'u', 'q', 's', 'u', 'b', '1', '6', 0, + /* 1808 */ 's', 's', 'u', 'b', '1', '6', 0, + /* 1815 */ 'u', 's', 'u', 'b', '1', '6', 0, + /* 1822 */ 's', 'h', 'a', 'd', 'd', '1', '6', 0, + /* 1830 */ 'u', 'h', 'a', 'd', 'd', '1', '6', 0, + /* 1838 */ 'u', 'q', 'a', 'd', 'd', '1', '6', 0, + /* 1846 */ 's', 'a', 'd', 'd', '1', '6', 0, + /* 1853 */ 'u', 'a', 'd', 'd', '1', '6', 0, + /* 1860 */ 's', 's', 'a', 't', '1', '6', 0, + /* 1867 */ 'u', 's', 'a', 't', '1', '6', 0, + /* 1874 */ 'v', 'r', 'e', 'v', '1', '6', 0, + /* 1881 */ 'u', 's', 'a', 'd', 'a', '8', 0, + /* 1888 */ 's', 'h', 's', 'u', 'b', '8', 0, + /* 1895 */ 'u', 'h', 's', 'u', 'b', '8', 0, + /* 1902 */ 'u', 'q', 's', 'u', 'b', '8', 0, + /* 1909 */ 's', 's', 'u', 'b', '8', 0, + /* 1915 */ 'u', 's', 'u', 'b', '8', 0, + /* 1921 */ 'u', 's', 'a', 'd', '8', 0, + /* 1927 */ 's', 'h', 'a', 'd', 'd', '8', 0, + /* 1934 */ 'u', 'h', 'a', 'd', 'd', '8', 0, + /* 1941 */ 'u', 'q', 'a', 'd', 'd', '8', 0, + /* 1948 */ 's', 'a', 'd', 'd', '8', 0, + /* 1954 */ 'u', 'a', 'd', 'd', '8', 0, + /* 1960 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 1973 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 1980 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 1990 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, + /* 2000 */ '@', 32, 'C', 'O', 'M', 'P', 'I', 'L', 'E', 'R', 32, 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0, + /* 2019 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 2034 */ 'v', 'a', 'b', 'a', 0, + /* 2039 */ 'l', 'd', 'a', 0, + /* 2043 */ 'l', 'd', 'm', 'd', 'a', 0, + /* 2049 */ 's', 't', 'm', 'd', 'a', 0, + /* 2055 */ 'r', 'f', 'e', 'i', 'a', 0, + /* 2061 */ 'v', 'l', 'd', 'm', 'i', 'a', 0, + /* 2068 */ 'v', 's', 't', 'm', 'i', 'a', 0, + /* 2075 */ 's', 'r', 's', 'i', 'a', 0, + /* 2081 */ 's', 'm', 'm', 'l', 'a', 0, + /* 2087 */ 'v', 'n', 'm', 'l', 'a', 0, + /* 2093 */ 'v', 'm', 'l', 'a', 0, + /* 2098 */ 'v', 'f', 'm', 'a', 0, + /* 2103 */ 'v', 'f', 'n', 'm', 'a', 0, + /* 2109 */ 'v', 'r', 's', 'r', 'a', 0, + /* 2115 */ 'v', 's', 'r', 'a', 0, + /* 2120 */ 't', 't', 'a', 0, + /* 2124 */ 'l', 'd', 'a', 'b', 0, + /* 2129 */ 's', 'x', 't', 'a', 'b', 0, + /* 2135 */ 'u', 'x', 't', 'a', 'b', 0, + /* 2141 */ 's', 'm', 'l', 'a', 'b', 'b', 0, + /* 2148 */ 's', 'm', 'l', 'a', 'l', 'b', 'b', 0, + /* 2156 */ 's', 'm', 'u', 'l', 'b', 'b', 0, + /* 2163 */ 't', 'b', 'b', 0, + /* 2167 */ 'r', 'f', 'e', 'd', 'b', 0, + /* 2173 */ 'v', 'l', 'd', 'm', 'd', 'b', 0, + /* 2180 */ 'v', 's', 't', 'm', 'd', 'b', 0, + /* 2187 */ 's', 'r', 's', 'd', 'b', 0, + /* 2193 */ 'l', 'd', 'm', 'i', 'b', 0, + /* 2199 */ 's', 't', 'm', 'i', 'b', 0, + /* 2205 */ 's', 't', 'l', 'b', 0, + /* 2210 */ 'd', 'm', 'b', 0, + /* 2214 */ 's', 'w', 'p', 'b', 0, + /* 2219 */ 'l', 'd', 'r', 'b', 0, + /* 2224 */ 's', 't', 'r', 'b', 0, + /* 2229 */ 'd', 's', 'b', 0, + /* 2233 */ 'i', 's', 'b', 0, + /* 2237 */ 'l', 'd', 'r', 's', 'b', 0, + /* 2243 */ 't', 's', 'b', 0, + /* 2247 */ 's', 'm', 'l', 'a', 't', 'b', 0, + /* 2254 */ 'p', 'k', 'h', 't', 'b', 0, + /* 2260 */ 's', 'm', 'l', 'a', 'l', 't', 'b', 0, + /* 2268 */ 's', 'm', 'u', 'l', 't', 'b', 0, + /* 2275 */ 'v', 'c', 'v', 't', 'b', 0, + /* 2281 */ 's', 'x', 't', 'b', 0, + /* 2286 */ 'u', 'x', 't', 'b', 0, + /* 2291 */ 'q', 'd', 's', 'u', 'b', 0, + /* 2297 */ 'v', 'h', 's', 'u', 'b', 0, + /* 2303 */ 'v', 'q', 's', 'u', 'b', 0, + /* 2309 */ 'v', 's', 'u', 'b', 0, + /* 2314 */ 's', 'm', 'l', 'a', 'w', 'b', 0, + /* 2321 */ 's', 'm', 'u', 'l', 'w', 'b', 0, + /* 2328 */ 'l', 'd', 'a', 'e', 'x', 'b', 0, + /* 2335 */ 's', 't', 'l', 'e', 'x', 'b', 0, + /* 2342 */ 'l', 'd', 'r', 'e', 'x', 'b', 0, + /* 2349 */ 's', 't', 'r', 'e', 'x', 'b', 0, + /* 2356 */ 's', 'b', 'c', 0, + /* 2360 */ 'a', 'd', 'c', 0, + /* 2364 */ 'l', 'd', 'c', 0, + /* 2368 */ 'b', 'f', 'c', 0, + /* 2372 */ 'v', 'b', 'i', 'c', 0, + /* 2377 */ 's', 'm', 'c', 0, + /* 2381 */ 'm', 'r', 'c', 0, + /* 2385 */ 'm', 'r', 'r', 'c', 0, + /* 2390 */ 'r', 's', 'c', 0, + /* 2394 */ 's', 't', 'c', 0, + /* 2398 */ 's', 'v', 'c', 0, + /* 2402 */ 's', 'm', 'l', 'a', 'd', 0, + /* 2408 */ 's', 'm', 'u', 'a', 'd', 0, + /* 2414 */ 'v', 'a', 'b', 'd', 0, + /* 2419 */ 'q', 'd', 'a', 'd', 'd', 0, + /* 2425 */ 'v', 'r', 'h', 'a', 'd', 'd', 0, + /* 2432 */ 'v', 'h', 'a', 'd', 'd', 0, + /* 2438 */ 'v', 'p', 'a', 'd', 'd', 0, + /* 2444 */ 'v', 'q', 'a', 'd', 'd', 0, + /* 2450 */ 'v', 'a', 'd', 'd', 0, + /* 2455 */ 's', 'm', 'l', 'a', 'l', 'd', 0, + /* 2462 */ 'p', 'l', 'd', 0, + /* 2466 */ 's', 'm', 'l', 's', 'l', 'd', 0, + /* 2473 */ 'v', 'a', 'n', 'd', 0, + /* 2478 */ 'l', 'd', 'r', 'd', 0, + /* 2483 */ 's', 't', 'r', 'd', 0, + /* 2488 */ 's', 'm', 'l', 's', 'd', 0, + /* 2494 */ 's', 'm', 'u', 's', 'd', 0, + /* 2500 */ 'l', 'd', 'a', 'e', 'x', 'd', 0, + /* 2507 */ 's', 't', 'l', 'e', 'x', 'd', 0, + /* 2514 */ 'l', 'd', 'r', 'e', 'x', 'd', 0, + /* 2521 */ 's', 't', 'r', 'e', 'x', 'd', 0, + /* 2528 */ 'v', 'a', 'c', 'g', 'e', 0, + /* 2534 */ 'v', 'c', 'g', 'e', 0, + /* 2539 */ 'v', 'c', 'l', 'e', 0, + /* 2544 */ 'v', 'r', 'e', 'c', 'p', 'e', 0, + /* 2551 */ 'v', 'c', 'm', 'p', 'e', 0, + /* 2557 */ 'v', 'r', 's', 'q', 'r', 't', 'e', 0, + /* 2565 */ 'v', 'b', 'i', 'f', 0, + /* 2570 */ 'd', 'b', 'g', 0, + /* 2574 */ 'v', 'q', 'n', 'e', 'g', 0, + /* 2580 */ 'v', 'n', 'e', 'g', 0, + /* 2585 */ 's', 'g', 0, + /* 2588 */ 'l', 'd', 'a', 'h', 0, + /* 2593 */ 'v', 'q', 'r', 'd', 'm', 'l', 'a', 'h', 0, + /* 2602 */ 's', 'x', 't', 'a', 'h', 0, + /* 2608 */ 'u', 'x', 't', 'a', 'h', 0, + /* 2614 */ 't', 'b', 'h', 0, + /* 2618 */ 's', 't', 'l', 'h', 0, + /* 2623 */ 'v', 'q', 'd', 'm', 'u', 'l', 'h', 0, + /* 2631 */ 'v', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 0, + /* 2640 */ 'l', 'd', 'r', 'h', 0, + /* 2645 */ 's', 't', 'r', 'h', 0, + /* 2650 */ 'v', 'q', 'r', 'd', 'm', 'l', 's', 'h', 0, + /* 2659 */ 'l', 'd', 'r', 's', 'h', 0, + /* 2665 */ 'p', 'u', 's', 'h', 0, + /* 2670 */ 'r', 'e', 'v', 's', 'h', 0, + /* 2676 */ 's', 'x', 't', 'h', 0, + /* 2681 */ 'u', 'x', 't', 'h', 0, + /* 2686 */ 'l', 'd', 'a', 'e', 'x', 'h', 0, + /* 2693 */ 's', 't', 'l', 'e', 'x', 'h', 0, + /* 2700 */ 'l', 'd', 'r', 'e', 'x', 'h', 0, + /* 2707 */ 's', 't', 'r', 'e', 'x', 'h', 0, + /* 2714 */ 'b', 'f', 'i', 0, + /* 2718 */ 'p', 'l', 'i', 0, + /* 2722 */ 'v', 's', 'l', 'i', 0, + /* 2727 */ 'v', 's', 'r', 'i', 0, + /* 2732 */ 'b', 'x', 'j', 0, + /* 2736 */ 'l', 'd', 'c', '2', 'l', 0, + /* 2742 */ 's', 't', 'c', '2', 'l', 0, + /* 2748 */ 'u', 'm', 'a', 'a', 'l', 0, + /* 2754 */ 'v', 'a', 'b', 'a', 'l', 0, + /* 2760 */ 'v', 'p', 'a', 'd', 'a', 'l', 0, + /* 2767 */ 'v', 'q', 'd', 'm', 'l', 'a', 'l', 0, + /* 2775 */ 's', 'm', 'l', 'a', 'l', 0, + /* 2781 */ 'u', 'm', 'l', 'a', 'l', 0, + /* 2787 */ 'v', 'm', 'l', 'a', 'l', 0, + /* 2793 */ 'v', 't', 'b', 'l', 0, + /* 2798 */ 'v', 's', 'u', 'b', 'l', 0, + /* 2804 */ 'l', 'd', 'c', 'l', 0, + /* 2809 */ 's', 't', 'c', 'l', 0, + /* 2814 */ 'v', 'a', 'b', 'd', 'l', 0, + /* 2820 */ 'v', 'p', 'a', 'd', 'd', 'l', 0, + /* 2827 */ 'v', 'a', 'd', 'd', 'l', 0, + /* 2833 */ 's', 'e', 'l', 0, + /* 2837 */ 'v', 'q', 's', 'h', 'l', 0, + /* 2843 */ 'v', 'q', 'r', 's', 'h', 'l', 0, + /* 2850 */ 'v', 'r', 's', 'h', 'l', 0, + /* 2856 */ 'v', 's', 'h', 'l', 0, + /* 2861 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, + /* 2875 */ 'v', 's', 'h', 'l', 'l', 0, + /* 2881 */ 'v', 'q', 'd', 'm', 'u', 'l', 'l', 0, + /* 2889 */ 's', 'm', 'u', 'l', 'l', 0, + /* 2895 */ 'u', 'm', 'u', 'l', 'l', 0, + /* 2901 */ 'v', 'm', 'u', 'l', 'l', 0, + /* 2907 */ 'v', 'b', 's', 'l', 0, + /* 2912 */ 'v', 'q', 'd', 'm', 'l', 's', 'l', 0, + /* 2920 */ 'v', 'm', 'l', 's', 'l', 0, + /* 2926 */ 's', 't', 'l', 0, + /* 2930 */ 's', 'm', 'm', 'u', 'l', 0, + /* 2936 */ 'v', 'n', 'm', 'u', 'l', 0, + /* 2942 */ 'v', 'm', 'u', 'l', 0, + /* 2947 */ 'v', 'm', 'o', 'v', 'l', 0, + /* 2953 */ 'v', 'l', 'l', 'd', 'm', 0, + /* 2959 */ 'v', 'l', 's', 't', 'm', 0, + /* 2965 */ 'v', 'r', 's', 'u', 'b', 'h', 'n', 0, + /* 2973 */ 'v', 's', 'u', 'b', 'h', 'n', 0, + /* 2980 */ 'v', 'r', 'a', 'd', 'd', 'h', 'n', 0, + /* 2988 */ 'v', 'a', 'd', 'd', 'h', 'n', 0, + /* 2995 */ 'v', 'p', 'm', 'i', 'n', 0, + /* 3001 */ 'v', 'm', 'i', 'n', 0, + /* 3006 */ 'c', 'm', 'n', 0, + /* 3010 */ 'v', 'q', 's', 'h', 'r', 'n', 0, + /* 3017 */ 'v', 'q', 'r', 's', 'h', 'r', 'n', 0, + /* 3025 */ 'v', 'r', 's', 'h', 'r', 'n', 0, + /* 3032 */ 'v', 's', 'h', 'r', 'n', 0, + /* 3038 */ 'v', 'o', 'r', 'n', 0, + /* 3043 */ 'v', 't', 'r', 'n', 0, + /* 3048 */ 'v', 'q', 's', 'h', 'r', 'u', 'n', 0, + /* 3056 */ 'v', 'q', 'r', 's', 'h', 'r', 'u', 'n', 0, + /* 3065 */ 'v', 'q', 'm', 'o', 'v', 'u', 'n', 0, + /* 3073 */ 'v', 'm', 'v', 'n', 0, + /* 3078 */ 'v', 'q', 'm', 'o', 'v', 'n', 0, + /* 3085 */ 'v', 'm', 'o', 'v', 'n', 0, + /* 3091 */ 't', 'r', 'a', 'p', 0, + /* 3096 */ 'c', 'd', 'p', 0, + /* 3100 */ 'v', 'z', 'i', 'p', 0, + /* 3105 */ 'v', 'c', 'm', 'p', 0, + /* 3110 */ 'p', 'o', 'p', 0, + /* 3114 */ 'v', 'd', 'u', 'p', 0, + /* 3119 */ 'v', 's', 'w', 'p', 0, + /* 3124 */ 'v', 'u', 'z', 'p', 0, + /* 3129 */ 'v', 'c', 'e', 'q', 0, + /* 3134 */ 't', 'e', 'q', 0, + /* 3138 */ 's', 'm', 'm', 'l', 'a', 'r', 0, + /* 3145 */ 'm', 'c', 'r', 0, + /* 3149 */ 'a', 'd', 'r', 0, + /* 3153 */ 'v', 'l', 'd', 'r', 0, + /* 3158 */ 'v', 'r', 's', 'h', 'r', 0, + /* 3164 */ 'v', 's', 'h', 'r', 0, + /* 3169 */ 's', 'm', 'm', 'u', 'l', 'r', 0, + /* 3176 */ 'v', 'e', 'o', 'r', 0, + /* 3181 */ 'r', 'o', 'r', 0, + /* 3185 */ 'm', 'c', 'r', 'r', 0, + /* 3190 */ 'v', 'o', 'r', 'r', 0, + /* 3195 */ 'a', 's', 'r', 0, + /* 3199 */ 's', 'm', 'm', 'l', 's', 'r', 0, + /* 3206 */ 'v', 'm', 's', 'r', 0, + /* 3211 */ 'v', 'r', 'i', 'n', 't', 'r', 0, + /* 3218 */ 'v', 's', 't', 'r', 0, + /* 3223 */ 'v', 'c', 'v', 't', 'r', 0, + /* 3229 */ 'v', 'q', 'a', 'b', 's', 0, + /* 3235 */ 'v', 'a', 'b', 's', 0, + /* 3240 */ 's', 'u', 'b', 's', 0, + /* 3245 */ 'v', 'c', 'l', 's', 0, + /* 3250 */ 's', 'm', 'm', 'l', 's', 0, + /* 3256 */ 'v', 'n', 'm', 'l', 's', 0, + /* 3262 */ 'v', 'm', 'l', 's', 0, + /* 3267 */ 'v', 'f', 'm', 's', 0, + /* 3272 */ 'v', 'f', 'n', 'm', 's', 0, + /* 3278 */ 'b', 'x', 'n', 's', 0, + /* 3283 */ 'b', 'l', 'x', 'n', 's', 0, + /* 3289 */ 'v', 'r', 'e', 'c', 'p', 's', 0, + /* 3296 */ 'v', 'm', 'r', 's', 0, + /* 3301 */ 'a', 's', 'r', 's', 0, + /* 3306 */ 'l', 's', 'r', 's', 0, + /* 3311 */ 'v', 'r', 's', 'q', 'r', 't', 's', 0, + /* 3319 */ 'm', 'o', 'v', 's', 0, + /* 3324 */ 's', 's', 'a', 't', 0, + /* 3329 */ 'u', 's', 'a', 't', 0, + /* 3334 */ 't', 't', 'a', 't', 0, + /* 3339 */ 's', 'm', 'l', 'a', 'b', 't', 0, + /* 3346 */ 'p', 'k', 'h', 'b', 't', 0, + /* 3352 */ 's', 'm', 'l', 'a', 'l', 'b', 't', 0, + /* 3360 */ 's', 'm', 'u', 'l', 'b', 't', 0, + /* 3367 */ 'l', 'd', 'r', 'b', 't', 0, + /* 3373 */ 's', 't', 'r', 'b', 't', 0, + /* 3379 */ 'l', 'd', 'r', 's', 'b', 't', 0, + /* 3386 */ 'e', 'r', 'e', 't', 0, + /* 3391 */ 'v', 'a', 'c', 'g', 't', 0, + /* 3397 */ 'v', 'c', 'g', 't', 0, + /* 3402 */ 'l', 'd', 'r', 'h', 't', 0, + /* 3408 */ 's', 't', 'r', 'h', 't', 0, + /* 3414 */ 'l', 'd', 'r', 's', 'h', 't', 0, + /* 3421 */ 'r', 'b', 'i', 't', 0, + /* 3426 */ 'v', 'b', 'i', 't', 0, + /* 3431 */ 'v', 'c', 'l', 't', 0, + /* 3436 */ 'v', 'c', 'n', 't', 0, + /* 3441 */ 'h', 'i', 'n', 't', 0, + /* 3446 */ 'l', 'd', 'r', 't', 0, + /* 3451 */ 'v', 's', 'q', 'r', 't', 0, + /* 3457 */ 's', 't', 'r', 't', 0, + /* 3462 */ 'v', 't', 's', 't', 0, + /* 3467 */ 's', 'm', 'l', 'a', 't', 't', 0, + /* 3474 */ 's', 'm', 'l', 'a', 'l', 't', 't', 0, + /* 3482 */ 's', 'm', 'u', 'l', 't', 't', 0, + /* 3489 */ 't', 't', 't', 0, + /* 3493 */ 'v', 'c', 'v', 't', 't', 0, + /* 3499 */ 'v', 'j', 'c', 'v', 't', 0, + /* 3505 */ 'v', 'c', 'v', 't', 0, + /* 3510 */ 'm', 'o', 'v', 't', 0, + /* 3515 */ 's', 'm', 'l', 'a', 'w', 't', 0, + /* 3522 */ 's', 'm', 'u', 'l', 'w', 't', 0, + /* 3529 */ 'v', 'e', 'x', 't', 0, + /* 3534 */ 'v', 'q', 's', 'h', 'l', 'u', 0, + /* 3541 */ 'r', 'e', 'v', 0, + /* 3545 */ 's', 'd', 'i', 'v', 0, + /* 3550 */ 'u', 'd', 'i', 'v', 0, + /* 3555 */ 'v', 'd', 'i', 'v', 0, + /* 3560 */ 'v', 'm', 'o', 'v', 0, + /* 3565 */ 'v', 's', 'u', 'b', 'w', 0, + /* 3571 */ 'v', 'a', 'd', 'd', 'w', 0, + /* 3577 */ 'p', 'l', 'd', 'w', 0, + /* 3582 */ 'm', 'o', 'v', 'w', 0, + /* 3587 */ 'f', 'l', 'd', 'm', 'i', 'a', 'x', 0, + /* 3595 */ 'f', 's', 't', 'm', 'i', 'a', 'x', 0, + /* 3603 */ 'v', 'p', 'm', 'a', 'x', 0, + /* 3609 */ 'v', 'm', 'a', 'x', 0, + /* 3614 */ 's', 'h', 's', 'a', 'x', 0, + /* 3620 */ 'u', 'h', 's', 'a', 'x', 0, + /* 3626 */ 'u', 'q', 's', 'a', 'x', 0, + /* 3632 */ 's', 's', 'a', 'x', 0, + /* 3637 */ 'u', 's', 'a', 'x', 0, + /* 3642 */ 'f', 'l', 'd', 'm', 'd', 'b', 'x', 0, + /* 3650 */ 'f', 's', 't', 'm', 'd', 'b', 'x', 0, + /* 3658 */ 'v', 't', 'b', 'x', 0, + /* 3663 */ 's', 'm', 'l', 'a', 'd', 'x', 0, + /* 3670 */ 's', 'm', 'u', 'a', 'd', 'x', 0, + /* 3677 */ 's', 'm', 'l', 'a', 'l', 'd', 'x', 0, + /* 3685 */ 's', 'm', 'l', 's', 'l', 'd', 'x', 0, + /* 3693 */ 's', 'm', 'l', 's', 'd', 'x', 0, + /* 3700 */ 's', 'm', 'u', 's', 'd', 'x', 0, + /* 3707 */ 'l', 'd', 'a', 'e', 'x', 0, + /* 3713 */ 's', 't', 'l', 'e', 'x', 0, + /* 3719 */ 'l', 'd', 'r', 'e', 'x', 0, + /* 3725 */ 'c', 'l', 'r', 'e', 'x', 0, + /* 3731 */ 's', 't', 'r', 'e', 'x', 0, + /* 3737 */ 's', 'b', 'f', 'x', 0, + /* 3742 */ 'u', 'b', 'f', 'x', 0, + /* 3747 */ 'b', 'l', 'x', 0, + /* 3751 */ 'r', 'r', 'x', 0, + /* 3755 */ 's', 'h', 'a', 's', 'x', 0, + /* 3761 */ 'u', 'h', 'a', 's', 'x', 0, + /* 3767 */ 'u', 'q', 'a', 's', 'x', 0, + /* 3773 */ 's', 'a', 's', 'x', 0, + /* 3778 */ 'u', 'a', 's', 'x', 0, + /* 3783 */ 'v', 'r', 'i', 'n', 't', 'x', 0, + /* 3790 */ 'v', 'c', 'l', 'z', 0, + /* 3795 */ 'v', 'r', 'i', 'n', 't', 'z', 0, + }; +#endif + + static const uint32_t OpInfo0[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 1981U, // DBG_VALUE + 1991U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 1974U, // BUNDLE + 2020U, // LIFETIME_START + 1961U, // LIFETIME_END + 0U, // STACKMAP + 2862U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 1568U, // PATCHABLE_FUNCTION_ENTER + 1488U, // PATCHABLE_RET + 1614U, // PATCHABLE_FUNCTION_EXIT + 1591U, // PATCHABLE_TAIL_CALL + 1543U, // PATCHABLE_EVENT_CALL + 1519U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // ABS + 0U, // ADDSri + 0U, // ADDSrr + 0U, // ADDSrsi + 0U, // ADDSrsr + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 7292U, // ASRi + 7292U, // ASRr + 0U, // B + 0U, // BCCZi64 + 0U, // BCCi64 + 0U, // BMOVPCB_CALL + 0U, // BMOVPCRX_CALL + 0U, // BR_JTadd + 0U, // BR_JTm_i12 + 0U, // BR_JTm_rs + 0U, // BR_JTr + 0U, // BX_CALL + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_STRUCT_BYVAL_I32 + 2001U, // CompilerBarrier + 16788832U, // ITasm + 0U, // Int_eh_sjlj_dispatchsetup + 0U, // Int_eh_sjlj_longjmp + 0U, // Int_eh_sjlj_setjmp + 0U, // Int_eh_sjlj_setjmp_nofp + 0U, // Int_eh_sjlj_setup_dispatch + 0U, // JUMPTABLE_ADDRS + 0U, // JUMPTABLE_INSTS + 0U, // JUMPTABLE_TBB + 0U, // JUMPTABLE_TBH + 0U, // LDMIA_RET + 15656U, // LDRBT_POST + 15443U, // LDRConstPool + 0U, // LDRLIT_ga_abs + 0U, // LDRLIT_ga_pcrel + 0U, // LDRLIT_ga_pcrel_ldr + 15735U, // LDRT_POST + 0U, // LEApcrel + 0U, // LEApcrelJT + 7013U, // LSLi + 7013U, // LSLr + 7299U, // LSRi + 7299U, // LSRr + 0U, // MEMCPY + 0U, // MLAv5 + 0U, // MOVCCi + 0U, // MOVCCi16 + 0U, // MOVCCi32imm + 0U, // MOVCCr + 0U, // MOVCCsi + 0U, // MOVCCsr + 0U, // MOVPCRX + 0U, // MOVTi16_ga_pcrel + 0U, // MOV_ga_pcrel + 0U, // MOV_ga_pcrel_ldr + 0U, // MOVi16_ga_pcrel + 0U, // MOVi32imm + 0U, // MOVsra_flag + 0U, // MOVsrl_flag + 0U, // MULv5 + 0U, // MVNCCi + 0U, // PICADD + 0U, // PICLDR + 0U, // PICLDRB + 0U, // PICLDRH + 0U, // PICLDRSB + 0U, // PICLDRSH + 0U, // PICSTR + 0U, // PICSTRB + 0U, // PICSTRH + 7278U, // RORi + 7278U, // RORr + 0U, // RRX + 20136U, // RRXi + 0U, // RSBSri + 0U, // RSBSrsi + 0U, // RSBSrsr + 0U, // SMLALv5 + 0U, // SMULLv5 + 0U, // SPACE + 15662U, // STRBT_POST + 0U, // STRBi_preidx + 0U, // STRBr_preidx + 0U, // STRH_preidx + 15746U, // STRT_POST + 0U, // STRi_preidx + 0U, // STRr_preidx + 0U, // SUBS_PC_LR + 0U, // SUBSri + 0U, // SUBSrr + 0U, // SUBSrsi + 0U, // SUBSrsr + 0U, // TAILJMPd + 0U, // TAILJMPr + 0U, // TAILJMPr4 + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TPsoft + 0U, // UMLALv5 + 0U, // UMULLv5 + 153198U, // VLD1LNdAsm_16 + 284270U, // VLD1LNdAsm_32 + 415342U, // VLD1LNdAsm_8 + 153198U, // VLD1LNdWB_fixed_Asm_16 + 284270U, // VLD1LNdWB_fixed_Asm_32 + 415342U, // VLD1LNdWB_fixed_Asm_8 + 157294U, // VLD1LNdWB_register_Asm_16 + 288366U, // VLD1LNdWB_register_Asm_32 + 419438U, // VLD1LNdWB_register_Asm_8 + 153242U, // VLD2LNdAsm_16 + 284314U, // VLD2LNdAsm_32 + 415386U, // VLD2LNdAsm_8 + 153242U, // VLD2LNdWB_fixed_Asm_16 + 284314U, // VLD2LNdWB_fixed_Asm_32 + 415386U, // VLD2LNdWB_fixed_Asm_8 + 157338U, // VLD2LNdWB_register_Asm_16 + 288410U, // VLD2LNdWB_register_Asm_32 + 419482U, // VLD2LNdWB_register_Asm_8 + 153242U, // VLD2LNqAsm_16 + 284314U, // VLD2LNqAsm_32 + 153242U, // VLD2LNqWB_fixed_Asm_16 + 284314U, // VLD2LNqWB_fixed_Asm_32 + 157338U, // VLD2LNqWB_register_Asm_16 + 288410U, // VLD2LNqWB_register_Asm_32 + 1107457722U, // VLD3DUPdAsm_16 + 1107588794U, // VLD3DUPdAsm_32 + 1107719866U, // VLD3DUPdAsm_8 + 2181199546U, // VLD3DUPdWB_fixed_Asm_16 + 2181330618U, // VLD3DUPdWB_fixed_Asm_32 + 2181461690U, // VLD3DUPdWB_fixed_Asm_8 + 33707706U, // VLD3DUPdWB_register_Asm_16 + 33838778U, // VLD3DUPdWB_register_Asm_32 + 33969850U, // VLD3DUPdWB_register_Asm_8 + 1124234938U, // VLD3DUPqAsm_16 + 1124366010U, // VLD3DUPqAsm_32 + 1124497082U, // VLD3DUPqAsm_8 + 2197976762U, // VLD3DUPqWB_fixed_Asm_16 + 2198107834U, // VLD3DUPqWB_fixed_Asm_32 + 2198238906U, // VLD3DUPqWB_fixed_Asm_8 + 50484922U, // VLD3DUPqWB_register_Asm_16 + 50615994U, // VLD3DUPqWB_register_Asm_32 + 50747066U, // VLD3DUPqWB_register_Asm_8 + 153274U, // VLD3LNdAsm_16 + 284346U, // VLD3LNdAsm_32 + 415418U, // VLD3LNdAsm_8 + 153274U, // VLD3LNdWB_fixed_Asm_16 + 284346U, // VLD3LNdWB_fixed_Asm_32 + 415418U, // VLD3LNdWB_fixed_Asm_8 + 157370U, // VLD3LNdWB_register_Asm_16 + 288442U, // VLD3LNdWB_register_Asm_32 + 419514U, // VLD3LNdWB_register_Asm_8 + 153274U, // VLD3LNqAsm_16 + 284346U, // VLD3LNqAsm_32 + 153274U, // VLD3LNqWB_fixed_Asm_16 + 284346U, // VLD3LNqWB_fixed_Asm_32 + 157370U, // VLD3LNqWB_register_Asm_16 + 288442U, // VLD3LNqWB_register_Asm_32 + 3288495802U, // VLD3dAsm_16 + 3288626874U, // VLD3dAsm_32 + 3288757946U, // VLD3dAsm_8 + 3288495802U, // VLD3dWB_fixed_Asm_16 + 3288626874U, // VLD3dWB_fixed_Asm_32 + 3288757946U, // VLD3dWB_fixed_Asm_8 + 3288487610U, // VLD3dWB_register_Asm_16 + 3288618682U, // VLD3dWB_register_Asm_32 + 3288749754U, // VLD3dWB_register_Asm_8 + 1157789370U, // VLD3qAsm_16 + 1157920442U, // VLD3qAsm_32 + 1158051514U, // VLD3qAsm_8 + 2231531194U, // VLD3qWB_fixed_Asm_16 + 2231662266U, // VLD3qWB_fixed_Asm_32 + 2231793338U, // VLD3qWB_fixed_Asm_8 + 84039354U, // VLD3qWB_register_Asm_16 + 84170426U, // VLD3qWB_register_Asm_32 + 84301498U, // VLD3qWB_register_Asm_8 + 1174566609U, // VLD4DUPdAsm_16 + 1174697681U, // VLD4DUPdAsm_32 + 1174828753U, // VLD4DUPdAsm_8 + 2248308433U, // VLD4DUPdWB_fixed_Asm_16 + 2248439505U, // VLD4DUPdWB_fixed_Asm_32 + 2248570577U, // VLD4DUPdWB_fixed_Asm_8 + 100816593U, // VLD4DUPdWB_register_Asm_16 + 100947665U, // VLD4DUPdWB_register_Asm_32 + 101078737U, // VLD4DUPdWB_register_Asm_8 + 1191343825U, // VLD4DUPqAsm_16 + 1191474897U, // VLD4DUPqAsm_32 + 1191605969U, // VLD4DUPqAsm_8 + 2265085649U, // VLD4DUPqWB_fixed_Asm_16 + 2265216721U, // VLD4DUPqWB_fixed_Asm_32 + 2265347793U, // VLD4DUPqWB_fixed_Asm_8 + 117593809U, // VLD4DUPqWB_register_Asm_16 + 117724881U, // VLD4DUPqWB_register_Asm_32 + 117855953U, // VLD4DUPqWB_register_Asm_8 + 153297U, // VLD4LNdAsm_16 + 284369U, // VLD4LNdAsm_32 + 415441U, // VLD4LNdAsm_8 + 153297U, // VLD4LNdWB_fixed_Asm_16 + 284369U, // VLD4LNdWB_fixed_Asm_32 + 415441U, // VLD4LNdWB_fixed_Asm_8 + 157393U, // VLD4LNdWB_register_Asm_16 + 288465U, // VLD4LNdWB_register_Asm_32 + 419537U, // VLD4LNdWB_register_Asm_8 + 153297U, // VLD4LNqAsm_16 + 284369U, // VLD4LNqAsm_32 + 153297U, // VLD4LNqWB_fixed_Asm_16 + 284369U, // VLD4LNqWB_fixed_Asm_32 + 157393U, // VLD4LNqWB_register_Asm_16 + 288465U, // VLD4LNqWB_register_Asm_32 + 3355604689U, // VLD4dAsm_16 + 3355735761U, // VLD4dAsm_32 + 3355866833U, // VLD4dAsm_8 + 3355604689U, // VLD4dWB_fixed_Asm_16 + 3355735761U, // VLD4dWB_fixed_Asm_32 + 3355866833U, // VLD4dWB_fixed_Asm_8 + 3355596497U, // VLD4dWB_register_Asm_16 + 3355727569U, // VLD4dWB_register_Asm_32 + 3355858641U, // VLD4dWB_register_Asm_8 + 1224898257U, // VLD4qAsm_16 + 1225029329U, // VLD4qAsm_32 + 1225160401U, // VLD4qAsm_8 + 2298640081U, // VLD4qWB_fixed_Asm_16 + 2298771153U, // VLD4qWB_fixed_Asm_32 + 2298902225U, // VLD4qWB_fixed_Asm_8 + 151148241U, // VLD4qWB_register_Asm_16 + 151279313U, // VLD4qWB_register_Asm_32 + 151410385U, // VLD4qWB_register_Asm_8 + 0U, // VMOVD0 + 0U, // VMOVDcc + 0U, // VMOVQ0 + 0U, // VMOVScc + 153209U, // VST1LNdAsm_16 + 284281U, // VST1LNdAsm_32 + 415353U, // VST1LNdAsm_8 + 153209U, // VST1LNdWB_fixed_Asm_16 + 284281U, // VST1LNdWB_fixed_Asm_32 + 415353U, // VST1LNdWB_fixed_Asm_8 + 157305U, // VST1LNdWB_register_Asm_16 + 288377U, // VST1LNdWB_register_Asm_32 + 419449U, // VST1LNdWB_register_Asm_8 + 153269U, // VST2LNdAsm_16 + 284341U, // VST2LNdAsm_32 + 415413U, // VST2LNdAsm_8 + 153269U, // VST2LNdWB_fixed_Asm_16 + 284341U, // VST2LNdWB_fixed_Asm_32 + 415413U, // VST2LNdWB_fixed_Asm_8 + 157365U, // VST2LNdWB_register_Asm_16 + 288437U, // VST2LNdWB_register_Asm_32 + 419509U, // VST2LNdWB_register_Asm_8 + 153269U, // VST2LNqAsm_16 + 284341U, // VST2LNqAsm_32 + 153269U, // VST2LNqWB_fixed_Asm_16 + 284341U, // VST2LNqWB_fixed_Asm_32 + 157365U, // VST2LNqWB_register_Asm_16 + 288437U, // VST2LNqWB_register_Asm_32 + 153285U, // VST3LNdAsm_16 + 284357U, // VST3LNdAsm_32 + 415429U, // VST3LNdAsm_8 + 153285U, // VST3LNdWB_fixed_Asm_16 + 284357U, // VST3LNdWB_fixed_Asm_32 + 415429U, // VST3LNdWB_fixed_Asm_8 + 157381U, // VST3LNdWB_register_Asm_16 + 288453U, // VST3LNdWB_register_Asm_32 + 419525U, // VST3LNdWB_register_Asm_8 + 153285U, // VST3LNqAsm_16 + 284357U, // VST3LNqAsm_32 + 153285U, // VST3LNqWB_fixed_Asm_16 + 284357U, // VST3LNqWB_fixed_Asm_32 + 157381U, // VST3LNqWB_register_Asm_16 + 288453U, // VST3LNqWB_register_Asm_32 + 3288495813U, // VST3dAsm_16 + 3288626885U, // VST3dAsm_32 + 3288757957U, // VST3dAsm_8 + 3288495813U, // VST3dWB_fixed_Asm_16 + 3288626885U, // VST3dWB_fixed_Asm_32 + 3288757957U, // VST3dWB_fixed_Asm_8 + 3288487621U, // VST3dWB_register_Asm_16 + 3288618693U, // VST3dWB_register_Asm_32 + 3288749765U, // VST3dWB_register_Asm_8 + 1157789381U, // VST3qAsm_16 + 1157920453U, // VST3qAsm_32 + 1158051525U, // VST3qAsm_8 + 2231531205U, // VST3qWB_fixed_Asm_16 + 2231662277U, // VST3qWB_fixed_Asm_32 + 2231793349U, // VST3qWB_fixed_Asm_8 + 84039365U, // VST3qWB_register_Asm_16 + 84170437U, // VST3qWB_register_Asm_32 + 84301509U, // VST3qWB_register_Asm_8 + 153302U, // VST4LNdAsm_16 + 284374U, // VST4LNdAsm_32 + 415446U, // VST4LNdAsm_8 + 153302U, // VST4LNdWB_fixed_Asm_16 + 284374U, // VST4LNdWB_fixed_Asm_32 + 415446U, // VST4LNdWB_fixed_Asm_8 + 157398U, // VST4LNdWB_register_Asm_16 + 288470U, // VST4LNdWB_register_Asm_32 + 419542U, // VST4LNdWB_register_Asm_8 + 153302U, // VST4LNqAsm_16 + 284374U, // VST4LNqAsm_32 + 153302U, // VST4LNqWB_fixed_Asm_16 + 284374U, // VST4LNqWB_fixed_Asm_32 + 157398U, // VST4LNqWB_register_Asm_16 + 288470U, // VST4LNqWB_register_Asm_32 + 3355604694U, // VST4dAsm_16 + 3355735766U, // VST4dAsm_32 + 3355866838U, // VST4dAsm_8 + 3355604694U, // VST4dWB_fixed_Asm_16 + 3355735766U, // VST4dWB_fixed_Asm_32 + 3355866838U, // VST4dWB_fixed_Asm_8 + 3355596502U, // VST4dWB_register_Asm_16 + 3355727574U, // VST4dWB_register_Asm_32 + 3355858646U, // VST4dWB_register_Asm_8 + 1224898262U, // VST4qAsm_16 + 1225029334U, // VST4qAsm_32 + 1225160406U, // VST4qAsm_8 + 2298640086U, // VST4qWB_fixed_Asm_16 + 2298771158U, // VST4qWB_fixed_Asm_32 + 2298902230U, // VST4qWB_fixed_Asm_8 + 151148246U, // VST4qWB_register_Asm_16 + 151279318U, // VST4qWB_register_Asm_32 + 151410390U, // VST4qWB_register_Asm_8 + 0U, // WIN__CHKSTK + 0U, // WIN__DBZCHK + 0U, // t2ABS + 0U, // t2ADDSri + 0U, // t2ADDSrr + 0U, // t2ADDSrs + 0U, // t2BR_JT + 0U, // t2LDMIA_RET + 14508U, // t2LDRBpcrel + 15443U, // t2LDRConstPool + 14929U, // t2LDRHpcrel + 14526U, // t2LDRSBpcrel + 14948U, // t2LDRSHpcrel + 0U, // t2LDRpci_pic + 15443U, // t2LDRpcrel + 0U, // t2LEApcrel + 0U, // t2LEApcrelJT + 0U, // t2MOVCCasr + 0U, // t2MOVCCi + 0U, // t2MOVCCi16 + 0U, // t2MOVCCi32imm + 0U, // t2MOVCClsl + 0U, // t2MOVCClsr + 0U, // t2MOVCCr + 0U, // t2MOVCCror + 31992U, // t2MOVSsi + 23800U, // t2MOVSsr + 0U, // t2MOVTi16_ga_pcrel + 0U, // t2MOV_ga_pcrel + 0U, // t2MOVi16_ga_pcrel + 0U, // t2MOVi32imm + 32234U, // t2MOVsi + 24042U, // t2MOVsr + 0U, // t2MVNCCi + 0U, // t2RSBSri + 0U, // t2RSBSrs + 0U, // t2STRB_preidx + 0U, // t2STRH_preidx + 0U, // t2STR_preidx + 0U, // t2SUBSri + 0U, // t2SUBSrr + 0U, // t2SUBSrs + 0U, // t2TBB_JT + 0U, // t2TBH_JT + 0U, // tADCS + 0U, // tADDSi3 + 0U, // tADDSi8 + 0U, // tADDSrr + 0U, // tADDframe + 0U, // tADJCALLSTACKDOWN + 0U, // tADJCALLSTACKUP + 0U, // tBRIND + 0U, // tBR_JTr + 0U, // tBX_CALL + 0U, // tBX_RET + 0U, // tBX_RET_vararg + 0U, // tBfar + 0U, // tLDMIA_UPD + 15443U, // tLDRConstPool + 0U, // tLDRLIT_ga_abs + 0U, // tLDRLIT_ga_pcrel + 0U, // tLDR_postidx + 0U, // tLDRpci_pic + 0U, // tLEApcrel + 0U, // tLEApcrelJT + 0U, // tMOVCCr_pseudo + 0U, // tPOP_RET + 0U, // tSBCS + 0U, // tSUBSi3 + 0U, // tSUBSi8 + 0U, // tSUBSrr + 0U, // tTAILJMPd + 0U, // tTAILJMPdND + 0U, // tTAILJMPr + 0U, // tTBB_JT + 0U, // tTBH_JT + 0U, // tTPsoft + 530745U, // ADCri + 530745U, // ADCrr + 559417U, // ADCrsi + 39225U, // ADCrsr + 530806U, // ADDri + 530806U, // ADDrr + 559478U, // ADDrsi + 39286U, // ADDrsr + 539726U, // ADR + 1242211449U, // AESD + 1242211457U, // AESE + 1258988646U, // AESIMC + 1258988656U, // AESMC + 530859U, // ANDri + 530859U, // ANDrr + 559531U, // ANDrsi + 39339U, // ANDrsr + 555329U, // BFC + 547483U, // BFI + 530758U, // BICri + 530758U, // BICrr + 559430U, // BICrsi + 39238U, // BICrsr + 828725U, // BKPT + 828697U, // BL + 828772U, // BLX + 1074314916U, // BLX_pred + 828772U, // BLXi + 1074313964U, // BL_pred + 828768U, // BX + 1074313901U, // BXJ + 970304U, // BX_RET + 1074314816U, // BX_pred + 1074313296U, // Bcc + 201907225U, // CDP + 219210157U, // CDP2 + 3726U, // CLREX + 540368U, // CLZ + 539583U, // CMNri + 539583U, // CMNzrr + 555967U, // CMNzrsi + 547775U, // CMNzrsr + 539683U, // CMPri + 539683U, // CMPrr + 556067U, // CMPrsi + 547875U, // CMPrsr + 828709U, // CPS1p + 1309211869U, // CPS2p + 235470045U, // CPS3p + 185246891U, // CRC32B + 185246899U, // CRC32CB + 185246973U, // CRC32CH + 185247057U, // CRC32CW + 185246965U, // CRC32H + 185247049U, // CRC32W + 1074313739U, // DBG + 66762U, // DMB + 66767U, // DSB + 531562U, // EORri + 531562U, // EORrr + 560234U, // EORrsi + 40042U, // EORrsr + 838971U, // ERET + 1326595561U, // FCONSTD + 1326726633U, // FCONSTH + 1326857705U, // FCONSTS + 2332573243U, // FLDMXDB_UPD + 572932U, // FLDMXIA + 2332573188U, // FLDMXIA_UPD + 1625313U, // FMSTAT + 2332573251U, // FSTMXDB_UPD + 572940U, // FSTMXIA + 2332573196U, // FSTMXIA_UPD + 1074314610U, // HINT + 828720U, // HLT + 828638U, // HVC + 70868U, // ISB + 538616U, // LDA + 538701U, // LDAB + 540284U, // LDAEX + 538905U, // LDAEXB + 268974533U, // LDAEXD + 539263U, // LDAEXH + 539165U, // LDAH + 286975243U, // LDC2L_OFFSET + 3524977931U, // LDC2L_OPTION + 303752459U, // LDC2L_POST + 320529675U, // LDC2L_PRE + 286974356U, // LDC2_OFFSET + 3524977044U, // LDC2_OPTION + 303751572U, // LDC2_POST + 320528788U, // LDC2_PRE + 1275615989U, // LDCL_OFFSET + 1275615989U, // LDCL_OPTION + 1275615989U, // LDCL_POST + 1275615989U, // LDCL_PRE + 1275615549U, // LDC_OFFSET + 1275615549U, // LDC_OPTION + 1275615549U, // LDC_POST + 1275615549U, // LDC_PRE + 571388U, // LDMDA + 2332571644U, // LDMDA_UPD + 571519U, // LDMDB + 2332571775U, // LDMDB_UPD + 572300U, // LDMIA + 2332572556U, // LDMIA_UPD + 571538U, // LDMIB + 2332571794U, // LDMIB_UPD + 552232U, // LDRBT_POST_IMM + 552232U, // LDRBT_POST_REG + 551084U, // LDRB_POST_IMM + 551084U, // LDRB_POST_REG + 546988U, // LDRB_PRE_IMM + 551084U, // LDRB_PRE_REG + 555180U, // LDRBi12 + 546988U, // LDRBrs + 551343U, // LDRD + 580015U, // LDRD_POST + 580015U, // LDRD_PRE + 540296U, // LDREX + 538919U, // LDREXB + 268974547U, // LDREXD + 539277U, // LDREXH + 547409U, // LDRH + 548171U, // LDRHTi + 552267U, // LDRHTr + 551505U, // LDRH_POST + 551505U, // LDRH_PRE + 547006U, // LDRSB + 548148U, // LDRSBTi + 552244U, // LDRSBTr + 551102U, // LDRSB_POST + 551102U, // LDRSB_PRE + 547428U, // LDRSH + 548183U, // LDRSHTi + 552279U, // LDRSHTr + 551524U, // LDRSH_POST + 551524U, // LDRSH_PRE + 552311U, // LDRT_POST_IMM + 552311U, // LDRT_POST_REG + 552019U, // LDR_POST_IMM + 552019U, // LDR_POST_REG + 547923U, // LDR_PRE_IMM + 552019U, // LDR_PRE_REG + 556115U, // LDRcp + 556115U, // LDRi12 + 547923U, // LDRrs + 201907274U, // MCR + 168878515U, // MCR2 + 201878642U, // MCRR + 168878521U, // MCRR2 + 559140U, // MLA + 548021U, // MLS + 1887722U, // MOVPCLR + 556471U, // MOVTi16 + 544234U, // MOVi + 540159U, // MOVi16 + 544234U, // MOVr + 544234U, // MOVr_TC + 531946U, // MOVsi + 560618U, // MOVsr + 336124238U, // MRC + 74138U, // MRC2 + 352872786U, // MRRC + 78240U, // MRRC2 + 2148056290U, // MRS + 539874U, // MRSbanked + 3221798114U, // MRSsys + 369638536U, // MSR + 386415752U, // MSRbanked + 369638536U, // MSRi + 531317U, // MUL + 543747U, // MVNi + 543747U, // MVNr + 531459U, // MVNsi + 560131U, // MVNsr + 531576U, // ORRri + 531576U, // ORRrr + 560248U, // ORRrsi + 40056U, // ORRrsr + 548115U, // PKHBT + 547023U, // PKHTB + 83290U, // PLDWi12 + 87386U, // PLDWrs + 83171U, // PLDi12 + 87267U, // PLDrs + 83206U, // PLIi12 + 87302U, // PLIrs + 555406U, // QADD + 554800U, // QADD16 + 554903U, // QADD8 + 556729U, // QASX + 555380U, // QDADD + 555252U, // QDSUB + 556588U, // QSAX + 555265U, // QSUB + 554762U, // QSUB16 + 554864U, // QSUB8 + 539998U, // RBIT + 540118U, // REV + 538452U, // REV16 + 539247U, // REVSH + 828573U, // RFEDA + 2008221U, // RFEDA_UPD + 828604U, // RFEDB + 2008252U, // RFEDB_UPD + 828580U, // RFEIA + 2008228U, // RFEIA_UPD + 828611U, // RFEIB + 2008259U, // RFEIB_UPD + 530624U, // RSBri + 530624U, // RSBrr + 559296U, // RSBrsi + 39104U, // RSBrsr + 530775U, // RSCri + 530775U, // RSCrr + 559447U, // RSCrsi + 39255U, // RSCrsr + 554807U, // SADD16 + 554909U, // SADD8 + 556734U, // SASX + 530741U, // SBCri + 530741U, // SBCrr + 559413U, // SBCrsi + 39221U, // SBCrsr + 548506U, // SBFX + 556506U, // SDIV + 555794U, // SEL + 91368U, // SETEND + 828701U, // SETPAN + 168468546U, // SHA1C + 1258987596U, // SHA1H + 168468578U, // SHA1M + 168468588U, // SHA1P + 168468481U, // SHA1SU0 + 1242210331U, // SHA1SU1 + 168468566U, // SHA256H + 168468533U, // SHA256H2 + 1242210317U, // SHA256SU0 + 168468519U, // SHA256SU1 + 554783U, // SHADD16 + 554888U, // SHADD8 + 556716U, // SHASX + 556575U, // SHSAX + 554745U, // SHSUB16 + 554849U, // SHSUB8 + 1074313546U, // SMC + 546910U, // SMLABB + 548108U, // SMLABT + 547171U, // SMLAD + 548432U, // SMLADX + 96984U, // SMLAL + 579685U, // SMLALBB + 580889U, // SMLALBT + 579992U, // SMLALD + 581214U, // SMLALDX + 579797U, // SMLALTB + 581011U, // SMLALTT + 547016U, // SMLATB + 548236U, // SMLATT + 547083U, // SMLAWB + 548284U, // SMLAWT + 547257U, // SMLSD + 548462U, // SMLSDX + 580003U, // SMLSLD + 581222U, // SMLSLDX + 546850U, // SMMLA + 547907U, // SMMLAR + 548019U, // SMMLS + 547968U, // SMMLSR + 555891U, // SMMUL + 556130U, // SMMULR + 555369U, // SMUAD + 556631U, // SMUADX + 555117U, // SMULBB + 556321U, // SMULBT + 559946U, // SMULL + 555229U, // SMULTB + 556443U, // SMULTT + 555282U, // SMULWB + 556483U, // SMULWT + 555455U, // SMUSD + 556661U, // SMUSDX + 828836U, // SRSDA + 828788U, // SRSDA_UPD + 828858U, // SRSDB + 828812U, // SRSDB_UPD + 828847U, // SRSIA + 828800U, // SRSIA_UPD + 828869U, // SRSIB + 828824U, // SRSIB_UPD + 548093U, // SSAT + 554821U, // SSAT16 + 556593U, // SSAX + 554769U, // SSUB16 + 554870U, // SSUB8 + 286975250U, // STC2L_OFFSET + 3524977938U, // STC2L_OPTION + 303752466U, // STC2L_POST + 320529682U, // STC2L_PRE + 286974375U, // STC2_OFFSET + 3524977063U, // STC2_OPTION + 303751591U, // STC2_POST + 320528807U, // STC2_PRE + 1275615994U, // STCL_OFFSET + 1275615994U, // STCL_OPTION + 1275615994U, // STCL_POST + 1275615994U, // STCL_PRE + 1275615579U, // STC_OFFSET + 1275615579U, // STC_OPTION + 1275615579U, // STC_POST + 1275615579U, // STC_PRE + 539503U, // STL + 538782U, // STLB + 556674U, // STLEX + 555296U, // STLEXB + 555468U, // STLEXD + 555654U, // STLEXH + 539195U, // STLH + 571394U, // STMDA + 2332571650U, // STMDA_UPD + 571526U, // STMDB + 2332571782U, // STMDB_UPD + 572306U, // STMIA + 2332572562U, // STMIA_UPD + 571544U, // STMIB + 2332571800U, // STMIB_UPD + 185101614U, // STRBT_POST_IMM + 185101614U, // STRBT_POST_REG + 185100465U, // STRB_POST_IMM + 185100465U, // STRB_POST_REG + 185096369U, // STRB_PRE_IMM + 185100465U, // STRB_PRE_REG + 555185U, // STRBi12 + 546993U, // STRBrs + 551348U, // STRD + 185129396U, // STRD_POST + 185129396U, // STRD_PRE + 556692U, // STREX + 555310U, // STREXB + 555482U, // STREXD + 555668U, // STREXH + 547414U, // STRH + 185097553U, // STRHTi + 185101649U, // STRHTr + 185100886U, // STRH_POST + 185100886U, // STRH_PRE + 185101698U, // STRT_POST_IMM + 185101698U, // STRT_POST_REG + 185101460U, // STR_POST_IMM + 185101460U, // STR_POST_REG + 185097364U, // STR_PRE_IMM + 185101460U, // STR_PRE_REG + 556180U, // STRi12 + 547988U, // STRrs + 530678U, // SUBri + 530678U, // SUBrr + 559350U, // SUBrsi + 39158U, // SUBrsr + 1074313567U, // SVC + 556081U, // SWP + 555175U, // SWPB + 546898U, // SXTAB + 546523U, // SXTAB16 + 547371U, // SXTAH + 555242U, // SXTB + 554731U, // SXTB16 + 555637U, // SXTH + 539711U, // TEQri + 539711U, // TEQrr + 556095U, // TEQrsi + 547903U, // TEQrsr + 3092U, // TRAP + 3092U, // TRAPNaCl + 99545U, // TSB + 540040U, // TSTri + 540040U, // TSTrr + 556424U, // TSTrsi + 548232U, // TSTrsr + 554814U, // UADD16 + 554915U, // UADD8 + 556739U, // UASX + 548511U, // UBFX + 828656U, // UDF + 556511U, // UDIV + 554791U, // UHADD16 + 554895U, // UHADD8 + 556722U, // UHASX + 556581U, // UHSAX + 554753U, // UHSUB16 + 554856U, // UHSUB8 + 580285U, // UMAAL + 96990U, // UMLAL + 559952U, // UMULL + 554799U, // UQADD16 + 554902U, // UQADD8 + 556728U, // UQASX + 556587U, // UQSAX + 554761U, // UQSUB16 + 554863U, // UQSUB8 + 554882U, // USAD8 + 546650U, // USADA8 + 548098U, // USAT + 554828U, // USAT16 + 556598U, // USAX + 554776U, // USUB16 + 554876U, // USUB8 + 546904U, // UXTAB + 546531U, // UXTAB16 + 547377U, // UXTAH + 555247U, // UXTB + 554738U, // UXTB16 + 555642U, // UXTH + 169892547U, // VABALsv2i64 + 170023619U, // VABALsv4i32 + 170154691U, // VABALsv8i16 + 170285763U, // VABALuv2i64 + 170416835U, // VABALuv4i32 + 170547907U, // VABALuv8i16 + 170153971U, // VABAsv16i8 + 169891827U, // VABAsv2i32 + 170022899U, // VABAsv4i16 + 169891827U, // VABAsv4i32 + 170022899U, // VABAsv8i16 + 170153971U, // VABAsv8i8 + 170547187U, // VABAuv16i8 + 170285043U, // VABAuv2i32 + 170416115U, // VABAuv4i16 + 170285043U, // VABAuv4i32 + 170416115U, // VABAuv8i16 + 170547187U, // VABAuv8i8 + 186678015U, // VABDLsv2i64 + 186809087U, // VABDLsv4i32 + 186940159U, // VABDLsv8i16 + 187071231U, // VABDLuv2i64 + 187202303U, // VABDLuv4i32 + 187333375U, // VABDLuv8i16 + 253131119U, // VABDfd + 253131119U, // VABDfq + 253000047U, // VABDhd + 253000047U, // VABDhq + 186939759U, // VABDsv16i8 + 186677615U, // VABDsv2i32 + 186808687U, // VABDsv4i16 + 186677615U, // VABDsv4i32 + 186808687U, // VABDsv8i16 + 186939759U, // VABDsv8i8 + 187332975U, // VABDuv16i8 + 187070831U, // VABDuv2i32 + 187201903U, // VABDuv4i16 + 187070831U, // VABDuv4i32 + 187201903U, // VABDuv8i16 + 187332975U, // VABDuv8i8 + 252853412U, // VABSD + 252984484U, // VABSH + 253115556U, // VABSS + 253115556U, // VABSfd + 253115556U, // VABSfq + 252984484U, // VABShd + 252984484U, // VABShq + 1260666020U, // VABSv16i8 + 1260403876U, // VABSv2i32 + 1260534948U, // VABSv4i16 + 1260403876U, // VABSv4i32 + 1260534948U, // VABSv8i16 + 1260666020U, // VABSv8i8 + 253131233U, // VACGEfd + 253131233U, // VACGEfq + 253000161U, // VACGEhd + 253000161U, // VACGEhq + 253132096U, // VACGTfd + 253132096U, // VACGTfq + 253001024U, // VACGThd + 253001024U, // VACGThq + 252869011U, // VADDD + 253000083U, // VADDH + 187464621U, // VADDHNv2i32 + 187595693U, // VADDHNv4i16 + 187726765U, // VADDHNv8i8 + 186678028U, // VADDLsv2i64 + 186809100U, // VADDLsv4i32 + 186940172U, // VADDLsv8i16 + 187071244U, // VADDLuv2i64 + 187202316U, // VADDLuv4i32 + 187333388U, // VADDLuv8i16 + 253131155U, // VADDS + 186678772U, // VADDWsv2i64 + 186809844U, // VADDWsv4i32 + 186940916U, // VADDWsv8i16 + 187071988U, // VADDWuv2i64 + 187203060U, // VADDWuv4i32 + 187334132U, // VADDWuv8i16 + 253131155U, // VADDfd + 253131155U, // VADDfq + 253000083U, // VADDhd + 253000083U, // VADDhq + 187857299U, // VADDv16i8 + 187464083U, // VADDv1i64 + 187595155U, // VADDv2i32 + 187464083U, // VADDv2i64 + 187726227U, // VADDv4i16 + 187595155U, // VADDv4i32 + 187726227U, // VADDv8i16 + 187857299U, // VADDv8i8 + 555434U, // VANDd + 555434U, // VANDq + 555333U, // VBICd + 405698885U, // VBICiv2i32 + 405829957U, // VBICiv4i16 + 405698885U, // VBICiv4i32 + 405829957U, // VBICiv8i16 + 555333U, // VBICq + 547334U, // VBIFd + 547334U, // VBIFq + 548195U, // VBITd + 548195U, // VBITq + 547676U, // VBSLd + 547676U, // VBSLq + 185245957U, // VCADDv2f32 + 185246658U, // VCADDv4f16 + 185245957U, // VCADDv4f32 + 185246658U, // VCADDv8f16 + 253131834U, // VCEQfd + 253131834U, // VCEQfq + 253000762U, // VCEQhd + 253000762U, // VCEQhq + 187857978U, // VCEQv16i8 + 187595834U, // VCEQv2i32 + 187726906U, // VCEQv4i16 + 187595834U, // VCEQv4i32 + 187726906U, // VCEQv8i16 + 187857978U, // VCEQv8i8 + 1261583418U, // VCEQzv16i8 + 253115450U, // VCEQzv2f32 + 1261321274U, // VCEQzv2i32 + 252984378U, // VCEQzv4f16 + 253115450U, // VCEQzv4f32 + 1261452346U, // VCEQzv4i16 + 1261321274U, // VCEQzv4i32 + 252984378U, // VCEQzv8f16 + 1261452346U, // VCEQzv8i16 + 1261583418U, // VCEQzv8i8 + 253131239U, // VCGEfd + 253131239U, // VCGEfq + 253000167U, // VCGEhd + 253000167U, // VCGEhq + 186939879U, // VCGEsv16i8 + 186677735U, // VCGEsv2i32 + 186808807U, // VCGEsv4i16 + 186677735U, // VCGEsv4i32 + 186808807U, // VCGEsv8i16 + 186939879U, // VCGEsv8i8 + 187333095U, // VCGEuv16i8 + 187070951U, // VCGEuv2i32 + 187202023U, // VCGEuv4i16 + 187070951U, // VCGEuv4i32 + 187202023U, // VCGEuv8i16 + 187333095U, // VCGEuv8i8 + 1260665319U, // VCGEzv16i8 + 253114855U, // VCGEzv2f32 + 1260403175U, // VCGEzv2i32 + 252983783U, // VCGEzv4f16 + 253114855U, // VCGEzv4f32 + 1260534247U, // VCGEzv4i16 + 1260403175U, // VCGEzv4i32 + 252983783U, // VCGEzv8f16 + 1260534247U, // VCGEzv8i16 + 1260665319U, // VCGEzv8i8 + 253132102U, // VCGTfd + 253132102U, // VCGTfq + 253001030U, // VCGThd + 253001030U, // VCGThq + 186940742U, // VCGTsv16i8 + 186678598U, // VCGTsv2i32 + 186809670U, // VCGTsv4i16 + 186678598U, // VCGTsv4i32 + 186809670U, // VCGTsv8i16 + 186940742U, // VCGTsv8i8 + 187333958U, // VCGTuv16i8 + 187071814U, // VCGTuv2i32 + 187202886U, // VCGTuv4i16 + 187071814U, // VCGTuv4i32 + 187202886U, // VCGTuv8i16 + 187333958U, // VCGTuv8i8 + 1260666182U, // VCGTzv16i8 + 253115718U, // VCGTzv2f32 + 1260404038U, // VCGTzv2i32 + 252984646U, // VCGTzv4f16 + 253115718U, // VCGTzv4f32 + 1260535110U, // VCGTzv4i16 + 1260404038U, // VCGTzv4i32 + 252984646U, // VCGTzv8f16 + 1260535110U, // VCGTzv8i16 + 1260666182U, // VCGTzv8i8 + 1260665324U, // VCLEzv16i8 + 253114860U, // VCLEzv2f32 + 1260403180U, // VCLEzv2i32 + 252983788U, // VCLEzv4f16 + 253114860U, // VCLEzv4f32 + 1260534252U, // VCLEzv4i16 + 1260403180U, // VCLEzv4i32 + 252983788U, // VCLEzv8f16 + 1260534252U, // VCLEzv8i16 + 1260665324U, // VCLEzv8i8 + 1260666030U, // VCLSv16i8 + 1260403886U, // VCLSv2i32 + 1260534958U, // VCLSv4i16 + 1260403886U, // VCLSv4i32 + 1260534958U, // VCLSv8i16 + 1260666030U, // VCLSv8i8 + 1260666216U, // VCLTzv16i8 + 253115752U, // VCLTzv2f32 + 1260404072U, // VCLTzv2i32 + 252984680U, // VCLTzv4f16 + 253115752U, // VCLTzv4f32 + 1260535144U, // VCLTzv4i16 + 1260404072U, // VCLTzv4i32 + 252984680U, // VCLTzv8f16 + 1260535144U, // VCLTzv8i16 + 1260666216U, // VCLTzv8i8 + 1261584079U, // VCLZv16i8 + 1261321935U, // VCLZv2i32 + 1261453007U, // VCLZv4i16 + 1261321935U, // VCLZv4i32 + 1261453007U, // VCLZv8i16 + 1261584079U, // VCLZv8i8 + 168468718U, // VCMLAv2f32 + 168468718U, // VCMLAv2f32_indexed + 168469419U, // VCMLAv4f16 + 168469419U, // VCMLAv4f16_indexed + 168468718U, // VCMLAv4f32 + 168468718U, // VCMLAv4f32_indexed + 168469419U, // VCMLAv8f16 + 168469419U, // VCMLAv8f16_indexed + 252853282U, // VCMPD + 252852728U, // VCMPED + 252983800U, // VCMPEH + 253114872U, // VCMPES + 420657656U, // VCMPEZD + 420788728U, // VCMPEZH + 420919800U, // VCMPEZS + 252984354U, // VCMPH + 253115426U, // VCMPS + 420658210U, // VCMPZD + 420789282U, // VCMPZH + 420920354U, // VCMPZS + 408941U, // VCNTd + 408941U, // VCNTq + 1258987638U, // VCVTANSDf + 1258988339U, // VCVTANSDh + 1258987638U, // VCVTANSQf + 1258988339U, // VCVTANSQh + 1258987698U, // VCVTANUDf + 1258988399U, // VCVTANUDh + 1258987698U, // VCVTANUQf + 1258988399U, // VCVTANUQh + 1258987968U, // VCVTASD + 1258988219U, // VCVTASH + 1258987638U, // VCVTASS + 1258988028U, // VCVTAUD + 1258988279U, // VCVTAUH + 1258987698U, // VCVTAUS + 3422436U, // VCVTBDH + 3553508U, // VCVTBHD + 3684580U, // VCVTBHS + 3815652U, // VCVTBSH + 3947954U, // VCVTDS + 1258987653U, // VCVTMNSDf + 1258988354U, // VCVTMNSDh + 1258987653U, // VCVTMNSQf + 1258988354U, // VCVTMNSQh + 1258987713U, // VCVTMNUDf + 1258988414U, // VCVTMNUDh + 1258987713U, // VCVTMNUQf + 1258988414U, // VCVTMNUQh + 1258987983U, // VCVTMSD + 1258988234U, // VCVTMSH + 1258987653U, // VCVTMSS + 1258988043U, // VCVTMUD + 1258988294U, // VCVTMUH + 1258987713U, // VCVTMUS + 1258987668U, // VCVTNNSDf + 1258988369U, // VCVTNNSDh + 1258987668U, // VCVTNNSQf + 1258988369U, // VCVTNNSQh + 1258987728U, // VCVTNNUDf + 1258988429U, // VCVTNNUDh + 1258987728U, // VCVTNNUQf + 1258988429U, // VCVTNNUQh + 1258987998U, // VCVTNSD + 1258988249U, // VCVTNSH + 1258987668U, // VCVTNSS + 1258988058U, // VCVTNUD + 1258988309U, // VCVTNUH + 1258987728U, // VCVTNUS + 1258987683U, // VCVTPNSDf + 1258988384U, // VCVTPNSDh + 1258987683U, // VCVTPNSQf + 1258988384U, // VCVTPNSQh + 1258987743U, // VCVTPNUDf + 1258988444U, // VCVTPNUDh + 1258987743U, // VCVTPNUQf + 1258988444U, // VCVTPNUQh + 1258988013U, // VCVTPSD + 1258988264U, // VCVTPSH + 1258987683U, // VCVTPSS + 1258988073U, // VCVTPUD + 1258988324U, // VCVTPUH + 1258987743U, // VCVTPUS + 4079026U, // VCVTSD + 3423654U, // VCVTTDH + 3554726U, // VCVTTHD + 3685798U, // VCVTTHS + 3816870U, // VCVTTSH + 3816882U, // VCVTf2h + 440417714U, // VCVTf2sd + 440417714U, // VCVTf2sq + 440548786U, // VCVTf2ud + 440548786U, // VCVTf2uq + 2403368370U, // VCVTf2xsd + 2403368370U, // VCVTf2xsq + 2403499442U, // VCVTf2xud + 2403499442U, // VCVTf2xuq + 3685810U, // VCVTh2f + 440679858U, // VCVTh2sd + 440679858U, // VCVTh2sq + 440810930U, // VCVTh2ud + 440810930U, // VCVTh2uq + 2403630514U, // VCVTh2xsd + 2403630514U, // VCVTh2xsq + 2403761586U, // VCVTh2xud + 2403761586U, // VCVTh2xuq + 440942002U, // VCVTs2fd + 440942002U, // VCVTs2fq + 441073074U, // VCVTs2hd + 441073074U, // VCVTs2hq + 441204146U, // VCVTu2fd + 441204146U, // VCVTu2fq + 441335218U, // VCVTu2hd + 441335218U, // VCVTu2hq + 2403892658U, // VCVTxs2fd + 2403892658U, // VCVTxs2fq + 2404023730U, // VCVTxs2hd + 2404023730U, // VCVTxs2hq + 2404154802U, // VCVTxu2fd + 2404154802U, // VCVTxu2fq + 2404285874U, // VCVTxu2hd + 2404285874U, // VCVTxu2hq + 252870116U, // VDIVD + 253001188U, // VDIVH + 253132260U, // VDIVS + 146475U, // VDUP16d + 146475U, // VDUP16q + 277547U, // VDUP32d + 277547U, // VDUP32q + 408619U, // VDUP8d + 408619U, // VDUP8q + 162859U, // VDUPLN16d + 162859U, // VDUPLN16q + 293931U, // VDUPLN32d + 293931U, // VDUPLN32q + 425003U, // VDUPLN8d + 425003U, // VDUPLN8q + 556137U, // VEORd + 556137U, // VEORq + 155082U, // VEXTd16 + 286154U, // VEXTd32 + 417226U, // VEXTd8 + 155082U, // VEXTq16 + 286154U, // VEXTq32 + 5266890U, // VEXTq64 + 417226U, // VEXTq8 + 2400344115U, // VFMAD + 2400475187U, // VFMAH + 2400606259U, // VFMAS + 2400606259U, // VFMAfd + 2400606259U, // VFMAfq + 2400475187U, // VFMAhd + 2400475187U, // VFMAhq + 2400345284U, // VFMSD + 2400476356U, // VFMSH + 2400607428U, // VFMSS + 2400607428U, // VFMSfd + 2400607428U, // VFMSfq + 2400476356U, // VFMShd + 2400476356U, // VFMShq + 2400344120U, // VFNMAD + 2400475192U, // VFNMAH + 2400606264U, // VFNMAS + 2400345289U, // VFNMSD + 2400476361U, // VFNMSH + 2400607433U, // VFNMSS + 294377U, // VGETLNi32 + 3408035305U, // VGETLNs16 + 3408166377U, // VGETLNs8 + 3408428521U, // VGETLNu16 + 3408559593U, // VGETLNu8 + 186939777U, // VHADDsv16i8 + 186677633U, // VHADDsv2i32 + 186808705U, // VHADDsv4i16 + 186677633U, // VHADDsv4i32 + 186808705U, // VHADDsv8i16 + 186939777U, // VHADDsv8i8 + 187332993U, // VHADDuv16i8 + 187070849U, // VHADDuv2i32 + 187201921U, // VHADDuv4i16 + 187070849U, // VHADDuv4i32 + 187201921U, // VHADDuv8i16 + 187332993U, // VHADDuv8i8 + 186939642U, // VHSUBsv16i8 + 186677498U, // VHSUBsv2i32 + 186808570U, // VHSUBsv4i16 + 186677498U, // VHSUBsv4i32 + 186808570U, // VHSUBsv8i16 + 186939642U, // VHSUBsv8i8 + 187332858U, // VHSUBuv16i8 + 187070714U, // VHSUBuv2i32 + 187201786U, // VHSUBuv4i16 + 187070714U, // VHSUBuv4i32 + 187201786U, // VHSUBuv8i16 + 187332858U, // VHSUBuv8i8 + 1258988577U, // VINSH + 441597356U, // VJCVT + 3674371694U, // VLD1DUPd16 + 453138030U, // VLD1DUPd16wb_fixed + 453142126U, // VLD1DUPd16wb_register + 3674502766U, // VLD1DUPd32 + 453269102U, // VLD1DUPd32wb_fixed + 453273198U, // VLD1DUPd32wb_register + 3674633838U, // VLD1DUPd8 + 453400174U, // VLD1DUPd8wb_fixed + 453404270U, // VLD1DUPd8wb_register + 3691148910U, // VLD1DUPq16 + 469915246U, // VLD1DUPq16wb_fixed + 469919342U, // VLD1DUPq16wb_register + 3691279982U, // VLD1DUPq32 + 470046318U, // VLD1DUPq32wb_fixed + 470050414U, // VLD1DUPq32wb_register + 3691411054U, // VLD1DUPq8 + 470177390U, // VLD1DUPq8wb_fixed + 470181486U, // VLD1DUPq8wb_register + 1079273070U, // VLD1LNd16 + 1079350894U, // VLD1LNd16_UPD + 1079404142U, // VLD1LNd32 + 1079481966U, // VLD1LNd32_UPD + 1079535214U, // VLD1LNd8 + 1079613038U, // VLD1LNd8_UPD + 0U, // VLD1LNq16Pseudo + 0U, // VLD1LNq16Pseudo_UPD + 0U, // VLD1LNq32Pseudo + 0U, // VLD1LNq32Pseudo_UPD + 0U, // VLD1LNq8Pseudo + 0U, // VLD1LNq8Pseudo_UPD + 3707926126U, // VLD1d16 + 3355604590U, // VLD1d16Q + 0U, // VLD1d16QPseudo + 134370926U, // VLD1d16Qwb_fixed + 134375022U, // VLD1d16Qwb_register + 3288495726U, // VLD1d16T + 0U, // VLD1d16TPseudo + 67262062U, // VLD1d16Twb_fixed + 67266158U, // VLD1d16Twb_register + 486692462U, // VLD1d16wb_fixed + 486696558U, // VLD1d16wb_register + 3708057198U, // VLD1d32 + 3355735662U, // VLD1d32Q + 0U, // VLD1d32QPseudo + 134501998U, // VLD1d32Qwb_fixed + 134506094U, // VLD1d32Qwb_register + 3288626798U, // VLD1d32T + 0U, // VLD1d32TPseudo + 67393134U, // VLD1d32Twb_fixed + 67397230U, // VLD1d32Twb_register + 486823534U, // VLD1d32wb_fixed + 486827630U, // VLD1d32wb_register + 3713037934U, // VLD1d64 + 3360716398U, // VLD1d64Q + 0U, // VLD1d64QPseudo + 0U, // VLD1d64QPseudoWB_fixed + 0U, // VLD1d64QPseudoWB_register + 139482734U, // VLD1d64Qwb_fixed + 139486830U, // VLD1d64Qwb_register + 3293607534U, // VLD1d64T + 0U, // VLD1d64TPseudo + 0U, // VLD1d64TPseudoWB_fixed + 0U, // VLD1d64TPseudoWB_register + 72373870U, // VLD1d64Twb_fixed + 72377966U, // VLD1d64Twb_register + 491804270U, // VLD1d64wb_fixed + 491808366U, // VLD1d64wb_register + 3708188270U, // VLD1d8 + 3355866734U, // VLD1d8Q + 0U, // VLD1d8QPseudo + 134633070U, // VLD1d8Qwb_fixed + 134637166U, // VLD1d8Qwb_register + 3288757870U, // VLD1d8T + 0U, // VLD1d8TPseudo + 67524206U, // VLD1d8Twb_fixed + 67528302U, // VLD1d8Twb_register + 486954606U, // VLD1d8wb_fixed + 486958702U, // VLD1d8wb_register + 3724703342U, // VLD1q16 + 0U, // VLD1q16HighQPseudo + 0U, // VLD1q16HighTPseudo + 0U, // VLD1q16LowQPseudo_UPD + 0U, // VLD1q16LowTPseudo_UPD + 503469678U, // VLD1q16wb_fixed + 503473774U, // VLD1q16wb_register + 3724834414U, // VLD1q32 + 0U, // VLD1q32HighQPseudo + 0U, // VLD1q32HighTPseudo + 0U, // VLD1q32LowQPseudo_UPD + 0U, // VLD1q32LowTPseudo_UPD + 503600750U, // VLD1q32wb_fixed + 503604846U, // VLD1q32wb_register + 3729815150U, // VLD1q64 + 0U, // VLD1q64HighQPseudo + 0U, // VLD1q64HighTPseudo + 0U, // VLD1q64LowQPseudo_UPD + 0U, // VLD1q64LowTPseudo_UPD + 508581486U, // VLD1q64wb_fixed + 508585582U, // VLD1q64wb_register + 3724965486U, // VLD1q8 + 0U, // VLD1q8HighQPseudo + 0U, // VLD1q8HighTPseudo + 0U, // VLD1q8LowQPseudo_UPD + 0U, // VLD1q8LowTPseudo_UPD + 503731822U, // VLD1q8wb_fixed + 503735918U, // VLD1q8wb_register + 3691148954U, // VLD2DUPd16 + 469915290U, // VLD2DUPd16wb_fixed + 469919386U, // VLD2DUPd16wb_register + 3741480602U, // VLD2DUPd16x2 + 520246938U, // VLD2DUPd16x2wb_fixed + 520251034U, // VLD2DUPd16x2wb_register + 3691280026U, // VLD2DUPd32 + 470046362U, // VLD2DUPd32wb_fixed + 470050458U, // VLD2DUPd32wb_register + 3741611674U, // VLD2DUPd32x2 + 520378010U, // VLD2DUPd32x2wb_fixed + 520382106U, // VLD2DUPd32x2wb_register + 3691411098U, // VLD2DUPd8 + 470177434U, // VLD2DUPd8wb_fixed + 470181530U, // VLD2DUPd8wb_register + 3741742746U, // VLD2DUPd8x2 + 520509082U, // VLD2DUPd8x2wb_fixed + 520513178U, // VLD2DUPd8x2wb_register + 0U, // VLD2DUPq16EvenPseudo + 0U, // VLD2DUPq16OddPseudo + 0U, // VLD2DUPq32EvenPseudo + 0U, // VLD2DUPq32OddPseudo + 0U, // VLD2DUPq8EvenPseudo + 0U, // VLD2DUPq8OddPseudo + 1079350938U, // VLD2LNd16 + 0U, // VLD2LNd16Pseudo + 0U, // VLD2LNd16Pseudo_UPD + 1079355034U, // VLD2LNd16_UPD + 1079482010U, // VLD2LNd32 + 0U, // VLD2LNd32Pseudo + 0U, // VLD2LNd32Pseudo_UPD + 1079486106U, // VLD2LNd32_UPD + 1079613082U, // VLD2LNd8 + 0U, // VLD2LNd8Pseudo + 0U, // VLD2LNd8Pseudo_UPD + 1079617178U, // VLD2LNd8_UPD + 1079350938U, // VLD2LNq16 + 0U, // VLD2LNq16Pseudo + 0U, // VLD2LNq16Pseudo_UPD + 1079355034U, // VLD2LNq16_UPD + 1079482010U, // VLD2LNq32 + 0U, // VLD2LNq32Pseudo + 0U, // VLD2LNq32Pseudo_UPD + 1079486106U, // VLD2LNq32_UPD + 3758257818U, // VLD2b16 + 537024154U, // VLD2b16wb_fixed + 537028250U, // VLD2b16wb_register + 3758388890U, // VLD2b32 + 537155226U, // VLD2b32wb_fixed + 537159322U, // VLD2b32wb_register + 3758519962U, // VLD2b8 + 537286298U, // VLD2b8wb_fixed + 537290394U, // VLD2b8wb_register + 3724703386U, // VLD2d16 + 503469722U, // VLD2d16wb_fixed + 503473818U, // VLD2d16wb_register + 3724834458U, // VLD2d32 + 503600794U, // VLD2d32wb_fixed + 503604890U, // VLD2d32wb_register + 3724965530U, // VLD2d8 + 503731866U, // VLD2d8wb_fixed + 503735962U, // VLD2d8wb_register + 3355604634U, // VLD2q16 + 0U, // VLD2q16Pseudo + 0U, // VLD2q16PseudoWB_fixed + 0U, // VLD2q16PseudoWB_register + 134370970U, // VLD2q16wb_fixed + 134375066U, // VLD2q16wb_register + 3355735706U, // VLD2q32 + 0U, // VLD2q32Pseudo + 0U, // VLD2q32PseudoWB_fixed + 0U, // VLD2q32PseudoWB_register + 134502042U, // VLD2q32wb_fixed + 134506138U, // VLD2q32wb_register + 3355866778U, // VLD2q8 + 0U, // VLD2q8Pseudo + 0U, // VLD2q8PseudoWB_fixed + 0U, // VLD2q8PseudoWB_register + 134633114U, // VLD2q8wb_fixed + 134637210U, // VLD2q8wb_register + 2153014970U, // VLD3DUPd16 + 0U, // VLD3DUPd16Pseudo + 0U, // VLD3DUPd16Pseudo_UPD + 2153092794U, // VLD3DUPd16_UPD + 2153146042U, // VLD3DUPd32 + 0U, // VLD3DUPd32Pseudo + 0U, // VLD3DUPd32Pseudo_UPD + 2153223866U, // VLD3DUPd32_UPD + 2153277114U, // VLD3DUPd8 + 0U, // VLD3DUPd8Pseudo + 0U, // VLD3DUPd8Pseudo_UPD + 2153354938U, // VLD3DUPd8_UPD + 2153014970U, // VLD3DUPq16 + 0U, // VLD3DUPq16EvenPseudo + 0U, // VLD3DUPq16OddPseudo + 2153092794U, // VLD3DUPq16_UPD + 2153146042U, // VLD3DUPq32 + 0U, // VLD3DUPq32EvenPseudo + 0U, // VLD3DUPq32OddPseudo + 2153223866U, // VLD3DUPq32_UPD + 2153277114U, // VLD3DUPq8 + 0U, // VLD3DUPq8EvenPseudo + 0U, // VLD3DUPq8OddPseudo + 2153354938U, // VLD3DUPq8_UPD + 1079355066U, // VLD3LNd16 + 0U, // VLD3LNd16Pseudo + 0U, // VLD3LNd16Pseudo_UPD + 1079359162U, // VLD3LNd16_UPD + 1079486138U, // VLD3LNd32 + 0U, // VLD3LNd32Pseudo + 0U, // VLD3LNd32Pseudo_UPD + 1079490234U, // VLD3LNd32_UPD + 1079617210U, // VLD3LNd8 + 0U, // VLD3LNd8Pseudo + 0U, // VLD3LNd8Pseudo_UPD + 1079621306U, // VLD3LNd8_UPD + 1079355066U, // VLD3LNq16 + 0U, // VLD3LNq16Pseudo + 0U, // VLD3LNq16Pseudo_UPD + 1079359162U, // VLD3LNq16_UPD + 1079486138U, // VLD3LNq32 + 0U, // VLD3LNq32Pseudo + 0U, // VLD3LNq32Pseudo_UPD + 1079490234U, // VLD3LNq32_UPD + 5531322U, // VLD3d16 + 0U, // VLD3d16Pseudo + 0U, // VLD3d16Pseudo_UPD + 5609146U, // VLD3d16_UPD + 5662394U, // VLD3d32 + 0U, // VLD3d32Pseudo + 0U, // VLD3d32Pseudo_UPD + 5740218U, // VLD3d32_UPD + 5793466U, // VLD3d8 + 0U, // VLD3d8Pseudo + 0U, // VLD3d8Pseudo_UPD + 5871290U, // VLD3d8_UPD + 5531322U, // VLD3q16 + 0U, // VLD3q16Pseudo_UPD + 5609146U, // VLD3q16_UPD + 0U, // VLD3q16oddPseudo + 0U, // VLD3q16oddPseudo_UPD + 5662394U, // VLD3q32 + 0U, // VLD3q32Pseudo_UPD + 5740218U, // VLD3q32_UPD + 0U, // VLD3q32oddPseudo + 0U, // VLD3q32oddPseudo_UPD + 5793466U, // VLD3q8 + 0U, // VLD3q8Pseudo_UPD + 5871290U, // VLD3q8_UPD + 0U, // VLD3q8oddPseudo + 0U, // VLD3q8oddPseudo_UPD + 2153043665U, // VLD4DUPd16 + 0U, // VLD4DUPd16Pseudo + 0U, // VLD4DUPd16Pseudo_UPD + 2153105105U, // VLD4DUPd16_UPD + 2153174737U, // VLD4DUPd32 + 0U, // VLD4DUPd32Pseudo + 0U, // VLD4DUPd32Pseudo_UPD + 2153236177U, // VLD4DUPd32_UPD + 2153305809U, // VLD4DUPd8 + 0U, // VLD4DUPd8Pseudo + 0U, // VLD4DUPd8Pseudo_UPD + 2153367249U, // VLD4DUPd8_UPD + 2153043665U, // VLD4DUPq16 + 0U, // VLD4DUPq16EvenPseudo + 0U, // VLD4DUPq16OddPseudo + 2153105105U, // VLD4DUPq16_UPD + 2153174737U, // VLD4DUPq32 + 0U, // VLD4DUPq32EvenPseudo + 0U, // VLD4DUPq32OddPseudo + 2153236177U, // VLD4DUPq32_UPD + 2153305809U, // VLD4DUPq8 + 0U, // VLD4DUPq8EvenPseudo + 0U, // VLD4DUPq8OddPseudo + 2153367249U, // VLD4DUPq8_UPD + 1079359185U, // VLD4LNd16 + 0U, // VLD4LNd16Pseudo + 0U, // VLD4LNd16Pseudo_UPD + 1079367377U, // VLD4LNd16_UPD + 1079490257U, // VLD4LNd32 + 0U, // VLD4LNd32Pseudo + 0U, // VLD4LNd32Pseudo_UPD + 1079498449U, // VLD4LNd32_UPD + 1079621329U, // VLD4LNd8 + 0U, // VLD4LNd8Pseudo + 0U, // VLD4LNd8Pseudo_UPD + 1079629521U, // VLD4LNd8_UPD + 1079359185U, // VLD4LNq16 + 0U, // VLD4LNq16Pseudo + 0U, // VLD4LNq16Pseudo_UPD + 1079367377U, // VLD4LNq16_UPD + 1079490257U, // VLD4LNq32 + 0U, // VLD4LNq32Pseudo + 0U, // VLD4LNq32Pseudo_UPD + 1079498449U, // VLD4LNq32_UPD + 5560017U, // VLD4d16 + 0U, // VLD4d16Pseudo + 0U, // VLD4d16Pseudo_UPD + 5621457U, // VLD4d16_UPD + 5691089U, // VLD4d32 + 0U, // VLD4d32Pseudo + 0U, // VLD4d32Pseudo_UPD + 5752529U, // VLD4d32_UPD + 5822161U, // VLD4d8 + 0U, // VLD4d8Pseudo + 0U, // VLD4d8Pseudo_UPD + 5883601U, // VLD4d8_UPD + 5560017U, // VLD4q16 + 0U, // VLD4q16Pseudo_UPD + 5621457U, // VLD4q16_UPD + 0U, // VLD4q16oddPseudo + 0U, // VLD4q16oddPseudo_UPD + 5691089U, // VLD4q32 + 0U, // VLD4q32Pseudo_UPD + 5752529U, // VLD4q32_UPD + 0U, // VLD4q32oddPseudo + 0U, // VLD4q32oddPseudo_UPD + 5822161U, // VLD4q8 + 0U, // VLD4q8Pseudo_UPD + 5883601U, // VLD4q8_UPD + 0U, // VLD4q8oddPseudo + 0U, // VLD4q8oddPseudo_UPD + 2332571774U, // VLDMDDB_UPD + 571406U, // VLDMDIA + 2332571662U, // VLDMDIA_UPD + 0U, // VLDMQIA + 2332571774U, // VLDMSDB_UPD + 571406U, // VLDMSIA + 2332571662U, // VLDMSIA_UPD + 556114U, // VLDRD + 162898U, // VLDRH + 556114U, // VLDRS + 1074314122U, // VLLDM + 1074314128U, // VLSTM + 185246300U, // VMAXNMD + 185246693U, // VMAXNMH + 185245992U, // VMAXNMNDf + 185246693U, // VMAXNMNDh + 185245992U, // VMAXNMNQf + 185246693U, // VMAXNMNQh + 185245992U, // VMAXNMS + 253132314U, // VMAXfd + 253132314U, // VMAXfq + 253001242U, // VMAXhd + 253001242U, // VMAXhq + 186940954U, // VMAXsv16i8 + 186678810U, // VMAXsv2i32 + 186809882U, // VMAXsv4i16 + 186678810U, // VMAXsv4i32 + 186809882U, // VMAXsv8i16 + 186940954U, // VMAXsv8i8 + 187334170U, // VMAXuv16i8 + 187072026U, // VMAXuv2i32 + 187203098U, // VMAXuv4i16 + 187072026U, // VMAXuv4i32 + 187203098U, // VMAXuv8i16 + 187334170U, // VMAXuv8i8 + 185246288U, // VMINNMD + 185246681U, // VMINNMH + 185245980U, // VMINNMNDf + 185246681U, // VMINNMNDh + 185245980U, // VMINNMNQf + 185246681U, // VMINNMNQh + 185245980U, // VMINNMS + 253131706U, // VMINfd + 253131706U, // VMINfq + 253000634U, // VMINhd + 253000634U, // VMINhq + 186940346U, // VMINsv16i8 + 186678202U, // VMINsv2i32 + 186809274U, // VMINsv4i16 + 186678202U, // VMINsv4i32 + 186809274U, // VMINsv8i16 + 186940346U, // VMINsv8i8 + 187333562U, // VMINuv16i8 + 187071418U, // VMINuv2i32 + 187202490U, // VMINuv4i16 + 187071418U, // VMINuv4i32 + 187202490U, // VMINuv8i16 + 187333562U, // VMINuv8i8 + 2400344110U, // VMLAD + 2400475182U, // VMLAH + 169896676U, // VMLALslsv2i32 + 170027748U, // VMLALslsv4i16 + 170289892U, // VMLALsluv2i32 + 170420964U, // VMLALsluv4i16 + 169892580U, // VMLALsv2i64 + 170023652U, // VMLALsv4i32 + 170154724U, // VMLALsv8i16 + 170285796U, // VMLALuv2i64 + 170416868U, // VMLALuv4i32 + 170547940U, // VMLALuv8i16 + 2400606254U, // VMLAS + 2400606254U, // VMLAfd + 2400606254U, // VMLAfq + 2400475182U, // VMLAhd + 2400475182U, // VMLAhq + 2400610350U, // VMLAslfd + 2400610350U, // VMLAslfq + 2400479278U, // VMLAslhd + 2400479278U, // VMLAslhq + 170813486U, // VMLAslv2i32 + 170944558U, // VMLAslv4i16 + 170813486U, // VMLAslv4i32 + 170944558U, // VMLAslv8i16 + 171071534U, // VMLAv16i8 + 170809390U, // VMLAv2i32 + 170940462U, // VMLAv4i16 + 170809390U, // VMLAv4i32 + 170940462U, // VMLAv8i16 + 171071534U, // VMLAv8i8 + 2400345279U, // VMLSD + 2400476351U, // VMLSH + 169896809U, // VMLSLslsv2i32 + 170027881U, // VMLSLslsv4i16 + 170290025U, // VMLSLsluv2i32 + 170421097U, // VMLSLsluv4i16 + 169892713U, // VMLSLsv2i64 + 170023785U, // VMLSLsv4i32 + 170154857U, // VMLSLsv8i16 + 170285929U, // VMLSLuv2i64 + 170417001U, // VMLSLuv4i32 + 170548073U, // VMLSLuv8i16 + 2400607423U, // VMLSS + 2400607423U, // VMLSfd + 2400607423U, // VMLSfq + 2400476351U, // VMLShd + 2400476351U, // VMLShq + 2400611519U, // VMLSslfd + 2400611519U, // VMLSslfq + 2400480447U, // VMLSslhd + 2400480447U, // VMLSslhq + 170814655U, // VMLSslv2i32 + 170945727U, // VMLSslv4i16 + 170814655U, // VMLSslv4i32 + 170945727U, // VMLSslv8i16 + 171072703U, // VMLSv16i8 + 170810559U, // VMLSv2i32 + 170941631U, // VMLSv4i16 + 170810559U, // VMLSv4i32 + 170941631U, // VMLSv8i16 + 171072703U, // VMLSv8i8 + 252853737U, // VMOVD + 556521U, // VMOVDRR + 1258988623U, // VMOVH + 252984809U, // VMOVHR + 1260403588U, // VMOVLsv2i64 + 1260534660U, // VMOVLsv4i32 + 1260665732U, // VMOVLsv8i16 + 1260796804U, // VMOVLuv2i64 + 1260927876U, // VMOVLuv4i32 + 1261058948U, // VMOVLuv8i16 + 1261190158U, // VMOVNv2i32 + 1261321230U, // VMOVNv4i16 + 1261452302U, // VMOVNv8i8 + 252984809U, // VMOVRH + 556521U, // VMOVRRD + 548329U, // VMOVRRS + 540137U, // VMOVRS + 253115881U, // VMOVS + 540137U, // VMOVSR + 548329U, // VMOVSRR + 405945833U, // VMOVv16i8 + 405552617U, // VMOVv1i64 + 1326857705U, // VMOVv2f32 + 405683689U, // VMOVv2i32 + 405552617U, // VMOVv2i64 + 1326857705U, // VMOVv4f32 + 405814761U, // VMOVv4i16 + 405683689U, // VMOVv4i32 + 405814761U, // VMOVv8i16 + 405945833U, // VMOVv8i8 + 3221798113U, // VMRS + 572641U, // VMRS_FPEXC + 1074314465U, // VMRS_FPINST + 2148056289U, // VMRS_FPINST2 + 3221798113U, // VMRS_FPSID + 572641U, // VMRS_MVFR0 + 1074314465U, // VMRS_MVFR1 + 2148056289U, // VMRS_MVFR2 + 5946503U, // VMSR + 6077575U, // VMSR_FPEXC + 6208647U, // VMSR_FPINST + 6339719U, // VMSR_FPINST2 + 6470791U, // VMSR_FPSID + 252869503U, // VMULD + 253000575U, // VMULH + 185246384U, // VMULLp64 + 6585174U, // VMULLp8 + 186669910U, // VMULLslsv2i32 + 186800982U, // VMULLslsv4i16 + 187063126U, // VMULLsluv2i32 + 187194198U, // VMULLsluv4i16 + 186678102U, // VMULLsv2i64 + 186809174U, // VMULLsv4i32 + 186940246U, // VMULLsv8i16 + 187071318U, // VMULLuv2i64 + 187202390U, // VMULLuv4i32 + 187333462U, // VMULLuv8i16 + 253131647U, // VMULS + 253131647U, // VMULfd + 253131647U, // VMULfq + 253000575U, // VMULhd + 253000575U, // VMULhq + 6585215U, // VMULpd + 6585215U, // VMULpq + 253123455U, // VMULslfd + 253123455U, // VMULslfq + 252992383U, // VMULslhd + 252992383U, // VMULslhq + 187587455U, // VMULslv2i32 + 187718527U, // VMULslv4i16 + 187587455U, // VMULslv4i32 + 187718527U, // VMULslv8i16 + 187857791U, // VMULv16i8 + 187595647U, // VMULv2i32 + 187726719U, // VMULv4i16 + 187595647U, // VMULv4i32 + 187726719U, // VMULv8i16 + 187857791U, // VMULv8i8 + 539650U, // VMVNd + 539650U, // VMVNq + 405683202U, // VMVNv2i32 + 405814274U, // VMVNv4i16 + 405683202U, // VMVNv4i32 + 405814274U, // VMVNv8i16 + 252852757U, // VNEGD + 252983829U, // VNEGH + 253114901U, // VNEGS + 253114901U, // VNEGf32q + 253114901U, // VNEGfd + 252983829U, // VNEGhd + 252983829U, // VNEGhq + 1260534293U, // VNEGs16d + 1260534293U, // VNEGs16q + 1260403221U, // VNEGs32d + 1260403221U, // VNEGs32q + 1260665365U, // VNEGs8d + 1260665365U, // VNEGs8q + 2400344104U, // VNMLAD + 2400475176U, // VNMLAH + 2400606248U, // VNMLAS + 2400345273U, // VNMLSD + 2400476345U, // VNMLSH + 2400607417U, // VNMLSS + 252869497U, // VNMULD + 253000569U, // VNMULH + 253131641U, // VNMULS + 555999U, // VORNd + 555999U, // VORNq + 556151U, // VORRd + 405699703U, // VORRiv2i32 + 405830775U, // VORRiv4i16 + 405699703U, // VORRiv4i32 + 405830775U, // VORRiv8i16 + 556151U, // VORRq + 1243904713U, // VPADALsv16i8 + 1243642569U, // VPADALsv2i32 + 1243773641U, // VPADALsv4i16 + 1243642569U, // VPADALsv4i32 + 1243773641U, // VPADALsv8i16 + 1243904713U, // VPADALsv8i8 + 1244297929U, // VPADALuv16i8 + 1244035785U, // VPADALuv2i32 + 1244166857U, // VPADALuv4i16 + 1244035785U, // VPADALuv4i32 + 1244166857U, // VPADALuv8i16 + 1244297929U, // VPADALuv8i8 + 1260665605U, // VPADDLsv16i8 + 1260403461U, // VPADDLsv2i32 + 1260534533U, // VPADDLsv4i16 + 1260403461U, // VPADDLsv4i32 + 1260534533U, // VPADDLsv8i16 + 1260665605U, // VPADDLsv8i8 + 1261058821U, // VPADDLuv16i8 + 1260796677U, // VPADDLuv2i32 + 1260927749U, // VPADDLuv4i16 + 1260796677U, // VPADDLuv4i32 + 1260927749U, // VPADDLuv8i16 + 1261058821U, // VPADDLuv8i8 + 253131143U, // VPADDf + 253000071U, // VPADDh + 187726215U, // VPADDi16 + 187595143U, // VPADDi32 + 187857287U, // VPADDi8 + 253132308U, // VPMAXf + 253001236U, // VPMAXh + 186809876U, // VPMAXs16 + 186678804U, // VPMAXs32 + 186940948U, // VPMAXs8 + 187203092U, // VPMAXu16 + 187072020U, // VPMAXu32 + 187334164U, // VPMAXu8 + 253131700U, // VPMINf + 253000628U, // VPMINh + 186809268U, // VPMINs16 + 186678196U, // VPMINs32 + 186940340U, // VPMINs8 + 187202484U, // VPMINu16 + 187071412U, // VPMINu32 + 187333556U, // VPMINu8 + 1260666014U, // VQABSv16i8 + 1260403870U, // VQABSv2i32 + 1260534942U, // VQABSv4i16 + 1260403870U, // VQABSv4i32 + 1260534942U, // VQABSv8i16 + 1260666014U, // VQABSv8i8 + 186939789U, // VQADDsv16i8 + 191265165U, // VQADDsv1i64 + 186677645U, // VQADDsv2i32 + 191265165U, // VQADDsv2i64 + 186808717U, // VQADDsv4i16 + 186677645U, // VQADDsv4i32 + 186808717U, // VQADDsv8i16 + 186939789U, // VQADDsv8i8 + 187333005U, // VQADDuv16i8 + 191396237U, // VQADDuv1i64 + 187070861U, // VQADDuv2i32 + 191396237U, // VQADDuv2i64 + 187201933U, // VQADDuv4i16 + 187070861U, // VQADDuv4i32 + 187201933U, // VQADDuv8i16 + 187333005U, // VQADDuv8i8 + 169896656U, // VQDMLALslv2i32 + 170027728U, // VQDMLALslv4i16 + 169892560U, // VQDMLALv2i64 + 170023632U, // VQDMLALv4i32 + 169896801U, // VQDMLSLslv2i32 + 170027873U, // VQDMLSLslv4i16 + 169892705U, // VQDMLSLv2i64 + 170023777U, // VQDMLSLv4i32 + 186669632U, // VQDMULHslv2i32 + 186800704U, // VQDMULHslv4i16 + 186669632U, // VQDMULHslv4i32 + 186800704U, // VQDMULHslv8i16 + 186677824U, // VQDMULHv2i32 + 186808896U, // VQDMULHv4i16 + 186677824U, // VQDMULHv4i32 + 186808896U, // VQDMULHv8i16 + 186669890U, // VQDMULLslv2i32 + 186800962U, // VQDMULLslv4i16 + 186678082U, // VQDMULLv2i64 + 186809154U, // VQDMULLv4i32 + 1264991226U, // VQMOVNsuv2i32 + 1260403706U, // VQMOVNsuv4i16 + 1260534778U, // VQMOVNsuv8i8 + 1264991239U, // VQMOVNsv2i32 + 1260403719U, // VQMOVNsv4i16 + 1260534791U, // VQMOVNsv8i8 + 1265122311U, // VQMOVNuv2i32 + 1260796935U, // VQMOVNuv4i16 + 1260928007U, // VQMOVNuv8i8 + 1260665359U, // VQNEGv16i8 + 1260403215U, // VQNEGv2i32 + 1260534287U, // VQNEGv4i16 + 1260403215U, // VQNEGv4i32 + 1260534287U, // VQNEGv8i16 + 1260665359U, // VQNEGv8i8 + 169896482U, // VQRDMLAHslv2i32 + 170027554U, // VQRDMLAHslv4i16 + 169896482U, // VQRDMLAHslv4i32 + 170027554U, // VQRDMLAHslv8i16 + 169892386U, // VQRDMLAHv2i32 + 170023458U, // VQRDMLAHv4i16 + 169892386U, // VQRDMLAHv4i32 + 170023458U, // VQRDMLAHv8i16 + 169896539U, // VQRDMLSHslv2i32 + 170027611U, // VQRDMLSHslv4i16 + 169896539U, // VQRDMLSHslv4i32 + 170027611U, // VQRDMLSHslv8i16 + 169892443U, // VQRDMLSHv2i32 + 170023515U, // VQRDMLSHv4i16 + 169892443U, // VQRDMLSHv4i32 + 170023515U, // VQRDMLSHv8i16 + 186669640U, // VQRDMULHslv2i32 + 186800712U, // VQRDMULHslv4i16 + 186669640U, // VQRDMULHslv4i32 + 186800712U, // VQRDMULHslv8i16 + 186677832U, // VQRDMULHv2i32 + 186808904U, // VQRDMULHv4i16 + 186677832U, // VQRDMULHv4i32 + 186808904U, // VQRDMULHv8i16 + 186940188U, // VQRSHLsv16i8 + 191265564U, // VQRSHLsv1i64 + 186678044U, // VQRSHLsv2i32 + 191265564U, // VQRSHLsv2i64 + 186809116U, // VQRSHLsv4i16 + 186678044U, // VQRSHLsv4i32 + 186809116U, // VQRSHLsv8i16 + 186940188U, // VQRSHLsv8i8 + 187333404U, // VQRSHLuv16i8 + 191396636U, // VQRSHLuv1i64 + 187071260U, // VQRSHLuv2i32 + 191396636U, // VQRSHLuv2i64 + 187202332U, // VQRSHLuv4i16 + 187071260U, // VQRSHLuv4i32 + 187202332U, // VQRSHLuv8i16 + 187333404U, // VQRSHLuv8i8 + 191265738U, // VQRSHRNsv2i32 + 186678218U, // VQRSHRNsv4i16 + 186809290U, // VQRSHRNsv8i8 + 191396810U, // VQRSHRNuv2i32 + 187071434U, // VQRSHRNuv4i16 + 187202506U, // VQRSHRNuv8i8 + 191265777U, // VQRSHRUNv2i32 + 186678257U, // VQRSHRUNv4i16 + 186809329U, // VQRSHRUNv8i8 + 186940182U, // VQSHLsiv16i8 + 191265558U, // VQSHLsiv1i64 + 186678038U, // VQSHLsiv2i32 + 191265558U, // VQSHLsiv2i64 + 186809110U, // VQSHLsiv4i16 + 186678038U, // VQSHLsiv4i32 + 186809110U, // VQSHLsiv8i16 + 186940182U, // VQSHLsiv8i8 + 186940879U, // VQSHLsuv16i8 + 191266255U, // VQSHLsuv1i64 + 186678735U, // VQSHLsuv2i32 + 191266255U, // VQSHLsuv2i64 + 186809807U, // VQSHLsuv4i16 + 186678735U, // VQSHLsuv4i32 + 186809807U, // VQSHLsuv8i16 + 186940879U, // VQSHLsuv8i8 + 186940182U, // VQSHLsv16i8 + 191265558U, // VQSHLsv1i64 + 186678038U, // VQSHLsv2i32 + 191265558U, // VQSHLsv2i64 + 186809110U, // VQSHLsv4i16 + 186678038U, // VQSHLsv4i32 + 186809110U, // VQSHLsv8i16 + 186940182U, // VQSHLsv8i8 + 187333398U, // VQSHLuiv16i8 + 191396630U, // VQSHLuiv1i64 + 187071254U, // VQSHLuiv2i32 + 191396630U, // VQSHLuiv2i64 + 187202326U, // VQSHLuiv4i16 + 187071254U, // VQSHLuiv4i32 + 187202326U, // VQSHLuiv8i16 + 187333398U, // VQSHLuiv8i8 + 187333398U, // VQSHLuv16i8 + 191396630U, // VQSHLuv1i64 + 187071254U, // VQSHLuv2i32 + 191396630U, // VQSHLuv2i64 + 187202326U, // VQSHLuv4i16 + 187071254U, // VQSHLuv4i32 + 187202326U, // VQSHLuv8i16 + 187333398U, // VQSHLuv8i8 + 191265731U, // VQSHRNsv2i32 + 186678211U, // VQSHRNsv4i16 + 186809283U, // VQSHRNsv8i8 + 191396803U, // VQSHRNuv2i32 + 187071427U, // VQSHRNuv4i16 + 187202499U, // VQSHRNuv8i8 + 191265769U, // VQSHRUNv2i32 + 186678249U, // VQSHRUNv4i16 + 186809321U, // VQSHRUNv8i8 + 186939648U, // VQSUBsv16i8 + 191265024U, // VQSUBsv1i64 + 186677504U, // VQSUBsv2i32 + 191265024U, // VQSUBsv2i64 + 186808576U, // VQSUBsv4i16 + 186677504U, // VQSUBsv4i32 + 186808576U, // VQSUBsv8i16 + 186939648U, // VQSUBsv8i8 + 187332864U, // VQSUBuv16i8 + 191396096U, // VQSUBuv1i64 + 187070720U, // VQSUBuv2i32 + 191396096U, // VQSUBuv2i64 + 187201792U, // VQSUBuv4i16 + 187070720U, // VQSUBuv4i32 + 187201792U, // VQSUBuv8i16 + 187332864U, // VQSUBuv8i8 + 187464613U, // VRADDHNv2i32 + 187595685U, // VRADDHNv4i16 + 187726757U, // VRADDHNv8i8 + 1260796401U, // VRECPEd + 253114865U, // VRECPEfd + 253114865U, // VRECPEfq + 252983793U, // VRECPEhd + 252983793U, // VRECPEhq + 1260796401U, // VRECPEq + 253131994U, // VRECPSfd + 253131994U, // VRECPSfq + 253000922U, // VRECPShd + 253000922U, // VRECPShq + 407379U, // VREV16d8 + 407379U, // VREV16q8 + 145022U, // VREV32d16 + 407166U, // VREV32d8 + 145022U, // VREV32q16 + 407166U, // VREV32q8 + 145098U, // VREV64d16 + 276170U, // VREV64d32 + 407242U, // VREV64d8 + 145098U, // VREV64q16 + 276170U, // VREV64q32 + 407242U, // VREV64q8 + 186939770U, // VRHADDsv16i8 + 186677626U, // VRHADDsv2i32 + 186808698U, // VRHADDsv4i16 + 186677626U, // VRHADDsv4i32 + 186808698U, // VRHADDsv8i16 + 186939770U, // VRHADDsv8i8 + 187332986U, // VRHADDuv16i8 + 187070842U, // VRHADDuv2i32 + 187201914U, // VRHADDuv4i16 + 187070842U, // VRHADDuv4i32 + 187201914U, // VRHADDuv8i16 + 187332986U, // VRHADDuv8i8 + 1258988088U, // VRINTAD + 1258988470U, // VRINTAH + 1258987769U, // VRINTANDf + 1258988470U, // VRINTANDh + 1258987769U, // VRINTANQf + 1258988470U, // VRINTANQh + 1258987769U, // VRINTAS + 1258988136U, // VRINTMD + 1258988529U, // VRINTMH + 1258987828U, // VRINTMNDf + 1258988529U, // VRINTMNDh + 1258987828U, // VRINTMNQf + 1258988529U, // VRINTMNQh + 1258987828U, // VRINTMS + 1258988148U, // VRINTND + 1258988541U, // VRINTNH + 1258987840U, // VRINTNNDf + 1258988541U, // VRINTNNDh + 1258987840U, // VRINTNNQf + 1258988541U, // VRINTNNQh + 1258987840U, // VRINTNS + 1258988160U, // VRINTPD + 1258988553U, // VRINTPH + 1258987852U, // VRINTPNDf + 1258988553U, // VRINTPNDh + 1258987852U, // VRINTPNQf + 1258988553U, // VRINTPNQh + 1258987852U, // VRINTPS + 252853388U, // VRINTRD + 252984460U, // VRINTRH + 253115532U, // VRINTRS + 252853960U, // VRINTXD + 252985032U, // VRINTXH + 1258987900U, // VRINTXNDf + 1258988611U, // VRINTXNDh + 1258987900U, // VRINTXNQf + 1258988611U, // VRINTXNQh + 253116104U, // VRINTXS + 252853972U, // VRINTZD + 252985044U, // VRINTZH + 1258987912U, // VRINTZNDf + 1258988634U, // VRINTZNDh + 1258987912U, // VRINTZNQf + 1258988634U, // VRINTZNQh + 253116116U, // VRINTZS + 186940195U, // VRSHLsv16i8 + 191265571U, // VRSHLsv1i64 + 186678051U, // VRSHLsv2i32 + 191265571U, // VRSHLsv2i64 + 186809123U, // VRSHLsv4i16 + 186678051U, // VRSHLsv4i32 + 186809123U, // VRSHLsv8i16 + 186940195U, // VRSHLsv8i8 + 187333411U, // VRSHLuv16i8 + 191396643U, // VRSHLuv1i64 + 187071267U, // VRSHLuv2i32 + 191396643U, // VRSHLuv2i64 + 187202339U, // VRSHLuv4i16 + 187071267U, // VRSHLuv4i32 + 187202339U, // VRSHLuv8i16 + 187333411U, // VRSHLuv8i8 + 187464658U, // VRSHRNv2i32 + 187595730U, // VRSHRNv4i16 + 187726802U, // VRSHRNv8i8 + 186940503U, // VRSHRsv16i8 + 191265879U, // VRSHRsv1i64 + 186678359U, // VRSHRsv2i32 + 191265879U, // VRSHRsv2i64 + 186809431U, // VRSHRsv4i16 + 186678359U, // VRSHRsv4i32 + 186809431U, // VRSHRsv8i16 + 186940503U, // VRSHRsv8i8 + 187333719U, // VRSHRuv16i8 + 191396951U, // VRSHRuv1i64 + 187071575U, // VRSHRuv2i32 + 191396951U, // VRSHRuv2i64 + 187202647U, // VRSHRuv4i16 + 187071575U, // VRSHRuv4i32 + 187202647U, // VRSHRuv8i16 + 187333719U, // VRSHRuv8i8 + 1260796414U, // VRSQRTEd + 253114878U, // VRSQRTEfd + 253114878U, // VRSQRTEfq + 252983806U, // VRSQRTEhd + 252983806U, // VRSQRTEhq + 1260796414U, // VRSQRTEq + 253132016U, // VRSQRTSfd + 253132016U, // VRSQRTSfq + 253000944U, // VRSQRTShd + 253000944U, // VRSQRTShq + 170154046U, // VRSRAsv16i8 + 174479422U, // VRSRAsv1i64 + 169891902U, // VRSRAsv2i32 + 174479422U, // VRSRAsv2i64 + 170022974U, // VRSRAsv4i16 + 169891902U, // VRSRAsv4i32 + 170022974U, // VRSRAsv8i16 + 170154046U, // VRSRAsv8i8 + 170547262U, // VRSRAuv16i8 + 174610494U, // VRSRAuv1i64 + 170285118U, // VRSRAuv2i32 + 174610494U, // VRSRAuv2i64 + 170416190U, // VRSRAuv4i16 + 170285118U, // VRSRAuv4i32 + 170416190U, // VRSRAuv8i16 + 170547262U, // VRSRAuv8i8 + 187464598U, // VRSUBHNv2i32 + 187595670U, // VRSUBHNv4i16 + 187726742U, // VRSUBHNv8i8 + 910473U, // VSDOTD + 7070857U, // VSDOTDI + 910473U, // VSDOTQ + 7070857U, // VSDOTQI + 185246348U, // VSELEQD + 185246741U, // VSELEQH + 185246040U, // VSELEQS + 185246276U, // VSELGED + 185246669U, // VSELGEH + 185245968U, // VSELGES + 185246372U, // VSELGTD + 185246775U, // VSELGTH + 185246064U, // VSELGTS + 185246360U, // VSELVSD + 185246763U, // VSELVSH + 185246052U, // VSELVSS + 3221380585U, // VSETLNi16 + 3221511657U, // VSETLNi32 + 3221642729U, // VSETLNi8 + 187726652U, // VSHLLi16 + 187595580U, // VSHLLi32 + 187857724U, // VSHLLi8 + 186678076U, // VSHLLsv2i64 + 186809148U, // VSHLLsv4i32 + 186940220U, // VSHLLsv8i16 + 187071292U, // VSHLLuv2i64 + 187202364U, // VSHLLuv4i32 + 187333436U, // VSHLLuv8i16 + 187857705U, // VSHLiv16i8 + 187464489U, // VSHLiv1i64 + 187595561U, // VSHLiv2i32 + 187464489U, // VSHLiv2i64 + 187726633U, // VSHLiv4i16 + 187595561U, // VSHLiv4i32 + 187726633U, // VSHLiv8i16 + 187857705U, // VSHLiv8i8 + 186940201U, // VSHLsv16i8 + 191265577U, // VSHLsv1i64 + 186678057U, // VSHLsv2i32 + 191265577U, // VSHLsv2i64 + 186809129U, // VSHLsv4i16 + 186678057U, // VSHLsv4i32 + 186809129U, // VSHLsv8i16 + 186940201U, // VSHLsv8i8 + 187333417U, // VSHLuv16i8 + 191396649U, // VSHLuv1i64 + 187071273U, // VSHLuv2i32 + 191396649U, // VSHLuv2i64 + 187202345U, // VSHLuv4i16 + 187071273U, // VSHLuv4i32 + 187202345U, // VSHLuv8i16 + 187333417U, // VSHLuv8i8 + 187464665U, // VSHRNv2i32 + 187595737U, // VSHRNv4i16 + 187726809U, // VSHRNv8i8 + 186940509U, // VSHRsv16i8 + 191265885U, // VSHRsv1i64 + 186678365U, // VSHRsv2i32 + 191265885U, // VSHRsv2i64 + 186809437U, // VSHRsv4i16 + 186678365U, // VSHRsv4i32 + 186809437U, // VSHRsv8i16 + 186940509U, // VSHRsv8i8 + 187333725U, // VSHRuv16i8 + 191396957U, // VSHRuv1i64 + 187071581U, // VSHRuv2i32 + 191396957U, // VSHRuv2i64 + 187202653U, // VSHRuv4i16 + 187071581U, // VSHRuv4i32 + 187202653U, // VSHRuv8i16 + 187333725U, // VSHRuv8i8 + 7110066U, // VSHTOD + 256540082U, // VSHTOH + 7241138U, // VSHTOS + 443563442U, // VSITOD + 443694514U, // VSITOH + 440942002U, // VSITOS + 416419U, // VSLIv16i8 + 5266083U, // VSLIv1i64 + 285347U, // VSLIv2i32 + 5266083U, // VSLIv2i64 + 154275U, // VSLIv4i16 + 285347U, // VSLIv4i32 + 154275U, // VSLIv8i16 + 416419U, // VSLIv8i8 + 1332772274U, // VSLTOD + 1332903346U, // VSLTOH + 1330150834U, // VSLTOS + 252853628U, // VSQRTD + 252984700U, // VSQRTH + 253115772U, // VSQRTS + 170154052U, // VSRAsv16i8 + 174479428U, // VSRAsv1i64 + 169891908U, // VSRAsv2i32 + 174479428U, // VSRAsv2i64 + 170022980U, // VSRAsv4i16 + 169891908U, // VSRAsv4i32 + 170022980U, // VSRAsv8i16 + 170154052U, // VSRAsv8i8 + 170547268U, // VSRAuv16i8 + 174610500U, // VSRAuv1i64 + 170285124U, // VSRAuv2i32 + 174610500U, // VSRAuv2i64 + 170416196U, // VSRAuv4i16 + 170285124U, // VSRAuv4i32 + 170416196U, // VSRAuv8i16 + 170547268U, // VSRAuv8i8 + 416424U, // VSRIv16i8 + 5266088U, // VSRIv1i64 + 285352U, // VSRIv2i32 + 5266088U, // VSRIv2i64 + 154280U, // VSRIv4i16 + 285352U, // VSRIv4i32 + 154280U, // VSRIv8i16 + 416424U, // VSRIv8i8 + 1247041145U, // VST1LNd16 + 1632949881U, // VST1LNd16_UPD + 1247172217U, // VST1LNd32 + 1633080953U, // VST1LNd32_UPD + 1247303289U, // VST1LNd8 + 1633212025U, // VST1LNd8_UPD + 0U, // VST1LNq16Pseudo + 0U, // VST1LNq16Pseudo_UPD + 0U, // VST1LNq32Pseudo + 0U, // VST1LNq32Pseudo_UPD + 0U, // VST1LNq8Pseudo + 0U, // VST1LNq8Pseudo_UPD + 570586745U, // VST1d16 + 587363961U, // VST1d16Q + 0U, // VST1d16QPseudo + 604132985U, // VST1d16Qwb_fixed + 620914297U, // VST1d16Qwb_register + 637695609U, // VST1d16T + 0U, // VST1d16TPseudo + 654464633U, // VST1d16Twb_fixed + 671245945U, // VST1d16Twb_register + 688019065U, // VST1d16wb_fixed + 704800377U, // VST1d16wb_register + 570717817U, // VST1d32 + 587495033U, // VST1d32Q + 0U, // VST1d32QPseudo + 604264057U, // VST1d32Qwb_fixed + 621045369U, // VST1d32Qwb_register + 637826681U, // VST1d32T + 0U, // VST1d32TPseudo + 654595705U, // VST1d32Twb_fixed + 671377017U, // VST1d32Twb_register + 688150137U, // VST1d32wb_fixed + 704931449U, // VST1d32wb_register + 575698553U, // VST1d64 + 592475769U, // VST1d64Q + 0U, // VST1d64QPseudo + 0U, // VST1d64QPseudoWB_fixed + 0U, // VST1d64QPseudoWB_register + 609244793U, // VST1d64Qwb_fixed + 626026105U, // VST1d64Qwb_register + 642807417U, // VST1d64T + 0U, // VST1d64TPseudo + 0U, // VST1d64TPseudoWB_fixed + 0U, // VST1d64TPseudoWB_register + 659576441U, // VST1d64Twb_fixed + 676357753U, // VST1d64Twb_register + 693130873U, // VST1d64wb_fixed + 709912185U, // VST1d64wb_register + 570848889U, // VST1d8 + 587626105U, // VST1d8Q + 0U, // VST1d8QPseudo + 604395129U, // VST1d8Qwb_fixed + 621176441U, // VST1d8Qwb_register + 637957753U, // VST1d8T + 0U, // VST1d8TPseudo + 654726777U, // VST1d8Twb_fixed + 671508089U, // VST1d8Twb_register + 688281209U, // VST1d8wb_fixed + 705062521U, // VST1d8wb_register + 721581689U, // VST1q16 + 0U, // VST1q16HighQPseudo + 0U, // VST1q16HighTPseudo + 0U, // VST1q16LowQPseudo_UPD + 0U, // VST1q16LowTPseudo_UPD + 738350713U, // VST1q16wb_fixed + 755132025U, // VST1q16wb_register + 721712761U, // VST1q32 + 0U, // VST1q32HighQPseudo + 0U, // VST1q32HighTPseudo + 0U, // VST1q32LowQPseudo_UPD + 0U, // VST1q32LowTPseudo_UPD + 738481785U, // VST1q32wb_fixed + 755263097U, // VST1q32wb_register + 726693497U, // VST1q64 + 0U, // VST1q64HighQPseudo + 0U, // VST1q64HighTPseudo + 0U, // VST1q64LowQPseudo_UPD + 0U, // VST1q64LowTPseudo_UPD + 743462521U, // VST1q64wb_fixed + 760243833U, // VST1q64wb_register + 721843833U, // VST1q8 + 0U, // VST1q8HighQPseudo + 0U, // VST1q8HighTPseudo + 0U, // VST1q8LowQPseudo_UPD + 0U, // VST1q8LowTPseudo_UPD + 738612857U, // VST1q8wb_fixed + 755394169U, // VST1q8wb_register + 1247045301U, // VST2LNd16 + 0U, // VST2LNd16Pseudo + 0U, // VST2LNd16Pseudo_UPD + 1632999093U, // VST2LNd16_UPD + 1247176373U, // VST2LNd32 + 0U, // VST2LNd32Pseudo + 0U, // VST2LNd32Pseudo_UPD + 1633130165U, // VST2LNd32_UPD + 1247307445U, // VST2LNd8 + 0U, // VST2LNd8Pseudo + 0U, // VST2LNd8Pseudo_UPD + 1633261237U, // VST2LNd8_UPD + 1247045301U, // VST2LNq16 + 0U, // VST2LNq16Pseudo + 0U, // VST2LNq16Pseudo_UPD + 1632999093U, // VST2LNq16_UPD + 1247176373U, // VST2LNq32 + 0U, // VST2LNq32Pseudo + 0U, // VST2LNq32Pseudo_UPD + 1633130165U, // VST2LNq32_UPD + 771913397U, // VST2b16 + 788682421U, // VST2b16wb_fixed + 805463733U, // VST2b16wb_register + 772044469U, // VST2b32 + 788813493U, // VST2b32wb_fixed + 805594805U, // VST2b32wb_register + 772175541U, // VST2b8 + 788944565U, // VST2b8wb_fixed + 805725877U, // VST2b8wb_register + 721581749U, // VST2d16 + 738350773U, // VST2d16wb_fixed + 755132085U, // VST2d16wb_register + 721712821U, // VST2d32 + 738481845U, // VST2d32wb_fixed + 755263157U, // VST2d32wb_register + 721843893U, // VST2d8 + 738612917U, // VST2d8wb_fixed + 755394229U, // VST2d8wb_register + 587364021U, // VST2q16 + 0U, // VST2q16Pseudo + 0U, // VST2q16PseudoWB_fixed + 0U, // VST2q16PseudoWB_register + 604133045U, // VST2q16wb_fixed + 620914357U, // VST2q16wb_register + 587495093U, // VST2q32 + 0U, // VST2q32Pseudo + 0U, // VST2q32PseudoWB_fixed + 0U, // VST2q32PseudoWB_register + 604264117U, // VST2q32wb_fixed + 621045429U, // VST2q32wb_register + 587626165U, // VST2q8 + 0U, // VST2q8Pseudo + 0U, // VST2q8PseudoWB_fixed + 0U, // VST2q8PseudoWB_register + 604395189U, // VST2q8wb_fixed + 621176501U, // VST2q8wb_register + 1247073989U, // VST3LNd16 + 0U, // VST3LNd16Pseudo + 0U, // VST3LNd16Pseudo_UPD + 1633011397U, // VST3LNd16_UPD + 1247205061U, // VST3LNd32 + 0U, // VST3LNd32Pseudo + 0U, // VST3LNd32Pseudo_UPD + 1633142469U, // VST3LNd32_UPD + 1247336133U, // VST3LNd8 + 0U, // VST3LNd8Pseudo + 0U, // VST3LNd8Pseudo_UPD + 1633273541U, // VST3LNd8_UPD + 1247073989U, // VST3LNq16 + 0U, // VST3LNq16Pseudo + 0U, // VST3LNq16Pseudo_UPD + 1633011397U, // VST3LNq16_UPD + 1247205061U, // VST3LNq32 + 0U, // VST3LNq32Pseudo + 0U, // VST3LNq32Pseudo_UPD + 1633142469U, // VST3LNq32_UPD + 173303493U, // VST3d16 + 0U, // VST3d16Pseudo + 0U, // VST3d16Pseudo_UPD + 559257285U, // VST3d16_UPD + 173434565U, // VST3d32 + 0U, // VST3d32Pseudo + 0U, // VST3d32Pseudo_UPD + 559388357U, // VST3d32_UPD + 173565637U, // VST3d8 + 0U, // VST3d8Pseudo + 0U, // VST3d8Pseudo_UPD + 559519429U, // VST3d8_UPD + 173303493U, // VST3q16 + 0U, // VST3q16Pseudo_UPD + 559257285U, // VST3q16_UPD + 0U, // VST3q16oddPseudo + 0U, // VST3q16oddPseudo_UPD + 173434565U, // VST3q32 + 0U, // VST3q32Pseudo_UPD + 559388357U, // VST3q32_UPD + 0U, // VST3q32oddPseudo + 0U, // VST3q32oddPseudo_UPD + 173565637U, // VST3q8 + 0U, // VST3q8Pseudo_UPD + 559519429U, // VST3q8_UPD + 0U, // VST3q8oddPseudo + 0U, // VST3q8oddPseudo_UPD + 1247123158U, // VST4LNd16 + 0U, // VST4LNd16Pseudo + 0U, // VST4LNd16Pseudo_UPD + 1633003222U, // VST4LNd16_UPD + 1247254230U, // VST4LNd32 + 0U, // VST4LNd32Pseudo + 0U, // VST4LNd32Pseudo_UPD + 1633134294U, // VST4LNd32_UPD + 1247385302U, // VST4LNd8 + 0U, // VST4LNd8Pseudo + 0U, // VST4LNd8Pseudo_UPD + 1633265366U, // VST4LNd8_UPD + 1247123158U, // VST4LNq16 + 0U, // VST4LNq16Pseudo + 0U, // VST4LNq16Pseudo_UPD + 1633003222U, // VST4LNq16_UPD + 1247254230U, // VST4LNq32 + 0U, // VST4LNq32Pseudo + 0U, // VST4LNq32Pseudo_UPD + 1633134294U, // VST4LNq32_UPD + 173332182U, // VST4d16 + 0U, // VST4d16Pseudo + 0U, // VST4d16Pseudo_UPD + 559269590U, // VST4d16_UPD + 173463254U, // VST4d32 + 0U, // VST4d32Pseudo + 0U, // VST4d32Pseudo_UPD + 559400662U, // VST4d32_UPD + 173594326U, // VST4d8 + 0U, // VST4d8Pseudo + 0U, // VST4d8Pseudo_UPD + 559531734U, // VST4d8_UPD + 173332182U, // VST4q16 + 0U, // VST4q16Pseudo_UPD + 559269590U, // VST4q16_UPD + 0U, // VST4q16oddPseudo + 0U, // VST4q16oddPseudo_UPD + 173463254U, // VST4q32 + 0U, // VST4q32Pseudo_UPD + 559400662U, // VST4q32_UPD + 0U, // VST4q32oddPseudo + 0U, // VST4q32oddPseudo_UPD + 173594326U, // VST4q8 + 0U, // VST4q8Pseudo_UPD + 559531734U, // VST4q8_UPD + 0U, // VST4q8oddPseudo + 0U, // VST4q8oddPseudo_UPD + 2332571781U, // VSTMDDB_UPD + 571413U, // VSTMDIA + 2332571669U, // VSTMDIA_UPD + 0U, // VSTMQIA + 2332571781U, // VSTMSDB_UPD + 571413U, // VSTMSIA + 2332571669U, // VSTMSIA_UPD + 556179U, // VSTRD + 162963U, // VSTRH + 556179U, // VSTRS + 252868870U, // VSUBD + 252999942U, // VSUBH + 187464606U, // VSUBHNv2i32 + 187595678U, // VSUBHNv4i16 + 187726750U, // VSUBHNv8i8 + 186677999U, // VSUBLsv2i64 + 186809071U, // VSUBLsv4i32 + 186940143U, // VSUBLsv8i16 + 187071215U, // VSUBLuv2i64 + 187202287U, // VSUBLuv4i32 + 187333359U, // VSUBLuv8i16 + 253131014U, // VSUBS + 186678766U, // VSUBWsv2i64 + 186809838U, // VSUBWsv4i32 + 186940910U, // VSUBWsv8i16 + 187071982U, // VSUBWuv2i64 + 187203054U, // VSUBWuv4i32 + 187334126U, // VSUBWuv8i16 + 253131014U, // VSUBfd + 253131014U, // VSUBfq + 252999942U, // VSUBhd + 252999942U, // VSUBhq + 187857158U, // VSUBv16i8 + 187463942U, // VSUBv1i64 + 187595014U, // VSUBv2i32 + 187463942U, // VSUBv2i64 + 187726086U, // VSUBv4i16 + 187595014U, // VSUBv4i32 + 187726086U, // VSUBv8i16 + 187857158U, // VSUBv8i8 + 547888U, // VSWPd + 547888U, // VSWPq + 424682U, // VTBL1 + 424682U, // VTBL2 + 424682U, // VTBL3 + 0U, // VTBL3Pseudo + 424682U, // VTBL4 + 0U, // VTBL4Pseudo + 417355U, // VTBX1 + 417355U, // VTBX2 + 417355U, // VTBX3 + 0U, // VTBX3Pseudo + 417355U, // VTBX4 + 0U, // VTBX4Pseudo + 7634354U, // VTOSHD + 256146866U, // VTOSHH + 7765426U, // VTOSHS + 441597080U, // VTOSIRD + 444087448U, // VTOSIRH + 440417432U, // VTOSIRS + 441597362U, // VTOSIZD + 444087730U, // VTOSIZH + 440417714U, // VTOSIZS + 1330806194U, // VTOSLD + 1333296562U, // VTOSLH + 1329626546U, // VTOSLS + 8027570U, // VTOUHD + 256277938U, // VTOUHH + 8158642U, // VTOUHS + 444480664U, // VTOUIRD + 444611736U, // VTOUIRH + 440548504U, // VTOUIRS + 444480946U, // VTOUIZD + 444612018U, // VTOUIZH + 440548786U, // VTOUIZS + 1333689778U, // VTOULD + 1333820850U, // VTOULH + 1329757618U, // VTOULS + 154596U, // VTRNd16 + 285668U, // VTRNd32 + 416740U, // VTRNd8 + 154596U, // VTRNq16 + 285668U, // VTRNq32 + 416740U, // VTRNq8 + 425351U, // VTSTv16i8 + 294279U, // VTSTv2i32 + 163207U, // VTSTv4i16 + 294279U, // VTSTv4i32 + 163207U, // VTSTv8i16 + 425351U, // VTSTv8i8 + 910483U, // VUDOTD + 7070867U, // VUDOTDI + 910483U, // VUDOTQ + 7070867U, // VUDOTQI + 8551858U, // VUHTOD + 256802226U, // VUHTOH + 8682930U, // VUHTOS + 445005234U, // VUITOD + 445136306U, // VUITOH + 441204146U, // VUITOS + 1334214066U, // VULTOD + 1334345138U, // VULTOH + 1330412978U, // VULTOS + 154677U, // VUZPd16 + 416821U, // VUZPd8 + 154677U, // VUZPq16 + 285749U, // VUZPq32 + 416821U, // VUZPq8 + 154653U, // VZIPd16 + 416797U, // VZIPd8 + 154653U, // VZIPq16 + 285725U, // VZIPq32 + 416797U, // VZIPq8 + 571388U, // sysLDMDA + 2332571644U, // sysLDMDA_UPD + 571519U, // sysLDMDB + 2332571775U, // sysLDMDB_UPD + 572300U, // sysLDMIA + 2332572556U, // sysLDMIA_UPD + 571538U, // sysLDMIB + 2332571794U, // sysLDMIB_UPD + 571394U, // sysSTMDA + 2332571650U, // sysSTMDA_UPD + 571526U, // sysSTMDB + 2332571782U, // sysSTMDB_UPD + 572306U, // sysSTMIA + 2332572562U, // sysSTMIA_UPD + 571544U, // sysSTMIB + 2332571800U, // sysSTMIB_UPD + 530745U, // t2ADCri + 9050425U, // t2ADCrr + 9079097U, // t2ADCrs + 9050486U, // t2ADDri + 556533U, // t2ADDri12 + 9050486U, // t2ADDrr + 9079158U, // t2ADDrs + 9059406U, // t2ADR + 530859U, // t2ANDri + 9050539U, // t2ANDrr + 9079211U, // t2ANDrs + 9051260U, // t2ASRri + 9051260U, // t2ASRrr + 1082832976U, // t2B + 555329U, // t2BFC + 547483U, // t2BFI + 530758U, // t2BICri + 9050438U, // t2BICrr + 9079110U, // t2BICrs + 1074313901U, // t2BXJ + 1082832976U, // t2Bcc + 201907225U, // t2CDP + 201905823U, // t2CDP2 + 839310U, // t2CLREX + 540368U, // t2CLZ + 9059263U, // t2CMNri + 9059263U, // t2CMNzrr + 9075647U, // t2CMNzrs + 9059363U, // t2CMPri + 9059363U, // t2CMPrr + 9075747U, // t2CMPrs + 828709U, // t2CPS1p + 1317731549U, // t2CPS2p + 235470045U, // t2CPS3p + 185246891U, // t2CRC32B + 185246899U, // t2CRC32CB + 185246973U, // t2CRC32CH + 185247057U, // t2CRC32CW + 185246965U, // t2CRC32H + 185247049U, // t2CRC32W + 1074313739U, // t2DBG + 837235U, // t2DCPS1 + 837295U, // t2DCPS2 + 837311U, // t2DCPS3 + 822655139U, // t2DMB + 822655158U, // t2DSB + 531562U, // t2EORri + 9051242U, // t2EORrr + 9079914U, // t2EORrs + 1082834290U, // t2HINT + 828731U, // t2HVC + 839432378U, // t2ISB + 17313120U, // t2IT + 0U, // t2Int_eh_sjlj_setjmp + 0U, // t2Int_eh_sjlj_setjmp_nofp + 538616U, // t2LDA + 538701U, // t2LDAB + 540284U, // t2LDAEX + 538905U, // t2LDAEXB + 555461U, // t2LDAEXD + 539263U, // t2LDAEXH + 539165U, // t2LDAH + 1275615921U, // t2LDC2L_OFFSET + 1275615921U, // t2LDC2L_OPTION + 1275615921U, // t2LDC2L_POST + 1275615921U, // t2LDC2L_PRE + 1275614853U, // t2LDC2_OFFSET + 1275614853U, // t2LDC2_OPTION + 1275614853U, // t2LDC2_POST + 1275614853U, // t2LDC2_PRE + 1275615989U, // t2LDCL_OFFSET + 1275615989U, // t2LDCL_OPTION + 1275615989U, // t2LDCL_POST + 1275615989U, // t2LDCL_PRE + 1275615549U, // t2LDC_OFFSET + 1275615549U, // t2LDC_OPTION + 1275615549U, // t2LDC_POST + 1275615549U, // t2LDC_PRE + 571519U, // t2LDMDB + 2332571775U, // t2LDMDB_UPD + 9091980U, // t2LDMIA + 2341092236U, // t2LDMIA_UPD + 556328U, // t2LDRBT + 546988U, // t2LDRB_POST + 546988U, // t2LDRB_PRE + 9074860U, // t2LDRBi12 + 555180U, // t2LDRBi8 + 9058476U, // t2LDRBpci + 9066668U, // t2LDRBs + 551343U, // t2LDRD_POST + 551343U, // t2LDRD_PRE + 547247U, // t2LDRDi8 + 556680U, // t2LDREX + 538919U, // t2LDREXB + 555475U, // t2LDREXD + 539277U, // t2LDREXH + 556363U, // t2LDRHT + 547409U, // t2LDRH_POST + 547409U, // t2LDRH_PRE + 9075281U, // t2LDRHi12 + 555601U, // t2LDRHi8 + 9058897U, // t2LDRHpci + 9067089U, // t2LDRHs + 556340U, // t2LDRSBT + 547006U, // t2LDRSB_POST + 547006U, // t2LDRSB_PRE + 9074878U, // t2LDRSBi12 + 555198U, // t2LDRSBi8 + 9058494U, // t2LDRSBpci + 9066686U, // t2LDRSBs + 556375U, // t2LDRSHT + 547428U, // t2LDRSH_POST + 547428U, // t2LDRSH_PRE + 9075300U, // t2LDRSHi12 + 555620U, // t2LDRSHi8 + 9058916U, // t2LDRSHpci + 9067108U, // t2LDRSHs + 556407U, // t2LDRT + 547923U, // t2LDR_POST + 547923U, // t2LDR_PRE + 9075795U, // t2LDRi12 + 556115U, // t2LDRi8 + 9059411U, // t2LDRpci + 9067603U, // t2LDRs + 9050981U, // t2LSLri + 9050981U, // t2LSLrr + 9051267U, // t2LSRri + 9051267U, // t2LSRrr + 201907274U, // t2MCR + 201905828U, // t2MCR2 + 201878642U, // t2MCRR + 201877161U, // t2MCRR2 + 546852U, // t2MLA + 548021U, // t2MLS + 556471U, // t2MOVTi16 + 9063914U, // t2MOVi + 540159U, // t2MOVi16 + 9063914U, // t2MOVr + 9059558U, // t2MOVsra_flag + 9059563U, // t2MOVsrl_flag + 336124238U, // t2MRC + 336123530U, // t2MRC2 + 352872786U, // t2MRRC + 352872079U, // t2MRRC2 + 2148056290U, // t2MRS_AR + 539874U, // t2MRS_M + 539874U, // t2MRSbanked + 3221798114U, // t2MRSsys_AR + 369638536U, // t2MSR_AR + 369638536U, // t2MSR_M + 386415752U, // t2MSRbanked + 555893U, // t2MUL + 543747U, // t2MVNi + 9063427U, // t2MVNr + 9051139U, // t2MVNs + 531424U, // t2ORNri + 531424U, // t2ORNrr + 560096U, // t2ORNrs + 531576U, // t2ORRri + 9051256U, // t2ORRrr + 9079928U, // t2ORRrs + 548115U, // t2PKHBT + 547023U, // t2PKHTB + 856178170U, // t2PLDWi12 + 872955386U, // t2PLDWi8 + 889748986U, // t2PLDWs + 856177055U, // t2PLDi12 + 872954271U, // t2PLDi8 + 906541471U, // t2PLDpci + 889747871U, // t2PLDs + 856177311U, // t2PLIi12 + 872954527U, // t2PLIi8 + 906541727U, // t2PLIpci + 889748127U, // t2PLIs + 555406U, // t2QADD + 554800U, // t2QADD16 + 554903U, // t2QADD8 + 556729U, // t2QASX + 555380U, // t2QDADD + 555252U, // t2QDSUB + 556588U, // t2QSAX + 555265U, // t2QSUB + 554762U, // t2QSUB16 + 554864U, // t2QSUB8 + 539998U, // t2RBIT + 9059798U, // t2REV + 9058132U, // t2REV16 + 9058927U, // t2REVSH + 1074313336U, // t2RFEDB + 2148055160U, // t2RFEDBW + 1074313224U, // t2RFEIA + 2148055048U, // t2RFEIAW + 9051246U, // t2RORri + 9051246U, // t2RORrr + 544424U, // t2RRX + 9050304U, // t2RSBri + 530624U, // t2RSBrr + 559296U, // t2RSBrs + 554807U, // t2SADD16 + 554909U, // t2SADD8 + 556734U, // t2SASX + 530741U, // t2SBCri + 9050421U, // t2SBCrr + 9079093U, // t2SBCrs + 548506U, // t2SBFX + 556506U, // t2SDIV + 555794U, // t2SEL + 828701U, // t2SETPAN + 838170U, // t2SG + 554783U, // t2SHADD16 + 554888U, // t2SHADD8 + 556716U, // t2SHASX + 556575U, // t2SHSAX + 554745U, // t2SHSUB16 + 554849U, // t2SHSUB8 + 1074313546U, // t2SMC + 546910U, // t2SMLABB + 548108U, // t2SMLABT + 547171U, // t2SMLAD + 548432U, // t2SMLADX + 580312U, // t2SMLAL + 579685U, // t2SMLALBB + 580889U, // t2SMLALBT + 579992U, // t2SMLALD + 581214U, // t2SMLALDX + 579797U, // t2SMLALTB + 581011U, // t2SMLALTT + 547016U, // t2SMLATB + 548236U, // t2SMLATT + 547083U, // t2SMLAWB + 548284U, // t2SMLAWT + 547257U, // t2SMLSD + 548462U, // t2SMLSDX + 580003U, // t2SMLSLD + 581222U, // t2SMLSLDX + 546850U, // t2SMMLA + 547907U, // t2SMMLAR + 548019U, // t2SMMLS + 547968U, // t2SMMLSR + 555891U, // t2SMMUL + 556130U, // t2SMMULR + 555369U, // t2SMUAD + 556631U, // t2SMUADX + 555117U, // t2SMULBB + 556321U, // t2SMULBT + 547658U, // t2SMULL + 555229U, // t2SMULTB + 556443U, // t2SMULTT + 555282U, // t2SMULWB + 556483U, // t2SMULWT + 555455U, // t2SMUSD + 556661U, // t2SMUSDX + 9222284U, // t2SRSDB + 9353356U, // t2SRSDB_UPD + 9222172U, // t2SRSIA + 9353244U, // t2SRSIA_UPD + 548093U, // t2SSAT + 554821U, // t2SSAT16 + 556593U, // t2SSAX + 554769U, // t2SSUB16 + 554870U, // t2SSUB8 + 1275615927U, // t2STC2L_OFFSET + 1275615927U, // t2STC2L_OPTION + 1275615927U, // t2STC2L_POST + 1275615927U, // t2STC2L_PRE + 1275614869U, // t2STC2_OFFSET + 1275614869U, // t2STC2_OPTION + 1275614869U, // t2STC2_POST + 1275614869U, // t2STC2_PRE + 1275615994U, // t2STCL_OFFSET + 1275615994U, // t2STCL_OPTION + 1275615994U, // t2STCL_POST + 1275615994U, // t2STCL_PRE + 1275615579U, // t2STC_OFFSET + 1275615579U, // t2STC_OPTION + 1275615579U, // t2STC_POST + 1275615579U, // t2STC_PRE + 539503U, // t2STL + 538782U, // t2STLB + 556674U, // t2STLEX + 555296U, // t2STLEXB + 547276U, // t2STLEXD + 555654U, // t2STLEXH + 539195U, // t2STLH + 571526U, // t2STMDB + 2332571782U, // t2STMDB_UPD + 9091986U, // t2STMIA + 2341092242U, // t2STMIA_UPD + 556334U, // t2STRBT + 185096369U, // t2STRB_POST + 185096369U, // t2STRB_PRE + 9074865U, // t2STRBi12 + 555185U, // t2STRBi8 + 9066673U, // t2STRBs + 185100724U, // t2STRD_POST + 185100724U, // t2STRD_PRE + 547252U, // t2STRDi8 + 548500U, // t2STREX + 555310U, // t2STREXB + 547290U, // t2STREXD + 555668U, // t2STREXH + 556369U, // t2STRHT + 185096790U, // t2STRH_POST + 185096790U, // t2STRH_PRE + 9075286U, // t2STRHi12 + 555606U, // t2STRHi8 + 9067094U, // t2STRHs + 556418U, // t2STRT + 185097364U, // t2STR_POST + 185097364U, // t2STR_PRE + 9075860U, // t2STRi12 + 556180U, // t2STRi8 + 9067668U, // t2STRs + 9485481U, // t2SUBS_PC_LR + 9050358U, // t2SUBri + 556527U, // t2SUBri12 + 9050358U, // t2SUBrr + 9079030U, // t2SUBrs + 546898U, // t2SXTAB + 546523U, // t2SXTAB16 + 547371U, // t2SXTAH + 9074922U, // t2SXTB + 554731U, // t2SXTB16 + 9075317U, // t2SXTH + 923285620U, // t2TBB + 940063287U, // t2TBH + 9059391U, // t2TEQri + 9059391U, // t2TEQrr + 9075775U, // t2TEQrs + 956872900U, // t2TSB + 9059720U, // t2TSTri + 9059720U, // t2TSTrr + 9076104U, // t2TSTrs + 540048U, // t2TT + 538697U, // t2TTA + 539911U, // t2TTAT + 540066U, // t2TTT + 554814U, // t2UADD16 + 554915U, // t2UADD8 + 556739U, // t2UASX + 548511U, // t2UBFX + 828738U, // t2UDF + 556511U, // t2UDIV + 554791U, // t2UHADD16 + 554895U, // t2UHADD8 + 556722U, // t2UHASX + 556581U, // t2UHSAX + 554753U, // t2UHSUB16 + 554856U, // t2UHSUB8 + 580285U, // t2UMAAL + 580318U, // t2UMLAL + 547664U, // t2UMULL + 554799U, // t2UQADD16 + 554902U, // t2UQADD8 + 556728U, // t2UQASX + 556587U, // t2UQSAX + 554761U, // t2UQSUB16 + 554863U, // t2UQSUB8 + 554882U, // t2USAD8 + 546650U, // t2USADA8 + 548098U, // t2USAT + 554828U, // t2USAT16 + 556598U, // t2USAX + 554776U, // t2USUB16 + 554876U, // t2USUB8 + 546904U, // t2UXTAB + 546531U, // t2UXTAB16 + 547377U, // t2UXTAH + 9074927U, // t2UXTB + 554738U, // t2UXTB16 + 9075322U, // t2UXTH + 982776121U, // tADC + 555382U, // tADDhirr + 177469814U, // tADDi3 + 982776182U, // tADDi8 + 555382U, // tADDrSP + 555382U, // tADDrSPi + 177469814U, // tADDrr + 555382U, // tADDspi + 555382U, // tADDspr + 539726U, // tADR + 982776235U, // tAND + 177470588U, // tASRri + 982776956U, // tASRrr + 1074313296U, // tB + 982776134U, // tBIC + 828725U, // tBKPT + 1242090220U, // tBL + 1242090708U, // tBLXNSr + 1242091172U, // tBLXi + 1242091172U, // tBLXr + 1074314816U, // tBX + 1074314447U, // tBXNS + 1074313296U, // tBcc + 1258988910U, // tCBNZ + 1258988905U, // tCBZ + 539583U, // tCMNz + 539683U, // tCMPhir + 539683U, // tCMPi8 + 539683U, // tCMPr + 1308687581U, // tCPS + 982776938U, // tEOR + 1074314610U, // tHINT + 828720U, // tHLT + 0U, // tInt_WIN_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_setjmp + 572300U, // tLDMIA + 555180U, // tLDRBi + 555180U, // tLDRBr + 555601U, // tLDRHi + 555601U, // tLDRHr + 555198U, // tLDRSB + 555620U, // tLDRSH + 556115U, // tLDRi + 539731U, // tLDRpci + 556115U, // tLDRr + 556115U, // tLDRspi + 177470309U, // tLSLri + 982776677U, // tLSLrr + 177470595U, // tLSRri + 982776963U, // tLSRrr + 1258988842U, // tMOVSr + 446037482U, // tMOVi8 + 540138U, // tMOVr + 177470325U, // tMUL + 446036995U, // tMVN + 982776952U, // tORR + 0U, // tPICADD + 990432295U, // tPOP + 990431850U, // tPUSH + 540118U, // tREV + 538452U, // tREV16 + 539247U, // tREVSH + 982776942U, // tROR + 429258944U, // tRSB + 982776117U, // tSBC + 91368U, // tSETEND + 2332572562U, // tSTMIA_UPD + 555185U, // tSTRBi + 555185U, // tSTRBr + 555606U, // tSTRHi + 555606U, // tSTRHr + 556180U, // tSTRi + 556180U, // tSTRr + 556180U, // tSTRspi + 177469686U, // tSUBi3 + 982776054U, // tSUBi8 + 177469686U, // tSUBrr + 555254U, // tSUBspi + 1074313567U, // tSVC + 538858U, // tSXTB + 539253U, // tSXTH + 3092U, // tTRAP + 540040U, // tTST + 828656U, // tUDF + 538863U, // tUXTB + 539258U, // tUXTH + 1636U, // t__brkdiv0 + }; + + static const uint32_t OpInfo1[] = { + 0U, // PHI + 0U, // INLINEASM + 0U, // CFI_INSTRUCTION + 0U, // EH_LABEL + 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL + 0U, // KILL + 0U, // EXTRACT_SUBREG + 0U, // INSERT_SUBREG + 0U, // IMPLICIT_DEF + 0U, // SUBREG_TO_REG + 0U, // COPY_TO_REGCLASS + 0U, // DBG_VALUE + 0U, // DBG_LABEL + 0U, // REG_SEQUENCE + 0U, // COPY + 0U, // BUNDLE + 0U, // LIFETIME_START + 0U, // LIFETIME_END + 0U, // STACKMAP + 0U, // FENTRY_CALL + 0U, // PATCHPOINT + 0U, // LOAD_STACK_GUARD + 0U, // STATEPOINT + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // ABS + 0U, // ADDSri + 0U, // ADDSrr + 0U, // ADDSrsi + 0U, // ADDSrsr + 0U, // ADJCALLSTACKDOWN + 0U, // ADJCALLSTACKUP + 0U, // ASRi + 0U, // ASRr + 0U, // B + 0U, // BCCZi64 + 0U, // BCCi64 + 0U, // BMOVPCB_CALL + 0U, // BMOVPCRX_CALL + 0U, // BR_JTadd + 0U, // BR_JTm_i12 + 0U, // BR_JTm_rs + 0U, // BR_JTr + 0U, // BX_CALL + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 0U, // CONSTPOOL_ENTRY + 0U, // COPY_STRUCT_BYVAL_I32 + 0U, // CompilerBarrier + 0U, // ITasm + 0U, // Int_eh_sjlj_dispatchsetup + 0U, // Int_eh_sjlj_longjmp + 0U, // Int_eh_sjlj_setjmp + 0U, // Int_eh_sjlj_setjmp_nofp + 0U, // Int_eh_sjlj_setup_dispatch + 0U, // JUMPTABLE_ADDRS + 0U, // JUMPTABLE_INSTS + 0U, // JUMPTABLE_TBB + 0U, // JUMPTABLE_TBH + 0U, // LDMIA_RET + 8U, // LDRBT_POST + 1024U, // LDRConstPool + 0U, // LDRLIT_ga_abs + 0U, // LDRLIT_ga_pcrel + 0U, // LDRLIT_ga_pcrel_ldr + 8U, // LDRT_POST + 0U, // LEApcrel + 0U, // LEApcrelJT + 0U, // LSLi + 0U, // LSLr + 0U, // LSRi + 0U, // LSRr + 0U, // MEMCPY + 0U, // MLAv5 + 0U, // MOVCCi + 0U, // MOVCCi16 + 0U, // MOVCCi32imm + 0U, // MOVCCr + 0U, // MOVCCsi + 0U, // MOVCCsr + 0U, // MOVPCRX + 0U, // MOVTi16_ga_pcrel + 0U, // MOV_ga_pcrel + 0U, // MOV_ga_pcrel_ldr + 0U, // MOVi16_ga_pcrel + 0U, // MOVi32imm + 0U, // MOVsra_flag + 0U, // MOVsrl_flag + 0U, // MULv5 + 0U, // MVNCCi + 0U, // PICADD + 0U, // PICLDR + 0U, // PICLDRB + 0U, // PICLDRH + 0U, // PICLDRSB + 0U, // PICLDRSH + 0U, // PICSTR + 0U, // PICSTRB + 0U, // PICSTRH + 0U, // RORi + 0U, // RORr + 0U, // RRX + 1024U, // RRXi + 0U, // RSBSri + 0U, // RSBSrsi + 0U, // RSBSrsr + 0U, // SMLALv5 + 0U, // SMULLv5 + 0U, // SPACE + 8U, // STRBT_POST + 0U, // STRBi_preidx + 0U, // STRBr_preidx + 0U, // STRH_preidx + 8U, // STRT_POST + 0U, // STRi_preidx + 0U, // STRr_preidx + 0U, // SUBS_PC_LR + 0U, // SUBSri + 0U, // SUBSrr + 0U, // SUBSrsi + 0U, // SUBSrsr + 0U, // TAILJMPd + 0U, // TAILJMPr + 0U, // TAILJMPr4 + 0U, // TCRETURNdi + 0U, // TCRETURNri + 0U, // TPsoft + 0U, // UMLALv5 + 0U, // UMULLv5 + 1040U, // VLD1LNdAsm_16 + 1040U, // VLD1LNdAsm_32 + 1040U, // VLD1LNdAsm_8 + 2064U, // VLD1LNdWB_fixed_Asm_16 + 2064U, // VLD1LNdWB_fixed_Asm_32 + 2064U, // VLD1LNdWB_fixed_Asm_8 + 32784U, // VLD1LNdWB_register_Asm_16 + 32784U, // VLD1LNdWB_register_Asm_32 + 32784U, // VLD1LNdWB_register_Asm_8 + 1040U, // VLD2LNdAsm_16 + 1040U, // VLD2LNdAsm_32 + 1040U, // VLD2LNdAsm_8 + 2064U, // VLD2LNdWB_fixed_Asm_16 + 2064U, // VLD2LNdWB_fixed_Asm_32 + 2064U, // VLD2LNdWB_fixed_Asm_8 + 32784U, // VLD2LNdWB_register_Asm_16 + 32784U, // VLD2LNdWB_register_Asm_32 + 32784U, // VLD2LNdWB_register_Asm_8 + 1040U, // VLD2LNqAsm_16 + 1040U, // VLD2LNqAsm_32 + 2064U, // VLD2LNqWB_fixed_Asm_16 + 2064U, // VLD2LNqWB_fixed_Asm_32 + 32784U, // VLD2LNqWB_register_Asm_16 + 32784U, // VLD2LNqWB_register_Asm_32 + 0U, // VLD3DUPdAsm_16 + 0U, // VLD3DUPdAsm_32 + 0U, // VLD3DUPdAsm_8 + 0U, // VLD3DUPdWB_fixed_Asm_16 + 0U, // VLD3DUPdWB_fixed_Asm_32 + 0U, // VLD3DUPdWB_fixed_Asm_8 + 1048U, // VLD3DUPdWB_register_Asm_16 + 1048U, // VLD3DUPdWB_register_Asm_32 + 1048U, // VLD3DUPdWB_register_Asm_8 + 0U, // VLD3DUPqAsm_16 + 0U, // VLD3DUPqAsm_32 + 0U, // VLD3DUPqAsm_8 + 0U, // VLD3DUPqWB_fixed_Asm_16 + 0U, // VLD3DUPqWB_fixed_Asm_32 + 0U, // VLD3DUPqWB_fixed_Asm_8 + 1048U, // VLD3DUPqWB_register_Asm_16 + 1048U, // VLD3DUPqWB_register_Asm_32 + 1048U, // VLD3DUPqWB_register_Asm_8 + 1040U, // VLD3LNdAsm_16 + 1040U, // VLD3LNdAsm_32 + 1040U, // VLD3LNdAsm_8 + 2064U, // VLD3LNdWB_fixed_Asm_16 + 2064U, // VLD3LNdWB_fixed_Asm_32 + 2064U, // VLD3LNdWB_fixed_Asm_8 + 32784U, // VLD3LNdWB_register_Asm_16 + 32784U, // VLD3LNdWB_register_Asm_32 + 32784U, // VLD3LNdWB_register_Asm_8 + 1040U, // VLD3LNqAsm_16 + 1040U, // VLD3LNqAsm_32 + 2064U, // VLD3LNqWB_fixed_Asm_16 + 2064U, // VLD3LNqWB_fixed_Asm_32 + 32784U, // VLD3LNqWB_register_Asm_16 + 32784U, // VLD3LNqWB_register_Asm_32 + 32U, // VLD3dAsm_16 + 32U, // VLD3dAsm_32 + 32U, // VLD3dAsm_8 + 40U, // VLD3dWB_fixed_Asm_16 + 40U, // VLD3dWB_fixed_Asm_32 + 40U, // VLD3dWB_fixed_Asm_8 + 68656U, // VLD3dWB_register_Asm_16 + 68656U, // VLD3dWB_register_Asm_32 + 68656U, // VLD3dWB_register_Asm_8 + 0U, // VLD3qAsm_16 + 0U, // VLD3qAsm_32 + 0U, // VLD3qAsm_8 + 0U, // VLD3qWB_fixed_Asm_16 + 0U, // VLD3qWB_fixed_Asm_32 + 0U, // VLD3qWB_fixed_Asm_8 + 1048U, // VLD3qWB_register_Asm_16 + 1048U, // VLD3qWB_register_Asm_32 + 1048U, // VLD3qWB_register_Asm_8 + 0U, // VLD4DUPdAsm_16 + 0U, // VLD4DUPdAsm_32 + 0U, // VLD4DUPdAsm_8 + 0U, // VLD4DUPdWB_fixed_Asm_16 + 0U, // VLD4DUPdWB_fixed_Asm_32 + 0U, // VLD4DUPdWB_fixed_Asm_8 + 1048U, // VLD4DUPdWB_register_Asm_16 + 1048U, // VLD4DUPdWB_register_Asm_32 + 1048U, // VLD4DUPdWB_register_Asm_8 + 0U, // VLD4DUPqAsm_16 + 0U, // VLD4DUPqAsm_32 + 0U, // VLD4DUPqAsm_8 + 0U, // VLD4DUPqWB_fixed_Asm_16 + 0U, // VLD4DUPqWB_fixed_Asm_32 + 0U, // VLD4DUPqWB_fixed_Asm_8 + 1048U, // VLD4DUPqWB_register_Asm_16 + 1048U, // VLD4DUPqWB_register_Asm_32 + 1048U, // VLD4DUPqWB_register_Asm_8 + 1040U, // VLD4LNdAsm_16 + 1040U, // VLD4LNdAsm_32 + 1040U, // VLD4LNdAsm_8 + 2064U, // VLD4LNdWB_fixed_Asm_16 + 2064U, // VLD4LNdWB_fixed_Asm_32 + 2064U, // VLD4LNdWB_fixed_Asm_8 + 32784U, // VLD4LNdWB_register_Asm_16 + 32784U, // VLD4LNdWB_register_Asm_32 + 32784U, // VLD4LNdWB_register_Asm_8 + 1040U, // VLD4LNqAsm_16 + 1040U, // VLD4LNqAsm_32 + 2064U, // VLD4LNqWB_fixed_Asm_16 + 2064U, // VLD4LNqWB_fixed_Asm_32 + 32784U, // VLD4LNqWB_register_Asm_16 + 32784U, // VLD4LNqWB_register_Asm_32 + 32U, // VLD4dAsm_16 + 32U, // VLD4dAsm_32 + 32U, // VLD4dAsm_8 + 40U, // VLD4dWB_fixed_Asm_16 + 40U, // VLD4dWB_fixed_Asm_32 + 40U, // VLD4dWB_fixed_Asm_8 + 68656U, // VLD4dWB_register_Asm_16 + 68656U, // VLD4dWB_register_Asm_32 + 68656U, // VLD4dWB_register_Asm_8 + 0U, // VLD4qAsm_16 + 0U, // VLD4qAsm_32 + 0U, // VLD4qAsm_8 + 0U, // VLD4qWB_fixed_Asm_16 + 0U, // VLD4qWB_fixed_Asm_32 + 0U, // VLD4qWB_fixed_Asm_8 + 1048U, // VLD4qWB_register_Asm_16 + 1048U, // VLD4qWB_register_Asm_32 + 1048U, // VLD4qWB_register_Asm_8 + 0U, // VMOVD0 + 0U, // VMOVDcc + 0U, // VMOVQ0 + 0U, // VMOVScc + 1040U, // VST1LNdAsm_16 + 1040U, // VST1LNdAsm_32 + 1040U, // VST1LNdAsm_8 + 2064U, // VST1LNdWB_fixed_Asm_16 + 2064U, // VST1LNdWB_fixed_Asm_32 + 2064U, // VST1LNdWB_fixed_Asm_8 + 32784U, // VST1LNdWB_register_Asm_16 + 32784U, // VST1LNdWB_register_Asm_32 + 32784U, // VST1LNdWB_register_Asm_8 + 1040U, // VST2LNdAsm_16 + 1040U, // VST2LNdAsm_32 + 1040U, // VST2LNdAsm_8 + 2064U, // VST2LNdWB_fixed_Asm_16 + 2064U, // VST2LNdWB_fixed_Asm_32 + 2064U, // VST2LNdWB_fixed_Asm_8 + 32784U, // VST2LNdWB_register_Asm_16 + 32784U, // VST2LNdWB_register_Asm_32 + 32784U, // VST2LNdWB_register_Asm_8 + 1040U, // VST2LNqAsm_16 + 1040U, // VST2LNqAsm_32 + 2064U, // VST2LNqWB_fixed_Asm_16 + 2064U, // VST2LNqWB_fixed_Asm_32 + 32784U, // VST2LNqWB_register_Asm_16 + 32784U, // VST2LNqWB_register_Asm_32 + 1040U, // VST3LNdAsm_16 + 1040U, // VST3LNdAsm_32 + 1040U, // VST3LNdAsm_8 + 2064U, // VST3LNdWB_fixed_Asm_16 + 2064U, // VST3LNdWB_fixed_Asm_32 + 2064U, // VST3LNdWB_fixed_Asm_8 + 32784U, // VST3LNdWB_register_Asm_16 + 32784U, // VST3LNdWB_register_Asm_32 + 32784U, // VST3LNdWB_register_Asm_8 + 1040U, // VST3LNqAsm_16 + 1040U, // VST3LNqAsm_32 + 2064U, // VST3LNqWB_fixed_Asm_16 + 2064U, // VST3LNqWB_fixed_Asm_32 + 32784U, // VST3LNqWB_register_Asm_16 + 32784U, // VST3LNqWB_register_Asm_32 + 32U, // VST3dAsm_16 + 32U, // VST3dAsm_32 + 32U, // VST3dAsm_8 + 40U, // VST3dWB_fixed_Asm_16 + 40U, // VST3dWB_fixed_Asm_32 + 40U, // VST3dWB_fixed_Asm_8 + 68656U, // VST3dWB_register_Asm_16 + 68656U, // VST3dWB_register_Asm_32 + 68656U, // VST3dWB_register_Asm_8 + 0U, // VST3qAsm_16 + 0U, // VST3qAsm_32 + 0U, // VST3qAsm_8 + 0U, // VST3qWB_fixed_Asm_16 + 0U, // VST3qWB_fixed_Asm_32 + 0U, // VST3qWB_fixed_Asm_8 + 1048U, // VST3qWB_register_Asm_16 + 1048U, // VST3qWB_register_Asm_32 + 1048U, // VST3qWB_register_Asm_8 + 1040U, // VST4LNdAsm_16 + 1040U, // VST4LNdAsm_32 + 1040U, // VST4LNdAsm_8 + 2064U, // VST4LNdWB_fixed_Asm_16 + 2064U, // VST4LNdWB_fixed_Asm_32 + 2064U, // VST4LNdWB_fixed_Asm_8 + 32784U, // VST4LNdWB_register_Asm_16 + 32784U, // VST4LNdWB_register_Asm_32 + 32784U, // VST4LNdWB_register_Asm_8 + 1040U, // VST4LNqAsm_16 + 1040U, // VST4LNqAsm_32 + 2064U, // VST4LNqWB_fixed_Asm_16 + 2064U, // VST4LNqWB_fixed_Asm_32 + 32784U, // VST4LNqWB_register_Asm_16 + 32784U, // VST4LNqWB_register_Asm_32 + 32U, // VST4dAsm_16 + 32U, // VST4dAsm_32 + 32U, // VST4dAsm_8 + 40U, // VST4dWB_fixed_Asm_16 + 40U, // VST4dWB_fixed_Asm_32 + 40U, // VST4dWB_fixed_Asm_8 + 68656U, // VST4dWB_register_Asm_16 + 68656U, // VST4dWB_register_Asm_32 + 68656U, // VST4dWB_register_Asm_8 + 0U, // VST4qAsm_16 + 0U, // VST4qAsm_32 + 0U, // VST4qAsm_8 + 0U, // VST4qWB_fixed_Asm_16 + 0U, // VST4qWB_fixed_Asm_32 + 0U, // VST4qWB_fixed_Asm_8 + 1048U, // VST4qWB_register_Asm_16 + 1048U, // VST4qWB_register_Asm_32 + 1048U, // VST4qWB_register_Asm_8 + 0U, // WIN__CHKSTK + 0U, // WIN__DBZCHK + 0U, // t2ABS + 0U, // t2ADDSri + 0U, // t2ADDSrr + 0U, // t2ADDSrs + 0U, // t2BR_JT + 0U, // t2LDMIA_RET + 1024U, // t2LDRBpcrel + 1024U, // t2LDRConstPool + 1024U, // t2LDRHpcrel + 1024U, // t2LDRSBpcrel + 1024U, // t2LDRSHpcrel + 0U, // t2LDRpci_pic + 1024U, // t2LDRpcrel + 0U, // t2LEApcrel + 0U, // t2LEApcrelJT + 0U, // t2MOVCCasr + 0U, // t2MOVCCi + 0U, // t2MOVCCi16 + 0U, // t2MOVCCi32imm + 0U, // t2MOVCClsl + 0U, // t2MOVCClsr + 0U, // t2MOVCCr + 0U, // t2MOVCCror + 56U, // t2MOVSsi + 64U, // t2MOVSsr + 0U, // t2MOVTi16_ga_pcrel + 0U, // t2MOV_ga_pcrel + 0U, // t2MOVi16_ga_pcrel + 0U, // t2MOVi32imm + 56U, // t2MOVsi + 64U, // t2MOVsr + 0U, // t2MVNCCi + 0U, // t2RSBSri + 0U, // t2RSBSrs + 0U, // t2STRB_preidx + 0U, // t2STRH_preidx + 0U, // t2STR_preidx + 0U, // t2SUBSri + 0U, // t2SUBSrr + 0U, // t2SUBSrs + 0U, // t2TBB_JT + 0U, // t2TBH_JT + 0U, // tADCS + 0U, // tADDSi3 + 0U, // tADDSi8 + 0U, // tADDSrr + 0U, // tADDframe + 0U, // tADJCALLSTACKDOWN + 0U, // tADJCALLSTACKUP + 0U, // tBRIND + 0U, // tBR_JTr + 0U, // tBX_CALL + 0U, // tBX_RET + 0U, // tBX_RET_vararg + 0U, // tBfar + 0U, // tLDMIA_UPD + 1024U, // tLDRConstPool + 0U, // tLDRLIT_ga_abs + 0U, // tLDRLIT_ga_pcrel + 0U, // tLDR_postidx + 0U, // tLDRpci_pic + 0U, // tLEApcrel + 0U, // tLEApcrelJT + 0U, // tMOVCCr_pseudo + 0U, // tPOP_RET + 0U, // tSBCS + 0U, // tSUBSi3 + 0U, // tSUBSi8 + 0U, // tSUBSrr + 0U, // tTAILJMPd + 0U, // tTAILJMPdND + 0U, // tTAILJMPr + 0U, // tTBB_JT + 0U, // tTBH_JT + 0U, // tTPsoft + 98304U, // ADCri + 0U, // ADCrr + 131072U, // ADCrsi + 0U, // ADCrsr + 98304U, // ADDri + 0U, // ADDrr + 131072U, // ADDrsi + 0U, // ADDrsr + 72U, // ADR + 0U, // AESD + 0U, // AESE + 0U, // AESIMC + 0U, // AESMC + 98304U, // ANDri + 0U, // ANDrr + 131072U, // ANDrsi + 0U, // ANDrsr + 80U, // BFC + 163928U, // BFI + 98304U, // BICri + 0U, // BICrr + 131072U, // BICrsi + 0U, // BICrsr + 0U, // BKPT + 0U, // BL + 0U, // BLX + 0U, // BLX_pred + 0U, // BLXi + 0U, // BL_pred + 0U, // BX + 0U, // BXJ + 0U, // BX_RET + 0U, // BX_pred + 0U, // Bcc + 4145U, // CDP + 0U, // CDP2 + 0U, // CLREX + 1024U, // CLZ + 96U, // CMNri + 1024U, // CMNzrr + 104U, // CMNzrsi + 64U, // CMNzrsr + 96U, // CMPri + 1024U, // CMPrr + 104U, // CMPrsi + 64U, // CMPrsr + 0U, // CPS1p + 0U, // CPS2p + 1112U, // CPS3p + 1112U, // CRC32B + 1112U, // CRC32CB + 1112U, // CRC32CH + 1112U, // CRC32CW + 1112U, // CRC32H + 1112U, // CRC32W + 0U, // DBG + 0U, // DMB + 0U, // DSB + 98304U, // EORri + 0U, // EORrr + 131072U, // EORrsi + 0U, // EORrsr + 0U, // ERET + 1U, // FCONSTD + 1U, // FCONSTH + 1U, // FCONSTS + 33U, // FLDMXDB_UPD + 1136U, // FLDMXIA + 33U, // FLDMXIA_UPD + 0U, // FMSTAT + 33U, // FSTMXDB_UPD + 1136U, // FSTMXIA + 33U, // FSTMXIA_UPD + 0U, // HINT + 0U, // HLT + 0U, // HVC + 0U, // ISB + 8U, // LDA + 8U, // LDAB + 8U, // LDAEX + 8U, // LDAEXB + 0U, // LDAEXD + 8U, // LDAEXH + 8U, // LDAH + 0U, // LDC2L_OFFSET + 1U, // LDC2L_OPTION + 2U, // LDC2L_POST + 0U, // LDC2L_PRE + 0U, // LDC2_OFFSET + 1U, // LDC2_OPTION + 2U, // LDC2_POST + 0U, // LDC2_PRE + 122U, // LDCL_OFFSET + 196738U, // LDCL_OPTION + 229506U, // LDCL_POST + 138U, // LDCL_PRE + 122U, // LDC_OFFSET + 196738U, // LDC_OPTION + 229506U, // LDC_POST + 138U, // LDC_PRE + 1136U, // LDMDA + 33U, // LDMDA_UPD + 1136U, // LDMDB + 33U, // LDMDB_UPD + 1136U, // LDMIA + 33U, // LDMIA_UPD + 1136U, // LDMIB + 33U, // LDMIB_UPD + 262272U, // LDRBT_POST_IMM + 262272U, // LDRBT_POST_REG + 262272U, // LDRB_POST_IMM + 262272U, // LDRB_POST_REG + 144U, // LDRB_PRE_IMM + 152U, // LDRB_PRE_REG + 160U, // LDRBi12 + 168U, // LDRBrs + 294912U, // LDRD + 2424832U, // LDRD_POST + 360448U, // LDRD_PRE + 8U, // LDREX + 8U, // LDREXB + 0U, // LDREXD + 8U, // LDREXH + 176U, // LDRH + 393344U, // LDRHTi + 426112U, // LDRHTr + 458880U, // LDRH_POST + 184U, // LDRH_PRE + 176U, // LDRSB + 393344U, // LDRSBTi + 426112U, // LDRSBTr + 458880U, // LDRSB_POST + 184U, // LDRSB_PRE + 176U, // LDRSH + 393344U, // LDRSHTi + 426112U, // LDRSHTr + 458880U, // LDRSH_POST + 184U, // LDRSH_PRE + 262272U, // LDRT_POST_IMM + 262272U, // LDRT_POST_REG + 262272U, // LDR_POST_IMM + 262272U, // LDR_POST_REG + 144U, // LDR_PRE_IMM + 152U, // LDR_PRE_REG + 160U, // LDRcp + 160U, // LDRi12 + 168U, // LDRrs + 4690993U, // MCR + 192U, // MCR2 + 6788145U, // MCRR + 524312U, // MCRR2 + 35651584U, // MLA + 35651584U, // MLS + 0U, // MOVPCLR + 1112U, // MOVTi16 + 96U, // MOVi + 1024U, // MOVi16 + 1024U, // MOVr + 1024U, // MOVr_TC + 104U, // MOVsi + 64U, // MOVsr + 0U, // MRC + 0U, // MRC2 + 0U, // MRRC + 0U, // MRRC2 + 2U, // MRS + 200U, // MRSbanked + 2U, // MRSsys + 33U, // MSR + 0U, // MSRbanked + 3U, // MSRi + 0U, // MUL + 96U, // MVNi + 1024U, // MVNr + 104U, // MVNsi + 64U, // MVNsr + 98304U, // ORRri + 0U, // ORRrr + 131072U, // ORRrsi + 0U, // ORRrsr + 8388608U, // PKHBT + 10485760U, // PKHTB + 0U, // PLDWi12 + 0U, // PLDWrs + 0U, // PLDi12 + 0U, // PLDrs + 0U, // PLIi12 + 0U, // PLIrs + 0U, // QADD + 0U, // QADD16 + 0U, // QADD8 + 0U, // QASX + 0U, // QDADD + 0U, // QDSUB + 0U, // QSAX + 0U, // QSUB + 0U, // QSUB16 + 0U, // QSUB8 + 1024U, // RBIT + 1024U, // REV + 1024U, // REV16 + 1024U, // REVSH + 0U, // RFEDA + 0U, // RFEDA_UPD + 0U, // RFEDB + 0U, // RFEDB_UPD + 0U, // RFEIA + 0U, // RFEIA_UPD + 0U, // RFEIB + 0U, // RFEIB_UPD + 98304U, // RSBri + 0U, // RSBrr + 131072U, // RSBrsi + 0U, // RSBrsr + 98304U, // RSCri + 0U, // RSCrr + 131072U, // RSCrsi + 0U, // RSCrsr + 0U, // SADD16 + 0U, // SADD8 + 0U, // SASX + 98304U, // SBCri + 0U, // SBCrr + 131072U, // SBCrsi + 0U, // SBCrsr + 69206016U, // SBFX + 0U, // SDIV + 0U, // SEL + 0U, // SETEND + 0U, // SETPAN + 1048U, // SHA1C + 0U, // SHA1H + 1048U, // SHA1M + 1048U, // SHA1P + 1048U, // SHA1SU0 + 0U, // SHA1SU1 + 1048U, // SHA256H + 1048U, // SHA256H2 + 0U, // SHA256SU0 + 1048U, // SHA256SU1 + 0U, // SHADD16 + 0U, // SHADD8 + 0U, // SHASX + 0U, // SHSAX + 0U, // SHSUB16 + 0U, // SHSUB8 + 0U, // SMC + 35651584U, // SMLABB + 35651584U, // SMLABT + 35651584U, // SMLAD + 35651584U, // SMLADX + 0U, // SMLAL + 35651584U, // SMLALBB + 35651584U, // SMLALBT + 35651584U, // SMLALD + 35651584U, // SMLALDX + 35651584U, // SMLALTB + 35651584U, // SMLALTT + 35651584U, // SMLATB + 35651584U, // SMLATT + 35651584U, // SMLAWB + 35651584U, // SMLAWT + 35651584U, // SMLSD + 35651584U, // SMLSDX + 35651584U, // SMLSLD + 35651584U, // SMLSLDX + 35651584U, // SMMLA + 35651584U, // SMMLAR + 35651584U, // SMMLS + 35651584U, // SMMLSR + 0U, // SMMUL + 0U, // SMMULR + 0U, // SMUAD + 0U, // SMUADX + 0U, // SMULBB + 0U, // SMULBT + 35651584U, // SMULL + 0U, // SMULTB + 0U, // SMULTT + 0U, // SMULWB + 0U, // SMULWT + 0U, // SMUSD + 0U, // SMUSDX + 0U, // SRSDA + 0U, // SRSDA_UPD + 0U, // SRSDB + 0U, // SRSDB_UPD + 0U, // SRSIA + 0U, // SRSIA_UPD + 0U, // SRSIB + 0U, // SRSIB_UPD + 6352U, // SSAT + 1232U, // SSAT16 + 0U, // SSAX + 0U, // SSUB16 + 0U, // SSUB8 + 0U, // STC2L_OFFSET + 1U, // STC2L_OPTION + 2U, // STC2L_POST + 0U, // STC2L_PRE + 0U, // STC2_OFFSET + 1U, // STC2_OPTION + 2U, // STC2_POST + 0U, // STC2_PRE + 122U, // STCL_OFFSET + 196738U, // STCL_OPTION + 229506U, // STCL_POST + 138U, // STCL_PRE + 122U, // STC_OFFSET + 196738U, // STC_OPTION + 229506U, // STC_POST + 138U, // STC_PRE + 8U, // STL + 8U, // STLB + 557056U, // STLEX + 557056U, // STLEXB + 216U, // STLEXD + 557056U, // STLEXH + 8U, // STLH + 1136U, // STMDA + 33U, // STMDA_UPD + 1136U, // STMDB + 33U, // STMDB_UPD + 1136U, // STMIA + 33U, // STMIA_UPD + 1136U, // STMIB + 33U, // STMIB_UPD + 262272U, // STRBT_POST_IMM + 262272U, // STRBT_POST_REG + 262272U, // STRB_POST_IMM + 262272U, // STRB_POST_REG + 144U, // STRB_PRE_IMM + 152U, // STRB_PRE_REG + 160U, // STRBi12 + 168U, // STRBrs + 294912U, // STRD + 2424920U, // STRD_POST + 360536U, // STRD_PRE + 557056U, // STREX + 557056U, // STREXB + 216U, // STREXD + 557056U, // STREXH + 176U, // STRH + 393344U, // STRHTi + 426112U, // STRHTr + 458880U, // STRH_POST + 184U, // STRH_PRE + 262272U, // STRT_POST_IMM + 262272U, // STRT_POST_REG + 262272U, // STR_POST_IMM + 262272U, // STR_POST_REG + 144U, // STR_PRE_IMM + 152U, // STR_PRE_REG + 160U, // STRi12 + 168U, // STRrs + 98304U, // SUBri + 0U, // SUBrr + 131072U, // SUBrsi + 0U, // SUBrsr + 0U, // SVC + 557056U, // SWP + 557056U, // SWPB + 12582912U, // SXTAB + 12582912U, // SXTAB16 + 12582912U, // SXTAH + 7168U, // SXTB + 7168U, // SXTB16 + 7168U, // SXTH + 96U, // TEQri + 1024U, // TEQrr + 104U, // TEQrsi + 64U, // TEQrsr + 0U, // TRAP + 0U, // TRAPNaCl + 0U, // TSB + 96U, // TSTri + 1024U, // TSTrr + 104U, // TSTrsi + 64U, // TSTrsr + 0U, // UADD16 + 0U, // UADD8 + 0U, // UASX + 69206016U, // UBFX + 0U, // UDF + 0U, // UDIV + 0U, // UHADD16 + 0U, // UHADD8 + 0U, // UHASX + 0U, // UHSAX + 0U, // UHSUB16 + 0U, // UHSUB8 + 35651584U, // UMAAL + 0U, // UMLAL + 35651584U, // UMULL + 0U, // UQADD16 + 0U, // UQADD8 + 0U, // UQASX + 0U, // UQSAX + 0U, // UQSUB16 + 0U, // UQSUB8 + 0U, // USAD8 + 35651584U, // USADA8 + 14680064U, // USAT + 0U, // USAT16 + 0U, // USAX + 0U, // USUB16 + 0U, // USUB8 + 12582912U, // UXTAB + 12582912U, // UXTAB16 + 12582912U, // UXTAH + 7168U, // UXTB + 7168U, // UXTB16 + 7168U, // UXTH + 1048U, // VABALsv2i64 + 1048U, // VABALsv4i32 + 1048U, // VABALsv8i16 + 1048U, // VABALuv2i64 + 1048U, // VABALuv4i32 + 1048U, // VABALuv8i16 + 1048U, // VABAsv16i8 + 1048U, // VABAsv2i32 + 1048U, // VABAsv4i16 + 1048U, // VABAsv4i32 + 1048U, // VABAsv8i16 + 1048U, // VABAsv8i8 + 1048U, // VABAuv16i8 + 1048U, // VABAuv2i32 + 1048U, // VABAuv4i16 + 1048U, // VABAuv4i32 + 1048U, // VABAuv8i16 + 1048U, // VABAuv8i8 + 1112U, // VABDLsv2i64 + 1112U, // VABDLsv4i32 + 1112U, // VABDLsv8i16 + 1112U, // VABDLuv2i64 + 1112U, // VABDLuv4i32 + 1112U, // VABDLuv8i16 + 70705U, // VABDfd + 70705U, // VABDfq + 70705U, // VABDhd + 70705U, // VABDhq + 1112U, // VABDsv16i8 + 1112U, // VABDsv2i32 + 1112U, // VABDsv4i16 + 1112U, // VABDsv4i32 + 1112U, // VABDsv8i16 + 1112U, // VABDsv8i8 + 1112U, // VABDuv16i8 + 1112U, // VABDuv2i32 + 1112U, // VABDuv4i16 + 1112U, // VABDuv4i32 + 1112U, // VABDuv8i16 + 1112U, // VABDuv8i8 + 33U, // VABSD + 33U, // VABSH + 33U, // VABSS + 33U, // VABSfd + 33U, // VABSfq + 33U, // VABShd + 33U, // VABShq + 0U, // VABSv16i8 + 0U, // VABSv2i32 + 0U, // VABSv4i16 + 0U, // VABSv4i32 + 0U, // VABSv8i16 + 0U, // VABSv8i8 + 70705U, // VACGEfd + 70705U, // VACGEfq + 70705U, // VACGEhd + 70705U, // VACGEhq + 70705U, // VACGTfd + 70705U, // VACGTfq + 70705U, // VACGThd + 70705U, // VACGThq + 70705U, // VADDD + 70705U, // VADDH + 1112U, // VADDHNv2i32 + 1112U, // VADDHNv4i16 + 1112U, // VADDHNv8i8 + 1112U, // VADDLsv2i64 + 1112U, // VADDLsv4i32 + 1112U, // VADDLsv8i16 + 1112U, // VADDLuv2i64 + 1112U, // VADDLuv4i32 + 1112U, // VADDLuv8i16 + 70705U, // VADDS + 1112U, // VADDWsv2i64 + 1112U, // VADDWsv4i32 + 1112U, // VADDWsv8i16 + 1112U, // VADDWuv2i64 + 1112U, // VADDWuv4i32 + 1112U, // VADDWuv8i16 + 70705U, // VADDfd + 70705U, // VADDfq + 70705U, // VADDhd + 70705U, // VADDhq + 1112U, // VADDv16i8 + 1112U, // VADDv1i64 + 1112U, // VADDv2i32 + 1112U, // VADDv2i64 + 1112U, // VADDv4i16 + 1112U, // VADDv4i32 + 1112U, // VADDv8i16 + 1112U, // VADDv8i8 + 0U, // VANDd + 0U, // VANDq + 0U, // VBICd + 0U, // VBICiv2i32 + 0U, // VBICiv4i16 + 0U, // VBICiv4i32 + 0U, // VBICiv8i16 + 0U, // VBICq + 589912U, // VBIFd + 589912U, // VBIFq + 589912U, // VBITd + 589912U, // VBITq + 589912U, // VBSLd + 589912U, // VBSLq + 622680U, // VCADDv2f32 + 622680U, // VCADDv4f16 + 622680U, // VCADDv4f32 + 622680U, // VCADDv8f16 + 70705U, // VCEQfd + 70705U, // VCEQfq + 70705U, // VCEQhd + 70705U, // VCEQhq + 1112U, // VCEQv16i8 + 1112U, // VCEQv2i32 + 1112U, // VCEQv4i16 + 1112U, // VCEQv4i32 + 1112U, // VCEQv8i16 + 1112U, // VCEQv8i8 + 3U, // VCEQzv16i8 + 225U, // VCEQzv2f32 + 3U, // VCEQzv2i32 + 225U, // VCEQzv4f16 + 225U, // VCEQzv4f32 + 3U, // VCEQzv4i16 + 3U, // VCEQzv4i32 + 225U, // VCEQzv8f16 + 3U, // VCEQzv8i16 + 3U, // VCEQzv8i8 + 70705U, // VCGEfd + 70705U, // VCGEfq + 70705U, // VCGEhd + 70705U, // VCGEhq + 1112U, // VCGEsv16i8 + 1112U, // VCGEsv2i32 + 1112U, // VCGEsv4i16 + 1112U, // VCGEsv4i32 + 1112U, // VCGEsv8i16 + 1112U, // VCGEsv8i8 + 1112U, // VCGEuv16i8 + 1112U, // VCGEuv2i32 + 1112U, // VCGEuv4i16 + 1112U, // VCGEuv4i32 + 1112U, // VCGEuv8i16 + 1112U, // VCGEuv8i8 + 3U, // VCGEzv16i8 + 225U, // VCGEzv2f32 + 3U, // VCGEzv2i32 + 225U, // VCGEzv4f16 + 225U, // VCGEzv4f32 + 3U, // VCGEzv4i16 + 3U, // VCGEzv4i32 + 225U, // VCGEzv8f16 + 3U, // VCGEzv8i16 + 3U, // VCGEzv8i8 + 70705U, // VCGTfd + 70705U, // VCGTfq + 70705U, // VCGThd + 70705U, // VCGThq + 1112U, // VCGTsv16i8 + 1112U, // VCGTsv2i32 + 1112U, // VCGTsv4i16 + 1112U, // VCGTsv4i32 + 1112U, // VCGTsv8i16 + 1112U, // VCGTsv8i8 + 1112U, // VCGTuv16i8 + 1112U, // VCGTuv2i32 + 1112U, // VCGTuv4i16 + 1112U, // VCGTuv4i32 + 1112U, // VCGTuv8i16 + 1112U, // VCGTuv8i8 + 3U, // VCGTzv16i8 + 225U, // VCGTzv2f32 + 3U, // VCGTzv2i32 + 225U, // VCGTzv4f16 + 225U, // VCGTzv4f32 + 3U, // VCGTzv4i16 + 3U, // VCGTzv4i32 + 225U, // VCGTzv8f16 + 3U, // VCGTzv8i16 + 3U, // VCGTzv8i8 + 3U, // VCLEzv16i8 + 225U, // VCLEzv2f32 + 3U, // VCLEzv2i32 + 225U, // VCLEzv4f16 + 225U, // VCLEzv4f32 + 3U, // VCLEzv4i16 + 3U, // VCLEzv4i32 + 225U, // VCLEzv8f16 + 3U, // VCLEzv8i16 + 3U, // VCLEzv8i8 + 0U, // VCLSv16i8 + 0U, // VCLSv2i32 + 0U, // VCLSv4i16 + 0U, // VCLSv4i32 + 0U, // VCLSv8i16 + 0U, // VCLSv8i8 + 3U, // VCLTzv16i8 + 225U, // VCLTzv2f32 + 3U, // VCLTzv2i32 + 225U, // VCLTzv4f16 + 225U, // VCLTzv4f32 + 3U, // VCLTzv4i16 + 3U, // VCLTzv4i32 + 225U, // VCLTzv8f16 + 3U, // VCLTzv8i16 + 3U, // VCLTzv8i8 + 0U, // VCLZv16i8 + 0U, // VCLZv2i32 + 0U, // VCLZv4i16 + 0U, // VCLZv4i32 + 0U, // VCLZv8i16 + 0U, // VCLZv8i8 + 655384U, // VCMLAv2f32 + 17276952U, // VCMLAv2f32_indexed + 655384U, // VCMLAv4f16 + 17276952U, // VCMLAv4f16_indexed + 655384U, // VCMLAv4f32 + 17276952U, // VCMLAv4f32_indexed + 655384U, // VCMLAv8f16 + 17276952U, // VCMLAv8f16_indexed + 33U, // VCMPD + 33U, // VCMPED + 33U, // VCMPEH + 33U, // VCMPES + 0U, // VCMPEZD + 0U, // VCMPEZH + 0U, // VCMPEZS + 33U, // VCMPH + 33U, // VCMPS + 0U, // VCMPZD + 0U, // VCMPZH + 0U, // VCMPZS + 1024U, // VCNTd + 1024U, // VCNTq + 0U, // VCVTANSDf + 0U, // VCVTANSDh + 0U, // VCVTANSQf + 0U, // VCVTANSQh + 0U, // VCVTANUDf + 0U, // VCVTANUDh + 0U, // VCVTANUQf + 0U, // VCVTANUQh + 0U, // VCVTASD + 0U, // VCVTASH + 0U, // VCVTASS + 0U, // VCVTAUD + 0U, // VCVTAUH + 0U, // VCVTAUS + 0U, // VCVTBDH + 0U, // VCVTBHD + 0U, // VCVTBHS + 0U, // VCVTBSH + 0U, // VCVTDS + 0U, // VCVTMNSDf + 0U, // VCVTMNSDh + 0U, // VCVTMNSQf + 0U, // VCVTMNSQh + 0U, // VCVTMNUDf + 0U, // VCVTMNUDh + 0U, // VCVTMNUQf + 0U, // VCVTMNUQh + 0U, // VCVTMSD + 0U, // VCVTMSH + 0U, // VCVTMSS + 0U, // VCVTMUD + 0U, // VCVTMUH + 0U, // VCVTMUS + 0U, // VCVTNNSDf + 0U, // VCVTNNSDh + 0U, // VCVTNNSQf + 0U, // VCVTNNSQh + 0U, // VCVTNNUDf + 0U, // VCVTNNUDh + 0U, // VCVTNNUQf + 0U, // VCVTNNUQh + 0U, // VCVTNSD + 0U, // VCVTNSH + 0U, // VCVTNSS + 0U, // VCVTNUD + 0U, // VCVTNUH + 0U, // VCVTNUS + 0U, // VCVTPNSDf + 0U, // VCVTPNSDh + 0U, // VCVTPNSQf + 0U, // VCVTPNSQh + 0U, // VCVTPNUDf + 0U, // VCVTPNUDh + 0U, // VCVTPNUQf + 0U, // VCVTPNUQh + 0U, // VCVTPSD + 0U, // VCVTPSH + 0U, // VCVTPSS + 0U, // VCVTPUD + 0U, // VCVTPUH + 0U, // VCVTPUS + 0U, // VCVTSD + 0U, // VCVTTDH + 0U, // VCVTTHD + 0U, // VCVTTHS + 0U, // VCVTTSH + 0U, // VCVTf2h + 0U, // VCVTf2sd + 0U, // VCVTf2sq + 0U, // VCVTf2ud + 0U, // VCVTf2uq + 35U, // VCVTf2xsd + 35U, // VCVTf2xsq + 35U, // VCVTf2xud + 35U, // VCVTf2xuq + 0U, // VCVTh2f + 0U, // VCVTh2sd + 0U, // VCVTh2sq + 0U, // VCVTh2ud + 0U, // VCVTh2uq + 35U, // VCVTh2xsd + 35U, // VCVTh2xsq + 35U, // VCVTh2xud + 35U, // VCVTh2xuq + 0U, // VCVTs2fd + 0U, // VCVTs2fq + 0U, // VCVTs2hd + 0U, // VCVTs2hq + 0U, // VCVTu2fd + 0U, // VCVTu2fq + 0U, // VCVTu2hd + 0U, // VCVTu2hq + 35U, // VCVTxs2fd + 35U, // VCVTxs2fq + 35U, // VCVTxs2hd + 35U, // VCVTxs2hq + 35U, // VCVTxu2fd + 35U, // VCVTxu2fq + 35U, // VCVTxu2hd + 35U, // VCVTxu2hq + 70705U, // VDIVD + 70705U, // VDIVH + 70705U, // VDIVS + 1024U, // VDUP16d + 1024U, // VDUP16q + 1024U, // VDUP32d + 1024U, // VDUP32q + 1024U, // VDUP8d + 1024U, // VDUP8q + 9216U, // VDUPLN16d + 9216U, // VDUPLN16q + 9216U, // VDUPLN32d + 9216U, // VDUPLN32q + 9216U, // VDUPLN8d + 9216U, // VDUPLN8q + 0U, // VEORd + 0U, // VEORq + 35651584U, // VEXTd16 + 35651584U, // VEXTd32 + 35651584U, // VEXTd8 + 35651584U, // VEXTq16 + 35651584U, // VEXTq32 + 35651584U, // VEXTq64 + 35651584U, // VEXTq8 + 68659U, // VFMAD + 68659U, // VFMAH + 68659U, // VFMAS + 68659U, // VFMAfd + 68659U, // VFMAfq + 68659U, // VFMAhd + 68659U, // VFMAhq + 68659U, // VFMSD + 68659U, // VFMSH + 68659U, // VFMSS + 68659U, // VFMSfd + 68659U, // VFMSfq + 68659U, // VFMShd + 68659U, // VFMShq + 68659U, // VFNMAD + 68659U, // VFNMAH + 68659U, // VFNMAS + 68659U, // VFNMSD + 68659U, // VFNMSH + 68659U, // VFNMSS + 9216U, // VGETLNi32 + 3U, // VGETLNs16 + 3U, // VGETLNs8 + 3U, // VGETLNu16 + 3U, // VGETLNu8 + 1112U, // VHADDsv16i8 + 1112U, // VHADDsv2i32 + 1112U, // VHADDsv4i16 + 1112U, // VHADDsv4i32 + 1112U, // VHADDsv8i16 + 1112U, // VHADDsv8i8 + 1112U, // VHADDuv16i8 + 1112U, // VHADDuv2i32 + 1112U, // VHADDuv4i16 + 1112U, // VHADDuv4i32 + 1112U, // VHADDuv8i16 + 1112U, // VHADDuv8i8 + 1112U, // VHSUBsv16i8 + 1112U, // VHSUBsv2i32 + 1112U, // VHSUBsv4i16 + 1112U, // VHSUBsv4i32 + 1112U, // VHSUBsv8i16 + 1112U, // VHSUBsv8i8 + 1112U, // VHSUBuv16i8 + 1112U, // VHSUBuv2i32 + 1112U, // VHSUBuv4i16 + 1112U, // VHSUBuv4i32 + 1112U, // VHSUBuv8i16 + 1112U, // VHSUBuv8i8 + 0U, // VINSH + 0U, // VJCVT + 32U, // VLD1DUPd16 + 44U, // VLD1DUPd16wb_fixed + 10292U, // VLD1DUPd16wb_register + 32U, // VLD1DUPd32 + 44U, // VLD1DUPd32wb_fixed + 10292U, // VLD1DUPd32wb_register + 32U, // VLD1DUPd8 + 44U, // VLD1DUPd8wb_fixed + 10292U, // VLD1DUPd8wb_register + 32U, // VLD1DUPq16 + 44U, // VLD1DUPq16wb_fixed + 10292U, // VLD1DUPq16wb_register + 32U, // VLD1DUPq32 + 44U, // VLD1DUPq32wb_fixed + 10292U, // VLD1DUPq32wb_register + 32U, // VLD1DUPq8 + 44U, // VLD1DUPq8wb_fixed + 10292U, // VLD1DUPq8wb_register + 699628U, // VLD1LNd16 + 732404U, // VLD1LNd16_UPD + 699628U, // VLD1LNd32 + 732404U, // VLD1LNd32_UPD + 699628U, // VLD1LNd8 + 732404U, // VLD1LNd8_UPD + 0U, // VLD1LNq16Pseudo + 0U, // VLD1LNq16Pseudo_UPD + 0U, // VLD1LNq32Pseudo + 0U, // VLD1LNq32Pseudo_UPD + 0U, // VLD1LNq8Pseudo + 0U, // VLD1LNq8Pseudo_UPD + 32U, // VLD1d16 + 32U, // VLD1d16Q + 0U, // VLD1d16QPseudo + 44U, // VLD1d16Qwb_fixed + 10292U, // VLD1d16Qwb_register + 32U, // VLD1d16T + 0U, // VLD1d16TPseudo + 44U, // VLD1d16Twb_fixed + 10292U, // VLD1d16Twb_register + 44U, // VLD1d16wb_fixed + 10292U, // VLD1d16wb_register + 32U, // VLD1d32 + 32U, // VLD1d32Q + 0U, // VLD1d32QPseudo + 44U, // VLD1d32Qwb_fixed + 10292U, // VLD1d32Qwb_register + 32U, // VLD1d32T + 0U, // VLD1d32TPseudo + 44U, // VLD1d32Twb_fixed + 10292U, // VLD1d32Twb_register + 44U, // VLD1d32wb_fixed + 10292U, // VLD1d32wb_register + 32U, // VLD1d64 + 32U, // VLD1d64Q + 0U, // VLD1d64QPseudo + 0U, // VLD1d64QPseudoWB_fixed + 0U, // VLD1d64QPseudoWB_register + 44U, // VLD1d64Qwb_fixed + 10292U, // VLD1d64Qwb_register + 32U, // VLD1d64T + 0U, // VLD1d64TPseudo + 0U, // VLD1d64TPseudoWB_fixed + 0U, // VLD1d64TPseudoWB_register + 44U, // VLD1d64Twb_fixed + 10292U, // VLD1d64Twb_register + 44U, // VLD1d64wb_fixed + 10292U, // VLD1d64wb_register + 32U, // VLD1d8 + 32U, // VLD1d8Q + 0U, // VLD1d8QPseudo + 44U, // VLD1d8Qwb_fixed + 10292U, // VLD1d8Qwb_register + 32U, // VLD1d8T + 0U, // VLD1d8TPseudo + 44U, // VLD1d8Twb_fixed + 10292U, // VLD1d8Twb_register + 44U, // VLD1d8wb_fixed + 10292U, // VLD1d8wb_register + 32U, // VLD1q16 + 0U, // VLD1q16HighQPseudo + 0U, // VLD1q16HighTPseudo + 0U, // VLD1q16LowQPseudo_UPD + 0U, // VLD1q16LowTPseudo_UPD + 44U, // VLD1q16wb_fixed + 10292U, // VLD1q16wb_register + 32U, // VLD1q32 + 0U, // VLD1q32HighQPseudo + 0U, // VLD1q32HighTPseudo + 0U, // VLD1q32LowQPseudo_UPD + 0U, // VLD1q32LowTPseudo_UPD + 44U, // VLD1q32wb_fixed + 10292U, // VLD1q32wb_register + 32U, // VLD1q64 + 0U, // VLD1q64HighQPseudo + 0U, // VLD1q64HighTPseudo + 0U, // VLD1q64LowQPseudo_UPD + 0U, // VLD1q64LowTPseudo_UPD + 44U, // VLD1q64wb_fixed + 10292U, // VLD1q64wb_register + 32U, // VLD1q8 + 0U, // VLD1q8HighQPseudo + 0U, // VLD1q8HighTPseudo + 0U, // VLD1q8LowQPseudo_UPD + 0U, // VLD1q8LowTPseudo_UPD + 44U, // VLD1q8wb_fixed + 10292U, // VLD1q8wb_register + 32U, // VLD2DUPd16 + 44U, // VLD2DUPd16wb_fixed + 10292U, // VLD2DUPd16wb_register + 32U, // VLD2DUPd16x2 + 44U, // VLD2DUPd16x2wb_fixed + 10292U, // VLD2DUPd16x2wb_register + 32U, // VLD2DUPd32 + 44U, // VLD2DUPd32wb_fixed + 10292U, // VLD2DUPd32wb_register + 32U, // VLD2DUPd32x2 + 44U, // VLD2DUPd32x2wb_fixed + 10292U, // VLD2DUPd32x2wb_register + 32U, // VLD2DUPd8 + 44U, // VLD2DUPd8wb_fixed + 10292U, // VLD2DUPd8wb_register + 32U, // VLD2DUPd8x2 + 44U, // VLD2DUPd8x2wb_fixed + 10292U, // VLD2DUPd8x2wb_register + 0U, // VLD2DUPq16EvenPseudo + 0U, // VLD2DUPq16OddPseudo + 0U, // VLD2DUPq32EvenPseudo + 0U, // VLD2DUPq32OddPseudo + 0U, // VLD2DUPq8EvenPseudo + 0U, // VLD2DUPq8OddPseudo + 766196U, // VLD2LNd16 + 0U, // VLD2LNd16Pseudo + 0U, // VLD2LNd16Pseudo_UPD + 799996U, // VLD2LNd16_UPD + 766196U, // VLD2LNd32 + 0U, // VLD2LNd32Pseudo + 0U, // VLD2LNd32Pseudo_UPD + 799996U, // VLD2LNd32_UPD + 766196U, // VLD2LNd8 + 0U, // VLD2LNd8Pseudo + 0U, // VLD2LNd8Pseudo_UPD + 799996U, // VLD2LNd8_UPD + 766196U, // VLD2LNq16 + 0U, // VLD2LNq16Pseudo + 0U, // VLD2LNq16Pseudo_UPD + 799996U, // VLD2LNq16_UPD + 766196U, // VLD2LNq32 + 0U, // VLD2LNq32Pseudo + 0U, // VLD2LNq32Pseudo_UPD + 799996U, // VLD2LNq32_UPD + 32U, // VLD2b16 + 44U, // VLD2b16wb_fixed + 10292U, // VLD2b16wb_register + 32U, // VLD2b32 + 44U, // VLD2b32wb_fixed + 10292U, // VLD2b32wb_register + 32U, // VLD2b8 + 44U, // VLD2b8wb_fixed + 10292U, // VLD2b8wb_register + 32U, // VLD2d16 + 44U, // VLD2d16wb_fixed + 10292U, // VLD2d16wb_register + 32U, // VLD2d32 + 44U, // VLD2d32wb_fixed + 10292U, // VLD2d32wb_register + 32U, // VLD2d8 + 44U, // VLD2d8wb_fixed + 10292U, // VLD2d8wb_register + 32U, // VLD2q16 + 0U, // VLD2q16Pseudo + 0U, // VLD2q16PseudoWB_fixed + 0U, // VLD2q16PseudoWB_register + 44U, // VLD2q16wb_fixed + 10292U, // VLD2q16wb_register + 32U, // VLD2q32 + 0U, // VLD2q32Pseudo + 0U, // VLD2q32PseudoWB_fixed + 0U, // VLD2q32PseudoWB_register + 44U, // VLD2q32wb_fixed + 10292U, // VLD2q32wb_register + 32U, // VLD2q8 + 0U, // VLD2q8Pseudo + 0U, // VLD2q8PseudoWB_fixed + 0U, // VLD2q8PseudoWB_register + 44U, // VLD2q8wb_fixed + 10292U, // VLD2q8wb_register + 14596U, // VLD3DUPd16 + 0U, // VLD3DUPd16Pseudo + 0U, // VLD3DUPd16Pseudo_UPD + 834820U, // VLD3DUPd16_UPD + 14596U, // VLD3DUPd32 + 0U, // VLD3DUPd32Pseudo + 0U, // VLD3DUPd32Pseudo_UPD + 834820U, // VLD3DUPd32_UPD + 14596U, // VLD3DUPd8 + 0U, // VLD3DUPd8Pseudo + 0U, // VLD3DUPd8Pseudo_UPD + 834820U, // VLD3DUPd8_UPD + 14596U, // VLD3DUPq16 + 0U, // VLD3DUPq16EvenPseudo + 0U, // VLD3DUPq16OddPseudo + 834820U, // VLD3DUPq16_UPD + 14596U, // VLD3DUPq32 + 0U, // VLD3DUPq32EvenPseudo + 0U, // VLD3DUPq32OddPseudo + 834820U, // VLD3DUPq32_UPD + 14596U, // VLD3DUPq8 + 0U, // VLD3DUPq8EvenPseudo + 0U, // VLD3DUPq8OddPseudo + 834820U, // VLD3DUPq8_UPD + 865532U, // VLD3LNd16 + 0U, // VLD3LNd16Pseudo + 0U, // VLD3LNd16Pseudo_UPD + 896268U, // VLD3LNd16_UPD + 865532U, // VLD3LNd32 + 0U, // VLD3LNd32Pseudo + 0U, // VLD3LNd32Pseudo_UPD + 896268U, // VLD3LNd32_UPD + 865532U, // VLD3LNd8 + 0U, // VLD3LNd8Pseudo + 0U, // VLD3LNd8Pseudo_UPD + 896268U, // VLD3LNd8_UPD + 865532U, // VLD3LNq16 + 0U, // VLD3LNq16Pseudo + 0U, // VLD3LNq16Pseudo_UPD + 896268U, // VLD3LNq16_UPD + 865532U, // VLD3LNq32 + 0U, // VLD3LNq32Pseudo + 0U, // VLD3LNq32Pseudo_UPD + 896268U, // VLD3LNq32_UPD + 119537664U, // VLD3d16 + 0U, // VLD3d16Pseudo + 0U, // VLD3d16Pseudo_UPD + 153092096U, // VLD3d16_UPD + 119537664U, // VLD3d32 + 0U, // VLD3d32Pseudo + 0U, // VLD3d32Pseudo_UPD + 153092096U, // VLD3d32_UPD + 119537664U, // VLD3d8 + 0U, // VLD3d8Pseudo + 0U, // VLD3d8Pseudo_UPD + 153092096U, // VLD3d8_UPD + 119537664U, // VLD3q16 + 0U, // VLD3q16Pseudo_UPD + 153092096U, // VLD3q16_UPD + 0U, // VLD3q16oddPseudo + 0U, // VLD3q16oddPseudo_UPD + 119537664U, // VLD3q32 + 0U, // VLD3q32Pseudo_UPD + 153092096U, // VLD3q32_UPD + 0U, // VLD3q32oddPseudo + 0U, // VLD3q32oddPseudo_UPD + 119537664U, // VLD3q8 + 0U, // VLD3q8Pseudo_UPD + 153092096U, // VLD3q8_UPD + 0U, // VLD3q8oddPseudo + 0U, // VLD3q8oddPseudo_UPD + 81172U, // VLD4DUPd16 + 0U, // VLD4DUPd16Pseudo + 0U, // VLD4DUPd16Pseudo_UPD + 16660U, // VLD4DUPd16_UPD + 81172U, // VLD4DUPd32 + 0U, // VLD4DUPd32Pseudo + 0U, // VLD4DUPd32Pseudo_UPD + 16660U, // VLD4DUPd32_UPD + 81172U, // VLD4DUPd8 + 0U, // VLD4DUPd8Pseudo + 0U, // VLD4DUPd8Pseudo_UPD + 16660U, // VLD4DUPd8_UPD + 81172U, // VLD4DUPq16 + 0U, // VLD4DUPq16EvenPseudo + 0U, // VLD4DUPq16OddPseudo + 16660U, // VLD4DUPq16_UPD + 81172U, // VLD4DUPq32 + 0U, // VLD4DUPq32EvenPseudo + 0U, // VLD4DUPq32OddPseudo + 16660U, // VLD4DUPq32_UPD + 81172U, // VLD4DUPq8 + 0U, // VLD4DUPq8EvenPseudo + 0U, // VLD4DUPq8OddPseudo + 16660U, // VLD4DUPq8_UPD + 189346060U, // VLD4LNd16 + 0U, // VLD4LNd16Pseudo + 0U, // VLD4LNd16Pseudo_UPD + 284U, // VLD4LNd16_UPD + 189346060U, // VLD4LNd32 + 0U, // VLD4LNd32Pseudo + 0U, // VLD4LNd32Pseudo_UPD + 284U, // VLD4LNd32_UPD + 189346060U, // VLD4LNd8 + 0U, // VLD4LNd8Pseudo + 0U, // VLD4LNd8Pseudo_UPD + 284U, // VLD4LNd8_UPD + 189346060U, // VLD4LNq16 + 0U, // VLD4LNq16Pseudo + 0U, // VLD4LNq16Pseudo_UPD + 284U, // VLD4LNq16_UPD + 189346060U, // VLD4LNq32 + 0U, // VLD4LNq32Pseudo + 0U, // VLD4LNq32Pseudo_UPD + 284U, // VLD4LNq32_UPD + 572522496U, // VLD4d16 + 0U, // VLD4d16Pseudo + 0U, // VLD4d16Pseudo_UPD + 1646264320U, // VLD4d16_UPD + 572522496U, // VLD4d32 + 0U, // VLD4d32Pseudo + 0U, // VLD4d32Pseudo_UPD + 1646264320U, // VLD4d32_UPD + 572522496U, // VLD4d8 + 0U, // VLD4d8Pseudo + 0U, // VLD4d8Pseudo_UPD + 1646264320U, // VLD4d8_UPD + 572522496U, // VLD4q16 + 0U, // VLD4q16Pseudo_UPD + 1646264320U, // VLD4q16_UPD + 0U, // VLD4q16oddPseudo + 0U, // VLD4q16oddPseudo_UPD + 572522496U, // VLD4q32 + 0U, // VLD4q32Pseudo_UPD + 1646264320U, // VLD4q32_UPD + 0U, // VLD4q32oddPseudo + 0U, // VLD4q32oddPseudo_UPD + 572522496U, // VLD4q8 + 0U, // VLD4q8Pseudo_UPD + 1646264320U, // VLD4q8_UPD + 0U, // VLD4q8oddPseudo + 0U, // VLD4q8oddPseudo_UPD + 33U, // VLDMDDB_UPD + 1136U, // VLDMDIA + 33U, // VLDMDIA_UPD + 0U, // VLDMQIA + 33U, // VLDMSDB_UPD + 1136U, // VLDMSIA + 33U, // VLDMSIA_UPD + 288U, // VLDRD + 296U, // VLDRH + 288U, // VLDRS + 0U, // VLLDM + 0U, // VLSTM + 1112U, // VMAXNMD + 1112U, // VMAXNMH + 1112U, // VMAXNMNDf + 1112U, // VMAXNMNDh + 1112U, // VMAXNMNQf + 1112U, // VMAXNMNQh + 1112U, // VMAXNMS + 70705U, // VMAXfd + 70705U, // VMAXfq + 70705U, // VMAXhd + 70705U, // VMAXhq + 1112U, // VMAXsv16i8 + 1112U, // VMAXsv2i32 + 1112U, // VMAXsv4i16 + 1112U, // VMAXsv4i32 + 1112U, // VMAXsv8i16 + 1112U, // VMAXsv8i8 + 1112U, // VMAXuv16i8 + 1112U, // VMAXuv2i32 + 1112U, // VMAXuv4i16 + 1112U, // VMAXuv4i32 + 1112U, // VMAXuv8i16 + 1112U, // VMAXuv8i8 + 1112U, // VMINNMD + 1112U, // VMINNMH + 1112U, // VMINNMNDf + 1112U, // VMINNMNDh + 1112U, // VMINNMNQf + 1112U, // VMINNMNQh + 1112U, // VMINNMS + 70705U, // VMINfd + 70705U, // VMINfq + 70705U, // VMINhd + 70705U, // VMINhq + 1112U, // VMINsv16i8 + 1112U, // VMINsv2i32 + 1112U, // VMINsv4i16 + 1112U, // VMINsv4i32 + 1112U, // VMINsv8i16 + 1112U, // VMINsv8i8 + 1112U, // VMINuv16i8 + 1112U, // VMINuv2i32 + 1112U, // VMINuv4i16 + 1112U, // VMINuv4i32 + 1112U, // VMINuv8i16 + 1112U, // VMINuv8i8 + 68659U, // VMLAD + 68659U, // VMLAH + 73752U, // VMLALslsv2i32 + 73752U, // VMLALslsv4i16 + 73752U, // VMLALsluv2i32 + 73752U, // VMLALsluv4i16 + 1048U, // VMLALsv2i64 + 1048U, // VMLALsv4i32 + 1048U, // VMLALsv8i16 + 1048U, // VMLALuv2i64 + 1048U, // VMLALuv4i32 + 1048U, // VMLALuv8i16 + 68659U, // VMLAS + 68659U, // VMLAfd + 68659U, // VMLAfq + 68659U, // VMLAhd + 68659U, // VMLAhq + 920627U, // VMLAslfd + 920627U, // VMLAslfq + 920627U, // VMLAslhd + 920627U, // VMLAslhq + 73752U, // VMLAslv2i32 + 73752U, // VMLAslv4i16 + 73752U, // VMLAslv4i32 + 73752U, // VMLAslv8i16 + 1048U, // VMLAv16i8 + 1048U, // VMLAv2i32 + 1048U, // VMLAv4i16 + 1048U, // VMLAv4i32 + 1048U, // VMLAv8i16 + 1048U, // VMLAv8i8 + 68659U, // VMLSD + 68659U, // VMLSH + 73752U, // VMLSLslsv2i32 + 73752U, // VMLSLslsv4i16 + 73752U, // VMLSLsluv2i32 + 73752U, // VMLSLsluv4i16 + 1048U, // VMLSLsv2i64 + 1048U, // VMLSLsv4i32 + 1048U, // VMLSLsv8i16 + 1048U, // VMLSLuv2i64 + 1048U, // VMLSLuv4i32 + 1048U, // VMLSLuv8i16 + 68659U, // VMLSS + 68659U, // VMLSfd + 68659U, // VMLSfq + 68659U, // VMLShd + 68659U, // VMLShq + 920627U, // VMLSslfd + 920627U, // VMLSslfq + 920627U, // VMLSslhd + 920627U, // VMLSslhq + 73752U, // VMLSslv2i32 + 73752U, // VMLSslv4i16 + 73752U, // VMLSslv4i32 + 73752U, // VMLSslv8i16 + 1048U, // VMLSv16i8 + 1048U, // VMLSv2i32 + 1048U, // VMLSv4i16 + 1048U, // VMLSv4i32 + 1048U, // VMLSv8i16 + 1048U, // VMLSv8i8 + 33U, // VMOVD + 0U, // VMOVDRR + 0U, // VMOVH + 33U, // VMOVHR + 0U, // VMOVLsv2i64 + 0U, // VMOVLsv4i32 + 0U, // VMOVLsv8i16 + 0U, // VMOVLuv2i64 + 0U, // VMOVLuv4i32 + 0U, // VMOVLuv8i16 + 0U, // VMOVNv2i32 + 0U, // VMOVNv4i16 + 0U, // VMOVNv8i8 + 33U, // VMOVRH + 0U, // VMOVRRD + 35651584U, // VMOVRRS + 1024U, // VMOVRS + 33U, // VMOVS + 1024U, // VMOVSR + 35651584U, // VMOVSRR + 0U, // VMOVv16i8 + 0U, // VMOVv1i64 + 1U, // VMOVv2f32 + 0U, // VMOVv2i32 + 0U, // VMOVv2i64 + 1U, // VMOVv4f32 + 0U, // VMOVv4i16 + 0U, // VMOVv4i32 + 0U, // VMOVv8i16 + 0U, // VMOVv8i8 + 4U, // VMRS + 5U, // VMRS_FPEXC + 5U, // VMRS_FPINST + 5U, // VMRS_FPINST2 + 5U, // VMRS_FPSID + 6U, // VMRS_MVFR0 + 6U, // VMRS_MVFR1 + 6U, // VMRS_MVFR2 + 0U, // VMSR + 0U, // VMSR_FPEXC + 0U, // VMSR_FPINST + 0U, // VMSR_FPINST2 + 0U, // VMSR_FPSID + 70705U, // VMULD + 70705U, // VMULH + 1112U, // VMULLp64 + 0U, // VMULLp8 + 17496U, // VMULLslsv2i32 + 17496U, // VMULLslsv4i16 + 17496U, // VMULLsluv2i32 + 17496U, // VMULLsluv4i16 + 1112U, // VMULLsv2i64 + 1112U, // VMULLsv4i32 + 1112U, // VMULLsv8i16 + 1112U, // VMULLuv2i64 + 1112U, // VMULLuv4i32 + 1112U, // VMULLuv8i16 + 70705U, // VMULS + 70705U, // VMULfd + 70705U, // VMULfq + 70705U, // VMULhd + 70705U, // VMULhq + 0U, // VMULpd + 0U, // VMULpq + 955441U, // VMULslfd + 955441U, // VMULslfq + 955441U, // VMULslhd + 955441U, // VMULslhq + 17496U, // VMULslv2i32 + 17496U, // VMULslv4i16 + 17496U, // VMULslv4i32 + 17496U, // VMULslv8i16 + 1112U, // VMULv16i8 + 1112U, // VMULv2i32 + 1112U, // VMULv4i16 + 1112U, // VMULv4i32 + 1112U, // VMULv8i16 + 1112U, // VMULv8i8 + 1024U, // VMVNd + 1024U, // VMVNq + 0U, // VMVNv2i32 + 0U, // VMVNv4i16 + 0U, // VMVNv4i32 + 0U, // VMVNv8i16 + 33U, // VNEGD + 33U, // VNEGH + 33U, // VNEGS + 33U, // VNEGf32q + 33U, // VNEGfd + 33U, // VNEGhd + 33U, // VNEGhq + 0U, // VNEGs16d + 0U, // VNEGs16q + 0U, // VNEGs32d + 0U, // VNEGs32q + 0U, // VNEGs8d + 0U, // VNEGs8q + 68659U, // VNMLAD + 68659U, // VNMLAH + 68659U, // VNMLAS + 68659U, // VNMLSD + 68659U, // VNMLSH + 68659U, // VNMLSS + 70705U, // VNMULD + 70705U, // VNMULH + 70705U, // VNMULS + 0U, // VORNd + 0U, // VORNq + 0U, // VORRd + 0U, // VORRiv2i32 + 0U, // VORRiv4i16 + 0U, // VORRiv4i32 + 0U, // VORRiv8i16 + 0U, // VORRq + 0U, // VPADALsv16i8 + 0U, // VPADALsv2i32 + 0U, // VPADALsv4i16 + 0U, // VPADALsv4i32 + 0U, // VPADALsv8i16 + 0U, // VPADALsv8i8 + 0U, // VPADALuv16i8 + 0U, // VPADALuv2i32 + 0U, // VPADALuv4i16 + 0U, // VPADALuv4i32 + 0U, // VPADALuv8i16 + 0U, // VPADALuv8i8 + 0U, // VPADDLsv16i8 + 0U, // VPADDLsv2i32 + 0U, // VPADDLsv4i16 + 0U, // VPADDLsv4i32 + 0U, // VPADDLsv8i16 + 0U, // VPADDLsv8i8 + 0U, // VPADDLuv16i8 + 0U, // VPADDLuv2i32 + 0U, // VPADDLuv4i16 + 0U, // VPADDLuv4i32 + 0U, // VPADDLuv8i16 + 0U, // VPADDLuv8i8 + 70705U, // VPADDf + 70705U, // VPADDh + 1112U, // VPADDi16 + 1112U, // VPADDi32 + 1112U, // VPADDi8 + 70705U, // VPMAXf + 70705U, // VPMAXh + 1112U, // VPMAXs16 + 1112U, // VPMAXs32 + 1112U, // VPMAXs8 + 1112U, // VPMAXu16 + 1112U, // VPMAXu32 + 1112U, // VPMAXu8 + 70705U, // VPMINf + 70705U, // VPMINh + 1112U, // VPMINs16 + 1112U, // VPMINs32 + 1112U, // VPMINs8 + 1112U, // VPMINu16 + 1112U, // VPMINu32 + 1112U, // VPMINu8 + 0U, // VQABSv16i8 + 0U, // VQABSv2i32 + 0U, // VQABSv4i16 + 0U, // VQABSv4i32 + 0U, // VQABSv8i16 + 0U, // VQABSv8i8 + 1112U, // VQADDsv16i8 + 1112U, // VQADDsv1i64 + 1112U, // VQADDsv2i32 + 1112U, // VQADDsv2i64 + 1112U, // VQADDsv4i16 + 1112U, // VQADDsv4i32 + 1112U, // VQADDsv8i16 + 1112U, // VQADDsv8i8 + 1112U, // VQADDuv16i8 + 1112U, // VQADDuv1i64 + 1112U, // VQADDuv2i32 + 1112U, // VQADDuv2i64 + 1112U, // VQADDuv4i16 + 1112U, // VQADDuv4i32 + 1112U, // VQADDuv8i16 + 1112U, // VQADDuv8i8 + 73752U, // VQDMLALslv2i32 + 73752U, // VQDMLALslv4i16 + 1048U, // VQDMLALv2i64 + 1048U, // VQDMLALv4i32 + 73752U, // VQDMLSLslv2i32 + 73752U, // VQDMLSLslv4i16 + 1048U, // VQDMLSLv2i64 + 1048U, // VQDMLSLv4i32 + 17496U, // VQDMULHslv2i32 + 17496U, // VQDMULHslv4i16 + 17496U, // VQDMULHslv4i32 + 17496U, // VQDMULHslv8i16 + 1112U, // VQDMULHv2i32 + 1112U, // VQDMULHv4i16 + 1112U, // VQDMULHv4i32 + 1112U, // VQDMULHv8i16 + 17496U, // VQDMULLslv2i32 + 17496U, // VQDMULLslv4i16 + 1112U, // VQDMULLv2i64 + 1112U, // VQDMULLv4i32 + 0U, // VQMOVNsuv2i32 + 0U, // VQMOVNsuv4i16 + 0U, // VQMOVNsuv8i8 + 0U, // VQMOVNsv2i32 + 0U, // VQMOVNsv4i16 + 0U, // VQMOVNsv8i8 + 0U, // VQMOVNuv2i32 + 0U, // VQMOVNuv4i16 + 0U, // VQMOVNuv8i8 + 0U, // VQNEGv16i8 + 0U, // VQNEGv2i32 + 0U, // VQNEGv4i16 + 0U, // VQNEGv4i32 + 0U, // VQNEGv8i16 + 0U, // VQNEGv8i8 + 73752U, // VQRDMLAHslv2i32 + 73752U, // VQRDMLAHslv4i16 + 73752U, // VQRDMLAHslv4i32 + 73752U, // VQRDMLAHslv8i16 + 1048U, // VQRDMLAHv2i32 + 1048U, // VQRDMLAHv4i16 + 1048U, // VQRDMLAHv4i32 + 1048U, // VQRDMLAHv8i16 + 73752U, // VQRDMLSHslv2i32 + 73752U, // VQRDMLSHslv4i16 + 73752U, // VQRDMLSHslv4i32 + 73752U, // VQRDMLSHslv8i16 + 1048U, // VQRDMLSHv2i32 + 1048U, // VQRDMLSHv4i16 + 1048U, // VQRDMLSHv4i32 + 1048U, // VQRDMLSHv8i16 + 17496U, // VQRDMULHslv2i32 + 17496U, // VQRDMULHslv4i16 + 17496U, // VQRDMULHslv4i32 + 17496U, // VQRDMULHslv8i16 + 1112U, // VQRDMULHv2i32 + 1112U, // VQRDMULHv4i16 + 1112U, // VQRDMULHv4i32 + 1112U, // VQRDMULHv8i16 + 1112U, // VQRSHLsv16i8 + 1112U, // VQRSHLsv1i64 + 1112U, // VQRSHLsv2i32 + 1112U, // VQRSHLsv2i64 + 1112U, // VQRSHLsv4i16 + 1112U, // VQRSHLsv4i32 + 1112U, // VQRSHLsv8i16 + 1112U, // VQRSHLsv8i8 + 1112U, // VQRSHLuv16i8 + 1112U, // VQRSHLuv1i64 + 1112U, // VQRSHLuv2i32 + 1112U, // VQRSHLuv2i64 + 1112U, // VQRSHLuv4i16 + 1112U, // VQRSHLuv4i32 + 1112U, // VQRSHLuv8i16 + 1112U, // VQRSHLuv8i8 + 1112U, // VQRSHRNsv2i32 + 1112U, // VQRSHRNsv4i16 + 1112U, // VQRSHRNsv8i8 + 1112U, // VQRSHRNuv2i32 + 1112U, // VQRSHRNuv4i16 + 1112U, // VQRSHRNuv8i8 + 1112U, // VQRSHRUNv2i32 + 1112U, // VQRSHRUNv4i16 + 1112U, // VQRSHRUNv8i8 + 1112U, // VQSHLsiv16i8 + 1112U, // VQSHLsiv1i64 + 1112U, // VQSHLsiv2i32 + 1112U, // VQSHLsiv2i64 + 1112U, // VQSHLsiv4i16 + 1112U, // VQSHLsiv4i32 + 1112U, // VQSHLsiv8i16 + 1112U, // VQSHLsiv8i8 + 1112U, // VQSHLsuv16i8 + 1112U, // VQSHLsuv1i64 + 1112U, // VQSHLsuv2i32 + 1112U, // VQSHLsuv2i64 + 1112U, // VQSHLsuv4i16 + 1112U, // VQSHLsuv4i32 + 1112U, // VQSHLsuv8i16 + 1112U, // VQSHLsuv8i8 + 1112U, // VQSHLsv16i8 + 1112U, // VQSHLsv1i64 + 1112U, // VQSHLsv2i32 + 1112U, // VQSHLsv2i64 + 1112U, // VQSHLsv4i16 + 1112U, // VQSHLsv4i32 + 1112U, // VQSHLsv8i16 + 1112U, // VQSHLsv8i8 + 1112U, // VQSHLuiv16i8 + 1112U, // VQSHLuiv1i64 + 1112U, // VQSHLuiv2i32 + 1112U, // VQSHLuiv2i64 + 1112U, // VQSHLuiv4i16 + 1112U, // VQSHLuiv4i32 + 1112U, // VQSHLuiv8i16 + 1112U, // VQSHLuiv8i8 + 1112U, // VQSHLuv16i8 + 1112U, // VQSHLuv1i64 + 1112U, // VQSHLuv2i32 + 1112U, // VQSHLuv2i64 + 1112U, // VQSHLuv4i16 + 1112U, // VQSHLuv4i32 + 1112U, // VQSHLuv8i16 + 1112U, // VQSHLuv8i8 + 1112U, // VQSHRNsv2i32 + 1112U, // VQSHRNsv4i16 + 1112U, // VQSHRNsv8i8 + 1112U, // VQSHRNuv2i32 + 1112U, // VQSHRNuv4i16 + 1112U, // VQSHRNuv8i8 + 1112U, // VQSHRUNv2i32 + 1112U, // VQSHRUNv4i16 + 1112U, // VQSHRUNv8i8 + 1112U, // VQSUBsv16i8 + 1112U, // VQSUBsv1i64 + 1112U, // VQSUBsv2i32 + 1112U, // VQSUBsv2i64 + 1112U, // VQSUBsv4i16 + 1112U, // VQSUBsv4i32 + 1112U, // VQSUBsv8i16 + 1112U, // VQSUBsv8i8 + 1112U, // VQSUBuv16i8 + 1112U, // VQSUBuv1i64 + 1112U, // VQSUBuv2i32 + 1112U, // VQSUBuv2i64 + 1112U, // VQSUBuv4i16 + 1112U, // VQSUBuv4i32 + 1112U, // VQSUBuv8i16 + 1112U, // VQSUBuv8i8 + 1112U, // VRADDHNv2i32 + 1112U, // VRADDHNv4i16 + 1112U, // VRADDHNv8i8 + 0U, // VRECPEd + 33U, // VRECPEfd + 33U, // VRECPEfq + 33U, // VRECPEhd + 33U, // VRECPEhq + 0U, // VRECPEq + 70705U, // VRECPSfd + 70705U, // VRECPSfq + 70705U, // VRECPShd + 70705U, // VRECPShq + 1024U, // VREV16d8 + 1024U, // VREV16q8 + 1024U, // VREV32d16 + 1024U, // VREV32d8 + 1024U, // VREV32q16 + 1024U, // VREV32q8 + 1024U, // VREV64d16 + 1024U, // VREV64d32 + 1024U, // VREV64d8 + 1024U, // VREV64q16 + 1024U, // VREV64q32 + 1024U, // VREV64q8 + 1112U, // VRHADDsv16i8 + 1112U, // VRHADDsv2i32 + 1112U, // VRHADDsv4i16 + 1112U, // VRHADDsv4i32 + 1112U, // VRHADDsv8i16 + 1112U, // VRHADDsv8i8 + 1112U, // VRHADDuv16i8 + 1112U, // VRHADDuv2i32 + 1112U, // VRHADDuv4i16 + 1112U, // VRHADDuv4i32 + 1112U, // VRHADDuv8i16 + 1112U, // VRHADDuv8i8 + 0U, // VRINTAD + 0U, // VRINTAH + 0U, // VRINTANDf + 0U, // VRINTANDh + 0U, // VRINTANQf + 0U, // VRINTANQh + 0U, // VRINTAS + 0U, // VRINTMD + 0U, // VRINTMH + 0U, // VRINTMNDf + 0U, // VRINTMNDh + 0U, // VRINTMNQf + 0U, // VRINTMNQh + 0U, // VRINTMS + 0U, // VRINTND + 0U, // VRINTNH + 0U, // VRINTNNDf + 0U, // VRINTNNDh + 0U, // VRINTNNQf + 0U, // VRINTNNQh + 0U, // VRINTNS + 0U, // VRINTPD + 0U, // VRINTPH + 0U, // VRINTPNDf + 0U, // VRINTPNDh + 0U, // VRINTPNQf + 0U, // VRINTPNQh + 0U, // VRINTPS + 33U, // VRINTRD + 33U, // VRINTRH + 33U, // VRINTRS + 33U, // VRINTXD + 33U, // VRINTXH + 0U, // VRINTXNDf + 0U, // VRINTXNDh + 0U, // VRINTXNQf + 0U, // VRINTXNQh + 33U, // VRINTXS + 33U, // VRINTZD + 33U, // VRINTZH + 0U, // VRINTZNDf + 0U, // VRINTZNDh + 0U, // VRINTZNQf + 0U, // VRINTZNQh + 33U, // VRINTZS + 1112U, // VRSHLsv16i8 + 1112U, // VRSHLsv1i64 + 1112U, // VRSHLsv2i32 + 1112U, // VRSHLsv2i64 + 1112U, // VRSHLsv4i16 + 1112U, // VRSHLsv4i32 + 1112U, // VRSHLsv8i16 + 1112U, // VRSHLsv8i8 + 1112U, // VRSHLuv16i8 + 1112U, // VRSHLuv1i64 + 1112U, // VRSHLuv2i32 + 1112U, // VRSHLuv2i64 + 1112U, // VRSHLuv4i16 + 1112U, // VRSHLuv4i32 + 1112U, // VRSHLuv8i16 + 1112U, // VRSHLuv8i8 + 1112U, // VRSHRNv2i32 + 1112U, // VRSHRNv4i16 + 1112U, // VRSHRNv8i8 + 1112U, // VRSHRsv16i8 + 1112U, // VRSHRsv1i64 + 1112U, // VRSHRsv2i32 + 1112U, // VRSHRsv2i64 + 1112U, // VRSHRsv4i16 + 1112U, // VRSHRsv4i32 + 1112U, // VRSHRsv8i16 + 1112U, // VRSHRsv8i8 + 1112U, // VRSHRuv16i8 + 1112U, // VRSHRuv1i64 + 1112U, // VRSHRuv2i32 + 1112U, // VRSHRuv2i64 + 1112U, // VRSHRuv4i16 + 1112U, // VRSHRuv4i32 + 1112U, // VRSHRuv8i16 + 1112U, // VRSHRuv8i8 + 0U, // VRSQRTEd + 33U, // VRSQRTEfd + 33U, // VRSQRTEfq + 33U, // VRSQRTEhd + 33U, // VRSQRTEhq + 0U, // VRSQRTEq + 70705U, // VRSQRTSfd + 70705U, // VRSQRTSfq + 70705U, // VRSQRTShd + 70705U, // VRSQRTShq + 1048U, // VRSRAsv16i8 + 1048U, // VRSRAsv1i64 + 1048U, // VRSRAsv2i32 + 1048U, // VRSRAsv2i64 + 1048U, // VRSRAsv4i16 + 1048U, // VRSRAsv4i32 + 1048U, // VRSRAsv8i16 + 1048U, // VRSRAsv8i8 + 1048U, // VRSRAuv16i8 + 1048U, // VRSRAuv1i64 + 1048U, // VRSRAuv2i32 + 1048U, // VRSRAuv2i64 + 1048U, // VRSRAuv4i16 + 1048U, // VRSRAuv4i32 + 1048U, // VRSRAuv8i16 + 1048U, // VRSRAuv8i8 + 1112U, // VRSUBHNv2i32 + 1112U, // VRSUBHNv4i16 + 1112U, // VRSUBHNv8i8 + 0U, // VSDOTD + 0U, // VSDOTDI + 0U, // VSDOTQ + 0U, // VSDOTQI + 1112U, // VSELEQD + 1112U, // VSELEQH + 1112U, // VSELEQS + 1112U, // VSELGED + 1112U, // VSELGEH + 1112U, // VSELGES + 1112U, // VSELGTD + 1112U, // VSELGTH + 1112U, // VSELGTS + 1112U, // VSELVSD + 1112U, // VSELVSH + 1112U, // VSELVSS + 6U, // VSETLNi16 + 6U, // VSETLNi32 + 6U, // VSETLNi8 + 1112U, // VSHLLi16 + 1112U, // VSHLLi32 + 1112U, // VSHLLi8 + 1112U, // VSHLLsv2i64 + 1112U, // VSHLLsv4i32 + 1112U, // VSHLLsv8i16 + 1112U, // VSHLLuv2i64 + 1112U, // VSHLLuv4i32 + 1112U, // VSHLLuv8i16 + 1112U, // VSHLiv16i8 + 1112U, // VSHLiv1i64 + 1112U, // VSHLiv2i32 + 1112U, // VSHLiv2i64 + 1112U, // VSHLiv4i16 + 1112U, // VSHLiv4i32 + 1112U, // VSHLiv8i16 + 1112U, // VSHLiv8i8 + 1112U, // VSHLsv16i8 + 1112U, // VSHLsv1i64 + 1112U, // VSHLsv2i32 + 1112U, // VSHLsv2i64 + 1112U, // VSHLsv4i16 + 1112U, // VSHLsv4i32 + 1112U, // VSHLsv8i16 + 1112U, // VSHLsv8i8 + 1112U, // VSHLuv16i8 + 1112U, // VSHLuv1i64 + 1112U, // VSHLuv2i32 + 1112U, // VSHLuv2i64 + 1112U, // VSHLuv4i16 + 1112U, // VSHLuv4i32 + 1112U, // VSHLuv8i16 + 1112U, // VSHLuv8i8 + 1112U, // VSHRNv2i32 + 1112U, // VSHRNv4i16 + 1112U, // VSHRNv8i8 + 1112U, // VSHRsv16i8 + 1112U, // VSHRsv1i64 + 1112U, // VSHRsv2i32 + 1112U, // VSHRsv2i64 + 1112U, // VSHRsv4i16 + 1112U, // VSHRsv4i32 + 1112U, // VSHRsv8i16 + 1112U, // VSHRsv8i8 + 1112U, // VSHRuv16i8 + 1112U, // VSHRuv1i64 + 1112U, // VSHRuv2i32 + 1112U, // VSHRuv2i64 + 1112U, // VSHRuv4i16 + 1112U, // VSHRuv4i32 + 1112U, // VSHRuv8i16 + 1112U, // VSHRuv8i8 + 0U, // VSHTOD + 7U, // VSHTOH + 0U, // VSHTOS + 0U, // VSITOD + 0U, // VSITOH + 0U, // VSITOS + 589912U, // VSLIv16i8 + 589912U, // VSLIv1i64 + 589912U, // VSLIv2i32 + 589912U, // VSLIv2i64 + 589912U, // VSLIv4i16 + 589912U, // VSLIv4i32 + 589912U, // VSLIv8i16 + 589912U, // VSLIv8i8 + 7U, // VSLTOD + 7U, // VSLTOH + 7U, // VSLTOS + 33U, // VSQRTD + 33U, // VSQRTH + 33U, // VSQRTS + 1048U, // VSRAsv16i8 + 1048U, // VSRAsv1i64 + 1048U, // VSRAsv2i32 + 1048U, // VSRAsv2i64 + 1048U, // VSRAsv4i16 + 1048U, // VSRAsv4i32 + 1048U, // VSRAsv8i16 + 1048U, // VSRAsv8i8 + 1048U, // VSRAuv16i8 + 1048U, // VSRAuv1i64 + 1048U, // VSRAuv2i32 + 1048U, // VSRAuv2i64 + 1048U, // VSRAuv4i16 + 1048U, // VSRAuv4i32 + 1048U, // VSRAuv8i16 + 1048U, // VSRAuv8i8 + 589912U, // VSRIv16i8 + 589912U, // VSRIv1i64 + 589912U, // VSRIv2i32 + 589912U, // VSRIv2i64 + 589912U, // VSRIv4i16 + 589912U, // VSRIv4i32 + 589912U, // VSRIv8i16 + 589912U, // VSRIv8i8 + 308U, // VST1LNd16 + 23768380U, // VST1LNd16_UPD + 308U, // VST1LNd32 + 23768380U, // VST1LNd32_UPD + 308U, // VST1LNd8 + 23768380U, // VST1LNd8_UPD + 0U, // VST1LNq16Pseudo + 0U, // VST1LNq16Pseudo_UPD + 0U, // VST1LNq32Pseudo + 0U, // VST1LNq32Pseudo_UPD + 0U, // VST1LNq8Pseudo + 0U, // VST1LNq8Pseudo_UPD + 0U, // VST1d16 + 0U, // VST1d16Q + 0U, // VST1d16QPseudo + 0U, // VST1d16Qwb_fixed + 0U, // VST1d16Qwb_register + 0U, // VST1d16T + 0U, // VST1d16TPseudo + 0U, // VST1d16Twb_fixed + 0U, // VST1d16Twb_register + 0U, // VST1d16wb_fixed + 0U, // VST1d16wb_register + 0U, // VST1d32 + 0U, // VST1d32Q + 0U, // VST1d32QPseudo + 0U, // VST1d32Qwb_fixed + 0U, // VST1d32Qwb_register + 0U, // VST1d32T + 0U, // VST1d32TPseudo + 0U, // VST1d32Twb_fixed + 0U, // VST1d32Twb_register + 0U, // VST1d32wb_fixed + 0U, // VST1d32wb_register + 0U, // VST1d64 + 0U, // VST1d64Q + 0U, // VST1d64QPseudo + 0U, // VST1d64QPseudoWB_fixed + 0U, // VST1d64QPseudoWB_register + 0U, // VST1d64Qwb_fixed + 0U, // VST1d64Qwb_register + 0U, // VST1d64T + 0U, // VST1d64TPseudo + 0U, // VST1d64TPseudoWB_fixed + 0U, // VST1d64TPseudoWB_register + 0U, // VST1d64Twb_fixed + 0U, // VST1d64Twb_register + 0U, // VST1d64wb_fixed + 0U, // VST1d64wb_register + 0U, // VST1d8 + 0U, // VST1d8Q + 0U, // VST1d8QPseudo + 0U, // VST1d8Qwb_fixed + 0U, // VST1d8Qwb_register + 0U, // VST1d8T + 0U, // VST1d8TPseudo + 0U, // VST1d8Twb_fixed + 0U, // VST1d8Twb_register + 0U, // VST1d8wb_fixed + 0U, // VST1d8wb_register + 0U, // VST1q16 + 0U, // VST1q16HighQPseudo + 0U, // VST1q16HighTPseudo + 0U, // VST1q16LowQPseudo_UPD + 0U, // VST1q16LowTPseudo_UPD + 0U, // VST1q16wb_fixed + 0U, // VST1q16wb_register + 0U, // VST1q32 + 0U, // VST1q32HighQPseudo + 0U, // VST1q32HighTPseudo + 0U, // VST1q32LowQPseudo_UPD + 0U, // VST1q32LowTPseudo_UPD + 0U, // VST1q32wb_fixed + 0U, // VST1q32wb_register + 0U, // VST1q64 + 0U, // VST1q64HighQPseudo + 0U, // VST1q64HighTPseudo + 0U, // VST1q64LowQPseudo_UPD + 0U, // VST1q64LowTPseudo_UPD + 0U, // VST1q64wb_fixed + 0U, // VST1q64wb_register + 0U, // VST1q8 + 0U, // VST1q8HighQPseudo + 0U, // VST1q8HighTPseudo + 0U, // VST1q8LowQPseudo_UPD + 0U, // VST1q8LowTPseudo_UPD + 0U, // VST1q8wb_fixed + 0U, // VST1q8wb_register + 222900460U, // VST2LNd16 + 0U, // VST2LNd16Pseudo + 0U, // VST2LNd16Pseudo_UPD + 995572U, // VST2LNd16_UPD + 222900460U, // VST2LNd32 + 0U, // VST2LNd32Pseudo + 0U, // VST2LNd32Pseudo_UPD + 995572U, // VST2LNd32_UPD + 222900460U, // VST2LNd8 + 0U, // VST2LNd8Pseudo + 0U, // VST2LNd8Pseudo_UPD + 995572U, // VST2LNd8_UPD + 222900460U, // VST2LNq16 + 0U, // VST2LNq16Pseudo + 0U, // VST2LNq16Pseudo_UPD + 995572U, // VST2LNq16_UPD + 222900460U, // VST2LNq32 + 0U, // VST2LNq32Pseudo + 0U, // VST2LNq32Pseudo_UPD + 995572U, // VST2LNq32_UPD + 0U, // VST2b16 + 0U, // VST2b16wb_fixed + 0U, // VST2b16wb_register + 0U, // VST2b32 + 0U, // VST2b32wb_fixed + 0U, // VST2b32wb_register + 0U, // VST2b8 + 0U, // VST2b8wb_fixed + 0U, // VST2b8wb_register + 0U, // VST2d16 + 0U, // VST2d16wb_fixed + 0U, // VST2d16wb_register + 0U, // VST2d32 + 0U, // VST2d32wb_fixed + 0U, // VST2d32wb_register + 0U, // VST2d8 + 0U, // VST2d8wb_fixed + 0U, // VST2d8wb_register + 0U, // VST2q16 + 0U, // VST2q16Pseudo + 0U, // VST2q16PseudoWB_fixed + 0U, // VST2q16PseudoWB_register + 0U, // VST2q16wb_fixed + 0U, // VST2q16wb_register + 0U, // VST2q32 + 0U, // VST2q32Pseudo + 0U, // VST2q32PseudoWB_fixed + 0U, // VST2q32PseudoWB_register + 0U, // VST2q32wb_fixed + 0U, // VST2q32wb_register + 0U, // VST2q8 + 0U, // VST2q8Pseudo + 0U, // VST2q8PseudoWB_fixed + 0U, // VST2q8PseudoWB_register + 0U, // VST2q8wb_fixed + 0U, // VST2q8wb_register + 256454972U, // VST3LNd16 + 0U, // VST3LNd16Pseudo + 0U, // VST3LNd16Pseudo_UPD + 324U, // VST3LNd16_UPD + 256454972U, // VST3LNd32 + 0U, // VST3LNd32Pseudo + 0U, // VST3LNd32Pseudo_UPD + 324U, // VST3LNd32_UPD + 256454972U, // VST3LNd8 + 0U, // VST3LNd8Pseudo + 0U, // VST3LNd8Pseudo_UPD + 324U, // VST3LNd8_UPD + 256454972U, // VST3LNq16 + 0U, // VST3LNq16Pseudo + 0U, // VST3LNq16Pseudo_UPD + 324U, // VST3LNq16_UPD + 256454972U, // VST3LNq32 + 0U, // VST3LNq32Pseudo + 0U, // VST3LNq32Pseudo_UPD + 324U, // VST3LNq32_UPD + 287342616U, // VST3d16 + 0U, // VST3d16Pseudo + 0U, // VST3d16Pseudo_UPD + 18760U, // VST3d16_UPD + 287342616U, // VST3d32 + 0U, // VST3d32Pseudo + 0U, // VST3d32Pseudo_UPD + 18760U, // VST3d32_UPD + 287342616U, // VST3d8 + 0U, // VST3d8Pseudo + 0U, // VST3d8Pseudo_UPD + 18760U, // VST3d8_UPD + 287342616U, // VST3q16 + 0U, // VST3q16Pseudo_UPD + 18760U, // VST3q16_UPD + 0U, // VST3q16oddPseudo + 0U, // VST3q16oddPseudo_UPD + 287342616U, // VST3q32 + 0U, // VST3q32Pseudo_UPD + 18760U, // VST3q32_UPD + 0U, // VST3q32oddPseudo + 0U, // VST3q32oddPseudo_UPD + 287342616U, // VST3q8 + 0U, // VST3q8Pseudo_UPD + 18760U, // VST3q8_UPD + 0U, // VST3q8oddPseudo + 0U, // VST3q8oddPseudo_UPD + 323563764U, // VST4LNd16 + 0U, // VST4LNd16Pseudo + 0U, // VST4LNd16Pseudo_UPD + 19708U, // VST4LNd16_UPD + 323563764U, // VST4LNd32 + 0U, // VST4LNd32Pseudo + 0U, // VST4LNd32Pseudo_UPD + 19708U, // VST4LNd32_UPD + 323563764U, // VST4LNd8 + 0U, // VST4LNd8Pseudo + 0U, // VST4LNd8Pseudo_UPD + 19708U, // VST4LNd8_UPD + 323563764U, // VST4LNq16 + 0U, // VST4LNq16Pseudo + 0U, // VST4LNq16Pseudo_UPD + 19708U, // VST4LNq16_UPD + 323563764U, // VST4LNq32 + 0U, // VST4LNq32Pseudo + 0U, // VST4LNq32Pseudo_UPD + 19708U, // VST4LNq32_UPD + 337674264U, // VST4d16 + 0U, // VST4d16Pseudo + 0U, // VST4d16Pseudo_UPD + 1016136U, // VST4d16_UPD + 337674264U, // VST4d32 + 0U, // VST4d32Pseudo + 0U, // VST4d32Pseudo_UPD + 1016136U, // VST4d32_UPD + 337674264U, // VST4d8 + 0U, // VST4d8Pseudo + 0U, // VST4d8Pseudo_UPD + 1016136U, // VST4d8_UPD + 337674264U, // VST4q16 + 0U, // VST4q16Pseudo_UPD + 1016136U, // VST4q16_UPD + 0U, // VST4q16oddPseudo + 0U, // VST4q16oddPseudo_UPD + 337674264U, // VST4q32 + 0U, // VST4q32Pseudo_UPD + 1016136U, // VST4q32_UPD + 0U, // VST4q32oddPseudo + 0U, // VST4q32oddPseudo_UPD + 337674264U, // VST4q8 + 0U, // VST4q8Pseudo_UPD + 1016136U, // VST4q8_UPD + 0U, // VST4q8oddPseudo + 0U, // VST4q8oddPseudo_UPD + 33U, // VSTMDDB_UPD + 1136U, // VSTMDIA + 33U, // VSTMDIA_UPD + 0U, // VSTMQIA + 33U, // VSTMSDB_UPD + 1136U, // VSTMSIA + 33U, // VSTMSIA_UPD + 288U, // VSTRD + 296U, // VSTRH + 288U, // VSTRS + 70705U, // VSUBD + 70705U, // VSUBH + 1112U, // VSUBHNv2i32 + 1112U, // VSUBHNv4i16 + 1112U, // VSUBHNv8i8 + 1112U, // VSUBLsv2i64 + 1112U, // VSUBLsv4i32 + 1112U, // VSUBLsv8i16 + 1112U, // VSUBLuv2i64 + 1112U, // VSUBLuv4i32 + 1112U, // VSUBLuv8i16 + 70705U, // VSUBS + 1112U, // VSUBWsv2i64 + 1112U, // VSUBWsv4i32 + 1112U, // VSUBWsv8i16 + 1112U, // VSUBWuv2i64 + 1112U, // VSUBWuv4i32 + 1112U, // VSUBWuv8i16 + 70705U, // VSUBfd + 70705U, // VSUBfq + 70705U, // VSUBhd + 70705U, // VSUBhq + 1112U, // VSUBv16i8 + 1112U, // VSUBv1i64 + 1112U, // VSUBv2i32 + 1112U, // VSUBv2i64 + 1112U, // VSUBv4i16 + 1112U, // VSUBv4i32 + 1112U, // VSUBv8i16 + 1112U, // VSUBv8i8 + 1024U, // VSWPd + 1024U, // VSWPq + 336U, // VTBL1 + 344U, // VTBL2 + 352U, // VTBL3 + 0U, // VTBL3Pseudo + 360U, // VTBL4 + 0U, // VTBL4Pseudo + 368U, // VTBX1 + 376U, // VTBX2 + 384U, // VTBX3 + 0U, // VTBX3Pseudo + 392U, // VTBX4 + 0U, // VTBX4Pseudo + 0U, // VTOSHD + 7U, // VTOSHH + 0U, // VTOSHS + 0U, // VTOSIRD + 0U, // VTOSIRH + 0U, // VTOSIRS + 0U, // VTOSIZD + 0U, // VTOSIZH + 0U, // VTOSIZS + 7U, // VTOSLD + 7U, // VTOSLH + 7U, // VTOSLS + 0U, // VTOUHD + 7U, // VTOUHH + 0U, // VTOUHS + 0U, // VTOUIRD + 0U, // VTOUIRH + 0U, // VTOUIRS + 0U, // VTOUIZD + 0U, // VTOUIZH + 0U, // VTOUIZS + 7U, // VTOULD + 7U, // VTOULH + 7U, // VTOULS + 1024U, // VTRNd16 + 1024U, // VTRNd32 + 1024U, // VTRNd8 + 1024U, // VTRNq16 + 1024U, // VTRNq32 + 1024U, // VTRNq8 + 0U, // VTSTv16i8 + 0U, // VTSTv2i32 + 0U, // VTSTv4i16 + 0U, // VTSTv4i32 + 0U, // VTSTv8i16 + 0U, // VTSTv8i8 + 0U, // VUDOTD + 0U, // VUDOTDI + 0U, // VUDOTQ + 0U, // VUDOTQI + 0U, // VUHTOD + 7U, // VUHTOH + 0U, // VUHTOS + 0U, // VUITOD + 0U, // VUITOH + 0U, // VUITOS + 7U, // VULTOD + 7U, // VULTOH + 7U, // VULTOS + 1024U, // VUZPd16 + 1024U, // VUZPd8 + 1024U, // VUZPq16 + 1024U, // VUZPq32 + 1024U, // VUZPq8 + 1024U, // VZIPd16 + 1024U, // VZIPd8 + 1024U, // VZIPq16 + 1024U, // VZIPq32 + 1024U, // VZIPq8 + 20592U, // sysLDMDA + 401U, // sysLDMDA_UPD + 20592U, // sysLDMDB + 401U, // sysLDMDB_UPD + 20592U, // sysLDMIA + 401U, // sysLDMIA_UPD + 20592U, // sysLDMIB + 401U, // sysLDMIB_UPD + 20592U, // sysSTMDA + 401U, // sysSTMDA_UPD + 20592U, // sysSTMDB + 401U, // sysSTMDB_UPD + 20592U, // sysSTMIA + 401U, // sysSTMIA_UPD + 20592U, // sysSTMIB + 401U, // sysSTMIB_UPD + 0U, // t2ADCri + 0U, // t2ADCrr + 1048576U, // t2ADCrs + 0U, // t2ADDri + 0U, // t2ADDri12 + 0U, // t2ADDrr + 1048576U, // t2ADDrs + 72U, // t2ADR + 0U, // t2ANDri + 0U, // t2ANDrr + 1048576U, // t2ANDrs + 1081344U, // t2ASRri + 0U, // t2ASRrr + 0U, // t2B + 80U, // t2BFC + 163928U, // t2BFI + 0U, // t2BICri + 0U, // t2BICrr + 1048576U, // t2BICrs + 0U, // t2BXJ + 0U, // t2Bcc + 4145U, // t2CDP + 4145U, // t2CDP2 + 0U, // t2CLREX + 1024U, // t2CLZ + 1024U, // t2CMNri + 1024U, // t2CMNzrr + 56U, // t2CMNzrs + 1024U, // t2CMPri + 1024U, // t2CMPrr + 56U, // t2CMPrs + 0U, // t2CPS1p + 0U, // t2CPS2p + 1112U, // t2CPS3p + 1112U, // t2CRC32B + 1112U, // t2CRC32CB + 1112U, // t2CRC32CH + 1112U, // t2CRC32CW + 1112U, // t2CRC32H + 1112U, // t2CRC32W + 0U, // t2DBG + 0U, // t2DCPS1 + 0U, // t2DCPS2 + 0U, // t2DCPS3 + 0U, // t2DMB + 0U, // t2DSB + 0U, // t2EORri + 0U, // t2EORrr + 1048576U, // t2EORrs + 0U, // t2HINT + 0U, // t2HVC + 0U, // t2ISB + 0U, // t2IT + 0U, // t2Int_eh_sjlj_setjmp + 0U, // t2Int_eh_sjlj_setjmp_nofp + 8U, // t2LDA + 8U, // t2LDAB + 8U, // t2LDAEX + 8U, // t2LDAEXB + 557056U, // t2LDAEXD + 8U, // t2LDAEXH + 8U, // t2LDAH + 122U, // t2LDC2L_OFFSET + 196738U, // t2LDC2L_OPTION + 229506U, // t2LDC2L_POST + 138U, // t2LDC2L_PRE + 122U, // t2LDC2_OFFSET + 196738U, // t2LDC2_OPTION + 229506U, // t2LDC2_POST + 138U, // t2LDC2_PRE + 122U, // t2LDCL_OFFSET + 196738U, // t2LDCL_OPTION + 229506U, // t2LDCL_POST + 138U, // t2LDCL_PRE + 122U, // t2LDC_OFFSET + 196738U, // t2LDC_OPTION + 229506U, // t2LDC_POST + 138U, // t2LDC_PRE + 1136U, // t2LDMDB + 33U, // t2LDMDB_UPD + 1136U, // t2LDMIA + 33U, // t2LDMIA_UPD + 408U, // t2LDRBT + 21632U, // t2LDRB_POST + 416U, // t2LDRB_PRE + 160U, // t2LDRBi12 + 408U, // t2LDRBi8 + 424U, // t2LDRBpci + 432U, // t2LDRBs + 25493504U, // t2LDRD_POST + 1114112U, // t2LDRD_PRE + 1146880U, // t2LDRDi8 + 440U, // t2LDREX + 8U, // t2LDREXB + 557056U, // t2LDREXD + 8U, // t2LDREXH + 408U, // t2LDRHT + 21632U, // t2LDRH_POST + 416U, // t2LDRH_PRE + 160U, // t2LDRHi12 + 408U, // t2LDRHi8 + 424U, // t2LDRHpci + 432U, // t2LDRHs + 408U, // t2LDRSBT + 21632U, // t2LDRSB_POST + 416U, // t2LDRSB_PRE + 160U, // t2LDRSBi12 + 408U, // t2LDRSBi8 + 424U, // t2LDRSBpci + 432U, // t2LDRSBs + 408U, // t2LDRSHT + 21632U, // t2LDRSH_POST + 416U, // t2LDRSH_PRE + 160U, // t2LDRSHi12 + 408U, // t2LDRSHi8 + 424U, // t2LDRSHpci + 432U, // t2LDRSHs + 408U, // t2LDRT + 21632U, // t2LDR_POST + 416U, // t2LDR_PRE + 160U, // t2LDRi12 + 408U, // t2LDRi8 + 424U, // t2LDRpci + 432U, // t2LDRs + 0U, // t2LSLri + 0U, // t2LSLrr + 1081344U, // t2LSRri + 0U, // t2LSRrr + 4690993U, // t2MCR + 4690993U, // t2MCR2 + 6788145U, // t2MCRR + 6788145U, // t2MCRR2 + 35651584U, // t2MLA + 35651584U, // t2MLS + 1112U, // t2MOVTi16 + 1024U, // t2MOVi + 1024U, // t2MOVi16 + 1024U, // t2MOVr + 22528U, // t2MOVsra_flag + 22528U, // t2MOVsrl_flag + 0U, // t2MRC + 0U, // t2MRC2 + 0U, // t2MRRC + 0U, // t2MRRC2 + 2U, // t2MRS_AR + 448U, // t2MRS_M + 200U, // t2MRSbanked + 2U, // t2MRSsys_AR + 33U, // t2MSR_AR + 33U, // t2MSR_M + 0U, // t2MSRbanked + 0U, // t2MUL + 1024U, // t2MVNi + 1024U, // t2MVNr + 56U, // t2MVNs + 0U, // t2ORNri + 0U, // t2ORNrr + 1048576U, // t2ORNrs + 0U, // t2ORRri + 0U, // t2ORRrr + 1048576U, // t2ORRrs + 8388608U, // t2PKHBT + 10485760U, // t2PKHTB + 0U, // t2PLDWi12 + 0U, // t2PLDWi8 + 0U, // t2PLDWs + 0U, // t2PLDi12 + 0U, // t2PLDi8 + 0U, // t2PLDpci + 0U, // t2PLDs + 0U, // t2PLIi12 + 0U, // t2PLIi8 + 0U, // t2PLIpci + 0U, // t2PLIs + 0U, // t2QADD + 0U, // t2QADD16 + 0U, // t2QADD8 + 0U, // t2QASX + 0U, // t2QDADD + 0U, // t2QDSUB + 0U, // t2QSAX + 0U, // t2QSUB + 0U, // t2QSUB16 + 0U, // t2QSUB8 + 1024U, // t2RBIT + 1024U, // t2REV + 1024U, // t2REV16 + 1024U, // t2REVSH + 0U, // t2RFEDB + 0U, // t2RFEDBW + 0U, // t2RFEIA + 0U, // t2RFEIAW + 0U, // t2RORri + 0U, // t2RORrr + 1024U, // t2RRX + 0U, // t2RSBri + 0U, // t2RSBrr + 1048576U, // t2RSBrs + 0U, // t2SADD16 + 0U, // t2SADD8 + 0U, // t2SASX + 0U, // t2SBCri + 0U, // t2SBCrr + 1048576U, // t2SBCrs + 69206016U, // t2SBFX + 0U, // t2SDIV + 0U, // t2SEL + 0U, // t2SETPAN + 0U, // t2SG + 0U, // t2SHADD16 + 0U, // t2SHADD8 + 0U, // t2SHASX + 0U, // t2SHSAX + 0U, // t2SHSUB16 + 0U, // t2SHSUB8 + 0U, // t2SMC + 35651584U, // t2SMLABB + 35651584U, // t2SMLABT + 35651584U, // t2SMLAD + 35651584U, // t2SMLADX + 35651584U, // t2SMLAL + 35651584U, // t2SMLALBB + 35651584U, // t2SMLALBT + 35651584U, // t2SMLALD + 35651584U, // t2SMLALDX + 35651584U, // t2SMLALTB + 35651584U, // t2SMLALTT + 35651584U, // t2SMLATB + 35651584U, // t2SMLATT + 35651584U, // t2SMLAWB + 35651584U, // t2SMLAWT + 35651584U, // t2SMLSD + 35651584U, // t2SMLSDX + 35651584U, // t2SMLSLD + 35651584U, // t2SMLSLDX + 35651584U, // t2SMMLA + 35651584U, // t2SMMLAR + 35651584U, // t2SMMLS + 35651584U, // t2SMMLSR + 0U, // t2SMMUL + 0U, // t2SMMULR + 0U, // t2SMUAD + 0U, // t2SMUADX + 0U, // t2SMULBB + 0U, // t2SMULBT + 35651584U, // t2SMULL + 0U, // t2SMULTB + 0U, // t2SMULTT + 0U, // t2SMULWB + 0U, // t2SMULWT + 0U, // t2SMUSD + 0U, // t2SMUSDX + 0U, // t2SRSDB + 0U, // t2SRSDB_UPD + 0U, // t2SRSIA + 0U, // t2SRSIA_UPD + 6352U, // t2SSAT + 1232U, // t2SSAT16 + 0U, // t2SSAX + 0U, // t2SSUB16 + 0U, // t2SSUB8 + 122U, // t2STC2L_OFFSET + 196738U, // t2STC2L_OPTION + 229506U, // t2STC2L_POST + 138U, // t2STC2L_PRE + 122U, // t2STC2_OFFSET + 196738U, // t2STC2_OPTION + 229506U, // t2STC2_POST + 138U, // t2STC2_PRE + 122U, // t2STCL_OFFSET + 196738U, // t2STCL_OPTION + 229506U, // t2STCL_POST + 138U, // t2STCL_PRE + 122U, // t2STC_OFFSET + 196738U, // t2STC_OPTION + 229506U, // t2STC_POST + 138U, // t2STC_PRE + 8U, // t2STL + 8U, // t2STLB + 557056U, // t2STLEX + 557056U, // t2STLEXB + 371195904U, // t2STLEXD + 557056U, // t2STLEXH + 8U, // t2STLH + 1136U, // t2STMDB + 33U, // t2STMDB_UPD + 1136U, // t2STMIA + 33U, // t2STMIA_UPD + 408U, // t2STRBT + 21632U, // t2STRB_POST + 416U, // t2STRB_PRE + 160U, // t2STRBi12 + 408U, // t2STRBi8 + 432U, // t2STRBs + 25493592U, // t2STRD_POST + 1114200U, // t2STRD_PRE + 1146880U, // t2STRDi8 + 1179648U, // t2STREX + 557056U, // t2STREXB + 371195904U, // t2STREXD + 557056U, // t2STREXH + 408U, // t2STRHT + 21632U, // t2STRH_POST + 416U, // t2STRH_PRE + 160U, // t2STRHi12 + 408U, // t2STRHi8 + 432U, // t2STRHs + 408U, // t2STRT + 21632U, // t2STR_POST + 416U, // t2STR_PRE + 160U, // t2STRi12 + 408U, // t2STRi8 + 432U, // t2STRs + 0U, // t2SUBS_PC_LR + 0U, // t2SUBri + 0U, // t2SUBri12 + 0U, // t2SUBrr + 1048576U, // t2SUBrs + 12582912U, // t2SXTAB + 12582912U, // t2SXTAB16 + 12582912U, // t2SXTAH + 7168U, // t2SXTB + 7168U, // t2SXTB16 + 7168U, // t2SXTH + 0U, // t2TBB + 0U, // t2TBH + 1024U, // t2TEQri + 1024U, // t2TEQrr + 56U, // t2TEQrs + 0U, // t2TSB + 1024U, // t2TSTri + 1024U, // t2TSTrr + 56U, // t2TSTrs + 1024U, // t2TT + 1024U, // t2TTA + 1024U, // t2TTAT + 1024U, // t2TTT + 0U, // t2UADD16 + 0U, // t2UADD8 + 0U, // t2UASX + 69206016U, // t2UBFX + 0U, // t2UDF + 0U, // t2UDIV + 0U, // t2UHADD16 + 0U, // t2UHADD8 + 0U, // t2UHASX + 0U, // t2UHSAX + 0U, // t2UHSUB16 + 0U, // t2UHSUB8 + 35651584U, // t2UMAAL + 35651584U, // t2UMLAL + 35651584U, // t2UMULL + 0U, // t2UQADD16 + 0U, // t2UQADD8 + 0U, // t2UQASX + 0U, // t2UQSAX + 0U, // t2UQSUB16 + 0U, // t2UQSUB8 + 0U, // t2USAD8 + 35651584U, // t2USADA8 + 14680064U, // t2USAT + 0U, // t2USAT16 + 0U, // t2USAX + 0U, // t2USUB16 + 0U, // t2USUB8 + 12582912U, // t2UXTAB + 12582912U, // t2UXTAB16 + 12582912U, // t2UXTAH + 7168U, // t2UXTB + 7168U, // t2UXTB16 + 7168U, // t2UXTH + 0U, // tADC + 1112U, // tADDhirr + 1048U, // tADDi3 + 0U, // tADDi8 + 0U, // tADDrSP + 1212416U, // tADDrSPi + 1048U, // tADDrr + 456U, // tADDspi + 1112U, // tADDspr + 464U, // tADR + 0U, // tAND + 472U, // tASRri + 0U, // tASRrr + 0U, // tB + 0U, // tBIC + 0U, // tBKPT + 0U, // tBL + 0U, // tBLXNSr + 0U, // tBLXi + 0U, // tBLXr + 0U, // tBX + 0U, // tBXNS + 0U, // tBcc + 0U, // tCBNZ + 0U, // tCBZ + 1024U, // tCMNz + 1024U, // tCMPhir + 1024U, // tCMPi8 + 1024U, // tCMPr + 0U, // tCPS + 0U, // tEOR + 0U, // tHINT + 0U, // tHLT + 0U, // tInt_WIN_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_longjmp + 0U, // tInt_eh_sjlj_setjmp + 1136U, // tLDMIA + 480U, // tLDRBi + 488U, // tLDRBr + 496U, // tLDRHi + 488U, // tLDRHr + 488U, // tLDRSB + 488U, // tLDRSH + 504U, // tLDRi + 424U, // tLDRpci + 488U, // tLDRr + 512U, // tLDRspi + 1048U, // tLSLri + 0U, // tLSLrr + 472U, // tLSRri + 0U, // tLSRrr + 0U, // tMOVSr + 0U, // tMOVi8 + 1024U, // tMOVr + 1048U, // tMUL + 0U, // tMVN + 0U, // tORR + 0U, // tPICADD + 0U, // tPOP + 0U, // tPUSH + 1024U, // tREV + 1024U, // tREV16 + 1024U, // tREVSH + 0U, // tROR + 0U, // tRSB + 0U, // tSBC + 0U, // tSETEND + 33U, // tSTMIA_UPD + 480U, // tSTRBi + 488U, // tSTRBr + 496U, // tSTRHi + 488U, // tSTRHr + 504U, // tSTRi + 488U, // tSTRr + 512U, // tSTRspi + 1048U, // tSUBi3 + 0U, // tSUBi8 + 1048U, // tSUBrr + 456U, // tSUBspi + 0U, // tSVC + 1024U, // tSXTB + 1024U, // tSXTH + 0U, // tTRAP + 1024U, // tTST + 0U, // tUDF + 1024U, // tUXTB + 1024U, // tUXTH + 0U, // t__brkdiv0 + }; + + unsigned int opcode = MCInst_getOpcode(MI); + // printf("opcode = %u\n", opcode); + + // Emit the opcode for the instruction. + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[opcode] << 0; + Bits |= (uint64_t)OpInfo1[opcode] << 32; +#ifndef CAPSTONE_DIET + SStream_concat0(O, AsmStrs+(Bits & 4095)-1); +#endif + + + // Fragment 0 encoded into 5 bits for 32 unique commands. + // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 12) & 31)); + switch ((Bits >> 12) & 31) { + default: // unreachable + case 0: + // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... + return; + break; + case 1: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCri, ADCrr, ADDri, A... + printSBitModifierOperand(MI, 5, O); + printPredicateOperand(MI, 3, O); + break; + case 2: + // ITasm, t2IT + printThumbITMask(MI, 1, O); + break; + case 3: + // LDRBT_POST, LDRConstPool, LDRT_POST, STRBT_POST, STRT_POST, t2LDRBpcre... + printPredicateOperand(MI, 2, O); + break; + case 4: + // RRXi, MOVi, MOVr, MOVr_TC, MVNi, MVNr, t2MOVi, t2MOVr, t2MVNi, t2MVNr,... + printSBitModifierOperand(MI, 4, O); + printPredicateOperand(MI, 2, O); + break; + case 5: + // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... + printPredicateOperand(MI, 4, O); + break; + case 6: + // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... + printPredicateOperand(MI, 5, O); + break; + case 7: + // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... + printPredicateOperand(MI, 3, O); + break; + case 8: + // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, MLA, MOVsr, MVNsr, ORRrsi, RSB... + printSBitModifierOperand(MI, 6, O); + printPredicateOperand(MI, 4, O); + break; + case 9: + // ADCrsr, ADDrsr, ANDrsr, BICrsr, EORrsr, ORRrsr, RSBrsr, RSCrsr, SBCrsr... + printSBitModifierOperand(MI, 7, O); + printPredicateOperand(MI, 5, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printSORegRegOperand(MI, 2, O); + return; + break; + case 10: + // AESD, AESE, AESIMC, AESMC, BKPT, BL, BLX, BLXi, BX, CPS1p, CRC32B, CRC... + printOperand(MI, 0, O); + break; + case 11: + // BLX_pred, BL_pred, BXJ, BX_pred, Bcc, DBG, FLDMXIA, FSTMXIA, HINT, LDM... + printPredicateOperand(MI, 1, O); + break; + case 12: + // BX_RET, ERET, FMSTAT, MOVPCLR, t2CLREX, t2DCPS1, t2DCPS2, t2DCPS3, t2S... + printPredicateOperand(MI, 0, O); + break; + case 13: + // CDP, LDRD_POST, LDRD_PRE, MCR, MRC, SMLALBB, SMLALBT, SMLALD, SMLALDX,... + printPredicateOperand(MI, 6, O); + break; + case 14: + // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, ... + printPImmediate(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 15: + // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS + printCPSIMod(MI, 0, O); + break; + case 16: + // DMB, DSB + printMemBOption(MI, 0, O); + return; + break; + case 17: + // ISB + printInstSyncBOption(MI, 0, O); + return; + break; + case 18: + // MRC2 + printPImmediate(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 19: + // MRRC2 + printPImmediate(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + return; + break; + case 20: + // PLDWi12, PLDi12, PLIi12 + printAddrModeImm12Operand(MI, 0, O, false); + return; + break; + case 21: + // PLDWrs, PLDrs, PLIrs + printAddrMode2Operand(MI, 0, O); + return; + break; + case 22: + // SETEND, tSETEND + printSetendOperand(MI, 0, O); + return; + break; + case 23: + // SMLAL, UMLAL + printSBitModifierOperand(MI, 8, O); + printPredicateOperand(MI, 6, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 24: + // TSB + printTraceSyncBOption(MI, 0, O); + return; + break; + case 25: + // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... + printPredicateOperand(MI, 7, O); + break; + case 26: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + printPredicateOperand(MI, 9, O); + break; + case 27: + // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... + printPredicateOperand(MI, 11, O); + break; + case 28: + // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... + printPredicateOperand(MI, 8, O); + break; + case 29: + // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... + printPredicateOperand(MI, 13, O); + break; + case 30: + // VSDOTD, VSDOTDI, VSDOTQ, VSDOTQI, VUDOTD, VUDOTDI, VUDOTQ, VUDOTQI + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + break; + case 31: + // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... + printSBitModifierOperand(MI, 1, O); + break; + } + + + // Fragment 1 encoded into 7 bits for 75 unique commands. + // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 17) & 127)); + switch ((Bits >> 17) & 127) { + default: // unreachable + case 0: + // ASRi, ASRr, ITasm, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LS... + SStream_concat0(O, " "); + break; + case 1: + // VLD1LNdAsm_16, VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_register_Asm_16, VLD2... + SStream_concat0(O, ".16\t"); + ARM_addVectorDataSize(MI, 16); + break; + case 2: + // VLD1LNdAsm_32, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_register_Asm_32, VLD2... + SStream_concat0(O, ".32\t"); + ARM_addVectorDataSize(MI, 32); + break; + case 3: + // VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_8, VLD1LNdWB_register_Asm_8, VLD2LNd... + SStream_concat0(O, ".8\t"); + ARM_addVectorDataSize(MI, 8); + break; + case 4: + // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... + SStream_concat0(O, "\t"); + break; + case 5: + // AESD, AESE, AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, ... + SStream_concat0(O, ", "); + break; + case 6: + // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R... + return; + break; + case 7: + // BX_RET + SStream_concat0(O, "\tlr"); + ARM_addReg(MI, ARM_REG_LR); + return; + break; + case 8: + // CDP2, MCR2, MCRR2 + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 9: + // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V... + SStream_concat0(O, ".f64\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F64); + printOperand(MI, 0, O); + break; + case 10: + // FCONSTH, VABDhd, VABDhq, VABSH, VABShd, VABShq, VACGEhd, VACGEhq, VACG... + SStream_concat0(O, ".f16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F16); + printOperand(MI, 0, O); + break; + case 11: + // FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfq, VACGEfd, VACGEfq, VACG... + SStream_concat0(O, ".f32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F32); + printOperand(MI, 0, O); + break; + case 12: + // FMSTAT + SStream_concat0(O, "\tapsr_nzcv, fpscr"); + ARM_addReg(MI, ARM_REG_APSR_NZCV); + ARM_addReg(MI, ARM_REG_FPSCR); + return; + break; + case 13: + // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, LDC2_O... + printCImmediate(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 14: + // MOVPCLR + SStream_concat0(O, "\tpc, lr"); + ARM_addReg(MI, ARM_REG_PC); + ARM_addReg(MI, ARM_REG_LR); + return; + break; + case 15: + // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD + SStream_concat0(O, "!"); + return; + break; + case 16: + // VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i... + SStream_concat0(O, ".s32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_S32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 17: + // VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i... + SStream_concat0(O, ".s16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_S16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 18: + // VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8... + SStream_concat0(O, ".s8\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_S8); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 19: + // VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i... + SStream_concat0(O, ".u32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_U32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 20: + // VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i... + SStream_concat0(O, ".u16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_U16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 21: + // VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8... + SStream_concat0(O, ".u8\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_U8); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 22: + // VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V... + SStream_concat0(O, ".i64\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_I64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 23: + // VADDHNv4i16, VADDv2i32, VADDv4i32, VBICiv2i32, VBICiv4i32, VCEQv2i32, ... + SStream_concat0(O, ".i32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_I32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 24: + // VADDHNv8i8, VADDv4i16, VADDv8i16, VBICiv4i16, VBICiv8i16, VCEQv4i16, V... + SStream_concat0(O, ".i16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_I16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 25: + // VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv... + SStream_concat0(O, ".i8\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_I8); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 26: + // VCVTBDH, VCVTTDH + SStream_concat0(O, ".f16.f64\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 27: + // VCVTBHD, VCVTTHD + SStream_concat0(O, ".f64.f16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 28: + // VCVTBHS, VCVTTHS, VCVTh2f + SStream_concat0(O, ".f32.f16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 29: + // VCVTBSH, VCVTTSH, VCVTf2h + SStream_concat0(O, ".f16.f32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 30: + // VCVTDS + SStream_concat0(O, ".f64.f32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 31: + // VCVTSD + SStream_concat0(O, ".f32.f64\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 32: + // VCVTf2sd, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSIZS, VTOSLS + SStream_concat0(O, ".s32.f32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 33: + // VCVTf2ud, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUIZS, VTOULS + SStream_concat0(O, ".u32.f32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 34: + // VCVTh2sd, VCVTh2sq, VCVTh2xsd, VCVTh2xsq, VTOSHH + SStream_concat0(O, ".s16.f16\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 35: + // VCVTh2ud, VCVTh2uq, VCVTh2xud, VCVTh2xuq, VTOUHH + SStream_concat0(O, ".u16.f16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 36: + // VCVTs2fd, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS + SStream_concat0(O, ".f32.s32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 37: + // VCVTs2hd, VCVTs2hq, VCVTxs2hd, VCVTxs2hq, VSHTOH + SStream_concat0(O, ".f16.s16\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 38: + // VCVTu2fd, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS + SStream_concat0(O, ".f32.u32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 39: + // VCVTu2hd, VCVTu2hq, VCVTxu2hd, VCVTxu2hq, VUHTOH + SStream_concat0(O, ".f16.u16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 40: + // VEXTq64, VLD1d64, VLD1d64Q, VLD1d64Qwb_fixed, VLD1d64Qwb_register, VLD... + SStream_concat0(O, ".64\t"); + ARM_addVectorDataSize(MI, 64); + break; + case 41: + // VJCVT, VTOSIRD, VTOSIZD, VTOSLD + SStream_concat0(O, ".s32.f64\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 42: + // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq... + SStream_concat0(O, ".16\t{"); + ARM_addVectorDataSize(MI, 16); + break; + case 43: + // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq... + SStream_concat0(O, ".32\t{"); + ARM_addVectorDataSize(MI, 32); + break; + case 44: + // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U... + SStream_concat0(O, ".8\t{"); + ARM_addVectorDataSize(MI, 8); + break; + case 45: + // VMSR + SStream_concat0(O, "\tfpscr, "); + ARM_addReg(MI, ARM_REG_FPSCR); + printOperand(MI, 0, O); + return; + break; + case 46: + // VMSR_FPEXC + SStream_concat0(O, "\tfpexc, "); + ARM_addReg(MI, ARM_REG_FPEXC); + printOperand(MI, 0, O); + return; + break; + case 47: + // VMSR_FPINST + SStream_concat0(O, "\tfpinst, "); + ARM_addReg(MI, ARM_REG_FPINST); + printOperand(MI, 0, O); + return; + break; + case 48: + // VMSR_FPINST2 + SStream_concat0(O, "\tfpinst2, "); + ARM_addReg(MI, ARM_REG_FPINST2); + printOperand(MI, 0, O); + return; + break; + case 49: + // VMSR_FPSID + SStream_concat0(O, "\tfpsid, "); + ARM_addReg(MI, ARM_REG_FPSID); + printOperand(MI, 0, O); + return; + break; + case 50: + // VMULLp8, VMULpd, VMULpq + SStream_concat0(O, ".p8\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_P8); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 51: + // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V... + SStream_concat0(O, ".s64\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_S64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 52: + // VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ... + SStream_concat0(O, ".u64\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_U64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 53: + // VSDOTDI, VSDOTQI, VUDOTDI, VUDOTQI + printVectorIndex(MI, 4, O); + return; + break; + case 54: + // VSHTOD + SStream_concat0(O, ".f64.s16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 55: + // VSHTOS + SStream_concat0(O, ".f32.s16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 56: + // VSITOD, VSLTOD + SStream_concat0(O, ".f64.s32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 57: + // VSITOH, VSLTOH + SStream_concat0(O, ".f16.s32\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 58: + // VTOSHD + SStream_concat0(O, ".s16.f64\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 59: + // VTOSHS + SStream_concat0(O, ".s16.f32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 60: + // VTOSIRH, VTOSIZH, VTOSLH + SStream_concat0(O, ".s32.f16\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 61: + // VTOUHD + SStream_concat0(O, ".u16.f64\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 62: + // VTOUHS + SStream_concat0(O, ".u16.f32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 63: + // VTOUIRD, VTOUIZD, VTOULD + SStream_concat0(O, ".u32.f64\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F64); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 64: + // VTOUIRH, VTOUIZH, VTOULH + SStream_concat0(O, ".u32.f16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 65: + // VUHTOD + SStream_concat0(O, ".f64.u16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 66: + // VUHTOS + SStream_concat0(O, ".f32.u16\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U16); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printFBits16(MI, 2, O); + return; + break; + case 67: + // VUITOD, VULTOD + SStream_concat0(O, ".f64.u32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 68: + // VUITOH, VULTOH + SStream_concat0(O, ".f16.u32\t"); + ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U32); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + break; + case 69: + // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADR, t2ANDrr, t2ANDrs, ... + SStream_concat0(O, ".w\t"); + break; + case 70: + // t2SRSDB, t2SRSIA + SStream_concat0(O, "\tsp, "); + ARM_addReg(MI, ARM_REG_SP); + printOperand(MI, 0, O); + return; + break; + case 71: + // t2SRSDB_UPD, t2SRSIA_UPD + SStream_concat0(O, "\tsp!, "); + ARM_addReg(MI, ARM_REG_SP); + printOperand(MI, 0, O); + return; + break; + case 72: + // t2SUBS_PC_LR + SStream_concat0(O, "\tpc, lr, "); + printOperand(MI, 0, O); + return; + break; + case 73: + // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... + printPredicateOperand(MI, 4, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 74: + // tMOVi8, tMVN, tRSB + printPredicateOperand(MI, 3, O); + SStream_concat0(O, "\t"); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + break; + } + + + // Fragment 2 encoded into 6 bits for 60 unique commands. + // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 24) & 63)); + switch ((Bits >> 24) & 63) { + default: // unreachable + case 0: + // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LSRi, LSR... + printOperand(MI, 0, O); + break; + case 1: + // ITasm, t2IT + printMandatoryPredicateOperand(MI, 0, O); + return; + break; + case 2: + // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... + printVectorListThreeAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 3: + // VLD3DUPqAsm_16, VLD3DUPqAsm_32, VLD3DUPqAsm_8, VLD3DUPqWB_fixed_Asm_16... + printVectorListThreeSpacedAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 4: + // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... + printVectorListThree(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 5: + // VLD3qAsm_16, VLD3qAsm_32, VLD3qAsm_8, VLD3qWB_fixed_Asm_16, VLD3qWB_fi... + printVectorListThreeSpaced(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 6: + // VLD4DUPdAsm_16, VLD4DUPdAsm_32, VLD4DUPdAsm_8, VLD4DUPdWB_fixed_Asm_16... + printVectorListFourAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 7: + // VLD4DUPqAsm_16, VLD4DUPqAsm_32, VLD4DUPqAsm_8, VLD4DUPqWB_fixed_Asm_16... + printVectorListFourSpacedAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 8: + // VLD4dAsm_16, VLD4dAsm_32, VLD4dAsm_8, VLD4dWB_fixed_Asm_16, VLD4dWB_fi... + printVectorListFour(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 9: + // VLD4qAsm_16, VLD4qAsm_32, VLD4qAsm_8, VLD4qWB_fixed_Asm_16, VLD4qWB_fi... + printVectorListFourSpaced(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + break; + case 10: + // AESD, AESE, MCR2, MCRR2, SHA1C, SHA1M, SHA1P, SHA1SU0, SHA1SU1, SHA256... + printOperand(MI, 2, O); + break; + case 11: + // AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, FLDM... + printOperand(MI, 1, O); + break; + case 12: + // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OP... + printPImmediate(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 13: + // CDP2 + printCImmediate(MI, 2, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 14: + // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS + printCPSIFlag(MI, 1, O); + break; + case 15: + // FCONSTD, FCONSTH, FCONSTS, VABDfd, VABDfq, VABDhd, VABDhq, VABSD, VABS... + SStream_concat0(O, ", "); + break; + case 16: + // LDAEXD, LDREXD + printGPRPairOperand(MI, 0, O); + SStream_concat0(O, ", "); + printAddrMode7Operand(MI, 1, O); + return; + break; + case 17: + // LDC2L_OFFSET, LDC2_OFFSET, STC2L_OFFSET, STC2_OFFSET + printAddrMode5Operand(MI, 2, O, false); + return; + break; + case 18: + // LDC2L_OPTION, LDC2L_POST, LDC2_OPTION, LDC2_POST, STC2L_OPTION, STC2L_... + printAddrMode7Operand(MI, 2, O); + SStream_concat0(O, ", "); + break; + case 19: + // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE + printAddrMode5Operand(MI, 2, O, true); + SStream_concat0(O, "!"); + return; + break; + case 20: + // MRC, t2MRC, t2MRC2 + printPImmediate(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 21: + // MRRC, t2MRRC, t2MRRC2 + printPImmediate(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + return; + break; + case 22: + // MSR, MSRi, t2MSR_AR, t2MSR_M + printMSRMaskOperand(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 23: + // MSRbanked, t2MSRbanked + printBankedRegOperand(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 24: + // VBICiv2i32, VBICiv4i16, VBICiv4i32, VBICiv8i16, VMOVv16i8, VMOVv1i64, ... + printNEONModImmOperand(MI, 1, O); + return; + break; + case 25: + // VCMPEZD, VCMPEZH, VCMPEZS, VCMPZD, VCMPZH, VCMPZS, tRSB + SStream_concat0(O, ", #0"); + op_addImm(MI, 0); + return; + break; + case 26: + // VCVTf2sd, VCVTf2sq, VCVTf2ud, VCVTf2uq, VCVTh2sd, VCVTh2sq, VCVTh2ud, ... + return; + break; + case 27: + // VLD1DUPd16, VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32, VLD... + printVectorListOneAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 28: + // VLD1DUPq16, VLD1DUPq16wb_fixed, VLD1DUPq16wb_register, VLD1DUPq32, VLD... + printVectorListTwoAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 29: + // VLD1d16, VLD1d16wb_fixed, VLD1d16wb_register, VLD1d32, VLD1d32wb_fixed... + printVectorListOne(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 30: + // VLD1q16, VLD1q16wb_fixed, VLD1q16wb_register, VLD1q32, VLD1q32wb_fixed... + printVectorListTwo(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 31: + // VLD2DUPd16x2, VLD2DUPd16x2wb_fixed, VLD2DUPd16x2wb_register, VLD2DUPd3... + printVectorListTwoSpacedAllLanes(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 32: + // VLD2b16, VLD2b16wb_fixed, VLD2b16wb_register, VLD2b32, VLD2b32wb_fixed... + printVectorListTwoSpaced(MI, 0, O); + SStream_concat0(O, ", "); + break; + case 33: + // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST2LNd16_UPD, VST2LNd32_U... + printOperand(MI, 4, O); + break; + case 34: + // VST1d16, VST1d32, VST1d64, VST1d8 + printVectorListOne(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 35: + // VST1d16Q, VST1d32Q, VST1d64Q, VST1d8Q, VST2q16, VST2q32, VST2q8 + printVectorListFour(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 36: + // VST1d16Qwb_fixed, VST1d32Qwb_fixed, VST1d64Qwb_fixed, VST1d8Qwb_fixed,... + printVectorListFour(MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, "!"); + return; + break; + case 37: + // VST1d16Qwb_register, VST1d32Qwb_register, VST1d64Qwb_register, VST1d8Q... + printVectorListFour(MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 38: + // VST1d16T, VST1d32T, VST1d64T, VST1d8T + printVectorListThree(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 39: + // VST1d16Twb_fixed, VST1d32Twb_fixed, VST1d64Twb_fixed, VST1d8Twb_fixed + printVectorListThree(MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, "!"); + return; + break; + case 40: + // VST1d16Twb_register, VST1d32Twb_register, VST1d64Twb_register, VST1d8T... + printVectorListThree(MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 41: + // VST1d16wb_fixed, VST1d32wb_fixed, VST1d64wb_fixed, VST1d8wb_fixed + printVectorListOne(MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, "!"); + return; + break; + case 42: + // VST1d16wb_register, VST1d32wb_register, VST1d64wb_register, VST1d8wb_r... + printVectorListOne(MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 43: + // VST1q16, VST1q32, VST1q64, VST1q8, VST2d16, VST2d32, VST2d8 + printVectorListTwo(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 44: + // VST1q16wb_fixed, VST1q32wb_fixed, VST1q64wb_fixed, VST1q8wb_fixed, VST... + printVectorListTwo(MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, "!"); + return; + break; + case 45: + // VST1q16wb_register, VST1q32wb_register, VST1q64wb_register, VST1q8wb_r... + printVectorListTwo(MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 46: + // VST2b16, VST2b32, VST2b8 + printVectorListTwoSpaced(MI, 2, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 47: + // VST2b16wb_fixed, VST2b32wb_fixed, VST2b8wb_fixed + printVectorListTwoSpaced(MI, 3, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, "!"); + return; + break; + case 48: + // VST2b16wb_register, VST2b32wb_register, VST2b8wb_register + printVectorListTwoSpaced(MI, 4, O); + SStream_concat0(O, ", "); + printAddrMode6Operand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 49: + // t2DMB, t2DSB + printMemBOption(MI, 0, O); + return; + break; + case 50: + // t2ISB + printInstSyncBOption(MI, 0, O); + return; + break; + case 51: + // t2PLDWi12, t2PLDi12, t2PLIi12 + printAddrModeImm12Operand(MI, 0, O, false); + return; + break; + case 52: + // t2PLDWi8, t2PLDi8, t2PLIi8 + printT2AddrModeImm8Operand(MI, 0, O, false); + return; + break; + case 53: + // t2PLDWs, t2PLDs, t2PLIs + printT2AddrModeSoRegOperand(MI, 0, O); + return; + break; + case 54: + // t2PLDpci, t2PLIpci + printThumbLdrLabelOperand(MI, 0, O); + return; + break; + case 55: + // t2TBB + printAddrModeTBB(MI, 0, O); + return; + break; + case 56: + // t2TBH + printAddrModeTBH(MI, 0, O); + return; + break; + case 57: + // t2TSB + printTraceSyncBOption(MI, 0, O); + return; + break; + case 58: + // tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tORR, tROR, tS... + printOperand(MI, 3, O); + return; + break; + case 59: + // tPOP, tPUSH + printRegisterList(MI, 2, O); + return; + break; + } + + + // Fragment 3 encoded into 5 bits for 30 unique commands. + // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 30) & 31)); + switch ((Bits >> 30) & 31) { + default: // unreachable + case 0: + // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LSRi, LSR... + SStream_concat0(O, ", "); + break; + case 1: + // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPqAsm_16, VLD3DUP... + return; + break; + case 2: + // VLD3DUPdWB_fixed_Asm_16, VLD3DUPdWB_fixed_Asm_32, VLD3DUPdWB_fixed_Asm... + SStream_concat0(O, "!"); + return; + break; + case 3: + // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... + printAddrMode6Operand(MI, 1, O); + break; + case 4: + // CDP, MCR, MCRR, MSR, VABDfd, VABDfq, VABDhd, VABDhq, VABSD, VABSH, VAB... + printOperand(MI, 1, O); + break; + case 5: + // FCONSTD, FCONSTH, FCONSTS, VMOVv2f32, VMOVv4f32 + printFPImmOperand(MI, 1, O); + return; + break; + case 6: + // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U... + SStream_concat0(O, "!, "); + printRegisterList(MI, 4, O); + break; + case 7: + // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION + printCoprocOptionImm(MI, 3, O); + return; + break; + case 8: + // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST + printPostIdxImm8s4Operand(MI, 3, O); + return; + break; + case 9: + // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OPTION,... + printCImmediate(MI, 1, O); + SStream_concat0(O, ", "); + break; + case 10: + // MRS, t2MRS_AR + SStream_concat0(O, ", apsr"); + ARM_addReg(MI, ARM_REG_APSR); + return; + break; + case 11: + // MRSsys, t2MRSsys_AR + SStream_concat0(O, ", spsr"); + ARM_addReg(MI, ARM_REG_SPSR); + return; + break; + case 12: + // MSRi + printModImmOperand(MI, 1, O); + return; + break; + case 13: + // VCEQzv16i8, VCEQzv2i32, VCEQzv4i16, VCEQzv4i32, VCEQzv8i16, VCEQzv8i8,... + SStream_concat0(O, ", #0"); + op_addImm(MI, 0); + return; + break; + case 14: + // VCVTf2xsd, VCVTf2xsq, VCVTf2xud, VCVTf2xuq, VCVTh2xsd, VCVTh2xsq, VCVT... + printOperand(MI, 2, O); + break; + case 15: + // VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8 + printVectorIndex(MI, 2, O); + return; + break; + case 16: + // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP... + printAddrMode6Operand(MI, 2, O); + break; + case 17: + // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... + SStream_concat0(O, "["); + set_mem_access(MI, true); + break; + case 18: + // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... + SStream_concat0(O, "[], "); + printOperand(MI, 1, O); + SStream_concat0(O, "[], "); + printOperand(MI, 2, O); + break; + case 19: + // VMRS + SStream_concat0(O, ", fpscr"); + ARM_addReg(MI, ARM_REG_FPSCR); + return; + break; + case 20: + // VMRS_FPEXC + SStream_concat0(O, ", fpexc"); + ARM_addReg(MI, ARM_REG_FPEXC); + return; + break; + case 21: + // VMRS_FPINST + SStream_concat0(O, ", fpinst"); + ARM_addReg(MI, ARM_REG_FPINST); + return; + break; + case 22: + // VMRS_FPINST2 + SStream_concat0(O, ", fpinst2"); + ARM_addReg(MI, ARM_REG_FPINST2); + return; + break; + case 23: + // VMRS_FPSID + SStream_concat0(O, ", fpsid"); + ARM_addReg(MI, ARM_REG_FPSID); + return; + break; + case 24: + // VMRS_MVFR0 + SStream_concat0(O, ", mvfr0"); + ARM_addReg(MI, ARM_REG_MVFR0); + return; + break; + case 25: + // VMRS_MVFR1 + SStream_concat0(O, ", mvfr1"); + ARM_addReg(MI, ARM_REG_MVFR1); + return; + break; + case 26: + // VMRS_MVFR2 + SStream_concat0(O, ", mvfr2"); + ARM_addReg(MI, ARM_REG_MVFR2); + return; + break; + case 27: + // VSETLNi16, VSETLNi32, VSETLNi8 + printVectorIndex(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 28: + // VSHTOH, VTOSHH, VTOUHH, VUHTOH + printFBits16(MI, 2, O); + return; + break; + case 29: + // VSLTOD, VSLTOH, VSLTOS, VTOSLD, VTOSLH, VTOSLS, VTOULD, VTOULH, VTOULS... + printFBits32(MI, 2, O); + return; + break; + } + + + // Fragment 4 encoded into 7 bits for 65 unique commands. + // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 35) & 127)); + switch ((Bits >> 35) & 127) { + default: // unreachable + case 0: + // ASRi, ASRr, LDRConstPool, LSLi, LSLr, LSRi, LSRr, RORi, RORr, RRXi, t2... + printOperand(MI, 1, O); + break; + case 1: + // LDRBT_POST, LDRT_POST, STRBT_POST, STRT_POST, LDA, LDAB, LDAEX, LDAEXB... + printAddrMode7Operand(MI, 1, O); + return; + break; + case 2: + // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... + printAddrMode6Operand(MI, 2, O); + break; + case 3: + // VLD3DUPdWB_register_Asm_16, VLD3DUPdWB_register_Asm_32, VLD3DUPdWB_reg... + printOperand(MI, 3, O); + break; + case 4: + // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD4dAsm_16, VLD4dAsm_32, VLD4dA... + return; + break; + case 5: + // VLD3dWB_fixed_Asm_16, VLD3dWB_fixed_Asm_32, VLD3dWB_fixed_Asm_8, VLD4d... + SStream_concat0(O, "!"); + return; + break; + case 6: + // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... + SStream_concat0(O, ", "); + break; + case 7: + // t2MOVSsi, t2MOVsi, t2CMNzrs, t2CMPrs, t2MVNs, t2TEQrs, t2TSTrs + printT2SOOperand(MI, 1, O); + return; + break; + case 8: + // t2MOVSsr, t2MOVsr, CMNzrsr, CMPrsr, MOVsr, MVNsr, TEQrsr, TSTrsr + printSORegRegOperand(MI, 1, O); + return; + break; + case 9: + // ADR, t2ADR + printAdrLabelOperand(MI, 1, O, 0); + return; + break; + case 10: + // BFC, t2BFC + printBitfieldInvMaskImmOperand(MI, 2, O); + return; + break; + case 11: + // BFI, CPS3p, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, MOVTi16... + printOperand(MI, 2, O); + break; + case 12: + // CMNri, CMPri, MOVi, MVNi, TEQri, TSTri + printModImmOperand(MI, 1, O); + return; + break; + case 13: + // CMNzrsi, CMPrsi, MOVsi, MVNsi, TEQrsi, TSTrsi + printSORegImmOperand(MI, 1, O); + return; + break; + case 14: + // FLDMXIA, FSTMXIA, LDMDA, LDMDB, LDMIA, LDMIB, STMDA, STMDB, STMIA, STM... + printRegisterList(MI, 3, O); + break; + case 15: + // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD... + printAddrMode5Operand(MI, 2, O, false); + return; + break; + case 16: + // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO... + printAddrMode7Operand(MI, 2, O); + break; + case 17: + // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_... + printAddrMode5Operand(MI, 2, O, true); + SStream_concat0(O, "!"); + return; + break; + case 18: + // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM + printAddrModeImm12Operand(MI, 2, O, true); + SStream_concat0(O, "!"); + return; + break; + case 19: + // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG + printAddrMode2Operand(MI, 2, O); + SStream_concat0(O, "!"); + return; + break; + case 20: + // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB... + printAddrModeImm12Operand(MI, 1, O, false); + return; + break; + case 21: + // LDRBrs, LDRrs, STRBrs, STRrs + printAddrMode2Operand(MI, 1, O); + return; + break; + case 22: + // LDRH, LDRSB, LDRSH, STRH + printAddrMode3Operand(MI, 1, O, false); + return; + break; + case 23: + // LDRH_PRE, LDRSB_PRE, LDRSH_PRE, STRH_PRE + printAddrMode3Operand(MI, 2, O, true); + SStream_concat0(O, "!"); + return; + break; + case 24: + // MCR2 + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 25: + // MRSbanked, t2MRSbanked + printBankedRegOperand(MI, 1, O); + return; + break; + case 26: + // SSAT, SSAT16, t2SSAT, t2SSAT16 + printImmPlusOneOperand(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + break; + case 27: + // STLEXD, STREXD + printGPRPairOperand(MI, 1, O); + SStream_concat0(O, ", "); + printAddrMode7Operand(MI, 2, O); + return; + break; + case 28: + // VCEQzv2f32, VCEQzv4f16, VCEQzv4f32, VCEQzv8f16, VCGEzv2f32, VCGEzv4f16... + SStream_concat0(O, ", #0"); + op_addImm(MI, 0); + return; + break; + case 29: + // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST2LNd16, VST2LNd32, VST2LNd8, VST2LN... + printNoHashImmediate(MI, 4, O); + break; + case 30: + // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... + printNoHashImmediate(MI, 6, O); + break; + case 31: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + printNoHashImmediate(MI, 8, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 32: + // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... + SStream_concat0(O, "[]}, "); + break; + case 33: + // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... + printNoHashImmediate(MI, 10, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 1, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 10, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 2, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 10, O); + break; + case 34: + // VLD4DUPd16, VLD4DUPd16_UPD, VLD4DUPd32, VLD4DUPd32_UPD, VLD4DUPd8, VLD... + SStream_concat0(O, "[], "); + printOperand(MI, 3, O); + SStream_concat0(O, "[]}, "); + break; + case 35: + // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... + printNoHashImmediate(MI, 12, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 1, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 12, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 2, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 12, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 3, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 12, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 5, O); + printAddrMode6OffsetOperand(MI, 7, O); + return; + break; + case 36: + // VLDRD, VLDRS, VSTRD, VSTRS + printAddrMode5Operand(MI, 1, O, false); + return; + break; + case 37: + // VLDRH, VSTRH + printAddrMode5FP16Operand(MI, 1, O, false); + return; + break; + case 38: + // VST1LNd16, VST1LNd32, VST1LNd8 + printNoHashImmediate(MI, 3, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 39: + // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST3LNd16, VST3LNd32, VST3... + printNoHashImmediate(MI, 5, O); + break; + case 40: + // VST3LNd16_UPD, VST3LNd32_UPD, VST3LNd8_UPD, VST3LNq16_UPD, VST3LNq32_U... + printNoHashImmediate(MI, 7, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 5, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 7, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 6, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 7, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 1, O); + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 41: + // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... + printOperand(MI, 5, O); + SStream_concat0(O, ", "); + printOperand(MI, 6, O); + break; + case 42: + // VTBL1 + printVectorListOne(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 43: + // VTBL2 + printVectorListTwo(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 44: + // VTBL3 + printVectorListThree(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 45: + // VTBL4 + printVectorListFour(MI, 1, O); + SStream_concat0(O, ", "); + printOperand(MI, 2, O); + return; + break; + case 46: + // VTBX1 + printVectorListOne(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 47: + // VTBX2 + printVectorListTwo(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 48: + // VTBX3 + printVectorListThree(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 49: + // VTBX4 + printVectorListFour(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + return; + break; + case 50: + // sysLDMDA_UPD, sysLDMDB_UPD, sysLDMIA_UPD, sysLDMIB_UPD, sysSTMDA_UPD, ... + SStream_concat0(O, " ^"); + ARM_addUserMode(MI); + return; + break; + case 51: + // t2LDRBT, t2LDRBi8, t2LDRHT, t2LDRHi8, t2LDRSBT, t2LDRSBi8, t2LDRSHT, t... + printT2AddrModeImm8Operand(MI, 1, O, false); + return; + break; + case 52: + // t2LDRB_PRE, t2LDRH_PRE, t2LDRSB_PRE, t2LDRSH_PRE, t2LDR_PRE, t2STRB_PR... + printT2AddrModeImm8Operand(MI, 2, O, true); + SStream_concat0(O, "!"); + return; + break; + case 53: + // t2LDRBpci, t2LDRHpci, t2LDRSBpci, t2LDRSHpci, t2LDRpci, tLDRpci + printThumbLdrLabelOperand(MI, 1, O); + return; + break; + case 54: + // t2LDRBs, t2LDRHs, t2LDRSBs, t2LDRSHs, t2LDRs, t2STRBs, t2STRHs, t2STRs + printT2AddrModeSoRegOperand(MI, 1, O); + return; + break; + case 55: + // t2LDREX + printT2AddrModeImm0_1020s4Operand(MI, 1, O); + return; + break; + case 56: + // t2MRS_M + printMSRMaskOperand(MI, 1, O); + return; + break; + case 57: + // tADDspi, tSUBspi + printThumbS4ImmOperand(MI, 2, O); + return; + break; + case 58: + // tADR + printAdrLabelOperand(MI, 1, O, 2); + return; + break; + case 59: + // tASRri, tLSRri + printThumbSRImm(MI, 3, O); + return; + break; + case 60: + // tLDRBi, tSTRBi + printThumbAddrModeImm5S1Operand(MI, 1, O); + return; + break; + case 61: + // tLDRBr, tLDRHr, tLDRSB, tLDRSH, tLDRr, tSTRBr, tSTRHr, tSTRr + printThumbAddrModeRROperand(MI, 1, O); + return; + break; + case 62: + // tLDRHi, tSTRHi + printThumbAddrModeImm5S2Operand(MI, 1, O); + return; + break; + case 63: + // tLDRi, tSTRi + printThumbAddrModeImm5S4Operand(MI, 1, O); + return; + break; + case 64: + // tLDRspi, tSTRspi + printThumbAddrModeSPOperand(MI, 1, O); + return; + break; + } + + + // Fragment 5 encoded into 5 bits for 23 unique commands. + // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 42) & 31)); + switch ((Bits >> 42) & 31) { + default: // unreachable + case 0: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... + SStream_concat0(O, ", "); + break; + case 1: + // LDRConstPool, RRXi, VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD2LN... + return; + break; + case 2: + // VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_fixed_Asm_8,... + SStream_concat0(O, "!"); + return; + break; + case 3: + // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... + printOperand(MI, 3, O); + break; + case 4: + // CDP, t2CDP, t2CDP2 + printCImmediate(MI, 2, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 5: + // MCR, MCRR, VABDfd, VABDfq, VABDhd, VABDhq, VACGEfd, VACGEfq, VACGEhd, ... + printOperand(MI, 2, O); + break; + case 6: + // SSAT, t2SSAT + printShiftImmOperand(MI, 3, O); + return; + break; + case 7: + // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX... + printRotImmOperand(MI, 2, O); + return; + break; + case 8: + // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16... + printVectorIndex(MI, 4, O); + break; + case 9: + // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q, VGETLN... + printVectorIndex(MI, 2, O); + return; + break; + case 10: + // VLD1DUPd16wb_register, VLD1DUPd32wb_register, VLD1DUPd8wb_register, VL... + printOperand(MI, 4, O); + return; + break; + case 11: + // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + break; + case 12: + // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32, VLD4LNd16, VLD4L... + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 13: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + printOperand(MI, 1, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 8, O); + break; + case 14: + // VLD3DUPd16, VLD3DUPd32, VLD3DUPd8, VLD3DUPq16, VLD3DUPq32, VLD3DUPq8 + printAddrMode6Operand(MI, 3, O); + return; + break; + case 15: + // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... + printAddrMode6Operand(MI, 4, O); + break; + case 16: + // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... + printAddrMode6Operand(MI, 5, O); + printAddrMode6OffsetOperand(MI, 7, O); + return; + break; + case 17: + // VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4i16, VMULslv2i3... + printVectorIndex(MI, 3, O); + return; + break; + case 18: + // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... + SStream_concat0(O, "}, "); + printAddrMode6Operand(MI, 1, O); + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 19: + // VST4LNd16_UPD, VST4LNd32_UPD, VST4LNd8_UPD, VST4LNq16_UPD, VST4LNq32_U... + printOperand(MI, 5, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 8, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 6, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 8, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 7, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 8, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 1, O); + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 20: + // sysLDMDA, sysLDMDB, sysLDMIA, sysLDMIB, sysSTMDA, sysSTMDB, sysSTMIA, ... + SStream_concat0(O, " ^"); + ARM_addUserMode(MI); + return; + break; + case 21: + // t2LDRB_POST, t2LDRH_POST, t2LDRSB_POST, t2LDRSH_POST, t2LDR_POST, t2ST... + printT2AddrModeImm8OffsetOperand(MI, 3, O); + return; + break; + case 22: + // t2MOVsra_flag, t2MOVsrl_flag + SStream_concat0(O, ", #1"); + op_addImm(MI, 1); + return; + break; + } + + + // Fragment 6 encoded into 6 bits for 38 unique commands. + // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 47) & 63)); + switch ((Bits >> 47) & 63) { + default: // unreachable + case 0: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCrr, ADDrr, ANDrr, B... + printOperand(MI, 2, O); + break; + case 1: + // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... + printOperand(MI, 4, O); + break; + case 2: + // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... + return; + break; + case 3: + // ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri + printModImmOperand(MI, 2, O); + return; + break; + case 4: + // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, ORRrsi, RSBrsi, RSCrsi, SBCrsi... + printSORegImmOperand(MI, 2, O); + return; + break; + case 5: + // BFI, t2BFI + printBitfieldInvMaskImmOperand(MI, 3, O); + return; + break; + case 6: + // LDCL_OPTION, LDC_OPTION, STCL_OPTION, STC_OPTION, t2LDC2L_OPTION, t2LD... + printCoprocOptionImm(MI, 3, O); + return; + break; + case 7: + // LDCL_POST, LDC_POST, STCL_POST, STC_POST, t2LDC2L_POST, t2LDC2_POST, t... + printPostIdxImm8s4Operand(MI, 3, O); + return; + break; + case 8: + // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRT_POS... + printAddrMode2OffsetOperand(MI, 3, O); + return; + break; + case 9: + // LDRD, STRD + printAddrMode3Operand(MI, 2, O, false); + return; + break; + case 10: + // LDRD_POST, STRD_POST, t2LDRD_POST, t2STRD_POST + printAddrMode7Operand(MI, 3, O); + break; + case 11: + // LDRD_PRE, STRD_PRE + printAddrMode3Operand(MI, 3, O, true); + SStream_concat0(O, "!"); + return; + break; + case 12: + // LDRHTi, LDRSBTi, LDRSHTi, STRHTi + printPostIdxImm8Operand(MI, 3, O); + return; + break; + case 13: + // LDRHTr, LDRSBTr, LDRSHTr, STRHTr + printPostIdxRegOperand(MI, 3, O); + return; + break; + case 14: + // LDRH_POST, LDRSB_POST, LDRSH_POST, STRH_POST + printAddrMode3OffsetOperand(MI, 3, O); + return; + break; + case 15: + // MCR, MCRR, VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed,... + SStream_concat0(O, ", "); + break; + case 16: + // MCRR2 + printCImmediate(MI, 4, O); + return; + break; + case 17: + // STLEX, STLEXB, STLEXH, STREX, STREXB, STREXH, SWP, SWPB, t2LDAEXD, t2L... + printAddrMode7Operand(MI, 2, O); + return; + break; + case 18: + // VBIFd, VBIFq, VBITd, VBITq, VBSLd, VBSLq, VLD4LNd16, VLD4LNd32, VLD4LN... + printOperand(MI, 3, O); + break; + case 19: + // VCADDv2f32, VCADDv4f16, VCADDv4f32, VCADDv8f16 + printComplexRotationOp(MI, 3, O, 180, 90); + return; + break; + case 20: + // VCMLAv2f32, VCMLAv4f16, VCMLAv4f32, VCMLAv8f16 + printComplexRotationOp(MI, 4, O, 90, 0); + return; + break; + case 21: + // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8... + printAddrMode6Operand(MI, 1, O); + break; + case 22: + // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD + printAddrMode6Operand(MI, 2, O); + printAddrMode6OffsetOperand(MI, 4, O); + return; + break; + case 23: + // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32 + printOperand(MI, 1, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 6, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 2, O); + return; + break; + case 24: + // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 3, O); + printAddrMode6OffsetOperand(MI, 5, O); + return; + break; + case 25: + // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... + printAddrMode6OffsetOperand(MI, 6, O); + return; + break; + case 26: + // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16, VLD3LNq32 + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 2, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 8, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 3, O); + return; + break; + case 27: + // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... + printAddrMode6Operand(MI, 4, O); + printAddrMode6OffsetOperand(MI, 6, O); + return; + break; + case 28: + // VMLAslfd, VMLAslfq, VMLAslhd, VMLAslhq, VMLSslfd, VMLSslfq, VMLSslhd, ... + printVectorIndex(MI, 4, O); + return; + break; + case 29: + // VMULslfd, VMULslfq, VMULslhd, VMULslhq + printVectorIndex(MI, 3, O); + return; + break; + case 30: + // VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8_UPD, VST2LNq16_UPD, VST2LNq32_U... + printOperand(MI, 5, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 6, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 1, O); + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 31: + // VST4d16_UPD, VST4d32_UPD, VST4d8_UPD, VST4q16_UPD, VST4q32_UPD, VST4q8... + printOperand(MI, 7, O); + SStream_concat0(O, "}, "); + printAddrMode6Operand(MI, 1, O); + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 32: + // t2ADCrs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORRrs, t2RSBrs... + printT2SOOperand(MI, 2, O); + return; + break; + case 33: + // t2ASRri, t2LSRri + printThumbSRImm(MI, 2, O); + return; + break; + case 34: + // t2LDRD_PRE, t2STRD_PRE + printT2AddrModeImm8s4Operand(MI, 3, O, true); + SStream_concat0(O, "!"); + return; + break; + case 35: + // t2LDRDi8, t2STRDi8 + printT2AddrModeImm8s4Operand(MI, 2, O, false); + return; + break; + case 36: + // t2STREX + printT2AddrModeImm0_1020s4Operand(MI, 2, O); + return; + break; + case 37: + // tADDrSPi + printThumbS4ImmOperand(MI, 2, O); + return; + break; + } + + + // Fragment 7 encoded into 4 bits for 13 unique commands. + // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 53) & 15)); + switch ((Bits >> 53) & 15) { + default: // unreachable + case 0: + // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... + return; + break; + case 1: + // LDRD_POST, MLA, MLS, SBFX, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SML... + SStream_concat0(O, ", "); + break; + case 2: + // MCR, t2MCR, t2MCR2 + printCImmediate(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + SStream_concat0(O, ", "); + printOperand(MI, 5, O); + return; + break; + case 3: + // MCRR, t2MCRR, t2MCRR2 + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printCImmediate(MI, 4, O); + return; + break; + case 4: + // PKHBT, t2PKHBT + printPKHLSLShiftImm(MI, 3, O); + return; + break; + case 5: + // PKHTB, t2PKHTB + printPKHASRShiftImm(MI, 3, O); + return; + break; + case 6: + // SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH, t2SXTAB, t2SXTAB16, t2SX... + printRotImmOperand(MI, 3, O); + return; + break; + case 7: + // USAT, t2USAT + printShiftImmOperand(MI, 3, O); + return; + break; + case 8: + // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16... + printComplexRotationOp(MI, 5, O, 90, 0); + return; + break; + case 9: + // VLD3d16, VLD3d16_UPD, VLD3d32, VLD3d32_UPD, VLD3d8, VLD3d8_UPD, VLD3q1... + SStream_concat0(O, "}, "); + break; + case 10: + // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32, VST2LNd16, VST2L... + SStream_concat0(O, "["); + set_mem_access(MI, true); + break; + case 11: + // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD + printAddrMode6OffsetOperand(MI, 3, O); + return; + break; + case 12: + // t2LDRD_POST, t2STRD_POST + printT2AddrModeImm8s4OffsetOperand(MI, 4, O); + return; + break; + } + + + // Fragment 8 encoded into 4 bits for 12 unique commands. + // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 57) & 15)); + switch ((Bits >> 57) & 15) { + default: // unreachable + case 0: + // LDRD_POST, STRD_POST + printAddrMode3OffsetOperand(MI, 4, O); + return; + break; + case 1: + // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML... + printOperand(MI, 3, O); + break; + case 2: + // SBFX, UBFX, t2SBFX, t2UBFX + printImmPlusOneOperand(MI, 3, O); + return; + break; + case 3: + // VLD3d16, VLD3d32, VLD3d8, VLD3q16, VLD3q32, VLD3q8 + printAddrMode6Operand(MI, 3, O); + return; + break; + case 4: + // VLD3d16_UPD, VLD3d32_UPD, VLD3d8_UPD, VLD3q16_UPD, VLD3q32_UPD, VLD3q8... + printAddrMode6Operand(MI, 4, O); + printAddrMode6OffsetOperand(MI, 6, O); + return; + break; + case 5: + // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32 + printNoHashImmediate(MI, 10, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 4, O); + return; + break; + case 6: + // VST2LNd16, VST2LNd32, VST2LNd8, VST2LNq16, VST2LNq32 + printNoHashImmediate(MI, 4, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 7: + // VST3LNd16, VST3LNd32, VST3LNd8, VST3LNq16, VST3LNq32 + printNoHashImmediate(MI, 5, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 4, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 5, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 8: + // VST3d16, VST3d32, VST3d8, VST3q16, VST3q32, VST3q8 + printAddrMode6Operand(MI, 0, O); + return; + break; + case 9: + // VST4LNd16, VST4LNd32, VST4LNd8, VST4LNq16, VST4LNq32 + printNoHashImmediate(MI, 6, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 4, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 6, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 5, O); + SStream_concat0(O, "["); + set_mem_access(MI, true); + printNoHashImmediate(MI, 6, O); + SStream_concat0(O, "]}, "); + set_mem_access(MI, false); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 10: + // VST4d16, VST4d32, VST4d8, VST4q16, VST4q32, VST4q8 + printOperand(MI, 5, O); + SStream_concat0(O, "}, "); + printAddrMode6Operand(MI, 0, O); + return; + break; + case 11: + // t2STLEXD, t2STREXD + printAddrMode7Operand(MI, 3, O); + return; + break; + } + + + // Fragment 9 encoded into 1 bits for 2 unique commands. + // printf("Fragment 9: %"PRIu64"\n", ((Bits >> 61) & 1)); + if ((Bits >> 61) & 1) { + // VLD4d16, VLD4d16_UPD, VLD4d32, VLD4d32_UPD, VLD4d8, VLD4d8_UPD, VLD4q1... + SStream_concat0(O, "}, "); + } else { + // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML... + return; + } + + + // Fragment 10 encoded into 1 bits for 2 unique commands. + // printf("Fragment 10: %"PRIu64"\n", ((Bits >> 62) & 1)); + if ((Bits >> 62) & 1) { + // VLD4d16_UPD, VLD4d32_UPD, VLD4d8_UPD, VLD4q16_UPD, VLD4q32_UPD, VLD4q8... + printAddrMode6Operand(MI, 5, O); + printAddrMode6OffsetOperand(MI, 7, O); + return; + } else { + // VLD4d16, VLD4d32, VLD4d8, VLD4q16, VLD4q32, VLD4q8 + printAddrMode6Operand(MI, 4, O); + return; + } + +} + + + +#ifdef PRINT_ALIAS_INSTR +#undef PRINT_ALIAS_INSTR + +static bool printAliasInstr(MCInst *MI, SStream *OS) +{ + unsigned int I = 0, OpIdx, PrintMethodIdx; + char *tmpString; + const char *AsmString; + switch (MCInst_getOpcode(MI)) { + default: return false; + case ARM_DSB: + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDFB)) { + // (DSB 12) + AsmString = "dfb"; + break; + } + return false; + case ARM_HINT: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { + // (HINT 0, pred:$p) + AsmString = "nop$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && + !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { + // (HINT 1, pred:$p) + AsmString = "yield$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { + // (HINT 2, pred:$p) + AsmString = "wfe$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 && + !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { + // (HINT 3, pred:$p) + AsmString = "wfi$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && + !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { + // (HINT 4, pred:$p) + AsmString = "sev$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 && + !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) { + // (HINT 5, pred:$p) + AsmString = "sevl$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && + !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) { + // (HINT 16, pred:$p) + AsmString = "esb$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 20 && + !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { + // (HINT 20, pred:$p) + AsmString = "csdb$\xFF\x02\x01"; + break; + } + return false; + case ARM_t2DSB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDFB)) { + // (t2DSB 12, pred:$p) + AsmString = "dfb$\xFF\x02\x01"; + break; + } + return false; + case ARM_t2HINT: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { + // (t2HINT 0, pred:$p) + AsmString = "nop$\xFF\x02\x01.w"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { + // (t2HINT 1, pred:$p) + AsmString = "yield$\xFF\x02\x01.w"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { + // (t2HINT 2, pred:$p) + AsmString = "wfe$\xFF\x02\x01.w"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { + // (t2HINT 3, pred:$p) + AsmString = "wfi$\xFF\x02\x01.w"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { + // (t2HINT 4, pred:$p) + AsmString = "sev$\xFF\x02\x01.w"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) { + // (t2HINT 5, pred:$p) + AsmString = "sevl$\xFF\x02\x01.w"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) { + // (t2HINT 16, pred:$p) + AsmString = "esb$\xFF\x02\x01.w"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 20 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { + // (t2HINT 20, pred:$p) + AsmString = "csdb$\xFF\x02\x01"; + break; + } + return false; + case ARM_t2SUBS_PC_LR: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)) { + // (t2SUBS_PC_LR 0, pred:$p) + AsmString = "eret$\xFF\x02\x01"; + break; + } + return false; + case ARM_tHINT: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { + // (tHINT 0, pred:$p) + AsmString = "nop$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { + // (tHINT 1, pred:$p) + AsmString = "yield$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { + // (tHINT 2, pred:$p) + AsmString = "wfe$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { + // (tHINT 3, pred:$p) + AsmString = "wfi$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { + // (tHINT 4, pred:$p) + AsmString = "sev$\xFF\x02\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 && + ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && + ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && + ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) { + // (tHINT 5, pred:$p) + AsmString = "sevl$\xFF\x02\x01"; + break; + } + return false; + } + + + tmpString = cs_strdup(AsmString); + + while (AsmString[I] != ' ' && AsmString[I] != '\t' && + AsmString[I] != '$' && AsmString[I] != '\0') + ++I; + + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + cs_mem_free(tmpString); + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, " "); + ++I; + } + + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + OpIdx = AsmString[I++] - 1; + PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else + printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); + } else { + if (AsmString[I] == '[') { + set_mem_access(MI, true); + } else if (AsmString[I] == ']') { + set_mem_access(MI, false); + } + SStream_concat1(OS, AsmString[I++]); + } + } while (AsmString[I] != '\0'); + } + + return true; +} + +static void printCustomAliasOperand( + MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, + SStream *OS) +{ + switch (PrintMethodIdx) { + default: + break; + case 0: + printPredicateOperand(MI, OpIdx, OS); + break; + } +} + +#endif // PRINT_ALIAS_INSTR diff --git a/capstone/arch/ARM/ARMGenDisassemblerTables.inc b/capstone/arch/ARM/ARMGenDisassemblerTables.inc new file mode 100644 index 000000000..385a7d555 --- /dev/null +++ b/capstone/arch/ARM/ARMGenDisassemblerTables.inc @@ -0,0 +1,15185 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ +/* Automatically generated file, do not edit! */ + +#include "../../MCInst.h" +#include "../../LEB128.h" + + +// Helper function for extracting fields from encoded instructions. + +//#if defined(_MSC_VER) && !defined(__clang__) +//__declspec(noinline) +//#endif + +#define FieldFromInstruction(fname, InsnType) \ +static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ +{ \ + InsnType fieldMask; \ + if (numBits == sizeof(InsnType) * 8) \ + fieldMask = (InsnType)(-1LL); \ + else \ + fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ + return (insn & fieldMask) >> startBit; \ +} + +static const uint8_t DecoderTableARM32[] = { +/* 0 */ MCD_OPC_ExtractField, 25, 3, // Inst{27-25} ... +/* 3 */ MCD_OPC_FilterValue, 0, 47, 14, 0, // Skip to: 3639 +/* 8 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 11 */ MCD_OPC_FilterValue, 0, 110, 7, 0, // Skip to: 1918 +/* 16 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 19 */ MCD_OPC_FilterValue, 0, 139, 1, 0, // Skip to: 419 +/* 24 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 27 */ MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 155 +/* 32 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 35 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 65 +/* 40 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 56 +/* 45 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 56 +/* 52 */ MCD_OPC_Decode, 159, 4, 0, // Opcode: ANDrr +/* 56 */ MCD_OPC_CheckPredicate, 0, 92, 32, 0, // Skip to: 8345 +/* 61 */ MCD_OPC_Decode, 160, 4, 1, // Opcode: ANDrsi +/* 65 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 95 +/* 70 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 86 +/* 75 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 86 +/* 82 */ MCD_OPC_Decode, 245, 6, 0, // Opcode: SUBrr +/* 86 */ MCD_OPC_CheckPredicate, 0, 62, 32, 0, // Skip to: 8345 +/* 91 */ MCD_OPC_Decode, 246, 6, 1, // Opcode: SUBrsi +/* 95 */ MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 125 +/* 100 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 116 +/* 105 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 116 +/* 112 */ MCD_OPC_Decode, 150, 4, 0, // Opcode: ADDrr +/* 116 */ MCD_OPC_CheckPredicate, 0, 32, 32, 0, // Skip to: 8345 +/* 121 */ MCD_OPC_Decode, 151, 4, 1, // Opcode: ADDrsi +/* 125 */ MCD_OPC_FilterValue, 3, 23, 32, 0, // Skip to: 8345 +/* 130 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 146 +/* 135 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 146 +/* 142 */ MCD_OPC_Decode, 239, 5, 0, // Opcode: SBCrr +/* 146 */ MCD_OPC_CheckPredicate, 0, 2, 32, 0, // Skip to: 8345 +/* 151 */ MCD_OPC_Decode, 240, 5, 1, // Opcode: SBCrsi +/* 155 */ MCD_OPC_FilterValue, 1, 249, 31, 0, // Skip to: 8345 +/* 160 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 163 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 227 +/* 168 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 171 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 185 +/* 176 */ MCD_OPC_CheckPredicate, 0, 228, 31, 0, // Skip to: 8345 +/* 181 */ MCD_OPC_Decode, 161, 4, 2, // Opcode: ANDrsr +/* 185 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 199 +/* 190 */ MCD_OPC_CheckPredicate, 0, 214, 31, 0, // Skip to: 8345 +/* 195 */ MCD_OPC_Decode, 247, 6, 2, // Opcode: SUBrsr +/* 199 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 213 +/* 204 */ MCD_OPC_CheckPredicate, 0, 200, 31, 0, // Skip to: 8345 +/* 209 */ MCD_OPC_Decode, 152, 4, 2, // Opcode: ADDrsr +/* 213 */ MCD_OPC_FilterValue, 3, 191, 31, 0, // Skip to: 8345 +/* 218 */ MCD_OPC_CheckPredicate, 0, 186, 31, 0, // Skip to: 8345 +/* 223 */ MCD_OPC_Decode, 241, 5, 3, // Opcode: SBCrsr +/* 227 */ MCD_OPC_FilterValue, 1, 177, 31, 0, // Skip to: 8345 +/* 232 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... +/* 235 */ MCD_OPC_FilterValue, 0, 71, 0, 0, // Skip to: 311 +/* 240 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 243 */ MCD_OPC_FilterValue, 0, 14, 0, 0, // Skip to: 262 +/* 248 */ MCD_OPC_CheckPredicate, 1, 156, 31, 0, // Skip to: 8345 +/* 253 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 258 */ MCD_OPC_Decode, 188, 5, 4, // Opcode: MUL +/* 262 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 283 +/* 267 */ MCD_OPC_CheckPredicate, 1, 137, 31, 0, // Skip to: 8345 +/* 272 */ MCD_OPC_CheckField, 20, 1, 0, 130, 31, 0, // Skip to: 8345 +/* 279 */ MCD_OPC_Decode, 152, 7, 5, // Opcode: UMAAL +/* 283 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 297 +/* 288 */ MCD_OPC_CheckPredicate, 1, 116, 31, 0, // Skip to: 8345 +/* 293 */ MCD_OPC_Decode, 154, 7, 6, // Opcode: UMULL +/* 297 */ MCD_OPC_FilterValue, 3, 107, 31, 0, // Skip to: 8345 +/* 302 */ MCD_OPC_CheckPredicate, 1, 102, 31, 0, // Skip to: 8345 +/* 307 */ MCD_OPC_Decode, 165, 6, 6, // Opcode: SMULL +/* 311 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 347 +/* 316 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 319 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 333 +/* 324 */ MCD_OPC_CheckPredicate, 0, 80, 31, 0, // Skip to: 8345 +/* 329 */ MCD_OPC_Decode, 234, 6, 7, // Opcode: STRH_POST +/* 333 */ MCD_OPC_FilterValue, 1, 71, 31, 0, // Skip to: 8345 +/* 338 */ MCD_OPC_CheckPredicate, 0, 66, 31, 0, // Skip to: 8345 +/* 343 */ MCD_OPC_Decode, 143, 5, 7, // Opcode: LDRH_POST +/* 347 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 383 +/* 352 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 355 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 369 +/* 360 */ MCD_OPC_CheckPredicate, 0, 44, 31, 0, // Skip to: 8345 +/* 365 */ MCD_OPC_Decode, 134, 5, 7, // Opcode: LDRD_POST +/* 369 */ MCD_OPC_FilterValue, 1, 35, 31, 0, // Skip to: 8345 +/* 374 */ MCD_OPC_CheckPredicate, 0, 30, 31, 0, // Skip to: 8345 +/* 379 */ MCD_OPC_Decode, 148, 5, 7, // Opcode: LDRSB_POST +/* 383 */ MCD_OPC_FilterValue, 3, 21, 31, 0, // Skip to: 8345 +/* 388 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 391 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 405 +/* 396 */ MCD_OPC_CheckPredicate, 0, 8, 31, 0, // Skip to: 8345 +/* 401 */ MCD_OPC_Decode, 225, 6, 7, // Opcode: STRD_POST +/* 405 */ MCD_OPC_FilterValue, 1, 255, 30, 0, // Skip to: 8345 +/* 410 */ MCD_OPC_CheckPredicate, 0, 250, 30, 0, // Skip to: 8345 +/* 415 */ MCD_OPC_Decode, 153, 5, 7, // Opcode: LDRSH_POST +/* 419 */ MCD_OPC_FilterValue, 1, 241, 30, 0, // Skip to: 8345 +/* 424 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 427 */ MCD_OPC_FilterValue, 0, 6, 2, 0, // Skip to: 950 +/* 432 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 435 */ MCD_OPC_FilterValue, 0, 152, 1, 0, // Skip to: 848 +/* 440 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 443 */ MCD_OPC_FilterValue, 0, 66, 1, 0, // Skip to: 770 +/* 448 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... +/* 451 */ MCD_OPC_FilterValue, 14, 67, 0, 0, // Skip to: 523 +/* 456 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 459 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 491 +/* 464 */ MCD_OPC_CheckPredicate, 2, 171, 0, 0, // Skip to: 640 +/* 469 */ MCD_OPC_CheckField, 6, 2, 1, 164, 0, 0, // Skip to: 640 +/* 476 */ MCD_OPC_CheckField, 4, 1, 0, 157, 0, 0, // Skip to: 640 +/* 483 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, +/* 487 */ MCD_OPC_Decode, 194, 4, 8, // Opcode: CRC32B +/* 491 */ MCD_OPC_FilterValue, 1, 144, 0, 0, // Skip to: 640 +/* 496 */ MCD_OPC_CheckPredicate, 2, 139, 0, 0, // Skip to: 640 +/* 501 */ MCD_OPC_CheckField, 6, 2, 1, 132, 0, 0, // Skip to: 640 +/* 508 */ MCD_OPC_CheckField, 4, 1, 0, 125, 0, 0, // Skip to: 640 +/* 515 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, +/* 519 */ MCD_OPC_Decode, 195, 4, 8, // Opcode: CRC32CB +/* 523 */ MCD_OPC_FilterValue, 15, 112, 0, 0, // Skip to: 640 +/* 528 */ MCD_OPC_ExtractField, 10, 8, // Inst{17-10} ... +/* 531 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 559 +/* 536 */ MCD_OPC_CheckPredicate, 0, 99, 0, 0, // Skip to: 640 +/* 541 */ MCD_OPC_CheckField, 9, 1, 0, 92, 0, 0, // Skip to: 640 +/* 548 */ MCD_OPC_CheckField, 0, 5, 0, 85, 0, 0, // Skip to: 640 +/* 555 */ MCD_OPC_Decode, 192, 4, 9, // Opcode: CPS2p +/* 559 */ MCD_OPC_FilterValue, 64, 30, 0, 0, // Skip to: 594 +/* 564 */ MCD_OPC_CheckPredicate, 0, 71, 0, 0, // Skip to: 640 +/* 569 */ MCD_OPC_CheckField, 18, 2, 0, 64, 0, 0, // Skip to: 640 +/* 576 */ MCD_OPC_CheckField, 6, 3, 0, 57, 0, 0, // Skip to: 640 +/* 583 */ MCD_OPC_CheckField, 0, 5, 0, 50, 0, 0, // Skip to: 640 +/* 590 */ MCD_OPC_Decode, 245, 5, 10, // Opcode: SETEND +/* 594 */ MCD_OPC_FilterValue, 128, 1, 40, 0, 0, // Skip to: 640 +/* 600 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 603 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 640 +/* 608 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 631 +/* 613 */ MCD_OPC_CheckField, 18, 2, 0, 11, 0, 0, // Skip to: 631 +/* 620 */ MCD_OPC_CheckField, 6, 3, 0, 4, 0, 0, // Skip to: 631 +/* 627 */ MCD_OPC_Decode, 191, 4, 9, // Opcode: CPS1p +/* 631 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 640 +/* 636 */ MCD_OPC_Decode, 193, 4, 9, // Opcode: CPS3p +/* 640 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 643 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 684 +/* 648 */ MCD_OPC_CheckPredicate, 0, 88, 4, 0, // Skip to: 1765 +/* 653 */ MCD_OPC_CheckField, 16, 1, 1, 81, 4, 0, // Skip to: 1765 +/* 660 */ MCD_OPC_CheckField, 9, 1, 0, 74, 4, 0, // Skip to: 1765 +/* 667 */ MCD_OPC_CheckField, 4, 1, 0, 67, 4, 0, // Skip to: 1765 +/* 674 */ MCD_OPC_SoftFail, 143, 26 /* 0xd0f */, 128, 128, 56 /* 0xe0000 */, +/* 680 */ MCD_OPC_Decode, 182, 5, 11, // Opcode: MRS +/* 684 */ MCD_OPC_FilterValue, 1, 20, 0, 0, // Skip to: 709 +/* 689 */ MCD_OPC_CheckPredicate, 0, 47, 4, 0, // Skip to: 1765 +/* 694 */ MCD_OPC_CheckField, 4, 1, 1, 40, 4, 0, // Skip to: 1765 +/* 701 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, +/* 705 */ MCD_OPC_Decode, 205, 5, 12, // Opcode: QADD +/* 709 */ MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 749 +/* 714 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 717 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 731 +/* 722 */ MCD_OPC_CheckPredicate, 3, 14, 4, 0, // Skip to: 1765 +/* 727 */ MCD_OPC_Decode, 136, 6, 13, // Opcode: SMLABB +/* 731 */ MCD_OPC_FilterValue, 1, 5, 4, 0, // Skip to: 1765 +/* 736 */ MCD_OPC_CheckPredicate, 4, 0, 4, 0, // Skip to: 1765 +/* 741 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, +/* 745 */ MCD_OPC_Decode, 249, 6, 14, // Opcode: SWP +/* 749 */ MCD_OPC_FilterValue, 3, 243, 3, 0, // Skip to: 1765 +/* 754 */ MCD_OPC_CheckPredicate, 3, 238, 3, 0, // Skip to: 1765 +/* 759 */ MCD_OPC_CheckField, 4, 1, 0, 231, 3, 0, // Skip to: 1765 +/* 766 */ MCD_OPC_Decode, 137, 6, 13, // Opcode: SMLABT +/* 770 */ MCD_OPC_FilterValue, 1, 222, 3, 0, // Skip to: 1765 +/* 775 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 778 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 806 +/* 783 */ MCD_OPC_CheckPredicate, 5, 209, 3, 0, // Skip to: 1765 +/* 788 */ MCD_OPC_CheckField, 28, 4, 14, 202, 3, 0, // Skip to: 1765 +/* 795 */ MCD_OPC_CheckField, 4, 1, 1, 195, 3, 0, // Skip to: 1765 +/* 802 */ MCD_OPC_Decode, 219, 4, 15, // Opcode: HLT +/* 806 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 827 +/* 811 */ MCD_OPC_CheckPredicate, 3, 181, 3, 0, // Skip to: 1765 +/* 816 */ MCD_OPC_CheckField, 4, 1, 0, 174, 3, 0, // Skip to: 1765 +/* 823 */ MCD_OPC_Decode, 147, 6, 13, // Opcode: SMLATB +/* 827 */ MCD_OPC_FilterValue, 3, 165, 3, 0, // Skip to: 1765 +/* 832 */ MCD_OPC_CheckPredicate, 3, 160, 3, 0, // Skip to: 1765 +/* 837 */ MCD_OPC_CheckField, 4, 1, 0, 153, 3, 0, // Skip to: 1765 +/* 844 */ MCD_OPC_Decode, 148, 6, 13, // Opcode: SMLATT +/* 848 */ MCD_OPC_FilterValue, 1, 144, 3, 0, // Skip to: 1765 +/* 853 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 856 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 924 +/* 861 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 882 +/* 866 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 882 +/* 873 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 878 */ MCD_OPC_Decode, 137, 7, 16, // Opcode: TSTrr +/* 882 */ MCD_OPC_CheckPredicate, 6, 23, 0, 0, // Skip to: 910 +/* 887 */ MCD_OPC_CheckField, 28, 4, 15, 16, 0, 0, // Skip to: 910 +/* 894 */ MCD_OPC_CheckField, 5, 3, 0, 9, 0, 0, // Skip to: 910 +/* 901 */ MCD_OPC_SoftFail, 143, 250, 63 /* 0xffd0f */, 0, +/* 906 */ MCD_OPC_Decode, 246, 5, 10, // Opcode: SETPAN +/* 910 */ MCD_OPC_CheckPredicate, 0, 82, 3, 0, // Skip to: 1765 +/* 915 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 920 */ MCD_OPC_Decode, 138, 7, 17, // Opcode: TSTrsi +/* 924 */ MCD_OPC_FilterValue, 1, 68, 3, 0, // Skip to: 1765 +/* 929 */ MCD_OPC_CheckPredicate, 0, 63, 3, 0, // Skip to: 1765 +/* 934 */ MCD_OPC_CheckField, 7, 1, 0, 56, 3, 0, // Skip to: 1765 +/* 941 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 946 */ MCD_OPC_Decode, 139, 7, 18, // Opcode: TSTrsr +/* 950 */ MCD_OPC_FilterValue, 1, 62, 1, 0, // Skip to: 1273 +/* 955 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 958 */ MCD_OPC_FilterValue, 0, 192, 0, 0, // Skip to: 1155 +/* 963 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 966 */ MCD_OPC_FilterValue, 0, 144, 0, 0, // Skip to: 1115 +/* 971 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 974 */ MCD_OPC_FilterValue, 0, 22, 0, 0, // Skip to: 1001 +/* 979 */ MCD_OPC_CheckPredicate, 0, 13, 3, 0, // Skip to: 1765 +/* 984 */ MCD_OPC_CheckField, 9, 1, 0, 6, 3, 0, // Skip to: 1765 +/* 991 */ MCD_OPC_SoftFail, 143, 26 /* 0xd0f */, 128, 128, 60 /* 0xf0000 */, +/* 997 */ MCD_OPC_Decode, 184, 5, 11, // Opcode: MRSsys +/* 1001 */ MCD_OPC_FilterValue, 2, 53, 0, 0, // Skip to: 1059 +/* 1006 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 1009 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 1034 +/* 1014 */ MCD_OPC_CheckPredicate, 2, 234, 2, 0, // Skip to: 1765 +/* 1019 */ MCD_OPC_CheckField, 28, 4, 14, 227, 2, 0, // Skip to: 1765 +/* 1026 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, +/* 1030 */ MCD_OPC_Decode, 199, 4, 8, // Opcode: CRC32W +/* 1034 */ MCD_OPC_FilterValue, 1, 214, 2, 0, // Skip to: 1765 +/* 1039 */ MCD_OPC_CheckPredicate, 2, 209, 2, 0, // Skip to: 1765 +/* 1044 */ MCD_OPC_CheckField, 28, 4, 14, 202, 2, 0, // Skip to: 1765 +/* 1051 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, +/* 1055 */ MCD_OPC_Decode, 197, 4, 8, // Opcode: CRC32CW +/* 1059 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1073 +/* 1064 */ MCD_OPC_CheckPredicate, 3, 184, 2, 0, // Skip to: 1765 +/* 1069 */ MCD_OPC_Decode, 141, 6, 19, // Opcode: SMLALBB +/* 1073 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1087 +/* 1078 */ MCD_OPC_CheckPredicate, 3, 170, 2, 0, // Skip to: 1765 +/* 1083 */ MCD_OPC_Decode, 145, 6, 19, // Opcode: SMLALTB +/* 1087 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1101 +/* 1092 */ MCD_OPC_CheckPredicate, 3, 156, 2, 0, // Skip to: 1765 +/* 1097 */ MCD_OPC_Decode, 142, 6, 19, // Opcode: SMLALBT +/* 1101 */ MCD_OPC_FilterValue, 7, 147, 2, 0, // Skip to: 1765 +/* 1106 */ MCD_OPC_CheckPredicate, 3, 142, 2, 0, // Skip to: 1765 +/* 1111 */ MCD_OPC_Decode, 146, 6, 19, // Opcode: SMLALTT +/* 1115 */ MCD_OPC_FilterValue, 1, 133, 2, 0, // Skip to: 1765 +/* 1120 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 1141 +/* 1125 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 1141 +/* 1132 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 1137 */ MCD_OPC_Decode, 188, 4, 20, // Opcode: CMPrr +/* 1141 */ MCD_OPC_CheckPredicate, 0, 107, 2, 0, // Skip to: 1765 +/* 1146 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 1151 */ MCD_OPC_Decode, 189, 4, 17, // Opcode: CMPrsi +/* 1155 */ MCD_OPC_FilterValue, 1, 93, 2, 0, // Skip to: 1765 +/* 1160 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 1163 */ MCD_OPC_FilterValue, 0, 73, 0, 0, // Skip to: 1241 +/* 1168 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1171 */ MCD_OPC_FilterValue, 0, 46, 0, 0, // Skip to: 1222 +/* 1176 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... +/* 1179 */ MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 1197 +/* 1184 */ MCD_OPC_CheckPredicate, 0, 64, 2, 0, // Skip to: 1765 +/* 1189 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, +/* 1193 */ MCD_OPC_Decode, 209, 5, 21, // Opcode: QDADD +/* 1197 */ MCD_OPC_FilterValue, 3, 51, 2, 0, // Skip to: 1765 +/* 1202 */ MCD_OPC_CheckPredicate, 7, 46, 2, 0, // Skip to: 1765 +/* 1207 */ MCD_OPC_SoftFail, 128, 128, 128, 128, 1 /* 0x10000000 */, 128, 128, 128, 128, 14 /* 0xffffffffe0000000 */, +/* 1218 */ MCD_OPC_Decode, 220, 4, 15, // Opcode: HVC +/* 1222 */ MCD_OPC_FilterValue, 1, 26, 2, 0, // Skip to: 1765 +/* 1227 */ MCD_OPC_CheckPredicate, 0, 21, 2, 0, // Skip to: 1765 +/* 1232 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 1237 */ MCD_OPC_Decode, 190, 4, 18, // Opcode: CMPrsr +/* 1241 */ MCD_OPC_FilterValue, 1, 7, 2, 0, // Skip to: 1765 +/* 1246 */ MCD_OPC_CheckPredicate, 4, 2, 2, 0, // Skip to: 1765 +/* 1251 */ MCD_OPC_CheckField, 20, 1, 0, 251, 1, 0, // Skip to: 1765 +/* 1258 */ MCD_OPC_CheckField, 5, 2, 0, 244, 1, 0, // Skip to: 1765 +/* 1265 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, +/* 1269 */ MCD_OPC_Decode, 250, 6, 14, // Opcode: SWPB +/* 1273 */ MCD_OPC_FilterValue, 2, 241, 0, 0, // Skip to: 1519 +/* 1278 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 1281 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1311 +/* 1286 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1302 +/* 1291 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1302 +/* 1298 */ MCD_OPC_Decode, 194, 5, 0, // Opcode: ORRrr +/* 1302 */ MCD_OPC_CheckPredicate, 0, 202, 1, 0, // Skip to: 1765 +/* 1307 */ MCD_OPC_Decode, 195, 5, 1, // Opcode: ORRrsi +/* 1311 */ MCD_OPC_FilterValue, 1, 193, 1, 0, // Skip to: 1765 +/* 1316 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 1319 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1333 +/* 1324 */ MCD_OPC_CheckPredicate, 0, 180, 1, 0, // Skip to: 1765 +/* 1329 */ MCD_OPC_Decode, 196, 5, 2, // Opcode: ORRrsr +/* 1333 */ MCD_OPC_FilterValue, 1, 171, 1, 0, // Skip to: 1765 +/* 1338 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1341 */ MCD_OPC_FilterValue, 12, 59, 0, 0, // Skip to: 1405 +/* 1346 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1349 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1377 +/* 1354 */ MCD_OPC_CheckPredicate, 8, 150, 1, 0, // Skip to: 1765 +/* 1359 */ MCD_OPC_CheckField, 12, 4, 15, 143, 1, 0, // Skip to: 1765 +/* 1366 */ MCD_OPC_CheckField, 5, 2, 0, 136, 1, 0, // Skip to: 1765 +/* 1373 */ MCD_OPC_Decode, 201, 6, 22, // Opcode: STL +/* 1377 */ MCD_OPC_FilterValue, 1, 127, 1, 0, // Skip to: 1765 +/* 1382 */ MCD_OPC_CheckPredicate, 8, 122, 1, 0, // Skip to: 1765 +/* 1387 */ MCD_OPC_CheckField, 5, 2, 0, 115, 1, 0, // Skip to: 1765 +/* 1394 */ MCD_OPC_CheckField, 0, 4, 15, 108, 1, 0, // Skip to: 1765 +/* 1401 */ MCD_OPC_Decode, 222, 4, 23, // Opcode: LDA +/* 1405 */ MCD_OPC_FilterValue, 14, 52, 0, 0, // Skip to: 1462 +/* 1410 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1413 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1434 +/* 1418 */ MCD_OPC_CheckPredicate, 9, 86, 1, 0, // Skip to: 1765 +/* 1423 */ MCD_OPC_CheckField, 5, 2, 0, 79, 1, 0, // Skip to: 1765 +/* 1430 */ MCD_OPC_Decode, 203, 6, 24, // Opcode: STLEX +/* 1434 */ MCD_OPC_FilterValue, 1, 70, 1, 0, // Skip to: 1765 +/* 1439 */ MCD_OPC_CheckPredicate, 9, 65, 1, 0, // Skip to: 1765 +/* 1444 */ MCD_OPC_CheckField, 5, 2, 0, 58, 1, 0, // Skip to: 1765 +/* 1451 */ MCD_OPC_CheckField, 0, 4, 15, 51, 1, 0, // Skip to: 1765 +/* 1458 */ MCD_OPC_Decode, 224, 4, 23, // Opcode: LDAEX +/* 1462 */ MCD_OPC_FilterValue, 15, 42, 1, 0, // Skip to: 1765 +/* 1467 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1470 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1491 +/* 1475 */ MCD_OPC_CheckPredicate, 0, 29, 1, 0, // Skip to: 1765 +/* 1480 */ MCD_OPC_CheckField, 5, 2, 0, 22, 1, 0, // Skip to: 1765 +/* 1487 */ MCD_OPC_Decode, 227, 6, 24, // Opcode: STREX +/* 1491 */ MCD_OPC_FilterValue, 1, 13, 1, 0, // Skip to: 1765 +/* 1496 */ MCD_OPC_CheckPredicate, 0, 8, 1, 0, // Skip to: 1765 +/* 1501 */ MCD_OPC_CheckField, 5, 2, 0, 1, 1, 0, // Skip to: 1765 +/* 1508 */ MCD_OPC_CheckField, 0, 4, 15, 250, 0, 0, // Skip to: 1765 +/* 1515 */ MCD_OPC_Decode, 136, 5, 23, // Opcode: LDREX +/* 1519 */ MCD_OPC_FilterValue, 3, 241, 0, 0, // Skip to: 1765 +/* 1524 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 1527 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1557 +/* 1532 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1548 +/* 1537 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1548 +/* 1544 */ MCD_OPC_Decode, 165, 4, 0, // Opcode: BICrr +/* 1548 */ MCD_OPC_CheckPredicate, 0, 212, 0, 0, // Skip to: 1765 +/* 1553 */ MCD_OPC_Decode, 166, 4, 1, // Opcode: BICrsi +/* 1557 */ MCD_OPC_FilterValue, 1, 203, 0, 0, // Skip to: 1765 +/* 1562 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 1565 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1579 +/* 1570 */ MCD_OPC_CheckPredicate, 0, 190, 0, 0, // Skip to: 1765 +/* 1575 */ MCD_OPC_Decode, 167, 4, 2, // Opcode: BICrsr +/* 1579 */ MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 1765 +/* 1584 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1587 */ MCD_OPC_FilterValue, 12, 59, 0, 0, // Skip to: 1651 +/* 1592 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1595 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1623 +/* 1600 */ MCD_OPC_CheckPredicate, 8, 160, 0, 0, // Skip to: 1765 +/* 1605 */ MCD_OPC_CheckField, 12, 4, 15, 153, 0, 0, // Skip to: 1765 +/* 1612 */ MCD_OPC_CheckField, 5, 2, 0, 146, 0, 0, // Skip to: 1765 +/* 1619 */ MCD_OPC_Decode, 202, 6, 22, // Opcode: STLB +/* 1623 */ MCD_OPC_FilterValue, 1, 137, 0, 0, // Skip to: 1765 +/* 1628 */ MCD_OPC_CheckPredicate, 8, 132, 0, 0, // Skip to: 1765 +/* 1633 */ MCD_OPC_CheckField, 5, 2, 0, 125, 0, 0, // Skip to: 1765 +/* 1640 */ MCD_OPC_CheckField, 0, 4, 15, 118, 0, 0, // Skip to: 1765 +/* 1647 */ MCD_OPC_Decode, 223, 4, 23, // Opcode: LDAB +/* 1651 */ MCD_OPC_FilterValue, 14, 52, 0, 0, // Skip to: 1708 +/* 1656 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1659 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1680 +/* 1664 */ MCD_OPC_CheckPredicate, 9, 96, 0, 0, // Skip to: 1765 +/* 1669 */ MCD_OPC_CheckField, 5, 2, 0, 89, 0, 0, // Skip to: 1765 +/* 1676 */ MCD_OPC_Decode, 204, 6, 24, // Opcode: STLEXB +/* 1680 */ MCD_OPC_FilterValue, 1, 80, 0, 0, // Skip to: 1765 +/* 1685 */ MCD_OPC_CheckPredicate, 9, 75, 0, 0, // Skip to: 1765 +/* 1690 */ MCD_OPC_CheckField, 5, 2, 0, 68, 0, 0, // Skip to: 1765 +/* 1697 */ MCD_OPC_CheckField, 0, 4, 15, 61, 0, 0, // Skip to: 1765 +/* 1704 */ MCD_OPC_Decode, 225, 4, 23, // Opcode: LDAEXB +/* 1708 */ MCD_OPC_FilterValue, 15, 52, 0, 0, // Skip to: 1765 +/* 1713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1716 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1737 +/* 1721 */ MCD_OPC_CheckPredicate, 0, 39, 0, 0, // Skip to: 1765 +/* 1726 */ MCD_OPC_CheckField, 5, 2, 0, 32, 0, 0, // Skip to: 1765 +/* 1733 */ MCD_OPC_Decode, 228, 6, 24, // Opcode: STREXB +/* 1737 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 1765 +/* 1742 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 1765 +/* 1747 */ MCD_OPC_CheckField, 5, 2, 0, 11, 0, 0, // Skip to: 1765 +/* 1754 */ MCD_OPC_CheckField, 0, 4, 15, 4, 0, 0, // Skip to: 1765 +/* 1761 */ MCD_OPC_Decode, 137, 5, 23, // Opcode: LDREXB +/* 1765 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 1768 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 1810 +/* 1773 */ MCD_OPC_CheckPredicate, 7, 167, 25, 0, // Skip to: 8345 +/* 1778 */ MCD_OPC_CheckField, 23, 1, 0, 160, 25, 0, // Skip to: 8345 +/* 1785 */ MCD_OPC_CheckField, 20, 1, 0, 153, 25, 0, // Skip to: 8345 +/* 1792 */ MCD_OPC_CheckField, 9, 3, 1, 146, 25, 0, // Skip to: 8345 +/* 1799 */ MCD_OPC_CheckField, 0, 4, 0, 139, 25, 0, // Skip to: 8345 +/* 1806 */ MCD_OPC_Decode, 183, 5, 25, // Opcode: MRSbanked +/* 1810 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 1846 +/* 1815 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1818 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1832 +/* 1823 */ MCD_OPC_CheckPredicate, 0, 117, 25, 0, // Skip to: 8345 +/* 1828 */ MCD_OPC_Decode, 231, 6, 7, // Opcode: STRH +/* 1832 */ MCD_OPC_FilterValue, 1, 108, 25, 0, // Skip to: 8345 +/* 1837 */ MCD_OPC_CheckPredicate, 0, 103, 25, 0, // Skip to: 8345 +/* 1842 */ MCD_OPC_Decode, 140, 5, 7, // Opcode: LDRH +/* 1846 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 1882 +/* 1851 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1854 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1868 +/* 1859 */ MCD_OPC_CheckPredicate, 3, 81, 25, 0, // Skip to: 8345 +/* 1864 */ MCD_OPC_Decode, 133, 5, 7, // Opcode: LDRD +/* 1868 */ MCD_OPC_FilterValue, 1, 72, 25, 0, // Skip to: 8345 +/* 1873 */ MCD_OPC_CheckPredicate, 0, 67, 25, 0, // Skip to: 8345 +/* 1878 */ MCD_OPC_Decode, 145, 5, 7, // Opcode: LDRSB +/* 1882 */ MCD_OPC_FilterValue, 15, 58, 25, 0, // Skip to: 8345 +/* 1887 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1890 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1904 +/* 1895 */ MCD_OPC_CheckPredicate, 3, 45, 25, 0, // Skip to: 8345 +/* 1900 */ MCD_OPC_Decode, 224, 6, 7, // Opcode: STRD +/* 1904 */ MCD_OPC_FilterValue, 1, 36, 25, 0, // Skip to: 8345 +/* 1909 */ MCD_OPC_CheckPredicate, 0, 31, 25, 0, // Skip to: 8345 +/* 1914 */ MCD_OPC_Decode, 150, 5, 7, // Opcode: LDRSH +/* 1918 */ MCD_OPC_FilterValue, 1, 22, 25, 0, // Skip to: 8345 +/* 1923 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 1926 */ MCD_OPC_FilterValue, 0, 180, 2, 0, // Skip to: 2623 +/* 1931 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 1934 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 2002 +/* 1939 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1942 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1972 +/* 1947 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1963 +/* 1952 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1963 +/* 1959 */ MCD_OPC_Decode, 204, 4, 0, // Opcode: EORrr +/* 1963 */ MCD_OPC_CheckPredicate, 0, 233, 24, 0, // Skip to: 8345 +/* 1968 */ MCD_OPC_Decode, 205, 4, 1, // Opcode: EORrsi +/* 1972 */ MCD_OPC_FilterValue, 1, 224, 24, 0, // Skip to: 8345 +/* 1977 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1993 +/* 1982 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1993 +/* 1989 */ MCD_OPC_Decode, 228, 5, 0, // Opcode: RSBrr +/* 1993 */ MCD_OPC_CheckPredicate, 0, 203, 24, 0, // Skip to: 8345 +/* 1998 */ MCD_OPC_Decode, 229, 5, 1, // Opcode: RSBrsi +/* 2002 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 2070 +/* 2007 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2010 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2040 +/* 2015 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2031 +/* 2020 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 2031 +/* 2027 */ MCD_OPC_Decode, 146, 4, 0, // Opcode: ADCrr +/* 2031 */ MCD_OPC_CheckPredicate, 0, 165, 24, 0, // Skip to: 8345 +/* 2036 */ MCD_OPC_Decode, 147, 4, 1, // Opcode: ADCrsi +/* 2040 */ MCD_OPC_FilterValue, 1, 156, 24, 0, // Skip to: 8345 +/* 2045 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2061 +/* 2050 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 2061 +/* 2057 */ MCD_OPC_Decode, 232, 5, 0, // Opcode: RSCrr +/* 2061 */ MCD_OPC_CheckPredicate, 0, 135, 24, 0, // Skip to: 8345 +/* 2066 */ MCD_OPC_Decode, 233, 5, 1, // Opcode: RSCrsi +/* 2070 */ MCD_OPC_FilterValue, 2, 166, 1, 0, // Skip to: 2497 +/* 2075 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 2078 */ MCD_OPC_FilterValue, 0, 70, 1, 0, // Skip to: 2409 +/* 2083 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 2086 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 2129 +/* 2091 */ MCD_OPC_ExtractField, 9, 7, // Inst{15-9} ... +/* 2094 */ MCD_OPC_FilterValue, 120, 16, 0, 0, // Skip to: 2115 +/* 2099 */ MCD_OPC_CheckPredicate, 0, 97, 24, 0, // Skip to: 8345 +/* 2104 */ MCD_OPC_CheckField, 8, 1, 0, 90, 24, 0, // Skip to: 8345 +/* 2111 */ MCD_OPC_Decode, 185, 5, 26, // Opcode: MSR +/* 2115 */ MCD_OPC_FilterValue, 121, 81, 24, 0, // Skip to: 8345 +/* 2120 */ MCD_OPC_CheckPredicate, 7, 76, 24, 0, // Skip to: 8345 +/* 2125 */ MCD_OPC_Decode, 186, 5, 27, // Opcode: MSRbanked +/* 2129 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2158 +/* 2134 */ MCD_OPC_CheckPredicate, 0, 62, 24, 0, // Skip to: 8345 +/* 2139 */ MCD_OPC_CheckField, 22, 1, 0, 55, 24, 0, // Skip to: 8345 +/* 2146 */ MCD_OPC_CheckField, 8, 12, 255, 31, 47, 24, 0, // Skip to: 8345 +/* 2154 */ MCD_OPC_Decode, 175, 4, 28, // Opcode: BXJ +/* 2158 */ MCD_OPC_FilterValue, 2, 67, 0, 0, // Skip to: 2230 +/* 2163 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 2166 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2198 +/* 2171 */ MCD_OPC_CheckPredicate, 2, 25, 24, 0, // Skip to: 8345 +/* 2176 */ MCD_OPC_CheckField, 28, 4, 14, 18, 24, 0, // Skip to: 8345 +/* 2183 */ MCD_OPC_CheckField, 22, 1, 0, 11, 24, 0, // Skip to: 8345 +/* 2190 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, +/* 2194 */ MCD_OPC_Decode, 198, 4, 8, // Opcode: CRC32H +/* 2198 */ MCD_OPC_FilterValue, 1, 254, 23, 0, // Skip to: 8345 +/* 2203 */ MCD_OPC_CheckPredicate, 2, 249, 23, 0, // Skip to: 8345 +/* 2208 */ MCD_OPC_CheckField, 28, 4, 14, 242, 23, 0, // Skip to: 8345 +/* 2215 */ MCD_OPC_CheckField, 22, 1, 0, 235, 23, 0, // Skip to: 8345 +/* 2222 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, +/* 2226 */ MCD_OPC_Decode, 196, 4, 8, // Opcode: CRC32CH +/* 2230 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 2265 +/* 2235 */ MCD_OPC_CheckPredicate, 7, 217, 23, 0, // Skip to: 8345 +/* 2240 */ MCD_OPC_CheckField, 22, 1, 1, 210, 23, 0, // Skip to: 8345 +/* 2247 */ MCD_OPC_CheckField, 8, 12, 0, 203, 23, 0, // Skip to: 8345 +/* 2254 */ MCD_OPC_CheckField, 0, 4, 14, 196, 23, 0, // Skip to: 8345 +/* 2261 */ MCD_OPC_Decode, 207, 4, 29, // Opcode: ERET +/* 2265 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 2301 +/* 2270 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2273 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2287 +/* 2278 */ MCD_OPC_CheckPredicate, 3, 174, 23, 0, // Skip to: 8345 +/* 2283 */ MCD_OPC_Decode, 149, 6, 13, // Opcode: SMLAWB +/* 2287 */ MCD_OPC_FilterValue, 1, 165, 23, 0, // Skip to: 8345 +/* 2292 */ MCD_OPC_CheckPredicate, 3, 160, 23, 0, // Skip to: 8345 +/* 2297 */ MCD_OPC_Decode, 163, 6, 30, // Opcode: SMULBB +/* 2301 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 2337 +/* 2306 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2309 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2323 +/* 2314 */ MCD_OPC_CheckPredicate, 3, 138, 23, 0, // Skip to: 8345 +/* 2319 */ MCD_OPC_Decode, 168, 6, 30, // Opcode: SMULWB +/* 2323 */ MCD_OPC_FilterValue, 1, 129, 23, 0, // Skip to: 8345 +/* 2328 */ MCD_OPC_CheckPredicate, 3, 124, 23, 0, // Skip to: 8345 +/* 2333 */ MCD_OPC_Decode, 166, 6, 30, // Opcode: SMULTB +/* 2337 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 2373 +/* 2342 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2345 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2359 +/* 2350 */ MCD_OPC_CheckPredicate, 3, 102, 23, 0, // Skip to: 8345 +/* 2355 */ MCD_OPC_Decode, 150, 6, 13, // Opcode: SMLAWT +/* 2359 */ MCD_OPC_FilterValue, 1, 93, 23, 0, // Skip to: 8345 +/* 2364 */ MCD_OPC_CheckPredicate, 3, 88, 23, 0, // Skip to: 8345 +/* 2369 */ MCD_OPC_Decode, 164, 6, 30, // Opcode: SMULBT +/* 2373 */ MCD_OPC_FilterValue, 7, 79, 23, 0, // Skip to: 8345 +/* 2378 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2381 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2395 +/* 2386 */ MCD_OPC_CheckPredicate, 3, 66, 23, 0, // Skip to: 8345 +/* 2391 */ MCD_OPC_Decode, 169, 6, 30, // Opcode: SMULWT +/* 2395 */ MCD_OPC_FilterValue, 1, 57, 23, 0, // Skip to: 8345 +/* 2400 */ MCD_OPC_CheckPredicate, 3, 52, 23, 0, // Skip to: 8345 +/* 2405 */ MCD_OPC_Decode, 167, 6, 30, // Opcode: SMULTT +/* 2409 */ MCD_OPC_FilterValue, 1, 43, 23, 0, // Skip to: 8345 +/* 2414 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2417 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2457 +/* 2422 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2443 +/* 2427 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2443 +/* 2434 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 2439 */ MCD_OPC_Decode, 130, 7, 20, // Opcode: TEQrr +/* 2443 */ MCD_OPC_CheckPredicate, 0, 9, 23, 0, // Skip to: 8345 +/* 2448 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 2453 */ MCD_OPC_Decode, 131, 7, 17, // Opcode: TEQrsi +/* 2457 */ MCD_OPC_FilterValue, 1, 251, 22, 0, // Skip to: 8345 +/* 2462 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2483 +/* 2467 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2483 +/* 2474 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 2479 */ MCD_OPC_Decode, 184, 4, 20, // Opcode: CMNzrr +/* 2483 */ MCD_OPC_CheckPredicate, 0, 225, 22, 0, // Skip to: 8345 +/* 2488 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 2493 */ MCD_OPC_Decode, 185, 4, 17, // Opcode: CMNzrsi +/* 2497 */ MCD_OPC_FilterValue, 3, 211, 22, 0, // Skip to: 8345 +/* 2502 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2505 */ MCD_OPC_FilterValue, 0, 73, 0, 0, // Skip to: 2583 +/* 2510 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 2534 +/* 2515 */ MCD_OPC_CheckField, 5, 16, 128, 15, 11, 0, 0, // Skip to: 2534 +/* 2523 */ MCD_OPC_CheckField, 0, 4, 14, 4, 0, 0, // Skip to: 2534 +/* 2530 */ MCD_OPC_Decode, 170, 5, 29, // Opcode: MOVPCLR +/* 2534 */ MCD_OPC_ExtractField, 5, 7, // Inst{11-5} ... +/* 2537 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2567 +/* 2542 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2558 +/* 2547 */ MCD_OPC_CheckField, 16, 4, 0, 4, 0, 0, // Skip to: 2558 +/* 2554 */ MCD_OPC_Decode, 174, 5, 31, // Opcode: MOVr +/* 2558 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 2567 +/* 2563 */ MCD_OPC_Decode, 175, 5, 32, // Opcode: MOVr_TC +/* 2567 */ MCD_OPC_CheckPredicate, 0, 141, 22, 0, // Skip to: 8345 +/* 2572 */ MCD_OPC_CheckField, 16, 4, 0, 134, 22, 0, // Skip to: 8345 +/* 2579 */ MCD_OPC_Decode, 176, 5, 33, // Opcode: MOVsi +/* 2583 */ MCD_OPC_FilterValue, 1, 125, 22, 0, // Skip to: 8345 +/* 2588 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2609 +/* 2593 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2609 +/* 2600 */ MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0, +/* 2605 */ MCD_OPC_Decode, 190, 5, 31, // Opcode: MVNr +/* 2609 */ MCD_OPC_CheckPredicate, 0, 99, 22, 0, // Skip to: 8345 +/* 2614 */ MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0, +/* 2619 */ MCD_OPC_Decode, 191, 5, 33, // Opcode: MVNsi +/* 2623 */ MCD_OPC_FilterValue, 1, 85, 22, 0, // Skip to: 8345 +/* 2628 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 2631 */ MCD_OPC_FilterValue, 0, 113, 1, 0, // Skip to: 3005 +/* 2636 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... +/* 2639 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2653 +/* 2644 */ MCD_OPC_CheckPredicate, 0, 64, 22, 0, // Skip to: 8345 +/* 2649 */ MCD_OPC_Decode, 206, 4, 2, // Opcode: EORrsr +/* 2653 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2667 +/* 2658 */ MCD_OPC_CheckPredicate, 0, 50, 22, 0, // Skip to: 8345 +/* 2663 */ MCD_OPC_Decode, 230, 5, 2, // Opcode: RSBrsr +/* 2667 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2681 +/* 2672 */ MCD_OPC_CheckPredicate, 0, 36, 22, 0, // Skip to: 8345 +/* 2677 */ MCD_OPC_Decode, 148, 4, 3, // Opcode: ADCrsr +/* 2681 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2695 +/* 2686 */ MCD_OPC_CheckPredicate, 0, 22, 22, 0, // Skip to: 8345 +/* 2691 */ MCD_OPC_Decode, 234, 5, 2, // Opcode: RSCrsr +/* 2695 */ MCD_OPC_FilterValue, 4, 163, 0, 0, // Skip to: 2863 +/* 2700 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 2703 */ MCD_OPC_FilterValue, 0, 136, 0, 0, // Skip to: 2844 +/* 2708 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... +/* 2711 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 2766 +/* 2716 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... +/* 2719 */ MCD_OPC_FilterValue, 255, 31, 244, 21, 0, // Skip to: 8345 +/* 2725 */ MCD_OPC_CheckPredicate, 10, 11, 0, 0, // Skip to: 2741 +/* 2730 */ MCD_OPC_CheckField, 0, 4, 14, 4, 0, 0, // Skip to: 2741 +/* 2737 */ MCD_OPC_Decode, 176, 4, 29, // Opcode: BX_RET +/* 2741 */ MCD_OPC_CheckPredicate, 10, 11, 0, 0, // Skip to: 2757 +/* 2746 */ MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 2757 +/* 2753 */ MCD_OPC_Decode, 174, 4, 34, // Opcode: BX +/* 2757 */ MCD_OPC_CheckPredicate, 10, 207, 21, 0, // Skip to: 8345 +/* 2762 */ MCD_OPC_Decode, 177, 4, 28, // Opcode: BX_pred +/* 2766 */ MCD_OPC_FilterValue, 1, 34, 0, 0, // Skip to: 2805 +/* 2771 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... +/* 2774 */ MCD_OPC_FilterValue, 255, 31, 189, 21, 0, // Skip to: 8345 +/* 2780 */ MCD_OPC_CheckPredicate, 11, 11, 0, 0, // Skip to: 2796 +/* 2785 */ MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 2796 +/* 2792 */ MCD_OPC_Decode, 170, 4, 34, // Opcode: BLX +/* 2796 */ MCD_OPC_CheckPredicate, 11, 168, 21, 0, // Skip to: 8345 +/* 2801 */ MCD_OPC_Decode, 171, 4, 28, // Opcode: BLX_pred +/* 2805 */ MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 2823 +/* 2810 */ MCD_OPC_CheckPredicate, 0, 154, 21, 0, // Skip to: 8345 +/* 2815 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, +/* 2819 */ MCD_OPC_Decode, 212, 5, 21, // Opcode: QSUB +/* 2823 */ MCD_OPC_FilterValue, 3, 141, 21, 0, // Skip to: 8345 +/* 2828 */ MCD_OPC_CheckPredicate, 0, 136, 21, 0, // Skip to: 8345 +/* 2833 */ MCD_OPC_CheckField, 28, 4, 14, 129, 21, 0, // Skip to: 8345 +/* 2840 */ MCD_OPC_Decode, 168, 4, 15, // Opcode: BKPT +/* 2844 */ MCD_OPC_FilterValue, 1, 120, 21, 0, // Skip to: 8345 +/* 2849 */ MCD_OPC_CheckPredicate, 0, 115, 21, 0, // Skip to: 8345 +/* 2854 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 2859 */ MCD_OPC_Decode, 132, 7, 18, // Opcode: TEQrsr +/* 2863 */ MCD_OPC_FilterValue, 5, 97, 0, 0, // Skip to: 2965 +/* 2868 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 2871 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 2946 +/* 2876 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... +/* 2879 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 2907 +/* 2884 */ MCD_OPC_CheckPredicate, 11, 80, 21, 0, // Skip to: 8345 +/* 2889 */ MCD_OPC_CheckField, 16, 4, 15, 73, 21, 0, // Skip to: 8345 +/* 2896 */ MCD_OPC_CheckField, 8, 4, 15, 66, 21, 0, // Skip to: 8345 +/* 2903 */ MCD_OPC_Decode, 182, 4, 35, // Opcode: CLZ +/* 2907 */ MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 2925 +/* 2912 */ MCD_OPC_CheckPredicate, 0, 52, 21, 0, // Skip to: 8345 +/* 2917 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, +/* 2921 */ MCD_OPC_Decode, 210, 5, 21, // Opcode: QDSUB +/* 2925 */ MCD_OPC_FilterValue, 3, 39, 21, 0, // Skip to: 8345 +/* 2930 */ MCD_OPC_CheckPredicate, 12, 34, 21, 0, // Skip to: 8345 +/* 2935 */ MCD_OPC_CheckField, 8, 12, 0, 27, 21, 0, // Skip to: 8345 +/* 2942 */ MCD_OPC_Decode, 135, 6, 36, // Opcode: SMC +/* 2946 */ MCD_OPC_FilterValue, 1, 18, 21, 0, // Skip to: 8345 +/* 2951 */ MCD_OPC_CheckPredicate, 0, 13, 21, 0, // Skip to: 8345 +/* 2956 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 2961 */ MCD_OPC_Decode, 186, 4, 18, // Opcode: CMNzrsr +/* 2965 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2986 +/* 2970 */ MCD_OPC_CheckPredicate, 0, 250, 20, 0, // Skip to: 8345 +/* 2975 */ MCD_OPC_CheckField, 16, 4, 0, 243, 20, 0, // Skip to: 8345 +/* 2982 */ MCD_OPC_Decode, 177, 5, 37, // Opcode: MOVsr +/* 2986 */ MCD_OPC_FilterValue, 7, 234, 20, 0, // Skip to: 8345 +/* 2991 */ MCD_OPC_CheckPredicate, 0, 229, 20, 0, // Skip to: 8345 +/* 2996 */ MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0, +/* 3001 */ MCD_OPC_Decode, 192, 5, 37, // Opcode: MVNsr +/* 3005 */ MCD_OPC_FilterValue, 1, 215, 20, 0, // Skip to: 8345 +/* 3010 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... +/* 3013 */ MCD_OPC_FilterValue, 0, 48, 1, 0, // Skip to: 3322 +/* 3018 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... +/* 3021 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3035 +/* 3026 */ MCD_OPC_CheckPredicate, 1, 194, 20, 0, // Skip to: 8345 +/* 3031 */ MCD_OPC_Decode, 168, 5, 38, // Opcode: MLA +/* 3035 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3056 +/* 3040 */ MCD_OPC_CheckPredicate, 13, 180, 20, 0, // Skip to: 8345 +/* 3045 */ MCD_OPC_CheckField, 20, 1, 0, 173, 20, 0, // Skip to: 8345 +/* 3052 */ MCD_OPC_Decode, 169, 5, 39, // Opcode: MLS +/* 3056 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3070 +/* 3061 */ MCD_OPC_CheckPredicate, 1, 159, 20, 0, // Skip to: 8345 +/* 3066 */ MCD_OPC_Decode, 153, 7, 40, // Opcode: UMLAL +/* 3070 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3084 +/* 3075 */ MCD_OPC_CheckPredicate, 1, 145, 20, 0, // Skip to: 8345 +/* 3080 */ MCD_OPC_Decode, 140, 6, 40, // Opcode: SMLAL +/* 3084 */ MCD_OPC_FilterValue, 6, 89, 0, 0, // Skip to: 3178 +/* 3089 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 3092 */ MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 3135 +/* 3097 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3100 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3114 +/* 3105 */ MCD_OPC_CheckPredicate, 9, 115, 20, 0, // Skip to: 8345 +/* 3110 */ MCD_OPC_Decode, 205, 6, 41, // Opcode: STLEXD +/* 3114 */ MCD_OPC_FilterValue, 1, 106, 20, 0, // Skip to: 8345 +/* 3119 */ MCD_OPC_CheckPredicate, 9, 101, 20, 0, // Skip to: 8345 +/* 3124 */ MCD_OPC_CheckField, 0, 4, 15, 94, 20, 0, // Skip to: 8345 +/* 3131 */ MCD_OPC_Decode, 226, 4, 42, // Opcode: LDAEXD +/* 3135 */ MCD_OPC_FilterValue, 15, 85, 20, 0, // Skip to: 8345 +/* 3140 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3143 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3157 +/* 3148 */ MCD_OPC_CheckPredicate, 0, 72, 20, 0, // Skip to: 8345 +/* 3153 */ MCD_OPC_Decode, 229, 6, 41, // Opcode: STREXD +/* 3157 */ MCD_OPC_FilterValue, 1, 63, 20, 0, // Skip to: 8345 +/* 3162 */ MCD_OPC_CheckPredicate, 0, 58, 20, 0, // Skip to: 8345 +/* 3167 */ MCD_OPC_CheckField, 0, 4, 15, 51, 20, 0, // Skip to: 8345 +/* 3174 */ MCD_OPC_Decode, 138, 5, 42, // Opcode: LDREXD +/* 3178 */ MCD_OPC_FilterValue, 7, 42, 20, 0, // Skip to: 8345 +/* 3183 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 3186 */ MCD_OPC_FilterValue, 12, 45, 0, 0, // Skip to: 3236 +/* 3191 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3194 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3215 +/* 3199 */ MCD_OPC_CheckPredicate, 8, 21, 20, 0, // Skip to: 8345 +/* 3204 */ MCD_OPC_CheckField, 12, 4, 15, 14, 20, 0, // Skip to: 8345 +/* 3211 */ MCD_OPC_Decode, 207, 6, 22, // Opcode: STLH +/* 3215 */ MCD_OPC_FilterValue, 1, 5, 20, 0, // Skip to: 8345 +/* 3220 */ MCD_OPC_CheckPredicate, 8, 0, 20, 0, // Skip to: 8345 +/* 3225 */ MCD_OPC_CheckField, 0, 4, 15, 249, 19, 0, // Skip to: 8345 +/* 3232 */ MCD_OPC_Decode, 228, 4, 23, // Opcode: LDAH +/* 3236 */ MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 3279 +/* 3241 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3244 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3258 +/* 3249 */ MCD_OPC_CheckPredicate, 9, 227, 19, 0, // Skip to: 8345 +/* 3254 */ MCD_OPC_Decode, 206, 6, 24, // Opcode: STLEXH +/* 3258 */ MCD_OPC_FilterValue, 1, 218, 19, 0, // Skip to: 8345 +/* 3263 */ MCD_OPC_CheckPredicate, 9, 213, 19, 0, // Skip to: 8345 +/* 3268 */ MCD_OPC_CheckField, 0, 4, 15, 206, 19, 0, // Skip to: 8345 +/* 3275 */ MCD_OPC_Decode, 227, 4, 23, // Opcode: LDAEXH +/* 3279 */ MCD_OPC_FilterValue, 15, 197, 19, 0, // Skip to: 8345 +/* 3284 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3287 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3301 +/* 3292 */ MCD_OPC_CheckPredicate, 0, 184, 19, 0, // Skip to: 8345 +/* 3297 */ MCD_OPC_Decode, 230, 6, 24, // Opcode: STREXH +/* 3301 */ MCD_OPC_FilterValue, 1, 175, 19, 0, // Skip to: 8345 +/* 3306 */ MCD_OPC_CheckPredicate, 0, 170, 19, 0, // Skip to: 8345 +/* 3311 */ MCD_OPC_CheckField, 0, 4, 15, 163, 19, 0, // Skip to: 8345 +/* 3318 */ MCD_OPC_Decode, 139, 5, 23, // Opcode: LDREXH +/* 3322 */ MCD_OPC_FilterValue, 1, 130, 0, 0, // Skip to: 3457 +/* 3327 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3330 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 3395 +/* 3335 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 3338 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 3381 +/* 3343 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3346 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3367 +/* 3351 */ MCD_OPC_CheckPredicate, 0, 125, 19, 0, // Skip to: 8345 +/* 3356 */ MCD_OPC_CheckField, 8, 4, 0, 118, 19, 0, // Skip to: 8345 +/* 3363 */ MCD_OPC_Decode, 233, 6, 43, // Opcode: STRHTr +/* 3367 */ MCD_OPC_FilterValue, 1, 109, 19, 0, // Skip to: 8345 +/* 3372 */ MCD_OPC_CheckPredicate, 0, 104, 19, 0, // Skip to: 8345 +/* 3377 */ MCD_OPC_Decode, 232, 6, 44, // Opcode: STRHTi +/* 3381 */ MCD_OPC_FilterValue, 1, 95, 19, 0, // Skip to: 8345 +/* 3386 */ MCD_OPC_CheckPredicate, 0, 90, 19, 0, // Skip to: 8345 +/* 3391 */ MCD_OPC_Decode, 235, 6, 7, // Opcode: STRH_PRE +/* 3395 */ MCD_OPC_FilterValue, 1, 81, 19, 0, // Skip to: 8345 +/* 3400 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 3403 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3443 +/* 3408 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3411 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3429 +/* 3416 */ MCD_OPC_CheckPredicate, 0, 60, 19, 0, // Skip to: 8345 +/* 3421 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, +/* 3425 */ MCD_OPC_Decode, 142, 5, 45, // Opcode: LDRHTr +/* 3429 */ MCD_OPC_FilterValue, 1, 47, 19, 0, // Skip to: 8345 +/* 3434 */ MCD_OPC_CheckPredicate, 0, 42, 19, 0, // Skip to: 8345 +/* 3439 */ MCD_OPC_Decode, 141, 5, 46, // Opcode: LDRHTi +/* 3443 */ MCD_OPC_FilterValue, 1, 33, 19, 0, // Skip to: 8345 +/* 3448 */ MCD_OPC_CheckPredicate, 0, 28, 19, 0, // Skip to: 8345 +/* 3453 */ MCD_OPC_Decode, 144, 5, 7, // Opcode: LDRH_PRE +/* 3457 */ MCD_OPC_FilterValue, 2, 86, 0, 0, // Skip to: 3548 +/* 3462 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3465 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3486 +/* 3470 */ MCD_OPC_CheckPredicate, 0, 6, 19, 0, // Skip to: 8345 +/* 3475 */ MCD_OPC_CheckField, 24, 1, 1, 255, 18, 0, // Skip to: 8345 +/* 3482 */ MCD_OPC_Decode, 135, 5, 7, // Opcode: LDRD_PRE +/* 3486 */ MCD_OPC_FilterValue, 1, 246, 18, 0, // Skip to: 8345 +/* 3491 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 3494 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3534 +/* 3499 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3502 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3520 +/* 3507 */ MCD_OPC_CheckPredicate, 0, 225, 18, 0, // Skip to: 8345 +/* 3512 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, +/* 3516 */ MCD_OPC_Decode, 147, 5, 45, // Opcode: LDRSBTr +/* 3520 */ MCD_OPC_FilterValue, 1, 212, 18, 0, // Skip to: 8345 +/* 3525 */ MCD_OPC_CheckPredicate, 0, 207, 18, 0, // Skip to: 8345 +/* 3530 */ MCD_OPC_Decode, 146, 5, 46, // Opcode: LDRSBTi +/* 3534 */ MCD_OPC_FilterValue, 1, 198, 18, 0, // Skip to: 8345 +/* 3539 */ MCD_OPC_CheckPredicate, 0, 193, 18, 0, // Skip to: 8345 +/* 3544 */ MCD_OPC_Decode, 149, 5, 7, // Opcode: LDRSB_PRE +/* 3548 */ MCD_OPC_FilterValue, 3, 184, 18, 0, // Skip to: 8345 +/* 3553 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3556 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3577 +/* 3561 */ MCD_OPC_CheckPredicate, 0, 171, 18, 0, // Skip to: 8345 +/* 3566 */ MCD_OPC_CheckField, 24, 1, 1, 164, 18, 0, // Skip to: 8345 +/* 3573 */ MCD_OPC_Decode, 226, 6, 7, // Opcode: STRD_PRE +/* 3577 */ MCD_OPC_FilterValue, 1, 155, 18, 0, // Skip to: 8345 +/* 3582 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 3585 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3625 +/* 3590 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3593 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3611 +/* 3598 */ MCD_OPC_CheckPredicate, 0, 134, 18, 0, // Skip to: 8345 +/* 3603 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, +/* 3607 */ MCD_OPC_Decode, 152, 5, 45, // Opcode: LDRSHTr +/* 3611 */ MCD_OPC_FilterValue, 1, 121, 18, 0, // Skip to: 8345 +/* 3616 */ MCD_OPC_CheckPredicate, 0, 116, 18, 0, // Skip to: 8345 +/* 3621 */ MCD_OPC_Decode, 151, 5, 46, // Opcode: LDRSHTi +/* 3625 */ MCD_OPC_FilterValue, 1, 107, 18, 0, // Skip to: 8345 +/* 3630 */ MCD_OPC_CheckPredicate, 0, 102, 18, 0, // Skip to: 8345 +/* 3635 */ MCD_OPC_Decode, 154, 5, 7, // Opcode: LDRSH_PRE +/* 3639 */ MCD_OPC_FilterValue, 1, 0, 2, 0, // Skip to: 4156 +/* 3644 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 3647 */ MCD_OPC_FilterValue, 0, 201, 0, 0, // Skip to: 3853 +/* 3652 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 3655 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 3735 +/* 3660 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 3663 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3677 +/* 3668 */ MCD_OPC_CheckPredicate, 0, 46, 0, 0, // Skip to: 3719 +/* 3673 */ MCD_OPC_Decode, 158, 4, 47, // Opcode: ANDri +/* 3677 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3691 +/* 3682 */ MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 3719 +/* 3687 */ MCD_OPC_Decode, 244, 6, 47, // Opcode: SUBri +/* 3691 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3705 +/* 3696 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 3719 +/* 3701 */ MCD_OPC_Decode, 149, 4, 47, // Opcode: ADDri +/* 3705 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3719 +/* 3710 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 3719 +/* 3715 */ MCD_OPC_Decode, 238, 5, 47, // Opcode: SBCri +/* 3719 */ MCD_OPC_CheckPredicate, 0, 13, 18, 0, // Skip to: 8345 +/* 3724 */ MCD_OPC_CheckField, 16, 5, 15, 6, 18, 0, // Skip to: 8345 +/* 3731 */ MCD_OPC_Decode, 153, 4, 48, // Opcode: ADR +/* 3735 */ MCD_OPC_FilterValue, 1, 253, 17, 0, // Skip to: 8345 +/* 3740 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 3743 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 3784 +/* 3748 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3751 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3765 +/* 3756 */ MCD_OPC_CheckPredicate, 13, 232, 17, 0, // Skip to: 8345 +/* 3761 */ MCD_OPC_Decode, 173, 5, 49, // Opcode: MOVi16 +/* 3765 */ MCD_OPC_FilterValue, 1, 223, 17, 0, // Skip to: 8345 +/* 3770 */ MCD_OPC_CheckPredicate, 0, 218, 17, 0, // Skip to: 8345 +/* 3775 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 3780 */ MCD_OPC_Decode, 136, 7, 50, // Opcode: TSTri +/* 3784 */ MCD_OPC_FilterValue, 1, 36, 0, 0, // Skip to: 3825 +/* 3789 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3792 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3806 +/* 3797 */ MCD_OPC_CheckPredicate, 13, 191, 17, 0, // Skip to: 8345 +/* 3802 */ MCD_OPC_Decode, 171, 5, 49, // Opcode: MOVTi16 +/* 3806 */ MCD_OPC_FilterValue, 1, 182, 17, 0, // Skip to: 8345 +/* 3811 */ MCD_OPC_CheckPredicate, 0, 177, 17, 0, // Skip to: 8345 +/* 3816 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 3821 */ MCD_OPC_Decode, 187, 4, 50, // Opcode: CMPri +/* 3825 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3839 +/* 3830 */ MCD_OPC_CheckPredicate, 0, 158, 17, 0, // Skip to: 8345 +/* 3835 */ MCD_OPC_Decode, 193, 5, 47, // Opcode: ORRri +/* 3839 */ MCD_OPC_FilterValue, 3, 149, 17, 0, // Skip to: 8345 +/* 3844 */ MCD_OPC_CheckPredicate, 0, 144, 17, 0, // Skip to: 8345 +/* 3849 */ MCD_OPC_Decode, 164, 4, 47, // Opcode: BICri +/* 3853 */ MCD_OPC_FilterValue, 1, 135, 17, 0, // Skip to: 8345 +/* 3858 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 3861 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 3897 +/* 3866 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3869 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3883 +/* 3874 */ MCD_OPC_CheckPredicate, 0, 114, 17, 0, // Skip to: 8345 +/* 3879 */ MCD_OPC_Decode, 203, 4, 47, // Opcode: EORri +/* 3883 */ MCD_OPC_FilterValue, 1, 105, 17, 0, // Skip to: 8345 +/* 3888 */ MCD_OPC_CheckPredicate, 0, 100, 17, 0, // Skip to: 8345 +/* 3893 */ MCD_OPC_Decode, 227, 5, 47, // Opcode: RSBri +/* 3897 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 3933 +/* 3902 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3905 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3919 +/* 3910 */ MCD_OPC_CheckPredicate, 0, 78, 17, 0, // Skip to: 8345 +/* 3915 */ MCD_OPC_Decode, 145, 4, 47, // Opcode: ADCri +/* 3919 */ MCD_OPC_FilterValue, 1, 69, 17, 0, // Skip to: 8345 +/* 3924 */ MCD_OPC_CheckPredicate, 0, 64, 17, 0, // Skip to: 8345 +/* 3929 */ MCD_OPC_Decode, 231, 5, 47, // Opcode: RSCri +/* 3933 */ MCD_OPC_FilterValue, 2, 168, 0, 0, // Skip to: 4106 +/* 3938 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3941 */ MCD_OPC_FilterValue, 0, 114, 0, 0, // Skip to: 4060 +/* 3946 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3949 */ MCD_OPC_FilterValue, 15, 39, 17, 0, // Skip to: 8345 +/* 3954 */ MCD_OPC_CheckPredicate, 14, 32, 0, 0, // Skip to: 3991 +/* 3959 */ MCD_OPC_CheckField, 28, 4, 14, 25, 0, 0, // Skip to: 3991 +/* 3966 */ MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 3991 +/* 3973 */ MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 3991 +/* 3980 */ MCD_OPC_CheckField, 0, 12, 18, 4, 0, 0, // Skip to: 3991 +/* 3987 */ MCD_OPC_Decode, 135, 7, 51, // Opcode: TSB +/* 3991 */ MCD_OPC_CheckPredicate, 15, 25, 0, 0, // Skip to: 4021 +/* 3996 */ MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 4021 +/* 4003 */ MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 4021 +/* 4010 */ MCD_OPC_CheckField, 4, 8, 15, 4, 0, 0, // Skip to: 4021 +/* 4017 */ MCD_OPC_Decode, 200, 4, 36, // Opcode: DBG +/* 4021 */ MCD_OPC_CheckPredicate, 1, 25, 0, 0, // Skip to: 4051 +/* 4026 */ MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 4051 +/* 4033 */ MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 4051 +/* 4040 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4051 +/* 4047 */ MCD_OPC_Decode, 218, 4, 52, // Opcode: HINT +/* 4051 */ MCD_OPC_CheckPredicate, 0, 193, 16, 0, // Skip to: 8345 +/* 4056 */ MCD_OPC_Decode, 187, 5, 53, // Opcode: MSRi +/* 4060 */ MCD_OPC_FilterValue, 1, 184, 16, 0, // Skip to: 8345 +/* 4065 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4068 */ MCD_OPC_FilterValue, 0, 14, 0, 0, // Skip to: 4087 +/* 4073 */ MCD_OPC_CheckPredicate, 0, 171, 16, 0, // Skip to: 8345 +/* 4078 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 4083 */ MCD_OPC_Decode, 129, 7, 50, // Opcode: TEQri +/* 4087 */ MCD_OPC_FilterValue, 1, 157, 16, 0, // Skip to: 8345 +/* 4092 */ MCD_OPC_CheckPredicate, 0, 152, 16, 0, // Skip to: 8345 +/* 4097 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, +/* 4102 */ MCD_OPC_Decode, 183, 4, 50, // Opcode: CMNri +/* 4106 */ MCD_OPC_FilterValue, 3, 138, 16, 0, // Skip to: 8345 +/* 4111 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4114 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4135 +/* 4119 */ MCD_OPC_CheckPredicate, 0, 125, 16, 0, // Skip to: 8345 +/* 4124 */ MCD_OPC_CheckField, 16, 4, 0, 118, 16, 0, // Skip to: 8345 +/* 4131 */ MCD_OPC_Decode, 172, 5, 54, // Opcode: MOVi +/* 4135 */ MCD_OPC_FilterValue, 1, 109, 16, 0, // Skip to: 8345 +/* 4140 */ MCD_OPC_CheckPredicate, 0, 104, 16, 0, // Skip to: 8345 +/* 4145 */ MCD_OPC_CheckField, 16, 4, 0, 97, 16, 0, // Skip to: 8345 +/* 4152 */ MCD_OPC_Decode, 189, 5, 54, // Opcode: MVNi +/* 4156 */ MCD_OPC_FilterValue, 2, 229, 1, 0, // Skip to: 4646 +/* 4161 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 4164 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4200 +/* 4169 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 4172 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4186 +/* 4177 */ MCD_OPC_CheckPredicate, 0, 67, 16, 0, // Skip to: 8345 +/* 4182 */ MCD_OPC_Decode, 238, 6, 55, // Opcode: STR_POST_IMM +/* 4186 */ MCD_OPC_FilterValue, 1, 58, 16, 0, // Skip to: 8345 +/* 4191 */ MCD_OPC_CheckPredicate, 0, 53, 16, 0, // Skip to: 8345 +/* 4196 */ MCD_OPC_Decode, 242, 6, 56, // Opcode: STRi12 +/* 4200 */ MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 4259 +/* 4205 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 4208 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4222 +/* 4213 */ MCD_OPC_CheckPredicate, 0, 31, 16, 0, // Skip to: 8345 +/* 4218 */ MCD_OPC_Decode, 157, 5, 55, // Opcode: LDR_POST_IMM +/* 4222 */ MCD_OPC_FilterValue, 1, 22, 16, 0, // Skip to: 8345 +/* 4227 */ MCD_OPC_CheckPredicate, 16, 18, 0, 0, // Skip to: 4250 +/* 4232 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4250 +/* 4239 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4250 +/* 4246 */ MCD_OPC_Decode, 199, 5, 57, // Opcode: PLDWi12 +/* 4250 */ MCD_OPC_CheckPredicate, 0, 250, 15, 0, // Skip to: 8345 +/* 4255 */ MCD_OPC_Decode, 162, 5, 56, // Opcode: LDRi12 +/* 4259 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 4295 +/* 4264 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 4267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4281 +/* 4272 */ MCD_OPC_CheckPredicate, 0, 228, 15, 0, // Skip to: 8345 +/* 4277 */ MCD_OPC_Decode, 236, 6, 55, // Opcode: STRT_POST_IMM +/* 4281 */ MCD_OPC_FilterValue, 1, 219, 15, 0, // Skip to: 8345 +/* 4286 */ MCD_OPC_CheckPredicate, 0, 214, 15, 0, // Skip to: 8345 +/* 4291 */ MCD_OPC_Decode, 240, 6, 58, // Opcode: STR_PRE_IMM +/* 4295 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 4331 +/* 4300 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 4303 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4317 +/* 4308 */ MCD_OPC_CheckPredicate, 0, 192, 15, 0, // Skip to: 8345 +/* 4313 */ MCD_OPC_Decode, 155, 5, 55, // Opcode: LDRT_POST_IMM +/* 4317 */ MCD_OPC_FilterValue, 1, 183, 15, 0, // Skip to: 8345 +/* 4322 */ MCD_OPC_CheckPredicate, 0, 178, 15, 0, // Skip to: 8345 +/* 4327 */ MCD_OPC_Decode, 159, 5, 59, // Opcode: LDR_PRE_IMM +/* 4331 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 4367 +/* 4336 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 4339 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4353 +/* 4344 */ MCD_OPC_CheckPredicate, 0, 156, 15, 0, // Skip to: 8345 +/* 4349 */ MCD_OPC_Decode, 218, 6, 55, // Opcode: STRB_POST_IMM +/* 4353 */ MCD_OPC_FilterValue, 1, 147, 15, 0, // Skip to: 8345 +/* 4358 */ MCD_OPC_CheckPredicate, 0, 142, 15, 0, // Skip to: 8345 +/* 4363 */ MCD_OPC_Decode, 222, 6, 60, // Opcode: STRBi12 +/* 4367 */ MCD_OPC_FilterValue, 5, 77, 0, 0, // Skip to: 4449 +/* 4372 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 4375 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 4412 +/* 4380 */ MCD_OPC_CheckPredicate, 15, 18, 0, 0, // Skip to: 4403 +/* 4385 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4403 +/* 4392 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4403 +/* 4399 */ MCD_OPC_Decode, 203, 5, 57, // Opcode: PLIi12 +/* 4403 */ MCD_OPC_CheckPredicate, 0, 97, 15, 0, // Skip to: 8345 +/* 4408 */ MCD_OPC_Decode, 255, 4, 55, // Opcode: LDRB_POST_IMM +/* 4412 */ MCD_OPC_FilterValue, 1, 88, 15, 0, // Skip to: 8345 +/* 4417 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 4440 +/* 4422 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4440 +/* 4429 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4440 +/* 4436 */ MCD_OPC_Decode, 201, 5, 57, // Opcode: PLDi12 +/* 4440 */ MCD_OPC_CheckPredicate, 0, 60, 15, 0, // Skip to: 8345 +/* 4445 */ MCD_OPC_Decode, 131, 5, 60, // Opcode: LDRBi12 +/* 4449 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 4485 +/* 4454 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 4457 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4471 +/* 4462 */ MCD_OPC_CheckPredicate, 0, 38, 15, 0, // Skip to: 8345 +/* 4467 */ MCD_OPC_Decode, 216, 6, 55, // Opcode: STRBT_POST_IMM +/* 4471 */ MCD_OPC_FilterValue, 1, 29, 15, 0, // Skip to: 8345 +/* 4476 */ MCD_OPC_CheckPredicate, 0, 24, 15, 0, // Skip to: 8345 +/* 4481 */ MCD_OPC_Decode, 220, 6, 58, // Opcode: STRB_PRE_IMM +/* 4485 */ MCD_OPC_FilterValue, 7, 15, 15, 0, // Skip to: 8345 +/* 4490 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 4493 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4507 +/* 4498 */ MCD_OPC_CheckPredicate, 0, 2, 15, 0, // Skip to: 8345 +/* 4503 */ MCD_OPC_Decode, 253, 4, 55, // Opcode: LDRBT_POST_IMM +/* 4507 */ MCD_OPC_FilterValue, 1, 249, 14, 0, // Skip to: 8345 +/* 4512 */ MCD_OPC_CheckPredicate, 17, 27, 0, 0, // Skip to: 4544 +/* 4517 */ MCD_OPC_CheckField, 28, 4, 15, 20, 0, 0, // Skip to: 4544 +/* 4524 */ MCD_OPC_CheckField, 23, 1, 0, 13, 0, 0, // Skip to: 4544 +/* 4531 */ MCD_OPC_CheckField, 0, 20, 159, 224, 63, 4, 0, 0, // Skip to: 4544 +/* 4540 */ MCD_OPC_Decode, 181, 4, 51, // Opcode: CLREX +/* 4544 */ MCD_OPC_ExtractField, 4, 16, // Inst{19-4} ... +/* 4547 */ MCD_OPC_FilterValue, 132, 254, 3, 23, 0, 0, // Skip to: 4577 +/* 4554 */ MCD_OPC_CheckPredicate, 18, 78, 0, 0, // Skip to: 4637 +/* 4559 */ MCD_OPC_CheckField, 28, 4, 15, 71, 0, 0, // Skip to: 4637 +/* 4566 */ MCD_OPC_CheckField, 23, 1, 0, 64, 0, 0, // Skip to: 4637 +/* 4573 */ MCD_OPC_Decode, 202, 4, 61, // Opcode: DSB +/* 4577 */ MCD_OPC_FilterValue, 133, 254, 3, 23, 0, 0, // Skip to: 4607 +/* 4584 */ MCD_OPC_CheckPredicate, 18, 48, 0, 0, // Skip to: 4637 +/* 4589 */ MCD_OPC_CheckField, 28, 4, 15, 41, 0, 0, // Skip to: 4637 +/* 4596 */ MCD_OPC_CheckField, 23, 1, 0, 34, 0, 0, // Skip to: 4637 +/* 4603 */ MCD_OPC_Decode, 201, 4, 61, // Opcode: DMB +/* 4607 */ MCD_OPC_FilterValue, 134, 254, 3, 23, 0, 0, // Skip to: 4637 +/* 4614 */ MCD_OPC_CheckPredicate, 18, 18, 0, 0, // Skip to: 4637 +/* 4619 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4637 +/* 4626 */ MCD_OPC_CheckField, 23, 1, 0, 4, 0, 0, // Skip to: 4637 +/* 4633 */ MCD_OPC_Decode, 221, 4, 62, // Opcode: ISB +/* 4637 */ MCD_OPC_CheckPredicate, 0, 119, 14, 0, // Skip to: 8345 +/* 4642 */ MCD_OPC_Decode, 129, 5, 59, // Opcode: LDRB_PRE_IMM +/* 4646 */ MCD_OPC_FilterValue, 3, 129, 10, 0, // Skip to: 7340 +/* 4651 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 4654 */ MCD_OPC_FilterValue, 0, 200, 2, 0, // Skip to: 5371 +/* 4659 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 4662 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 4765 +/* 4667 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4670 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4706 +/* 4675 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 4678 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4692 +/* 4683 */ MCD_OPC_CheckPredicate, 0, 73, 14, 0, // Skip to: 8345 +/* 4688 */ MCD_OPC_Decode, 239, 6, 55, // Opcode: STR_POST_REG +/* 4692 */ MCD_OPC_FilterValue, 1, 64, 14, 0, // Skip to: 8345 +/* 4697 */ MCD_OPC_CheckPredicate, 0, 59, 14, 0, // Skip to: 8345 +/* 4702 */ MCD_OPC_Decode, 243, 6, 63, // Opcode: STRrs +/* 4706 */ MCD_OPC_FilterValue, 1, 50, 14, 0, // Skip to: 8345 +/* 4711 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 4714 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4728 +/* 4719 */ MCD_OPC_CheckPredicate, 0, 37, 14, 0, // Skip to: 8345 +/* 4724 */ MCD_OPC_Decode, 158, 5, 55, // Opcode: LDR_POST_REG +/* 4728 */ MCD_OPC_FilterValue, 1, 28, 14, 0, // Skip to: 8345 +/* 4733 */ MCD_OPC_CheckPredicate, 16, 18, 0, 0, // Skip to: 4756 +/* 4738 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4756 +/* 4745 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4756 +/* 4752 */ MCD_OPC_Decode, 200, 5, 64, // Opcode: PLDWrs +/* 4756 */ MCD_OPC_CheckPredicate, 0, 0, 14, 0, // Skip to: 8345 +/* 4761 */ MCD_OPC_Decode, 163, 5, 63, // Opcode: LDRrs +/* 4765 */ MCD_OPC_FilterValue, 1, 247, 13, 0, // Skip to: 8345 +/* 4770 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... +/* 4773 */ MCD_OPC_FilterValue, 0, 202, 0, 0, // Skip to: 4980 +/* 4778 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 4781 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 4839 +/* 4786 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4789 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 4814 +/* 4794 */ MCD_OPC_CheckPredicate, 0, 218, 13, 0, // Skip to: 8345 +/* 4799 */ MCD_OPC_CheckField, 20, 1, 1, 211, 13, 0, // Skip to: 8345 +/* 4806 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 4810 */ MCD_OPC_Decode, 235, 5, 65, // Opcode: SADD16 +/* 4814 */ MCD_OPC_FilterValue, 1, 198, 13, 0, // Skip to: 8345 +/* 4819 */ MCD_OPC_CheckPredicate, 0, 193, 13, 0, // Skip to: 8345 +/* 4824 */ MCD_OPC_CheckField, 20, 1, 1, 186, 13, 0, // Skip to: 8345 +/* 4831 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 4835 */ MCD_OPC_Decode, 236, 5, 65, // Opcode: SADD8 +/* 4839 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4860 +/* 4844 */ MCD_OPC_CheckPredicate, 1, 168, 13, 0, // Skip to: 8345 +/* 4849 */ MCD_OPC_CheckField, 20, 1, 0, 161, 13, 0, // Skip to: 8345 +/* 4856 */ MCD_OPC_Decode, 197, 5, 66, // Opcode: PKHBT +/* 4860 */ MCD_OPC_FilterValue, 2, 69, 0, 0, // Skip to: 4934 +/* 4865 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4868 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 4906 +/* 4873 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4876 */ MCD_OPC_FilterValue, 0, 136, 13, 0, // Skip to: 8345 +/* 4881 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 4897 +/* 4886 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4897 +/* 4893 */ MCD_OPC_Decode, 161, 6, 67, // Opcode: SMUAD +/* 4897 */ MCD_OPC_CheckPredicate, 1, 115, 13, 0, // Skip to: 8345 +/* 4902 */ MCD_OPC_Decode, 138, 6, 68, // Opcode: SMLAD +/* 4906 */ MCD_OPC_FilterValue, 1, 106, 13, 0, // Skip to: 8345 +/* 4911 */ MCD_OPC_CheckPredicate, 19, 101, 13, 0, // Skip to: 8345 +/* 4916 */ MCD_OPC_CheckField, 12, 4, 15, 94, 13, 0, // Skip to: 8345 +/* 4923 */ MCD_OPC_CheckField, 7, 1, 0, 87, 13, 0, // Skip to: 8345 +/* 4930 */ MCD_OPC_Decode, 243, 5, 30, // Opcode: SDIV +/* 4934 */ MCD_OPC_FilterValue, 3, 78, 13, 0, // Skip to: 8345 +/* 4939 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4942 */ MCD_OPC_FilterValue, 0, 70, 13, 0, // Skip to: 8345 +/* 4947 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4950 */ MCD_OPC_FilterValue, 0, 62, 13, 0, // Skip to: 8345 +/* 4955 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 4971 +/* 4960 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4971 +/* 4967 */ MCD_OPC_Decode, 161, 7, 30, // Opcode: USAD8 +/* 4971 */ MCD_OPC_CheckPredicate, 1, 41, 13, 0, // Skip to: 8345 +/* 4976 */ MCD_OPC_Decode, 162, 7, 39, // Opcode: USADA8 +/* 4980 */ MCD_OPC_FilterValue, 1, 113, 0, 0, // Skip to: 5098 +/* 4985 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 4988 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5020 +/* 4993 */ MCD_OPC_CheckPredicate, 0, 19, 13, 0, // Skip to: 8345 +/* 4998 */ MCD_OPC_CheckField, 20, 1, 1, 12, 13, 0, // Skip to: 8345 +/* 5005 */ MCD_OPC_CheckField, 7, 1, 0, 5, 13, 0, // Skip to: 8345 +/* 5012 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5016 */ MCD_OPC_Decode, 237, 5, 65, // Opcode: SASX +/* 5020 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 5052 +/* 5025 */ MCD_OPC_CheckPredicate, 1, 243, 12, 0, // Skip to: 8345 +/* 5030 */ MCD_OPC_CheckField, 20, 1, 0, 236, 12, 0, // Skip to: 8345 +/* 5037 */ MCD_OPC_CheckField, 7, 1, 1, 229, 12, 0, // Skip to: 8345 +/* 5044 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5048 */ MCD_OPC_Decode, 244, 5, 69, // Opcode: SEL +/* 5052 */ MCD_OPC_FilterValue, 2, 216, 12, 0, // Skip to: 8345 +/* 5057 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 5060 */ MCD_OPC_FilterValue, 0, 208, 12, 0, // Skip to: 8345 +/* 5065 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5068 */ MCD_OPC_FilterValue, 0, 200, 12, 0, // Skip to: 8345 +/* 5073 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5089 +/* 5078 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5089 +/* 5085 */ MCD_OPC_Decode, 162, 6, 67, // Opcode: SMUADX +/* 5089 */ MCD_OPC_CheckPredicate, 1, 179, 12, 0, // Skip to: 8345 +/* 5094 */ MCD_OPC_Decode, 139, 6, 68, // Opcode: SMLADX +/* 5098 */ MCD_OPC_FilterValue, 2, 102, 0, 0, // Skip to: 5205 +/* 5103 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 5106 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5138 +/* 5111 */ MCD_OPC_CheckPredicate, 0, 157, 12, 0, // Skip to: 8345 +/* 5116 */ MCD_OPC_CheckField, 20, 1, 1, 150, 12, 0, // Skip to: 8345 +/* 5123 */ MCD_OPC_CheckField, 7, 1, 0, 143, 12, 0, // Skip to: 8345 +/* 5130 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5134 */ MCD_OPC_Decode, 182, 6, 65, // Opcode: SSAX +/* 5138 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 5159 +/* 5143 */ MCD_OPC_CheckPredicate, 1, 125, 12, 0, // Skip to: 8345 +/* 5148 */ MCD_OPC_CheckField, 20, 1, 0, 118, 12, 0, // Skip to: 8345 +/* 5155 */ MCD_OPC_Decode, 198, 5, 66, // Opcode: PKHTB +/* 5159 */ MCD_OPC_FilterValue, 2, 109, 12, 0, // Skip to: 8345 +/* 5164 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 5167 */ MCD_OPC_FilterValue, 0, 101, 12, 0, // Skip to: 8345 +/* 5172 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5175 */ MCD_OPC_FilterValue, 0, 93, 12, 0, // Skip to: 8345 +/* 5180 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5196 +/* 5185 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5196 +/* 5192 */ MCD_OPC_Decode, 170, 6, 67, // Opcode: SMUSD +/* 5196 */ MCD_OPC_CheckPredicate, 1, 72, 12, 0, // Skip to: 8345 +/* 5201 */ MCD_OPC_Decode, 151, 6, 68, // Opcode: SMLSD +/* 5205 */ MCD_OPC_FilterValue, 3, 63, 12, 0, // Skip to: 8345 +/* 5210 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 5213 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 5271 +/* 5218 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 5221 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 5246 +/* 5226 */ MCD_OPC_CheckPredicate, 0, 42, 12, 0, // Skip to: 8345 +/* 5231 */ MCD_OPC_CheckField, 20, 1, 1, 35, 12, 0, // Skip to: 8345 +/* 5238 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5242 */ MCD_OPC_Decode, 183, 6, 65, // Opcode: SSUB16 +/* 5246 */ MCD_OPC_FilterValue, 1, 22, 12, 0, // Skip to: 8345 +/* 5251 */ MCD_OPC_CheckPredicate, 0, 17, 12, 0, // Skip to: 8345 +/* 5256 */ MCD_OPC_CheckField, 20, 1, 1, 10, 12, 0, // Skip to: 8345 +/* 5263 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5267 */ MCD_OPC_Decode, 184, 6, 65, // Opcode: SSUB8 +/* 5271 */ MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 5325 +/* 5276 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 5279 */ MCD_OPC_FilterValue, 0, 245, 11, 0, // Skip to: 8345 +/* 5284 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5287 */ MCD_OPC_FilterValue, 0, 237, 11, 0, // Skip to: 8345 +/* 5292 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5312 +/* 5297 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5312 +/* 5304 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 5308 */ MCD_OPC_Decode, 255, 6, 70, // Opcode: SXTB16 +/* 5312 */ MCD_OPC_CheckPredicate, 1, 212, 11, 0, // Skip to: 8345 +/* 5317 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 5321 */ MCD_OPC_Decode, 252, 6, 71, // Opcode: SXTAB16 +/* 5325 */ MCD_OPC_FilterValue, 2, 199, 11, 0, // Skip to: 8345 +/* 5330 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 5333 */ MCD_OPC_FilterValue, 0, 191, 11, 0, // Skip to: 8345 +/* 5338 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5341 */ MCD_OPC_FilterValue, 0, 183, 11, 0, // Skip to: 8345 +/* 5346 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5362 +/* 5351 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5362 +/* 5358 */ MCD_OPC_Decode, 171, 6, 67, // Opcode: SMUSDX +/* 5362 */ MCD_OPC_CheckPredicate, 1, 162, 11, 0, // Skip to: 8345 +/* 5367 */ MCD_OPC_Decode, 152, 6, 68, // Opcode: SMLSDX +/* 5371 */ MCD_OPC_FilterValue, 1, 106, 2, 0, // Skip to: 5994 +/* 5376 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 5379 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 5459 +/* 5384 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5387 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5423 +/* 5392 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 5395 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5409 +/* 5400 */ MCD_OPC_CheckPredicate, 0, 124, 11, 0, // Skip to: 8345 +/* 5405 */ MCD_OPC_Decode, 237, 6, 55, // Opcode: STRT_POST_REG +/* 5409 */ MCD_OPC_FilterValue, 1, 115, 11, 0, // Skip to: 8345 +/* 5414 */ MCD_OPC_CheckPredicate, 0, 110, 11, 0, // Skip to: 8345 +/* 5419 */ MCD_OPC_Decode, 241, 6, 72, // Opcode: STR_PRE_REG +/* 5423 */ MCD_OPC_FilterValue, 1, 101, 11, 0, // Skip to: 8345 +/* 5428 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 5431 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5445 +/* 5436 */ MCD_OPC_CheckPredicate, 0, 88, 11, 0, // Skip to: 8345 +/* 5441 */ MCD_OPC_Decode, 156, 5, 55, // Opcode: LDRT_POST_REG +/* 5445 */ MCD_OPC_FilterValue, 1, 79, 11, 0, // Skip to: 8345 +/* 5450 */ MCD_OPC_CheckPredicate, 0, 74, 11, 0, // Skip to: 8345 +/* 5455 */ MCD_OPC_Decode, 160, 5, 73, // Opcode: LDR_PRE_REG +/* 5459 */ MCD_OPC_FilterValue, 1, 65, 11, 0, // Skip to: 8345 +/* 5464 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 5467 */ MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 5739 +/* 5472 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 5475 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 5519 +/* 5480 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5483 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5501 +/* 5488 */ MCD_OPC_CheckPredicate, 0, 36, 11, 0, // Skip to: 8345 +/* 5493 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5497 */ MCD_OPC_Decode, 206, 5, 65, // Opcode: QADD16 +/* 5501 */ MCD_OPC_FilterValue, 1, 23, 11, 0, // Skip to: 8345 +/* 5506 */ MCD_OPC_CheckPredicate, 0, 18, 11, 0, // Skip to: 8345 +/* 5511 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5515 */ MCD_OPC_Decode, 129, 6, 65, // Opcode: SHADD16 +/* 5519 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 5563 +/* 5524 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5527 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5545 +/* 5532 */ MCD_OPC_CheckPredicate, 0, 248, 10, 0, // Skip to: 8345 +/* 5537 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5541 */ MCD_OPC_Decode, 208, 5, 65, // Opcode: QASX +/* 5545 */ MCD_OPC_FilterValue, 1, 235, 10, 0, // Skip to: 8345 +/* 5550 */ MCD_OPC_CheckPredicate, 0, 230, 10, 0, // Skip to: 8345 +/* 5555 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5559 */ MCD_OPC_Decode, 131, 6, 65, // Opcode: SHASX +/* 5563 */ MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 5607 +/* 5568 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5571 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5589 +/* 5576 */ MCD_OPC_CheckPredicate, 0, 204, 10, 0, // Skip to: 8345 +/* 5581 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5585 */ MCD_OPC_Decode, 211, 5, 65, // Opcode: QSAX +/* 5589 */ MCD_OPC_FilterValue, 1, 191, 10, 0, // Skip to: 8345 +/* 5594 */ MCD_OPC_CheckPredicate, 0, 186, 10, 0, // Skip to: 8345 +/* 5599 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5603 */ MCD_OPC_Decode, 132, 6, 65, // Opcode: SHSAX +/* 5607 */ MCD_OPC_FilterValue, 3, 39, 0, 0, // Skip to: 5651 +/* 5612 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5615 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5633 +/* 5620 */ MCD_OPC_CheckPredicate, 0, 160, 10, 0, // Skip to: 8345 +/* 5625 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5629 */ MCD_OPC_Decode, 213, 5, 65, // Opcode: QSUB16 +/* 5633 */ MCD_OPC_FilterValue, 1, 147, 10, 0, // Skip to: 8345 +/* 5638 */ MCD_OPC_CheckPredicate, 0, 142, 10, 0, // Skip to: 8345 +/* 5643 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5647 */ MCD_OPC_Decode, 133, 6, 65, // Opcode: SHSUB16 +/* 5651 */ MCD_OPC_FilterValue, 4, 39, 0, 0, // Skip to: 5695 +/* 5656 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5659 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5677 +/* 5664 */ MCD_OPC_CheckPredicate, 0, 116, 10, 0, // Skip to: 8345 +/* 5669 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5673 */ MCD_OPC_Decode, 207, 5, 65, // Opcode: QADD8 +/* 5677 */ MCD_OPC_FilterValue, 1, 103, 10, 0, // Skip to: 8345 +/* 5682 */ MCD_OPC_CheckPredicate, 0, 98, 10, 0, // Skip to: 8345 +/* 5687 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5691 */ MCD_OPC_Decode, 130, 6, 65, // Opcode: SHADD8 +/* 5695 */ MCD_OPC_FilterValue, 7, 85, 10, 0, // Skip to: 8345 +/* 5700 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5703 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5721 +/* 5708 */ MCD_OPC_CheckPredicate, 0, 72, 10, 0, // Skip to: 8345 +/* 5713 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5717 */ MCD_OPC_Decode, 214, 5, 65, // Opcode: QSUB8 +/* 5721 */ MCD_OPC_FilterValue, 1, 59, 10, 0, // Skip to: 8345 +/* 5726 */ MCD_OPC_CheckPredicate, 0, 54, 10, 0, // Skip to: 8345 +/* 5731 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 5735 */ MCD_OPC_Decode, 134, 6, 65, // Opcode: SHSUB8 +/* 5739 */ MCD_OPC_FilterValue, 1, 194, 0, 0, // Skip to: 5938 +/* 5744 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 5747 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5761 +/* 5752 */ MCD_OPC_CheckPredicate, 1, 28, 10, 0, // Skip to: 8345 +/* 5757 */ MCD_OPC_Decode, 180, 6, 74, // Opcode: SSAT +/* 5761 */ MCD_OPC_FilterValue, 1, 19, 10, 0, // Skip to: 8345 +/* 5766 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 5769 */ MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 5826 +/* 5774 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5777 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 5798 +/* 5782 */ MCD_OPC_CheckPredicate, 1, 254, 9, 0, // Skip to: 8345 +/* 5787 */ MCD_OPC_CheckField, 8, 4, 15, 247, 9, 0, // Skip to: 8345 +/* 5794 */ MCD_OPC_Decode, 181, 6, 75, // Opcode: SSAT16 +/* 5798 */ MCD_OPC_FilterValue, 1, 238, 9, 0, // Skip to: 8345 +/* 5803 */ MCD_OPC_CheckPredicate, 1, 233, 9, 0, // Skip to: 8345 +/* 5808 */ MCD_OPC_CheckField, 16, 4, 15, 226, 9, 0, // Skip to: 8345 +/* 5815 */ MCD_OPC_CheckField, 8, 4, 15, 219, 9, 0, // Skip to: 8345 +/* 5822 */ MCD_OPC_Decode, 216, 5, 35, // Opcode: REV +/* 5826 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 5910 +/* 5831 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5834 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 5872 +/* 5839 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5859 +/* 5844 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5859 +/* 5851 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 5855 */ MCD_OPC_Decode, 254, 6, 70, // Opcode: SXTB +/* 5859 */ MCD_OPC_CheckPredicate, 1, 177, 9, 0, // Skip to: 8345 +/* 5864 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 5868 */ MCD_OPC_Decode, 251, 6, 71, // Opcode: SXTAB +/* 5872 */ MCD_OPC_FilterValue, 1, 164, 9, 0, // Skip to: 8345 +/* 5877 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5897 +/* 5882 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5897 +/* 5889 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 5893 */ MCD_OPC_Decode, 128, 7, 70, // Opcode: SXTH +/* 5897 */ MCD_OPC_CheckPredicate, 1, 139, 9, 0, // Skip to: 8345 +/* 5902 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 5906 */ MCD_OPC_Decode, 253, 6, 71, // Opcode: SXTAH +/* 5910 */ MCD_OPC_FilterValue, 2, 126, 9, 0, // Skip to: 8345 +/* 5915 */ MCD_OPC_CheckPredicate, 1, 121, 9, 0, // Skip to: 8345 +/* 5920 */ MCD_OPC_CheckField, 16, 5, 31, 114, 9, 0, // Skip to: 8345 +/* 5927 */ MCD_OPC_CheckField, 8, 4, 15, 107, 9, 0, // Skip to: 8345 +/* 5934 */ MCD_OPC_Decode, 217, 5, 35, // Opcode: REV16 +/* 5938 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 5973 +/* 5943 */ MCD_OPC_CheckPredicate, 19, 93, 9, 0, // Skip to: 8345 +/* 5948 */ MCD_OPC_CheckField, 20, 1, 1, 86, 9, 0, // Skip to: 8345 +/* 5955 */ MCD_OPC_CheckField, 12, 4, 15, 79, 9, 0, // Skip to: 8345 +/* 5962 */ MCD_OPC_CheckField, 5, 3, 0, 72, 9, 0, // Skip to: 8345 +/* 5969 */ MCD_OPC_Decode, 145, 7, 30, // Opcode: UDIV +/* 5973 */ MCD_OPC_FilterValue, 3, 63, 9, 0, // Skip to: 8345 +/* 5978 */ MCD_OPC_CheckPredicate, 13, 58, 9, 0, // Skip to: 8345 +/* 5983 */ MCD_OPC_CheckField, 5, 2, 2, 51, 9, 0, // Skip to: 8345 +/* 5990 */ MCD_OPC_Decode, 242, 5, 76, // Opcode: SBFX +/* 5994 */ MCD_OPC_FilterValue, 2, 155, 2, 0, // Skip to: 6666 +/* 5999 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 6002 */ MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 6128 +/* 6007 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6010 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6046 +/* 6015 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 6018 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6032 +/* 6023 */ MCD_OPC_CheckPredicate, 0, 13, 9, 0, // Skip to: 8345 +/* 6028 */ MCD_OPC_Decode, 219, 6, 55, // Opcode: STRB_POST_REG +/* 6032 */ MCD_OPC_FilterValue, 1, 4, 9, 0, // Skip to: 8345 +/* 6037 */ MCD_OPC_CheckPredicate, 0, 255, 8, 0, // Skip to: 8345 +/* 6042 */ MCD_OPC_Decode, 223, 6, 77, // Opcode: STRBrs +/* 6046 */ MCD_OPC_FilterValue, 1, 246, 8, 0, // Skip to: 8345 +/* 6051 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 6054 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 6091 +/* 6059 */ MCD_OPC_CheckPredicate, 15, 18, 0, 0, // Skip to: 6082 +/* 6064 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 6082 +/* 6071 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6082 +/* 6078 */ MCD_OPC_Decode, 204, 5, 64, // Opcode: PLIrs +/* 6082 */ MCD_OPC_CheckPredicate, 0, 210, 8, 0, // Skip to: 8345 +/* 6087 */ MCD_OPC_Decode, 128, 5, 55, // Opcode: LDRB_POST_REG +/* 6091 */ MCD_OPC_FilterValue, 1, 201, 8, 0, // Skip to: 8345 +/* 6096 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 6119 +/* 6101 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 6119 +/* 6108 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6119 +/* 6115 */ MCD_OPC_Decode, 202, 5, 64, // Opcode: PLDrs +/* 6119 */ MCD_OPC_CheckPredicate, 0, 173, 8, 0, // Skip to: 8345 +/* 6124 */ MCD_OPC_Decode, 132, 5, 77, // Opcode: LDRBrs +/* 6128 */ MCD_OPC_FilterValue, 1, 164, 8, 0, // Skip to: 8345 +/* 6133 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... +/* 6136 */ MCD_OPC_FilterValue, 0, 158, 0, 0, // Skip to: 6299 +/* 6141 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 6144 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 6202 +/* 6149 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 6152 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6177 +/* 6157 */ MCD_OPC_CheckPredicate, 0, 135, 8, 0, // Skip to: 8345 +/* 6162 */ MCD_OPC_CheckField, 20, 1, 1, 128, 8, 0, // Skip to: 8345 +/* 6169 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6173 */ MCD_OPC_Decode, 140, 7, 65, // Opcode: UADD16 +/* 6177 */ MCD_OPC_FilterValue, 1, 115, 8, 0, // Skip to: 8345 +/* 6182 */ MCD_OPC_CheckPredicate, 0, 110, 8, 0, // Skip to: 8345 +/* 6187 */ MCD_OPC_CheckField, 20, 1, 1, 103, 8, 0, // Skip to: 8345 +/* 6194 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6198 */ MCD_OPC_Decode, 141, 7, 65, // Opcode: UADD8 +/* 6202 */ MCD_OPC_FilterValue, 2, 62, 0, 0, // Skip to: 6269 +/* 6207 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6210 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6231 +/* 6215 */ MCD_OPC_CheckPredicate, 1, 77, 8, 0, // Skip to: 8345 +/* 6220 */ MCD_OPC_CheckField, 7, 1, 0, 70, 8, 0, // Skip to: 8345 +/* 6227 */ MCD_OPC_Decode, 143, 6, 19, // Opcode: SMLALD +/* 6231 */ MCD_OPC_FilterValue, 1, 61, 8, 0, // Skip to: 8345 +/* 6236 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 6239 */ MCD_OPC_FilterValue, 0, 53, 8, 0, // Skip to: 8345 +/* 6244 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 6260 +/* 6249 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6260 +/* 6256 */ MCD_OPC_Decode, 159, 6, 30, // Opcode: SMMUL +/* 6260 */ MCD_OPC_CheckPredicate, 1, 32, 8, 0, // Skip to: 8345 +/* 6265 */ MCD_OPC_Decode, 155, 6, 39, // Opcode: SMMLA +/* 6269 */ MCD_OPC_FilterValue, 3, 23, 8, 0, // Skip to: 8345 +/* 6274 */ MCD_OPC_CheckPredicate, 13, 11, 0, 0, // Skip to: 6290 +/* 6279 */ MCD_OPC_CheckField, 0, 4, 15, 4, 0, 0, // Skip to: 6290 +/* 6286 */ MCD_OPC_Decode, 162, 4, 78, // Opcode: BFC +/* 6290 */ MCD_OPC_CheckPredicate, 13, 2, 8, 0, // Skip to: 8345 +/* 6295 */ MCD_OPC_Decode, 163, 4, 79, // Opcode: BFI +/* 6299 */ MCD_OPC_FilterValue, 1, 102, 0, 0, // Skip to: 6406 +/* 6304 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6307 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6335 +/* 6312 */ MCD_OPC_CheckPredicate, 1, 236, 7, 0, // Skip to: 8345 +/* 6317 */ MCD_OPC_CheckField, 23, 2, 2, 229, 7, 0, // Skip to: 8345 +/* 6324 */ MCD_OPC_CheckField, 7, 1, 0, 222, 7, 0, // Skip to: 8345 +/* 6331 */ MCD_OPC_Decode, 144, 6, 19, // Opcode: SMLALDX +/* 6335 */ MCD_OPC_FilterValue, 1, 213, 7, 0, // Skip to: 8345 +/* 6340 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 6343 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6368 +/* 6348 */ MCD_OPC_CheckPredicate, 0, 200, 7, 0, // Skip to: 8345 +/* 6353 */ MCD_OPC_CheckField, 7, 1, 0, 193, 7, 0, // Skip to: 8345 +/* 6360 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6364 */ MCD_OPC_Decode, 142, 7, 65, // Opcode: UASX +/* 6368 */ MCD_OPC_FilterValue, 2, 180, 7, 0, // Skip to: 8345 +/* 6373 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 6376 */ MCD_OPC_FilterValue, 0, 172, 7, 0, // Skip to: 8345 +/* 6381 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 6397 +/* 6386 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6397 +/* 6393 */ MCD_OPC_Decode, 160, 6, 30, // Opcode: SMMULR +/* 6397 */ MCD_OPC_CheckPredicate, 1, 151, 7, 0, // Skip to: 8345 +/* 6402 */ MCD_OPC_Decode, 156, 6, 39, // Opcode: SMMLAR +/* 6406 */ MCD_OPC_FilterValue, 2, 85, 0, 0, // Skip to: 6496 +/* 6411 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 6414 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6468 +/* 6419 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6422 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6443 +/* 6427 */ MCD_OPC_CheckPredicate, 1, 121, 7, 0, // Skip to: 8345 +/* 6432 */ MCD_OPC_CheckField, 23, 2, 2, 114, 7, 0, // Skip to: 8345 +/* 6439 */ MCD_OPC_Decode, 153, 6, 19, // Opcode: SMLSLD +/* 6443 */ MCD_OPC_FilterValue, 1, 105, 7, 0, // Skip to: 8345 +/* 6448 */ MCD_OPC_CheckPredicate, 0, 100, 7, 0, // Skip to: 8345 +/* 6453 */ MCD_OPC_CheckField, 23, 2, 0, 93, 7, 0, // Skip to: 8345 +/* 6460 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6464 */ MCD_OPC_Decode, 165, 7, 65, // Opcode: USAX +/* 6468 */ MCD_OPC_FilterValue, 1, 80, 7, 0, // Skip to: 8345 +/* 6473 */ MCD_OPC_CheckPredicate, 1, 75, 7, 0, // Skip to: 8345 +/* 6478 */ MCD_OPC_CheckField, 23, 2, 2, 68, 7, 0, // Skip to: 8345 +/* 6485 */ MCD_OPC_CheckField, 20, 1, 1, 61, 7, 0, // Skip to: 8345 +/* 6492 */ MCD_OPC_Decode, 157, 6, 39, // Opcode: SMMLS +/* 6496 */ MCD_OPC_FilterValue, 3, 52, 7, 0, // Skip to: 8345 +/* 6501 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 6504 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 6562 +/* 6509 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 6512 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6537 +/* 6517 */ MCD_OPC_CheckPredicate, 0, 31, 7, 0, // Skip to: 8345 +/* 6522 */ MCD_OPC_CheckField, 20, 1, 1, 24, 7, 0, // Skip to: 8345 +/* 6529 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6533 */ MCD_OPC_Decode, 166, 7, 65, // Opcode: USUB16 +/* 6537 */ MCD_OPC_FilterValue, 1, 11, 7, 0, // Skip to: 8345 +/* 6542 */ MCD_OPC_CheckPredicate, 0, 6, 7, 0, // Skip to: 8345 +/* 6547 */ MCD_OPC_CheckField, 20, 1, 1, 255, 6, 0, // Skip to: 8345 +/* 6554 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6558 */ MCD_OPC_Decode, 167, 7, 65, // Opcode: USUB8 +/* 6562 */ MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 6616 +/* 6567 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 6570 */ MCD_OPC_FilterValue, 0, 234, 6, 0, // Skip to: 8345 +/* 6575 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6578 */ MCD_OPC_FilterValue, 0, 226, 6, 0, // Skip to: 8345 +/* 6583 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 6603 +/* 6588 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 6603 +/* 6595 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 6599 */ MCD_OPC_Decode, 172, 7, 70, // Opcode: UXTB16 +/* 6603 */ MCD_OPC_CheckPredicate, 1, 201, 6, 0, // Skip to: 8345 +/* 6608 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 6612 */ MCD_OPC_Decode, 169, 7, 71, // Opcode: UXTAB16 +/* 6616 */ MCD_OPC_FilterValue, 2, 188, 6, 0, // Skip to: 8345 +/* 6621 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 6624 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6645 +/* 6629 */ MCD_OPC_CheckPredicate, 1, 175, 6, 0, // Skip to: 8345 +/* 6634 */ MCD_OPC_CheckField, 20, 1, 0, 168, 6, 0, // Skip to: 8345 +/* 6641 */ MCD_OPC_Decode, 154, 6, 19, // Opcode: SMLSLDX +/* 6645 */ MCD_OPC_FilterValue, 1, 159, 6, 0, // Skip to: 8345 +/* 6650 */ MCD_OPC_CheckPredicate, 1, 154, 6, 0, // Skip to: 8345 +/* 6655 */ MCD_OPC_CheckField, 20, 1, 1, 147, 6, 0, // Skip to: 8345 +/* 6662 */ MCD_OPC_Decode, 158, 6, 39, // Opcode: SMMLSR +/* 6666 */ MCD_OPC_FilterValue, 3, 138, 6, 0, // Skip to: 8345 +/* 6671 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 6674 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 6754 +/* 6679 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6682 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6718 +/* 6687 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 6690 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6704 +/* 6695 */ MCD_OPC_CheckPredicate, 0, 109, 6, 0, // Skip to: 8345 +/* 6700 */ MCD_OPC_Decode, 217, 6, 55, // Opcode: STRBT_POST_REG +/* 6704 */ MCD_OPC_FilterValue, 1, 100, 6, 0, // Skip to: 8345 +/* 6709 */ MCD_OPC_CheckPredicate, 0, 95, 6, 0, // Skip to: 8345 +/* 6714 */ MCD_OPC_Decode, 221, 6, 72, // Opcode: STRB_PRE_REG +/* 6718 */ MCD_OPC_FilterValue, 1, 86, 6, 0, // Skip to: 8345 +/* 6723 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 6726 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6740 +/* 6731 */ MCD_OPC_CheckPredicate, 0, 73, 6, 0, // Skip to: 8345 +/* 6736 */ MCD_OPC_Decode, 254, 4, 55, // Opcode: LDRBT_POST_REG +/* 6740 */ MCD_OPC_FilterValue, 1, 64, 6, 0, // Skip to: 8345 +/* 6745 */ MCD_OPC_CheckPredicate, 0, 59, 6, 0, // Skip to: 8345 +/* 6750 */ MCD_OPC_Decode, 130, 5, 73, // Opcode: LDRB_PRE_REG +/* 6754 */ MCD_OPC_FilterValue, 1, 50, 6, 0, // Skip to: 8345 +/* 6759 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 6762 */ MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 7034 +/* 6767 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 6770 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 6814 +/* 6775 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6778 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6796 +/* 6783 */ MCD_OPC_CheckPredicate, 0, 21, 6, 0, // Skip to: 8345 +/* 6788 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6792 */ MCD_OPC_Decode, 155, 7, 65, // Opcode: UQADD16 +/* 6796 */ MCD_OPC_FilterValue, 1, 8, 6, 0, // Skip to: 8345 +/* 6801 */ MCD_OPC_CheckPredicate, 0, 3, 6, 0, // Skip to: 8345 +/* 6806 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6810 */ MCD_OPC_Decode, 146, 7, 65, // Opcode: UHADD16 +/* 6814 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 6858 +/* 6819 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6822 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6840 +/* 6827 */ MCD_OPC_CheckPredicate, 0, 233, 5, 0, // Skip to: 8345 +/* 6832 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6836 */ MCD_OPC_Decode, 157, 7, 65, // Opcode: UQASX +/* 6840 */ MCD_OPC_FilterValue, 1, 220, 5, 0, // Skip to: 8345 +/* 6845 */ MCD_OPC_CheckPredicate, 0, 215, 5, 0, // Skip to: 8345 +/* 6850 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6854 */ MCD_OPC_Decode, 148, 7, 65, // Opcode: UHASX +/* 6858 */ MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 6902 +/* 6863 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6866 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6884 +/* 6871 */ MCD_OPC_CheckPredicate, 0, 189, 5, 0, // Skip to: 8345 +/* 6876 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6880 */ MCD_OPC_Decode, 158, 7, 65, // Opcode: UQSAX +/* 6884 */ MCD_OPC_FilterValue, 1, 176, 5, 0, // Skip to: 8345 +/* 6889 */ MCD_OPC_CheckPredicate, 0, 171, 5, 0, // Skip to: 8345 +/* 6894 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6898 */ MCD_OPC_Decode, 149, 7, 65, // Opcode: UHSAX +/* 6902 */ MCD_OPC_FilterValue, 3, 39, 0, 0, // Skip to: 6946 +/* 6907 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6910 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6928 +/* 6915 */ MCD_OPC_CheckPredicate, 0, 145, 5, 0, // Skip to: 8345 +/* 6920 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6924 */ MCD_OPC_Decode, 159, 7, 65, // Opcode: UQSUB16 +/* 6928 */ MCD_OPC_FilterValue, 1, 132, 5, 0, // Skip to: 8345 +/* 6933 */ MCD_OPC_CheckPredicate, 0, 127, 5, 0, // Skip to: 8345 +/* 6938 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6942 */ MCD_OPC_Decode, 150, 7, 65, // Opcode: UHSUB16 +/* 6946 */ MCD_OPC_FilterValue, 4, 39, 0, 0, // Skip to: 6990 +/* 6951 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6954 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6972 +/* 6959 */ MCD_OPC_CheckPredicate, 0, 101, 5, 0, // Skip to: 8345 +/* 6964 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6968 */ MCD_OPC_Decode, 156, 7, 65, // Opcode: UQADD8 +/* 6972 */ MCD_OPC_FilterValue, 1, 88, 5, 0, // Skip to: 8345 +/* 6977 */ MCD_OPC_CheckPredicate, 0, 83, 5, 0, // Skip to: 8345 +/* 6982 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 6986 */ MCD_OPC_Decode, 147, 7, 65, // Opcode: UHADD8 +/* 6990 */ MCD_OPC_FilterValue, 7, 70, 5, 0, // Skip to: 8345 +/* 6995 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6998 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 7016 +/* 7003 */ MCD_OPC_CheckPredicate, 0, 57, 5, 0, // Skip to: 8345 +/* 7008 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 7012 */ MCD_OPC_Decode, 160, 7, 65, // Opcode: UQSUB8 +/* 7016 */ MCD_OPC_FilterValue, 1, 44, 5, 0, // Skip to: 8345 +/* 7021 */ MCD_OPC_CheckPredicate, 0, 39, 5, 0, // Skip to: 8345 +/* 7026 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, +/* 7030 */ MCD_OPC_Decode, 151, 7, 65, // Opcode: UHSUB8 +/* 7034 */ MCD_OPC_FilterValue, 1, 194, 0, 0, // Skip to: 7233 +/* 7039 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 7042 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7056 +/* 7047 */ MCD_OPC_CheckPredicate, 1, 13, 5, 0, // Skip to: 8345 +/* 7052 */ MCD_OPC_Decode, 163, 7, 74, // Opcode: USAT +/* 7056 */ MCD_OPC_FilterValue, 1, 4, 5, 0, // Skip to: 8345 +/* 7061 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7064 */ MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 7121 +/* 7069 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7072 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7093 +/* 7077 */ MCD_OPC_CheckPredicate, 1, 239, 4, 0, // Skip to: 8345 +/* 7082 */ MCD_OPC_CheckField, 8, 4, 15, 232, 4, 0, // Skip to: 8345 +/* 7089 */ MCD_OPC_Decode, 164, 7, 75, // Opcode: USAT16 +/* 7093 */ MCD_OPC_FilterValue, 1, 223, 4, 0, // Skip to: 8345 +/* 7098 */ MCD_OPC_CheckPredicate, 13, 218, 4, 0, // Skip to: 8345 +/* 7103 */ MCD_OPC_CheckField, 16, 4, 15, 211, 4, 0, // Skip to: 8345 +/* 7110 */ MCD_OPC_CheckField, 8, 4, 15, 204, 4, 0, // Skip to: 8345 +/* 7117 */ MCD_OPC_Decode, 215, 5, 35, // Opcode: RBIT +/* 7121 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 7205 +/* 7126 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7129 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7167 +/* 7134 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 7154 +/* 7139 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 7154 +/* 7146 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 7150 */ MCD_OPC_Decode, 171, 7, 70, // Opcode: UXTB +/* 7154 */ MCD_OPC_CheckPredicate, 1, 162, 4, 0, // Skip to: 8345 +/* 7159 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 7163 */ MCD_OPC_Decode, 168, 7, 71, // Opcode: UXTAB +/* 7167 */ MCD_OPC_FilterValue, 1, 149, 4, 0, // Skip to: 8345 +/* 7172 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 7192 +/* 7177 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 7192 +/* 7184 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 7188 */ MCD_OPC_Decode, 173, 7, 70, // Opcode: UXTH +/* 7192 */ MCD_OPC_CheckPredicate, 1, 124, 4, 0, // Skip to: 8345 +/* 7197 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, +/* 7201 */ MCD_OPC_Decode, 170, 7, 71, // Opcode: UXTAH +/* 7205 */ MCD_OPC_FilterValue, 2, 111, 4, 0, // Skip to: 8345 +/* 7210 */ MCD_OPC_CheckPredicate, 1, 106, 4, 0, // Skip to: 8345 +/* 7215 */ MCD_OPC_CheckField, 16, 5, 31, 99, 4, 0, // Skip to: 8345 +/* 7222 */ MCD_OPC_CheckField, 8, 4, 15, 92, 4, 0, // Skip to: 8345 +/* 7229 */ MCD_OPC_Decode, 218, 5, 35, // Opcode: REVSH +/* 7233 */ MCD_OPC_FilterValue, 3, 83, 4, 0, // Skip to: 8345 +/* 7238 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... +/* 7241 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7255 +/* 7246 */ MCD_OPC_CheckPredicate, 13, 70, 4, 0, // Skip to: 8345 +/* 7251 */ MCD_OPC_Decode, 143, 7, 76, // Opcode: UBFX +/* 7255 */ MCD_OPC_FilterValue, 3, 61, 4, 0, // Skip to: 8345 +/* 7260 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 7263 */ MCD_OPC_FilterValue, 1, 53, 4, 0, // Skip to: 8345 +/* 7268 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7271 */ MCD_OPC_FilterValue, 1, 45, 4, 0, // Skip to: 8345 +/* 7276 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... +/* 7279 */ MCD_OPC_FilterValue, 14, 37, 4, 0, // Skip to: 8345 +/* 7284 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 7287 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7309 +/* 7292 */ MCD_OPC_CheckPredicate, 20, 34, 0, 0, // Skip to: 7331 +/* 7297 */ MCD_OPC_CheckField, 8, 12, 222, 29, 26, 0, 0, // Skip to: 7331 +/* 7305 */ MCD_OPC_Decode, 134, 7, 51, // Opcode: TRAPNaCl +/* 7309 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7331 +/* 7314 */ MCD_OPC_CheckPredicate, 0, 12, 0, 0, // Skip to: 7331 +/* 7319 */ MCD_OPC_CheckField, 8, 12, 222, 31, 4, 0, 0, // Skip to: 7331 +/* 7327 */ MCD_OPC_Decode, 133, 7, 51, // Opcode: TRAP +/* 7331 */ MCD_OPC_CheckPredicate, 0, 241, 3, 0, // Skip to: 8345 +/* 7336 */ MCD_OPC_Decode, 144, 7, 15, // Opcode: UDF +/* 7340 */ MCD_OPC_FilterValue, 4, 75, 3, 0, // Skip to: 8188 +/* 7345 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... +/* 7348 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7362 +/* 7353 */ MCD_OPC_CheckPredicate, 0, 219, 3, 0, // Skip to: 8345 +/* 7358 */ MCD_OPC_Decode, 208, 6, 80, // Opcode: STMDA +/* 7362 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 7400 +/* 7367 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7391 +/* 7372 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7391 +/* 7379 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7391 +/* 7387 */ MCD_OPC_Decode, 219, 5, 81, // Opcode: RFEDA +/* 7391 */ MCD_OPC_CheckPredicate, 0, 181, 3, 0, // Skip to: 8345 +/* 7396 */ MCD_OPC_Decode, 245, 4, 80, // Opcode: LDMDA +/* 7400 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7414 +/* 7405 */ MCD_OPC_CheckPredicate, 0, 167, 3, 0, // Skip to: 8345 +/* 7410 */ MCD_OPC_Decode, 209, 6, 82, // Opcode: STMDA_UPD +/* 7414 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 7452 +/* 7419 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7443 +/* 7424 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7443 +/* 7431 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7443 +/* 7439 */ MCD_OPC_Decode, 220, 5, 81, // Opcode: RFEDA_UPD +/* 7443 */ MCD_OPC_CheckPredicate, 0, 129, 3, 0, // Skip to: 8345 +/* 7448 */ MCD_OPC_Decode, 246, 4, 82, // Opcode: LDMDA_UPD +/* 7452 */ MCD_OPC_FilterValue, 4, 34, 0, 0, // Skip to: 7491 +/* 7457 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7482 +/* 7462 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7482 +/* 7469 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7482 +/* 7478 */ MCD_OPC_Decode, 172, 6, 83, // Opcode: SRSDA +/* 7482 */ MCD_OPC_CheckPredicate, 0, 90, 3, 0, // Skip to: 8345 +/* 7487 */ MCD_OPC_Decode, 190, 21, 80, // Opcode: sysSTMDA +/* 7491 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 7505 +/* 7496 */ MCD_OPC_CheckPredicate, 0, 76, 3, 0, // Skip to: 8345 +/* 7501 */ MCD_OPC_Decode, 182, 21, 80, // Opcode: sysLDMDA +/* 7505 */ MCD_OPC_FilterValue, 6, 34, 0, 0, // Skip to: 7544 +/* 7510 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7535 +/* 7515 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7535 +/* 7522 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7535 +/* 7531 */ MCD_OPC_Decode, 173, 6, 83, // Opcode: SRSDA_UPD +/* 7535 */ MCD_OPC_CheckPredicate, 0, 37, 3, 0, // Skip to: 8345 +/* 7540 */ MCD_OPC_Decode, 191, 21, 82, // Opcode: sysSTMDA_UPD +/* 7544 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 7558 +/* 7549 */ MCD_OPC_CheckPredicate, 0, 23, 3, 0, // Skip to: 8345 +/* 7554 */ MCD_OPC_Decode, 183, 21, 82, // Opcode: sysLDMDA_UPD +/* 7558 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7572 +/* 7563 */ MCD_OPC_CheckPredicate, 0, 9, 3, 0, // Skip to: 8345 +/* 7568 */ MCD_OPC_Decode, 212, 6, 80, // Opcode: STMIA +/* 7572 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 7610 +/* 7577 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7601 +/* 7582 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7601 +/* 7589 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7601 +/* 7597 */ MCD_OPC_Decode, 223, 5, 81, // Opcode: RFEIA +/* 7601 */ MCD_OPC_CheckPredicate, 0, 227, 2, 0, // Skip to: 8345 +/* 7606 */ MCD_OPC_Decode, 249, 4, 80, // Opcode: LDMIA +/* 7610 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7624 +/* 7615 */ MCD_OPC_CheckPredicate, 0, 213, 2, 0, // Skip to: 8345 +/* 7620 */ MCD_OPC_Decode, 213, 6, 82, // Opcode: STMIA_UPD +/* 7624 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 7662 +/* 7629 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7653 +/* 7634 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7653 +/* 7641 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7653 +/* 7649 */ MCD_OPC_Decode, 224, 5, 81, // Opcode: RFEIA_UPD +/* 7653 */ MCD_OPC_CheckPredicate, 0, 175, 2, 0, // Skip to: 8345 +/* 7658 */ MCD_OPC_Decode, 250, 4, 82, // Opcode: LDMIA_UPD +/* 7662 */ MCD_OPC_FilterValue, 12, 34, 0, 0, // Skip to: 7701 +/* 7667 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7692 +/* 7672 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7692 +/* 7679 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7692 +/* 7688 */ MCD_OPC_Decode, 176, 6, 83, // Opcode: SRSIA +/* 7692 */ MCD_OPC_CheckPredicate, 0, 136, 2, 0, // Skip to: 8345 +/* 7697 */ MCD_OPC_Decode, 194, 21, 80, // Opcode: sysSTMIA +/* 7701 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 7715 +/* 7706 */ MCD_OPC_CheckPredicate, 0, 122, 2, 0, // Skip to: 8345 +/* 7711 */ MCD_OPC_Decode, 186, 21, 80, // Opcode: sysLDMIA +/* 7715 */ MCD_OPC_FilterValue, 14, 34, 0, 0, // Skip to: 7754 +/* 7720 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7745 +/* 7725 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7745 +/* 7732 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7745 +/* 7741 */ MCD_OPC_Decode, 177, 6, 83, // Opcode: SRSIA_UPD +/* 7745 */ MCD_OPC_CheckPredicate, 0, 83, 2, 0, // Skip to: 8345 +/* 7750 */ MCD_OPC_Decode, 195, 21, 82, // Opcode: sysSTMIA_UPD +/* 7754 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 7768 +/* 7759 */ MCD_OPC_CheckPredicate, 0, 69, 2, 0, // Skip to: 8345 +/* 7764 */ MCD_OPC_Decode, 187, 21, 82, // Opcode: sysLDMIA_UPD +/* 7768 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 7782 +/* 7773 */ MCD_OPC_CheckPredicate, 0, 55, 2, 0, // Skip to: 8345 +/* 7778 */ MCD_OPC_Decode, 210, 6, 80, // Opcode: STMDB +/* 7782 */ MCD_OPC_FilterValue, 17, 33, 0, 0, // Skip to: 7820 +/* 7787 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7811 +/* 7792 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7811 +/* 7799 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7811 +/* 7807 */ MCD_OPC_Decode, 221, 5, 81, // Opcode: RFEDB +/* 7811 */ MCD_OPC_CheckPredicate, 0, 17, 2, 0, // Skip to: 8345 +/* 7816 */ MCD_OPC_Decode, 247, 4, 80, // Opcode: LDMDB +/* 7820 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 7834 +/* 7825 */ MCD_OPC_CheckPredicate, 0, 3, 2, 0, // Skip to: 8345 +/* 7830 */ MCD_OPC_Decode, 211, 6, 82, // Opcode: STMDB_UPD +/* 7834 */ MCD_OPC_FilterValue, 19, 33, 0, 0, // Skip to: 7872 +/* 7839 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7863 +/* 7844 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7863 +/* 7851 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7863 +/* 7859 */ MCD_OPC_Decode, 222, 5, 81, // Opcode: RFEDB_UPD +/* 7863 */ MCD_OPC_CheckPredicate, 0, 221, 1, 0, // Skip to: 8345 +/* 7868 */ MCD_OPC_Decode, 248, 4, 82, // Opcode: LDMDB_UPD +/* 7872 */ MCD_OPC_FilterValue, 20, 34, 0, 0, // Skip to: 7911 +/* 7877 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7902 +/* 7882 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7902 +/* 7889 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7902 +/* 7898 */ MCD_OPC_Decode, 174, 6, 83, // Opcode: SRSDB +/* 7902 */ MCD_OPC_CheckPredicate, 0, 182, 1, 0, // Skip to: 8345 +/* 7907 */ MCD_OPC_Decode, 192, 21, 80, // Opcode: sysSTMDB +/* 7911 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 7925 +/* 7916 */ MCD_OPC_CheckPredicate, 0, 168, 1, 0, // Skip to: 8345 +/* 7921 */ MCD_OPC_Decode, 184, 21, 80, // Opcode: sysLDMDB +/* 7925 */ MCD_OPC_FilterValue, 22, 34, 0, 0, // Skip to: 7964 +/* 7930 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7955 +/* 7935 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7955 +/* 7942 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7955 +/* 7951 */ MCD_OPC_Decode, 175, 6, 83, // Opcode: SRSDB_UPD +/* 7955 */ MCD_OPC_CheckPredicate, 0, 129, 1, 0, // Skip to: 8345 +/* 7960 */ MCD_OPC_Decode, 193, 21, 82, // Opcode: sysSTMDB_UPD +/* 7964 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 7978 +/* 7969 */ MCD_OPC_CheckPredicate, 0, 115, 1, 0, // Skip to: 8345 +/* 7974 */ MCD_OPC_Decode, 185, 21, 82, // Opcode: sysLDMDB_UPD +/* 7978 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 7992 +/* 7983 */ MCD_OPC_CheckPredicate, 0, 101, 1, 0, // Skip to: 8345 +/* 7988 */ MCD_OPC_Decode, 214, 6, 80, // Opcode: STMIB +/* 7992 */ MCD_OPC_FilterValue, 25, 33, 0, 0, // Skip to: 8030 +/* 7997 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 8021 +/* 8002 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 8021 +/* 8009 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 8021 +/* 8017 */ MCD_OPC_Decode, 225, 5, 81, // Opcode: RFEIB +/* 8021 */ MCD_OPC_CheckPredicate, 0, 63, 1, 0, // Skip to: 8345 +/* 8026 */ MCD_OPC_Decode, 251, 4, 80, // Opcode: LDMIB +/* 8030 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 8044 +/* 8035 */ MCD_OPC_CheckPredicate, 0, 49, 1, 0, // Skip to: 8345 +/* 8040 */ MCD_OPC_Decode, 215, 6, 82, // Opcode: STMIB_UPD +/* 8044 */ MCD_OPC_FilterValue, 27, 33, 0, 0, // Skip to: 8082 +/* 8049 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 8073 +/* 8054 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 8073 +/* 8061 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 8073 +/* 8069 */ MCD_OPC_Decode, 226, 5, 81, // Opcode: RFEIB_UPD +/* 8073 */ MCD_OPC_CheckPredicate, 0, 11, 1, 0, // Skip to: 8345 +/* 8078 */ MCD_OPC_Decode, 252, 4, 82, // Opcode: LDMIB_UPD +/* 8082 */ MCD_OPC_FilterValue, 28, 34, 0, 0, // Skip to: 8121 +/* 8087 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 8112 +/* 8092 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 8112 +/* 8099 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 8112 +/* 8108 */ MCD_OPC_Decode, 178, 6, 83, // Opcode: SRSIB +/* 8112 */ MCD_OPC_CheckPredicate, 0, 228, 0, 0, // Skip to: 8345 +/* 8117 */ MCD_OPC_Decode, 196, 21, 80, // Opcode: sysSTMIB +/* 8121 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 8135 +/* 8126 */ MCD_OPC_CheckPredicate, 0, 214, 0, 0, // Skip to: 8345 +/* 8131 */ MCD_OPC_Decode, 188, 21, 80, // Opcode: sysLDMIB +/* 8135 */ MCD_OPC_FilterValue, 30, 34, 0, 0, // Skip to: 8174 +/* 8140 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 8165 +/* 8145 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 8165 +/* 8152 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 8165 +/* 8161 */ MCD_OPC_Decode, 179, 6, 83, // Opcode: SRSIB_UPD +/* 8165 */ MCD_OPC_CheckPredicate, 0, 175, 0, 0, // Skip to: 8345 +/* 8170 */ MCD_OPC_Decode, 197, 21, 82, // Opcode: sysSTMIB_UPD +/* 8174 */ MCD_OPC_FilterValue, 31, 166, 0, 0, // Skip to: 8345 +/* 8179 */ MCD_OPC_CheckPredicate, 0, 161, 0, 0, // Skip to: 8345 +/* 8184 */ MCD_OPC_Decode, 189, 21, 82, // Opcode: sysLDMIB_UPD +/* 8188 */ MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 8256 +/* 8193 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 8196 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8210 +/* 8201 */ MCD_OPC_CheckPredicate, 0, 34, 0, 0, // Skip to: 8240 +/* 8206 */ MCD_OPC_Decode, 178, 4, 84, // Opcode: Bcc +/* 8210 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 8240 +/* 8215 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 8231 +/* 8220 */ MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 8231 +/* 8227 */ MCD_OPC_Decode, 169, 4, 84, // Opcode: BL +/* 8231 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 8240 +/* 8236 */ MCD_OPC_Decode, 173, 4, 84, // Opcode: BL_pred +/* 8240 */ MCD_OPC_CheckPredicate, 11, 100, 0, 0, // Skip to: 8345 +/* 8245 */ MCD_OPC_CheckField, 28, 4, 15, 93, 0, 0, // Skip to: 8345 +/* 8252 */ MCD_OPC_Decode, 172, 4, 85, // Opcode: BLXi +/* 8256 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 8324 +/* 8261 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... +/* 8264 */ MCD_OPC_FilterValue, 4, 25, 0, 0, // Skip to: 8294 +/* 8269 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 8285 +/* 8274 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 8285 +/* 8281 */ MCD_OPC_Decode, 167, 5, 86, // Opcode: MCRR2 +/* 8285 */ MCD_OPC_CheckPredicate, 0, 55, 0, 0, // Skip to: 8345 +/* 8290 */ MCD_OPC_Decode, 166, 5, 87, // Opcode: MCRR +/* 8294 */ MCD_OPC_FilterValue, 5, 46, 0, 0, // Skip to: 8345 +/* 8299 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 8315 +/* 8304 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 8315 +/* 8311 */ MCD_OPC_Decode, 181, 5, 86, // Opcode: MRRC2 +/* 8315 */ MCD_OPC_CheckPredicate, 0, 25, 0, 0, // Skip to: 8345 +/* 8320 */ MCD_OPC_Decode, 180, 5, 88, // Opcode: MRRC +/* 8324 */ MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 8345 +/* 8329 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 8345 +/* 8334 */ MCD_OPC_CheckField, 24, 1, 1, 4, 0, 0, // Skip to: 8345 +/* 8341 */ MCD_OPC_Decode, 248, 6, 89, // Opcode: SVC +/* 8345 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableCoProc32[] = { +/* 0 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 3 */ MCD_OPC_FilterValue, 12, 19, 1, 0, // Skip to: 283 +/* 8 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 11 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 49 +/* 16 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 19 */ MCD_OPC_FilterValue, 1, 101, 2, 0, // Skip to: 637 +/* 24 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 40 +/* 29 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 40 +/* 36 */ MCD_OPC_Decode, 190, 6, 90, // Opcode: STC2_OPTION +/* 40 */ MCD_OPC_CheckPredicate, 0, 80, 2, 0, // Skip to: 637 +/* 45 */ MCD_OPC_Decode, 198, 6, 90, // Opcode: STC_OPTION +/* 49 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 87 +/* 54 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 57 */ MCD_OPC_FilterValue, 1, 63, 2, 0, // Skip to: 637 +/* 62 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 78 +/* 67 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 78 +/* 74 */ MCD_OPC_Decode, 234, 4, 90, // Opcode: LDC2_OPTION +/* 78 */ MCD_OPC_CheckPredicate, 0, 42, 2, 0, // Skip to: 637 +/* 83 */ MCD_OPC_Decode, 242, 4, 90, // Opcode: LDC_OPTION +/* 87 */ MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 117 +/* 92 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 108 +/* 97 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 108 +/* 104 */ MCD_OPC_Decode, 191, 6, 90, // Opcode: STC2_POST +/* 108 */ MCD_OPC_CheckPredicate, 0, 12, 2, 0, // Skip to: 637 +/* 113 */ MCD_OPC_Decode, 199, 6, 90, // Opcode: STC_POST +/* 117 */ MCD_OPC_FilterValue, 3, 25, 0, 0, // Skip to: 147 +/* 122 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 138 +/* 127 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 138 +/* 134 */ MCD_OPC_Decode, 235, 4, 90, // Opcode: LDC2_POST +/* 138 */ MCD_OPC_CheckPredicate, 0, 238, 1, 0, // Skip to: 637 +/* 143 */ MCD_OPC_Decode, 243, 4, 90, // Opcode: LDC_POST +/* 147 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 185 +/* 152 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 155 */ MCD_OPC_FilterValue, 1, 221, 1, 0, // Skip to: 637 +/* 160 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 176 +/* 165 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 176 +/* 172 */ MCD_OPC_Decode, 186, 6, 90, // Opcode: STC2L_OPTION +/* 176 */ MCD_OPC_CheckPredicate, 0, 200, 1, 0, // Skip to: 637 +/* 181 */ MCD_OPC_Decode, 194, 6, 90, // Opcode: STCL_OPTION +/* 185 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 223 +/* 190 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 193 */ MCD_OPC_FilterValue, 1, 183, 1, 0, // Skip to: 637 +/* 198 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 214 +/* 203 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 214 +/* 210 */ MCD_OPC_Decode, 230, 4, 90, // Opcode: LDC2L_OPTION +/* 214 */ MCD_OPC_CheckPredicate, 0, 162, 1, 0, // Skip to: 637 +/* 219 */ MCD_OPC_Decode, 238, 4, 90, // Opcode: LDCL_OPTION +/* 223 */ MCD_OPC_FilterValue, 6, 25, 0, 0, // Skip to: 253 +/* 228 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 244 +/* 233 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 244 +/* 240 */ MCD_OPC_Decode, 187, 6, 90, // Opcode: STC2L_POST +/* 244 */ MCD_OPC_CheckPredicate, 0, 132, 1, 0, // Skip to: 637 +/* 249 */ MCD_OPC_Decode, 195, 6, 90, // Opcode: STCL_POST +/* 253 */ MCD_OPC_FilterValue, 7, 123, 1, 0, // Skip to: 637 +/* 258 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 274 +/* 263 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 274 +/* 270 */ MCD_OPC_Decode, 231, 4, 90, // Opcode: LDC2L_POST +/* 274 */ MCD_OPC_CheckPredicate, 0, 102, 1, 0, // Skip to: 637 +/* 279 */ MCD_OPC_Decode, 239, 4, 90, // Opcode: LDCL_POST +/* 283 */ MCD_OPC_FilterValue, 13, 243, 0, 0, // Skip to: 531 +/* 288 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 291 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 321 +/* 296 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 312 +/* 301 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 312 +/* 308 */ MCD_OPC_Decode, 189, 6, 90, // Opcode: STC2_OFFSET +/* 312 */ MCD_OPC_CheckPredicate, 0, 64, 1, 0, // Skip to: 637 +/* 317 */ MCD_OPC_Decode, 197, 6, 90, // Opcode: STC_OFFSET +/* 321 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 351 +/* 326 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 342 +/* 331 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 342 +/* 338 */ MCD_OPC_Decode, 233, 4, 90, // Opcode: LDC2_OFFSET +/* 342 */ MCD_OPC_CheckPredicate, 0, 34, 1, 0, // Skip to: 637 +/* 347 */ MCD_OPC_Decode, 241, 4, 90, // Opcode: LDC_OFFSET +/* 351 */ MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 381 +/* 356 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 372 +/* 361 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 372 +/* 368 */ MCD_OPC_Decode, 192, 6, 90, // Opcode: STC2_PRE +/* 372 */ MCD_OPC_CheckPredicate, 0, 4, 1, 0, // Skip to: 637 +/* 377 */ MCD_OPC_Decode, 200, 6, 90, // Opcode: STC_PRE +/* 381 */ MCD_OPC_FilterValue, 3, 25, 0, 0, // Skip to: 411 +/* 386 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 402 +/* 391 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 402 +/* 398 */ MCD_OPC_Decode, 236, 4, 90, // Opcode: LDC2_PRE +/* 402 */ MCD_OPC_CheckPredicate, 0, 230, 0, 0, // Skip to: 637 +/* 407 */ MCD_OPC_Decode, 244, 4, 90, // Opcode: LDC_PRE +/* 411 */ MCD_OPC_FilterValue, 4, 25, 0, 0, // Skip to: 441 +/* 416 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 432 +/* 421 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 432 +/* 428 */ MCD_OPC_Decode, 185, 6, 90, // Opcode: STC2L_OFFSET +/* 432 */ MCD_OPC_CheckPredicate, 0, 200, 0, 0, // Skip to: 637 +/* 437 */ MCD_OPC_Decode, 193, 6, 90, // Opcode: STCL_OFFSET +/* 441 */ MCD_OPC_FilterValue, 5, 25, 0, 0, // Skip to: 471 +/* 446 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 462 +/* 451 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 462 +/* 458 */ MCD_OPC_Decode, 229, 4, 90, // Opcode: LDC2L_OFFSET +/* 462 */ MCD_OPC_CheckPredicate, 0, 170, 0, 0, // Skip to: 637 +/* 467 */ MCD_OPC_Decode, 237, 4, 90, // Opcode: LDCL_OFFSET +/* 471 */ MCD_OPC_FilterValue, 6, 25, 0, 0, // Skip to: 501 +/* 476 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 492 +/* 481 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 492 +/* 488 */ MCD_OPC_Decode, 188, 6, 90, // Opcode: STC2L_PRE +/* 492 */ MCD_OPC_CheckPredicate, 0, 140, 0, 0, // Skip to: 637 +/* 497 */ MCD_OPC_Decode, 196, 6, 90, // Opcode: STCL_PRE +/* 501 */ MCD_OPC_FilterValue, 7, 131, 0, 0, // Skip to: 637 +/* 506 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 522 +/* 511 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 522 +/* 518 */ MCD_OPC_Decode, 232, 4, 90, // Opcode: LDC2L_PRE +/* 522 */ MCD_OPC_CheckPredicate, 0, 110, 0, 0, // Skip to: 637 +/* 527 */ MCD_OPC_Decode, 240, 4, 90, // Opcode: LDCL_PRE +/* 531 */ MCD_OPC_FilterValue, 14, 101, 0, 0, // Skip to: 637 +/* 536 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 539 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 569 +/* 544 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 560 +/* 549 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 560 +/* 556 */ MCD_OPC_Decode, 180, 4, 91, // Opcode: CDP2 +/* 560 */ MCD_OPC_CheckPredicate, 4, 72, 0, 0, // Skip to: 637 +/* 565 */ MCD_OPC_Decode, 179, 4, 92, // Opcode: CDP +/* 569 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 637 +/* 574 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 577 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 607 +/* 582 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 598 +/* 587 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 598 +/* 594 */ MCD_OPC_Decode, 165, 5, 93, // Opcode: MCR2 +/* 598 */ MCD_OPC_CheckPredicate, 0, 34, 0, 0, // Skip to: 637 +/* 603 */ MCD_OPC_Decode, 164, 5, 94, // Opcode: MCR +/* 607 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 637 +/* 612 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 628 +/* 617 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 628 +/* 624 */ MCD_OPC_Decode, 179, 5, 95, // Opcode: MRC2 +/* 628 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 637 +/* 633 */ MCD_OPC_Decode, 178, 5, 96, // Opcode: MRC +/* 637 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNEONData32[] = { +/* 0 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 3 */ MCD_OPC_FilterValue, 0, 221, 39, 0, // Skip to: 10213 +/* 8 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11 */ MCD_OPC_FilterValue, 0, 73, 6, 0, // Skip to: 1625 +/* 16 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 19 */ MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 145 +/* 24 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 27 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 64 +/* 33 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 36 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 50 +/* 41 */ MCD_OPC_CheckPredicate, 21, 75, 72, 0, // Skip to: 18553 +/* 46 */ MCD_OPC_Decode, 179, 10, 97, // Opcode: VHADDsv8i8 +/* 50 */ MCD_OPC_FilterValue, 1, 66, 72, 0, // Skip to: 18553 +/* 55 */ MCD_OPC_CheckPredicate, 21, 61, 72, 0, // Skip to: 18553 +/* 60 */ MCD_OPC_Decode, 174, 10, 98, // Opcode: VHADDsv16i8 +/* 64 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 86 +/* 70 */ MCD_OPC_CheckPredicate, 21, 46, 72, 0, // Skip to: 18553 +/* 75 */ MCD_OPC_CheckField, 6, 1, 0, 39, 72, 0, // Skip to: 18553 +/* 82 */ MCD_OPC_Decode, 242, 7, 99, // Opcode: VADDLsv8i16 +/* 86 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 123 +/* 92 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 95 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 109 +/* 100 */ MCD_OPC_CheckPredicate, 21, 16, 72, 0, // Skip to: 18553 +/* 105 */ MCD_OPC_Decode, 185, 10, 97, // Opcode: VHADDuv8i8 +/* 109 */ MCD_OPC_FilterValue, 1, 7, 72, 0, // Skip to: 18553 +/* 114 */ MCD_OPC_CheckPredicate, 21, 2, 72, 0, // Skip to: 18553 +/* 119 */ MCD_OPC_Decode, 180, 10, 98, // Opcode: VHADDuv16i8 +/* 123 */ MCD_OPC_FilterValue, 231, 3, 248, 71, 0, // Skip to: 18553 +/* 129 */ MCD_OPC_CheckPredicate, 21, 243, 71, 0, // Skip to: 18553 +/* 134 */ MCD_OPC_CheckField, 6, 1, 0, 236, 71, 0, // Skip to: 18553 +/* 141 */ MCD_OPC_Decode, 245, 7, 99, // Opcode: VADDLuv8i16 +/* 145 */ MCD_OPC_FilterValue, 1, 121, 0, 0, // Skip to: 271 +/* 150 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 153 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 190 +/* 159 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 162 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 176 +/* 167 */ MCD_OPC_CheckPredicate, 21, 205, 71, 0, // Skip to: 18553 +/* 172 */ MCD_OPC_Decode, 240, 16, 97, // Opcode: VRHADDsv8i8 +/* 176 */ MCD_OPC_FilterValue, 1, 196, 71, 0, // Skip to: 18553 +/* 181 */ MCD_OPC_CheckPredicate, 21, 191, 71, 0, // Skip to: 18553 +/* 186 */ MCD_OPC_Decode, 235, 16, 98, // Opcode: VRHADDsv16i8 +/* 190 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 212 +/* 196 */ MCD_OPC_CheckPredicate, 21, 176, 71, 0, // Skip to: 18553 +/* 201 */ MCD_OPC_CheckField, 6, 1, 0, 169, 71, 0, // Skip to: 18553 +/* 208 */ MCD_OPC_Decode, 249, 7, 100, // Opcode: VADDWsv8i16 +/* 212 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 249 +/* 218 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 221 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 235 +/* 226 */ MCD_OPC_CheckPredicate, 21, 146, 71, 0, // Skip to: 18553 +/* 231 */ MCD_OPC_Decode, 246, 16, 97, // Opcode: VRHADDuv8i8 +/* 235 */ MCD_OPC_FilterValue, 1, 137, 71, 0, // Skip to: 18553 +/* 240 */ MCD_OPC_CheckPredicate, 21, 132, 71, 0, // Skip to: 18553 +/* 245 */ MCD_OPC_Decode, 241, 16, 98, // Opcode: VRHADDuv16i8 +/* 249 */ MCD_OPC_FilterValue, 231, 3, 122, 71, 0, // Skip to: 18553 +/* 255 */ MCD_OPC_CheckPredicate, 21, 117, 71, 0, // Skip to: 18553 +/* 260 */ MCD_OPC_CheckField, 6, 1, 0, 110, 71, 0, // Skip to: 18553 +/* 267 */ MCD_OPC_Decode, 252, 7, 100, // Opcode: VADDWuv8i16 +/* 271 */ MCD_OPC_FilterValue, 2, 121, 0, 0, // Skip to: 397 +/* 276 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 279 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 316 +/* 285 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 288 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 302 +/* 293 */ MCD_OPC_CheckPredicate, 21, 79, 71, 0, // Skip to: 18553 +/* 298 */ MCD_OPC_Decode, 191, 10, 97, // Opcode: VHSUBsv8i8 +/* 302 */ MCD_OPC_FilterValue, 1, 70, 71, 0, // Skip to: 18553 +/* 307 */ MCD_OPC_CheckPredicate, 21, 65, 71, 0, // Skip to: 18553 +/* 312 */ MCD_OPC_Decode, 186, 10, 98, // Opcode: VHSUBsv16i8 +/* 316 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 338 +/* 322 */ MCD_OPC_CheckPredicate, 21, 50, 71, 0, // Skip to: 18553 +/* 327 */ MCD_OPC_CheckField, 6, 1, 0, 43, 71, 0, // Skip to: 18553 +/* 334 */ MCD_OPC_Decode, 214, 20, 99, // Opcode: VSUBLsv8i16 +/* 338 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 375 +/* 344 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 347 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 361 +/* 352 */ MCD_OPC_CheckPredicate, 21, 20, 71, 0, // Skip to: 18553 +/* 357 */ MCD_OPC_Decode, 197, 10, 97, // Opcode: VHSUBuv8i8 +/* 361 */ MCD_OPC_FilterValue, 1, 11, 71, 0, // Skip to: 18553 +/* 366 */ MCD_OPC_CheckPredicate, 21, 6, 71, 0, // Skip to: 18553 +/* 371 */ MCD_OPC_Decode, 192, 10, 98, // Opcode: VHSUBuv16i8 +/* 375 */ MCD_OPC_FilterValue, 231, 3, 252, 70, 0, // Skip to: 18553 +/* 381 */ MCD_OPC_CheckPredicate, 21, 247, 70, 0, // Skip to: 18553 +/* 386 */ MCD_OPC_CheckField, 6, 1, 0, 240, 70, 0, // Skip to: 18553 +/* 393 */ MCD_OPC_Decode, 217, 20, 99, // Opcode: VSUBLuv8i16 +/* 397 */ MCD_OPC_FilterValue, 3, 121, 0, 0, // Skip to: 523 +/* 402 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 405 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 442 +/* 411 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 414 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 428 +/* 419 */ MCD_OPC_CheckPredicate, 21, 209, 70, 0, // Skip to: 18553 +/* 424 */ MCD_OPC_Decode, 210, 8, 97, // Opcode: VCGTsv8i8 +/* 428 */ MCD_OPC_FilterValue, 1, 200, 70, 0, // Skip to: 18553 +/* 433 */ MCD_OPC_CheckPredicate, 21, 195, 70, 0, // Skip to: 18553 +/* 438 */ MCD_OPC_Decode, 205, 8, 98, // Opcode: VCGTsv16i8 +/* 442 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 464 +/* 448 */ MCD_OPC_CheckPredicate, 21, 180, 70, 0, // Skip to: 18553 +/* 453 */ MCD_OPC_CheckField, 6, 1, 0, 173, 70, 0, // Skip to: 18553 +/* 460 */ MCD_OPC_Decode, 221, 20, 100, // Opcode: VSUBWsv8i16 +/* 464 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 501 +/* 470 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 473 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 487 +/* 478 */ MCD_OPC_CheckPredicate, 21, 150, 70, 0, // Skip to: 18553 +/* 483 */ MCD_OPC_Decode, 216, 8, 97, // Opcode: VCGTuv8i8 +/* 487 */ MCD_OPC_FilterValue, 1, 141, 70, 0, // Skip to: 18553 +/* 492 */ MCD_OPC_CheckPredicate, 21, 136, 70, 0, // Skip to: 18553 +/* 497 */ MCD_OPC_Decode, 211, 8, 98, // Opcode: VCGTuv16i8 +/* 501 */ MCD_OPC_FilterValue, 231, 3, 126, 70, 0, // Skip to: 18553 +/* 507 */ MCD_OPC_CheckPredicate, 21, 121, 70, 0, // Skip to: 18553 +/* 512 */ MCD_OPC_CheckField, 6, 1, 0, 114, 70, 0, // Skip to: 18553 +/* 519 */ MCD_OPC_Decode, 224, 20, 100, // Opcode: VSUBWuv8i16 +/* 523 */ MCD_OPC_FilterValue, 4, 121, 0, 0, // Skip to: 649 +/* 528 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 531 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 568 +/* 537 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 540 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 554 +/* 545 */ MCD_OPC_CheckPredicate, 21, 83, 70, 0, // Skip to: 18553 +/* 550 */ MCD_OPC_Decode, 143, 18, 101, // Opcode: VSHLsv8i8 +/* 554 */ MCD_OPC_FilterValue, 1, 74, 70, 0, // Skip to: 18553 +/* 559 */ MCD_OPC_CheckPredicate, 21, 69, 70, 0, // Skip to: 18553 +/* 564 */ MCD_OPC_Decode, 136, 18, 102, // Opcode: VSHLsv16i8 +/* 568 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 590 +/* 574 */ MCD_OPC_CheckPredicate, 21, 54, 70, 0, // Skip to: 18553 +/* 579 */ MCD_OPC_CheckField, 6, 1, 0, 47, 70, 0, // Skip to: 18553 +/* 586 */ MCD_OPC_Decode, 239, 7, 103, // Opcode: VADDHNv8i8 +/* 590 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 627 +/* 596 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 599 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 613 +/* 604 */ MCD_OPC_CheckPredicate, 21, 24, 70, 0, // Skip to: 18553 +/* 609 */ MCD_OPC_Decode, 151, 18, 101, // Opcode: VSHLuv8i8 +/* 613 */ MCD_OPC_FilterValue, 1, 15, 70, 0, // Skip to: 18553 +/* 618 */ MCD_OPC_CheckPredicate, 21, 10, 70, 0, // Skip to: 18553 +/* 623 */ MCD_OPC_Decode, 144, 18, 102, // Opcode: VSHLuv16i8 +/* 627 */ MCD_OPC_FilterValue, 231, 3, 0, 70, 0, // Skip to: 18553 +/* 633 */ MCD_OPC_CheckPredicate, 21, 251, 69, 0, // Skip to: 18553 +/* 638 */ MCD_OPC_CheckField, 6, 1, 0, 244, 69, 0, // Skip to: 18553 +/* 645 */ MCD_OPC_Decode, 212, 16, 103, // Opcode: VRADDHNv8i8 +/* 649 */ MCD_OPC_FilterValue, 5, 121, 0, 0, // Skip to: 775 +/* 654 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 657 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 694 +/* 663 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 666 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 680 +/* 671 */ MCD_OPC_CheckPredicate, 21, 213, 69, 0, // Skip to: 18553 +/* 676 */ MCD_OPC_Decode, 171, 17, 101, // Opcode: VRSHLsv8i8 +/* 680 */ MCD_OPC_FilterValue, 1, 204, 69, 0, // Skip to: 18553 +/* 685 */ MCD_OPC_CheckPredicate, 21, 199, 69, 0, // Skip to: 18553 +/* 690 */ MCD_OPC_Decode, 164, 17, 102, // Opcode: VRSHLsv16i8 +/* 694 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 716 +/* 700 */ MCD_OPC_CheckPredicate, 21, 184, 69, 0, // Skip to: 18553 +/* 705 */ MCD_OPC_CheckField, 6, 1, 0, 177, 69, 0, // Skip to: 18553 +/* 712 */ MCD_OPC_Decode, 176, 7, 104, // Opcode: VABALsv8i16 +/* 716 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 753 +/* 722 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 725 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 739 +/* 730 */ MCD_OPC_CheckPredicate, 21, 154, 69, 0, // Skip to: 18553 +/* 735 */ MCD_OPC_Decode, 179, 17, 101, // Opcode: VRSHLuv8i8 +/* 739 */ MCD_OPC_FilterValue, 1, 145, 69, 0, // Skip to: 18553 +/* 744 */ MCD_OPC_CheckPredicate, 21, 140, 69, 0, // Skip to: 18553 +/* 749 */ MCD_OPC_Decode, 172, 17, 102, // Opcode: VRSHLuv16i8 +/* 753 */ MCD_OPC_FilterValue, 231, 3, 130, 69, 0, // Skip to: 18553 +/* 759 */ MCD_OPC_CheckPredicate, 21, 125, 69, 0, // Skip to: 18553 +/* 764 */ MCD_OPC_CheckField, 6, 1, 0, 118, 69, 0, // Skip to: 18553 +/* 771 */ MCD_OPC_Decode, 179, 7, 104, // Opcode: VABALuv8i16 +/* 775 */ MCD_OPC_FilterValue, 6, 121, 0, 0, // Skip to: 901 +/* 780 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 783 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 820 +/* 789 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 792 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 806 +/* 797 */ MCD_OPC_CheckPredicate, 21, 87, 69, 0, // Skip to: 18553 +/* 802 */ MCD_OPC_Decode, 172, 13, 97, // Opcode: VMAXsv8i8 +/* 806 */ MCD_OPC_FilterValue, 1, 78, 69, 0, // Skip to: 18553 +/* 811 */ MCD_OPC_CheckPredicate, 21, 73, 69, 0, // Skip to: 18553 +/* 816 */ MCD_OPC_Decode, 167, 13, 98, // Opcode: VMAXsv16i8 +/* 820 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 842 +/* 826 */ MCD_OPC_CheckPredicate, 21, 58, 69, 0, // Skip to: 18553 +/* 831 */ MCD_OPC_CheckField, 6, 1, 0, 51, 69, 0, // Skip to: 18553 +/* 838 */ MCD_OPC_Decode, 211, 20, 103, // Opcode: VSUBHNv8i8 +/* 842 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 879 +/* 848 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 851 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 865 +/* 856 */ MCD_OPC_CheckPredicate, 21, 28, 69, 0, // Skip to: 18553 +/* 861 */ MCD_OPC_Decode, 178, 13, 97, // Opcode: VMAXuv8i8 +/* 865 */ MCD_OPC_FilterValue, 1, 19, 69, 0, // Skip to: 18553 +/* 870 */ MCD_OPC_CheckPredicate, 21, 14, 69, 0, // Skip to: 18553 +/* 875 */ MCD_OPC_Decode, 173, 13, 98, // Opcode: VMAXuv16i8 +/* 879 */ MCD_OPC_FilterValue, 231, 3, 4, 69, 0, // Skip to: 18553 +/* 885 */ MCD_OPC_CheckPredicate, 21, 255, 68, 0, // Skip to: 18553 +/* 890 */ MCD_OPC_CheckField, 6, 1, 0, 248, 68, 0, // Skip to: 18553 +/* 897 */ MCD_OPC_Decode, 227, 17, 103, // Opcode: VRSUBHNv8i8 +/* 901 */ MCD_OPC_FilterValue, 7, 121, 0, 0, // Skip to: 1027 +/* 906 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 909 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 946 +/* 915 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 918 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 932 +/* 923 */ MCD_OPC_CheckPredicate, 21, 217, 68, 0, // Skip to: 18553 +/* 928 */ MCD_OPC_Decode, 207, 7, 97, // Opcode: VABDsv8i8 +/* 932 */ MCD_OPC_FilterValue, 1, 208, 68, 0, // Skip to: 18553 +/* 937 */ MCD_OPC_CheckPredicate, 21, 203, 68, 0, // Skip to: 18553 +/* 942 */ MCD_OPC_Decode, 202, 7, 98, // Opcode: VABDsv16i8 +/* 946 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 968 +/* 952 */ MCD_OPC_CheckPredicate, 21, 188, 68, 0, // Skip to: 18553 +/* 957 */ MCD_OPC_CheckField, 6, 1, 0, 181, 68, 0, // Skip to: 18553 +/* 964 */ MCD_OPC_Decode, 194, 7, 99, // Opcode: VABDLsv8i16 +/* 968 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1005 +/* 974 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 977 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 991 +/* 982 */ MCD_OPC_CheckPredicate, 21, 158, 68, 0, // Skip to: 18553 +/* 987 */ MCD_OPC_Decode, 213, 7, 97, // Opcode: VABDuv8i8 +/* 991 */ MCD_OPC_FilterValue, 1, 149, 68, 0, // Skip to: 18553 +/* 996 */ MCD_OPC_CheckPredicate, 21, 144, 68, 0, // Skip to: 18553 +/* 1001 */ MCD_OPC_Decode, 208, 7, 98, // Opcode: VABDuv16i8 +/* 1005 */ MCD_OPC_FilterValue, 231, 3, 134, 68, 0, // Skip to: 18553 +/* 1011 */ MCD_OPC_CheckPredicate, 21, 129, 68, 0, // Skip to: 18553 +/* 1016 */ MCD_OPC_CheckField, 6, 1, 0, 122, 68, 0, // Skip to: 18553 +/* 1023 */ MCD_OPC_Decode, 197, 7, 99, // Opcode: VABDLuv8i16 +/* 1027 */ MCD_OPC_FilterValue, 8, 121, 0, 0, // Skip to: 1153 +/* 1032 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1035 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1072 +/* 1041 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1044 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1058 +/* 1049 */ MCD_OPC_CheckPredicate, 21, 91, 68, 0, // Skip to: 18553 +/* 1054 */ MCD_OPC_Decode, 136, 8, 97, // Opcode: VADDv8i8 +/* 1058 */ MCD_OPC_FilterValue, 1, 82, 68, 0, // Skip to: 18553 +/* 1063 */ MCD_OPC_CheckPredicate, 21, 77, 68, 0, // Skip to: 18553 +/* 1068 */ MCD_OPC_Decode, 129, 8, 98, // Opcode: VADDv16i8 +/* 1072 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1094 +/* 1078 */ MCD_OPC_CheckPredicate, 21, 62, 68, 0, // Skip to: 18553 +/* 1083 */ MCD_OPC_CheckField, 6, 1, 0, 55, 68, 0, // Skip to: 18553 +/* 1090 */ MCD_OPC_Decode, 210, 13, 104, // Opcode: VMLALsv8i16 +/* 1094 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1131 +/* 1100 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1103 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1117 +/* 1108 */ MCD_OPC_CheckPredicate, 21, 32, 68, 0, // Skip to: 18553 +/* 1113 */ MCD_OPC_Decode, 236, 20, 97, // Opcode: VSUBv8i8 +/* 1117 */ MCD_OPC_FilterValue, 1, 23, 68, 0, // Skip to: 18553 +/* 1122 */ MCD_OPC_CheckPredicate, 21, 18, 68, 0, // Skip to: 18553 +/* 1127 */ MCD_OPC_Decode, 229, 20, 98, // Opcode: VSUBv16i8 +/* 1131 */ MCD_OPC_FilterValue, 231, 3, 8, 68, 0, // Skip to: 18553 +/* 1137 */ MCD_OPC_CheckPredicate, 21, 3, 68, 0, // Skip to: 18553 +/* 1142 */ MCD_OPC_CheckField, 6, 1, 0, 252, 67, 0, // Skip to: 18553 +/* 1149 */ MCD_OPC_Decode, 213, 13, 104, // Opcode: VMLALuv8i16 +/* 1153 */ MCD_OPC_FilterValue, 9, 79, 0, 0, // Skip to: 1237 +/* 1158 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1161 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1199 +/* 1166 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1169 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1184 +/* 1175 */ MCD_OPC_CheckPredicate, 21, 221, 67, 0, // Skip to: 18553 +/* 1180 */ MCD_OPC_Decode, 232, 13, 105, // Opcode: VMLAv8i8 +/* 1184 */ MCD_OPC_FilterValue, 230, 3, 211, 67, 0, // Skip to: 18553 +/* 1190 */ MCD_OPC_CheckPredicate, 21, 206, 67, 0, // Skip to: 18553 +/* 1195 */ MCD_OPC_Decode, 135, 14, 105, // Opcode: VMLSv8i8 +/* 1199 */ MCD_OPC_FilterValue, 1, 197, 67, 0, // Skip to: 18553 +/* 1204 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1207 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1222 +/* 1213 */ MCD_OPC_CheckPredicate, 21, 183, 67, 0, // Skip to: 18553 +/* 1218 */ MCD_OPC_Decode, 227, 13, 106, // Opcode: VMLAv16i8 +/* 1222 */ MCD_OPC_FilterValue, 230, 3, 173, 67, 0, // Skip to: 18553 +/* 1228 */ MCD_OPC_CheckPredicate, 21, 168, 67, 0, // Skip to: 18553 +/* 1233 */ MCD_OPC_Decode, 130, 14, 106, // Opcode: VMLSv16i8 +/* 1237 */ MCD_OPC_FilterValue, 10, 91, 0, 0, // Skip to: 1333 +/* 1242 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1245 */ MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 1267 +/* 1251 */ MCD_OPC_CheckPredicate, 21, 145, 67, 0, // Skip to: 18553 +/* 1256 */ MCD_OPC_CheckField, 6, 1, 0, 138, 67, 0, // Skip to: 18553 +/* 1263 */ MCD_OPC_Decode, 155, 15, 97, // Opcode: VPMAXs8 +/* 1267 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1289 +/* 1273 */ MCD_OPC_CheckPredicate, 21, 123, 67, 0, // Skip to: 18553 +/* 1278 */ MCD_OPC_CheckField, 6, 1, 0, 116, 67, 0, // Skip to: 18553 +/* 1285 */ MCD_OPC_Decode, 241, 13, 104, // Opcode: VMLSLsv8i16 +/* 1289 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 1311 +/* 1295 */ MCD_OPC_CheckPredicate, 21, 101, 67, 0, // Skip to: 18553 +/* 1300 */ MCD_OPC_CheckField, 6, 1, 0, 94, 67, 0, // Skip to: 18553 +/* 1307 */ MCD_OPC_Decode, 158, 15, 97, // Opcode: VPMAXu8 +/* 1311 */ MCD_OPC_FilterValue, 231, 3, 84, 67, 0, // Skip to: 18553 +/* 1317 */ MCD_OPC_CheckPredicate, 21, 79, 67, 0, // Skip to: 18553 +/* 1322 */ MCD_OPC_CheckField, 6, 1, 0, 72, 67, 0, // Skip to: 18553 +/* 1329 */ MCD_OPC_Decode, 244, 13, 104, // Opcode: VMLSLuv8i16 +/* 1333 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 1385 +/* 1338 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1341 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1363 +/* 1347 */ MCD_OPC_CheckPredicate, 21, 49, 67, 0, // Skip to: 18553 +/* 1352 */ MCD_OPC_CheckField, 6, 1, 0, 42, 67, 0, // Skip to: 18553 +/* 1359 */ MCD_OPC_Decode, 189, 14, 99, // Opcode: VMULLsv8i16 +/* 1363 */ MCD_OPC_FilterValue, 231, 3, 32, 67, 0, // Skip to: 18553 +/* 1369 */ MCD_OPC_CheckPredicate, 21, 27, 67, 0, // Skip to: 18553 +/* 1374 */ MCD_OPC_CheckField, 6, 1, 0, 20, 67, 0, // Skip to: 18553 +/* 1381 */ MCD_OPC_Decode, 192, 14, 99, // Opcode: VMULLuv8i16 +/* 1385 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1453 +/* 1390 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1393 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1431 +/* 1398 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1401 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1416 +/* 1407 */ MCD_OPC_CheckPredicate, 21, 245, 66, 0, // Skip to: 18553 +/* 1412 */ MCD_OPC_Decode, 253, 7, 97, // Opcode: VADDfd +/* 1416 */ MCD_OPC_FilterValue, 230, 3, 235, 66, 0, // Skip to: 18553 +/* 1422 */ MCD_OPC_CheckPredicate, 21, 230, 66, 0, // Skip to: 18553 +/* 1427 */ MCD_OPC_Decode, 146, 15, 97, // Opcode: VPADDf +/* 1431 */ MCD_OPC_FilterValue, 1, 221, 66, 0, // Skip to: 18553 +/* 1436 */ MCD_OPC_CheckPredicate, 21, 216, 66, 0, // Skip to: 18553 +/* 1441 */ MCD_OPC_CheckField, 23, 9, 228, 3, 208, 66, 0, // Skip to: 18553 +/* 1449 */ MCD_OPC_Decode, 254, 7, 98, // Opcode: VADDfq +/* 1453 */ MCD_OPC_FilterValue, 14, 99, 0, 0, // Skip to: 1557 +/* 1458 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1461 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1498 +/* 1467 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1470 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1484 +/* 1475 */ MCD_OPC_CheckPredicate, 21, 177, 66, 0, // Skip to: 18553 +/* 1480 */ MCD_OPC_Decode, 155, 8, 97, // Opcode: VCEQfd +/* 1484 */ MCD_OPC_FilterValue, 1, 168, 66, 0, // Skip to: 18553 +/* 1489 */ MCD_OPC_CheckPredicate, 21, 163, 66, 0, // Skip to: 18553 +/* 1494 */ MCD_OPC_Decode, 156, 8, 98, // Opcode: VCEQfq +/* 1498 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1520 +/* 1504 */ MCD_OPC_CheckPredicate, 21, 148, 66, 0, // Skip to: 18553 +/* 1509 */ MCD_OPC_CheckField, 6, 1, 0, 141, 66, 0, // Skip to: 18553 +/* 1516 */ MCD_OPC_Decode, 182, 14, 99, // Opcode: VMULLp8 +/* 1520 */ MCD_OPC_FilterValue, 230, 3, 131, 66, 0, // Skip to: 18553 +/* 1526 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1529 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1543 +/* 1534 */ MCD_OPC_CheckPredicate, 21, 118, 66, 0, // Skip to: 18553 +/* 1539 */ MCD_OPC_Decode, 175, 8, 97, // Opcode: VCGEfd +/* 1543 */ MCD_OPC_FilterValue, 1, 109, 66, 0, // Skip to: 18553 +/* 1548 */ MCD_OPC_CheckPredicate, 21, 104, 66, 0, // Skip to: 18553 +/* 1553 */ MCD_OPC_Decode, 176, 8, 98, // Opcode: VCGEfq +/* 1557 */ MCD_OPC_FilterValue, 15, 95, 66, 0, // Skip to: 18553 +/* 1562 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1565 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1603 +/* 1570 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1573 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1588 +/* 1579 */ MCD_OPC_CheckPredicate, 21, 73, 66, 0, // Skip to: 18553 +/* 1584 */ MCD_OPC_Decode, 163, 13, 97, // Opcode: VMAXfd +/* 1588 */ MCD_OPC_FilterValue, 230, 3, 63, 66, 0, // Skip to: 18553 +/* 1594 */ MCD_OPC_CheckPredicate, 21, 58, 66, 0, // Skip to: 18553 +/* 1599 */ MCD_OPC_Decode, 151, 15, 97, // Opcode: VPMAXf +/* 1603 */ MCD_OPC_FilterValue, 1, 49, 66, 0, // Skip to: 18553 +/* 1608 */ MCD_OPC_CheckPredicate, 21, 44, 66, 0, // Skip to: 18553 +/* 1613 */ MCD_OPC_CheckField, 23, 9, 228, 3, 36, 66, 0, // Skip to: 18553 +/* 1621 */ MCD_OPC_Decode, 164, 13, 98, // Opcode: VMAXfq +/* 1625 */ MCD_OPC_FilterValue, 1, 162, 8, 0, // Skip to: 3840 +/* 1630 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1633 */ MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 1789 +/* 1638 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1641 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1678 +/* 1647 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1650 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1664 +/* 1655 */ MCD_OPC_CheckPredicate, 21, 253, 65, 0, // Skip to: 18553 +/* 1660 */ MCD_OPC_Decode, 176, 10, 97, // Opcode: VHADDsv4i16 +/* 1664 */ MCD_OPC_FilterValue, 1, 244, 65, 0, // Skip to: 18553 +/* 1669 */ MCD_OPC_CheckPredicate, 21, 239, 65, 0, // Skip to: 18553 +/* 1674 */ MCD_OPC_Decode, 178, 10, 98, // Opcode: VHADDsv8i16 +/* 1678 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 1715 +/* 1684 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1687 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1701 +/* 1692 */ MCD_OPC_CheckPredicate, 21, 216, 65, 0, // Skip to: 18553 +/* 1697 */ MCD_OPC_Decode, 241, 7, 99, // Opcode: VADDLsv4i32 +/* 1701 */ MCD_OPC_FilterValue, 1, 207, 65, 0, // Skip to: 18553 +/* 1706 */ MCD_OPC_CheckPredicate, 21, 202, 65, 0, // Skip to: 18553 +/* 1711 */ MCD_OPC_Decode, 224, 13, 107, // Opcode: VMLAslv4i16 +/* 1715 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1752 +/* 1721 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1724 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1738 +/* 1729 */ MCD_OPC_CheckPredicate, 21, 179, 65, 0, // Skip to: 18553 +/* 1734 */ MCD_OPC_Decode, 182, 10, 97, // Opcode: VHADDuv4i16 +/* 1738 */ MCD_OPC_FilterValue, 1, 170, 65, 0, // Skip to: 18553 +/* 1743 */ MCD_OPC_CheckPredicate, 21, 165, 65, 0, // Skip to: 18553 +/* 1748 */ MCD_OPC_Decode, 184, 10, 98, // Opcode: VHADDuv8i16 +/* 1752 */ MCD_OPC_FilterValue, 231, 3, 155, 65, 0, // Skip to: 18553 +/* 1758 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1761 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1775 +/* 1766 */ MCD_OPC_CheckPredicate, 21, 142, 65, 0, // Skip to: 18553 +/* 1771 */ MCD_OPC_Decode, 244, 7, 99, // Opcode: VADDLuv4i32 +/* 1775 */ MCD_OPC_FilterValue, 1, 133, 65, 0, // Skip to: 18553 +/* 1780 */ MCD_OPC_CheckPredicate, 21, 128, 65, 0, // Skip to: 18553 +/* 1785 */ MCD_OPC_Decode, 226, 13, 108, // Opcode: VMLAslv8i16 +/* 1789 */ MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 1945 +/* 1794 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1797 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1834 +/* 1803 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1806 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1820 +/* 1811 */ MCD_OPC_CheckPredicate, 21, 97, 65, 0, // Skip to: 18553 +/* 1816 */ MCD_OPC_Decode, 237, 16, 97, // Opcode: VRHADDsv4i16 +/* 1820 */ MCD_OPC_FilterValue, 1, 88, 65, 0, // Skip to: 18553 +/* 1825 */ MCD_OPC_CheckPredicate, 21, 83, 65, 0, // Skip to: 18553 +/* 1830 */ MCD_OPC_Decode, 239, 16, 98, // Opcode: VRHADDsv8i16 +/* 1834 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 1871 +/* 1840 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1843 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1857 +/* 1848 */ MCD_OPC_CheckPredicate, 21, 60, 65, 0, // Skip to: 18553 +/* 1853 */ MCD_OPC_Decode, 248, 7, 100, // Opcode: VADDWsv4i32 +/* 1857 */ MCD_OPC_FilterValue, 1, 51, 65, 0, // Skip to: 18553 +/* 1862 */ MCD_OPC_CheckPredicate, 22, 46, 65, 0, // Skip to: 18553 +/* 1867 */ MCD_OPC_Decode, 221, 13, 107, // Opcode: VMLAslhd +/* 1871 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1908 +/* 1877 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1880 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1894 +/* 1885 */ MCD_OPC_CheckPredicate, 21, 23, 65, 0, // Skip to: 18553 +/* 1890 */ MCD_OPC_Decode, 243, 16, 97, // Opcode: VRHADDuv4i16 +/* 1894 */ MCD_OPC_FilterValue, 1, 14, 65, 0, // Skip to: 18553 +/* 1899 */ MCD_OPC_CheckPredicate, 21, 9, 65, 0, // Skip to: 18553 +/* 1904 */ MCD_OPC_Decode, 245, 16, 98, // Opcode: VRHADDuv8i16 +/* 1908 */ MCD_OPC_FilterValue, 231, 3, 255, 64, 0, // Skip to: 18553 +/* 1914 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1917 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1931 +/* 1922 */ MCD_OPC_CheckPredicate, 21, 242, 64, 0, // Skip to: 18553 +/* 1927 */ MCD_OPC_Decode, 251, 7, 100, // Opcode: VADDWuv4i32 +/* 1931 */ MCD_OPC_FilterValue, 1, 233, 64, 0, // Skip to: 18553 +/* 1936 */ MCD_OPC_CheckPredicate, 22, 228, 64, 0, // Skip to: 18553 +/* 1941 */ MCD_OPC_Decode, 222, 13, 108, // Opcode: VMLAslhq +/* 1945 */ MCD_OPC_FilterValue, 2, 151, 0, 0, // Skip to: 2101 +/* 1950 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1953 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1990 +/* 1959 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1962 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1976 +/* 1967 */ MCD_OPC_CheckPredicate, 21, 197, 64, 0, // Skip to: 18553 +/* 1972 */ MCD_OPC_Decode, 188, 10, 97, // Opcode: VHSUBsv4i16 +/* 1976 */ MCD_OPC_FilterValue, 1, 188, 64, 0, // Skip to: 18553 +/* 1981 */ MCD_OPC_CheckPredicate, 21, 183, 64, 0, // Skip to: 18553 +/* 1986 */ MCD_OPC_Decode, 190, 10, 98, // Opcode: VHSUBsv8i16 +/* 1990 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2027 +/* 1996 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1999 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2013 +/* 2004 */ MCD_OPC_CheckPredicate, 21, 160, 64, 0, // Skip to: 18553 +/* 2009 */ MCD_OPC_Decode, 213, 20, 99, // Opcode: VSUBLsv4i32 +/* 2013 */ MCD_OPC_FilterValue, 1, 151, 64, 0, // Skip to: 18553 +/* 2018 */ MCD_OPC_CheckPredicate, 21, 146, 64, 0, // Skip to: 18553 +/* 2023 */ MCD_OPC_Decode, 205, 13, 109, // Opcode: VMLALslsv4i16 +/* 2027 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2064 +/* 2033 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2036 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2050 +/* 2041 */ MCD_OPC_CheckPredicate, 21, 123, 64, 0, // Skip to: 18553 +/* 2046 */ MCD_OPC_Decode, 194, 10, 97, // Opcode: VHSUBuv4i16 +/* 2050 */ MCD_OPC_FilterValue, 1, 114, 64, 0, // Skip to: 18553 +/* 2055 */ MCD_OPC_CheckPredicate, 21, 109, 64, 0, // Skip to: 18553 +/* 2060 */ MCD_OPC_Decode, 196, 10, 98, // Opcode: VHSUBuv8i16 +/* 2064 */ MCD_OPC_FilterValue, 231, 3, 99, 64, 0, // Skip to: 18553 +/* 2070 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2073 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2087 +/* 2078 */ MCD_OPC_CheckPredicate, 21, 86, 64, 0, // Skip to: 18553 +/* 2083 */ MCD_OPC_Decode, 216, 20, 99, // Opcode: VSUBLuv4i32 +/* 2087 */ MCD_OPC_FilterValue, 1, 77, 64, 0, // Skip to: 18553 +/* 2092 */ MCD_OPC_CheckPredicate, 21, 72, 64, 0, // Skip to: 18553 +/* 2097 */ MCD_OPC_Decode, 207, 13, 109, // Opcode: VMLALsluv4i16 +/* 2101 */ MCD_OPC_FilterValue, 3, 136, 0, 0, // Skip to: 2242 +/* 2106 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2109 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2146 +/* 2115 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2118 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2132 +/* 2123 */ MCD_OPC_CheckPredicate, 21, 41, 64, 0, // Skip to: 18553 +/* 2128 */ MCD_OPC_Decode, 207, 8, 97, // Opcode: VCGTsv4i16 +/* 2132 */ MCD_OPC_FilterValue, 1, 32, 64, 0, // Skip to: 18553 +/* 2137 */ MCD_OPC_CheckPredicate, 21, 27, 64, 0, // Skip to: 18553 +/* 2142 */ MCD_OPC_Decode, 209, 8, 98, // Opcode: VCGTsv8i16 +/* 2146 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2183 +/* 2152 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2155 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2169 +/* 2160 */ MCD_OPC_CheckPredicate, 21, 4, 64, 0, // Skip to: 18553 +/* 2165 */ MCD_OPC_Decode, 220, 20, 100, // Opcode: VSUBWsv4i32 +/* 2169 */ MCD_OPC_FilterValue, 1, 251, 63, 0, // Skip to: 18553 +/* 2174 */ MCD_OPC_CheckPredicate, 21, 246, 63, 0, // Skip to: 18553 +/* 2179 */ MCD_OPC_Decode, 190, 15, 109, // Opcode: VQDMLALslv4i16 +/* 2183 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2220 +/* 2189 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2192 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2206 +/* 2197 */ MCD_OPC_CheckPredicate, 21, 223, 63, 0, // Skip to: 18553 +/* 2202 */ MCD_OPC_Decode, 213, 8, 97, // Opcode: VCGTuv4i16 +/* 2206 */ MCD_OPC_FilterValue, 1, 214, 63, 0, // Skip to: 18553 +/* 2211 */ MCD_OPC_CheckPredicate, 21, 209, 63, 0, // Skip to: 18553 +/* 2216 */ MCD_OPC_Decode, 215, 8, 98, // Opcode: VCGTuv8i16 +/* 2220 */ MCD_OPC_FilterValue, 231, 3, 199, 63, 0, // Skip to: 18553 +/* 2226 */ MCD_OPC_CheckPredicate, 21, 194, 63, 0, // Skip to: 18553 +/* 2231 */ MCD_OPC_CheckField, 6, 1, 0, 187, 63, 0, // Skip to: 18553 +/* 2238 */ MCD_OPC_Decode, 223, 20, 100, // Opcode: VSUBWuv4i32 +/* 2242 */ MCD_OPC_FilterValue, 4, 151, 0, 0, // Skip to: 2398 +/* 2247 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2250 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2287 +/* 2256 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2259 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2273 +/* 2264 */ MCD_OPC_CheckPredicate, 21, 156, 63, 0, // Skip to: 18553 +/* 2269 */ MCD_OPC_Decode, 140, 18, 101, // Opcode: VSHLsv4i16 +/* 2273 */ MCD_OPC_FilterValue, 1, 147, 63, 0, // Skip to: 18553 +/* 2278 */ MCD_OPC_CheckPredicate, 21, 142, 63, 0, // Skip to: 18553 +/* 2283 */ MCD_OPC_Decode, 142, 18, 102, // Opcode: VSHLsv8i16 +/* 2287 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2324 +/* 2293 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2296 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2310 +/* 2301 */ MCD_OPC_CheckPredicate, 21, 119, 63, 0, // Skip to: 18553 +/* 2306 */ MCD_OPC_Decode, 238, 7, 103, // Opcode: VADDHNv4i16 +/* 2310 */ MCD_OPC_FilterValue, 1, 110, 63, 0, // Skip to: 18553 +/* 2315 */ MCD_OPC_CheckPredicate, 21, 105, 63, 0, // Skip to: 18553 +/* 2320 */ MCD_OPC_Decode, 255, 13, 107, // Opcode: VMLSslv4i16 +/* 2324 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2361 +/* 2330 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2333 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2347 +/* 2338 */ MCD_OPC_CheckPredicate, 21, 82, 63, 0, // Skip to: 18553 +/* 2343 */ MCD_OPC_Decode, 148, 18, 101, // Opcode: VSHLuv4i16 +/* 2347 */ MCD_OPC_FilterValue, 1, 73, 63, 0, // Skip to: 18553 +/* 2352 */ MCD_OPC_CheckPredicate, 21, 68, 63, 0, // Skip to: 18553 +/* 2357 */ MCD_OPC_Decode, 150, 18, 102, // Opcode: VSHLuv8i16 +/* 2361 */ MCD_OPC_FilterValue, 231, 3, 58, 63, 0, // Skip to: 18553 +/* 2367 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2370 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2384 +/* 2375 */ MCD_OPC_CheckPredicate, 21, 45, 63, 0, // Skip to: 18553 +/* 2380 */ MCD_OPC_Decode, 211, 16, 103, // Opcode: VRADDHNv4i16 +/* 2384 */ MCD_OPC_FilterValue, 1, 36, 63, 0, // Skip to: 18553 +/* 2389 */ MCD_OPC_CheckPredicate, 21, 31, 63, 0, // Skip to: 18553 +/* 2394 */ MCD_OPC_Decode, 129, 14, 108, // Opcode: VMLSslv8i16 +/* 2398 */ MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 2554 +/* 2403 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2406 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2443 +/* 2412 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2415 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2429 +/* 2420 */ MCD_OPC_CheckPredicate, 21, 0, 63, 0, // Skip to: 18553 +/* 2425 */ MCD_OPC_Decode, 168, 17, 101, // Opcode: VRSHLsv4i16 +/* 2429 */ MCD_OPC_FilterValue, 1, 247, 62, 0, // Skip to: 18553 +/* 2434 */ MCD_OPC_CheckPredicate, 21, 242, 62, 0, // Skip to: 18553 +/* 2439 */ MCD_OPC_Decode, 170, 17, 102, // Opcode: VRSHLsv8i16 +/* 2443 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2480 +/* 2449 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2452 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2466 +/* 2457 */ MCD_OPC_CheckPredicate, 21, 219, 62, 0, // Skip to: 18553 +/* 2462 */ MCD_OPC_Decode, 175, 7, 104, // Opcode: VABALsv4i32 +/* 2466 */ MCD_OPC_FilterValue, 1, 210, 62, 0, // Skip to: 18553 +/* 2471 */ MCD_OPC_CheckPredicate, 22, 205, 62, 0, // Skip to: 18553 +/* 2476 */ MCD_OPC_Decode, 252, 13, 107, // Opcode: VMLSslhd +/* 2480 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2517 +/* 2486 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2489 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2503 +/* 2494 */ MCD_OPC_CheckPredicate, 21, 182, 62, 0, // Skip to: 18553 +/* 2499 */ MCD_OPC_Decode, 176, 17, 101, // Opcode: VRSHLuv4i16 +/* 2503 */ MCD_OPC_FilterValue, 1, 173, 62, 0, // Skip to: 18553 +/* 2508 */ MCD_OPC_CheckPredicate, 21, 168, 62, 0, // Skip to: 18553 +/* 2513 */ MCD_OPC_Decode, 178, 17, 102, // Opcode: VRSHLuv8i16 +/* 2517 */ MCD_OPC_FilterValue, 231, 3, 158, 62, 0, // Skip to: 18553 +/* 2523 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2526 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2540 +/* 2531 */ MCD_OPC_CheckPredicate, 21, 145, 62, 0, // Skip to: 18553 +/* 2536 */ MCD_OPC_Decode, 178, 7, 104, // Opcode: VABALuv4i32 +/* 2540 */ MCD_OPC_FilterValue, 1, 136, 62, 0, // Skip to: 18553 +/* 2545 */ MCD_OPC_CheckPredicate, 22, 131, 62, 0, // Skip to: 18553 +/* 2550 */ MCD_OPC_Decode, 253, 13, 108, // Opcode: VMLSslhq +/* 2554 */ MCD_OPC_FilterValue, 6, 151, 0, 0, // Skip to: 2710 +/* 2559 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2562 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2599 +/* 2568 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2571 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2585 +/* 2576 */ MCD_OPC_CheckPredicate, 21, 100, 62, 0, // Skip to: 18553 +/* 2581 */ MCD_OPC_Decode, 169, 13, 97, // Opcode: VMAXsv4i16 +/* 2585 */ MCD_OPC_FilterValue, 1, 91, 62, 0, // Skip to: 18553 +/* 2590 */ MCD_OPC_CheckPredicate, 21, 86, 62, 0, // Skip to: 18553 +/* 2595 */ MCD_OPC_Decode, 171, 13, 98, // Opcode: VMAXsv8i16 +/* 2599 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2636 +/* 2605 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2608 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2622 +/* 2613 */ MCD_OPC_CheckPredicate, 21, 63, 62, 0, // Skip to: 18553 +/* 2618 */ MCD_OPC_Decode, 210, 20, 103, // Opcode: VSUBHNv4i16 +/* 2622 */ MCD_OPC_FilterValue, 1, 54, 62, 0, // Skip to: 18553 +/* 2627 */ MCD_OPC_CheckPredicate, 21, 49, 62, 0, // Skip to: 18553 +/* 2632 */ MCD_OPC_Decode, 236, 13, 109, // Opcode: VMLSLslsv4i16 +/* 2636 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2673 +/* 2642 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2645 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2659 +/* 2650 */ MCD_OPC_CheckPredicate, 21, 26, 62, 0, // Skip to: 18553 +/* 2655 */ MCD_OPC_Decode, 175, 13, 97, // Opcode: VMAXuv4i16 +/* 2659 */ MCD_OPC_FilterValue, 1, 17, 62, 0, // Skip to: 18553 +/* 2664 */ MCD_OPC_CheckPredicate, 21, 12, 62, 0, // Skip to: 18553 +/* 2669 */ MCD_OPC_Decode, 177, 13, 98, // Opcode: VMAXuv8i16 +/* 2673 */ MCD_OPC_FilterValue, 231, 3, 2, 62, 0, // Skip to: 18553 +/* 2679 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2682 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2696 +/* 2687 */ MCD_OPC_CheckPredicate, 21, 245, 61, 0, // Skip to: 18553 +/* 2692 */ MCD_OPC_Decode, 226, 17, 103, // Opcode: VRSUBHNv4i16 +/* 2696 */ MCD_OPC_FilterValue, 1, 236, 61, 0, // Skip to: 18553 +/* 2701 */ MCD_OPC_CheckPredicate, 21, 231, 61, 0, // Skip to: 18553 +/* 2706 */ MCD_OPC_Decode, 238, 13, 109, // Opcode: VMLSLsluv4i16 +/* 2710 */ MCD_OPC_FilterValue, 7, 136, 0, 0, // Skip to: 2851 +/* 2715 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2718 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2755 +/* 2724 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2727 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2741 +/* 2732 */ MCD_OPC_CheckPredicate, 21, 200, 61, 0, // Skip to: 18553 +/* 2737 */ MCD_OPC_Decode, 204, 7, 97, // Opcode: VABDsv4i16 +/* 2741 */ MCD_OPC_FilterValue, 1, 191, 61, 0, // Skip to: 18553 +/* 2746 */ MCD_OPC_CheckPredicate, 21, 186, 61, 0, // Skip to: 18553 +/* 2751 */ MCD_OPC_Decode, 206, 7, 98, // Opcode: VABDsv8i16 +/* 2755 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2792 +/* 2761 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2764 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2778 +/* 2769 */ MCD_OPC_CheckPredicate, 21, 163, 61, 0, // Skip to: 18553 +/* 2774 */ MCD_OPC_Decode, 193, 7, 99, // Opcode: VABDLsv4i32 +/* 2778 */ MCD_OPC_FilterValue, 1, 154, 61, 0, // Skip to: 18553 +/* 2783 */ MCD_OPC_CheckPredicate, 21, 149, 61, 0, // Skip to: 18553 +/* 2788 */ MCD_OPC_Decode, 194, 15, 109, // Opcode: VQDMLSLslv4i16 +/* 2792 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2829 +/* 2798 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2801 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2815 +/* 2806 */ MCD_OPC_CheckPredicate, 21, 126, 61, 0, // Skip to: 18553 +/* 2811 */ MCD_OPC_Decode, 210, 7, 97, // Opcode: VABDuv4i16 +/* 2815 */ MCD_OPC_FilterValue, 1, 117, 61, 0, // Skip to: 18553 +/* 2820 */ MCD_OPC_CheckPredicate, 21, 112, 61, 0, // Skip to: 18553 +/* 2825 */ MCD_OPC_Decode, 212, 7, 98, // Opcode: VABDuv8i16 +/* 2829 */ MCD_OPC_FilterValue, 231, 3, 102, 61, 0, // Skip to: 18553 +/* 2835 */ MCD_OPC_CheckPredicate, 21, 97, 61, 0, // Skip to: 18553 +/* 2840 */ MCD_OPC_CheckField, 6, 1, 0, 90, 61, 0, // Skip to: 18553 +/* 2847 */ MCD_OPC_Decode, 196, 7, 99, // Opcode: VABDLuv4i32 +/* 2851 */ MCD_OPC_FilterValue, 8, 151, 0, 0, // Skip to: 3007 +/* 2856 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2859 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2896 +/* 2865 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2868 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2882 +/* 2873 */ MCD_OPC_CheckPredicate, 21, 59, 61, 0, // Skip to: 18553 +/* 2878 */ MCD_OPC_Decode, 133, 8, 97, // Opcode: VADDv4i16 +/* 2882 */ MCD_OPC_FilterValue, 1, 50, 61, 0, // Skip to: 18553 +/* 2887 */ MCD_OPC_CheckPredicate, 21, 45, 61, 0, // Skip to: 18553 +/* 2892 */ MCD_OPC_Decode, 135, 8, 98, // Opcode: VADDv8i16 +/* 2896 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2933 +/* 2902 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2905 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2919 +/* 2910 */ MCD_OPC_CheckPredicate, 21, 22, 61, 0, // Skip to: 18553 +/* 2915 */ MCD_OPC_Decode, 209, 13, 104, // Opcode: VMLALsv4i32 +/* 2919 */ MCD_OPC_FilterValue, 1, 13, 61, 0, // Skip to: 18553 +/* 2924 */ MCD_OPC_CheckPredicate, 21, 8, 61, 0, // Skip to: 18553 +/* 2929 */ MCD_OPC_Decode, 205, 14, 110, // Opcode: VMULslv4i16 +/* 2933 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2970 +/* 2939 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2942 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2956 +/* 2947 */ MCD_OPC_CheckPredicate, 21, 241, 60, 0, // Skip to: 18553 +/* 2952 */ MCD_OPC_Decode, 233, 20, 97, // Opcode: VSUBv4i16 +/* 2956 */ MCD_OPC_FilterValue, 1, 232, 60, 0, // Skip to: 18553 +/* 2961 */ MCD_OPC_CheckPredicate, 21, 227, 60, 0, // Skip to: 18553 +/* 2966 */ MCD_OPC_Decode, 235, 20, 98, // Opcode: VSUBv8i16 +/* 2970 */ MCD_OPC_FilterValue, 231, 3, 217, 60, 0, // Skip to: 18553 +/* 2976 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2979 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2993 +/* 2984 */ MCD_OPC_CheckPredicate, 21, 204, 60, 0, // Skip to: 18553 +/* 2989 */ MCD_OPC_Decode, 212, 13, 104, // Opcode: VMLALuv4i32 +/* 2993 */ MCD_OPC_FilterValue, 1, 195, 60, 0, // Skip to: 18553 +/* 2998 */ MCD_OPC_CheckPredicate, 21, 190, 60, 0, // Skip to: 18553 +/* 3003 */ MCD_OPC_Decode, 207, 14, 111, // Opcode: VMULslv8i16 +/* 3007 */ MCD_OPC_FilterValue, 9, 136, 0, 0, // Skip to: 3148 +/* 3012 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3015 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3052 +/* 3021 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3024 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3038 +/* 3029 */ MCD_OPC_CheckPredicate, 21, 159, 60, 0, // Skip to: 18553 +/* 3034 */ MCD_OPC_Decode, 229, 13, 105, // Opcode: VMLAv4i16 +/* 3038 */ MCD_OPC_FilterValue, 1, 150, 60, 0, // Skip to: 18553 +/* 3043 */ MCD_OPC_CheckPredicate, 21, 145, 60, 0, // Skip to: 18553 +/* 3048 */ MCD_OPC_Decode, 231, 13, 106, // Opcode: VMLAv8i16 +/* 3052 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3089 +/* 3058 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3061 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3075 +/* 3066 */ MCD_OPC_CheckPredicate, 21, 122, 60, 0, // Skip to: 18553 +/* 3071 */ MCD_OPC_Decode, 192, 15, 104, // Opcode: VQDMLALv4i32 +/* 3075 */ MCD_OPC_FilterValue, 1, 113, 60, 0, // Skip to: 18553 +/* 3080 */ MCD_OPC_CheckPredicate, 22, 108, 60, 0, // Skip to: 18553 +/* 3085 */ MCD_OPC_Decode, 202, 14, 110, // Opcode: VMULslhd +/* 3089 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3126 +/* 3095 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3098 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3112 +/* 3103 */ MCD_OPC_CheckPredicate, 21, 85, 60, 0, // Skip to: 18553 +/* 3108 */ MCD_OPC_Decode, 132, 14, 105, // Opcode: VMLSv4i16 +/* 3112 */ MCD_OPC_FilterValue, 1, 76, 60, 0, // Skip to: 18553 +/* 3117 */ MCD_OPC_CheckPredicate, 21, 71, 60, 0, // Skip to: 18553 +/* 3122 */ MCD_OPC_Decode, 134, 14, 106, // Opcode: VMLSv8i16 +/* 3126 */ MCD_OPC_FilterValue, 231, 3, 61, 60, 0, // Skip to: 18553 +/* 3132 */ MCD_OPC_CheckPredicate, 22, 56, 60, 0, // Skip to: 18553 +/* 3137 */ MCD_OPC_CheckField, 6, 1, 1, 49, 60, 0, // Skip to: 18553 +/* 3144 */ MCD_OPC_Decode, 203, 14, 111, // Opcode: VMULslhq +/* 3148 */ MCD_OPC_FilterValue, 10, 121, 0, 0, // Skip to: 3274 +/* 3153 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3156 */ MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 3178 +/* 3162 */ MCD_OPC_CheckPredicate, 21, 26, 60, 0, // Skip to: 18553 +/* 3167 */ MCD_OPC_CheckField, 6, 1, 0, 19, 60, 0, // Skip to: 18553 +/* 3174 */ MCD_OPC_Decode, 153, 15, 97, // Opcode: VPMAXs16 +/* 3178 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3215 +/* 3184 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3187 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3201 +/* 3192 */ MCD_OPC_CheckPredicate, 21, 252, 59, 0, // Skip to: 18553 +/* 3197 */ MCD_OPC_Decode, 240, 13, 104, // Opcode: VMLSLsv4i32 +/* 3201 */ MCD_OPC_FilterValue, 1, 243, 59, 0, // Skip to: 18553 +/* 3206 */ MCD_OPC_CheckPredicate, 21, 238, 59, 0, // Skip to: 18553 +/* 3211 */ MCD_OPC_Decode, 184, 14, 112, // Opcode: VMULLslsv4i16 +/* 3215 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3237 +/* 3221 */ MCD_OPC_CheckPredicate, 21, 223, 59, 0, // Skip to: 18553 +/* 3226 */ MCD_OPC_CheckField, 6, 1, 0, 216, 59, 0, // Skip to: 18553 +/* 3233 */ MCD_OPC_Decode, 156, 15, 97, // Opcode: VPMAXu16 +/* 3237 */ MCD_OPC_FilterValue, 231, 3, 206, 59, 0, // Skip to: 18553 +/* 3243 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3246 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3260 +/* 3251 */ MCD_OPC_CheckPredicate, 21, 193, 59, 0, // Skip to: 18553 +/* 3256 */ MCD_OPC_Decode, 243, 13, 104, // Opcode: VMLSLuv4i32 +/* 3260 */ MCD_OPC_FilterValue, 1, 184, 59, 0, // Skip to: 18553 +/* 3265 */ MCD_OPC_CheckPredicate, 21, 179, 59, 0, // Skip to: 18553 +/* 3270 */ MCD_OPC_Decode, 186, 14, 112, // Opcode: VMULLsluv4i16 +/* 3274 */ MCD_OPC_FilterValue, 11, 114, 0, 0, // Skip to: 3393 +/* 3279 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3282 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3319 +/* 3288 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3291 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3305 +/* 3296 */ MCD_OPC_CheckPredicate, 21, 148, 59, 0, // Skip to: 18553 +/* 3301 */ MCD_OPC_Decode, 202, 15, 97, // Opcode: VQDMULHv4i16 +/* 3305 */ MCD_OPC_FilterValue, 1, 139, 59, 0, // Skip to: 18553 +/* 3310 */ MCD_OPC_CheckPredicate, 21, 134, 59, 0, // Skip to: 18553 +/* 3315 */ MCD_OPC_Decode, 204, 15, 98, // Opcode: VQDMULHv8i16 +/* 3319 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3356 +/* 3325 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3328 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3342 +/* 3333 */ MCD_OPC_CheckPredicate, 21, 111, 59, 0, // Skip to: 18553 +/* 3338 */ MCD_OPC_Decode, 196, 15, 104, // Opcode: VQDMLSLv4i32 +/* 3342 */ MCD_OPC_FilterValue, 1, 102, 59, 0, // Skip to: 18553 +/* 3347 */ MCD_OPC_CheckPredicate, 21, 97, 59, 0, // Skip to: 18553 +/* 3352 */ MCD_OPC_Decode, 206, 15, 112, // Opcode: VQDMULLslv4i16 +/* 3356 */ MCD_OPC_FilterValue, 230, 3, 87, 59, 0, // Skip to: 18553 +/* 3362 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3365 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3379 +/* 3370 */ MCD_OPC_CheckPredicate, 21, 74, 59, 0, // Skip to: 18553 +/* 3375 */ MCD_OPC_Decode, 245, 15, 97, // Opcode: VQRDMULHv4i16 +/* 3379 */ MCD_OPC_FilterValue, 1, 65, 59, 0, // Skip to: 18553 +/* 3384 */ MCD_OPC_CheckPredicate, 21, 60, 59, 0, // Skip to: 18553 +/* 3389 */ MCD_OPC_Decode, 247, 15, 98, // Opcode: VQRDMULHv8i16 +/* 3393 */ MCD_OPC_FilterValue, 12, 79, 0, 0, // Skip to: 3477 +/* 3398 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3401 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 3439 +/* 3406 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3409 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 3424 +/* 3415 */ MCD_OPC_CheckPredicate, 21, 29, 59, 0, // Skip to: 18553 +/* 3420 */ MCD_OPC_Decode, 188, 14, 99, // Opcode: VMULLsv4i32 +/* 3424 */ MCD_OPC_FilterValue, 231, 3, 19, 59, 0, // Skip to: 18553 +/* 3430 */ MCD_OPC_CheckPredicate, 21, 14, 59, 0, // Skip to: 18553 +/* 3435 */ MCD_OPC_Decode, 191, 14, 99, // Opcode: VMULLuv4i32 +/* 3439 */ MCD_OPC_FilterValue, 1, 5, 59, 0, // Skip to: 18553 +/* 3444 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3447 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 3462 +/* 3453 */ MCD_OPC_CheckPredicate, 21, 247, 58, 0, // Skip to: 18553 +/* 3458 */ MCD_OPC_Decode, 198, 15, 110, // Opcode: VQDMULHslv4i16 +/* 3462 */ MCD_OPC_FilterValue, 231, 3, 237, 58, 0, // Skip to: 18553 +/* 3468 */ MCD_OPC_CheckPredicate, 21, 232, 58, 0, // Skip to: 18553 +/* 3473 */ MCD_OPC_Decode, 200, 15, 111, // Opcode: VQDMULHslv8i16 +/* 3477 */ MCD_OPC_FilterValue, 13, 121, 0, 0, // Skip to: 3603 +/* 3482 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3485 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3522 +/* 3491 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3494 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3508 +/* 3499 */ MCD_OPC_CheckPredicate, 22, 201, 58, 0, // Skip to: 18553 +/* 3504 */ MCD_OPC_Decode, 255, 7, 97, // Opcode: VADDhd +/* 3508 */ MCD_OPC_FilterValue, 1, 192, 58, 0, // Skip to: 18553 +/* 3513 */ MCD_OPC_CheckPredicate, 22, 187, 58, 0, // Skip to: 18553 +/* 3518 */ MCD_OPC_Decode, 128, 8, 98, // Opcode: VADDhq +/* 3522 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3559 +/* 3528 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3531 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3545 +/* 3536 */ MCD_OPC_CheckPredicate, 21, 164, 58, 0, // Skip to: 18553 +/* 3541 */ MCD_OPC_Decode, 208, 15, 99, // Opcode: VQDMULLv4i32 +/* 3545 */ MCD_OPC_FilterValue, 1, 155, 58, 0, // Skip to: 18553 +/* 3550 */ MCD_OPC_CheckPredicate, 21, 150, 58, 0, // Skip to: 18553 +/* 3555 */ MCD_OPC_Decode, 241, 15, 110, // Opcode: VQRDMULHslv4i16 +/* 3559 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3581 +/* 3565 */ MCD_OPC_CheckPredicate, 22, 135, 58, 0, // Skip to: 18553 +/* 3570 */ MCD_OPC_CheckField, 6, 1, 0, 128, 58, 0, // Skip to: 18553 +/* 3577 */ MCD_OPC_Decode, 147, 15, 97, // Opcode: VPADDh +/* 3581 */ MCD_OPC_FilterValue, 231, 3, 118, 58, 0, // Skip to: 18553 +/* 3587 */ MCD_OPC_CheckPredicate, 21, 113, 58, 0, // Skip to: 18553 +/* 3592 */ MCD_OPC_CheckField, 6, 1, 1, 106, 58, 0, // Skip to: 18553 +/* 3599 */ MCD_OPC_Decode, 243, 15, 111, // Opcode: VQRDMULHslv8i16 +/* 3603 */ MCD_OPC_FilterValue, 14, 121, 0, 0, // Skip to: 3729 +/* 3608 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3611 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3648 +/* 3617 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3620 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3634 +/* 3625 */ MCD_OPC_CheckPredicate, 22, 75, 58, 0, // Skip to: 18553 +/* 3630 */ MCD_OPC_Decode, 157, 8, 97, // Opcode: VCEQhd +/* 3634 */ MCD_OPC_FilterValue, 1, 66, 58, 0, // Skip to: 18553 +/* 3639 */ MCD_OPC_CheckPredicate, 22, 61, 58, 0, // Skip to: 18553 +/* 3644 */ MCD_OPC_Decode, 158, 8, 98, // Opcode: VCEQhq +/* 3648 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 3670 +/* 3654 */ MCD_OPC_CheckPredicate, 23, 46, 58, 0, // Skip to: 18553 +/* 3659 */ MCD_OPC_CheckField, 6, 1, 1, 39, 58, 0, // Skip to: 18553 +/* 3666 */ MCD_OPC_Decode, 225, 15, 107, // Opcode: VQRDMLAHslv4i16 +/* 3670 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3707 +/* 3676 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3679 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3693 +/* 3684 */ MCD_OPC_CheckPredicate, 22, 16, 58, 0, // Skip to: 18553 +/* 3689 */ MCD_OPC_Decode, 177, 8, 97, // Opcode: VCGEhd +/* 3693 */ MCD_OPC_FilterValue, 1, 7, 58, 0, // Skip to: 18553 +/* 3698 */ MCD_OPC_CheckPredicate, 22, 2, 58, 0, // Skip to: 18553 +/* 3703 */ MCD_OPC_Decode, 178, 8, 98, // Opcode: VCGEhq +/* 3707 */ MCD_OPC_FilterValue, 231, 3, 248, 57, 0, // Skip to: 18553 +/* 3713 */ MCD_OPC_CheckPredicate, 23, 243, 57, 0, // Skip to: 18553 +/* 3718 */ MCD_OPC_CheckField, 6, 1, 1, 236, 57, 0, // Skip to: 18553 +/* 3725 */ MCD_OPC_Decode, 227, 15, 108, // Opcode: VQRDMLAHslv8i16 +/* 3729 */ MCD_OPC_FilterValue, 15, 227, 57, 0, // Skip to: 18553 +/* 3734 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3737 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3774 +/* 3743 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3746 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3760 +/* 3751 */ MCD_OPC_CheckPredicate, 22, 205, 57, 0, // Skip to: 18553 +/* 3756 */ MCD_OPC_Decode, 165, 13, 97, // Opcode: VMAXhd +/* 3760 */ MCD_OPC_FilterValue, 1, 196, 57, 0, // Skip to: 18553 +/* 3765 */ MCD_OPC_CheckPredicate, 22, 191, 57, 0, // Skip to: 18553 +/* 3770 */ MCD_OPC_Decode, 166, 13, 98, // Opcode: VMAXhq +/* 3774 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 3796 +/* 3780 */ MCD_OPC_CheckPredicate, 23, 176, 57, 0, // Skip to: 18553 +/* 3785 */ MCD_OPC_CheckField, 6, 1, 1, 169, 57, 0, // Skip to: 18553 +/* 3792 */ MCD_OPC_Decode, 233, 15, 107, // Opcode: VQRDMLSHslv4i16 +/* 3796 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3818 +/* 3802 */ MCD_OPC_CheckPredicate, 22, 154, 57, 0, // Skip to: 18553 +/* 3807 */ MCD_OPC_CheckField, 6, 1, 0, 147, 57, 0, // Skip to: 18553 +/* 3814 */ MCD_OPC_Decode, 152, 15, 97, // Opcode: VPMAXh +/* 3818 */ MCD_OPC_FilterValue, 231, 3, 137, 57, 0, // Skip to: 18553 +/* 3824 */ MCD_OPC_CheckPredicate, 23, 132, 57, 0, // Skip to: 18553 +/* 3829 */ MCD_OPC_CheckField, 6, 1, 1, 125, 57, 0, // Skip to: 18553 +/* 3836 */ MCD_OPC_Decode, 235, 15, 108, // Opcode: VQRDMLSHslv8i16 +/* 3840 */ MCD_OPC_FilterValue, 2, 155, 8, 0, // Skip to: 6048 +/* 3845 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 3848 */ MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 4004 +/* 3853 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3856 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3893 +/* 3862 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3865 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3879 +/* 3870 */ MCD_OPC_CheckPredicate, 21, 86, 57, 0, // Skip to: 18553 +/* 3875 */ MCD_OPC_Decode, 175, 10, 97, // Opcode: VHADDsv2i32 +/* 3879 */ MCD_OPC_FilterValue, 1, 77, 57, 0, // Skip to: 18553 +/* 3884 */ MCD_OPC_CheckPredicate, 21, 72, 57, 0, // Skip to: 18553 +/* 3889 */ MCD_OPC_Decode, 177, 10, 98, // Opcode: VHADDsv4i32 +/* 3893 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3930 +/* 3899 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3902 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3916 +/* 3907 */ MCD_OPC_CheckPredicate, 21, 49, 57, 0, // Skip to: 18553 +/* 3912 */ MCD_OPC_Decode, 240, 7, 99, // Opcode: VADDLsv2i64 +/* 3916 */ MCD_OPC_FilterValue, 1, 40, 57, 0, // Skip to: 18553 +/* 3921 */ MCD_OPC_CheckPredicate, 21, 35, 57, 0, // Skip to: 18553 +/* 3926 */ MCD_OPC_Decode, 223, 13, 113, // Opcode: VMLAslv2i32 +/* 3930 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3967 +/* 3936 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3939 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3953 +/* 3944 */ MCD_OPC_CheckPredicate, 21, 12, 57, 0, // Skip to: 18553 +/* 3949 */ MCD_OPC_Decode, 181, 10, 97, // Opcode: VHADDuv2i32 +/* 3953 */ MCD_OPC_FilterValue, 1, 3, 57, 0, // Skip to: 18553 +/* 3958 */ MCD_OPC_CheckPredicate, 21, 254, 56, 0, // Skip to: 18553 +/* 3963 */ MCD_OPC_Decode, 183, 10, 98, // Opcode: VHADDuv4i32 +/* 3967 */ MCD_OPC_FilterValue, 231, 3, 244, 56, 0, // Skip to: 18553 +/* 3973 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3976 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3990 +/* 3981 */ MCD_OPC_CheckPredicate, 21, 231, 56, 0, // Skip to: 18553 +/* 3986 */ MCD_OPC_Decode, 243, 7, 99, // Opcode: VADDLuv2i64 +/* 3990 */ MCD_OPC_FilterValue, 1, 222, 56, 0, // Skip to: 18553 +/* 3995 */ MCD_OPC_CheckPredicate, 21, 217, 56, 0, // Skip to: 18553 +/* 4000 */ MCD_OPC_Decode, 225, 13, 114, // Opcode: VMLAslv4i32 +/* 4004 */ MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 4160 +/* 4009 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4012 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4049 +/* 4018 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4021 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4035 +/* 4026 */ MCD_OPC_CheckPredicate, 21, 186, 56, 0, // Skip to: 18553 +/* 4031 */ MCD_OPC_Decode, 236, 16, 97, // Opcode: VRHADDsv2i32 +/* 4035 */ MCD_OPC_FilterValue, 1, 177, 56, 0, // Skip to: 18553 +/* 4040 */ MCD_OPC_CheckPredicate, 21, 172, 56, 0, // Skip to: 18553 +/* 4045 */ MCD_OPC_Decode, 238, 16, 98, // Opcode: VRHADDsv4i32 +/* 4049 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4086 +/* 4055 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4058 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4072 +/* 4063 */ MCD_OPC_CheckPredicate, 21, 149, 56, 0, // Skip to: 18553 +/* 4068 */ MCD_OPC_Decode, 247, 7, 100, // Opcode: VADDWsv2i64 +/* 4072 */ MCD_OPC_FilterValue, 1, 140, 56, 0, // Skip to: 18553 +/* 4077 */ MCD_OPC_CheckPredicate, 21, 135, 56, 0, // Skip to: 18553 +/* 4082 */ MCD_OPC_Decode, 219, 13, 113, // Opcode: VMLAslfd +/* 4086 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4123 +/* 4092 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4095 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4109 +/* 4100 */ MCD_OPC_CheckPredicate, 21, 112, 56, 0, // Skip to: 18553 +/* 4105 */ MCD_OPC_Decode, 242, 16, 97, // Opcode: VRHADDuv2i32 +/* 4109 */ MCD_OPC_FilterValue, 1, 103, 56, 0, // Skip to: 18553 +/* 4114 */ MCD_OPC_CheckPredicate, 21, 98, 56, 0, // Skip to: 18553 +/* 4119 */ MCD_OPC_Decode, 244, 16, 98, // Opcode: VRHADDuv4i32 +/* 4123 */ MCD_OPC_FilterValue, 231, 3, 88, 56, 0, // Skip to: 18553 +/* 4129 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4132 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4146 +/* 4137 */ MCD_OPC_CheckPredicate, 21, 75, 56, 0, // Skip to: 18553 +/* 4142 */ MCD_OPC_Decode, 250, 7, 100, // Opcode: VADDWuv2i64 +/* 4146 */ MCD_OPC_FilterValue, 1, 66, 56, 0, // Skip to: 18553 +/* 4151 */ MCD_OPC_CheckPredicate, 21, 61, 56, 0, // Skip to: 18553 +/* 4156 */ MCD_OPC_Decode, 220, 13, 114, // Opcode: VMLAslfq +/* 4160 */ MCD_OPC_FilterValue, 2, 151, 0, 0, // Skip to: 4316 +/* 4165 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4168 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4205 +/* 4174 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4177 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4191 +/* 4182 */ MCD_OPC_CheckPredicate, 21, 30, 56, 0, // Skip to: 18553 +/* 4187 */ MCD_OPC_Decode, 187, 10, 97, // Opcode: VHSUBsv2i32 +/* 4191 */ MCD_OPC_FilterValue, 1, 21, 56, 0, // Skip to: 18553 +/* 4196 */ MCD_OPC_CheckPredicate, 21, 16, 56, 0, // Skip to: 18553 +/* 4201 */ MCD_OPC_Decode, 189, 10, 98, // Opcode: VHSUBsv4i32 +/* 4205 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4242 +/* 4211 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4214 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4228 +/* 4219 */ MCD_OPC_CheckPredicate, 21, 249, 55, 0, // Skip to: 18553 +/* 4224 */ MCD_OPC_Decode, 212, 20, 99, // Opcode: VSUBLsv2i64 +/* 4228 */ MCD_OPC_FilterValue, 1, 240, 55, 0, // Skip to: 18553 +/* 4233 */ MCD_OPC_CheckPredicate, 21, 235, 55, 0, // Skip to: 18553 +/* 4238 */ MCD_OPC_Decode, 204, 13, 115, // Opcode: VMLALslsv2i32 +/* 4242 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4279 +/* 4248 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4251 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4265 +/* 4256 */ MCD_OPC_CheckPredicate, 21, 212, 55, 0, // Skip to: 18553 +/* 4261 */ MCD_OPC_Decode, 193, 10, 97, // Opcode: VHSUBuv2i32 +/* 4265 */ MCD_OPC_FilterValue, 1, 203, 55, 0, // Skip to: 18553 +/* 4270 */ MCD_OPC_CheckPredicate, 21, 198, 55, 0, // Skip to: 18553 +/* 4275 */ MCD_OPC_Decode, 195, 10, 98, // Opcode: VHSUBuv4i32 +/* 4279 */ MCD_OPC_FilterValue, 231, 3, 188, 55, 0, // Skip to: 18553 +/* 4285 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4288 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4302 +/* 4293 */ MCD_OPC_CheckPredicate, 21, 175, 55, 0, // Skip to: 18553 +/* 4298 */ MCD_OPC_Decode, 215, 20, 99, // Opcode: VSUBLuv2i64 +/* 4302 */ MCD_OPC_FilterValue, 1, 166, 55, 0, // Skip to: 18553 +/* 4307 */ MCD_OPC_CheckPredicate, 21, 161, 55, 0, // Skip to: 18553 +/* 4312 */ MCD_OPC_Decode, 206, 13, 115, // Opcode: VMLALsluv2i32 +/* 4316 */ MCD_OPC_FilterValue, 3, 136, 0, 0, // Skip to: 4457 +/* 4321 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4324 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4361 +/* 4330 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4333 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4347 +/* 4338 */ MCD_OPC_CheckPredicate, 21, 130, 55, 0, // Skip to: 18553 +/* 4343 */ MCD_OPC_Decode, 206, 8, 97, // Opcode: VCGTsv2i32 +/* 4347 */ MCD_OPC_FilterValue, 1, 121, 55, 0, // Skip to: 18553 +/* 4352 */ MCD_OPC_CheckPredicate, 21, 116, 55, 0, // Skip to: 18553 +/* 4357 */ MCD_OPC_Decode, 208, 8, 98, // Opcode: VCGTsv4i32 +/* 4361 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4398 +/* 4367 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4370 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4384 +/* 4375 */ MCD_OPC_CheckPredicate, 21, 93, 55, 0, // Skip to: 18553 +/* 4380 */ MCD_OPC_Decode, 219, 20, 100, // Opcode: VSUBWsv2i64 +/* 4384 */ MCD_OPC_FilterValue, 1, 84, 55, 0, // Skip to: 18553 +/* 4389 */ MCD_OPC_CheckPredicate, 21, 79, 55, 0, // Skip to: 18553 +/* 4394 */ MCD_OPC_Decode, 189, 15, 115, // Opcode: VQDMLALslv2i32 +/* 4398 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4435 +/* 4404 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4407 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4421 +/* 4412 */ MCD_OPC_CheckPredicate, 21, 56, 55, 0, // Skip to: 18553 +/* 4417 */ MCD_OPC_Decode, 212, 8, 97, // Opcode: VCGTuv2i32 +/* 4421 */ MCD_OPC_FilterValue, 1, 47, 55, 0, // Skip to: 18553 +/* 4426 */ MCD_OPC_CheckPredicate, 21, 42, 55, 0, // Skip to: 18553 +/* 4431 */ MCD_OPC_Decode, 214, 8, 98, // Opcode: VCGTuv4i32 +/* 4435 */ MCD_OPC_FilterValue, 231, 3, 32, 55, 0, // Skip to: 18553 +/* 4441 */ MCD_OPC_CheckPredicate, 21, 27, 55, 0, // Skip to: 18553 +/* 4446 */ MCD_OPC_CheckField, 6, 1, 0, 20, 55, 0, // Skip to: 18553 +/* 4453 */ MCD_OPC_Decode, 222, 20, 100, // Opcode: VSUBWuv2i64 +/* 4457 */ MCD_OPC_FilterValue, 4, 151, 0, 0, // Skip to: 4613 +/* 4462 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4465 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4502 +/* 4471 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4474 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4488 +/* 4479 */ MCD_OPC_CheckPredicate, 21, 245, 54, 0, // Skip to: 18553 +/* 4484 */ MCD_OPC_Decode, 138, 18, 101, // Opcode: VSHLsv2i32 +/* 4488 */ MCD_OPC_FilterValue, 1, 236, 54, 0, // Skip to: 18553 +/* 4493 */ MCD_OPC_CheckPredicate, 21, 231, 54, 0, // Skip to: 18553 +/* 4498 */ MCD_OPC_Decode, 141, 18, 102, // Opcode: VSHLsv4i32 +/* 4502 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4539 +/* 4508 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4511 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4525 +/* 4516 */ MCD_OPC_CheckPredicate, 21, 208, 54, 0, // Skip to: 18553 +/* 4521 */ MCD_OPC_Decode, 237, 7, 103, // Opcode: VADDHNv2i32 +/* 4525 */ MCD_OPC_FilterValue, 1, 199, 54, 0, // Skip to: 18553 +/* 4530 */ MCD_OPC_CheckPredicate, 21, 194, 54, 0, // Skip to: 18553 +/* 4535 */ MCD_OPC_Decode, 254, 13, 113, // Opcode: VMLSslv2i32 +/* 4539 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4576 +/* 4545 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4548 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4562 +/* 4553 */ MCD_OPC_CheckPredicate, 21, 171, 54, 0, // Skip to: 18553 +/* 4558 */ MCD_OPC_Decode, 146, 18, 101, // Opcode: VSHLuv2i32 +/* 4562 */ MCD_OPC_FilterValue, 1, 162, 54, 0, // Skip to: 18553 +/* 4567 */ MCD_OPC_CheckPredicate, 21, 157, 54, 0, // Skip to: 18553 +/* 4572 */ MCD_OPC_Decode, 149, 18, 102, // Opcode: VSHLuv4i32 +/* 4576 */ MCD_OPC_FilterValue, 231, 3, 147, 54, 0, // Skip to: 18553 +/* 4582 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4585 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4599 +/* 4590 */ MCD_OPC_CheckPredicate, 21, 134, 54, 0, // Skip to: 18553 +/* 4595 */ MCD_OPC_Decode, 210, 16, 103, // Opcode: VRADDHNv2i32 +/* 4599 */ MCD_OPC_FilterValue, 1, 125, 54, 0, // Skip to: 18553 +/* 4604 */ MCD_OPC_CheckPredicate, 21, 120, 54, 0, // Skip to: 18553 +/* 4609 */ MCD_OPC_Decode, 128, 14, 114, // Opcode: VMLSslv4i32 +/* 4613 */ MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 4769 +/* 4618 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4621 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4658 +/* 4627 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4630 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4644 +/* 4635 */ MCD_OPC_CheckPredicate, 21, 89, 54, 0, // Skip to: 18553 +/* 4640 */ MCD_OPC_Decode, 166, 17, 101, // Opcode: VRSHLsv2i32 +/* 4644 */ MCD_OPC_FilterValue, 1, 80, 54, 0, // Skip to: 18553 +/* 4649 */ MCD_OPC_CheckPredicate, 21, 75, 54, 0, // Skip to: 18553 +/* 4654 */ MCD_OPC_Decode, 169, 17, 102, // Opcode: VRSHLsv4i32 +/* 4658 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4695 +/* 4664 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4667 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4681 +/* 4672 */ MCD_OPC_CheckPredicate, 21, 52, 54, 0, // Skip to: 18553 +/* 4677 */ MCD_OPC_Decode, 174, 7, 104, // Opcode: VABALsv2i64 +/* 4681 */ MCD_OPC_FilterValue, 1, 43, 54, 0, // Skip to: 18553 +/* 4686 */ MCD_OPC_CheckPredicate, 21, 38, 54, 0, // Skip to: 18553 +/* 4691 */ MCD_OPC_Decode, 250, 13, 113, // Opcode: VMLSslfd +/* 4695 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4732 +/* 4701 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4704 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4718 +/* 4709 */ MCD_OPC_CheckPredicate, 21, 15, 54, 0, // Skip to: 18553 +/* 4714 */ MCD_OPC_Decode, 174, 17, 101, // Opcode: VRSHLuv2i32 +/* 4718 */ MCD_OPC_FilterValue, 1, 6, 54, 0, // Skip to: 18553 +/* 4723 */ MCD_OPC_CheckPredicate, 21, 1, 54, 0, // Skip to: 18553 +/* 4728 */ MCD_OPC_Decode, 177, 17, 102, // Opcode: VRSHLuv4i32 +/* 4732 */ MCD_OPC_FilterValue, 231, 3, 247, 53, 0, // Skip to: 18553 +/* 4738 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4741 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4755 +/* 4746 */ MCD_OPC_CheckPredicate, 21, 234, 53, 0, // Skip to: 18553 +/* 4751 */ MCD_OPC_Decode, 177, 7, 104, // Opcode: VABALuv2i64 +/* 4755 */ MCD_OPC_FilterValue, 1, 225, 53, 0, // Skip to: 18553 +/* 4760 */ MCD_OPC_CheckPredicate, 21, 220, 53, 0, // Skip to: 18553 +/* 4765 */ MCD_OPC_Decode, 251, 13, 114, // Opcode: VMLSslfq +/* 4769 */ MCD_OPC_FilterValue, 6, 151, 0, 0, // Skip to: 4925 +/* 4774 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4777 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4814 +/* 4783 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4786 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4800 +/* 4791 */ MCD_OPC_CheckPredicate, 21, 189, 53, 0, // Skip to: 18553 +/* 4796 */ MCD_OPC_Decode, 168, 13, 97, // Opcode: VMAXsv2i32 +/* 4800 */ MCD_OPC_FilterValue, 1, 180, 53, 0, // Skip to: 18553 +/* 4805 */ MCD_OPC_CheckPredicate, 21, 175, 53, 0, // Skip to: 18553 +/* 4810 */ MCD_OPC_Decode, 170, 13, 98, // Opcode: VMAXsv4i32 +/* 4814 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4851 +/* 4820 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4823 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4837 +/* 4828 */ MCD_OPC_CheckPredicate, 21, 152, 53, 0, // Skip to: 18553 +/* 4833 */ MCD_OPC_Decode, 209, 20, 103, // Opcode: VSUBHNv2i32 +/* 4837 */ MCD_OPC_FilterValue, 1, 143, 53, 0, // Skip to: 18553 +/* 4842 */ MCD_OPC_CheckPredicate, 21, 138, 53, 0, // Skip to: 18553 +/* 4847 */ MCD_OPC_Decode, 235, 13, 115, // Opcode: VMLSLslsv2i32 +/* 4851 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4888 +/* 4857 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4860 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4874 +/* 4865 */ MCD_OPC_CheckPredicate, 21, 115, 53, 0, // Skip to: 18553 +/* 4870 */ MCD_OPC_Decode, 174, 13, 97, // Opcode: VMAXuv2i32 +/* 4874 */ MCD_OPC_FilterValue, 1, 106, 53, 0, // Skip to: 18553 +/* 4879 */ MCD_OPC_CheckPredicate, 21, 101, 53, 0, // Skip to: 18553 +/* 4884 */ MCD_OPC_Decode, 176, 13, 98, // Opcode: VMAXuv4i32 +/* 4888 */ MCD_OPC_FilterValue, 231, 3, 91, 53, 0, // Skip to: 18553 +/* 4894 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4897 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4911 +/* 4902 */ MCD_OPC_CheckPredicate, 21, 78, 53, 0, // Skip to: 18553 +/* 4907 */ MCD_OPC_Decode, 225, 17, 103, // Opcode: VRSUBHNv2i32 +/* 4911 */ MCD_OPC_FilterValue, 1, 69, 53, 0, // Skip to: 18553 +/* 4916 */ MCD_OPC_CheckPredicate, 21, 64, 53, 0, // Skip to: 18553 +/* 4921 */ MCD_OPC_Decode, 237, 13, 115, // Opcode: VMLSLsluv2i32 +/* 4925 */ MCD_OPC_FilterValue, 7, 136, 0, 0, // Skip to: 5066 +/* 4930 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4933 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4970 +/* 4939 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4942 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4956 +/* 4947 */ MCD_OPC_CheckPredicate, 21, 33, 53, 0, // Skip to: 18553 +/* 4952 */ MCD_OPC_Decode, 203, 7, 97, // Opcode: VABDsv2i32 +/* 4956 */ MCD_OPC_FilterValue, 1, 24, 53, 0, // Skip to: 18553 +/* 4961 */ MCD_OPC_CheckPredicate, 21, 19, 53, 0, // Skip to: 18553 +/* 4966 */ MCD_OPC_Decode, 205, 7, 98, // Opcode: VABDsv4i32 +/* 4970 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5007 +/* 4976 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4979 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4993 +/* 4984 */ MCD_OPC_CheckPredicate, 21, 252, 52, 0, // Skip to: 18553 +/* 4989 */ MCD_OPC_Decode, 192, 7, 99, // Opcode: VABDLsv2i64 +/* 4993 */ MCD_OPC_FilterValue, 1, 243, 52, 0, // Skip to: 18553 +/* 4998 */ MCD_OPC_CheckPredicate, 21, 238, 52, 0, // Skip to: 18553 +/* 5003 */ MCD_OPC_Decode, 193, 15, 115, // Opcode: VQDMLSLslv2i32 +/* 5007 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5044 +/* 5013 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5016 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5030 +/* 5021 */ MCD_OPC_CheckPredicate, 21, 215, 52, 0, // Skip to: 18553 +/* 5026 */ MCD_OPC_Decode, 209, 7, 97, // Opcode: VABDuv2i32 +/* 5030 */ MCD_OPC_FilterValue, 1, 206, 52, 0, // Skip to: 18553 +/* 5035 */ MCD_OPC_CheckPredicate, 21, 201, 52, 0, // Skip to: 18553 +/* 5040 */ MCD_OPC_Decode, 211, 7, 98, // Opcode: VABDuv4i32 +/* 5044 */ MCD_OPC_FilterValue, 231, 3, 191, 52, 0, // Skip to: 18553 +/* 5050 */ MCD_OPC_CheckPredicate, 21, 186, 52, 0, // Skip to: 18553 +/* 5055 */ MCD_OPC_CheckField, 6, 1, 0, 179, 52, 0, // Skip to: 18553 +/* 5062 */ MCD_OPC_Decode, 195, 7, 99, // Opcode: VABDLuv2i64 +/* 5066 */ MCD_OPC_FilterValue, 8, 151, 0, 0, // Skip to: 5222 +/* 5071 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5074 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5111 +/* 5080 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5083 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5097 +/* 5088 */ MCD_OPC_CheckPredicate, 21, 148, 52, 0, // Skip to: 18553 +/* 5093 */ MCD_OPC_Decode, 131, 8, 97, // Opcode: VADDv2i32 +/* 5097 */ MCD_OPC_FilterValue, 1, 139, 52, 0, // Skip to: 18553 +/* 5102 */ MCD_OPC_CheckPredicate, 21, 134, 52, 0, // Skip to: 18553 +/* 5107 */ MCD_OPC_Decode, 134, 8, 98, // Opcode: VADDv4i32 +/* 5111 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5148 +/* 5117 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5120 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5134 +/* 5125 */ MCD_OPC_CheckPredicate, 21, 111, 52, 0, // Skip to: 18553 +/* 5130 */ MCD_OPC_Decode, 208, 13, 104, // Opcode: VMLALsv2i64 +/* 5134 */ MCD_OPC_FilterValue, 1, 102, 52, 0, // Skip to: 18553 +/* 5139 */ MCD_OPC_CheckPredicate, 21, 97, 52, 0, // Skip to: 18553 +/* 5144 */ MCD_OPC_Decode, 204, 14, 116, // Opcode: VMULslv2i32 +/* 5148 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5185 +/* 5154 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5157 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5171 +/* 5162 */ MCD_OPC_CheckPredicate, 21, 74, 52, 0, // Skip to: 18553 +/* 5167 */ MCD_OPC_Decode, 231, 20, 97, // Opcode: VSUBv2i32 +/* 5171 */ MCD_OPC_FilterValue, 1, 65, 52, 0, // Skip to: 18553 +/* 5176 */ MCD_OPC_CheckPredicate, 21, 60, 52, 0, // Skip to: 18553 +/* 5181 */ MCD_OPC_Decode, 234, 20, 98, // Opcode: VSUBv4i32 +/* 5185 */ MCD_OPC_FilterValue, 231, 3, 50, 52, 0, // Skip to: 18553 +/* 5191 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5194 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5208 +/* 5199 */ MCD_OPC_CheckPredicate, 21, 37, 52, 0, // Skip to: 18553 +/* 5204 */ MCD_OPC_Decode, 211, 13, 104, // Opcode: VMLALuv2i64 +/* 5208 */ MCD_OPC_FilterValue, 1, 28, 52, 0, // Skip to: 18553 +/* 5213 */ MCD_OPC_CheckPredicate, 21, 23, 52, 0, // Skip to: 18553 +/* 5218 */ MCD_OPC_Decode, 206, 14, 117, // Opcode: VMULslv4i32 +/* 5222 */ MCD_OPC_FilterValue, 9, 136, 0, 0, // Skip to: 5363 +/* 5227 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5230 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5267 +/* 5236 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5239 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5253 +/* 5244 */ MCD_OPC_CheckPredicate, 21, 248, 51, 0, // Skip to: 18553 +/* 5249 */ MCD_OPC_Decode, 228, 13, 105, // Opcode: VMLAv2i32 +/* 5253 */ MCD_OPC_FilterValue, 1, 239, 51, 0, // Skip to: 18553 +/* 5258 */ MCD_OPC_CheckPredicate, 21, 234, 51, 0, // Skip to: 18553 +/* 5263 */ MCD_OPC_Decode, 230, 13, 106, // Opcode: VMLAv4i32 +/* 5267 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5304 +/* 5273 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5276 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5290 +/* 5281 */ MCD_OPC_CheckPredicate, 21, 211, 51, 0, // Skip to: 18553 +/* 5286 */ MCD_OPC_Decode, 191, 15, 104, // Opcode: VQDMLALv2i64 +/* 5290 */ MCD_OPC_FilterValue, 1, 202, 51, 0, // Skip to: 18553 +/* 5295 */ MCD_OPC_CheckPredicate, 21, 197, 51, 0, // Skip to: 18553 +/* 5300 */ MCD_OPC_Decode, 200, 14, 116, // Opcode: VMULslfd +/* 5304 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5341 +/* 5310 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5313 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5327 +/* 5318 */ MCD_OPC_CheckPredicate, 21, 174, 51, 0, // Skip to: 18553 +/* 5323 */ MCD_OPC_Decode, 131, 14, 105, // Opcode: VMLSv2i32 +/* 5327 */ MCD_OPC_FilterValue, 1, 165, 51, 0, // Skip to: 18553 +/* 5332 */ MCD_OPC_CheckPredicate, 21, 160, 51, 0, // Skip to: 18553 +/* 5337 */ MCD_OPC_Decode, 133, 14, 106, // Opcode: VMLSv4i32 +/* 5341 */ MCD_OPC_FilterValue, 231, 3, 150, 51, 0, // Skip to: 18553 +/* 5347 */ MCD_OPC_CheckPredicate, 21, 145, 51, 0, // Skip to: 18553 +/* 5352 */ MCD_OPC_CheckField, 6, 1, 1, 138, 51, 0, // Skip to: 18553 +/* 5359 */ MCD_OPC_Decode, 201, 14, 117, // Opcode: VMULslfq +/* 5363 */ MCD_OPC_FilterValue, 10, 121, 0, 0, // Skip to: 5489 +/* 5368 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5371 */ MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 5393 +/* 5377 */ MCD_OPC_CheckPredicate, 21, 115, 51, 0, // Skip to: 18553 +/* 5382 */ MCD_OPC_CheckField, 6, 1, 0, 108, 51, 0, // Skip to: 18553 +/* 5389 */ MCD_OPC_Decode, 154, 15, 97, // Opcode: VPMAXs32 +/* 5393 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5430 +/* 5399 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5402 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5416 +/* 5407 */ MCD_OPC_CheckPredicate, 21, 85, 51, 0, // Skip to: 18553 +/* 5412 */ MCD_OPC_Decode, 239, 13, 104, // Opcode: VMLSLsv2i64 +/* 5416 */ MCD_OPC_FilterValue, 1, 76, 51, 0, // Skip to: 18553 +/* 5421 */ MCD_OPC_CheckPredicate, 21, 71, 51, 0, // Skip to: 18553 +/* 5426 */ MCD_OPC_Decode, 183, 14, 118, // Opcode: VMULLslsv2i32 +/* 5430 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 5452 +/* 5436 */ MCD_OPC_CheckPredicate, 21, 56, 51, 0, // Skip to: 18553 +/* 5441 */ MCD_OPC_CheckField, 6, 1, 0, 49, 51, 0, // Skip to: 18553 +/* 5448 */ MCD_OPC_Decode, 157, 15, 97, // Opcode: VPMAXu32 +/* 5452 */ MCD_OPC_FilterValue, 231, 3, 39, 51, 0, // Skip to: 18553 +/* 5458 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5461 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5475 +/* 5466 */ MCD_OPC_CheckPredicate, 21, 26, 51, 0, // Skip to: 18553 +/* 5471 */ MCD_OPC_Decode, 242, 13, 104, // Opcode: VMLSLuv2i64 +/* 5475 */ MCD_OPC_FilterValue, 1, 17, 51, 0, // Skip to: 18553 +/* 5480 */ MCD_OPC_CheckPredicate, 21, 12, 51, 0, // Skip to: 18553 +/* 5485 */ MCD_OPC_Decode, 185, 14, 118, // Opcode: VMULLsluv2i32 +/* 5489 */ MCD_OPC_FilterValue, 11, 114, 0, 0, // Skip to: 5608 +/* 5494 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5497 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5534 +/* 5503 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5506 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5520 +/* 5511 */ MCD_OPC_CheckPredicate, 21, 237, 50, 0, // Skip to: 18553 +/* 5516 */ MCD_OPC_Decode, 201, 15, 97, // Opcode: VQDMULHv2i32 +/* 5520 */ MCD_OPC_FilterValue, 1, 228, 50, 0, // Skip to: 18553 +/* 5525 */ MCD_OPC_CheckPredicate, 21, 223, 50, 0, // Skip to: 18553 +/* 5530 */ MCD_OPC_Decode, 203, 15, 98, // Opcode: VQDMULHv4i32 +/* 5534 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5571 +/* 5540 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5543 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5557 +/* 5548 */ MCD_OPC_CheckPredicate, 21, 200, 50, 0, // Skip to: 18553 +/* 5553 */ MCD_OPC_Decode, 195, 15, 104, // Opcode: VQDMLSLv2i64 +/* 5557 */ MCD_OPC_FilterValue, 1, 191, 50, 0, // Skip to: 18553 +/* 5562 */ MCD_OPC_CheckPredicate, 21, 186, 50, 0, // Skip to: 18553 +/* 5567 */ MCD_OPC_Decode, 205, 15, 118, // Opcode: VQDMULLslv2i32 +/* 5571 */ MCD_OPC_FilterValue, 230, 3, 176, 50, 0, // Skip to: 18553 +/* 5577 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5580 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5594 +/* 5585 */ MCD_OPC_CheckPredicate, 21, 163, 50, 0, // Skip to: 18553 +/* 5590 */ MCD_OPC_Decode, 244, 15, 97, // Opcode: VQRDMULHv2i32 +/* 5594 */ MCD_OPC_FilterValue, 1, 154, 50, 0, // Skip to: 18553 +/* 5599 */ MCD_OPC_CheckPredicate, 21, 149, 50, 0, // Skip to: 18553 +/* 5604 */ MCD_OPC_Decode, 246, 15, 98, // Opcode: VQRDMULHv4i32 +/* 5608 */ MCD_OPC_FilterValue, 12, 79, 0, 0, // Skip to: 5692 +/* 5613 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5616 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 5654 +/* 5621 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5624 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 5639 +/* 5630 */ MCD_OPC_CheckPredicate, 21, 118, 50, 0, // Skip to: 18553 +/* 5635 */ MCD_OPC_Decode, 187, 14, 99, // Opcode: VMULLsv2i64 +/* 5639 */ MCD_OPC_FilterValue, 231, 3, 108, 50, 0, // Skip to: 18553 +/* 5645 */ MCD_OPC_CheckPredicate, 21, 103, 50, 0, // Skip to: 18553 +/* 5650 */ MCD_OPC_Decode, 190, 14, 99, // Opcode: VMULLuv2i64 +/* 5654 */ MCD_OPC_FilterValue, 1, 94, 50, 0, // Skip to: 18553 +/* 5659 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5662 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 5677 +/* 5668 */ MCD_OPC_CheckPredicate, 21, 80, 50, 0, // Skip to: 18553 +/* 5673 */ MCD_OPC_Decode, 197, 15, 116, // Opcode: VQDMULHslv2i32 +/* 5677 */ MCD_OPC_FilterValue, 231, 3, 70, 50, 0, // Skip to: 18553 +/* 5683 */ MCD_OPC_CheckPredicate, 21, 65, 50, 0, // Skip to: 18553 +/* 5688 */ MCD_OPC_Decode, 199, 15, 117, // Opcode: VQDMULHslv4i32 +/* 5692 */ MCD_OPC_FilterValue, 13, 136, 0, 0, // Skip to: 5833 +/* 5697 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5700 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5737 +/* 5706 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5709 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5723 +/* 5714 */ MCD_OPC_CheckPredicate, 21, 34, 50, 0, // Skip to: 18553 +/* 5719 */ MCD_OPC_Decode, 225, 20, 97, // Opcode: VSUBfd +/* 5723 */ MCD_OPC_FilterValue, 1, 25, 50, 0, // Skip to: 18553 +/* 5728 */ MCD_OPC_CheckPredicate, 21, 20, 50, 0, // Skip to: 18553 +/* 5733 */ MCD_OPC_Decode, 226, 20, 98, // Opcode: VSUBfq +/* 5737 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5774 +/* 5743 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5746 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5760 +/* 5751 */ MCD_OPC_CheckPredicate, 21, 253, 49, 0, // Skip to: 18553 +/* 5756 */ MCD_OPC_Decode, 207, 15, 99, // Opcode: VQDMULLv2i64 +/* 5760 */ MCD_OPC_FilterValue, 1, 244, 49, 0, // Skip to: 18553 +/* 5765 */ MCD_OPC_CheckPredicate, 21, 239, 49, 0, // Skip to: 18553 +/* 5770 */ MCD_OPC_Decode, 240, 15, 116, // Opcode: VQRDMULHslv2i32 +/* 5774 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5811 +/* 5780 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5783 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5797 +/* 5788 */ MCD_OPC_CheckPredicate, 21, 216, 49, 0, // Skip to: 18553 +/* 5793 */ MCD_OPC_Decode, 198, 7, 97, // Opcode: VABDfd +/* 5797 */ MCD_OPC_FilterValue, 1, 207, 49, 0, // Skip to: 18553 +/* 5802 */ MCD_OPC_CheckPredicate, 21, 202, 49, 0, // Skip to: 18553 +/* 5807 */ MCD_OPC_Decode, 199, 7, 98, // Opcode: VABDfq +/* 5811 */ MCD_OPC_FilterValue, 231, 3, 192, 49, 0, // Skip to: 18553 +/* 5817 */ MCD_OPC_CheckPredicate, 21, 187, 49, 0, // Skip to: 18553 +/* 5822 */ MCD_OPC_CheckField, 6, 1, 1, 180, 49, 0, // Skip to: 18553 +/* 5829 */ MCD_OPC_Decode, 242, 15, 117, // Opcode: VQRDMULHslv4i32 +/* 5833 */ MCD_OPC_FilterValue, 14, 99, 0, 0, // Skip to: 5937 +/* 5838 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5841 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5878 +/* 5847 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5850 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5864 +/* 5855 */ MCD_OPC_CheckPredicate, 24, 149, 49, 0, // Skip to: 18553 +/* 5860 */ MCD_OPC_Decode, 181, 14, 99, // Opcode: VMULLp64 +/* 5864 */ MCD_OPC_FilterValue, 1, 140, 49, 0, // Skip to: 18553 +/* 5869 */ MCD_OPC_CheckPredicate, 23, 135, 49, 0, // Skip to: 18553 +/* 5874 */ MCD_OPC_Decode, 224, 15, 113, // Opcode: VQRDMLAHslv2i32 +/* 5878 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5915 +/* 5884 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5887 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5901 +/* 5892 */ MCD_OPC_CheckPredicate, 21, 112, 49, 0, // Skip to: 18553 +/* 5897 */ MCD_OPC_Decode, 201, 8, 97, // Opcode: VCGTfd +/* 5901 */ MCD_OPC_FilterValue, 1, 103, 49, 0, // Skip to: 18553 +/* 5906 */ MCD_OPC_CheckPredicate, 21, 98, 49, 0, // Skip to: 18553 +/* 5911 */ MCD_OPC_Decode, 202, 8, 98, // Opcode: VCGTfq +/* 5915 */ MCD_OPC_FilterValue, 231, 3, 88, 49, 0, // Skip to: 18553 +/* 5921 */ MCD_OPC_CheckPredicate, 23, 83, 49, 0, // Skip to: 18553 +/* 5926 */ MCD_OPC_CheckField, 6, 1, 1, 76, 49, 0, // Skip to: 18553 +/* 5933 */ MCD_OPC_Decode, 226, 15, 114, // Opcode: VQRDMLAHslv4i32 +/* 5937 */ MCD_OPC_FilterValue, 15, 67, 49, 0, // Skip to: 18553 +/* 5942 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5945 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5982 +/* 5951 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5954 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5968 +/* 5959 */ MCD_OPC_CheckPredicate, 21, 45, 49, 0, // Skip to: 18553 +/* 5964 */ MCD_OPC_Decode, 186, 13, 97, // Opcode: VMINfd +/* 5968 */ MCD_OPC_FilterValue, 1, 36, 49, 0, // Skip to: 18553 +/* 5973 */ MCD_OPC_CheckPredicate, 21, 31, 49, 0, // Skip to: 18553 +/* 5978 */ MCD_OPC_Decode, 187, 13, 98, // Opcode: VMINfq +/* 5982 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 6004 +/* 5988 */ MCD_OPC_CheckPredicate, 23, 16, 49, 0, // Skip to: 18553 +/* 5993 */ MCD_OPC_CheckField, 6, 1, 1, 9, 49, 0, // Skip to: 18553 +/* 6000 */ MCD_OPC_Decode, 232, 15, 113, // Opcode: VQRDMLSHslv2i32 +/* 6004 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 6026 +/* 6010 */ MCD_OPC_CheckPredicate, 21, 250, 48, 0, // Skip to: 18553 +/* 6015 */ MCD_OPC_CheckField, 6, 1, 0, 243, 48, 0, // Skip to: 18553 +/* 6022 */ MCD_OPC_Decode, 159, 15, 97, // Opcode: VPMINf +/* 6026 */ MCD_OPC_FilterValue, 231, 3, 233, 48, 0, // Skip to: 18553 +/* 6032 */ MCD_OPC_CheckPredicate, 23, 228, 48, 0, // Skip to: 18553 +/* 6037 */ MCD_OPC_CheckField, 6, 1, 1, 221, 48, 0, // Skip to: 18553 +/* 6044 */ MCD_OPC_Decode, 234, 15, 114, // Opcode: VQRDMLSHslv4i32 +/* 6048 */ MCD_OPC_FilterValue, 3, 212, 48, 0, // Skip to: 18553 +/* 6053 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6056 */ MCD_OPC_FilterValue, 228, 3, 183, 0, 0, // Skip to: 6245 +/* 6062 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6065 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 6101 +/* 6070 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6073 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6087 +/* 6078 */ MCD_OPC_CheckPredicate, 21, 182, 48, 0, // Skip to: 18553 +/* 6083 */ MCD_OPC_Decode, 137, 18, 101, // Opcode: VSHLsv1i64 +/* 6087 */ MCD_OPC_FilterValue, 1, 173, 48, 0, // Skip to: 18553 +/* 6092 */ MCD_OPC_CheckPredicate, 21, 168, 48, 0, // Skip to: 18553 +/* 6097 */ MCD_OPC_Decode, 139, 18, 102, // Opcode: VSHLsv2i64 +/* 6101 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 6137 +/* 6106 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6109 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6123 +/* 6114 */ MCD_OPC_CheckPredicate, 21, 146, 48, 0, // Skip to: 18553 +/* 6119 */ MCD_OPC_Decode, 165, 17, 101, // Opcode: VRSHLsv1i64 +/* 6123 */ MCD_OPC_FilterValue, 1, 137, 48, 0, // Skip to: 18553 +/* 6128 */ MCD_OPC_CheckPredicate, 21, 132, 48, 0, // Skip to: 18553 +/* 6133 */ MCD_OPC_Decode, 167, 17, 102, // Opcode: VRSHLsv2i64 +/* 6137 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6173 +/* 6142 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6145 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6159 +/* 6150 */ MCD_OPC_CheckPredicate, 21, 110, 48, 0, // Skip to: 18553 +/* 6155 */ MCD_OPC_Decode, 130, 8, 97, // Opcode: VADDv1i64 +/* 6159 */ MCD_OPC_FilterValue, 1, 101, 48, 0, // Skip to: 18553 +/* 6164 */ MCD_OPC_CheckPredicate, 21, 96, 48, 0, // Skip to: 18553 +/* 6169 */ MCD_OPC_Decode, 132, 8, 98, // Opcode: VADDv2i64 +/* 6173 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 6209 +/* 6178 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6181 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6195 +/* 6186 */ MCD_OPC_CheckPredicate, 22, 74, 48, 0, // Skip to: 18553 +/* 6191 */ MCD_OPC_Decode, 227, 20, 97, // Opcode: VSUBhd +/* 6195 */ MCD_OPC_FilterValue, 1, 65, 48, 0, // Skip to: 18553 +/* 6200 */ MCD_OPC_CheckPredicate, 22, 60, 48, 0, // Skip to: 18553 +/* 6205 */ MCD_OPC_Decode, 228, 20, 98, // Opcode: VSUBhq +/* 6209 */ MCD_OPC_FilterValue, 15, 51, 48, 0, // Skip to: 18553 +/* 6214 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6217 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6231 +/* 6222 */ MCD_OPC_CheckPredicate, 22, 38, 48, 0, // Skip to: 18553 +/* 6227 */ MCD_OPC_Decode, 188, 13, 97, // Opcode: VMINhd +/* 6231 */ MCD_OPC_FilterValue, 1, 29, 48, 0, // Skip to: 18553 +/* 6236 */ MCD_OPC_CheckPredicate, 22, 24, 48, 0, // Skip to: 18553 +/* 6241 */ MCD_OPC_Decode, 189, 13, 98, // Opcode: VMINhq +/* 6245 */ MCD_OPC_FilterValue, 229, 3, 119, 0, 0, // Skip to: 6370 +/* 6251 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6254 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6308 +/* 6259 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 6262 */ MCD_OPC_FilterValue, 0, 254, 47, 0, // Skip to: 18553 +/* 6267 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6283 +/* 6272 */ MCD_OPC_CheckField, 8, 2, 0, 4, 0, 0, // Skip to: 6283 +/* 6279 */ MCD_OPC_Decode, 143, 10, 119, // Opcode: VEXTd32 +/* 6283 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6299 +/* 6288 */ MCD_OPC_CheckField, 8, 1, 0, 4, 0, 0, // Skip to: 6299 +/* 6295 */ MCD_OPC_Decode, 142, 10, 120, // Opcode: VEXTd16 +/* 6299 */ MCD_OPC_CheckPredicate, 21, 217, 47, 0, // Skip to: 18553 +/* 6304 */ MCD_OPC_Decode, 144, 10, 121, // Opcode: VEXTd8 +/* 6308 */ MCD_OPC_FilterValue, 1, 208, 47, 0, // Skip to: 18553 +/* 6313 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6329 +/* 6318 */ MCD_OPC_CheckField, 8, 3, 0, 4, 0, 0, // Skip to: 6329 +/* 6325 */ MCD_OPC_Decode, 147, 10, 122, // Opcode: VEXTq64 +/* 6329 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6345 +/* 6334 */ MCD_OPC_CheckField, 8, 2, 0, 4, 0, 0, // Skip to: 6345 +/* 6341 */ MCD_OPC_Decode, 146, 10, 123, // Opcode: VEXTq32 +/* 6345 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6361 +/* 6350 */ MCD_OPC_CheckField, 8, 1, 0, 4, 0, 0, // Skip to: 6361 +/* 6357 */ MCD_OPC_Decode, 145, 10, 124, // Opcode: VEXTq16 +/* 6361 */ MCD_OPC_CheckPredicate, 21, 155, 47, 0, // Skip to: 18553 +/* 6366 */ MCD_OPC_Decode, 148, 10, 125, // Opcode: VEXTq8 +/* 6370 */ MCD_OPC_FilterValue, 230, 3, 204, 0, 0, // Skip to: 6580 +/* 6376 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6379 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 6415 +/* 6384 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6387 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6401 +/* 6392 */ MCD_OPC_CheckPredicate, 21, 124, 47, 0, // Skip to: 18553 +/* 6397 */ MCD_OPC_Decode, 145, 18, 101, // Opcode: VSHLuv1i64 +/* 6401 */ MCD_OPC_FilterValue, 1, 115, 47, 0, // Skip to: 18553 +/* 6406 */ MCD_OPC_CheckPredicate, 21, 110, 47, 0, // Skip to: 18553 +/* 6411 */ MCD_OPC_Decode, 147, 18, 102, // Opcode: VSHLuv2i64 +/* 6415 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 6451 +/* 6420 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6423 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6437 +/* 6428 */ MCD_OPC_CheckPredicate, 21, 88, 47, 0, // Skip to: 18553 +/* 6433 */ MCD_OPC_Decode, 173, 17, 101, // Opcode: VRSHLuv1i64 +/* 6437 */ MCD_OPC_FilterValue, 1, 79, 47, 0, // Skip to: 18553 +/* 6442 */ MCD_OPC_CheckPredicate, 21, 74, 47, 0, // Skip to: 18553 +/* 6447 */ MCD_OPC_Decode, 175, 17, 102, // Opcode: VRSHLuv2i64 +/* 6451 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6487 +/* 6456 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6459 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6473 +/* 6464 */ MCD_OPC_CheckPredicate, 21, 52, 47, 0, // Skip to: 18553 +/* 6469 */ MCD_OPC_Decode, 230, 20, 97, // Opcode: VSUBv1i64 +/* 6473 */ MCD_OPC_FilterValue, 1, 43, 47, 0, // Skip to: 18553 +/* 6478 */ MCD_OPC_CheckPredicate, 21, 38, 47, 0, // Skip to: 18553 +/* 6483 */ MCD_OPC_Decode, 232, 20, 98, // Opcode: VSUBv2i64 +/* 6487 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 6523 +/* 6492 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6495 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6509 +/* 6500 */ MCD_OPC_CheckPredicate, 22, 16, 47, 0, // Skip to: 18553 +/* 6505 */ MCD_OPC_Decode, 200, 7, 97, // Opcode: VABDhd +/* 6509 */ MCD_OPC_FilterValue, 1, 7, 47, 0, // Skip to: 18553 +/* 6514 */ MCD_OPC_CheckPredicate, 22, 2, 47, 0, // Skip to: 18553 +/* 6519 */ MCD_OPC_Decode, 201, 7, 98, // Opcode: VABDhq +/* 6523 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 6559 +/* 6528 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6531 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6545 +/* 6536 */ MCD_OPC_CheckPredicate, 22, 236, 46, 0, // Skip to: 18553 +/* 6541 */ MCD_OPC_Decode, 203, 8, 97, // Opcode: VCGThd +/* 6545 */ MCD_OPC_FilterValue, 1, 227, 46, 0, // Skip to: 18553 +/* 6550 */ MCD_OPC_CheckPredicate, 22, 222, 46, 0, // Skip to: 18553 +/* 6555 */ MCD_OPC_Decode, 204, 8, 98, // Opcode: VCGThq +/* 6559 */ MCD_OPC_FilterValue, 15, 213, 46, 0, // Skip to: 18553 +/* 6564 */ MCD_OPC_CheckPredicate, 22, 208, 46, 0, // Skip to: 18553 +/* 6569 */ MCD_OPC_CheckField, 6, 1, 0, 201, 46, 0, // Skip to: 18553 +/* 6576 */ MCD_OPC_Decode, 160, 15, 97, // Opcode: VPMINh +/* 6580 */ MCD_OPC_FilterValue, 231, 3, 191, 46, 0, // Skip to: 18553 +/* 6586 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 6589 */ MCD_OPC_FilterValue, 0, 247, 1, 0, // Skip to: 7097 +/* 6594 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 6597 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 6661 +/* 6602 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 6605 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6619 +/* 6610 */ MCD_OPC_CheckPredicate, 21, 162, 46, 0, // Skip to: 18553 +/* 6615 */ MCD_OPC_Decode, 231, 16, 126, // Opcode: VREV64d8 +/* 6619 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6633 +/* 6624 */ MCD_OPC_CheckPredicate, 21, 148, 46, 0, // Skip to: 18553 +/* 6629 */ MCD_OPC_Decode, 234, 16, 127, // Opcode: VREV64q8 +/* 6633 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6647 +/* 6638 */ MCD_OPC_CheckPredicate, 21, 134, 46, 0, // Skip to: 18553 +/* 6643 */ MCD_OPC_Decode, 226, 16, 126, // Opcode: VREV32d8 +/* 6647 */ MCD_OPC_FilterValue, 3, 125, 46, 0, // Skip to: 18553 +/* 6652 */ MCD_OPC_CheckPredicate, 21, 120, 46, 0, // Skip to: 18553 +/* 6657 */ MCD_OPC_Decode, 228, 16, 127, // Opcode: VREV32q8 +/* 6661 */ MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 6725 +/* 6666 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 6669 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6683 +/* 6674 */ MCD_OPC_CheckPredicate, 21, 98, 46, 0, // Skip to: 18553 +/* 6679 */ MCD_OPC_Decode, 226, 8, 126, // Opcode: VCGTzv8i8 +/* 6683 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6697 +/* 6688 */ MCD_OPC_CheckPredicate, 21, 84, 46, 0, // Skip to: 18553 +/* 6693 */ MCD_OPC_Decode, 217, 8, 127, // Opcode: VCGTzv16i8 +/* 6697 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6711 +/* 6702 */ MCD_OPC_CheckPredicate, 21, 70, 46, 0, // Skip to: 18553 +/* 6707 */ MCD_OPC_Decode, 200, 8, 126, // Opcode: VCGEzv8i8 +/* 6711 */ MCD_OPC_FilterValue, 3, 61, 46, 0, // Skip to: 18553 +/* 6716 */ MCD_OPC_CheckPredicate, 21, 56, 46, 0, // Skip to: 18553 +/* 6721 */ MCD_OPC_Decode, 191, 8, 127, // Opcode: VCGEzv16i8 +/* 6725 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 6793 +/* 6730 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 6733 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6748 +/* 6738 */ MCD_OPC_CheckPredicate, 21, 34, 46, 0, // Skip to: 18553 +/* 6743 */ MCD_OPC_Decode, 237, 20, 128, 1, // Opcode: VSWPd +/* 6748 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6763 +/* 6753 */ MCD_OPC_CheckPredicate, 21, 19, 46, 0, // Skip to: 18553 +/* 6758 */ MCD_OPC_Decode, 238, 20, 129, 1, // Opcode: VSWPq +/* 6763 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6778 +/* 6768 */ MCD_OPC_CheckPredicate, 21, 4, 46, 0, // Skip to: 18553 +/* 6773 */ MCD_OPC_Decode, 149, 21, 128, 1, // Opcode: VTRNd8 +/* 6778 */ MCD_OPC_FilterValue, 3, 250, 45, 0, // Skip to: 18553 +/* 6783 */ MCD_OPC_CheckPredicate, 21, 245, 45, 0, // Skip to: 18553 +/* 6788 */ MCD_OPC_Decode, 152, 21, 129, 1, // Opcode: VTRNq8 +/* 6793 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 6857 +/* 6798 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 6801 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6815 +/* 6806 */ MCD_OPC_CheckPredicate, 21, 222, 45, 0, // Skip to: 18553 +/* 6811 */ MCD_OPC_Decode, 229, 16, 126, // Opcode: VREV64d16 +/* 6815 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6829 +/* 6820 */ MCD_OPC_CheckPredicate, 21, 208, 45, 0, // Skip to: 18553 +/* 6825 */ MCD_OPC_Decode, 232, 16, 127, // Opcode: VREV64q16 +/* 6829 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6843 +/* 6834 */ MCD_OPC_CheckPredicate, 21, 194, 45, 0, // Skip to: 18553 +/* 6839 */ MCD_OPC_Decode, 225, 16, 126, // Opcode: VREV32d16 +/* 6843 */ MCD_OPC_FilterValue, 3, 185, 45, 0, // Skip to: 18553 +/* 6848 */ MCD_OPC_CheckPredicate, 21, 180, 45, 0, // Skip to: 18553 +/* 6853 */ MCD_OPC_Decode, 227, 16, 127, // Opcode: VREV32q16 +/* 6857 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 6921 +/* 6862 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 6865 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6879 +/* 6870 */ MCD_OPC_CheckPredicate, 21, 158, 45, 0, // Skip to: 18553 +/* 6875 */ MCD_OPC_Decode, 222, 8, 126, // Opcode: VCGTzv4i16 +/* 6879 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6893 +/* 6884 */ MCD_OPC_CheckPredicate, 21, 144, 45, 0, // Skip to: 18553 +/* 6889 */ MCD_OPC_Decode, 225, 8, 127, // Opcode: VCGTzv8i16 +/* 6893 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6907 +/* 6898 */ MCD_OPC_CheckPredicate, 21, 130, 45, 0, // Skip to: 18553 +/* 6903 */ MCD_OPC_Decode, 196, 8, 126, // Opcode: VCGEzv4i16 +/* 6907 */ MCD_OPC_FilterValue, 3, 121, 45, 0, // Skip to: 18553 +/* 6912 */ MCD_OPC_CheckPredicate, 21, 116, 45, 0, // Skip to: 18553 +/* 6917 */ MCD_OPC_Decode, 199, 8, 127, // Opcode: VCGEzv8i16 +/* 6921 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 6959 +/* 6926 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 6929 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6944 +/* 6934 */ MCD_OPC_CheckPredicate, 21, 94, 45, 0, // Skip to: 18553 +/* 6939 */ MCD_OPC_Decode, 147, 21, 128, 1, // Opcode: VTRNd16 +/* 6944 */ MCD_OPC_FilterValue, 3, 84, 45, 0, // Skip to: 18553 +/* 6949 */ MCD_OPC_CheckPredicate, 21, 79, 45, 0, // Skip to: 18553 +/* 6954 */ MCD_OPC_Decode, 150, 21, 129, 1, // Opcode: VTRNq16 +/* 6959 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6995 +/* 6964 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 6967 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6981 +/* 6972 */ MCD_OPC_CheckPredicate, 21, 56, 45, 0, // Skip to: 18553 +/* 6977 */ MCD_OPC_Decode, 230, 16, 126, // Opcode: VREV64d32 +/* 6981 */ MCD_OPC_FilterValue, 1, 47, 45, 0, // Skip to: 18553 +/* 6986 */ MCD_OPC_CheckPredicate, 21, 42, 45, 0, // Skip to: 18553 +/* 6991 */ MCD_OPC_Decode, 233, 16, 127, // Opcode: VREV64q32 +/* 6995 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 7059 +/* 7000 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7003 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7017 +/* 7008 */ MCD_OPC_CheckPredicate, 21, 20, 45, 0, // Skip to: 18553 +/* 7013 */ MCD_OPC_Decode, 219, 8, 126, // Opcode: VCGTzv2i32 +/* 7017 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7031 +/* 7022 */ MCD_OPC_CheckPredicate, 21, 6, 45, 0, // Skip to: 18553 +/* 7027 */ MCD_OPC_Decode, 223, 8, 127, // Opcode: VCGTzv4i32 +/* 7031 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7045 +/* 7036 */ MCD_OPC_CheckPredicate, 21, 248, 44, 0, // Skip to: 18553 +/* 7041 */ MCD_OPC_Decode, 193, 8, 126, // Opcode: VCGEzv2i32 +/* 7045 */ MCD_OPC_FilterValue, 3, 239, 44, 0, // Skip to: 18553 +/* 7050 */ MCD_OPC_CheckPredicate, 21, 234, 44, 0, // Skip to: 18553 +/* 7055 */ MCD_OPC_Decode, 197, 8, 127, // Opcode: VCGEzv4i32 +/* 7059 */ MCD_OPC_FilterValue, 10, 225, 44, 0, // Skip to: 18553 +/* 7064 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7067 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7082 +/* 7072 */ MCD_OPC_CheckPredicate, 21, 212, 44, 0, // Skip to: 18553 +/* 7077 */ MCD_OPC_Decode, 148, 21, 128, 1, // Opcode: VTRNd32 +/* 7082 */ MCD_OPC_FilterValue, 3, 202, 44, 0, // Skip to: 18553 +/* 7087 */ MCD_OPC_CheckPredicate, 21, 197, 44, 0, // Skip to: 18553 +/* 7092 */ MCD_OPC_Decode, 151, 21, 129, 1, // Opcode: VTRNq32 +/* 7097 */ MCD_OPC_FilterValue, 1, 149, 1, 0, // Skip to: 7507 +/* 7102 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7105 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7141 +/* 7110 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7113 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7127 +/* 7118 */ MCD_OPC_CheckPredicate, 21, 166, 44, 0, // Skip to: 18553 +/* 7123 */ MCD_OPC_Decode, 223, 16, 126, // Opcode: VREV16d8 +/* 7127 */ MCD_OPC_FilterValue, 1, 157, 44, 0, // Skip to: 18553 +/* 7132 */ MCD_OPC_CheckPredicate, 21, 152, 44, 0, // Skip to: 18553 +/* 7137 */ MCD_OPC_Decode, 224, 16, 127, // Opcode: VREV16q8 +/* 7141 */ MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 7205 +/* 7146 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7149 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7163 +/* 7154 */ MCD_OPC_CheckPredicate, 21, 130, 44, 0, // Skip to: 18553 +/* 7159 */ MCD_OPC_Decode, 174, 8, 126, // Opcode: VCEQzv8i8 +/* 7163 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7177 +/* 7168 */ MCD_OPC_CheckPredicate, 21, 116, 44, 0, // Skip to: 18553 +/* 7173 */ MCD_OPC_Decode, 165, 8, 127, // Opcode: VCEQzv16i8 +/* 7177 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7191 +/* 7182 */ MCD_OPC_CheckPredicate, 21, 102, 44, 0, // Skip to: 18553 +/* 7187 */ MCD_OPC_Decode, 236, 8, 126, // Opcode: VCLEzv8i8 +/* 7191 */ MCD_OPC_FilterValue, 3, 93, 44, 0, // Skip to: 18553 +/* 7196 */ MCD_OPC_CheckPredicate, 21, 88, 44, 0, // Skip to: 18553 +/* 7201 */ MCD_OPC_Decode, 227, 8, 127, // Opcode: VCLEzv16i8 +/* 7205 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 7273 +/* 7210 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7213 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7228 +/* 7218 */ MCD_OPC_CheckPredicate, 21, 66, 44, 0, // Skip to: 18553 +/* 7223 */ MCD_OPC_Decode, 173, 21, 128, 1, // Opcode: VUZPd8 +/* 7228 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7243 +/* 7233 */ MCD_OPC_CheckPredicate, 21, 51, 44, 0, // Skip to: 18553 +/* 7238 */ MCD_OPC_Decode, 176, 21, 129, 1, // Opcode: VUZPq8 +/* 7243 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7258 +/* 7248 */ MCD_OPC_CheckPredicate, 21, 36, 44, 0, // Skip to: 18553 +/* 7253 */ MCD_OPC_Decode, 178, 21, 128, 1, // Opcode: VZIPd8 +/* 7258 */ MCD_OPC_FilterValue, 3, 26, 44, 0, // Skip to: 18553 +/* 7263 */ MCD_OPC_CheckPredicate, 21, 21, 44, 0, // Skip to: 18553 +/* 7268 */ MCD_OPC_Decode, 181, 21, 129, 1, // Opcode: VZIPq8 +/* 7273 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 7337 +/* 7278 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7281 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7295 +/* 7286 */ MCD_OPC_CheckPredicate, 21, 254, 43, 0, // Skip to: 18553 +/* 7291 */ MCD_OPC_Decode, 170, 8, 126, // Opcode: VCEQzv4i16 +/* 7295 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7309 +/* 7300 */ MCD_OPC_CheckPredicate, 21, 240, 43, 0, // Skip to: 18553 +/* 7305 */ MCD_OPC_Decode, 173, 8, 127, // Opcode: VCEQzv8i16 +/* 7309 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7323 +/* 7314 */ MCD_OPC_CheckPredicate, 21, 226, 43, 0, // Skip to: 18553 +/* 7319 */ MCD_OPC_Decode, 232, 8, 126, // Opcode: VCLEzv4i16 +/* 7323 */ MCD_OPC_FilterValue, 3, 217, 43, 0, // Skip to: 18553 +/* 7328 */ MCD_OPC_CheckPredicate, 21, 212, 43, 0, // Skip to: 18553 +/* 7333 */ MCD_OPC_Decode, 235, 8, 127, // Opcode: VCLEzv8i16 +/* 7337 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 7405 +/* 7342 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7345 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7360 +/* 7350 */ MCD_OPC_CheckPredicate, 21, 190, 43, 0, // Skip to: 18553 +/* 7355 */ MCD_OPC_Decode, 172, 21, 128, 1, // Opcode: VUZPd16 +/* 7360 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7375 +/* 7365 */ MCD_OPC_CheckPredicate, 21, 175, 43, 0, // Skip to: 18553 +/* 7370 */ MCD_OPC_Decode, 174, 21, 129, 1, // Opcode: VUZPq16 +/* 7375 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7390 +/* 7380 */ MCD_OPC_CheckPredicate, 21, 160, 43, 0, // Skip to: 18553 +/* 7385 */ MCD_OPC_Decode, 177, 21, 128, 1, // Opcode: VZIPd16 +/* 7390 */ MCD_OPC_FilterValue, 3, 150, 43, 0, // Skip to: 18553 +/* 7395 */ MCD_OPC_CheckPredicate, 21, 145, 43, 0, // Skip to: 18553 +/* 7400 */ MCD_OPC_Decode, 179, 21, 129, 1, // Opcode: VZIPq16 +/* 7405 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 7469 +/* 7410 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7413 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7427 +/* 7418 */ MCD_OPC_CheckPredicate, 21, 122, 43, 0, // Skip to: 18553 +/* 7423 */ MCD_OPC_Decode, 167, 8, 126, // Opcode: VCEQzv2i32 +/* 7427 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7441 +/* 7432 */ MCD_OPC_CheckPredicate, 21, 108, 43, 0, // Skip to: 18553 +/* 7437 */ MCD_OPC_Decode, 171, 8, 127, // Opcode: VCEQzv4i32 +/* 7441 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7455 +/* 7446 */ MCD_OPC_CheckPredicate, 21, 94, 43, 0, // Skip to: 18553 +/* 7451 */ MCD_OPC_Decode, 229, 8, 126, // Opcode: VCLEzv2i32 +/* 7455 */ MCD_OPC_FilterValue, 3, 85, 43, 0, // Skip to: 18553 +/* 7460 */ MCD_OPC_CheckPredicate, 21, 80, 43, 0, // Skip to: 18553 +/* 7465 */ MCD_OPC_Decode, 233, 8, 127, // Opcode: VCLEzv4i32 +/* 7469 */ MCD_OPC_FilterValue, 10, 71, 43, 0, // Skip to: 18553 +/* 7474 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7477 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7492 +/* 7482 */ MCD_OPC_CheckPredicate, 21, 58, 43, 0, // Skip to: 18553 +/* 7487 */ MCD_OPC_Decode, 175, 21, 129, 1, // Opcode: VUZPq32 +/* 7492 */ MCD_OPC_FilterValue, 3, 48, 43, 0, // Skip to: 18553 +/* 7497 */ MCD_OPC_CheckPredicate, 21, 43, 43, 0, // Skip to: 18553 +/* 7502 */ MCD_OPC_Decode, 180, 21, 129, 1, // Opcode: VZIPq32 +/* 7507 */ MCD_OPC_FilterValue, 2, 251, 1, 0, // Skip to: 8019 +/* 7512 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 7515 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 7579 +/* 7520 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7523 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7537 +/* 7528 */ MCD_OPC_CheckPredicate, 21, 12, 43, 0, // Skip to: 18553 +/* 7533 */ MCD_OPC_Decode, 139, 15, 126, // Opcode: VPADDLsv8i8 +/* 7537 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7551 +/* 7542 */ MCD_OPC_CheckPredicate, 21, 254, 42, 0, // Skip to: 18553 +/* 7547 */ MCD_OPC_Decode, 134, 15, 127, // Opcode: VPADDLsv16i8 +/* 7551 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7565 +/* 7556 */ MCD_OPC_CheckPredicate, 21, 240, 42, 0, // Skip to: 18553 +/* 7561 */ MCD_OPC_Decode, 145, 15, 126, // Opcode: VPADDLuv8i8 +/* 7565 */ MCD_OPC_FilterValue, 3, 231, 42, 0, // Skip to: 18553 +/* 7570 */ MCD_OPC_CheckPredicate, 21, 226, 42, 0, // Skip to: 18553 +/* 7575 */ MCD_OPC_Decode, 140, 15, 127, // Opcode: VPADDLuv16i8 +/* 7579 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 7615 +/* 7584 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7587 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7601 +/* 7592 */ MCD_OPC_CheckPredicate, 21, 204, 42, 0, // Skip to: 18553 +/* 7597 */ MCD_OPC_Decode, 252, 8, 126, // Opcode: VCLTzv8i8 +/* 7601 */ MCD_OPC_FilterValue, 1, 195, 42, 0, // Skip to: 18553 +/* 7606 */ MCD_OPC_CheckPredicate, 21, 190, 42, 0, // Skip to: 18553 +/* 7611 */ MCD_OPC_Decode, 243, 8, 127, // Opcode: VCLTzv16i8 +/* 7615 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 7683 +/* 7620 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7623 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7638 +/* 7628 */ MCD_OPC_CheckPredicate, 21, 168, 42, 0, // Skip to: 18553 +/* 7633 */ MCD_OPC_Decode, 148, 14, 130, 1, // Opcode: VMOVNv8i8 +/* 7638 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7653 +/* 7643 */ MCD_OPC_CheckPredicate, 21, 153, 42, 0, // Skip to: 18553 +/* 7648 */ MCD_OPC_Decode, 211, 15, 130, 1, // Opcode: VQMOVNsuv8i8 +/* 7653 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7668 +/* 7658 */ MCD_OPC_CheckPredicate, 21, 138, 42, 0, // Skip to: 18553 +/* 7663 */ MCD_OPC_Decode, 214, 15, 130, 1, // Opcode: VQMOVNsv8i8 +/* 7668 */ MCD_OPC_FilterValue, 3, 128, 42, 0, // Skip to: 18553 +/* 7673 */ MCD_OPC_CheckPredicate, 21, 123, 42, 0, // Skip to: 18553 +/* 7678 */ MCD_OPC_Decode, 217, 15, 130, 1, // Opcode: VQMOVNuv8i8 +/* 7683 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 7747 +/* 7688 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7691 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7705 +/* 7696 */ MCD_OPC_CheckPredicate, 21, 100, 42, 0, // Skip to: 18553 +/* 7701 */ MCD_OPC_Decode, 136, 15, 126, // Opcode: VPADDLsv4i16 +/* 7705 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7719 +/* 7710 */ MCD_OPC_CheckPredicate, 21, 86, 42, 0, // Skip to: 18553 +/* 7715 */ MCD_OPC_Decode, 138, 15, 127, // Opcode: VPADDLsv8i16 +/* 7719 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7733 +/* 7724 */ MCD_OPC_CheckPredicate, 21, 72, 42, 0, // Skip to: 18553 +/* 7729 */ MCD_OPC_Decode, 142, 15, 126, // Opcode: VPADDLuv4i16 +/* 7733 */ MCD_OPC_FilterValue, 3, 63, 42, 0, // Skip to: 18553 +/* 7738 */ MCD_OPC_CheckPredicate, 21, 58, 42, 0, // Skip to: 18553 +/* 7743 */ MCD_OPC_Decode, 144, 15, 127, // Opcode: VPADDLuv8i16 +/* 7747 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 7783 +/* 7752 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7755 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7769 +/* 7760 */ MCD_OPC_CheckPredicate, 21, 36, 42, 0, // Skip to: 18553 +/* 7765 */ MCD_OPC_Decode, 248, 8, 126, // Opcode: VCLTzv4i16 +/* 7769 */ MCD_OPC_FilterValue, 1, 27, 42, 0, // Skip to: 18553 +/* 7774 */ MCD_OPC_CheckPredicate, 21, 22, 42, 0, // Skip to: 18553 +/* 7779 */ MCD_OPC_Decode, 251, 8, 127, // Opcode: VCLTzv8i16 +/* 7783 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 7851 +/* 7788 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7791 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7806 +/* 7796 */ MCD_OPC_CheckPredicate, 21, 0, 42, 0, // Skip to: 18553 +/* 7801 */ MCD_OPC_Decode, 147, 14, 130, 1, // Opcode: VMOVNv4i16 +/* 7806 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7821 +/* 7811 */ MCD_OPC_CheckPredicate, 21, 241, 41, 0, // Skip to: 18553 +/* 7816 */ MCD_OPC_Decode, 210, 15, 130, 1, // Opcode: VQMOVNsuv4i16 +/* 7821 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7836 +/* 7826 */ MCD_OPC_CheckPredicate, 21, 226, 41, 0, // Skip to: 18553 +/* 7831 */ MCD_OPC_Decode, 213, 15, 130, 1, // Opcode: VQMOVNsv4i16 +/* 7836 */ MCD_OPC_FilterValue, 3, 216, 41, 0, // Skip to: 18553 +/* 7841 */ MCD_OPC_CheckPredicate, 21, 211, 41, 0, // Skip to: 18553 +/* 7846 */ MCD_OPC_Decode, 216, 15, 130, 1, // Opcode: VQMOVNuv4i16 +/* 7851 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 7915 +/* 7856 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7859 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7873 +/* 7864 */ MCD_OPC_CheckPredicate, 21, 188, 41, 0, // Skip to: 18553 +/* 7869 */ MCD_OPC_Decode, 135, 15, 126, // Opcode: VPADDLsv2i32 +/* 7873 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7887 +/* 7878 */ MCD_OPC_CheckPredicate, 21, 174, 41, 0, // Skip to: 18553 +/* 7883 */ MCD_OPC_Decode, 137, 15, 127, // Opcode: VPADDLsv4i32 +/* 7887 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7901 +/* 7892 */ MCD_OPC_CheckPredicate, 21, 160, 41, 0, // Skip to: 18553 +/* 7897 */ MCD_OPC_Decode, 141, 15, 126, // Opcode: VPADDLuv2i32 +/* 7901 */ MCD_OPC_FilterValue, 3, 151, 41, 0, // Skip to: 18553 +/* 7906 */ MCD_OPC_CheckPredicate, 21, 146, 41, 0, // Skip to: 18553 +/* 7911 */ MCD_OPC_Decode, 143, 15, 127, // Opcode: VPADDLuv4i32 +/* 7915 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 7951 +/* 7920 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7923 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7937 +/* 7928 */ MCD_OPC_CheckPredicate, 21, 124, 41, 0, // Skip to: 18553 +/* 7933 */ MCD_OPC_Decode, 245, 8, 126, // Opcode: VCLTzv2i32 +/* 7937 */ MCD_OPC_FilterValue, 1, 115, 41, 0, // Skip to: 18553 +/* 7942 */ MCD_OPC_CheckPredicate, 21, 110, 41, 0, // Skip to: 18553 +/* 7947 */ MCD_OPC_Decode, 249, 8, 127, // Opcode: VCLTzv4i32 +/* 7951 */ MCD_OPC_FilterValue, 10, 101, 41, 0, // Skip to: 18553 +/* 7956 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 7959 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7974 +/* 7964 */ MCD_OPC_CheckPredicate, 21, 88, 41, 0, // Skip to: 18553 +/* 7969 */ MCD_OPC_Decode, 146, 14, 130, 1, // Opcode: VMOVNv2i32 +/* 7974 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7989 +/* 7979 */ MCD_OPC_CheckPredicate, 21, 73, 41, 0, // Skip to: 18553 +/* 7984 */ MCD_OPC_Decode, 209, 15, 130, 1, // Opcode: VQMOVNsuv2i32 +/* 7989 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8004 +/* 7994 */ MCD_OPC_CheckPredicate, 21, 58, 41, 0, // Skip to: 18553 +/* 7999 */ MCD_OPC_Decode, 212, 15, 130, 1, // Opcode: VQMOVNsv2i32 +/* 8004 */ MCD_OPC_FilterValue, 3, 48, 41, 0, // Skip to: 18553 +/* 8009 */ MCD_OPC_CheckPredicate, 21, 43, 41, 0, // Skip to: 18553 +/* 8014 */ MCD_OPC_Decode, 215, 15, 130, 1, // Opcode: VQMOVNuv2i32 +/* 8019 */ MCD_OPC_FilterValue, 3, 5, 1, 0, // Skip to: 8285 +/* 8024 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 8027 */ MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 8091 +/* 8032 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8035 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8049 +/* 8040 */ MCD_OPC_CheckPredicate, 21, 12, 41, 0, // Skip to: 18553 +/* 8045 */ MCD_OPC_Decode, 226, 7, 126, // Opcode: VABSv8i8 +/* 8049 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8063 +/* 8054 */ MCD_OPC_CheckPredicate, 21, 254, 40, 0, // Skip to: 18553 +/* 8059 */ MCD_OPC_Decode, 221, 7, 127, // Opcode: VABSv16i8 +/* 8063 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8077 +/* 8068 */ MCD_OPC_CheckPredicate, 21, 240, 40, 0, // Skip to: 18553 +/* 8073 */ MCD_OPC_Decode, 231, 14, 126, // Opcode: VNEGs8d +/* 8077 */ MCD_OPC_FilterValue, 3, 231, 40, 0, // Skip to: 18553 +/* 8082 */ MCD_OPC_CheckPredicate, 21, 226, 40, 0, // Skip to: 18553 +/* 8087 */ MCD_OPC_Decode, 232, 14, 127, // Opcode: VNEGs8q +/* 8091 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 8113 +/* 8096 */ MCD_OPC_CheckPredicate, 21, 212, 40, 0, // Skip to: 18553 +/* 8101 */ MCD_OPC_CheckField, 6, 2, 0, 205, 40, 0, // Skip to: 18553 +/* 8108 */ MCD_OPC_Decode, 249, 17, 131, 1, // Opcode: VSHLLi8 +/* 8113 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8177 +/* 8118 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8121 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8135 +/* 8126 */ MCD_OPC_CheckPredicate, 21, 182, 40, 0, // Skip to: 18553 +/* 8131 */ MCD_OPC_Decode, 223, 7, 126, // Opcode: VABSv4i16 +/* 8135 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8149 +/* 8140 */ MCD_OPC_CheckPredicate, 21, 168, 40, 0, // Skip to: 18553 +/* 8145 */ MCD_OPC_Decode, 225, 7, 127, // Opcode: VABSv8i16 +/* 8149 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8163 +/* 8154 */ MCD_OPC_CheckPredicate, 21, 154, 40, 0, // Skip to: 18553 +/* 8159 */ MCD_OPC_Decode, 227, 14, 126, // Opcode: VNEGs16d +/* 8163 */ MCD_OPC_FilterValue, 3, 145, 40, 0, // Skip to: 18553 +/* 8168 */ MCD_OPC_CheckPredicate, 21, 140, 40, 0, // Skip to: 18553 +/* 8173 */ MCD_OPC_Decode, 228, 14, 127, // Opcode: VNEGs16q +/* 8177 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 8199 +/* 8182 */ MCD_OPC_CheckPredicate, 21, 126, 40, 0, // Skip to: 18553 +/* 8187 */ MCD_OPC_CheckField, 6, 2, 0, 119, 40, 0, // Skip to: 18553 +/* 8194 */ MCD_OPC_Decode, 247, 17, 131, 1, // Opcode: VSHLLi16 +/* 8199 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8263 +/* 8204 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8207 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8221 +/* 8212 */ MCD_OPC_CheckPredicate, 21, 96, 40, 0, // Skip to: 18553 +/* 8217 */ MCD_OPC_Decode, 222, 7, 126, // Opcode: VABSv2i32 +/* 8221 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8235 +/* 8226 */ MCD_OPC_CheckPredicate, 21, 82, 40, 0, // Skip to: 18553 +/* 8231 */ MCD_OPC_Decode, 224, 7, 127, // Opcode: VABSv4i32 +/* 8235 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8249 +/* 8240 */ MCD_OPC_CheckPredicate, 21, 68, 40, 0, // Skip to: 18553 +/* 8245 */ MCD_OPC_Decode, 229, 14, 126, // Opcode: VNEGs32d +/* 8249 */ MCD_OPC_FilterValue, 3, 59, 40, 0, // Skip to: 18553 +/* 8254 */ MCD_OPC_CheckPredicate, 21, 54, 40, 0, // Skip to: 18553 +/* 8259 */ MCD_OPC_Decode, 230, 14, 127, // Opcode: VNEGs32q +/* 8263 */ MCD_OPC_FilterValue, 10, 45, 40, 0, // Skip to: 18553 +/* 8268 */ MCD_OPC_CheckPredicate, 21, 40, 40, 0, // Skip to: 18553 +/* 8273 */ MCD_OPC_CheckField, 6, 2, 0, 33, 40, 0, // Skip to: 18553 +/* 8280 */ MCD_OPC_Decode, 248, 17, 131, 1, // Opcode: VSHLLi32 +/* 8285 */ MCD_OPC_FilterValue, 4, 131, 1, 0, // Skip to: 8677 +/* 8290 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 8293 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 8357 +/* 8298 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8301 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8315 +/* 8306 */ MCD_OPC_CheckPredicate, 21, 2, 40, 0, // Skip to: 18553 +/* 8311 */ MCD_OPC_Decode, 242, 8, 126, // Opcode: VCLSv8i8 +/* 8315 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8329 +/* 8320 */ MCD_OPC_CheckPredicate, 21, 244, 39, 0, // Skip to: 18553 +/* 8325 */ MCD_OPC_Decode, 237, 8, 127, // Opcode: VCLSv16i8 +/* 8329 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8343 +/* 8334 */ MCD_OPC_CheckPredicate, 21, 230, 39, 0, // Skip to: 18553 +/* 8339 */ MCD_OPC_Decode, 130, 9, 126, // Opcode: VCLZv8i8 +/* 8343 */ MCD_OPC_FilterValue, 3, 221, 39, 0, // Skip to: 18553 +/* 8348 */ MCD_OPC_CheckPredicate, 21, 216, 39, 0, // Skip to: 18553 +/* 8353 */ MCD_OPC_Decode, 253, 8, 127, // Opcode: VCLZv16i8 +/* 8357 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 8421 +/* 8362 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8365 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8379 +/* 8370 */ MCD_OPC_CheckPredicate, 21, 194, 39, 0, // Skip to: 18553 +/* 8375 */ MCD_OPC_Decode, 239, 8, 126, // Opcode: VCLSv4i16 +/* 8379 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8393 +/* 8384 */ MCD_OPC_CheckPredicate, 21, 180, 39, 0, // Skip to: 18553 +/* 8389 */ MCD_OPC_Decode, 241, 8, 127, // Opcode: VCLSv8i16 +/* 8393 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8407 +/* 8398 */ MCD_OPC_CheckPredicate, 21, 166, 39, 0, // Skip to: 18553 +/* 8403 */ MCD_OPC_Decode, 255, 8, 126, // Opcode: VCLZv4i16 +/* 8407 */ MCD_OPC_FilterValue, 3, 157, 39, 0, // Skip to: 18553 +/* 8412 */ MCD_OPC_CheckPredicate, 21, 152, 39, 0, // Skip to: 18553 +/* 8417 */ MCD_OPC_Decode, 129, 9, 127, // Opcode: VCLZv8i16 +/* 8421 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8485 +/* 8426 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8429 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8443 +/* 8434 */ MCD_OPC_CheckPredicate, 22, 130, 39, 0, // Skip to: 18553 +/* 8439 */ MCD_OPC_Decode, 220, 8, 126, // Opcode: VCGTzv4f16 +/* 8443 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8457 +/* 8448 */ MCD_OPC_CheckPredicate, 22, 116, 39, 0, // Skip to: 18553 +/* 8453 */ MCD_OPC_Decode, 224, 8, 127, // Opcode: VCGTzv8f16 +/* 8457 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8471 +/* 8462 */ MCD_OPC_CheckPredicate, 22, 102, 39, 0, // Skip to: 18553 +/* 8467 */ MCD_OPC_Decode, 194, 8, 126, // Opcode: VCGEzv4f16 +/* 8471 */ MCD_OPC_FilterValue, 3, 93, 39, 0, // Skip to: 18553 +/* 8476 */ MCD_OPC_CheckPredicate, 22, 88, 39, 0, // Skip to: 18553 +/* 8481 */ MCD_OPC_Decode, 198, 8, 127, // Opcode: VCGEzv8f16 +/* 8485 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 8549 +/* 8490 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8493 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8507 +/* 8498 */ MCD_OPC_CheckPredicate, 21, 66, 39, 0, // Skip to: 18553 +/* 8503 */ MCD_OPC_Decode, 238, 8, 126, // Opcode: VCLSv2i32 +/* 8507 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8521 +/* 8512 */ MCD_OPC_CheckPredicate, 21, 52, 39, 0, // Skip to: 18553 +/* 8517 */ MCD_OPC_Decode, 240, 8, 127, // Opcode: VCLSv4i32 +/* 8521 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8535 +/* 8526 */ MCD_OPC_CheckPredicate, 21, 38, 39, 0, // Skip to: 18553 +/* 8531 */ MCD_OPC_Decode, 254, 8, 126, // Opcode: VCLZv2i32 +/* 8535 */ MCD_OPC_FilterValue, 3, 29, 39, 0, // Skip to: 18553 +/* 8540 */ MCD_OPC_CheckPredicate, 21, 24, 39, 0, // Skip to: 18553 +/* 8545 */ MCD_OPC_Decode, 128, 9, 127, // Opcode: VCLZv4i32 +/* 8549 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8613 +/* 8554 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8557 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8571 +/* 8562 */ MCD_OPC_CheckPredicate, 21, 2, 39, 0, // Skip to: 18553 +/* 8567 */ MCD_OPC_Decode, 218, 8, 126, // Opcode: VCGTzv2f32 +/* 8571 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8585 +/* 8576 */ MCD_OPC_CheckPredicate, 21, 244, 38, 0, // Skip to: 18553 +/* 8581 */ MCD_OPC_Decode, 221, 8, 127, // Opcode: VCGTzv4f32 +/* 8585 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8599 +/* 8590 */ MCD_OPC_CheckPredicate, 21, 230, 38, 0, // Skip to: 18553 +/* 8595 */ MCD_OPC_Decode, 192, 8, 126, // Opcode: VCGEzv2f32 +/* 8599 */ MCD_OPC_FilterValue, 3, 221, 38, 0, // Skip to: 18553 +/* 8604 */ MCD_OPC_CheckPredicate, 21, 216, 38, 0, // Skip to: 18553 +/* 8609 */ MCD_OPC_Decode, 195, 8, 127, // Opcode: VCGEzv4f32 +/* 8613 */ MCD_OPC_FilterValue, 11, 207, 38, 0, // Skip to: 18553 +/* 8618 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8621 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8635 +/* 8626 */ MCD_OPC_CheckPredicate, 21, 194, 38, 0, // Skip to: 18553 +/* 8631 */ MCD_OPC_Decode, 213, 16, 126, // Opcode: VRECPEd +/* 8635 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8649 +/* 8640 */ MCD_OPC_CheckPredicate, 21, 180, 38, 0, // Skip to: 18553 +/* 8645 */ MCD_OPC_Decode, 218, 16, 127, // Opcode: VRECPEq +/* 8649 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8663 +/* 8654 */ MCD_OPC_CheckPredicate, 21, 166, 38, 0, // Skip to: 18553 +/* 8659 */ MCD_OPC_Decode, 199, 17, 126, // Opcode: VRSQRTEd +/* 8663 */ MCD_OPC_FilterValue, 3, 157, 38, 0, // Skip to: 18553 +/* 8668 */ MCD_OPC_CheckPredicate, 21, 152, 38, 0, // Skip to: 18553 +/* 8673 */ MCD_OPC_Decode, 204, 17, 127, // Opcode: VRSQRTEq +/* 8677 */ MCD_OPC_FilterValue, 5, 67, 1, 0, // Skip to: 9005 +/* 8682 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 8685 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 8749 +/* 8690 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8693 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8707 +/* 8698 */ MCD_OPC_CheckPredicate, 21, 122, 38, 0, // Skip to: 18553 +/* 8703 */ MCD_OPC_Decode, 151, 9, 126, // Opcode: VCNTd +/* 8707 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8721 +/* 8712 */ MCD_OPC_CheckPredicate, 21, 108, 38, 0, // Skip to: 18553 +/* 8717 */ MCD_OPC_Decode, 152, 9, 127, // Opcode: VCNTq +/* 8721 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8735 +/* 8726 */ MCD_OPC_CheckPredicate, 21, 94, 38, 0, // Skip to: 18553 +/* 8731 */ MCD_OPC_Decode, 214, 14, 126, // Opcode: VMVNd +/* 8735 */ MCD_OPC_FilterValue, 3, 85, 38, 0, // Skip to: 18553 +/* 8740 */ MCD_OPC_CheckPredicate, 21, 80, 38, 0, // Skip to: 18553 +/* 8745 */ MCD_OPC_Decode, 215, 14, 127, // Opcode: VMVNq +/* 8749 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8813 +/* 8754 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8757 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8771 +/* 8762 */ MCD_OPC_CheckPredicate, 22, 58, 38, 0, // Skip to: 18553 +/* 8767 */ MCD_OPC_Decode, 168, 8, 126, // Opcode: VCEQzv4f16 +/* 8771 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8785 +/* 8776 */ MCD_OPC_CheckPredicate, 22, 44, 38, 0, // Skip to: 18553 +/* 8781 */ MCD_OPC_Decode, 172, 8, 127, // Opcode: VCEQzv8f16 +/* 8785 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8799 +/* 8790 */ MCD_OPC_CheckPredicate, 22, 30, 38, 0, // Skip to: 18553 +/* 8795 */ MCD_OPC_Decode, 230, 8, 126, // Opcode: VCLEzv4f16 +/* 8799 */ MCD_OPC_FilterValue, 3, 21, 38, 0, // Skip to: 18553 +/* 8804 */ MCD_OPC_CheckPredicate, 22, 16, 38, 0, // Skip to: 18553 +/* 8809 */ MCD_OPC_Decode, 234, 8, 127, // Opcode: VCLEzv8f16 +/* 8813 */ MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 8877 +/* 8818 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8821 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8835 +/* 8826 */ MCD_OPC_CheckPredicate, 22, 250, 37, 0, // Skip to: 18553 +/* 8831 */ MCD_OPC_Decode, 216, 16, 126, // Opcode: VRECPEhd +/* 8835 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8849 +/* 8840 */ MCD_OPC_CheckPredicate, 22, 236, 37, 0, // Skip to: 18553 +/* 8845 */ MCD_OPC_Decode, 217, 16, 127, // Opcode: VRECPEhq +/* 8849 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8863 +/* 8854 */ MCD_OPC_CheckPredicate, 22, 222, 37, 0, // Skip to: 18553 +/* 8859 */ MCD_OPC_Decode, 202, 17, 126, // Opcode: VRSQRTEhd +/* 8863 */ MCD_OPC_FilterValue, 3, 213, 37, 0, // Skip to: 18553 +/* 8868 */ MCD_OPC_CheckPredicate, 22, 208, 37, 0, // Skip to: 18553 +/* 8873 */ MCD_OPC_Decode, 203, 17, 127, // Opcode: VRSQRTEhq +/* 8877 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8941 +/* 8882 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8885 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8899 +/* 8890 */ MCD_OPC_CheckPredicate, 21, 186, 37, 0, // Skip to: 18553 +/* 8895 */ MCD_OPC_Decode, 166, 8, 126, // Opcode: VCEQzv2f32 +/* 8899 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8913 +/* 8904 */ MCD_OPC_CheckPredicate, 21, 172, 37, 0, // Skip to: 18553 +/* 8909 */ MCD_OPC_Decode, 169, 8, 127, // Opcode: VCEQzv4f32 +/* 8913 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8927 +/* 8918 */ MCD_OPC_CheckPredicate, 21, 158, 37, 0, // Skip to: 18553 +/* 8923 */ MCD_OPC_Decode, 228, 8, 126, // Opcode: VCLEzv2f32 +/* 8927 */ MCD_OPC_FilterValue, 3, 149, 37, 0, // Skip to: 18553 +/* 8932 */ MCD_OPC_CheckPredicate, 21, 144, 37, 0, // Skip to: 18553 +/* 8937 */ MCD_OPC_Decode, 231, 8, 127, // Opcode: VCLEzv4f32 +/* 8941 */ MCD_OPC_FilterValue, 11, 135, 37, 0, // Skip to: 18553 +/* 8946 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 8949 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8963 +/* 8954 */ MCD_OPC_CheckPredicate, 21, 122, 37, 0, // Skip to: 18553 +/* 8959 */ MCD_OPC_Decode, 214, 16, 126, // Opcode: VRECPEfd +/* 8963 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8977 +/* 8968 */ MCD_OPC_CheckPredicate, 21, 108, 37, 0, // Skip to: 18553 +/* 8973 */ MCD_OPC_Decode, 215, 16, 127, // Opcode: VRECPEfq +/* 8977 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8991 +/* 8982 */ MCD_OPC_CheckPredicate, 21, 94, 37, 0, // Skip to: 18553 +/* 8987 */ MCD_OPC_Decode, 200, 17, 126, // Opcode: VRSQRTEfd +/* 8991 */ MCD_OPC_FilterValue, 3, 85, 37, 0, // Skip to: 18553 +/* 8996 */ MCD_OPC_CheckPredicate, 21, 80, 37, 0, // Skip to: 18553 +/* 9001 */ MCD_OPC_Decode, 201, 17, 127, // Opcode: VRSQRTEfq +/* 9005 */ MCD_OPC_FilterValue, 6, 173, 1, 0, // Skip to: 9439 +/* 9010 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 9013 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 9081 +/* 9018 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9021 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9036 +/* 9026 */ MCD_OPC_CheckPredicate, 21, 50, 37, 0, // Skip to: 18553 +/* 9031 */ MCD_OPC_Decode, 255, 14, 132, 1, // Opcode: VPADALsv8i8 +/* 9036 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9051 +/* 9041 */ MCD_OPC_CheckPredicate, 21, 35, 37, 0, // Skip to: 18553 +/* 9046 */ MCD_OPC_Decode, 250, 14, 133, 1, // Opcode: VPADALsv16i8 +/* 9051 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9066 +/* 9056 */ MCD_OPC_CheckPredicate, 21, 20, 37, 0, // Skip to: 18553 +/* 9061 */ MCD_OPC_Decode, 133, 15, 132, 1, // Opcode: VPADALuv8i8 +/* 9066 */ MCD_OPC_FilterValue, 3, 10, 37, 0, // Skip to: 18553 +/* 9071 */ MCD_OPC_CheckPredicate, 21, 5, 37, 0, // Skip to: 18553 +/* 9076 */ MCD_OPC_Decode, 128, 15, 133, 1, // Opcode: VPADALuv16i8 +/* 9081 */ MCD_OPC_FilterValue, 4, 63, 0, 0, // Skip to: 9149 +/* 9086 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9089 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9104 +/* 9094 */ MCD_OPC_CheckPredicate, 21, 238, 36, 0, // Skip to: 18553 +/* 9099 */ MCD_OPC_Decode, 252, 14, 132, 1, // Opcode: VPADALsv4i16 +/* 9104 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9119 +/* 9109 */ MCD_OPC_CheckPredicate, 21, 223, 36, 0, // Skip to: 18553 +/* 9114 */ MCD_OPC_Decode, 254, 14, 133, 1, // Opcode: VPADALsv8i16 +/* 9119 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9134 +/* 9124 */ MCD_OPC_CheckPredicate, 21, 208, 36, 0, // Skip to: 18553 +/* 9129 */ MCD_OPC_Decode, 130, 15, 132, 1, // Opcode: VPADALuv4i16 +/* 9134 */ MCD_OPC_FilterValue, 3, 198, 36, 0, // Skip to: 18553 +/* 9139 */ MCD_OPC_CheckPredicate, 21, 193, 36, 0, // Skip to: 18553 +/* 9144 */ MCD_OPC_Decode, 132, 15, 133, 1, // Opcode: VPADALuv8i16 +/* 9149 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 9185 +/* 9154 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9157 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9171 +/* 9162 */ MCD_OPC_CheckPredicate, 22, 170, 36, 0, // Skip to: 18553 +/* 9167 */ MCD_OPC_Decode, 246, 8, 126, // Opcode: VCLTzv4f16 +/* 9171 */ MCD_OPC_FilterValue, 1, 161, 36, 0, // Skip to: 18553 +/* 9176 */ MCD_OPC_CheckPredicate, 22, 156, 36, 0, // Skip to: 18553 +/* 9181 */ MCD_OPC_Decode, 250, 8, 127, // Opcode: VCLTzv8f16 +/* 9185 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 9207 +/* 9190 */ MCD_OPC_CheckPredicate, 25, 142, 36, 0, // Skip to: 18553 +/* 9195 */ MCD_OPC_CheckField, 6, 2, 0, 135, 36, 0, // Skip to: 18553 +/* 9202 */ MCD_OPC_Decode, 219, 9, 130, 1, // Opcode: VCVTf2h +/* 9207 */ MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 9271 +/* 9212 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9215 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9229 +/* 9220 */ MCD_OPC_CheckPredicate, 22, 112, 36, 0, // Skip to: 18553 +/* 9225 */ MCD_OPC_Decode, 239, 9, 126, // Opcode: VCVTs2hd +/* 9229 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9243 +/* 9234 */ MCD_OPC_CheckPredicate, 22, 98, 36, 0, // Skip to: 18553 +/* 9239 */ MCD_OPC_Decode, 240, 9, 127, // Opcode: VCVTs2hq +/* 9243 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9257 +/* 9248 */ MCD_OPC_CheckPredicate, 22, 84, 36, 0, // Skip to: 18553 +/* 9253 */ MCD_OPC_Decode, 243, 9, 126, // Opcode: VCVTu2hd +/* 9257 */ MCD_OPC_FilterValue, 3, 75, 36, 0, // Skip to: 18553 +/* 9262 */ MCD_OPC_CheckPredicate, 22, 70, 36, 0, // Skip to: 18553 +/* 9267 */ MCD_OPC_Decode, 244, 9, 127, // Opcode: VCVTu2hq +/* 9271 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 9339 +/* 9276 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9279 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9294 +/* 9284 */ MCD_OPC_CheckPredicate, 21, 48, 36, 0, // Skip to: 18553 +/* 9289 */ MCD_OPC_Decode, 251, 14, 132, 1, // Opcode: VPADALsv2i32 +/* 9294 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9309 +/* 9299 */ MCD_OPC_CheckPredicate, 21, 33, 36, 0, // Skip to: 18553 +/* 9304 */ MCD_OPC_Decode, 253, 14, 133, 1, // Opcode: VPADALsv4i32 +/* 9309 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9324 +/* 9314 */ MCD_OPC_CheckPredicate, 21, 18, 36, 0, // Skip to: 18553 +/* 9319 */ MCD_OPC_Decode, 129, 15, 132, 1, // Opcode: VPADALuv2i32 +/* 9324 */ MCD_OPC_FilterValue, 3, 8, 36, 0, // Skip to: 18553 +/* 9329 */ MCD_OPC_CheckPredicate, 21, 3, 36, 0, // Skip to: 18553 +/* 9334 */ MCD_OPC_Decode, 131, 15, 133, 1, // Opcode: VPADALuv4i32 +/* 9339 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 9375 +/* 9344 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9347 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9361 +/* 9352 */ MCD_OPC_CheckPredicate, 21, 236, 35, 0, // Skip to: 18553 +/* 9357 */ MCD_OPC_Decode, 244, 8, 126, // Opcode: VCLTzv2f32 +/* 9361 */ MCD_OPC_FilterValue, 1, 227, 35, 0, // Skip to: 18553 +/* 9366 */ MCD_OPC_CheckPredicate, 21, 222, 35, 0, // Skip to: 18553 +/* 9371 */ MCD_OPC_Decode, 247, 8, 127, // Opcode: VCLTzv4f32 +/* 9375 */ MCD_OPC_FilterValue, 11, 213, 35, 0, // Skip to: 18553 +/* 9380 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9383 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9397 +/* 9388 */ MCD_OPC_CheckPredicate, 21, 200, 35, 0, // Skip to: 18553 +/* 9393 */ MCD_OPC_Decode, 237, 9, 126, // Opcode: VCVTs2fd +/* 9397 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9411 +/* 9402 */ MCD_OPC_CheckPredicate, 21, 186, 35, 0, // Skip to: 18553 +/* 9407 */ MCD_OPC_Decode, 238, 9, 127, // Opcode: VCVTs2fq +/* 9411 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9425 +/* 9416 */ MCD_OPC_CheckPredicate, 21, 172, 35, 0, // Skip to: 18553 +/* 9421 */ MCD_OPC_Decode, 241, 9, 126, // Opcode: VCVTu2fd +/* 9425 */ MCD_OPC_FilterValue, 3, 163, 35, 0, // Skip to: 18553 +/* 9430 */ MCD_OPC_CheckPredicate, 21, 158, 35, 0, // Skip to: 18553 +/* 9435 */ MCD_OPC_Decode, 242, 9, 127, // Opcode: VCVTu2fq +/* 9439 */ MCD_OPC_FilterValue, 7, 217, 1, 0, // Skip to: 9917 +/* 9444 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 9447 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 9511 +/* 9452 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9455 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9469 +/* 9460 */ MCD_OPC_CheckPredicate, 21, 128, 35, 0, // Skip to: 18553 +/* 9465 */ MCD_OPC_Decode, 172, 15, 126, // Opcode: VQABSv8i8 +/* 9469 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9483 +/* 9474 */ MCD_OPC_CheckPredicate, 21, 114, 35, 0, // Skip to: 18553 +/* 9479 */ MCD_OPC_Decode, 167, 15, 127, // Opcode: VQABSv16i8 +/* 9483 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9497 +/* 9488 */ MCD_OPC_CheckPredicate, 21, 100, 35, 0, // Skip to: 18553 +/* 9493 */ MCD_OPC_Decode, 223, 15, 126, // Opcode: VQNEGv8i8 +/* 9497 */ MCD_OPC_FilterValue, 3, 91, 35, 0, // Skip to: 18553 +/* 9502 */ MCD_OPC_CheckPredicate, 21, 86, 35, 0, // Skip to: 18553 +/* 9507 */ MCD_OPC_Decode, 218, 15, 127, // Opcode: VQNEGv16i8 +/* 9511 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 9575 +/* 9516 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9519 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9533 +/* 9524 */ MCD_OPC_CheckPredicate, 21, 64, 35, 0, // Skip to: 18553 +/* 9529 */ MCD_OPC_Decode, 169, 15, 126, // Opcode: VQABSv4i16 +/* 9533 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9547 +/* 9538 */ MCD_OPC_CheckPredicate, 21, 50, 35, 0, // Skip to: 18553 +/* 9543 */ MCD_OPC_Decode, 171, 15, 127, // Opcode: VQABSv8i16 +/* 9547 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9561 +/* 9552 */ MCD_OPC_CheckPredicate, 21, 36, 35, 0, // Skip to: 18553 +/* 9557 */ MCD_OPC_Decode, 220, 15, 126, // Opcode: VQNEGv4i16 +/* 9561 */ MCD_OPC_FilterValue, 3, 27, 35, 0, // Skip to: 18553 +/* 9566 */ MCD_OPC_CheckPredicate, 21, 22, 35, 0, // Skip to: 18553 +/* 9571 */ MCD_OPC_Decode, 222, 15, 127, // Opcode: VQNEGv8i16 +/* 9575 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 9639 +/* 9580 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9583 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9597 +/* 9588 */ MCD_OPC_CheckPredicate, 22, 0, 35, 0, // Skip to: 18553 +/* 9593 */ MCD_OPC_Decode, 219, 7, 126, // Opcode: VABShd +/* 9597 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9611 +/* 9602 */ MCD_OPC_CheckPredicate, 22, 242, 34, 0, // Skip to: 18553 +/* 9607 */ MCD_OPC_Decode, 220, 7, 127, // Opcode: VABShq +/* 9611 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9625 +/* 9616 */ MCD_OPC_CheckPredicate, 22, 228, 34, 0, // Skip to: 18553 +/* 9621 */ MCD_OPC_Decode, 225, 14, 126, // Opcode: VNEGhd +/* 9625 */ MCD_OPC_FilterValue, 3, 219, 34, 0, // Skip to: 18553 +/* 9630 */ MCD_OPC_CheckPredicate, 22, 214, 34, 0, // Skip to: 18553 +/* 9635 */ MCD_OPC_Decode, 226, 14, 127, // Opcode: VNEGhq +/* 9639 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 9661 +/* 9644 */ MCD_OPC_CheckPredicate, 25, 200, 34, 0, // Skip to: 18553 +/* 9649 */ MCD_OPC_CheckField, 6, 2, 0, 193, 34, 0, // Skip to: 18553 +/* 9656 */ MCD_OPC_Decode, 228, 9, 134, 1, // Opcode: VCVTh2f +/* 9661 */ MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 9725 +/* 9666 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9669 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9683 +/* 9674 */ MCD_OPC_CheckPredicate, 22, 170, 34, 0, // Skip to: 18553 +/* 9679 */ MCD_OPC_Decode, 229, 9, 126, // Opcode: VCVTh2sd +/* 9683 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9697 +/* 9688 */ MCD_OPC_CheckPredicate, 22, 156, 34, 0, // Skip to: 18553 +/* 9693 */ MCD_OPC_Decode, 230, 9, 127, // Opcode: VCVTh2sq +/* 9697 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9711 +/* 9702 */ MCD_OPC_CheckPredicate, 22, 142, 34, 0, // Skip to: 18553 +/* 9707 */ MCD_OPC_Decode, 231, 9, 126, // Opcode: VCVTh2ud +/* 9711 */ MCD_OPC_FilterValue, 3, 133, 34, 0, // Skip to: 18553 +/* 9716 */ MCD_OPC_CheckPredicate, 22, 128, 34, 0, // Skip to: 18553 +/* 9721 */ MCD_OPC_Decode, 232, 9, 127, // Opcode: VCVTh2uq +/* 9725 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 9789 +/* 9730 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9733 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9747 +/* 9738 */ MCD_OPC_CheckPredicate, 21, 106, 34, 0, // Skip to: 18553 +/* 9743 */ MCD_OPC_Decode, 168, 15, 126, // Opcode: VQABSv2i32 +/* 9747 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9761 +/* 9752 */ MCD_OPC_CheckPredicate, 21, 92, 34, 0, // Skip to: 18553 +/* 9757 */ MCD_OPC_Decode, 170, 15, 127, // Opcode: VQABSv4i32 +/* 9761 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9775 +/* 9766 */ MCD_OPC_CheckPredicate, 21, 78, 34, 0, // Skip to: 18553 +/* 9771 */ MCD_OPC_Decode, 219, 15, 126, // Opcode: VQNEGv2i32 +/* 9775 */ MCD_OPC_FilterValue, 3, 69, 34, 0, // Skip to: 18553 +/* 9780 */ MCD_OPC_CheckPredicate, 21, 64, 34, 0, // Skip to: 18553 +/* 9785 */ MCD_OPC_Decode, 221, 15, 127, // Opcode: VQNEGv4i32 +/* 9789 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 9853 +/* 9794 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9797 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9811 +/* 9802 */ MCD_OPC_CheckPredicate, 21, 42, 34, 0, // Skip to: 18553 +/* 9807 */ MCD_OPC_Decode, 217, 7, 126, // Opcode: VABSfd +/* 9811 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9825 +/* 9816 */ MCD_OPC_CheckPredicate, 21, 28, 34, 0, // Skip to: 18553 +/* 9821 */ MCD_OPC_Decode, 218, 7, 127, // Opcode: VABSfq +/* 9825 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9839 +/* 9830 */ MCD_OPC_CheckPredicate, 21, 14, 34, 0, // Skip to: 18553 +/* 9835 */ MCD_OPC_Decode, 224, 14, 126, // Opcode: VNEGfd +/* 9839 */ MCD_OPC_FilterValue, 3, 5, 34, 0, // Skip to: 18553 +/* 9844 */ MCD_OPC_CheckPredicate, 21, 0, 34, 0, // Skip to: 18553 +/* 9849 */ MCD_OPC_Decode, 223, 14, 127, // Opcode: VNEGf32q +/* 9853 */ MCD_OPC_FilterValue, 11, 247, 33, 0, // Skip to: 18553 +/* 9858 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 9861 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9875 +/* 9866 */ MCD_OPC_CheckPredicate, 21, 234, 33, 0, // Skip to: 18553 +/* 9871 */ MCD_OPC_Decode, 220, 9, 126, // Opcode: VCVTf2sd +/* 9875 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9889 +/* 9880 */ MCD_OPC_CheckPredicate, 21, 220, 33, 0, // Skip to: 18553 +/* 9885 */ MCD_OPC_Decode, 221, 9, 127, // Opcode: VCVTf2sq +/* 9889 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9903 +/* 9894 */ MCD_OPC_CheckPredicate, 21, 206, 33, 0, // Skip to: 18553 +/* 9899 */ MCD_OPC_Decode, 222, 9, 126, // Opcode: VCVTf2ud +/* 9903 */ MCD_OPC_FilterValue, 3, 197, 33, 0, // Skip to: 18553 +/* 9908 */ MCD_OPC_CheckPredicate, 21, 192, 33, 0, // Skip to: 18553 +/* 9913 */ MCD_OPC_Decode, 223, 9, 127, // Opcode: VCVTf2uq +/* 9917 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 9955 +/* 9922 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 9925 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9940 +/* 9930 */ MCD_OPC_CheckPredicate, 21, 170, 33, 0, // Skip to: 18553 +/* 9935 */ MCD_OPC_Decode, 239, 20, 135, 1, // Opcode: VTBL1 +/* 9940 */ MCD_OPC_FilterValue, 1, 160, 33, 0, // Skip to: 18553 +/* 9945 */ MCD_OPC_CheckPredicate, 21, 155, 33, 0, // Skip to: 18553 +/* 9950 */ MCD_OPC_Decode, 245, 20, 135, 1, // Opcode: VTBX1 +/* 9955 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 9993 +/* 9960 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 9963 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9978 +/* 9968 */ MCD_OPC_CheckPredicate, 21, 132, 33, 0, // Skip to: 18553 +/* 9973 */ MCD_OPC_Decode, 240, 20, 135, 1, // Opcode: VTBL2 +/* 9978 */ MCD_OPC_FilterValue, 1, 122, 33, 0, // Skip to: 18553 +/* 9983 */ MCD_OPC_CheckPredicate, 21, 117, 33, 0, // Skip to: 18553 +/* 9988 */ MCD_OPC_Decode, 246, 20, 135, 1, // Opcode: VTBX2 +/* 9993 */ MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 10031 +/* 9998 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 10001 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10016 +/* 10006 */ MCD_OPC_CheckPredicate, 21, 94, 33, 0, // Skip to: 18553 +/* 10011 */ MCD_OPC_Decode, 241, 20, 135, 1, // Opcode: VTBL3 +/* 10016 */ MCD_OPC_FilterValue, 1, 84, 33, 0, // Skip to: 18553 +/* 10021 */ MCD_OPC_CheckPredicate, 21, 79, 33, 0, // Skip to: 18553 +/* 10026 */ MCD_OPC_Decode, 247, 20, 135, 1, // Opcode: VTBX3 +/* 10031 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 10069 +/* 10036 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 10039 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10054 +/* 10044 */ MCD_OPC_CheckPredicate, 21, 56, 33, 0, // Skip to: 18553 +/* 10049 */ MCD_OPC_Decode, 243, 20, 135, 1, // Opcode: VTBL4 +/* 10054 */ MCD_OPC_FilterValue, 1, 46, 33, 0, // Skip to: 18553 +/* 10059 */ MCD_OPC_CheckPredicate, 21, 41, 33, 0, // Skip to: 18553 +/* 10064 */ MCD_OPC_Decode, 249, 20, 135, 1, // Opcode: VTBX4 +/* 10069 */ MCD_OPC_FilterValue, 12, 31, 33, 0, // Skip to: 18553 +/* 10074 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 10077 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 10145 +/* 10082 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 10085 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 10130 +/* 10090 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 10093 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 10115 +/* 10098 */ MCD_OPC_CheckPredicate, 21, 2, 33, 0, // Skip to: 18553 +/* 10103 */ MCD_OPC_CheckField, 18, 1, 1, 251, 32, 0, // Skip to: 18553 +/* 10110 */ MCD_OPC_Decode, 136, 10, 136, 1, // Opcode: VDUPLN32d +/* 10115 */ MCD_OPC_FilterValue, 1, 241, 32, 0, // Skip to: 18553 +/* 10120 */ MCD_OPC_CheckPredicate, 21, 236, 32, 0, // Skip to: 18553 +/* 10125 */ MCD_OPC_Decode, 134, 10, 137, 1, // Opcode: VDUPLN16d +/* 10130 */ MCD_OPC_FilterValue, 1, 226, 32, 0, // Skip to: 18553 +/* 10135 */ MCD_OPC_CheckPredicate, 21, 221, 32, 0, // Skip to: 18553 +/* 10140 */ MCD_OPC_Decode, 138, 10, 138, 1, // Opcode: VDUPLN8d +/* 10145 */ MCD_OPC_FilterValue, 1, 211, 32, 0, // Skip to: 18553 +/* 10150 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 10153 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 10198 +/* 10158 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 10161 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 10183 +/* 10166 */ MCD_OPC_CheckPredicate, 21, 190, 32, 0, // Skip to: 18553 +/* 10171 */ MCD_OPC_CheckField, 18, 1, 1, 183, 32, 0, // Skip to: 18553 +/* 10178 */ MCD_OPC_Decode, 137, 10, 139, 1, // Opcode: VDUPLN32q +/* 10183 */ MCD_OPC_FilterValue, 1, 173, 32, 0, // Skip to: 18553 +/* 10188 */ MCD_OPC_CheckPredicate, 21, 168, 32, 0, // Skip to: 18553 +/* 10193 */ MCD_OPC_Decode, 135, 10, 140, 1, // Opcode: VDUPLN16q +/* 10198 */ MCD_OPC_FilterValue, 1, 158, 32, 0, // Skip to: 18553 +/* 10203 */ MCD_OPC_CheckPredicate, 21, 153, 32, 0, // Skip to: 18553 +/* 10208 */ MCD_OPC_Decode, 139, 10, 141, 1, // Opcode: VDUPLN8q +/* 10213 */ MCD_OPC_FilterValue, 1, 143, 32, 0, // Skip to: 18553 +/* 10218 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 10221 */ MCD_OPC_FilterValue, 0, 21, 17, 0, // Skip to: 14599 +/* 10226 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 10229 */ MCD_OPC_FilterValue, 0, 9, 8, 0, // Skip to: 12291 +/* 10234 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 10237 */ MCD_OPC_FilterValue, 0, 155, 0, 0, // Skip to: 10397 +/* 10242 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 10245 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10283 +/* 10250 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10253 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10268 +/* 10259 */ MCD_OPC_CheckPredicate, 21, 97, 32, 0, // Skip to: 18553 +/* 10264 */ MCD_OPC_Decode, 180, 15, 97, // Opcode: VQADDsv8i8 +/* 10268 */ MCD_OPC_FilterValue, 243, 1, 87, 32, 0, // Skip to: 18553 +/* 10274 */ MCD_OPC_CheckPredicate, 21, 82, 32, 0, // Skip to: 18553 +/* 10279 */ MCD_OPC_Decode, 188, 15, 97, // Opcode: VQADDuv8i8 +/* 10283 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10321 +/* 10288 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10291 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10306 +/* 10297 */ MCD_OPC_CheckPredicate, 21, 59, 32, 0, // Skip to: 18553 +/* 10302 */ MCD_OPC_Decode, 177, 15, 97, // Opcode: VQADDsv4i16 +/* 10306 */ MCD_OPC_FilterValue, 243, 1, 49, 32, 0, // Skip to: 18553 +/* 10312 */ MCD_OPC_CheckPredicate, 21, 44, 32, 0, // Skip to: 18553 +/* 10317 */ MCD_OPC_Decode, 185, 15, 97, // Opcode: VQADDuv4i16 +/* 10321 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10359 +/* 10326 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10329 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10344 +/* 10335 */ MCD_OPC_CheckPredicate, 21, 21, 32, 0, // Skip to: 18553 +/* 10340 */ MCD_OPC_Decode, 175, 15, 97, // Opcode: VQADDsv2i32 +/* 10344 */ MCD_OPC_FilterValue, 243, 1, 11, 32, 0, // Skip to: 18553 +/* 10350 */ MCD_OPC_CheckPredicate, 21, 6, 32, 0, // Skip to: 18553 +/* 10355 */ MCD_OPC_Decode, 183, 15, 97, // Opcode: VQADDuv2i32 +/* 10359 */ MCD_OPC_FilterValue, 3, 253, 31, 0, // Skip to: 18553 +/* 10364 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10367 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10382 +/* 10373 */ MCD_OPC_CheckPredicate, 21, 239, 31, 0, // Skip to: 18553 +/* 10378 */ MCD_OPC_Decode, 174, 15, 97, // Opcode: VQADDsv1i64 +/* 10382 */ MCD_OPC_FilterValue, 243, 1, 229, 31, 0, // Skip to: 18553 +/* 10388 */ MCD_OPC_CheckPredicate, 21, 224, 31, 0, // Skip to: 18553 +/* 10393 */ MCD_OPC_Decode, 182, 15, 97, // Opcode: VQADDuv1i64 +/* 10397 */ MCD_OPC_FilterValue, 1, 155, 0, 0, // Skip to: 10557 +/* 10402 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 10405 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10443 +/* 10410 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10413 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10428 +/* 10419 */ MCD_OPC_CheckPredicate, 21, 193, 31, 0, // Skip to: 18553 +/* 10424 */ MCD_OPC_Decode, 137, 8, 97, // Opcode: VANDd +/* 10428 */ MCD_OPC_FilterValue, 243, 1, 183, 31, 0, // Skip to: 18553 +/* 10434 */ MCD_OPC_CheckPredicate, 21, 178, 31, 0, // Skip to: 18553 +/* 10439 */ MCD_OPC_Decode, 140, 10, 97, // Opcode: VEORd +/* 10443 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10481 +/* 10448 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10451 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10466 +/* 10457 */ MCD_OPC_CheckPredicate, 21, 155, 31, 0, // Skip to: 18553 +/* 10462 */ MCD_OPC_Decode, 139, 8, 97, // Opcode: VBICd +/* 10466 */ MCD_OPC_FilterValue, 243, 1, 145, 31, 0, // Skip to: 18553 +/* 10472 */ MCD_OPC_CheckPredicate, 21, 140, 31, 0, // Skip to: 18553 +/* 10477 */ MCD_OPC_Decode, 149, 8, 105, // Opcode: VBSLd +/* 10481 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10519 +/* 10486 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10489 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10504 +/* 10495 */ MCD_OPC_CheckPredicate, 21, 117, 31, 0, // Skip to: 18553 +/* 10500 */ MCD_OPC_Decode, 244, 14, 97, // Opcode: VORRd +/* 10504 */ MCD_OPC_FilterValue, 243, 1, 107, 31, 0, // Skip to: 18553 +/* 10510 */ MCD_OPC_CheckPredicate, 21, 102, 31, 0, // Skip to: 18553 +/* 10515 */ MCD_OPC_Decode, 147, 8, 105, // Opcode: VBITd +/* 10519 */ MCD_OPC_FilterValue, 3, 93, 31, 0, // Skip to: 18553 +/* 10524 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10527 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10542 +/* 10533 */ MCD_OPC_CheckPredicate, 21, 79, 31, 0, // Skip to: 18553 +/* 10538 */ MCD_OPC_Decode, 242, 14, 97, // Opcode: VORNd +/* 10542 */ MCD_OPC_FilterValue, 243, 1, 69, 31, 0, // Skip to: 18553 +/* 10548 */ MCD_OPC_CheckPredicate, 21, 64, 31, 0, // Skip to: 18553 +/* 10553 */ MCD_OPC_Decode, 145, 8, 105, // Opcode: VBIFd +/* 10557 */ MCD_OPC_FilterValue, 2, 155, 0, 0, // Skip to: 10717 +/* 10562 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 10565 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10603 +/* 10570 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10573 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10588 +/* 10579 */ MCD_OPC_CheckPredicate, 21, 33, 31, 0, // Skip to: 18553 +/* 10584 */ MCD_OPC_Decode, 201, 16, 97, // Opcode: VQSUBsv8i8 +/* 10588 */ MCD_OPC_FilterValue, 243, 1, 23, 31, 0, // Skip to: 18553 +/* 10594 */ MCD_OPC_CheckPredicate, 21, 18, 31, 0, // Skip to: 18553 +/* 10599 */ MCD_OPC_Decode, 209, 16, 97, // Opcode: VQSUBuv8i8 +/* 10603 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10641 +/* 10608 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10611 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10626 +/* 10617 */ MCD_OPC_CheckPredicate, 21, 251, 30, 0, // Skip to: 18553 +/* 10622 */ MCD_OPC_Decode, 198, 16, 97, // Opcode: VQSUBsv4i16 +/* 10626 */ MCD_OPC_FilterValue, 243, 1, 241, 30, 0, // Skip to: 18553 +/* 10632 */ MCD_OPC_CheckPredicate, 21, 236, 30, 0, // Skip to: 18553 +/* 10637 */ MCD_OPC_Decode, 206, 16, 97, // Opcode: VQSUBuv4i16 +/* 10641 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10679 +/* 10646 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10649 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10664 +/* 10655 */ MCD_OPC_CheckPredicate, 21, 213, 30, 0, // Skip to: 18553 +/* 10660 */ MCD_OPC_Decode, 196, 16, 97, // Opcode: VQSUBsv2i32 +/* 10664 */ MCD_OPC_FilterValue, 243, 1, 203, 30, 0, // Skip to: 18553 +/* 10670 */ MCD_OPC_CheckPredicate, 21, 198, 30, 0, // Skip to: 18553 +/* 10675 */ MCD_OPC_Decode, 204, 16, 97, // Opcode: VQSUBuv2i32 +/* 10679 */ MCD_OPC_FilterValue, 3, 189, 30, 0, // Skip to: 18553 +/* 10684 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10687 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10702 +/* 10693 */ MCD_OPC_CheckPredicate, 21, 175, 30, 0, // Skip to: 18553 +/* 10698 */ MCD_OPC_Decode, 195, 16, 97, // Opcode: VQSUBsv1i64 +/* 10702 */ MCD_OPC_FilterValue, 243, 1, 165, 30, 0, // Skip to: 18553 +/* 10708 */ MCD_OPC_CheckPredicate, 21, 160, 30, 0, // Skip to: 18553 +/* 10713 */ MCD_OPC_Decode, 203, 16, 97, // Opcode: VQSUBuv1i64 +/* 10717 */ MCD_OPC_FilterValue, 3, 117, 0, 0, // Skip to: 10839 +/* 10722 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 10725 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10763 +/* 10730 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10733 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10748 +/* 10739 */ MCD_OPC_CheckPredicate, 21, 129, 30, 0, // Skip to: 18553 +/* 10744 */ MCD_OPC_Decode, 184, 8, 97, // Opcode: VCGEsv8i8 +/* 10748 */ MCD_OPC_FilterValue, 243, 1, 119, 30, 0, // Skip to: 18553 +/* 10754 */ MCD_OPC_CheckPredicate, 21, 114, 30, 0, // Skip to: 18553 +/* 10759 */ MCD_OPC_Decode, 190, 8, 97, // Opcode: VCGEuv8i8 +/* 10763 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10801 +/* 10768 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10771 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10786 +/* 10777 */ MCD_OPC_CheckPredicate, 21, 91, 30, 0, // Skip to: 18553 +/* 10782 */ MCD_OPC_Decode, 181, 8, 97, // Opcode: VCGEsv4i16 +/* 10786 */ MCD_OPC_FilterValue, 243, 1, 81, 30, 0, // Skip to: 18553 +/* 10792 */ MCD_OPC_CheckPredicate, 21, 76, 30, 0, // Skip to: 18553 +/* 10797 */ MCD_OPC_Decode, 187, 8, 97, // Opcode: VCGEuv4i16 +/* 10801 */ MCD_OPC_FilterValue, 2, 67, 30, 0, // Skip to: 18553 +/* 10806 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10809 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10824 +/* 10815 */ MCD_OPC_CheckPredicate, 21, 53, 30, 0, // Skip to: 18553 +/* 10820 */ MCD_OPC_Decode, 180, 8, 97, // Opcode: VCGEsv2i32 +/* 10824 */ MCD_OPC_FilterValue, 243, 1, 43, 30, 0, // Skip to: 18553 +/* 10830 */ MCD_OPC_CheckPredicate, 21, 38, 30, 0, // Skip to: 18553 +/* 10835 */ MCD_OPC_Decode, 186, 8, 97, // Opcode: VCGEuv2i32 +/* 10839 */ MCD_OPC_FilterValue, 4, 155, 0, 0, // Skip to: 10999 +/* 10844 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 10847 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10885 +/* 10852 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10855 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10870 +/* 10861 */ MCD_OPC_CheckPredicate, 21, 7, 30, 0, // Skip to: 18553 +/* 10866 */ MCD_OPC_Decode, 168, 16, 101, // Opcode: VQSHLsv8i8 +/* 10870 */ MCD_OPC_FilterValue, 243, 1, 253, 29, 0, // Skip to: 18553 +/* 10876 */ MCD_OPC_CheckPredicate, 21, 248, 29, 0, // Skip to: 18553 +/* 10881 */ MCD_OPC_Decode, 184, 16, 101, // Opcode: VQSHLuv8i8 +/* 10885 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10923 +/* 10890 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10893 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10908 +/* 10899 */ MCD_OPC_CheckPredicate, 21, 225, 29, 0, // Skip to: 18553 +/* 10904 */ MCD_OPC_Decode, 165, 16, 101, // Opcode: VQSHLsv4i16 +/* 10908 */ MCD_OPC_FilterValue, 243, 1, 215, 29, 0, // Skip to: 18553 +/* 10914 */ MCD_OPC_CheckPredicate, 21, 210, 29, 0, // Skip to: 18553 +/* 10919 */ MCD_OPC_Decode, 181, 16, 101, // Opcode: VQSHLuv4i16 +/* 10923 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10961 +/* 10928 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10931 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10946 +/* 10937 */ MCD_OPC_CheckPredicate, 21, 187, 29, 0, // Skip to: 18553 +/* 10942 */ MCD_OPC_Decode, 163, 16, 101, // Opcode: VQSHLsv2i32 +/* 10946 */ MCD_OPC_FilterValue, 243, 1, 177, 29, 0, // Skip to: 18553 +/* 10952 */ MCD_OPC_CheckPredicate, 21, 172, 29, 0, // Skip to: 18553 +/* 10957 */ MCD_OPC_Decode, 179, 16, 101, // Opcode: VQSHLuv2i32 +/* 10961 */ MCD_OPC_FilterValue, 3, 163, 29, 0, // Skip to: 18553 +/* 10966 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 10969 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10984 +/* 10975 */ MCD_OPC_CheckPredicate, 21, 149, 29, 0, // Skip to: 18553 +/* 10980 */ MCD_OPC_Decode, 162, 16, 101, // Opcode: VQSHLsv1i64 +/* 10984 */ MCD_OPC_FilterValue, 243, 1, 139, 29, 0, // Skip to: 18553 +/* 10990 */ MCD_OPC_CheckPredicate, 21, 134, 29, 0, // Skip to: 18553 +/* 10995 */ MCD_OPC_Decode, 178, 16, 101, // Opcode: VQSHLuv1i64 +/* 10999 */ MCD_OPC_FilterValue, 5, 155, 0, 0, // Skip to: 11159 +/* 11004 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11007 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11045 +/* 11012 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11015 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11030 +/* 11021 */ MCD_OPC_CheckPredicate, 21, 103, 29, 0, // Skip to: 18553 +/* 11026 */ MCD_OPC_Decode, 255, 15, 101, // Opcode: VQRSHLsv8i8 +/* 11030 */ MCD_OPC_FilterValue, 243, 1, 93, 29, 0, // Skip to: 18553 +/* 11036 */ MCD_OPC_CheckPredicate, 21, 88, 29, 0, // Skip to: 18553 +/* 11041 */ MCD_OPC_Decode, 135, 16, 101, // Opcode: VQRSHLuv8i8 +/* 11045 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11083 +/* 11050 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11053 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11068 +/* 11059 */ MCD_OPC_CheckPredicate, 21, 65, 29, 0, // Skip to: 18553 +/* 11064 */ MCD_OPC_Decode, 252, 15, 101, // Opcode: VQRSHLsv4i16 +/* 11068 */ MCD_OPC_FilterValue, 243, 1, 55, 29, 0, // Skip to: 18553 +/* 11074 */ MCD_OPC_CheckPredicate, 21, 50, 29, 0, // Skip to: 18553 +/* 11079 */ MCD_OPC_Decode, 132, 16, 101, // Opcode: VQRSHLuv4i16 +/* 11083 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 11121 +/* 11088 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11091 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11106 +/* 11097 */ MCD_OPC_CheckPredicate, 21, 27, 29, 0, // Skip to: 18553 +/* 11102 */ MCD_OPC_Decode, 250, 15, 101, // Opcode: VQRSHLsv2i32 +/* 11106 */ MCD_OPC_FilterValue, 243, 1, 17, 29, 0, // Skip to: 18553 +/* 11112 */ MCD_OPC_CheckPredicate, 21, 12, 29, 0, // Skip to: 18553 +/* 11117 */ MCD_OPC_Decode, 130, 16, 101, // Opcode: VQRSHLuv2i32 +/* 11121 */ MCD_OPC_FilterValue, 3, 3, 29, 0, // Skip to: 18553 +/* 11126 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11129 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11144 +/* 11135 */ MCD_OPC_CheckPredicate, 21, 245, 28, 0, // Skip to: 18553 +/* 11140 */ MCD_OPC_Decode, 249, 15, 101, // Opcode: VQRSHLsv1i64 +/* 11144 */ MCD_OPC_FilterValue, 243, 1, 235, 28, 0, // Skip to: 18553 +/* 11150 */ MCD_OPC_CheckPredicate, 21, 230, 28, 0, // Skip to: 18553 +/* 11155 */ MCD_OPC_Decode, 129, 16, 101, // Opcode: VQRSHLuv1i64 +/* 11159 */ MCD_OPC_FilterValue, 6, 117, 0, 0, // Skip to: 11281 +/* 11164 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11167 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11205 +/* 11172 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11175 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11190 +/* 11181 */ MCD_OPC_CheckPredicate, 21, 199, 28, 0, // Skip to: 18553 +/* 11186 */ MCD_OPC_Decode, 195, 13, 97, // Opcode: VMINsv8i8 +/* 11190 */ MCD_OPC_FilterValue, 243, 1, 189, 28, 0, // Skip to: 18553 +/* 11196 */ MCD_OPC_CheckPredicate, 21, 184, 28, 0, // Skip to: 18553 +/* 11201 */ MCD_OPC_Decode, 201, 13, 97, // Opcode: VMINuv8i8 +/* 11205 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11243 +/* 11210 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11213 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11228 +/* 11219 */ MCD_OPC_CheckPredicate, 21, 161, 28, 0, // Skip to: 18553 +/* 11224 */ MCD_OPC_Decode, 192, 13, 97, // Opcode: VMINsv4i16 +/* 11228 */ MCD_OPC_FilterValue, 243, 1, 151, 28, 0, // Skip to: 18553 +/* 11234 */ MCD_OPC_CheckPredicate, 21, 146, 28, 0, // Skip to: 18553 +/* 11239 */ MCD_OPC_Decode, 198, 13, 97, // Opcode: VMINuv4i16 +/* 11243 */ MCD_OPC_FilterValue, 2, 137, 28, 0, // Skip to: 18553 +/* 11248 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11251 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11266 +/* 11257 */ MCD_OPC_CheckPredicate, 21, 123, 28, 0, // Skip to: 18553 +/* 11262 */ MCD_OPC_Decode, 191, 13, 97, // Opcode: VMINsv2i32 +/* 11266 */ MCD_OPC_FilterValue, 243, 1, 113, 28, 0, // Skip to: 18553 +/* 11272 */ MCD_OPC_CheckPredicate, 21, 108, 28, 0, // Skip to: 18553 +/* 11277 */ MCD_OPC_Decode, 197, 13, 97, // Opcode: VMINuv2i32 +/* 11281 */ MCD_OPC_FilterValue, 7, 117, 0, 0, // Skip to: 11403 +/* 11286 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11289 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11327 +/* 11294 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11297 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11312 +/* 11303 */ MCD_OPC_CheckPredicate, 21, 77, 28, 0, // Skip to: 18553 +/* 11308 */ MCD_OPC_Decode, 185, 7, 105, // Opcode: VABAsv8i8 +/* 11312 */ MCD_OPC_FilterValue, 243, 1, 67, 28, 0, // Skip to: 18553 +/* 11318 */ MCD_OPC_CheckPredicate, 21, 62, 28, 0, // Skip to: 18553 +/* 11323 */ MCD_OPC_Decode, 191, 7, 105, // Opcode: VABAuv8i8 +/* 11327 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11365 +/* 11332 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11335 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11350 +/* 11341 */ MCD_OPC_CheckPredicate, 21, 39, 28, 0, // Skip to: 18553 +/* 11346 */ MCD_OPC_Decode, 182, 7, 105, // Opcode: VABAsv4i16 +/* 11350 */ MCD_OPC_FilterValue, 243, 1, 29, 28, 0, // Skip to: 18553 +/* 11356 */ MCD_OPC_CheckPredicate, 21, 24, 28, 0, // Skip to: 18553 +/* 11361 */ MCD_OPC_Decode, 188, 7, 105, // Opcode: VABAuv4i16 +/* 11365 */ MCD_OPC_FilterValue, 2, 15, 28, 0, // Skip to: 18553 +/* 11370 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11373 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11388 +/* 11379 */ MCD_OPC_CheckPredicate, 21, 1, 28, 0, // Skip to: 18553 +/* 11384 */ MCD_OPC_Decode, 181, 7, 105, // Opcode: VABAsv2i32 +/* 11388 */ MCD_OPC_FilterValue, 243, 1, 247, 27, 0, // Skip to: 18553 +/* 11394 */ MCD_OPC_CheckPredicate, 21, 242, 27, 0, // Skip to: 18553 +/* 11399 */ MCD_OPC_Decode, 187, 7, 105, // Opcode: VABAuv2i32 +/* 11403 */ MCD_OPC_FilterValue, 8, 117, 0, 0, // Skip to: 11525 +/* 11408 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11411 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11449 +/* 11416 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11419 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11434 +/* 11425 */ MCD_OPC_CheckPredicate, 21, 211, 27, 0, // Skip to: 18553 +/* 11430 */ MCD_OPC_Decode, 158, 21, 97, // Opcode: VTSTv8i8 +/* 11434 */ MCD_OPC_FilterValue, 243, 1, 201, 27, 0, // Skip to: 18553 +/* 11440 */ MCD_OPC_CheckPredicate, 21, 196, 27, 0, // Skip to: 18553 +/* 11445 */ MCD_OPC_Decode, 164, 8, 97, // Opcode: VCEQv8i8 +/* 11449 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11487 +/* 11454 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11457 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11472 +/* 11463 */ MCD_OPC_CheckPredicate, 21, 173, 27, 0, // Skip to: 18553 +/* 11468 */ MCD_OPC_Decode, 155, 21, 97, // Opcode: VTSTv4i16 +/* 11472 */ MCD_OPC_FilterValue, 243, 1, 163, 27, 0, // Skip to: 18553 +/* 11478 */ MCD_OPC_CheckPredicate, 21, 158, 27, 0, // Skip to: 18553 +/* 11483 */ MCD_OPC_Decode, 161, 8, 97, // Opcode: VCEQv4i16 +/* 11487 */ MCD_OPC_FilterValue, 2, 149, 27, 0, // Skip to: 18553 +/* 11492 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11495 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11510 +/* 11501 */ MCD_OPC_CheckPredicate, 21, 135, 27, 0, // Skip to: 18553 +/* 11506 */ MCD_OPC_Decode, 154, 21, 97, // Opcode: VTSTv2i32 +/* 11510 */ MCD_OPC_FilterValue, 243, 1, 125, 27, 0, // Skip to: 18553 +/* 11516 */ MCD_OPC_CheckPredicate, 21, 120, 27, 0, // Skip to: 18553 +/* 11521 */ MCD_OPC_Decode, 160, 8, 97, // Opcode: VCEQv2i32 +/* 11525 */ MCD_OPC_FilterValue, 9, 85, 0, 0, // Skip to: 11615 +/* 11530 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11533 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11571 +/* 11538 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11541 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11556 +/* 11547 */ MCD_OPC_CheckPredicate, 21, 89, 27, 0, // Skip to: 18553 +/* 11552 */ MCD_OPC_Decode, 213, 14, 97, // Opcode: VMULv8i8 +/* 11556 */ MCD_OPC_FilterValue, 243, 1, 79, 27, 0, // Skip to: 18553 +/* 11562 */ MCD_OPC_CheckPredicate, 21, 74, 27, 0, // Skip to: 18553 +/* 11567 */ MCD_OPC_Decode, 198, 14, 97, // Opcode: VMULpd +/* 11571 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 11593 +/* 11576 */ MCD_OPC_CheckPredicate, 21, 60, 27, 0, // Skip to: 18553 +/* 11581 */ MCD_OPC_CheckField, 24, 8, 242, 1, 52, 27, 0, // Skip to: 18553 +/* 11589 */ MCD_OPC_Decode, 210, 14, 97, // Opcode: VMULv4i16 +/* 11593 */ MCD_OPC_FilterValue, 2, 43, 27, 0, // Skip to: 18553 +/* 11598 */ MCD_OPC_CheckPredicate, 21, 38, 27, 0, // Skip to: 18553 +/* 11603 */ MCD_OPC_CheckField, 24, 8, 242, 1, 30, 27, 0, // Skip to: 18553 +/* 11611 */ MCD_OPC_Decode, 209, 14, 97, // Opcode: VMULv2i32 +/* 11615 */ MCD_OPC_FilterValue, 10, 117, 0, 0, // Skip to: 11737 +/* 11620 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11623 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11661 +/* 11628 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11631 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11646 +/* 11637 */ MCD_OPC_CheckPredicate, 21, 255, 26, 0, // Skip to: 18553 +/* 11642 */ MCD_OPC_Decode, 163, 15, 97, // Opcode: VPMINs8 +/* 11646 */ MCD_OPC_FilterValue, 243, 1, 245, 26, 0, // Skip to: 18553 +/* 11652 */ MCD_OPC_CheckPredicate, 21, 240, 26, 0, // Skip to: 18553 +/* 11657 */ MCD_OPC_Decode, 166, 15, 97, // Opcode: VPMINu8 +/* 11661 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11699 +/* 11666 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11669 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11684 +/* 11675 */ MCD_OPC_CheckPredicate, 21, 217, 26, 0, // Skip to: 18553 +/* 11680 */ MCD_OPC_Decode, 161, 15, 97, // Opcode: VPMINs16 +/* 11684 */ MCD_OPC_FilterValue, 243, 1, 207, 26, 0, // Skip to: 18553 +/* 11690 */ MCD_OPC_CheckPredicate, 21, 202, 26, 0, // Skip to: 18553 +/* 11695 */ MCD_OPC_Decode, 164, 15, 97, // Opcode: VPMINu16 +/* 11699 */ MCD_OPC_FilterValue, 2, 193, 26, 0, // Skip to: 18553 +/* 11704 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11707 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11722 +/* 11713 */ MCD_OPC_CheckPredicate, 21, 179, 26, 0, // Skip to: 18553 +/* 11718 */ MCD_OPC_Decode, 162, 15, 97, // Opcode: VPMINs32 +/* 11722 */ MCD_OPC_FilterValue, 243, 1, 169, 26, 0, // Skip to: 18553 +/* 11728 */ MCD_OPC_CheckPredicate, 21, 164, 26, 0, // Skip to: 18553 +/* 11733 */ MCD_OPC_Decode, 165, 15, 97, // Opcode: VPMINu32 +/* 11737 */ MCD_OPC_FilterValue, 11, 101, 0, 0, // Skip to: 11843 +/* 11742 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11745 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11767 +/* 11750 */ MCD_OPC_CheckPredicate, 21, 142, 26, 0, // Skip to: 18553 +/* 11755 */ MCD_OPC_CheckField, 24, 8, 242, 1, 134, 26, 0, // Skip to: 18553 +/* 11763 */ MCD_OPC_Decode, 150, 15, 97, // Opcode: VPADDi8 +/* 11767 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11805 +/* 11772 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11775 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11790 +/* 11781 */ MCD_OPC_CheckPredicate, 21, 111, 26, 0, // Skip to: 18553 +/* 11786 */ MCD_OPC_Decode, 148, 15, 97, // Opcode: VPADDi16 +/* 11790 */ MCD_OPC_FilterValue, 243, 1, 101, 26, 0, // Skip to: 18553 +/* 11796 */ MCD_OPC_CheckPredicate, 23, 96, 26, 0, // Skip to: 18553 +/* 11801 */ MCD_OPC_Decode, 229, 15, 105, // Opcode: VQRDMLAHv4i16 +/* 11805 */ MCD_OPC_FilterValue, 2, 87, 26, 0, // Skip to: 18553 +/* 11810 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11813 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11828 +/* 11819 */ MCD_OPC_CheckPredicate, 21, 73, 26, 0, // Skip to: 18553 +/* 11824 */ MCD_OPC_Decode, 149, 15, 97, // Opcode: VPADDi32 +/* 11828 */ MCD_OPC_FilterValue, 243, 1, 63, 26, 0, // Skip to: 18553 +/* 11834 */ MCD_OPC_CheckPredicate, 23, 58, 26, 0, // Skip to: 18553 +/* 11839 */ MCD_OPC_Decode, 228, 15, 105, // Opcode: VQRDMLAHv2i32 +/* 11843 */ MCD_OPC_FilterValue, 12, 123, 0, 0, // Skip to: 11971 +/* 11848 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11851 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11873 +/* 11856 */ MCD_OPC_CheckPredicate, 26, 36, 26, 0, // Skip to: 18553 +/* 11861 */ MCD_OPC_CheckField, 24, 8, 242, 1, 28, 26, 0, // Skip to: 18553 +/* 11869 */ MCD_OPC_Decode, 152, 10, 105, // Opcode: VFMAfd +/* 11873 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11911 +/* 11878 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11881 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11896 +/* 11887 */ MCD_OPC_CheckPredicate, 22, 5, 26, 0, // Skip to: 18553 +/* 11892 */ MCD_OPC_Decode, 154, 10, 105, // Opcode: VFMAhd +/* 11896 */ MCD_OPC_FilterValue, 243, 1, 251, 25, 0, // Skip to: 18553 +/* 11902 */ MCD_OPC_CheckPredicate, 23, 246, 25, 0, // Skip to: 18553 +/* 11907 */ MCD_OPC_Decode, 237, 15, 105, // Opcode: VQRDMLSHv4i16 +/* 11911 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 11949 +/* 11916 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11919 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11934 +/* 11925 */ MCD_OPC_CheckPredicate, 26, 223, 25, 0, // Skip to: 18553 +/* 11930 */ MCD_OPC_Decode, 159, 10, 105, // Opcode: VFMSfd +/* 11934 */ MCD_OPC_FilterValue, 243, 1, 213, 25, 0, // Skip to: 18553 +/* 11940 */ MCD_OPC_CheckPredicate, 23, 208, 25, 0, // Skip to: 18553 +/* 11945 */ MCD_OPC_Decode, 236, 15, 105, // Opcode: VQRDMLSHv2i32 +/* 11949 */ MCD_OPC_FilterValue, 3, 199, 25, 0, // Skip to: 18553 +/* 11954 */ MCD_OPC_CheckPredicate, 22, 194, 25, 0, // Skip to: 18553 +/* 11959 */ MCD_OPC_CheckField, 24, 8, 242, 1, 186, 25, 0, // Skip to: 18553 +/* 11967 */ MCD_OPC_Decode, 161, 10, 105, // Opcode: VFMShd +/* 11971 */ MCD_OPC_FilterValue, 13, 123, 0, 0, // Skip to: 12099 +/* 11976 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11979 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 12017 +/* 11984 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 11987 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 12002 +/* 11993 */ MCD_OPC_CheckPredicate, 21, 155, 25, 0, // Skip to: 18553 +/* 11998 */ MCD_OPC_Decode, 215, 13, 105, // Opcode: VMLAfd +/* 12002 */ MCD_OPC_FilterValue, 243, 1, 145, 25, 0, // Skip to: 18553 +/* 12008 */ MCD_OPC_CheckPredicate, 21, 140, 25, 0, // Skip to: 18553 +/* 12013 */ MCD_OPC_Decode, 194, 14, 97, // Opcode: VMULfd +/* 12017 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 12055 +/* 12022 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 12025 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 12040 +/* 12031 */ MCD_OPC_CheckPredicate, 22, 117, 25, 0, // Skip to: 18553 +/* 12036 */ MCD_OPC_Decode, 217, 13, 105, // Opcode: VMLAhd +/* 12040 */ MCD_OPC_FilterValue, 243, 1, 107, 25, 0, // Skip to: 18553 +/* 12046 */ MCD_OPC_CheckPredicate, 22, 102, 25, 0, // Skip to: 18553 +/* 12051 */ MCD_OPC_Decode, 196, 14, 97, // Opcode: VMULhd +/* 12055 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12077 +/* 12060 */ MCD_OPC_CheckPredicate, 21, 88, 25, 0, // Skip to: 18553 +/* 12065 */ MCD_OPC_CheckField, 24, 8, 242, 1, 80, 25, 0, // Skip to: 18553 +/* 12073 */ MCD_OPC_Decode, 246, 13, 105, // Opcode: VMLSfd +/* 12077 */ MCD_OPC_FilterValue, 3, 71, 25, 0, // Skip to: 18553 +/* 12082 */ MCD_OPC_CheckPredicate, 22, 66, 25, 0, // Skip to: 18553 +/* 12087 */ MCD_OPC_CheckField, 24, 8, 242, 1, 58, 25, 0, // Skip to: 18553 +/* 12095 */ MCD_OPC_Decode, 248, 13, 105, // Opcode: VMLShd +/* 12099 */ MCD_OPC_FilterValue, 14, 91, 0, 0, // Skip to: 12195 +/* 12104 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 12107 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12129 +/* 12112 */ MCD_OPC_CheckPredicate, 21, 36, 25, 0, // Skip to: 18553 +/* 12117 */ MCD_OPC_CheckField, 24, 8, 243, 1, 28, 25, 0, // Skip to: 18553 +/* 12125 */ MCD_OPC_Decode, 227, 7, 97, // Opcode: VACGEfd +/* 12129 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 12151 +/* 12134 */ MCD_OPC_CheckPredicate, 22, 14, 25, 0, // Skip to: 18553 +/* 12139 */ MCD_OPC_CheckField, 24, 8, 243, 1, 6, 25, 0, // Skip to: 18553 +/* 12147 */ MCD_OPC_Decode, 229, 7, 97, // Opcode: VACGEhd +/* 12151 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12173 +/* 12156 */ MCD_OPC_CheckPredicate, 21, 248, 24, 0, // Skip to: 18553 +/* 12161 */ MCD_OPC_CheckField, 24, 8, 243, 1, 240, 24, 0, // Skip to: 18553 +/* 12169 */ MCD_OPC_Decode, 231, 7, 97, // Opcode: VACGTfd +/* 12173 */ MCD_OPC_FilterValue, 3, 231, 24, 0, // Skip to: 18553 +/* 12178 */ MCD_OPC_CheckPredicate, 22, 226, 24, 0, // Skip to: 18553 +/* 12183 */ MCD_OPC_CheckField, 24, 8, 243, 1, 218, 24, 0, // Skip to: 18553 +/* 12191 */ MCD_OPC_Decode, 233, 7, 97, // Opcode: VACGThd +/* 12195 */ MCD_OPC_FilterValue, 15, 209, 24, 0, // Skip to: 18553 +/* 12200 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 12203 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12225 +/* 12208 */ MCD_OPC_CheckPredicate, 21, 196, 24, 0, // Skip to: 18553 +/* 12213 */ MCD_OPC_CheckField, 24, 8, 242, 1, 188, 24, 0, // Skip to: 18553 +/* 12221 */ MCD_OPC_Decode, 219, 16, 97, // Opcode: VRECPSfd +/* 12225 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 12247 +/* 12230 */ MCD_OPC_CheckPredicate, 22, 174, 24, 0, // Skip to: 18553 +/* 12235 */ MCD_OPC_CheckField, 24, 8, 242, 1, 166, 24, 0, // Skip to: 18553 +/* 12243 */ MCD_OPC_Decode, 221, 16, 97, // Opcode: VRECPShd +/* 12247 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12269 +/* 12252 */ MCD_OPC_CheckPredicate, 21, 152, 24, 0, // Skip to: 18553 +/* 12257 */ MCD_OPC_CheckField, 24, 8, 242, 1, 144, 24, 0, // Skip to: 18553 +/* 12265 */ MCD_OPC_Decode, 205, 17, 97, // Opcode: VRSQRTSfd +/* 12269 */ MCD_OPC_FilterValue, 3, 135, 24, 0, // Skip to: 18553 +/* 12274 */ MCD_OPC_CheckPredicate, 22, 130, 24, 0, // Skip to: 18553 +/* 12279 */ MCD_OPC_CheckField, 24, 8, 242, 1, 122, 24, 0, // Skip to: 18553 +/* 12287 */ MCD_OPC_Decode, 207, 17, 97, // Opcode: VRSQRTShd +/* 12291 */ MCD_OPC_FilterValue, 1, 113, 24, 0, // Skip to: 18553 +/* 12296 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 12299 */ MCD_OPC_FilterValue, 0, 209, 7, 0, // Skip to: 14305 +/* 12304 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... +/* 12307 */ MCD_OPC_FilterValue, 121, 97, 24, 0, // Skip to: 18553 +/* 12312 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 12315 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 12459 +/* 12320 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 12323 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12421 +/* 12328 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 12331 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12383 +/* 12336 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12339 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12361 +/* 12344 */ MCD_OPC_CheckPredicate, 21, 231, 6, 0, // Skip to: 14116 +/* 12349 */ MCD_OPC_CheckField, 19, 1, 1, 224, 6, 0, // Skip to: 14116 +/* 12356 */ MCD_OPC_Decode, 162, 18, 142, 1, // Opcode: VSHRsv8i8 +/* 12361 */ MCD_OPC_FilterValue, 1, 214, 6, 0, // Skip to: 14116 +/* 12366 */ MCD_OPC_CheckPredicate, 21, 209, 6, 0, // Skip to: 14116 +/* 12371 */ MCD_OPC_CheckField, 19, 1, 1, 202, 6, 0, // Skip to: 14116 +/* 12378 */ MCD_OPC_Decode, 170, 18, 142, 1, // Opcode: VSHRuv8i8 +/* 12383 */ MCD_OPC_FilterValue, 1, 192, 6, 0, // Skip to: 14116 +/* 12388 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12391 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12406 +/* 12396 */ MCD_OPC_CheckPredicate, 21, 179, 6, 0, // Skip to: 14116 +/* 12401 */ MCD_OPC_Decode, 159, 18, 143, 1, // Opcode: VSHRsv4i16 +/* 12406 */ MCD_OPC_FilterValue, 1, 169, 6, 0, // Skip to: 14116 +/* 12411 */ MCD_OPC_CheckPredicate, 21, 164, 6, 0, // Skip to: 14116 +/* 12416 */ MCD_OPC_Decode, 167, 18, 143, 1, // Opcode: VSHRuv4i16 +/* 12421 */ MCD_OPC_FilterValue, 1, 154, 6, 0, // Skip to: 14116 +/* 12426 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12429 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12444 +/* 12434 */ MCD_OPC_CheckPredicate, 21, 141, 6, 0, // Skip to: 14116 +/* 12439 */ MCD_OPC_Decode, 157, 18, 144, 1, // Opcode: VSHRsv2i32 +/* 12444 */ MCD_OPC_FilterValue, 1, 131, 6, 0, // Skip to: 14116 +/* 12449 */ MCD_OPC_CheckPredicate, 21, 126, 6, 0, // Skip to: 14116 +/* 12454 */ MCD_OPC_Decode, 165, 18, 144, 1, // Opcode: VSHRuv2i32 +/* 12459 */ MCD_OPC_FilterValue, 1, 139, 0, 0, // Skip to: 12603 +/* 12464 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 12467 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12565 +/* 12472 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 12475 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12527 +/* 12480 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12483 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12505 +/* 12488 */ MCD_OPC_CheckPredicate, 21, 87, 6, 0, // Skip to: 14116 +/* 12493 */ MCD_OPC_CheckField, 19, 1, 1, 80, 6, 0, // Skip to: 14116 +/* 12500 */ MCD_OPC_Decode, 198, 18, 145, 1, // Opcode: VSRAsv8i8 +/* 12505 */ MCD_OPC_FilterValue, 1, 70, 6, 0, // Skip to: 14116 +/* 12510 */ MCD_OPC_CheckPredicate, 21, 65, 6, 0, // Skip to: 14116 +/* 12515 */ MCD_OPC_CheckField, 19, 1, 1, 58, 6, 0, // Skip to: 14116 +/* 12522 */ MCD_OPC_Decode, 206, 18, 145, 1, // Opcode: VSRAuv8i8 +/* 12527 */ MCD_OPC_FilterValue, 1, 48, 6, 0, // Skip to: 14116 +/* 12532 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12535 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12550 +/* 12540 */ MCD_OPC_CheckPredicate, 21, 35, 6, 0, // Skip to: 14116 +/* 12545 */ MCD_OPC_Decode, 195, 18, 146, 1, // Opcode: VSRAsv4i16 +/* 12550 */ MCD_OPC_FilterValue, 1, 25, 6, 0, // Skip to: 14116 +/* 12555 */ MCD_OPC_CheckPredicate, 21, 20, 6, 0, // Skip to: 14116 +/* 12560 */ MCD_OPC_Decode, 203, 18, 146, 1, // Opcode: VSRAuv4i16 +/* 12565 */ MCD_OPC_FilterValue, 1, 10, 6, 0, // Skip to: 14116 +/* 12570 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12573 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12588 +/* 12578 */ MCD_OPC_CheckPredicate, 21, 253, 5, 0, // Skip to: 14116 +/* 12583 */ MCD_OPC_Decode, 193, 18, 147, 1, // Opcode: VSRAsv2i32 +/* 12588 */ MCD_OPC_FilterValue, 1, 243, 5, 0, // Skip to: 14116 +/* 12593 */ MCD_OPC_CheckPredicate, 21, 238, 5, 0, // Skip to: 14116 +/* 12598 */ MCD_OPC_Decode, 201, 18, 147, 1, // Opcode: VSRAuv2i32 +/* 12603 */ MCD_OPC_FilterValue, 2, 139, 0, 0, // Skip to: 12747 +/* 12608 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 12611 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12709 +/* 12616 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 12619 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12671 +/* 12624 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12627 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12649 +/* 12632 */ MCD_OPC_CheckPredicate, 21, 199, 5, 0, // Skip to: 14116 +/* 12637 */ MCD_OPC_CheckField, 19, 1, 1, 192, 5, 0, // Skip to: 14116 +/* 12644 */ MCD_OPC_Decode, 190, 17, 142, 1, // Opcode: VRSHRsv8i8 +/* 12649 */ MCD_OPC_FilterValue, 1, 182, 5, 0, // Skip to: 14116 +/* 12654 */ MCD_OPC_CheckPredicate, 21, 177, 5, 0, // Skip to: 14116 +/* 12659 */ MCD_OPC_CheckField, 19, 1, 1, 170, 5, 0, // Skip to: 14116 +/* 12666 */ MCD_OPC_Decode, 198, 17, 142, 1, // Opcode: VRSHRuv8i8 +/* 12671 */ MCD_OPC_FilterValue, 1, 160, 5, 0, // Skip to: 14116 +/* 12676 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12679 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12694 +/* 12684 */ MCD_OPC_CheckPredicate, 21, 147, 5, 0, // Skip to: 14116 +/* 12689 */ MCD_OPC_Decode, 187, 17, 143, 1, // Opcode: VRSHRsv4i16 +/* 12694 */ MCD_OPC_FilterValue, 1, 137, 5, 0, // Skip to: 14116 +/* 12699 */ MCD_OPC_CheckPredicate, 21, 132, 5, 0, // Skip to: 14116 +/* 12704 */ MCD_OPC_Decode, 195, 17, 143, 1, // Opcode: VRSHRuv4i16 +/* 12709 */ MCD_OPC_FilterValue, 1, 122, 5, 0, // Skip to: 14116 +/* 12714 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12717 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12732 +/* 12722 */ MCD_OPC_CheckPredicate, 21, 109, 5, 0, // Skip to: 14116 +/* 12727 */ MCD_OPC_Decode, 185, 17, 144, 1, // Opcode: VRSHRsv2i32 +/* 12732 */ MCD_OPC_FilterValue, 1, 99, 5, 0, // Skip to: 14116 +/* 12737 */ MCD_OPC_CheckPredicate, 21, 94, 5, 0, // Skip to: 14116 +/* 12742 */ MCD_OPC_Decode, 193, 17, 144, 1, // Opcode: VRSHRuv2i32 +/* 12747 */ MCD_OPC_FilterValue, 3, 139, 0, 0, // Skip to: 12891 +/* 12752 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 12755 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12853 +/* 12760 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 12763 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12815 +/* 12768 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12771 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12793 +/* 12776 */ MCD_OPC_CheckPredicate, 21, 55, 5, 0, // Skip to: 14116 +/* 12781 */ MCD_OPC_CheckField, 19, 1, 1, 48, 5, 0, // Skip to: 14116 +/* 12788 */ MCD_OPC_Decode, 216, 17, 145, 1, // Opcode: VRSRAsv8i8 +/* 12793 */ MCD_OPC_FilterValue, 1, 38, 5, 0, // Skip to: 14116 +/* 12798 */ MCD_OPC_CheckPredicate, 21, 33, 5, 0, // Skip to: 14116 +/* 12803 */ MCD_OPC_CheckField, 19, 1, 1, 26, 5, 0, // Skip to: 14116 +/* 12810 */ MCD_OPC_Decode, 224, 17, 145, 1, // Opcode: VRSRAuv8i8 +/* 12815 */ MCD_OPC_FilterValue, 1, 16, 5, 0, // Skip to: 14116 +/* 12820 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12823 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12838 +/* 12828 */ MCD_OPC_CheckPredicate, 21, 3, 5, 0, // Skip to: 14116 +/* 12833 */ MCD_OPC_Decode, 213, 17, 146, 1, // Opcode: VRSRAsv4i16 +/* 12838 */ MCD_OPC_FilterValue, 1, 249, 4, 0, // Skip to: 14116 +/* 12843 */ MCD_OPC_CheckPredicate, 21, 244, 4, 0, // Skip to: 14116 +/* 12848 */ MCD_OPC_Decode, 221, 17, 146, 1, // Opcode: VRSRAuv4i16 +/* 12853 */ MCD_OPC_FilterValue, 1, 234, 4, 0, // Skip to: 14116 +/* 12858 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 12861 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12876 +/* 12866 */ MCD_OPC_CheckPredicate, 21, 221, 4, 0, // Skip to: 14116 +/* 12871 */ MCD_OPC_Decode, 211, 17, 147, 1, // Opcode: VRSRAsv2i32 +/* 12876 */ MCD_OPC_FilterValue, 1, 211, 4, 0, // Skip to: 14116 +/* 12881 */ MCD_OPC_CheckPredicate, 21, 206, 4, 0, // Skip to: 14116 +/* 12886 */ MCD_OPC_Decode, 219, 17, 147, 1, // Opcode: VRSRAuv2i32 +/* 12891 */ MCD_OPC_FilterValue, 4, 84, 0, 0, // Skip to: 12980 +/* 12896 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 12899 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 12958 +/* 12904 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 12907 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 12936 +/* 12912 */ MCD_OPC_CheckPredicate, 21, 175, 4, 0, // Skip to: 14116 +/* 12917 */ MCD_OPC_CheckField, 24, 1, 1, 168, 4, 0, // Skip to: 14116 +/* 12924 */ MCD_OPC_CheckField, 19, 1, 1, 161, 4, 0, // Skip to: 14116 +/* 12931 */ MCD_OPC_Decode, 214, 18, 145, 1, // Opcode: VSRIv8i8 +/* 12936 */ MCD_OPC_FilterValue, 1, 151, 4, 0, // Skip to: 14116 +/* 12941 */ MCD_OPC_CheckPredicate, 21, 146, 4, 0, // Skip to: 14116 +/* 12946 */ MCD_OPC_CheckField, 24, 1, 1, 139, 4, 0, // Skip to: 14116 +/* 12953 */ MCD_OPC_Decode, 211, 18, 146, 1, // Opcode: VSRIv4i16 +/* 12958 */ MCD_OPC_FilterValue, 1, 129, 4, 0, // Skip to: 14116 +/* 12963 */ MCD_OPC_CheckPredicate, 21, 124, 4, 0, // Skip to: 14116 +/* 12968 */ MCD_OPC_CheckField, 24, 1, 1, 117, 4, 0, // Skip to: 14116 +/* 12975 */ MCD_OPC_Decode, 209, 18, 147, 1, // Opcode: VSRIv2i32 +/* 12980 */ MCD_OPC_FilterValue, 5, 139, 0, 0, // Skip to: 13124 +/* 12985 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 12988 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13086 +/* 12993 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 12996 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13048 +/* 13001 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13004 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13026 +/* 13009 */ MCD_OPC_CheckPredicate, 21, 78, 4, 0, // Skip to: 14116 +/* 13014 */ MCD_OPC_CheckField, 19, 1, 1, 71, 4, 0, // Skip to: 14116 +/* 13021 */ MCD_OPC_Decode, 135, 18, 148, 1, // Opcode: VSHLiv8i8 +/* 13026 */ MCD_OPC_FilterValue, 1, 61, 4, 0, // Skip to: 14116 +/* 13031 */ MCD_OPC_CheckPredicate, 21, 56, 4, 0, // Skip to: 14116 +/* 13036 */ MCD_OPC_CheckField, 19, 1, 1, 49, 4, 0, // Skip to: 14116 +/* 13043 */ MCD_OPC_Decode, 184, 18, 149, 1, // Opcode: VSLIv8i8 +/* 13048 */ MCD_OPC_FilterValue, 1, 39, 4, 0, // Skip to: 14116 +/* 13053 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13056 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13071 +/* 13061 */ MCD_OPC_CheckPredicate, 21, 26, 4, 0, // Skip to: 14116 +/* 13066 */ MCD_OPC_Decode, 132, 18, 150, 1, // Opcode: VSHLiv4i16 +/* 13071 */ MCD_OPC_FilterValue, 1, 16, 4, 0, // Skip to: 14116 +/* 13076 */ MCD_OPC_CheckPredicate, 21, 11, 4, 0, // Skip to: 14116 +/* 13081 */ MCD_OPC_Decode, 181, 18, 151, 1, // Opcode: VSLIv4i16 +/* 13086 */ MCD_OPC_FilterValue, 1, 1, 4, 0, // Skip to: 14116 +/* 13091 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13094 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13109 +/* 13099 */ MCD_OPC_CheckPredicate, 21, 244, 3, 0, // Skip to: 14116 +/* 13104 */ MCD_OPC_Decode, 130, 18, 152, 1, // Opcode: VSHLiv2i32 +/* 13109 */ MCD_OPC_FilterValue, 1, 234, 3, 0, // Skip to: 14116 +/* 13114 */ MCD_OPC_CheckPredicate, 21, 229, 3, 0, // Skip to: 14116 +/* 13119 */ MCD_OPC_Decode, 179, 18, 153, 1, // Opcode: VSLIv2i32 +/* 13124 */ MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 13213 +/* 13129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 13132 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 13191 +/* 13137 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 13140 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 13169 +/* 13145 */ MCD_OPC_CheckPredicate, 21, 198, 3, 0, // Skip to: 14116 +/* 13150 */ MCD_OPC_CheckField, 24, 1, 1, 191, 3, 0, // Skip to: 14116 +/* 13157 */ MCD_OPC_CheckField, 19, 1, 1, 184, 3, 0, // Skip to: 14116 +/* 13164 */ MCD_OPC_Decode, 160, 16, 148, 1, // Opcode: VQSHLsuv8i8 +/* 13169 */ MCD_OPC_FilterValue, 1, 174, 3, 0, // Skip to: 14116 +/* 13174 */ MCD_OPC_CheckPredicate, 21, 169, 3, 0, // Skip to: 14116 +/* 13179 */ MCD_OPC_CheckField, 24, 1, 1, 162, 3, 0, // Skip to: 14116 +/* 13186 */ MCD_OPC_Decode, 157, 16, 150, 1, // Opcode: VQSHLsuv4i16 +/* 13191 */ MCD_OPC_FilterValue, 1, 152, 3, 0, // Skip to: 14116 +/* 13196 */ MCD_OPC_CheckPredicate, 21, 147, 3, 0, // Skip to: 14116 +/* 13201 */ MCD_OPC_CheckField, 24, 1, 1, 140, 3, 0, // Skip to: 14116 +/* 13208 */ MCD_OPC_Decode, 155, 16, 152, 1, // Opcode: VQSHLsuv2i32 +/* 13213 */ MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 13357 +/* 13218 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 13221 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13319 +/* 13226 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 13229 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13281 +/* 13234 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13237 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13259 +/* 13242 */ MCD_OPC_CheckPredicate, 21, 101, 3, 0, // Skip to: 14116 +/* 13247 */ MCD_OPC_CheckField, 19, 1, 1, 94, 3, 0, // Skip to: 14116 +/* 13254 */ MCD_OPC_Decode, 152, 16, 148, 1, // Opcode: VQSHLsiv8i8 +/* 13259 */ MCD_OPC_FilterValue, 1, 84, 3, 0, // Skip to: 14116 +/* 13264 */ MCD_OPC_CheckPredicate, 21, 79, 3, 0, // Skip to: 14116 +/* 13269 */ MCD_OPC_CheckField, 19, 1, 1, 72, 3, 0, // Skip to: 14116 +/* 13276 */ MCD_OPC_Decode, 176, 16, 148, 1, // Opcode: VQSHLuiv8i8 +/* 13281 */ MCD_OPC_FilterValue, 1, 62, 3, 0, // Skip to: 14116 +/* 13286 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13289 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13304 +/* 13294 */ MCD_OPC_CheckPredicate, 21, 49, 3, 0, // Skip to: 14116 +/* 13299 */ MCD_OPC_Decode, 149, 16, 150, 1, // Opcode: VQSHLsiv4i16 +/* 13304 */ MCD_OPC_FilterValue, 1, 39, 3, 0, // Skip to: 14116 +/* 13309 */ MCD_OPC_CheckPredicate, 21, 34, 3, 0, // Skip to: 14116 +/* 13314 */ MCD_OPC_Decode, 173, 16, 150, 1, // Opcode: VQSHLuiv4i16 +/* 13319 */ MCD_OPC_FilterValue, 1, 24, 3, 0, // Skip to: 14116 +/* 13324 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13327 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13342 +/* 13332 */ MCD_OPC_CheckPredicate, 21, 11, 3, 0, // Skip to: 14116 +/* 13337 */ MCD_OPC_Decode, 147, 16, 152, 1, // Opcode: VQSHLsiv2i32 +/* 13342 */ MCD_OPC_FilterValue, 1, 1, 3, 0, // Skip to: 14116 +/* 13347 */ MCD_OPC_CheckPredicate, 21, 252, 2, 0, // Skip to: 14116 +/* 13352 */ MCD_OPC_Decode, 171, 16, 152, 1, // Opcode: VQSHLuiv2i32 +/* 13357 */ MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 13501 +/* 13362 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 13365 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13463 +/* 13370 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 13373 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13425 +/* 13378 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13381 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13403 +/* 13386 */ MCD_OPC_CheckPredicate, 21, 213, 2, 0, // Skip to: 14116 +/* 13391 */ MCD_OPC_CheckField, 19, 1, 1, 206, 2, 0, // Skip to: 14116 +/* 13398 */ MCD_OPC_Decode, 154, 18, 154, 1, // Opcode: VSHRNv8i8 +/* 13403 */ MCD_OPC_FilterValue, 1, 196, 2, 0, // Skip to: 14116 +/* 13408 */ MCD_OPC_CheckPredicate, 21, 191, 2, 0, // Skip to: 14116 +/* 13413 */ MCD_OPC_CheckField, 19, 1, 1, 184, 2, 0, // Skip to: 14116 +/* 13420 */ MCD_OPC_Decode, 193, 16, 154, 1, // Opcode: VQSHRUNv8i8 +/* 13425 */ MCD_OPC_FilterValue, 1, 174, 2, 0, // Skip to: 14116 +/* 13430 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13433 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13448 +/* 13438 */ MCD_OPC_CheckPredicate, 21, 161, 2, 0, // Skip to: 14116 +/* 13443 */ MCD_OPC_Decode, 153, 18, 155, 1, // Opcode: VSHRNv4i16 +/* 13448 */ MCD_OPC_FilterValue, 1, 151, 2, 0, // Skip to: 14116 +/* 13453 */ MCD_OPC_CheckPredicate, 21, 146, 2, 0, // Skip to: 14116 +/* 13458 */ MCD_OPC_Decode, 192, 16, 155, 1, // Opcode: VQSHRUNv4i16 +/* 13463 */ MCD_OPC_FilterValue, 1, 136, 2, 0, // Skip to: 14116 +/* 13468 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13471 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13486 +/* 13476 */ MCD_OPC_CheckPredicate, 21, 123, 2, 0, // Skip to: 14116 +/* 13481 */ MCD_OPC_Decode, 152, 18, 156, 1, // Opcode: VSHRNv2i32 +/* 13486 */ MCD_OPC_FilterValue, 1, 113, 2, 0, // Skip to: 14116 +/* 13491 */ MCD_OPC_CheckPredicate, 21, 108, 2, 0, // Skip to: 14116 +/* 13496 */ MCD_OPC_Decode, 191, 16, 156, 1, // Opcode: VQSHRUNv2i32 +/* 13501 */ MCD_OPC_FilterValue, 9, 139, 0, 0, // Skip to: 13645 +/* 13506 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 13509 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13607 +/* 13514 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 13517 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13569 +/* 13522 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13525 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13547 +/* 13530 */ MCD_OPC_CheckPredicate, 21, 69, 2, 0, // Skip to: 14116 +/* 13535 */ MCD_OPC_CheckField, 19, 1, 1, 62, 2, 0, // Skip to: 14116 +/* 13542 */ MCD_OPC_Decode, 187, 16, 154, 1, // Opcode: VQSHRNsv8i8 +/* 13547 */ MCD_OPC_FilterValue, 1, 52, 2, 0, // Skip to: 14116 +/* 13552 */ MCD_OPC_CheckPredicate, 21, 47, 2, 0, // Skip to: 14116 +/* 13557 */ MCD_OPC_CheckField, 19, 1, 1, 40, 2, 0, // Skip to: 14116 +/* 13564 */ MCD_OPC_Decode, 190, 16, 154, 1, // Opcode: VQSHRNuv8i8 +/* 13569 */ MCD_OPC_FilterValue, 1, 30, 2, 0, // Skip to: 14116 +/* 13574 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13577 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13592 +/* 13582 */ MCD_OPC_CheckPredicate, 21, 17, 2, 0, // Skip to: 14116 +/* 13587 */ MCD_OPC_Decode, 186, 16, 155, 1, // Opcode: VQSHRNsv4i16 +/* 13592 */ MCD_OPC_FilterValue, 1, 7, 2, 0, // Skip to: 14116 +/* 13597 */ MCD_OPC_CheckPredicate, 21, 2, 2, 0, // Skip to: 14116 +/* 13602 */ MCD_OPC_Decode, 189, 16, 155, 1, // Opcode: VQSHRNuv4i16 +/* 13607 */ MCD_OPC_FilterValue, 1, 248, 1, 0, // Skip to: 14116 +/* 13612 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13615 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13630 +/* 13620 */ MCD_OPC_CheckPredicate, 21, 235, 1, 0, // Skip to: 14116 +/* 13625 */ MCD_OPC_Decode, 185, 16, 156, 1, // Opcode: VQSHRNsv2i32 +/* 13630 */ MCD_OPC_FilterValue, 1, 225, 1, 0, // Skip to: 14116 +/* 13635 */ MCD_OPC_CheckPredicate, 21, 220, 1, 0, // Skip to: 14116 +/* 13640 */ MCD_OPC_Decode, 188, 16, 156, 1, // Opcode: VQSHRNuv2i32 +/* 13645 */ MCD_OPC_FilterValue, 10, 243, 0, 0, // Skip to: 13893 +/* 13650 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 13653 */ MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 13821 +/* 13658 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 13661 */ MCD_OPC_FilterValue, 0, 83, 0, 0, // Skip to: 13749 +/* 13666 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13669 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 13709 +/* 13674 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 13677 */ MCD_OPC_FilterValue, 1, 178, 1, 0, // Skip to: 14116 +/* 13682 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13699 +/* 13687 */ MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 13699 +/* 13694 */ MCD_OPC_Decode, 142, 14, 134, 1, // Opcode: VMOVLsv8i16 +/* 13699 */ MCD_OPC_CheckPredicate, 21, 156, 1, 0, // Skip to: 14116 +/* 13704 */ MCD_OPC_Decode, 252, 17, 157, 1, // Opcode: VSHLLsv8i16 +/* 13709 */ MCD_OPC_FilterValue, 1, 146, 1, 0, // Skip to: 14116 +/* 13714 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 13717 */ MCD_OPC_FilterValue, 1, 138, 1, 0, // Skip to: 14116 +/* 13722 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13739 +/* 13727 */ MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 13739 +/* 13734 */ MCD_OPC_Decode, 145, 14, 134, 1, // Opcode: VMOVLuv8i16 +/* 13739 */ MCD_OPC_CheckPredicate, 21, 116, 1, 0, // Skip to: 14116 +/* 13744 */ MCD_OPC_Decode, 255, 17, 157, 1, // Opcode: VSHLLuv8i16 +/* 13749 */ MCD_OPC_FilterValue, 1, 106, 1, 0, // Skip to: 14116 +/* 13754 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13757 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 13789 +/* 13762 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13779 +/* 13767 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 13779 +/* 13774 */ MCD_OPC_Decode, 141, 14, 134, 1, // Opcode: VMOVLsv4i32 +/* 13779 */ MCD_OPC_CheckPredicate, 21, 76, 1, 0, // Skip to: 14116 +/* 13784 */ MCD_OPC_Decode, 251, 17, 158, 1, // Opcode: VSHLLsv4i32 +/* 13789 */ MCD_OPC_FilterValue, 1, 66, 1, 0, // Skip to: 14116 +/* 13794 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13811 +/* 13799 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 13811 +/* 13806 */ MCD_OPC_Decode, 144, 14, 134, 1, // Opcode: VMOVLuv4i32 +/* 13811 */ MCD_OPC_CheckPredicate, 21, 44, 1, 0, // Skip to: 14116 +/* 13816 */ MCD_OPC_Decode, 254, 17, 158, 1, // Opcode: VSHLLuv4i32 +/* 13821 */ MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 14116 +/* 13826 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13829 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 13861 +/* 13834 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13851 +/* 13839 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 13851 +/* 13846 */ MCD_OPC_Decode, 140, 14, 134, 1, // Opcode: VMOVLsv2i64 +/* 13851 */ MCD_OPC_CheckPredicate, 21, 4, 1, 0, // Skip to: 14116 +/* 13856 */ MCD_OPC_Decode, 250, 17, 159, 1, // Opcode: VSHLLsv2i64 +/* 13861 */ MCD_OPC_FilterValue, 1, 250, 0, 0, // Skip to: 14116 +/* 13866 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13883 +/* 13871 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 13883 +/* 13878 */ MCD_OPC_Decode, 143, 14, 134, 1, // Opcode: VMOVLuv2i64 +/* 13883 */ MCD_OPC_CheckPredicate, 21, 228, 0, 0, // Skip to: 14116 +/* 13888 */ MCD_OPC_Decode, 253, 17, 159, 1, // Opcode: VSHLLuv2i64 +/* 13893 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 13931 +/* 13898 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13901 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13916 +/* 13906 */ MCD_OPC_CheckPredicate, 22, 205, 0, 0, // Skip to: 14116 +/* 13911 */ MCD_OPC_Decode, 247, 9, 160, 1, // Opcode: VCVTxs2hd +/* 13916 */ MCD_OPC_FilterValue, 1, 195, 0, 0, // Skip to: 14116 +/* 13921 */ MCD_OPC_CheckPredicate, 22, 190, 0, 0, // Skip to: 14116 +/* 13926 */ MCD_OPC_Decode, 251, 9, 160, 1, // Opcode: VCVTxu2hd +/* 13931 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 13969 +/* 13936 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 13939 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13954 +/* 13944 */ MCD_OPC_CheckPredicate, 22, 167, 0, 0, // Skip to: 14116 +/* 13949 */ MCD_OPC_Decode, 233, 9, 160, 1, // Opcode: VCVTh2xsd +/* 13954 */ MCD_OPC_FilterValue, 1, 157, 0, 0, // Skip to: 14116 +/* 13959 */ MCD_OPC_CheckPredicate, 22, 152, 0, 0, // Skip to: 14116 +/* 13964 */ MCD_OPC_Decode, 235, 9, 160, 1, // Opcode: VCVTh2xud +/* 13969 */ MCD_OPC_FilterValue, 14, 80, 0, 0, // Skip to: 14054 +/* 13974 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 13977 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13999 +/* 13982 */ MCD_OPC_CheckPredicate, 21, 34, 0, 0, // Skip to: 14021 +/* 13987 */ MCD_OPC_CheckField, 19, 3, 0, 27, 0, 0, // Skip to: 14021 +/* 13994 */ MCD_OPC_Decode, 165, 14, 161, 1, // Opcode: VMOVv8i8 +/* 13999 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14021 +/* 14004 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14021 +/* 14009 */ MCD_OPC_CheckField, 19, 3, 0, 5, 0, 0, // Skip to: 14021 +/* 14016 */ MCD_OPC_Decode, 157, 14, 161, 1, // Opcode: VMOVv1i64 +/* 14021 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 14024 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14039 +/* 14029 */ MCD_OPC_CheckPredicate, 21, 82, 0, 0, // Skip to: 14116 +/* 14034 */ MCD_OPC_Decode, 245, 9, 160, 1, // Opcode: VCVTxs2fd +/* 14039 */ MCD_OPC_FilterValue, 1, 72, 0, 0, // Skip to: 14116 +/* 14044 */ MCD_OPC_CheckPredicate, 21, 67, 0, 0, // Skip to: 14116 +/* 14049 */ MCD_OPC_Decode, 249, 9, 160, 1, // Opcode: VCVTxu2fd +/* 14054 */ MCD_OPC_FilterValue, 15, 57, 0, 0, // Skip to: 14116 +/* 14059 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 14062 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14077 +/* 14067 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 14092 +/* 14072 */ MCD_OPC_Decode, 224, 9, 160, 1, // Opcode: VCVTf2xsd +/* 14077 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 14092 +/* 14082 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 14092 +/* 14087 */ MCD_OPC_Decode, 226, 9, 160, 1, // Opcode: VCVTf2xud +/* 14092 */ MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 14116 +/* 14097 */ MCD_OPC_CheckField, 19, 3, 0, 12, 0, 0, // Skip to: 14116 +/* 14104 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 14116 +/* 14111 */ MCD_OPC_Decode, 158, 14, 161, 1, // Opcode: VMOVv2f32 +/* 14116 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 14119 */ MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 14212 +/* 14124 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... +/* 14127 */ MCD_OPC_FilterValue, 0, 69, 17, 0, // Skip to: 18553 +/* 14132 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 14135 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14157 +/* 14140 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 14202 +/* 14145 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 14202 +/* 14152 */ MCD_OPC_Decode, 162, 14, 161, 1, // Opcode: VMOVv4i16 +/* 14157 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 14202 +/* 14162 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 14165 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14180 +/* 14170 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 14202 +/* 14175 */ MCD_OPC_Decode, 245, 14, 161, 1, // Opcode: VORRiv2i32 +/* 14180 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14202 +/* 14185 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14202 +/* 14190 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 14202 +/* 14197 */ MCD_OPC_Decode, 246, 14, 161, 1, // Opcode: VORRiv4i16 +/* 14202 */ MCD_OPC_CheckPredicate, 21, 250, 16, 0, // Skip to: 18553 +/* 14207 */ MCD_OPC_Decode, 159, 14, 161, 1, // Opcode: VMOVv2i32 +/* 14212 */ MCD_OPC_FilterValue, 1, 240, 16, 0, // Skip to: 18553 +/* 14217 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... +/* 14220 */ MCD_OPC_FilterValue, 0, 232, 16, 0, // Skip to: 18553 +/* 14225 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 14228 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14250 +/* 14233 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 14295 +/* 14238 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 14295 +/* 14245 */ MCD_OPC_Decode, 217, 14, 161, 1, // Opcode: VMVNv4i16 +/* 14250 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 14295 +/* 14255 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 14258 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14273 +/* 14263 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 14295 +/* 14268 */ MCD_OPC_Decode, 140, 8, 161, 1, // Opcode: VBICiv2i32 +/* 14273 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14295 +/* 14278 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14295 +/* 14283 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 14295 +/* 14290 */ MCD_OPC_Decode, 141, 8, 161, 1, // Opcode: VBICiv4i16 +/* 14295 */ MCD_OPC_CheckPredicate, 21, 157, 16, 0, // Skip to: 18553 +/* 14300 */ MCD_OPC_Decode, 216, 14, 161, 1, // Opcode: VMVNv2i32 +/* 14305 */ MCD_OPC_FilterValue, 1, 147, 16, 0, // Skip to: 18553 +/* 14310 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 14313 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 14353 +/* 14318 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14321 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14337 +/* 14327 */ MCD_OPC_CheckPredicate, 21, 125, 16, 0, // Skip to: 18553 +/* 14332 */ MCD_OPC_Decode, 156, 18, 162, 1, // Opcode: VSHRsv1i64 +/* 14337 */ MCD_OPC_FilterValue, 243, 1, 114, 16, 0, // Skip to: 18553 +/* 14343 */ MCD_OPC_CheckPredicate, 21, 109, 16, 0, // Skip to: 18553 +/* 14348 */ MCD_OPC_Decode, 164, 18, 162, 1, // Opcode: VSHRuv1i64 +/* 14353 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 14393 +/* 14358 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14361 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14377 +/* 14367 */ MCD_OPC_CheckPredicate, 21, 85, 16, 0, // Skip to: 18553 +/* 14372 */ MCD_OPC_Decode, 192, 18, 163, 1, // Opcode: VSRAsv1i64 +/* 14377 */ MCD_OPC_FilterValue, 243, 1, 74, 16, 0, // Skip to: 18553 +/* 14383 */ MCD_OPC_CheckPredicate, 21, 69, 16, 0, // Skip to: 18553 +/* 14388 */ MCD_OPC_Decode, 200, 18, 163, 1, // Opcode: VSRAuv1i64 +/* 14393 */ MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 14433 +/* 14398 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14401 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14417 +/* 14407 */ MCD_OPC_CheckPredicate, 21, 45, 16, 0, // Skip to: 18553 +/* 14412 */ MCD_OPC_Decode, 184, 17, 162, 1, // Opcode: VRSHRsv1i64 +/* 14417 */ MCD_OPC_FilterValue, 243, 1, 34, 16, 0, // Skip to: 18553 +/* 14423 */ MCD_OPC_CheckPredicate, 21, 29, 16, 0, // Skip to: 18553 +/* 14428 */ MCD_OPC_Decode, 192, 17, 162, 1, // Opcode: VRSHRuv1i64 +/* 14433 */ MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 14473 +/* 14438 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14441 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14457 +/* 14447 */ MCD_OPC_CheckPredicate, 21, 5, 16, 0, // Skip to: 18553 +/* 14452 */ MCD_OPC_Decode, 210, 17, 163, 1, // Opcode: VRSRAsv1i64 +/* 14457 */ MCD_OPC_FilterValue, 243, 1, 250, 15, 0, // Skip to: 18553 +/* 14463 */ MCD_OPC_CheckPredicate, 21, 245, 15, 0, // Skip to: 18553 +/* 14468 */ MCD_OPC_Decode, 218, 17, 163, 1, // Opcode: VRSRAuv1i64 +/* 14473 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 14496 +/* 14478 */ MCD_OPC_CheckPredicate, 21, 230, 15, 0, // Skip to: 18553 +/* 14483 */ MCD_OPC_CheckField, 24, 8, 243, 1, 222, 15, 0, // Skip to: 18553 +/* 14491 */ MCD_OPC_Decode, 208, 18, 163, 1, // Opcode: VSRIv1i64 +/* 14496 */ MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 14536 +/* 14501 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14504 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14520 +/* 14510 */ MCD_OPC_CheckPredicate, 21, 198, 15, 0, // Skip to: 18553 +/* 14515 */ MCD_OPC_Decode, 129, 18, 164, 1, // Opcode: VSHLiv1i64 +/* 14520 */ MCD_OPC_FilterValue, 243, 1, 187, 15, 0, // Skip to: 18553 +/* 14526 */ MCD_OPC_CheckPredicate, 21, 182, 15, 0, // Skip to: 18553 +/* 14531 */ MCD_OPC_Decode, 178, 18, 165, 1, // Opcode: VSLIv1i64 +/* 14536 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 14559 +/* 14541 */ MCD_OPC_CheckPredicate, 21, 167, 15, 0, // Skip to: 18553 +/* 14546 */ MCD_OPC_CheckField, 24, 8, 243, 1, 159, 15, 0, // Skip to: 18553 +/* 14554 */ MCD_OPC_Decode, 154, 16, 164, 1, // Opcode: VQSHLsuv1i64 +/* 14559 */ MCD_OPC_FilterValue, 7, 149, 15, 0, // Skip to: 18553 +/* 14564 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14567 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14583 +/* 14573 */ MCD_OPC_CheckPredicate, 21, 135, 15, 0, // Skip to: 18553 +/* 14578 */ MCD_OPC_Decode, 146, 16, 164, 1, // Opcode: VQSHLsiv1i64 +/* 14583 */ MCD_OPC_FilterValue, 243, 1, 124, 15, 0, // Skip to: 18553 +/* 14589 */ MCD_OPC_CheckPredicate, 21, 119, 15, 0, // Skip to: 18553 +/* 14594 */ MCD_OPC_Decode, 170, 16, 164, 1, // Opcode: VQSHLuiv1i64 +/* 14599 */ MCD_OPC_FilterValue, 1, 109, 15, 0, // Skip to: 18553 +/* 14604 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 14607 */ MCD_OPC_FilterValue, 0, 89, 7, 0, // Skip to: 16493 +/* 14612 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 14615 */ MCD_OPC_FilterValue, 0, 155, 0, 0, // Skip to: 14775 +/* 14620 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 14623 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14661 +/* 14628 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14631 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14646 +/* 14637 */ MCD_OPC_CheckPredicate, 21, 71, 15, 0, // Skip to: 18553 +/* 14642 */ MCD_OPC_Decode, 173, 15, 98, // Opcode: VQADDsv16i8 +/* 14646 */ MCD_OPC_FilterValue, 243, 1, 61, 15, 0, // Skip to: 18553 +/* 14652 */ MCD_OPC_CheckPredicate, 21, 56, 15, 0, // Skip to: 18553 +/* 14657 */ MCD_OPC_Decode, 181, 15, 98, // Opcode: VQADDuv16i8 +/* 14661 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 14699 +/* 14666 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14669 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14684 +/* 14675 */ MCD_OPC_CheckPredicate, 21, 33, 15, 0, // Skip to: 18553 +/* 14680 */ MCD_OPC_Decode, 179, 15, 98, // Opcode: VQADDsv8i16 +/* 14684 */ MCD_OPC_FilterValue, 243, 1, 23, 15, 0, // Skip to: 18553 +/* 14690 */ MCD_OPC_CheckPredicate, 21, 18, 15, 0, // Skip to: 18553 +/* 14695 */ MCD_OPC_Decode, 187, 15, 98, // Opcode: VQADDuv8i16 +/* 14699 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 14737 +/* 14704 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14707 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14722 +/* 14713 */ MCD_OPC_CheckPredicate, 21, 251, 14, 0, // Skip to: 18553 +/* 14718 */ MCD_OPC_Decode, 178, 15, 98, // Opcode: VQADDsv4i32 +/* 14722 */ MCD_OPC_FilterValue, 243, 1, 241, 14, 0, // Skip to: 18553 +/* 14728 */ MCD_OPC_CheckPredicate, 21, 236, 14, 0, // Skip to: 18553 +/* 14733 */ MCD_OPC_Decode, 186, 15, 98, // Opcode: VQADDuv4i32 +/* 14737 */ MCD_OPC_FilterValue, 3, 227, 14, 0, // Skip to: 18553 +/* 14742 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14745 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14760 +/* 14751 */ MCD_OPC_CheckPredicate, 21, 213, 14, 0, // Skip to: 18553 +/* 14756 */ MCD_OPC_Decode, 176, 15, 98, // Opcode: VQADDsv2i64 +/* 14760 */ MCD_OPC_FilterValue, 243, 1, 203, 14, 0, // Skip to: 18553 +/* 14766 */ MCD_OPC_CheckPredicate, 21, 198, 14, 0, // Skip to: 18553 +/* 14771 */ MCD_OPC_Decode, 184, 15, 98, // Opcode: VQADDuv2i64 +/* 14775 */ MCD_OPC_FilterValue, 1, 155, 0, 0, // Skip to: 14935 +/* 14780 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 14783 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14821 +/* 14788 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14791 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14806 +/* 14797 */ MCD_OPC_CheckPredicate, 21, 167, 14, 0, // Skip to: 18553 +/* 14802 */ MCD_OPC_Decode, 138, 8, 98, // Opcode: VANDq +/* 14806 */ MCD_OPC_FilterValue, 243, 1, 157, 14, 0, // Skip to: 18553 +/* 14812 */ MCD_OPC_CheckPredicate, 21, 152, 14, 0, // Skip to: 18553 +/* 14817 */ MCD_OPC_Decode, 141, 10, 98, // Opcode: VEORq +/* 14821 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 14859 +/* 14826 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14829 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14844 +/* 14835 */ MCD_OPC_CheckPredicate, 21, 129, 14, 0, // Skip to: 18553 +/* 14840 */ MCD_OPC_Decode, 144, 8, 98, // Opcode: VBICq +/* 14844 */ MCD_OPC_FilterValue, 243, 1, 119, 14, 0, // Skip to: 18553 +/* 14850 */ MCD_OPC_CheckPredicate, 21, 114, 14, 0, // Skip to: 18553 +/* 14855 */ MCD_OPC_Decode, 150, 8, 106, // Opcode: VBSLq +/* 14859 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 14897 +/* 14864 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14867 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14882 +/* 14873 */ MCD_OPC_CheckPredicate, 21, 91, 14, 0, // Skip to: 18553 +/* 14878 */ MCD_OPC_Decode, 249, 14, 98, // Opcode: VORRq +/* 14882 */ MCD_OPC_FilterValue, 243, 1, 81, 14, 0, // Skip to: 18553 +/* 14888 */ MCD_OPC_CheckPredicate, 21, 76, 14, 0, // Skip to: 18553 +/* 14893 */ MCD_OPC_Decode, 148, 8, 106, // Opcode: VBITq +/* 14897 */ MCD_OPC_FilterValue, 3, 67, 14, 0, // Skip to: 18553 +/* 14902 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14905 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14920 +/* 14911 */ MCD_OPC_CheckPredicate, 21, 53, 14, 0, // Skip to: 18553 +/* 14916 */ MCD_OPC_Decode, 243, 14, 98, // Opcode: VORNq +/* 14920 */ MCD_OPC_FilterValue, 243, 1, 43, 14, 0, // Skip to: 18553 +/* 14926 */ MCD_OPC_CheckPredicate, 21, 38, 14, 0, // Skip to: 18553 +/* 14931 */ MCD_OPC_Decode, 146, 8, 106, // Opcode: VBIFq +/* 14935 */ MCD_OPC_FilterValue, 2, 155, 0, 0, // Skip to: 15095 +/* 14940 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 14943 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14981 +/* 14948 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14951 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14966 +/* 14957 */ MCD_OPC_CheckPredicate, 21, 7, 14, 0, // Skip to: 18553 +/* 14962 */ MCD_OPC_Decode, 194, 16, 98, // Opcode: VQSUBsv16i8 +/* 14966 */ MCD_OPC_FilterValue, 243, 1, 253, 13, 0, // Skip to: 18553 +/* 14972 */ MCD_OPC_CheckPredicate, 21, 248, 13, 0, // Skip to: 18553 +/* 14977 */ MCD_OPC_Decode, 202, 16, 98, // Opcode: VQSUBuv16i8 +/* 14981 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15019 +/* 14986 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 14989 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15004 +/* 14995 */ MCD_OPC_CheckPredicate, 21, 225, 13, 0, // Skip to: 18553 +/* 15000 */ MCD_OPC_Decode, 200, 16, 98, // Opcode: VQSUBsv8i16 +/* 15004 */ MCD_OPC_FilterValue, 243, 1, 215, 13, 0, // Skip to: 18553 +/* 15010 */ MCD_OPC_CheckPredicate, 21, 210, 13, 0, // Skip to: 18553 +/* 15015 */ MCD_OPC_Decode, 208, 16, 98, // Opcode: VQSUBuv8i16 +/* 15019 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15057 +/* 15024 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15027 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15042 +/* 15033 */ MCD_OPC_CheckPredicate, 21, 187, 13, 0, // Skip to: 18553 +/* 15038 */ MCD_OPC_Decode, 199, 16, 98, // Opcode: VQSUBsv4i32 +/* 15042 */ MCD_OPC_FilterValue, 243, 1, 177, 13, 0, // Skip to: 18553 +/* 15048 */ MCD_OPC_CheckPredicate, 21, 172, 13, 0, // Skip to: 18553 +/* 15053 */ MCD_OPC_Decode, 207, 16, 98, // Opcode: VQSUBuv4i32 +/* 15057 */ MCD_OPC_FilterValue, 3, 163, 13, 0, // Skip to: 18553 +/* 15062 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15065 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15080 +/* 15071 */ MCD_OPC_CheckPredicate, 21, 149, 13, 0, // Skip to: 18553 +/* 15076 */ MCD_OPC_Decode, 197, 16, 98, // Opcode: VQSUBsv2i64 +/* 15080 */ MCD_OPC_FilterValue, 243, 1, 139, 13, 0, // Skip to: 18553 +/* 15086 */ MCD_OPC_CheckPredicate, 21, 134, 13, 0, // Skip to: 18553 +/* 15091 */ MCD_OPC_Decode, 205, 16, 98, // Opcode: VQSUBuv2i64 +/* 15095 */ MCD_OPC_FilterValue, 3, 117, 0, 0, // Skip to: 15217 +/* 15100 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 15103 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15141 +/* 15108 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15111 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15126 +/* 15117 */ MCD_OPC_CheckPredicate, 21, 103, 13, 0, // Skip to: 18553 +/* 15122 */ MCD_OPC_Decode, 179, 8, 98, // Opcode: VCGEsv16i8 +/* 15126 */ MCD_OPC_FilterValue, 243, 1, 93, 13, 0, // Skip to: 18553 +/* 15132 */ MCD_OPC_CheckPredicate, 21, 88, 13, 0, // Skip to: 18553 +/* 15137 */ MCD_OPC_Decode, 185, 8, 98, // Opcode: VCGEuv16i8 +/* 15141 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15179 +/* 15146 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15149 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15164 +/* 15155 */ MCD_OPC_CheckPredicate, 21, 65, 13, 0, // Skip to: 18553 +/* 15160 */ MCD_OPC_Decode, 183, 8, 98, // Opcode: VCGEsv8i16 +/* 15164 */ MCD_OPC_FilterValue, 243, 1, 55, 13, 0, // Skip to: 18553 +/* 15170 */ MCD_OPC_CheckPredicate, 21, 50, 13, 0, // Skip to: 18553 +/* 15175 */ MCD_OPC_Decode, 189, 8, 98, // Opcode: VCGEuv8i16 +/* 15179 */ MCD_OPC_FilterValue, 2, 41, 13, 0, // Skip to: 18553 +/* 15184 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15187 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15202 +/* 15193 */ MCD_OPC_CheckPredicate, 21, 27, 13, 0, // Skip to: 18553 +/* 15198 */ MCD_OPC_Decode, 182, 8, 98, // Opcode: VCGEsv4i32 +/* 15202 */ MCD_OPC_FilterValue, 243, 1, 17, 13, 0, // Skip to: 18553 +/* 15208 */ MCD_OPC_CheckPredicate, 21, 12, 13, 0, // Skip to: 18553 +/* 15213 */ MCD_OPC_Decode, 188, 8, 98, // Opcode: VCGEuv4i32 +/* 15217 */ MCD_OPC_FilterValue, 4, 155, 0, 0, // Skip to: 15377 +/* 15222 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 15225 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15263 +/* 15230 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15233 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15248 +/* 15239 */ MCD_OPC_CheckPredicate, 21, 237, 12, 0, // Skip to: 18553 +/* 15244 */ MCD_OPC_Decode, 161, 16, 102, // Opcode: VQSHLsv16i8 +/* 15248 */ MCD_OPC_FilterValue, 243, 1, 227, 12, 0, // Skip to: 18553 +/* 15254 */ MCD_OPC_CheckPredicate, 21, 222, 12, 0, // Skip to: 18553 +/* 15259 */ MCD_OPC_Decode, 177, 16, 102, // Opcode: VQSHLuv16i8 +/* 15263 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15301 +/* 15268 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15271 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15286 +/* 15277 */ MCD_OPC_CheckPredicate, 21, 199, 12, 0, // Skip to: 18553 +/* 15282 */ MCD_OPC_Decode, 167, 16, 102, // Opcode: VQSHLsv8i16 +/* 15286 */ MCD_OPC_FilterValue, 243, 1, 189, 12, 0, // Skip to: 18553 +/* 15292 */ MCD_OPC_CheckPredicate, 21, 184, 12, 0, // Skip to: 18553 +/* 15297 */ MCD_OPC_Decode, 183, 16, 102, // Opcode: VQSHLuv8i16 +/* 15301 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15339 +/* 15306 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15309 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15324 +/* 15315 */ MCD_OPC_CheckPredicate, 21, 161, 12, 0, // Skip to: 18553 +/* 15320 */ MCD_OPC_Decode, 166, 16, 102, // Opcode: VQSHLsv4i32 +/* 15324 */ MCD_OPC_FilterValue, 243, 1, 151, 12, 0, // Skip to: 18553 +/* 15330 */ MCD_OPC_CheckPredicate, 21, 146, 12, 0, // Skip to: 18553 +/* 15335 */ MCD_OPC_Decode, 182, 16, 102, // Opcode: VQSHLuv4i32 +/* 15339 */ MCD_OPC_FilterValue, 3, 137, 12, 0, // Skip to: 18553 +/* 15344 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15347 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15362 +/* 15353 */ MCD_OPC_CheckPredicate, 21, 123, 12, 0, // Skip to: 18553 +/* 15358 */ MCD_OPC_Decode, 164, 16, 102, // Opcode: VQSHLsv2i64 +/* 15362 */ MCD_OPC_FilterValue, 243, 1, 113, 12, 0, // Skip to: 18553 +/* 15368 */ MCD_OPC_CheckPredicate, 21, 108, 12, 0, // Skip to: 18553 +/* 15373 */ MCD_OPC_Decode, 180, 16, 102, // Opcode: VQSHLuv2i64 +/* 15377 */ MCD_OPC_FilterValue, 5, 155, 0, 0, // Skip to: 15537 +/* 15382 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 15385 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15423 +/* 15390 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15393 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15408 +/* 15399 */ MCD_OPC_CheckPredicate, 21, 77, 12, 0, // Skip to: 18553 +/* 15404 */ MCD_OPC_Decode, 248, 15, 102, // Opcode: VQRSHLsv16i8 +/* 15408 */ MCD_OPC_FilterValue, 243, 1, 67, 12, 0, // Skip to: 18553 +/* 15414 */ MCD_OPC_CheckPredicate, 21, 62, 12, 0, // Skip to: 18553 +/* 15419 */ MCD_OPC_Decode, 128, 16, 102, // Opcode: VQRSHLuv16i8 +/* 15423 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15461 +/* 15428 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15431 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15446 +/* 15437 */ MCD_OPC_CheckPredicate, 21, 39, 12, 0, // Skip to: 18553 +/* 15442 */ MCD_OPC_Decode, 254, 15, 102, // Opcode: VQRSHLsv8i16 +/* 15446 */ MCD_OPC_FilterValue, 243, 1, 29, 12, 0, // Skip to: 18553 +/* 15452 */ MCD_OPC_CheckPredicate, 21, 24, 12, 0, // Skip to: 18553 +/* 15457 */ MCD_OPC_Decode, 134, 16, 102, // Opcode: VQRSHLuv8i16 +/* 15461 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15499 +/* 15466 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15469 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15484 +/* 15475 */ MCD_OPC_CheckPredicate, 21, 1, 12, 0, // Skip to: 18553 +/* 15480 */ MCD_OPC_Decode, 253, 15, 102, // Opcode: VQRSHLsv4i32 +/* 15484 */ MCD_OPC_FilterValue, 243, 1, 247, 11, 0, // Skip to: 18553 +/* 15490 */ MCD_OPC_CheckPredicate, 21, 242, 11, 0, // Skip to: 18553 +/* 15495 */ MCD_OPC_Decode, 133, 16, 102, // Opcode: VQRSHLuv4i32 +/* 15499 */ MCD_OPC_FilterValue, 3, 233, 11, 0, // Skip to: 18553 +/* 15504 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15507 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15522 +/* 15513 */ MCD_OPC_CheckPredicate, 21, 219, 11, 0, // Skip to: 18553 +/* 15518 */ MCD_OPC_Decode, 251, 15, 102, // Opcode: VQRSHLsv2i64 +/* 15522 */ MCD_OPC_FilterValue, 243, 1, 209, 11, 0, // Skip to: 18553 +/* 15528 */ MCD_OPC_CheckPredicate, 21, 204, 11, 0, // Skip to: 18553 +/* 15533 */ MCD_OPC_Decode, 131, 16, 102, // Opcode: VQRSHLuv2i64 +/* 15537 */ MCD_OPC_FilterValue, 6, 117, 0, 0, // Skip to: 15659 +/* 15542 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 15545 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15583 +/* 15550 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15553 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15568 +/* 15559 */ MCD_OPC_CheckPredicate, 21, 173, 11, 0, // Skip to: 18553 +/* 15564 */ MCD_OPC_Decode, 190, 13, 98, // Opcode: VMINsv16i8 +/* 15568 */ MCD_OPC_FilterValue, 243, 1, 163, 11, 0, // Skip to: 18553 +/* 15574 */ MCD_OPC_CheckPredicate, 21, 158, 11, 0, // Skip to: 18553 +/* 15579 */ MCD_OPC_Decode, 196, 13, 98, // Opcode: VMINuv16i8 +/* 15583 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15621 +/* 15588 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15591 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15606 +/* 15597 */ MCD_OPC_CheckPredicate, 21, 135, 11, 0, // Skip to: 18553 +/* 15602 */ MCD_OPC_Decode, 194, 13, 98, // Opcode: VMINsv8i16 +/* 15606 */ MCD_OPC_FilterValue, 243, 1, 125, 11, 0, // Skip to: 18553 +/* 15612 */ MCD_OPC_CheckPredicate, 21, 120, 11, 0, // Skip to: 18553 +/* 15617 */ MCD_OPC_Decode, 200, 13, 98, // Opcode: VMINuv8i16 +/* 15621 */ MCD_OPC_FilterValue, 2, 111, 11, 0, // Skip to: 18553 +/* 15626 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15629 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15644 +/* 15635 */ MCD_OPC_CheckPredicate, 21, 97, 11, 0, // Skip to: 18553 +/* 15640 */ MCD_OPC_Decode, 193, 13, 98, // Opcode: VMINsv4i32 +/* 15644 */ MCD_OPC_FilterValue, 243, 1, 87, 11, 0, // Skip to: 18553 +/* 15650 */ MCD_OPC_CheckPredicate, 21, 82, 11, 0, // Skip to: 18553 +/* 15655 */ MCD_OPC_Decode, 199, 13, 98, // Opcode: VMINuv4i32 +/* 15659 */ MCD_OPC_FilterValue, 7, 117, 0, 0, // Skip to: 15781 +/* 15664 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 15667 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15705 +/* 15672 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15675 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15690 +/* 15681 */ MCD_OPC_CheckPredicate, 21, 51, 11, 0, // Skip to: 18553 +/* 15686 */ MCD_OPC_Decode, 180, 7, 106, // Opcode: VABAsv16i8 +/* 15690 */ MCD_OPC_FilterValue, 243, 1, 41, 11, 0, // Skip to: 18553 +/* 15696 */ MCD_OPC_CheckPredicate, 21, 36, 11, 0, // Skip to: 18553 +/* 15701 */ MCD_OPC_Decode, 186, 7, 106, // Opcode: VABAuv16i8 +/* 15705 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15743 +/* 15710 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15713 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15728 +/* 15719 */ MCD_OPC_CheckPredicate, 21, 13, 11, 0, // Skip to: 18553 +/* 15724 */ MCD_OPC_Decode, 184, 7, 106, // Opcode: VABAsv8i16 +/* 15728 */ MCD_OPC_FilterValue, 243, 1, 3, 11, 0, // Skip to: 18553 +/* 15734 */ MCD_OPC_CheckPredicate, 21, 254, 10, 0, // Skip to: 18553 +/* 15739 */ MCD_OPC_Decode, 190, 7, 106, // Opcode: VABAuv8i16 +/* 15743 */ MCD_OPC_FilterValue, 2, 245, 10, 0, // Skip to: 18553 +/* 15748 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15751 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15766 +/* 15757 */ MCD_OPC_CheckPredicate, 21, 231, 10, 0, // Skip to: 18553 +/* 15762 */ MCD_OPC_Decode, 183, 7, 106, // Opcode: VABAsv4i32 +/* 15766 */ MCD_OPC_FilterValue, 243, 1, 221, 10, 0, // Skip to: 18553 +/* 15772 */ MCD_OPC_CheckPredicate, 21, 216, 10, 0, // Skip to: 18553 +/* 15777 */ MCD_OPC_Decode, 189, 7, 106, // Opcode: VABAuv4i32 +/* 15781 */ MCD_OPC_FilterValue, 8, 117, 0, 0, // Skip to: 15903 +/* 15786 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 15789 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15827 +/* 15794 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15797 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15812 +/* 15803 */ MCD_OPC_CheckPredicate, 21, 185, 10, 0, // Skip to: 18553 +/* 15808 */ MCD_OPC_Decode, 153, 21, 98, // Opcode: VTSTv16i8 +/* 15812 */ MCD_OPC_FilterValue, 243, 1, 175, 10, 0, // Skip to: 18553 +/* 15818 */ MCD_OPC_CheckPredicate, 21, 170, 10, 0, // Skip to: 18553 +/* 15823 */ MCD_OPC_Decode, 159, 8, 98, // Opcode: VCEQv16i8 +/* 15827 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15865 +/* 15832 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15835 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15850 +/* 15841 */ MCD_OPC_CheckPredicate, 21, 147, 10, 0, // Skip to: 18553 +/* 15846 */ MCD_OPC_Decode, 157, 21, 98, // Opcode: VTSTv8i16 +/* 15850 */ MCD_OPC_FilterValue, 243, 1, 137, 10, 0, // Skip to: 18553 +/* 15856 */ MCD_OPC_CheckPredicate, 21, 132, 10, 0, // Skip to: 18553 +/* 15861 */ MCD_OPC_Decode, 163, 8, 98, // Opcode: VCEQv8i16 +/* 15865 */ MCD_OPC_FilterValue, 2, 123, 10, 0, // Skip to: 18553 +/* 15870 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15873 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15888 +/* 15879 */ MCD_OPC_CheckPredicate, 21, 109, 10, 0, // Skip to: 18553 +/* 15884 */ MCD_OPC_Decode, 156, 21, 98, // Opcode: VTSTv4i32 +/* 15888 */ MCD_OPC_FilterValue, 243, 1, 99, 10, 0, // Skip to: 18553 +/* 15894 */ MCD_OPC_CheckPredicate, 21, 94, 10, 0, // Skip to: 18553 +/* 15899 */ MCD_OPC_Decode, 162, 8, 98, // Opcode: VCEQv4i32 +/* 15903 */ MCD_OPC_FilterValue, 9, 85, 0, 0, // Skip to: 15993 +/* 15908 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 15911 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15949 +/* 15916 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 15919 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15934 +/* 15925 */ MCD_OPC_CheckPredicate, 21, 63, 10, 0, // Skip to: 18553 +/* 15930 */ MCD_OPC_Decode, 208, 14, 98, // Opcode: VMULv16i8 +/* 15934 */ MCD_OPC_FilterValue, 243, 1, 53, 10, 0, // Skip to: 18553 +/* 15940 */ MCD_OPC_CheckPredicate, 21, 48, 10, 0, // Skip to: 18553 +/* 15945 */ MCD_OPC_Decode, 199, 14, 98, // Opcode: VMULpq +/* 15949 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 15971 +/* 15954 */ MCD_OPC_CheckPredicate, 21, 34, 10, 0, // Skip to: 18553 +/* 15959 */ MCD_OPC_CheckField, 24, 8, 242, 1, 26, 10, 0, // Skip to: 18553 +/* 15967 */ MCD_OPC_Decode, 212, 14, 98, // Opcode: VMULv8i16 +/* 15971 */ MCD_OPC_FilterValue, 2, 17, 10, 0, // Skip to: 18553 +/* 15976 */ MCD_OPC_CheckPredicate, 21, 12, 10, 0, // Skip to: 18553 +/* 15981 */ MCD_OPC_CheckField, 24, 8, 242, 1, 4, 10, 0, // Skip to: 18553 +/* 15989 */ MCD_OPC_Decode, 211, 14, 98, // Opcode: VMULv4i32 +/* 15993 */ MCD_OPC_FilterValue, 11, 47, 0, 0, // Skip to: 16045 +/* 15998 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 16001 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16023 +/* 16006 */ MCD_OPC_CheckPredicate, 23, 238, 9, 0, // Skip to: 18553 +/* 16011 */ MCD_OPC_CheckField, 24, 8, 243, 1, 230, 9, 0, // Skip to: 18553 +/* 16019 */ MCD_OPC_Decode, 231, 15, 106, // Opcode: VQRDMLAHv8i16 +/* 16023 */ MCD_OPC_FilterValue, 2, 221, 9, 0, // Skip to: 18553 +/* 16028 */ MCD_OPC_CheckPredicate, 23, 216, 9, 0, // Skip to: 18553 +/* 16033 */ MCD_OPC_CheckField, 24, 8, 243, 1, 208, 9, 0, // Skip to: 18553 +/* 16041 */ MCD_OPC_Decode, 230, 15, 106, // Opcode: VQRDMLAHv4i32 +/* 16045 */ MCD_OPC_FilterValue, 12, 123, 0, 0, // Skip to: 16173 +/* 16050 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 16053 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16075 +/* 16058 */ MCD_OPC_CheckPredicate, 26, 186, 9, 0, // Skip to: 18553 +/* 16063 */ MCD_OPC_CheckField, 24, 8, 242, 1, 178, 9, 0, // Skip to: 18553 +/* 16071 */ MCD_OPC_Decode, 153, 10, 106, // Opcode: VFMAfq +/* 16075 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16113 +/* 16080 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 16083 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16098 +/* 16089 */ MCD_OPC_CheckPredicate, 22, 155, 9, 0, // Skip to: 18553 +/* 16094 */ MCD_OPC_Decode, 155, 10, 106, // Opcode: VFMAhq +/* 16098 */ MCD_OPC_FilterValue, 243, 1, 145, 9, 0, // Skip to: 18553 +/* 16104 */ MCD_OPC_CheckPredicate, 23, 140, 9, 0, // Skip to: 18553 +/* 16109 */ MCD_OPC_Decode, 239, 15, 106, // Opcode: VQRDMLSHv8i16 +/* 16113 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 16151 +/* 16118 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 16121 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16136 +/* 16127 */ MCD_OPC_CheckPredicate, 26, 117, 9, 0, // Skip to: 18553 +/* 16132 */ MCD_OPC_Decode, 160, 10, 106, // Opcode: VFMSfq +/* 16136 */ MCD_OPC_FilterValue, 243, 1, 107, 9, 0, // Skip to: 18553 +/* 16142 */ MCD_OPC_CheckPredicate, 23, 102, 9, 0, // Skip to: 18553 +/* 16147 */ MCD_OPC_Decode, 238, 15, 106, // Opcode: VQRDMLSHv4i32 +/* 16151 */ MCD_OPC_FilterValue, 3, 93, 9, 0, // Skip to: 18553 +/* 16156 */ MCD_OPC_CheckPredicate, 22, 88, 9, 0, // Skip to: 18553 +/* 16161 */ MCD_OPC_CheckField, 24, 8, 242, 1, 80, 9, 0, // Skip to: 18553 +/* 16169 */ MCD_OPC_Decode, 162, 10, 106, // Opcode: VFMShq +/* 16173 */ MCD_OPC_FilterValue, 13, 123, 0, 0, // Skip to: 16301 +/* 16178 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 16181 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 16219 +/* 16186 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 16189 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16204 +/* 16195 */ MCD_OPC_CheckPredicate, 21, 49, 9, 0, // Skip to: 18553 +/* 16200 */ MCD_OPC_Decode, 216, 13, 106, // Opcode: VMLAfq +/* 16204 */ MCD_OPC_FilterValue, 243, 1, 39, 9, 0, // Skip to: 18553 +/* 16210 */ MCD_OPC_CheckPredicate, 21, 34, 9, 0, // Skip to: 18553 +/* 16215 */ MCD_OPC_Decode, 195, 14, 98, // Opcode: VMULfq +/* 16219 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16257 +/* 16224 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 16227 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16242 +/* 16233 */ MCD_OPC_CheckPredicate, 22, 11, 9, 0, // Skip to: 18553 +/* 16238 */ MCD_OPC_Decode, 218, 13, 106, // Opcode: VMLAhq +/* 16242 */ MCD_OPC_FilterValue, 243, 1, 1, 9, 0, // Skip to: 18553 +/* 16248 */ MCD_OPC_CheckPredicate, 22, 252, 8, 0, // Skip to: 18553 +/* 16253 */ MCD_OPC_Decode, 197, 14, 98, // Opcode: VMULhq +/* 16257 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16279 +/* 16262 */ MCD_OPC_CheckPredicate, 21, 238, 8, 0, // Skip to: 18553 +/* 16267 */ MCD_OPC_CheckField, 24, 8, 242, 1, 230, 8, 0, // Skip to: 18553 +/* 16275 */ MCD_OPC_Decode, 247, 13, 106, // Opcode: VMLSfq +/* 16279 */ MCD_OPC_FilterValue, 3, 221, 8, 0, // Skip to: 18553 +/* 16284 */ MCD_OPC_CheckPredicate, 22, 216, 8, 0, // Skip to: 18553 +/* 16289 */ MCD_OPC_CheckField, 24, 8, 242, 1, 208, 8, 0, // Skip to: 18553 +/* 16297 */ MCD_OPC_Decode, 249, 13, 106, // Opcode: VMLShq +/* 16301 */ MCD_OPC_FilterValue, 14, 91, 0, 0, // Skip to: 16397 +/* 16306 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 16309 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16331 +/* 16314 */ MCD_OPC_CheckPredicate, 21, 186, 8, 0, // Skip to: 18553 +/* 16319 */ MCD_OPC_CheckField, 24, 8, 243, 1, 178, 8, 0, // Skip to: 18553 +/* 16327 */ MCD_OPC_Decode, 228, 7, 98, // Opcode: VACGEfq +/* 16331 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16353 +/* 16336 */ MCD_OPC_CheckPredicate, 22, 164, 8, 0, // Skip to: 18553 +/* 16341 */ MCD_OPC_CheckField, 24, 8, 243, 1, 156, 8, 0, // Skip to: 18553 +/* 16349 */ MCD_OPC_Decode, 230, 7, 98, // Opcode: VACGEhq +/* 16353 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16375 +/* 16358 */ MCD_OPC_CheckPredicate, 21, 142, 8, 0, // Skip to: 18553 +/* 16363 */ MCD_OPC_CheckField, 24, 8, 243, 1, 134, 8, 0, // Skip to: 18553 +/* 16371 */ MCD_OPC_Decode, 232, 7, 98, // Opcode: VACGTfq +/* 16375 */ MCD_OPC_FilterValue, 3, 125, 8, 0, // Skip to: 18553 +/* 16380 */ MCD_OPC_CheckPredicate, 22, 120, 8, 0, // Skip to: 18553 +/* 16385 */ MCD_OPC_CheckField, 24, 8, 243, 1, 112, 8, 0, // Skip to: 18553 +/* 16393 */ MCD_OPC_Decode, 234, 7, 98, // Opcode: VACGThq +/* 16397 */ MCD_OPC_FilterValue, 15, 103, 8, 0, // Skip to: 18553 +/* 16402 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 16405 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16427 +/* 16410 */ MCD_OPC_CheckPredicate, 21, 90, 8, 0, // Skip to: 18553 +/* 16415 */ MCD_OPC_CheckField, 24, 8, 242, 1, 82, 8, 0, // Skip to: 18553 +/* 16423 */ MCD_OPC_Decode, 220, 16, 98, // Opcode: VRECPSfq +/* 16427 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16449 +/* 16432 */ MCD_OPC_CheckPredicate, 22, 68, 8, 0, // Skip to: 18553 +/* 16437 */ MCD_OPC_CheckField, 24, 8, 242, 1, 60, 8, 0, // Skip to: 18553 +/* 16445 */ MCD_OPC_Decode, 222, 16, 98, // Opcode: VRECPShq +/* 16449 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16471 +/* 16454 */ MCD_OPC_CheckPredicate, 21, 46, 8, 0, // Skip to: 18553 +/* 16459 */ MCD_OPC_CheckField, 24, 8, 242, 1, 38, 8, 0, // Skip to: 18553 +/* 16467 */ MCD_OPC_Decode, 206, 17, 98, // Opcode: VRSQRTSfq +/* 16471 */ MCD_OPC_FilterValue, 3, 29, 8, 0, // Skip to: 18553 +/* 16476 */ MCD_OPC_CheckPredicate, 22, 24, 8, 0, // Skip to: 18553 +/* 16481 */ MCD_OPC_CheckField, 24, 8, 242, 1, 16, 8, 0, // Skip to: 18553 +/* 16489 */ MCD_OPC_Decode, 208, 17, 98, // Opcode: VRSQRTShq +/* 16493 */ MCD_OPC_FilterValue, 1, 7, 8, 0, // Skip to: 18553 +/* 16498 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 16501 */ MCD_OPC_FilterValue, 0, 217, 6, 0, // Skip to: 18259 +/* 16506 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... +/* 16509 */ MCD_OPC_FilterValue, 121, 247, 7, 0, // Skip to: 18553 +/* 16514 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 16517 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 16661 +/* 16522 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 16525 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16623 +/* 16530 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 16533 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16585 +/* 16538 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 16541 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16563 +/* 16546 */ MCD_OPC_CheckPredicate, 21, 239, 5, 0, // Skip to: 18070 +/* 16551 */ MCD_OPC_CheckField, 19, 1, 1, 232, 5, 0, // Skip to: 18070 +/* 16558 */ MCD_OPC_Decode, 155, 18, 166, 1, // Opcode: VSHRsv16i8 +/* 16563 */ MCD_OPC_FilterValue, 1, 222, 5, 0, // Skip to: 18070 +/* 16568 */ MCD_OPC_CheckPredicate, 21, 217, 5, 0, // Skip to: 18070 +/* 16573 */ MCD_OPC_CheckField, 19, 1, 1, 210, 5, 0, // Skip to: 18070 +/* 16580 */ MCD_OPC_Decode, 163, 18, 166, 1, // Opcode: VSHRuv16i8 +/* 16585 */ MCD_OPC_FilterValue, 1, 200, 5, 0, // Skip to: 18070 +/* 16590 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 16593 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16608 +/* 16598 */ MCD_OPC_CheckPredicate, 21, 187, 5, 0, // Skip to: 18070 +/* 16603 */ MCD_OPC_Decode, 161, 18, 167, 1, // Opcode: VSHRsv8i16 +/* 16608 */ MCD_OPC_FilterValue, 1, 177, 5, 0, // Skip to: 18070 +/* 16613 */ MCD_OPC_CheckPredicate, 21, 172, 5, 0, // Skip to: 18070 +/* 16618 */ MCD_OPC_Decode, 169, 18, 167, 1, // Opcode: VSHRuv8i16 +/* 16623 */ MCD_OPC_FilterValue, 1, 162, 5, 0, // Skip to: 18070 +/* 16628 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 16631 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16646 +/* 16636 */ MCD_OPC_CheckPredicate, 21, 149, 5, 0, // Skip to: 18070 +/* 16641 */ MCD_OPC_Decode, 160, 18, 168, 1, // Opcode: VSHRsv4i32 +/* 16646 */ MCD_OPC_FilterValue, 1, 139, 5, 0, // Skip to: 18070 +/* 16651 */ MCD_OPC_CheckPredicate, 21, 134, 5, 0, // Skip to: 18070 +/* 16656 */ MCD_OPC_Decode, 168, 18, 168, 1, // Opcode: VSHRuv4i32 +/* 16661 */ MCD_OPC_FilterValue, 1, 139, 0, 0, // Skip to: 16805 +/* 16666 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 16669 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16767 +/* 16674 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 16677 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16729 +/* 16682 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 16685 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16707 +/* 16690 */ MCD_OPC_CheckPredicate, 21, 95, 5, 0, // Skip to: 18070 +/* 16695 */ MCD_OPC_CheckField, 19, 1, 1, 88, 5, 0, // Skip to: 18070 +/* 16702 */ MCD_OPC_Decode, 191, 18, 169, 1, // Opcode: VSRAsv16i8 +/* 16707 */ MCD_OPC_FilterValue, 1, 78, 5, 0, // Skip to: 18070 +/* 16712 */ MCD_OPC_CheckPredicate, 21, 73, 5, 0, // Skip to: 18070 +/* 16717 */ MCD_OPC_CheckField, 19, 1, 1, 66, 5, 0, // Skip to: 18070 +/* 16724 */ MCD_OPC_Decode, 199, 18, 169, 1, // Opcode: VSRAuv16i8 +/* 16729 */ MCD_OPC_FilterValue, 1, 56, 5, 0, // Skip to: 18070 +/* 16734 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 16737 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16752 +/* 16742 */ MCD_OPC_CheckPredicate, 21, 43, 5, 0, // Skip to: 18070 +/* 16747 */ MCD_OPC_Decode, 197, 18, 170, 1, // Opcode: VSRAsv8i16 +/* 16752 */ MCD_OPC_FilterValue, 1, 33, 5, 0, // Skip to: 18070 +/* 16757 */ MCD_OPC_CheckPredicate, 21, 28, 5, 0, // Skip to: 18070 +/* 16762 */ MCD_OPC_Decode, 205, 18, 170, 1, // Opcode: VSRAuv8i16 +/* 16767 */ MCD_OPC_FilterValue, 1, 18, 5, 0, // Skip to: 18070 +/* 16772 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 16775 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16790 +/* 16780 */ MCD_OPC_CheckPredicate, 21, 5, 5, 0, // Skip to: 18070 +/* 16785 */ MCD_OPC_Decode, 196, 18, 171, 1, // Opcode: VSRAsv4i32 +/* 16790 */ MCD_OPC_FilterValue, 1, 251, 4, 0, // Skip to: 18070 +/* 16795 */ MCD_OPC_CheckPredicate, 21, 246, 4, 0, // Skip to: 18070 +/* 16800 */ MCD_OPC_Decode, 204, 18, 171, 1, // Opcode: VSRAuv4i32 +/* 16805 */ MCD_OPC_FilterValue, 2, 139, 0, 0, // Skip to: 16949 +/* 16810 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 16813 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16911 +/* 16818 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 16821 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16873 +/* 16826 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 16829 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16851 +/* 16834 */ MCD_OPC_CheckPredicate, 21, 207, 4, 0, // Skip to: 18070 +/* 16839 */ MCD_OPC_CheckField, 19, 1, 1, 200, 4, 0, // Skip to: 18070 +/* 16846 */ MCD_OPC_Decode, 183, 17, 166, 1, // Opcode: VRSHRsv16i8 +/* 16851 */ MCD_OPC_FilterValue, 1, 190, 4, 0, // Skip to: 18070 +/* 16856 */ MCD_OPC_CheckPredicate, 21, 185, 4, 0, // Skip to: 18070 +/* 16861 */ MCD_OPC_CheckField, 19, 1, 1, 178, 4, 0, // Skip to: 18070 +/* 16868 */ MCD_OPC_Decode, 191, 17, 166, 1, // Opcode: VRSHRuv16i8 +/* 16873 */ MCD_OPC_FilterValue, 1, 168, 4, 0, // Skip to: 18070 +/* 16878 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 16881 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16896 +/* 16886 */ MCD_OPC_CheckPredicate, 21, 155, 4, 0, // Skip to: 18070 +/* 16891 */ MCD_OPC_Decode, 189, 17, 167, 1, // Opcode: VRSHRsv8i16 +/* 16896 */ MCD_OPC_FilterValue, 1, 145, 4, 0, // Skip to: 18070 +/* 16901 */ MCD_OPC_CheckPredicate, 21, 140, 4, 0, // Skip to: 18070 +/* 16906 */ MCD_OPC_Decode, 197, 17, 167, 1, // Opcode: VRSHRuv8i16 +/* 16911 */ MCD_OPC_FilterValue, 1, 130, 4, 0, // Skip to: 18070 +/* 16916 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 16919 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16934 +/* 16924 */ MCD_OPC_CheckPredicate, 21, 117, 4, 0, // Skip to: 18070 +/* 16929 */ MCD_OPC_Decode, 188, 17, 168, 1, // Opcode: VRSHRsv4i32 +/* 16934 */ MCD_OPC_FilterValue, 1, 107, 4, 0, // Skip to: 18070 +/* 16939 */ MCD_OPC_CheckPredicate, 21, 102, 4, 0, // Skip to: 18070 +/* 16944 */ MCD_OPC_Decode, 196, 17, 168, 1, // Opcode: VRSHRuv4i32 +/* 16949 */ MCD_OPC_FilterValue, 3, 139, 0, 0, // Skip to: 17093 +/* 16954 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 16957 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17055 +/* 16962 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 16965 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17017 +/* 16970 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 16973 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16995 +/* 16978 */ MCD_OPC_CheckPredicate, 21, 63, 4, 0, // Skip to: 18070 +/* 16983 */ MCD_OPC_CheckField, 19, 1, 1, 56, 4, 0, // Skip to: 18070 +/* 16990 */ MCD_OPC_Decode, 209, 17, 169, 1, // Opcode: VRSRAsv16i8 +/* 16995 */ MCD_OPC_FilterValue, 1, 46, 4, 0, // Skip to: 18070 +/* 17000 */ MCD_OPC_CheckPredicate, 21, 41, 4, 0, // Skip to: 18070 +/* 17005 */ MCD_OPC_CheckField, 19, 1, 1, 34, 4, 0, // Skip to: 18070 +/* 17012 */ MCD_OPC_Decode, 217, 17, 169, 1, // Opcode: VRSRAuv16i8 +/* 17017 */ MCD_OPC_FilterValue, 1, 24, 4, 0, // Skip to: 18070 +/* 17022 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17025 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17040 +/* 17030 */ MCD_OPC_CheckPredicate, 21, 11, 4, 0, // Skip to: 18070 +/* 17035 */ MCD_OPC_Decode, 215, 17, 170, 1, // Opcode: VRSRAsv8i16 +/* 17040 */ MCD_OPC_FilterValue, 1, 1, 4, 0, // Skip to: 18070 +/* 17045 */ MCD_OPC_CheckPredicate, 21, 252, 3, 0, // Skip to: 18070 +/* 17050 */ MCD_OPC_Decode, 223, 17, 170, 1, // Opcode: VRSRAuv8i16 +/* 17055 */ MCD_OPC_FilterValue, 1, 242, 3, 0, // Skip to: 18070 +/* 17060 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17063 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17078 +/* 17068 */ MCD_OPC_CheckPredicate, 21, 229, 3, 0, // Skip to: 18070 +/* 17073 */ MCD_OPC_Decode, 214, 17, 171, 1, // Opcode: VRSRAsv4i32 +/* 17078 */ MCD_OPC_FilterValue, 1, 219, 3, 0, // Skip to: 18070 +/* 17083 */ MCD_OPC_CheckPredicate, 21, 214, 3, 0, // Skip to: 18070 +/* 17088 */ MCD_OPC_Decode, 222, 17, 171, 1, // Opcode: VRSRAuv4i32 +/* 17093 */ MCD_OPC_FilterValue, 4, 84, 0, 0, // Skip to: 17182 +/* 17098 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 17101 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 17160 +/* 17106 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 17109 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 17138 +/* 17114 */ MCD_OPC_CheckPredicate, 21, 183, 3, 0, // Skip to: 18070 +/* 17119 */ MCD_OPC_CheckField, 24, 1, 1, 176, 3, 0, // Skip to: 18070 +/* 17126 */ MCD_OPC_CheckField, 19, 1, 1, 169, 3, 0, // Skip to: 18070 +/* 17133 */ MCD_OPC_Decode, 207, 18, 169, 1, // Opcode: VSRIv16i8 +/* 17138 */ MCD_OPC_FilterValue, 1, 159, 3, 0, // Skip to: 18070 +/* 17143 */ MCD_OPC_CheckPredicate, 21, 154, 3, 0, // Skip to: 18070 +/* 17148 */ MCD_OPC_CheckField, 24, 1, 1, 147, 3, 0, // Skip to: 18070 +/* 17155 */ MCD_OPC_Decode, 213, 18, 170, 1, // Opcode: VSRIv8i16 +/* 17160 */ MCD_OPC_FilterValue, 1, 137, 3, 0, // Skip to: 18070 +/* 17165 */ MCD_OPC_CheckPredicate, 21, 132, 3, 0, // Skip to: 18070 +/* 17170 */ MCD_OPC_CheckField, 24, 1, 1, 125, 3, 0, // Skip to: 18070 +/* 17177 */ MCD_OPC_Decode, 212, 18, 171, 1, // Opcode: VSRIv4i32 +/* 17182 */ MCD_OPC_FilterValue, 5, 139, 0, 0, // Skip to: 17326 +/* 17187 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 17190 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17288 +/* 17195 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 17198 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17250 +/* 17203 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17206 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17228 +/* 17211 */ MCD_OPC_CheckPredicate, 21, 86, 3, 0, // Skip to: 18070 +/* 17216 */ MCD_OPC_CheckField, 19, 1, 1, 79, 3, 0, // Skip to: 18070 +/* 17223 */ MCD_OPC_Decode, 128, 18, 172, 1, // Opcode: VSHLiv16i8 +/* 17228 */ MCD_OPC_FilterValue, 1, 69, 3, 0, // Skip to: 18070 +/* 17233 */ MCD_OPC_CheckPredicate, 21, 64, 3, 0, // Skip to: 18070 +/* 17238 */ MCD_OPC_CheckField, 19, 1, 1, 57, 3, 0, // Skip to: 18070 +/* 17245 */ MCD_OPC_Decode, 177, 18, 173, 1, // Opcode: VSLIv16i8 +/* 17250 */ MCD_OPC_FilterValue, 1, 47, 3, 0, // Skip to: 18070 +/* 17255 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17258 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17273 +/* 17263 */ MCD_OPC_CheckPredicate, 21, 34, 3, 0, // Skip to: 18070 +/* 17268 */ MCD_OPC_Decode, 134, 18, 174, 1, // Opcode: VSHLiv8i16 +/* 17273 */ MCD_OPC_FilterValue, 1, 24, 3, 0, // Skip to: 18070 +/* 17278 */ MCD_OPC_CheckPredicate, 21, 19, 3, 0, // Skip to: 18070 +/* 17283 */ MCD_OPC_Decode, 183, 18, 175, 1, // Opcode: VSLIv8i16 +/* 17288 */ MCD_OPC_FilterValue, 1, 9, 3, 0, // Skip to: 18070 +/* 17293 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17296 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17311 +/* 17301 */ MCD_OPC_CheckPredicate, 21, 252, 2, 0, // Skip to: 18070 +/* 17306 */ MCD_OPC_Decode, 133, 18, 176, 1, // Opcode: VSHLiv4i32 +/* 17311 */ MCD_OPC_FilterValue, 1, 242, 2, 0, // Skip to: 18070 +/* 17316 */ MCD_OPC_CheckPredicate, 21, 237, 2, 0, // Skip to: 18070 +/* 17321 */ MCD_OPC_Decode, 182, 18, 177, 1, // Opcode: VSLIv4i32 +/* 17326 */ MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 17415 +/* 17331 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 17334 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 17393 +/* 17339 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 17342 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 17371 +/* 17347 */ MCD_OPC_CheckPredicate, 21, 206, 2, 0, // Skip to: 18070 +/* 17352 */ MCD_OPC_CheckField, 24, 1, 1, 199, 2, 0, // Skip to: 18070 +/* 17359 */ MCD_OPC_CheckField, 19, 1, 1, 192, 2, 0, // Skip to: 18070 +/* 17366 */ MCD_OPC_Decode, 153, 16, 172, 1, // Opcode: VQSHLsuv16i8 +/* 17371 */ MCD_OPC_FilterValue, 1, 182, 2, 0, // Skip to: 18070 +/* 17376 */ MCD_OPC_CheckPredicate, 21, 177, 2, 0, // Skip to: 18070 +/* 17381 */ MCD_OPC_CheckField, 24, 1, 1, 170, 2, 0, // Skip to: 18070 +/* 17388 */ MCD_OPC_Decode, 159, 16, 174, 1, // Opcode: VQSHLsuv8i16 +/* 17393 */ MCD_OPC_FilterValue, 1, 160, 2, 0, // Skip to: 18070 +/* 17398 */ MCD_OPC_CheckPredicate, 21, 155, 2, 0, // Skip to: 18070 +/* 17403 */ MCD_OPC_CheckField, 24, 1, 1, 148, 2, 0, // Skip to: 18070 +/* 17410 */ MCD_OPC_Decode, 158, 16, 176, 1, // Opcode: VQSHLsuv4i32 +/* 17415 */ MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 17559 +/* 17420 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 17423 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17521 +/* 17428 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 17431 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17483 +/* 17436 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17439 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17461 +/* 17444 */ MCD_OPC_CheckPredicate, 21, 109, 2, 0, // Skip to: 18070 +/* 17449 */ MCD_OPC_CheckField, 19, 1, 1, 102, 2, 0, // Skip to: 18070 +/* 17456 */ MCD_OPC_Decode, 145, 16, 172, 1, // Opcode: VQSHLsiv16i8 +/* 17461 */ MCD_OPC_FilterValue, 1, 92, 2, 0, // Skip to: 18070 +/* 17466 */ MCD_OPC_CheckPredicate, 21, 87, 2, 0, // Skip to: 18070 +/* 17471 */ MCD_OPC_CheckField, 19, 1, 1, 80, 2, 0, // Skip to: 18070 +/* 17478 */ MCD_OPC_Decode, 169, 16, 172, 1, // Opcode: VQSHLuiv16i8 +/* 17483 */ MCD_OPC_FilterValue, 1, 70, 2, 0, // Skip to: 18070 +/* 17488 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17491 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17506 +/* 17496 */ MCD_OPC_CheckPredicate, 21, 57, 2, 0, // Skip to: 18070 +/* 17501 */ MCD_OPC_Decode, 151, 16, 174, 1, // Opcode: VQSHLsiv8i16 +/* 17506 */ MCD_OPC_FilterValue, 1, 47, 2, 0, // Skip to: 18070 +/* 17511 */ MCD_OPC_CheckPredicate, 21, 42, 2, 0, // Skip to: 18070 +/* 17516 */ MCD_OPC_Decode, 175, 16, 174, 1, // Opcode: VQSHLuiv8i16 +/* 17521 */ MCD_OPC_FilterValue, 1, 32, 2, 0, // Skip to: 18070 +/* 17526 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17529 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17544 +/* 17534 */ MCD_OPC_CheckPredicate, 21, 19, 2, 0, // Skip to: 18070 +/* 17539 */ MCD_OPC_Decode, 150, 16, 176, 1, // Opcode: VQSHLsiv4i32 +/* 17544 */ MCD_OPC_FilterValue, 1, 9, 2, 0, // Skip to: 18070 +/* 17549 */ MCD_OPC_CheckPredicate, 21, 4, 2, 0, // Skip to: 18070 +/* 17554 */ MCD_OPC_Decode, 174, 16, 176, 1, // Opcode: VQSHLuiv4i32 +/* 17559 */ MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 17703 +/* 17564 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 17567 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17665 +/* 17572 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 17575 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17627 +/* 17580 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17583 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17605 +/* 17588 */ MCD_OPC_CheckPredicate, 21, 221, 1, 0, // Skip to: 18070 +/* 17593 */ MCD_OPC_CheckField, 19, 1, 1, 214, 1, 0, // Skip to: 18070 +/* 17600 */ MCD_OPC_Decode, 182, 17, 154, 1, // Opcode: VRSHRNv8i8 +/* 17605 */ MCD_OPC_FilterValue, 1, 204, 1, 0, // Skip to: 18070 +/* 17610 */ MCD_OPC_CheckPredicate, 21, 199, 1, 0, // Skip to: 18070 +/* 17615 */ MCD_OPC_CheckField, 19, 1, 1, 192, 1, 0, // Skip to: 18070 +/* 17622 */ MCD_OPC_Decode, 144, 16, 154, 1, // Opcode: VQRSHRUNv8i8 +/* 17627 */ MCD_OPC_FilterValue, 1, 182, 1, 0, // Skip to: 18070 +/* 17632 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17635 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17650 +/* 17640 */ MCD_OPC_CheckPredicate, 21, 169, 1, 0, // Skip to: 18070 +/* 17645 */ MCD_OPC_Decode, 181, 17, 155, 1, // Opcode: VRSHRNv4i16 +/* 17650 */ MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 18070 +/* 17655 */ MCD_OPC_CheckPredicate, 21, 154, 1, 0, // Skip to: 18070 +/* 17660 */ MCD_OPC_Decode, 143, 16, 155, 1, // Opcode: VQRSHRUNv4i16 +/* 17665 */ MCD_OPC_FilterValue, 1, 144, 1, 0, // Skip to: 18070 +/* 17670 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17673 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17688 +/* 17678 */ MCD_OPC_CheckPredicate, 21, 131, 1, 0, // Skip to: 18070 +/* 17683 */ MCD_OPC_Decode, 180, 17, 156, 1, // Opcode: VRSHRNv2i32 +/* 17688 */ MCD_OPC_FilterValue, 1, 121, 1, 0, // Skip to: 18070 +/* 17693 */ MCD_OPC_CheckPredicate, 21, 116, 1, 0, // Skip to: 18070 +/* 17698 */ MCD_OPC_Decode, 142, 16, 156, 1, // Opcode: VQRSHRUNv2i32 +/* 17703 */ MCD_OPC_FilterValue, 9, 139, 0, 0, // Skip to: 17847 +/* 17708 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 17711 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17809 +/* 17716 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 17719 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17771 +/* 17724 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17727 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17749 +/* 17732 */ MCD_OPC_CheckPredicate, 21, 77, 1, 0, // Skip to: 18070 +/* 17737 */ MCD_OPC_CheckField, 19, 1, 1, 70, 1, 0, // Skip to: 18070 +/* 17744 */ MCD_OPC_Decode, 138, 16, 154, 1, // Opcode: VQRSHRNsv8i8 +/* 17749 */ MCD_OPC_FilterValue, 1, 60, 1, 0, // Skip to: 18070 +/* 17754 */ MCD_OPC_CheckPredicate, 21, 55, 1, 0, // Skip to: 18070 +/* 17759 */ MCD_OPC_CheckField, 19, 1, 1, 48, 1, 0, // Skip to: 18070 +/* 17766 */ MCD_OPC_Decode, 141, 16, 154, 1, // Opcode: VQRSHRNuv8i8 +/* 17771 */ MCD_OPC_FilterValue, 1, 38, 1, 0, // Skip to: 18070 +/* 17776 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17779 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17794 +/* 17784 */ MCD_OPC_CheckPredicate, 21, 25, 1, 0, // Skip to: 18070 +/* 17789 */ MCD_OPC_Decode, 137, 16, 155, 1, // Opcode: VQRSHRNsv4i16 +/* 17794 */ MCD_OPC_FilterValue, 1, 15, 1, 0, // Skip to: 18070 +/* 17799 */ MCD_OPC_CheckPredicate, 21, 10, 1, 0, // Skip to: 18070 +/* 17804 */ MCD_OPC_Decode, 140, 16, 155, 1, // Opcode: VQRSHRNuv4i16 +/* 17809 */ MCD_OPC_FilterValue, 1, 0, 1, 0, // Skip to: 18070 +/* 17814 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17817 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17832 +/* 17822 */ MCD_OPC_CheckPredicate, 21, 243, 0, 0, // Skip to: 18070 +/* 17827 */ MCD_OPC_Decode, 136, 16, 156, 1, // Opcode: VQRSHRNsv2i32 +/* 17832 */ MCD_OPC_FilterValue, 1, 233, 0, 0, // Skip to: 18070 +/* 17837 */ MCD_OPC_CheckPredicate, 21, 228, 0, 0, // Skip to: 18070 +/* 17842 */ MCD_OPC_Decode, 139, 16, 156, 1, // Opcode: VQRSHRNuv2i32 +/* 17847 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 17885 +/* 17852 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17855 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17870 +/* 17860 */ MCD_OPC_CheckPredicate, 22, 205, 0, 0, // Skip to: 18070 +/* 17865 */ MCD_OPC_Decode, 248, 9, 178, 1, // Opcode: VCVTxs2hq +/* 17870 */ MCD_OPC_FilterValue, 1, 195, 0, 0, // Skip to: 18070 +/* 17875 */ MCD_OPC_CheckPredicate, 22, 190, 0, 0, // Skip to: 18070 +/* 17880 */ MCD_OPC_Decode, 252, 9, 178, 1, // Opcode: VCVTxu2hq +/* 17885 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 17923 +/* 17890 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17893 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17908 +/* 17898 */ MCD_OPC_CheckPredicate, 22, 167, 0, 0, // Skip to: 18070 +/* 17903 */ MCD_OPC_Decode, 234, 9, 178, 1, // Opcode: VCVTh2xsq +/* 17908 */ MCD_OPC_FilterValue, 1, 157, 0, 0, // Skip to: 18070 +/* 17913 */ MCD_OPC_CheckPredicate, 22, 152, 0, 0, // Skip to: 18070 +/* 17918 */ MCD_OPC_Decode, 236, 9, 178, 1, // Opcode: VCVTh2xuq +/* 17923 */ MCD_OPC_FilterValue, 14, 80, 0, 0, // Skip to: 18008 +/* 17928 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 17931 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17953 +/* 17936 */ MCD_OPC_CheckPredicate, 21, 34, 0, 0, // Skip to: 17975 +/* 17941 */ MCD_OPC_CheckField, 19, 3, 0, 27, 0, 0, // Skip to: 17975 +/* 17948 */ MCD_OPC_Decode, 156, 14, 161, 1, // Opcode: VMOVv16i8 +/* 17953 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 17975 +/* 17958 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 17975 +/* 17963 */ MCD_OPC_CheckField, 19, 3, 0, 5, 0, 0, // Skip to: 17975 +/* 17970 */ MCD_OPC_Decode, 160, 14, 161, 1, // Opcode: VMOVv2i64 +/* 17975 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 17978 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17993 +/* 17983 */ MCD_OPC_CheckPredicate, 21, 82, 0, 0, // Skip to: 18070 +/* 17988 */ MCD_OPC_Decode, 246, 9, 178, 1, // Opcode: VCVTxs2fq +/* 17993 */ MCD_OPC_FilterValue, 1, 72, 0, 0, // Skip to: 18070 +/* 17998 */ MCD_OPC_CheckPredicate, 21, 67, 0, 0, // Skip to: 18070 +/* 18003 */ MCD_OPC_Decode, 250, 9, 178, 1, // Opcode: VCVTxu2fq +/* 18008 */ MCD_OPC_FilterValue, 15, 57, 0, 0, // Skip to: 18070 +/* 18013 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... +/* 18016 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18031 +/* 18021 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 18046 +/* 18026 */ MCD_OPC_Decode, 225, 9, 178, 1, // Opcode: VCVTf2xsq +/* 18031 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 18046 +/* 18036 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 18046 +/* 18041 */ MCD_OPC_Decode, 227, 9, 178, 1, // Opcode: VCVTf2xuq +/* 18046 */ MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 18070 +/* 18051 */ MCD_OPC_CheckField, 19, 3, 0, 12, 0, 0, // Skip to: 18070 +/* 18058 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 18070 +/* 18065 */ MCD_OPC_Decode, 161, 14, 161, 1, // Opcode: VMOVv4f32 +/* 18070 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 18073 */ MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 18166 +/* 18078 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... +/* 18081 */ MCD_OPC_FilterValue, 0, 211, 1, 0, // Skip to: 18553 +/* 18086 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 18089 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18111 +/* 18094 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 18156 +/* 18099 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 18156 +/* 18106 */ MCD_OPC_Decode, 164, 14, 161, 1, // Opcode: VMOVv8i16 +/* 18111 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 18156 +/* 18116 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 18119 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18134 +/* 18124 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 18156 +/* 18129 */ MCD_OPC_Decode, 247, 14, 161, 1, // Opcode: VORRiv4i32 +/* 18134 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18156 +/* 18139 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 18156 +/* 18144 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 18156 +/* 18151 */ MCD_OPC_Decode, 248, 14, 161, 1, // Opcode: VORRiv8i16 +/* 18156 */ MCD_OPC_CheckPredicate, 21, 136, 1, 0, // Skip to: 18553 +/* 18161 */ MCD_OPC_Decode, 163, 14, 161, 1, // Opcode: VMOVv4i32 +/* 18166 */ MCD_OPC_FilterValue, 1, 126, 1, 0, // Skip to: 18553 +/* 18171 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... +/* 18174 */ MCD_OPC_FilterValue, 0, 118, 1, 0, // Skip to: 18553 +/* 18179 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 18182 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18204 +/* 18187 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 18249 +/* 18192 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 18249 +/* 18199 */ MCD_OPC_Decode, 219, 14, 161, 1, // Opcode: VMVNv8i16 +/* 18204 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 18249 +/* 18209 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 18212 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18227 +/* 18217 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 18249 +/* 18222 */ MCD_OPC_Decode, 142, 8, 161, 1, // Opcode: VBICiv4i32 +/* 18227 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18249 +/* 18232 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 18249 +/* 18237 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 18249 +/* 18244 */ MCD_OPC_Decode, 143, 8, 161, 1, // Opcode: VBICiv8i16 +/* 18249 */ MCD_OPC_CheckPredicate, 21, 43, 1, 0, // Skip to: 18553 +/* 18254 */ MCD_OPC_Decode, 218, 14, 161, 1, // Opcode: VMVNv4i32 +/* 18259 */ MCD_OPC_FilterValue, 1, 33, 1, 0, // Skip to: 18553 +/* 18264 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 18267 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 18307 +/* 18272 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 18275 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18291 +/* 18281 */ MCD_OPC_CheckPredicate, 21, 11, 1, 0, // Skip to: 18553 +/* 18286 */ MCD_OPC_Decode, 158, 18, 179, 1, // Opcode: VSHRsv2i64 +/* 18291 */ MCD_OPC_FilterValue, 243, 1, 0, 1, 0, // Skip to: 18553 +/* 18297 */ MCD_OPC_CheckPredicate, 21, 251, 0, 0, // Skip to: 18553 +/* 18302 */ MCD_OPC_Decode, 166, 18, 179, 1, // Opcode: VSHRuv2i64 +/* 18307 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 18347 +/* 18312 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 18315 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18331 +/* 18321 */ MCD_OPC_CheckPredicate, 21, 227, 0, 0, // Skip to: 18553 +/* 18326 */ MCD_OPC_Decode, 194, 18, 180, 1, // Opcode: VSRAsv2i64 +/* 18331 */ MCD_OPC_FilterValue, 243, 1, 216, 0, 0, // Skip to: 18553 +/* 18337 */ MCD_OPC_CheckPredicate, 21, 211, 0, 0, // Skip to: 18553 +/* 18342 */ MCD_OPC_Decode, 202, 18, 180, 1, // Opcode: VSRAuv2i64 +/* 18347 */ MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 18387 +/* 18352 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 18355 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18371 +/* 18361 */ MCD_OPC_CheckPredicate, 21, 187, 0, 0, // Skip to: 18553 +/* 18366 */ MCD_OPC_Decode, 186, 17, 179, 1, // Opcode: VRSHRsv2i64 +/* 18371 */ MCD_OPC_FilterValue, 243, 1, 176, 0, 0, // Skip to: 18553 +/* 18377 */ MCD_OPC_CheckPredicate, 21, 171, 0, 0, // Skip to: 18553 +/* 18382 */ MCD_OPC_Decode, 194, 17, 179, 1, // Opcode: VRSHRuv2i64 +/* 18387 */ MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 18427 +/* 18392 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 18395 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18411 +/* 18401 */ MCD_OPC_CheckPredicate, 21, 147, 0, 0, // Skip to: 18553 +/* 18406 */ MCD_OPC_Decode, 212, 17, 180, 1, // Opcode: VRSRAsv2i64 +/* 18411 */ MCD_OPC_FilterValue, 243, 1, 136, 0, 0, // Skip to: 18553 +/* 18417 */ MCD_OPC_CheckPredicate, 21, 131, 0, 0, // Skip to: 18553 +/* 18422 */ MCD_OPC_Decode, 220, 17, 180, 1, // Opcode: VRSRAuv2i64 +/* 18427 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 18450 +/* 18432 */ MCD_OPC_CheckPredicate, 21, 116, 0, 0, // Skip to: 18553 +/* 18437 */ MCD_OPC_CheckField, 24, 8, 243, 1, 108, 0, 0, // Skip to: 18553 +/* 18445 */ MCD_OPC_Decode, 210, 18, 180, 1, // Opcode: VSRIv2i64 +/* 18450 */ MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 18490 +/* 18455 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 18458 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18474 +/* 18464 */ MCD_OPC_CheckPredicate, 21, 84, 0, 0, // Skip to: 18553 +/* 18469 */ MCD_OPC_Decode, 131, 18, 181, 1, // Opcode: VSHLiv2i64 +/* 18474 */ MCD_OPC_FilterValue, 243, 1, 73, 0, 0, // Skip to: 18553 +/* 18480 */ MCD_OPC_CheckPredicate, 21, 68, 0, 0, // Skip to: 18553 +/* 18485 */ MCD_OPC_Decode, 180, 18, 182, 1, // Opcode: VSLIv2i64 +/* 18490 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 18513 +/* 18495 */ MCD_OPC_CheckPredicate, 21, 53, 0, 0, // Skip to: 18553 +/* 18500 */ MCD_OPC_CheckField, 24, 8, 243, 1, 45, 0, 0, // Skip to: 18553 +/* 18508 */ MCD_OPC_Decode, 156, 16, 181, 1, // Opcode: VQSHLsuv2i64 +/* 18513 */ MCD_OPC_FilterValue, 7, 35, 0, 0, // Skip to: 18553 +/* 18518 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 18521 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18537 +/* 18527 */ MCD_OPC_CheckPredicate, 21, 21, 0, 0, // Skip to: 18553 +/* 18532 */ MCD_OPC_Decode, 148, 16, 181, 1, // Opcode: VQSHLsiv2i64 +/* 18537 */ MCD_OPC_FilterValue, 243, 1, 10, 0, 0, // Skip to: 18553 +/* 18543 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 18553 +/* 18548 */ MCD_OPC_Decode, 172, 16, 181, 1, // Opcode: VQSHLuiv2i64 +/* 18553 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNEONDup32[] = { +/* 0 */ MCD_OPC_ExtractField, 22, 6, // Inst{27-22} ... +/* 3 */ MCD_OPC_FilterValue, 56, 121, 0, 0, // Skip to: 129 +/* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 11 */ MCD_OPC_FilterValue, 16, 61, 0, 0, // Skip to: 77 +/* 16 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 19 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 48 +/* 24 */ MCD_OPC_CheckPredicate, 27, 183, 1, 0, // Skip to: 468 +/* 29 */ MCD_OPC_CheckField, 8, 4, 11, 176, 1, 0, // Skip to: 468 +/* 36 */ MCD_OPC_CheckField, 6, 1, 0, 169, 1, 0, // Skip to: 468 +/* 43 */ MCD_OPC_Decode, 245, 17, 183, 1, // Opcode: VSETLNi32 +/* 48 */ MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 468 +/* 53 */ MCD_OPC_CheckPredicate, 27, 154, 1, 0, // Skip to: 468 +/* 58 */ MCD_OPC_CheckField, 8, 4, 11, 147, 1, 0, // Skip to: 468 +/* 65 */ MCD_OPC_CheckField, 6, 1, 0, 140, 1, 0, // Skip to: 468 +/* 72 */ MCD_OPC_Decode, 169, 10, 184, 1, // Opcode: VGETLNi32 +/* 77 */ MCD_OPC_FilterValue, 48, 130, 1, 0, // Skip to: 468 +/* 82 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 85 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 107 +/* 90 */ MCD_OPC_CheckPredicate, 21, 117, 1, 0, // Skip to: 468 +/* 95 */ MCD_OPC_CheckField, 8, 4, 11, 110, 1, 0, // Skip to: 468 +/* 102 */ MCD_OPC_Decode, 244, 17, 185, 1, // Opcode: VSETLNi16 +/* 107 */ MCD_OPC_FilterValue, 1, 100, 1, 0, // Skip to: 468 +/* 112 */ MCD_OPC_CheckPredicate, 21, 95, 1, 0, // Skip to: 468 +/* 117 */ MCD_OPC_CheckField, 8, 4, 11, 88, 1, 0, // Skip to: 468 +/* 124 */ MCD_OPC_Decode, 170, 10, 186, 1, // Opcode: VGETLNs16 +/* 129 */ MCD_OPC_FilterValue, 57, 61, 0, 0, // Skip to: 195 +/* 134 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 137 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 166 +/* 142 */ MCD_OPC_CheckPredicate, 21, 65, 1, 0, // Skip to: 468 +/* 147 */ MCD_OPC_CheckField, 8, 4, 11, 58, 1, 0, // Skip to: 468 +/* 154 */ MCD_OPC_CheckField, 0, 5, 16, 51, 1, 0, // Skip to: 468 +/* 161 */ MCD_OPC_Decode, 246, 17, 187, 1, // Opcode: VSETLNi8 +/* 166 */ MCD_OPC_FilterValue, 1, 41, 1, 0, // Skip to: 468 +/* 171 */ MCD_OPC_CheckPredicate, 21, 36, 1, 0, // Skip to: 468 +/* 176 */ MCD_OPC_CheckField, 8, 4, 11, 29, 1, 0, // Skip to: 468 +/* 183 */ MCD_OPC_CheckField, 0, 5, 16, 22, 1, 0, // Skip to: 468 +/* 190 */ MCD_OPC_Decode, 171, 10, 188, 1, // Opcode: VGETLNs8 +/* 195 */ MCD_OPC_FilterValue, 58, 165, 0, 0, // Skip to: 365 +/* 200 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... +/* 203 */ MCD_OPC_FilterValue, 16, 61, 0, 0, // Skip to: 269 +/* 208 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 211 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 240 +/* 216 */ MCD_OPC_CheckPredicate, 21, 247, 0, 0, // Skip to: 468 +/* 221 */ MCD_OPC_CheckField, 8, 4, 11, 240, 0, 0, // Skip to: 468 +/* 228 */ MCD_OPC_CheckField, 6, 1, 0, 233, 0, 0, // Skip to: 468 +/* 235 */ MCD_OPC_Decode, 130, 10, 189, 1, // Opcode: VDUP32d +/* 240 */ MCD_OPC_FilterValue, 2, 223, 0, 0, // Skip to: 468 +/* 245 */ MCD_OPC_CheckPredicate, 21, 218, 0, 0, // Skip to: 468 +/* 250 */ MCD_OPC_CheckField, 8, 4, 11, 211, 0, 0, // Skip to: 468 +/* 257 */ MCD_OPC_CheckField, 6, 1, 0, 204, 0, 0, // Skip to: 468 +/* 264 */ MCD_OPC_Decode, 131, 10, 190, 1, // Opcode: VDUP32q +/* 269 */ MCD_OPC_FilterValue, 48, 194, 0, 0, // Skip to: 468 +/* 274 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 277 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 343 +/* 282 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 285 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 314 +/* 290 */ MCD_OPC_CheckPredicate, 21, 173, 0, 0, // Skip to: 468 +/* 295 */ MCD_OPC_CheckField, 8, 4, 11, 166, 0, 0, // Skip to: 468 +/* 302 */ MCD_OPC_CheckField, 6, 1, 0, 159, 0, 0, // Skip to: 468 +/* 309 */ MCD_OPC_Decode, 128, 10, 189, 1, // Opcode: VDUP16d +/* 314 */ MCD_OPC_FilterValue, 1, 149, 0, 0, // Skip to: 468 +/* 319 */ MCD_OPC_CheckPredicate, 21, 144, 0, 0, // Skip to: 468 +/* 324 */ MCD_OPC_CheckField, 8, 4, 11, 137, 0, 0, // Skip to: 468 +/* 331 */ MCD_OPC_CheckField, 6, 1, 0, 130, 0, 0, // Skip to: 468 +/* 338 */ MCD_OPC_Decode, 129, 10, 190, 1, // Opcode: VDUP16q +/* 343 */ MCD_OPC_FilterValue, 1, 120, 0, 0, // Skip to: 468 +/* 348 */ MCD_OPC_CheckPredicate, 21, 115, 0, 0, // Skip to: 468 +/* 353 */ MCD_OPC_CheckField, 8, 4, 11, 108, 0, 0, // Skip to: 468 +/* 360 */ MCD_OPC_Decode, 172, 10, 186, 1, // Opcode: VGETLNu16 +/* 365 */ MCD_OPC_FilterValue, 59, 98, 0, 0, // Skip to: 468 +/* 370 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 373 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 439 +/* 378 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 381 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 410 +/* 386 */ MCD_OPC_CheckPredicate, 21, 77, 0, 0, // Skip to: 468 +/* 391 */ MCD_OPC_CheckField, 8, 4, 11, 70, 0, 0, // Skip to: 468 +/* 398 */ MCD_OPC_CheckField, 0, 7, 16, 63, 0, 0, // Skip to: 468 +/* 405 */ MCD_OPC_Decode, 132, 10, 189, 1, // Opcode: VDUP8d +/* 410 */ MCD_OPC_FilterValue, 1, 53, 0, 0, // Skip to: 468 +/* 415 */ MCD_OPC_CheckPredicate, 21, 48, 0, 0, // Skip to: 468 +/* 420 */ MCD_OPC_CheckField, 8, 4, 11, 41, 0, 0, // Skip to: 468 +/* 427 */ MCD_OPC_CheckField, 0, 7, 16, 34, 0, 0, // Skip to: 468 +/* 434 */ MCD_OPC_Decode, 133, 10, 190, 1, // Opcode: VDUP8q +/* 439 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 468 +/* 444 */ MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 468 +/* 449 */ MCD_OPC_CheckField, 8, 4, 11, 12, 0, 0, // Skip to: 468 +/* 456 */ MCD_OPC_CheckField, 0, 5, 16, 5, 0, 0, // Skip to: 468 +/* 463 */ MCD_OPC_Decode, 173, 10, 188, 1, // Opcode: VGETLNu8 +/* 468 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableNEONLoadStore32[] = { +/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 3 */ MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 319 +/* 8 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 11 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 165 +/* 16 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 19 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 124 +/* 25 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 28 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 60 +/* 33 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 50 +/* 38 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 50 +/* 45 */ MCD_OPC_Decode, 178, 20, 191, 1, // Opcode: VST4d8 +/* 50 */ MCD_OPC_CheckPredicate, 21, 246, 25, 0, // Skip to: 6701 +/* 55 */ MCD_OPC_Decode, 181, 20, 191, 1, // Opcode: VST4d8_UPD +/* 60 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 92 +/* 65 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 82 +/* 70 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 82 +/* 77 */ MCD_OPC_Decode, 170, 20, 191, 1, // Opcode: VST4d16 +/* 82 */ MCD_OPC_CheckPredicate, 21, 214, 25, 0, // Skip to: 6701 +/* 87 */ MCD_OPC_Decode, 173, 20, 191, 1, // Opcode: VST4d16_UPD +/* 92 */ MCD_OPC_FilterValue, 2, 204, 25, 0, // Skip to: 6701 +/* 97 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 114 +/* 102 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 114 +/* 109 */ MCD_OPC_Decode, 174, 20, 191, 1, // Opcode: VST4d32 +/* 114 */ MCD_OPC_CheckPredicate, 21, 182, 25, 0, // Skip to: 6701 +/* 119 */ MCD_OPC_Decode, 177, 20, 191, 1, // Opcode: VST4d32_UPD +/* 124 */ MCD_OPC_FilterValue, 233, 3, 171, 25, 0, // Skip to: 6701 +/* 130 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 133 */ MCD_OPC_FilterValue, 0, 163, 25, 0, // Skip to: 6701 +/* 138 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 155 +/* 143 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 155 +/* 150 */ MCD_OPC_Decode, 219, 18, 192, 1, // Opcode: VST1LNd8 +/* 155 */ MCD_OPC_CheckPredicate, 21, 141, 25, 0, // Skip to: 6701 +/* 160 */ MCD_OPC_Decode, 220, 18, 192, 1, // Opcode: VST1LNd8_UPD +/* 165 */ MCD_OPC_FilterValue, 2, 131, 25, 0, // Skip to: 6701 +/* 170 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 173 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 278 +/* 179 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 182 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 214 +/* 187 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 204 +/* 192 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 204 +/* 199 */ MCD_OPC_Decode, 253, 12, 191, 1, // Opcode: VLD4d8 +/* 204 */ MCD_OPC_CheckPredicate, 21, 92, 25, 0, // Skip to: 6701 +/* 209 */ MCD_OPC_Decode, 128, 13, 191, 1, // Opcode: VLD4d8_UPD +/* 214 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 246 +/* 219 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 236 +/* 224 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 236 +/* 231 */ MCD_OPC_Decode, 245, 12, 191, 1, // Opcode: VLD4d16 +/* 236 */ MCD_OPC_CheckPredicate, 21, 60, 25, 0, // Skip to: 6701 +/* 241 */ MCD_OPC_Decode, 248, 12, 191, 1, // Opcode: VLD4d16_UPD +/* 246 */ MCD_OPC_FilterValue, 2, 50, 25, 0, // Skip to: 6701 +/* 251 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 268 +/* 256 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 268 +/* 263 */ MCD_OPC_Decode, 249, 12, 191, 1, // Opcode: VLD4d32 +/* 268 */ MCD_OPC_CheckPredicate, 21, 28, 25, 0, // Skip to: 6701 +/* 273 */ MCD_OPC_Decode, 252, 12, 191, 1, // Opcode: VLD4d32_UPD +/* 278 */ MCD_OPC_FilterValue, 233, 3, 17, 25, 0, // Skip to: 6701 +/* 284 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 287 */ MCD_OPC_FilterValue, 0, 9, 25, 0, // Skip to: 6701 +/* 292 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 309 +/* 297 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 309 +/* 304 */ MCD_OPC_Decode, 222, 10, 193, 1, // Opcode: VLD1LNd8 +/* 309 */ MCD_OPC_CheckPredicate, 21, 243, 24, 0, // Skip to: 6701 +/* 314 */ MCD_OPC_Decode, 223, 10, 193, 1, // Opcode: VLD1LNd8_UPD +/* 319 */ MCD_OPC_FilterValue, 1, 39, 1, 0, // Skip to: 619 +/* 324 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 327 */ MCD_OPC_FilterValue, 0, 141, 0, 0, // Skip to: 473 +/* 332 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 335 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 440 +/* 341 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 344 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 376 +/* 349 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 366 +/* 354 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 366 +/* 361 */ MCD_OPC_Decode, 192, 20, 191, 1, // Opcode: VST4q8 +/* 366 */ MCD_OPC_CheckPredicate, 21, 186, 24, 0, // Skip to: 6701 +/* 371 */ MCD_OPC_Decode, 194, 20, 191, 1, // Opcode: VST4q8_UPD +/* 376 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 408 +/* 381 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 398 +/* 386 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 398 +/* 393 */ MCD_OPC_Decode, 182, 20, 191, 1, // Opcode: VST4q16 +/* 398 */ MCD_OPC_CheckPredicate, 21, 154, 24, 0, // Skip to: 6701 +/* 403 */ MCD_OPC_Decode, 184, 20, 191, 1, // Opcode: VST4q16_UPD +/* 408 */ MCD_OPC_FilterValue, 2, 144, 24, 0, // Skip to: 6701 +/* 413 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 430 +/* 418 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 430 +/* 425 */ MCD_OPC_Decode, 187, 20, 191, 1, // Opcode: VST4q32 +/* 430 */ MCD_OPC_CheckPredicate, 21, 122, 24, 0, // Skip to: 6701 +/* 435 */ MCD_OPC_Decode, 189, 20, 191, 1, // Opcode: VST4q32_UPD +/* 440 */ MCD_OPC_FilterValue, 233, 3, 111, 24, 0, // Skip to: 6701 +/* 446 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 463 +/* 451 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 463 +/* 458 */ MCD_OPC_Decode, 183, 19, 194, 1, // Opcode: VST2LNd8 +/* 463 */ MCD_OPC_CheckPredicate, 21, 89, 24, 0, // Skip to: 6701 +/* 468 */ MCD_OPC_Decode, 186, 19, 194, 1, // Opcode: VST2LNd8_UPD +/* 473 */ MCD_OPC_FilterValue, 2, 79, 24, 0, // Skip to: 6701 +/* 478 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 481 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 586 +/* 487 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 490 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 522 +/* 495 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 512 +/* 500 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 512 +/* 507 */ MCD_OPC_Decode, 139, 13, 191, 1, // Opcode: VLD4q8 +/* 512 */ MCD_OPC_CheckPredicate, 21, 40, 24, 0, // Skip to: 6701 +/* 517 */ MCD_OPC_Decode, 141, 13, 191, 1, // Opcode: VLD4q8_UPD +/* 522 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 554 +/* 527 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 544 +/* 532 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 544 +/* 539 */ MCD_OPC_Decode, 129, 13, 191, 1, // Opcode: VLD4q16 +/* 544 */ MCD_OPC_CheckPredicate, 21, 8, 24, 0, // Skip to: 6701 +/* 549 */ MCD_OPC_Decode, 131, 13, 191, 1, // Opcode: VLD4q16_UPD +/* 554 */ MCD_OPC_FilterValue, 2, 254, 23, 0, // Skip to: 6701 +/* 559 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 576 +/* 564 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 576 +/* 571 */ MCD_OPC_Decode, 134, 13, 191, 1, // Opcode: VLD4q32 +/* 576 */ MCD_OPC_CheckPredicate, 21, 232, 23, 0, // Skip to: 6701 +/* 581 */ MCD_OPC_Decode, 136, 13, 191, 1, // Opcode: VLD4q32_UPD +/* 586 */ MCD_OPC_FilterValue, 233, 3, 221, 23, 0, // Skip to: 6701 +/* 592 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 609 +/* 597 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 609 +/* 604 */ MCD_OPC_Decode, 210, 11, 195, 1, // Opcode: VLD2LNd8 +/* 609 */ MCD_OPC_CheckPredicate, 21, 199, 23, 0, // Skip to: 6701 +/* 614 */ MCD_OPC_Decode, 213, 11, 195, 1, // Opcode: VLD2LNd8_UPD +/* 619 */ MCD_OPC_FilterValue, 2, 247, 1, 0, // Skip to: 1127 +/* 624 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 627 */ MCD_OPC_FilterValue, 0, 245, 0, 0, // Skip to: 877 +/* 632 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 635 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 836 +/* 641 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 644 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 692 +/* 649 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 652 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 667 +/* 657 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 682 +/* 662 */ MCD_OPC_Decode, 139, 19, 196, 1, // Opcode: VST1d8Qwb_fixed +/* 667 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 682 +/* 672 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 682 +/* 677 */ MCD_OPC_Decode, 137, 19, 196, 1, // Opcode: VST1d8Q +/* 682 */ MCD_OPC_CheckPredicate, 21, 126, 23, 0, // Skip to: 6701 +/* 687 */ MCD_OPC_Decode, 140, 19, 196, 1, // Opcode: VST1d8Qwb_register +/* 692 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 740 +/* 697 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 700 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 715 +/* 705 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 730 +/* 710 */ MCD_OPC_Decode, 230, 18, 196, 1, // Opcode: VST1d16Qwb_fixed +/* 715 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 730 +/* 720 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 730 +/* 725 */ MCD_OPC_Decode, 228, 18, 196, 1, // Opcode: VST1d16Q +/* 730 */ MCD_OPC_CheckPredicate, 21, 78, 23, 0, // Skip to: 6701 +/* 735 */ MCD_OPC_Decode, 231, 18, 196, 1, // Opcode: VST1d16Qwb_register +/* 740 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 788 +/* 745 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 748 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 763 +/* 753 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 778 +/* 758 */ MCD_OPC_Decode, 241, 18, 196, 1, // Opcode: VST1d32Qwb_fixed +/* 763 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 778 +/* 768 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 778 +/* 773 */ MCD_OPC_Decode, 239, 18, 196, 1, // Opcode: VST1d32Q +/* 778 */ MCD_OPC_CheckPredicate, 21, 30, 23, 0, // Skip to: 6701 +/* 783 */ MCD_OPC_Decode, 242, 18, 196, 1, // Opcode: VST1d32Qwb_register +/* 788 */ MCD_OPC_FilterValue, 3, 20, 23, 0, // Skip to: 6701 +/* 793 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 796 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 811 +/* 801 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 826 +/* 806 */ MCD_OPC_Decode, 254, 18, 196, 1, // Opcode: VST1d64Qwb_fixed +/* 811 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 826 +/* 816 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 826 +/* 821 */ MCD_OPC_Decode, 250, 18, 196, 1, // Opcode: VST1d64Q +/* 826 */ MCD_OPC_CheckPredicate, 21, 238, 22, 0, // Skip to: 6701 +/* 831 */ MCD_OPC_Decode, 255, 18, 196, 1, // Opcode: VST1d64Qwb_register +/* 836 */ MCD_OPC_FilterValue, 233, 3, 227, 22, 0, // Skip to: 6701 +/* 842 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 845 */ MCD_OPC_FilterValue, 0, 219, 22, 0, // Skip to: 6701 +/* 850 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 867 +/* 855 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 867 +/* 862 */ MCD_OPC_Decode, 239, 19, 197, 1, // Opcode: VST3LNd8 +/* 867 */ MCD_OPC_CheckPredicate, 21, 197, 22, 0, // Skip to: 6701 +/* 872 */ MCD_OPC_Decode, 242, 19, 197, 1, // Opcode: VST3LNd8_UPD +/* 877 */ MCD_OPC_FilterValue, 2, 187, 22, 0, // Skip to: 6701 +/* 882 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 885 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 1086 +/* 891 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 894 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 942 +/* 899 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 902 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 917 +/* 907 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 932 +/* 912 */ MCD_OPC_Decode, 142, 11, 196, 1, // Opcode: VLD1d8Qwb_fixed +/* 917 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 932 +/* 922 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 932 +/* 927 */ MCD_OPC_Decode, 140, 11, 196, 1, // Opcode: VLD1d8Q +/* 932 */ MCD_OPC_CheckPredicate, 21, 132, 22, 0, // Skip to: 6701 +/* 937 */ MCD_OPC_Decode, 143, 11, 196, 1, // Opcode: VLD1d8Qwb_register +/* 942 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 990 +/* 947 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 950 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 965 +/* 955 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 980 +/* 960 */ MCD_OPC_Decode, 233, 10, 196, 1, // Opcode: VLD1d16Qwb_fixed +/* 965 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 980 +/* 970 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 980 +/* 975 */ MCD_OPC_Decode, 231, 10, 196, 1, // Opcode: VLD1d16Q +/* 980 */ MCD_OPC_CheckPredicate, 21, 84, 22, 0, // Skip to: 6701 +/* 985 */ MCD_OPC_Decode, 234, 10, 196, 1, // Opcode: VLD1d16Qwb_register +/* 990 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 1038 +/* 995 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 998 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1013 +/* 1003 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1028 +/* 1008 */ MCD_OPC_Decode, 244, 10, 196, 1, // Opcode: VLD1d32Qwb_fixed +/* 1013 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1028 +/* 1018 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1028 +/* 1023 */ MCD_OPC_Decode, 242, 10, 196, 1, // Opcode: VLD1d32Q +/* 1028 */ MCD_OPC_CheckPredicate, 21, 36, 22, 0, // Skip to: 6701 +/* 1033 */ MCD_OPC_Decode, 245, 10, 196, 1, // Opcode: VLD1d32Qwb_register +/* 1038 */ MCD_OPC_FilterValue, 3, 26, 22, 0, // Skip to: 6701 +/* 1043 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1046 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1061 +/* 1051 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1076 +/* 1056 */ MCD_OPC_Decode, 129, 11, 196, 1, // Opcode: VLD1d64Qwb_fixed +/* 1061 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1076 +/* 1066 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1076 +/* 1071 */ MCD_OPC_Decode, 253, 10, 196, 1, // Opcode: VLD1d64Q +/* 1076 */ MCD_OPC_CheckPredicate, 21, 244, 21, 0, // Skip to: 6701 +/* 1081 */ MCD_OPC_Decode, 130, 11, 196, 1, // Opcode: VLD1d64Qwb_register +/* 1086 */ MCD_OPC_FilterValue, 233, 3, 233, 21, 0, // Skip to: 6701 +/* 1092 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 1095 */ MCD_OPC_FilterValue, 0, 225, 21, 0, // Skip to: 6701 +/* 1100 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1117 +/* 1105 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1117 +/* 1112 */ MCD_OPC_Decode, 162, 12, 198, 1, // Opcode: VLD3LNd8 +/* 1117 */ MCD_OPC_CheckPredicate, 21, 203, 21, 0, // Skip to: 6701 +/* 1122 */ MCD_OPC_Decode, 165, 12, 198, 1, // Opcode: VLD3LNd8_UPD +/* 1127 */ MCD_OPC_FilterValue, 3, 135, 1, 0, // Skip to: 1523 +/* 1132 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 1135 */ MCD_OPC_FilterValue, 0, 189, 0, 0, // Skip to: 1329 +/* 1140 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1143 */ MCD_OPC_FilterValue, 232, 3, 147, 0, 0, // Skip to: 1296 +/* 1149 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 1152 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 1200 +/* 1157 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1160 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1175 +/* 1165 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1190 +/* 1170 */ MCD_OPC_Decode, 229, 19, 199, 1, // Opcode: VST2q8wb_fixed +/* 1175 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1190 +/* 1180 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1190 +/* 1185 */ MCD_OPC_Decode, 225, 19, 199, 1, // Opcode: VST2q8 +/* 1190 */ MCD_OPC_CheckPredicate, 21, 130, 21, 0, // Skip to: 6701 +/* 1195 */ MCD_OPC_Decode, 230, 19, 199, 1, // Opcode: VST2q8wb_register +/* 1200 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 1248 +/* 1205 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1208 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1223 +/* 1213 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1238 +/* 1218 */ MCD_OPC_Decode, 217, 19, 199, 1, // Opcode: VST2q16wb_fixed +/* 1223 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1238 +/* 1228 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1238 +/* 1233 */ MCD_OPC_Decode, 213, 19, 199, 1, // Opcode: VST2q16 +/* 1238 */ MCD_OPC_CheckPredicate, 21, 82, 21, 0, // Skip to: 6701 +/* 1243 */ MCD_OPC_Decode, 218, 19, 199, 1, // Opcode: VST2q16wb_register +/* 1248 */ MCD_OPC_FilterValue, 2, 72, 21, 0, // Skip to: 6701 +/* 1253 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1256 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1271 +/* 1261 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1286 +/* 1266 */ MCD_OPC_Decode, 223, 19, 199, 1, // Opcode: VST2q32wb_fixed +/* 1271 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1286 +/* 1276 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1286 +/* 1281 */ MCD_OPC_Decode, 219, 19, 199, 1, // Opcode: VST2q32 +/* 1286 */ MCD_OPC_CheckPredicate, 21, 34, 21, 0, // Skip to: 6701 +/* 1291 */ MCD_OPC_Decode, 224, 19, 199, 1, // Opcode: VST2q32wb_register +/* 1296 */ MCD_OPC_FilterValue, 233, 3, 23, 21, 0, // Skip to: 6701 +/* 1302 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1319 +/* 1307 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1319 +/* 1314 */ MCD_OPC_Decode, 158, 20, 200, 1, // Opcode: VST4LNd8 +/* 1319 */ MCD_OPC_CheckPredicate, 21, 1, 21, 0, // Skip to: 6701 +/* 1324 */ MCD_OPC_Decode, 161, 20, 200, 1, // Opcode: VST4LNd8_UPD +/* 1329 */ MCD_OPC_FilterValue, 2, 247, 20, 0, // Skip to: 6701 +/* 1334 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1337 */ MCD_OPC_FilterValue, 232, 3, 147, 0, 0, // Skip to: 1490 +/* 1343 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 1346 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 1394 +/* 1351 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1354 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1369 +/* 1359 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1384 +/* 1364 */ MCD_OPC_Decode, 128, 12, 199, 1, // Opcode: VLD2q8wb_fixed +/* 1369 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1384 +/* 1374 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1384 +/* 1379 */ MCD_OPC_Decode, 252, 11, 199, 1, // Opcode: VLD2q8 +/* 1384 */ MCD_OPC_CheckPredicate, 21, 192, 20, 0, // Skip to: 6701 +/* 1389 */ MCD_OPC_Decode, 129, 12, 199, 1, // Opcode: VLD2q8wb_register +/* 1394 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 1442 +/* 1399 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1402 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1417 +/* 1407 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1432 +/* 1412 */ MCD_OPC_Decode, 244, 11, 199, 1, // Opcode: VLD2q16wb_fixed +/* 1417 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1432 +/* 1422 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1432 +/* 1427 */ MCD_OPC_Decode, 240, 11, 199, 1, // Opcode: VLD2q16 +/* 1432 */ MCD_OPC_CheckPredicate, 21, 144, 20, 0, // Skip to: 6701 +/* 1437 */ MCD_OPC_Decode, 245, 11, 199, 1, // Opcode: VLD2q16wb_register +/* 1442 */ MCD_OPC_FilterValue, 2, 134, 20, 0, // Skip to: 6701 +/* 1447 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 1450 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1465 +/* 1455 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1480 +/* 1460 */ MCD_OPC_Decode, 250, 11, 199, 1, // Opcode: VLD2q32wb_fixed +/* 1465 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1480 +/* 1470 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1480 +/* 1475 */ MCD_OPC_Decode, 246, 11, 199, 1, // Opcode: VLD2q32 +/* 1480 */ MCD_OPC_CheckPredicate, 21, 96, 20, 0, // Skip to: 6701 +/* 1485 */ MCD_OPC_Decode, 251, 11, 199, 1, // Opcode: VLD2q32wb_register +/* 1490 */ MCD_OPC_FilterValue, 233, 3, 85, 20, 0, // Skip to: 6701 +/* 1496 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1513 +/* 1501 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1513 +/* 1508 */ MCD_OPC_Decode, 233, 12, 201, 1, // Opcode: VLD4LNd8 +/* 1513 */ MCD_OPC_CheckPredicate, 21, 63, 20, 0, // Skip to: 6701 +/* 1518 */ MCD_OPC_Decode, 236, 12, 201, 1, // Opcode: VLD4LNd8_UPD +/* 1523 */ MCD_OPC_FilterValue, 4, 54, 1, 0, // Skip to: 1838 +/* 1528 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 1531 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 1685 +/* 1536 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1539 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1644 +/* 1545 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 1548 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1580 +/* 1553 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1570 +/* 1558 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1570 +/* 1565 */ MCD_OPC_Decode, 131, 20, 202, 1, // Opcode: VST3d8 +/* 1570 */ MCD_OPC_CheckPredicate, 21, 6, 20, 0, // Skip to: 6701 +/* 1575 */ MCD_OPC_Decode, 134, 20, 202, 1, // Opcode: VST3d8_UPD +/* 1580 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 1612 +/* 1585 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1602 +/* 1590 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1602 +/* 1597 */ MCD_OPC_Decode, 251, 19, 202, 1, // Opcode: VST3d16 +/* 1602 */ MCD_OPC_CheckPredicate, 21, 230, 19, 0, // Skip to: 6701 +/* 1607 */ MCD_OPC_Decode, 254, 19, 202, 1, // Opcode: VST3d16_UPD +/* 1612 */ MCD_OPC_FilterValue, 4, 220, 19, 0, // Skip to: 6701 +/* 1617 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1634 +/* 1622 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1634 +/* 1629 */ MCD_OPC_Decode, 255, 19, 202, 1, // Opcode: VST3d32 +/* 1634 */ MCD_OPC_CheckPredicate, 21, 198, 19, 0, // Skip to: 6701 +/* 1639 */ MCD_OPC_Decode, 130, 20, 202, 1, // Opcode: VST3d32_UPD +/* 1644 */ MCD_OPC_FilterValue, 233, 3, 187, 19, 0, // Skip to: 6701 +/* 1650 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 1653 */ MCD_OPC_FilterValue, 0, 179, 19, 0, // Skip to: 6701 +/* 1658 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1675 +/* 1663 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1675 +/* 1670 */ MCD_OPC_Decode, 215, 18, 192, 1, // Opcode: VST1LNd16 +/* 1675 */ MCD_OPC_CheckPredicate, 21, 157, 19, 0, // Skip to: 6701 +/* 1680 */ MCD_OPC_Decode, 216, 18, 192, 1, // Opcode: VST1LNd16_UPD +/* 1685 */ MCD_OPC_FilterValue, 2, 147, 19, 0, // Skip to: 6701 +/* 1690 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1693 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1798 +/* 1699 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 1702 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1734 +/* 1707 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1724 +/* 1712 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1724 +/* 1719 */ MCD_OPC_Decode, 182, 12, 202, 1, // Opcode: VLD3d8 +/* 1724 */ MCD_OPC_CheckPredicate, 21, 108, 19, 0, // Skip to: 6701 +/* 1729 */ MCD_OPC_Decode, 185, 12, 202, 1, // Opcode: VLD3d8_UPD +/* 1734 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 1766 +/* 1739 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1756 +/* 1744 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1756 +/* 1751 */ MCD_OPC_Decode, 174, 12, 202, 1, // Opcode: VLD3d16 +/* 1756 */ MCD_OPC_CheckPredicate, 21, 76, 19, 0, // Skip to: 6701 +/* 1761 */ MCD_OPC_Decode, 177, 12, 202, 1, // Opcode: VLD3d16_UPD +/* 1766 */ MCD_OPC_FilterValue, 4, 66, 19, 0, // Skip to: 6701 +/* 1771 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1788 +/* 1776 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1788 +/* 1783 */ MCD_OPC_Decode, 178, 12, 202, 1, // Opcode: VLD3d32 +/* 1788 */ MCD_OPC_CheckPredicate, 21, 44, 19, 0, // Skip to: 6701 +/* 1793 */ MCD_OPC_Decode, 181, 12, 202, 1, // Opcode: VLD3d32_UPD +/* 1798 */ MCD_OPC_FilterValue, 233, 3, 33, 19, 0, // Skip to: 6701 +/* 1804 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1821 +/* 1809 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1821 +/* 1816 */ MCD_OPC_Decode, 218, 10, 193, 1, // Opcode: VLD1LNd16 +/* 1821 */ MCD_OPC_CheckPredicate, 21, 11, 19, 0, // Skip to: 6701 +/* 1826 */ MCD_OPC_CheckField, 5, 1, 0, 4, 19, 0, // Skip to: 6701 +/* 1833 */ MCD_OPC_Decode, 219, 10, 193, 1, // Opcode: VLD1LNd16_UPD +/* 1838 */ MCD_OPC_FilterValue, 5, 137, 1, 0, // Skip to: 2236 +/* 1843 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 1846 */ MCD_OPC_FilterValue, 0, 39, 1, 0, // Skip to: 2146 +/* 1851 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 1854 */ MCD_OPC_FilterValue, 0, 141, 0, 0, // Skip to: 2000 +/* 1859 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1862 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1967 +/* 1868 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 1871 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1903 +/* 1876 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1893 +/* 1881 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1893 +/* 1888 */ MCD_OPC_Decode, 145, 20, 202, 1, // Opcode: VST3q8 +/* 1893 */ MCD_OPC_CheckPredicate, 21, 195, 18, 0, // Skip to: 6701 +/* 1898 */ MCD_OPC_Decode, 147, 20, 202, 1, // Opcode: VST3q8_UPD +/* 1903 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 1935 +/* 1908 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1925 +/* 1913 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1925 +/* 1920 */ MCD_OPC_Decode, 135, 20, 202, 1, // Opcode: VST3q16 +/* 1925 */ MCD_OPC_CheckPredicate, 21, 163, 18, 0, // Skip to: 6701 +/* 1930 */ MCD_OPC_Decode, 137, 20, 202, 1, // Opcode: VST3q16_UPD +/* 1935 */ MCD_OPC_FilterValue, 2, 153, 18, 0, // Skip to: 6701 +/* 1940 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1957 +/* 1945 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1957 +/* 1952 */ MCD_OPC_Decode, 140, 20, 202, 1, // Opcode: VST3q32 +/* 1957 */ MCD_OPC_CheckPredicate, 21, 131, 18, 0, // Skip to: 6701 +/* 1962 */ MCD_OPC_Decode, 142, 20, 202, 1, // Opcode: VST3q32_UPD +/* 1967 */ MCD_OPC_FilterValue, 233, 3, 120, 18, 0, // Skip to: 6701 +/* 1973 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1990 +/* 1978 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1990 +/* 1985 */ MCD_OPC_Decode, 175, 19, 194, 1, // Opcode: VST2LNd16 +/* 1990 */ MCD_OPC_CheckPredicate, 21, 98, 18, 0, // Skip to: 6701 +/* 1995 */ MCD_OPC_Decode, 178, 19, 194, 1, // Opcode: VST2LNd16_UPD +/* 2000 */ MCD_OPC_FilterValue, 2, 88, 18, 0, // Skip to: 6701 +/* 2005 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2008 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 2113 +/* 2014 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 2017 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2049 +/* 2022 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2039 +/* 2027 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2039 +/* 2034 */ MCD_OPC_Decode, 196, 12, 202, 1, // Opcode: VLD3q8 +/* 2039 */ MCD_OPC_CheckPredicate, 21, 49, 18, 0, // Skip to: 6701 +/* 2044 */ MCD_OPC_Decode, 198, 12, 202, 1, // Opcode: VLD3q8_UPD +/* 2049 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 2081 +/* 2054 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2071 +/* 2059 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2071 +/* 2066 */ MCD_OPC_Decode, 186, 12, 202, 1, // Opcode: VLD3q16 +/* 2071 */ MCD_OPC_CheckPredicate, 21, 17, 18, 0, // Skip to: 6701 +/* 2076 */ MCD_OPC_Decode, 188, 12, 202, 1, // Opcode: VLD3q16_UPD +/* 2081 */ MCD_OPC_FilterValue, 2, 7, 18, 0, // Skip to: 6701 +/* 2086 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2103 +/* 2091 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2103 +/* 2098 */ MCD_OPC_Decode, 191, 12, 202, 1, // Opcode: VLD3q32 +/* 2103 */ MCD_OPC_CheckPredicate, 21, 241, 17, 0, // Skip to: 6701 +/* 2108 */ MCD_OPC_Decode, 193, 12, 202, 1, // Opcode: VLD3q32_UPD +/* 2113 */ MCD_OPC_FilterValue, 233, 3, 230, 17, 0, // Skip to: 6701 +/* 2119 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2136 +/* 2124 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2136 +/* 2131 */ MCD_OPC_Decode, 202, 11, 195, 1, // Opcode: VLD2LNd16 +/* 2136 */ MCD_OPC_CheckPredicate, 21, 208, 17, 0, // Skip to: 6701 +/* 2141 */ MCD_OPC_Decode, 205, 11, 195, 1, // Opcode: VLD2LNd16_UPD +/* 2146 */ MCD_OPC_FilterValue, 1, 198, 17, 0, // Skip to: 6701 +/* 2151 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 2154 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 2195 +/* 2159 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2162 */ MCD_OPC_FilterValue, 233, 3, 181, 17, 0, // Skip to: 6701 +/* 2168 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2185 +/* 2173 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2185 +/* 2180 */ MCD_OPC_Decode, 187, 19, 194, 1, // Opcode: VST2LNq16 +/* 2185 */ MCD_OPC_CheckPredicate, 21, 159, 17, 0, // Skip to: 6701 +/* 2190 */ MCD_OPC_Decode, 190, 19, 194, 1, // Opcode: VST2LNq16_UPD +/* 2195 */ MCD_OPC_FilterValue, 2, 149, 17, 0, // Skip to: 6701 +/* 2200 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2203 */ MCD_OPC_FilterValue, 233, 3, 140, 17, 0, // Skip to: 6701 +/* 2209 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2226 +/* 2214 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2226 +/* 2221 */ MCD_OPC_Decode, 214, 11, 195, 1, // Opcode: VLD2LNq16 +/* 2226 */ MCD_OPC_CheckPredicate, 21, 118, 17, 0, // Skip to: 6701 +/* 2231 */ MCD_OPC_Decode, 217, 11, 195, 1, // Opcode: VLD2LNq16_UPD +/* 2236 */ MCD_OPC_FilterValue, 6, 108, 2, 0, // Skip to: 2861 +/* 2241 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 2244 */ MCD_OPC_FilterValue, 0, 49, 1, 0, // Skip to: 2554 +/* 2249 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2252 */ MCD_OPC_FilterValue, 232, 3, 223, 0, 0, // Skip to: 2481 +/* 2258 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 2261 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 2316 +/* 2266 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2269 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2284 +/* 2274 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2306 +/* 2279 */ MCD_OPC_Decode, 143, 19, 196, 1, // Opcode: VST1d8Twb_fixed +/* 2284 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2306 +/* 2289 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2306 +/* 2294 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2306 +/* 2301 */ MCD_OPC_Decode, 141, 19, 196, 1, // Opcode: VST1d8T +/* 2306 */ MCD_OPC_CheckPredicate, 21, 38, 17, 0, // Skip to: 6701 +/* 2311 */ MCD_OPC_Decode, 144, 19, 196, 1, // Opcode: VST1d8Twb_register +/* 2316 */ MCD_OPC_FilterValue, 1, 50, 0, 0, // Skip to: 2371 +/* 2321 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2324 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2339 +/* 2329 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2361 +/* 2334 */ MCD_OPC_Decode, 234, 18, 196, 1, // Opcode: VST1d16Twb_fixed +/* 2339 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2361 +/* 2344 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2361 +/* 2349 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2361 +/* 2356 */ MCD_OPC_Decode, 232, 18, 196, 1, // Opcode: VST1d16T +/* 2361 */ MCD_OPC_CheckPredicate, 21, 239, 16, 0, // Skip to: 6701 +/* 2366 */ MCD_OPC_Decode, 235, 18, 196, 1, // Opcode: VST1d16Twb_register +/* 2371 */ MCD_OPC_FilterValue, 2, 50, 0, 0, // Skip to: 2426 +/* 2376 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2379 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2394 +/* 2384 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2416 +/* 2389 */ MCD_OPC_Decode, 245, 18, 196, 1, // Opcode: VST1d32Twb_fixed +/* 2394 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2416 +/* 2399 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2416 +/* 2404 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2416 +/* 2411 */ MCD_OPC_Decode, 243, 18, 196, 1, // Opcode: VST1d32T +/* 2416 */ MCD_OPC_CheckPredicate, 21, 184, 16, 0, // Skip to: 6701 +/* 2421 */ MCD_OPC_Decode, 246, 18, 196, 1, // Opcode: VST1d32Twb_register +/* 2426 */ MCD_OPC_FilterValue, 3, 174, 16, 0, // Skip to: 6701 +/* 2431 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2434 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2449 +/* 2439 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2471 +/* 2444 */ MCD_OPC_Decode, 132, 19, 196, 1, // Opcode: VST1d64Twb_fixed +/* 2449 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2471 +/* 2454 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2471 +/* 2459 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2471 +/* 2466 */ MCD_OPC_Decode, 128, 19, 196, 1, // Opcode: VST1d64T +/* 2471 */ MCD_OPC_CheckPredicate, 21, 129, 16, 0, // Skip to: 6701 +/* 2476 */ MCD_OPC_Decode, 133, 19, 196, 1, // Opcode: VST1d64Twb_register +/* 2481 */ MCD_OPC_FilterValue, 233, 3, 118, 16, 0, // Skip to: 6701 +/* 2487 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 2490 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2522 +/* 2495 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2512 +/* 2500 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2512 +/* 2507 */ MCD_OPC_Decode, 231, 19, 197, 1, // Opcode: VST3LNd16 +/* 2512 */ MCD_OPC_CheckPredicate, 21, 88, 16, 0, // Skip to: 6701 +/* 2517 */ MCD_OPC_Decode, 234, 19, 197, 1, // Opcode: VST3LNd16_UPD +/* 2522 */ MCD_OPC_FilterValue, 2, 78, 16, 0, // Skip to: 6701 +/* 2527 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2544 +/* 2532 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2544 +/* 2539 */ MCD_OPC_Decode, 243, 19, 197, 1, // Opcode: VST3LNq16 +/* 2544 */ MCD_OPC_CheckPredicate, 21, 56, 16, 0, // Skip to: 6701 +/* 2549 */ MCD_OPC_Decode, 246, 19, 197, 1, // Opcode: VST3LNq16_UPD +/* 2554 */ MCD_OPC_FilterValue, 2, 46, 16, 0, // Skip to: 6701 +/* 2559 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 2562 */ MCD_OPC_FilterValue, 0, 245, 0, 0, // Skip to: 2812 +/* 2567 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2570 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 2771 +/* 2576 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 2579 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 2627 +/* 2584 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2587 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2602 +/* 2592 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2617 +/* 2597 */ MCD_OPC_Decode, 146, 11, 196, 1, // Opcode: VLD1d8Twb_fixed +/* 2602 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2617 +/* 2607 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2617 +/* 2612 */ MCD_OPC_Decode, 144, 11, 196, 1, // Opcode: VLD1d8T +/* 2617 */ MCD_OPC_CheckPredicate, 21, 239, 15, 0, // Skip to: 6701 +/* 2622 */ MCD_OPC_Decode, 147, 11, 196, 1, // Opcode: VLD1d8Twb_register +/* 2627 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 2675 +/* 2632 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2635 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2650 +/* 2640 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2665 +/* 2645 */ MCD_OPC_Decode, 237, 10, 196, 1, // Opcode: VLD1d16Twb_fixed +/* 2650 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2665 +/* 2655 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2665 +/* 2660 */ MCD_OPC_Decode, 235, 10, 196, 1, // Opcode: VLD1d16T +/* 2665 */ MCD_OPC_CheckPredicate, 21, 191, 15, 0, // Skip to: 6701 +/* 2670 */ MCD_OPC_Decode, 238, 10, 196, 1, // Opcode: VLD1d16Twb_register +/* 2675 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 2723 +/* 2680 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2683 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2698 +/* 2688 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2713 +/* 2693 */ MCD_OPC_Decode, 248, 10, 196, 1, // Opcode: VLD1d32Twb_fixed +/* 2698 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2713 +/* 2703 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2713 +/* 2708 */ MCD_OPC_Decode, 246, 10, 196, 1, // Opcode: VLD1d32T +/* 2713 */ MCD_OPC_CheckPredicate, 21, 143, 15, 0, // Skip to: 6701 +/* 2718 */ MCD_OPC_Decode, 249, 10, 196, 1, // Opcode: VLD1d32Twb_register +/* 2723 */ MCD_OPC_FilterValue, 3, 133, 15, 0, // Skip to: 6701 +/* 2728 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2731 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2746 +/* 2736 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2761 +/* 2741 */ MCD_OPC_Decode, 135, 11, 196, 1, // Opcode: VLD1d64Twb_fixed +/* 2746 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2761 +/* 2751 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2761 +/* 2756 */ MCD_OPC_Decode, 131, 11, 196, 1, // Opcode: VLD1d64T +/* 2761 */ MCD_OPC_CheckPredicate, 21, 95, 15, 0, // Skip to: 6701 +/* 2766 */ MCD_OPC_Decode, 136, 11, 196, 1, // Opcode: VLD1d64Twb_register +/* 2771 */ MCD_OPC_FilterValue, 233, 3, 84, 15, 0, // Skip to: 6701 +/* 2777 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 2780 */ MCD_OPC_FilterValue, 0, 76, 15, 0, // Skip to: 6701 +/* 2785 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2802 +/* 2790 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2802 +/* 2797 */ MCD_OPC_Decode, 154, 12, 198, 1, // Opcode: VLD3LNd16 +/* 2802 */ MCD_OPC_CheckPredicate, 21, 54, 15, 0, // Skip to: 6701 +/* 2807 */ MCD_OPC_Decode, 157, 12, 198, 1, // Opcode: VLD3LNd16_UPD +/* 2812 */ MCD_OPC_FilterValue, 1, 44, 15, 0, // Skip to: 6701 +/* 2817 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 2820 */ MCD_OPC_FilterValue, 0, 36, 15, 0, // Skip to: 6701 +/* 2825 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2828 */ MCD_OPC_FilterValue, 233, 3, 27, 15, 0, // Skip to: 6701 +/* 2834 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2851 +/* 2839 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2851 +/* 2846 */ MCD_OPC_Decode, 166, 12, 198, 1, // Opcode: VLD3LNq16 +/* 2851 */ MCD_OPC_CheckPredicate, 21, 5, 15, 0, // Skip to: 6701 +/* 2856 */ MCD_OPC_Decode, 169, 12, 198, 1, // Opcode: VLD3LNq16_UPD +/* 2861 */ MCD_OPC_FilterValue, 7, 73, 2, 0, // Skip to: 3451 +/* 2866 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 2869 */ MCD_OPC_FilterValue, 0, 231, 1, 0, // Skip to: 3361 +/* 2874 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 2877 */ MCD_OPC_FilterValue, 0, 237, 0, 0, // Skip to: 3119 +/* 2882 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2885 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 3086 +/* 2891 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 2894 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 2942 +/* 2899 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2902 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2917 +/* 2907 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2932 +/* 2912 */ MCD_OPC_Decode, 145, 19, 196, 1, // Opcode: VST1d8wb_fixed +/* 2917 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2932 +/* 2922 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2932 +/* 2927 */ MCD_OPC_Decode, 136, 19, 196, 1, // Opcode: VST1d8 +/* 2932 */ MCD_OPC_CheckPredicate, 21, 180, 14, 0, // Skip to: 6701 +/* 2937 */ MCD_OPC_Decode, 146, 19, 196, 1, // Opcode: VST1d8wb_register +/* 2942 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 2990 +/* 2947 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2950 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2965 +/* 2955 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2980 +/* 2960 */ MCD_OPC_Decode, 236, 18, 196, 1, // Opcode: VST1d16wb_fixed +/* 2965 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2980 +/* 2970 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2980 +/* 2975 */ MCD_OPC_Decode, 227, 18, 196, 1, // Opcode: VST1d16 +/* 2980 */ MCD_OPC_CheckPredicate, 21, 132, 14, 0, // Skip to: 6701 +/* 2985 */ MCD_OPC_Decode, 237, 18, 196, 1, // Opcode: VST1d16wb_register +/* 2990 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 3038 +/* 2995 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2998 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3013 +/* 3003 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3028 +/* 3008 */ MCD_OPC_Decode, 247, 18, 196, 1, // Opcode: VST1d32wb_fixed +/* 3013 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3028 +/* 3018 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3028 +/* 3023 */ MCD_OPC_Decode, 238, 18, 196, 1, // Opcode: VST1d32 +/* 3028 */ MCD_OPC_CheckPredicate, 21, 84, 14, 0, // Skip to: 6701 +/* 3033 */ MCD_OPC_Decode, 248, 18, 196, 1, // Opcode: VST1d32wb_register +/* 3038 */ MCD_OPC_FilterValue, 3, 74, 14, 0, // Skip to: 6701 +/* 3043 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3046 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3061 +/* 3051 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3076 +/* 3056 */ MCD_OPC_Decode, 134, 19, 196, 1, // Opcode: VST1d64wb_fixed +/* 3061 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3076 +/* 3066 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3076 +/* 3071 */ MCD_OPC_Decode, 249, 18, 196, 1, // Opcode: VST1d64 +/* 3076 */ MCD_OPC_CheckPredicate, 21, 36, 14, 0, // Skip to: 6701 +/* 3081 */ MCD_OPC_Decode, 135, 19, 196, 1, // Opcode: VST1d64wb_register +/* 3086 */ MCD_OPC_FilterValue, 233, 3, 25, 14, 0, // Skip to: 6701 +/* 3092 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3109 +/* 3097 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3109 +/* 3104 */ MCD_OPC_Decode, 150, 20, 200, 1, // Opcode: VST4LNd16 +/* 3109 */ MCD_OPC_CheckPredicate, 21, 3, 14, 0, // Skip to: 6701 +/* 3114 */ MCD_OPC_Decode, 153, 20, 200, 1, // Opcode: VST4LNd16_UPD +/* 3119 */ MCD_OPC_FilterValue, 2, 249, 13, 0, // Skip to: 6701 +/* 3124 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3127 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 3328 +/* 3133 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 3136 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3184 +/* 3141 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3144 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3159 +/* 3149 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3174 +/* 3154 */ MCD_OPC_Decode, 148, 11, 196, 1, // Opcode: VLD1d8wb_fixed +/* 3159 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3174 +/* 3164 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3174 +/* 3169 */ MCD_OPC_Decode, 139, 11, 196, 1, // Opcode: VLD1d8 +/* 3174 */ MCD_OPC_CheckPredicate, 21, 194, 13, 0, // Skip to: 6701 +/* 3179 */ MCD_OPC_Decode, 149, 11, 196, 1, // Opcode: VLD1d8wb_register +/* 3184 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 3232 +/* 3189 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3192 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3207 +/* 3197 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3222 +/* 3202 */ MCD_OPC_Decode, 239, 10, 196, 1, // Opcode: VLD1d16wb_fixed +/* 3207 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3222 +/* 3212 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3222 +/* 3217 */ MCD_OPC_Decode, 230, 10, 196, 1, // Opcode: VLD1d16 +/* 3222 */ MCD_OPC_CheckPredicate, 21, 146, 13, 0, // Skip to: 6701 +/* 3227 */ MCD_OPC_Decode, 240, 10, 196, 1, // Opcode: VLD1d16wb_register +/* 3232 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 3280 +/* 3237 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3240 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3255 +/* 3245 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3270 +/* 3250 */ MCD_OPC_Decode, 250, 10, 196, 1, // Opcode: VLD1d32wb_fixed +/* 3255 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3270 +/* 3260 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3270 +/* 3265 */ MCD_OPC_Decode, 241, 10, 196, 1, // Opcode: VLD1d32 +/* 3270 */ MCD_OPC_CheckPredicate, 21, 98, 13, 0, // Skip to: 6701 +/* 3275 */ MCD_OPC_Decode, 251, 10, 196, 1, // Opcode: VLD1d32wb_register +/* 3280 */ MCD_OPC_FilterValue, 3, 88, 13, 0, // Skip to: 6701 +/* 3285 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3288 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3303 +/* 3293 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3318 +/* 3298 */ MCD_OPC_Decode, 137, 11, 196, 1, // Opcode: VLD1d64wb_fixed +/* 3303 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3318 +/* 3308 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3318 +/* 3313 */ MCD_OPC_Decode, 252, 10, 196, 1, // Opcode: VLD1d64 +/* 3318 */ MCD_OPC_CheckPredicate, 21, 50, 13, 0, // Skip to: 6701 +/* 3323 */ MCD_OPC_Decode, 138, 11, 196, 1, // Opcode: VLD1d64wb_register +/* 3328 */ MCD_OPC_FilterValue, 233, 3, 39, 13, 0, // Skip to: 6701 +/* 3334 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3351 +/* 3339 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3351 +/* 3346 */ MCD_OPC_Decode, 225, 12, 201, 1, // Opcode: VLD4LNd16 +/* 3351 */ MCD_OPC_CheckPredicate, 21, 17, 13, 0, // Skip to: 6701 +/* 3356 */ MCD_OPC_Decode, 228, 12, 201, 1, // Opcode: VLD4LNd16_UPD +/* 3361 */ MCD_OPC_FilterValue, 1, 7, 13, 0, // Skip to: 6701 +/* 3366 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 3369 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 3410 +/* 3374 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3377 */ MCD_OPC_FilterValue, 233, 3, 246, 12, 0, // Skip to: 6701 +/* 3383 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3400 +/* 3388 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3400 +/* 3395 */ MCD_OPC_Decode, 162, 20, 200, 1, // Opcode: VST4LNq16 +/* 3400 */ MCD_OPC_CheckPredicate, 21, 224, 12, 0, // Skip to: 6701 +/* 3405 */ MCD_OPC_Decode, 165, 20, 200, 1, // Opcode: VST4LNq16_UPD +/* 3410 */ MCD_OPC_FilterValue, 2, 214, 12, 0, // Skip to: 6701 +/* 3415 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3418 */ MCD_OPC_FilterValue, 233, 3, 205, 12, 0, // Skip to: 6701 +/* 3424 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3441 +/* 3429 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3441 +/* 3436 */ MCD_OPC_Decode, 237, 12, 201, 1, // Opcode: VLD4LNq16 +/* 3441 */ MCD_OPC_CheckPredicate, 21, 183, 12, 0, // Skip to: 6701 +/* 3446 */ MCD_OPC_Decode, 240, 12, 201, 1, // Opcode: VLD4LNq16_UPD +/* 3451 */ MCD_OPC_FilterValue, 8, 185, 1, 0, // Skip to: 3897 +/* 3456 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3459 */ MCD_OPC_FilterValue, 0, 39, 1, 0, // Skip to: 3759 +/* 3464 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 3467 */ MCD_OPC_FilterValue, 0, 141, 0, 0, // Skip to: 3613 +/* 3472 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3475 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 3580 +/* 3481 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 3484 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3532 +/* 3489 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3492 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3507 +/* 3497 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3522 +/* 3502 */ MCD_OPC_Decode, 211, 19, 199, 1, // Opcode: VST2d8wb_fixed +/* 3507 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3522 +/* 3512 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3522 +/* 3517 */ MCD_OPC_Decode, 210, 19, 199, 1, // Opcode: VST2d8 +/* 3522 */ MCD_OPC_CheckPredicate, 21, 102, 12, 0, // Skip to: 6701 +/* 3527 */ MCD_OPC_Decode, 212, 19, 199, 1, // Opcode: VST2d8wb_register +/* 3532 */ MCD_OPC_FilterValue, 1, 92, 12, 0, // Skip to: 6701 +/* 3537 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3540 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3555 +/* 3545 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3570 +/* 3550 */ MCD_OPC_Decode, 208, 19, 199, 1, // Opcode: VST2d32wb_fixed +/* 3555 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3570 +/* 3560 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3570 +/* 3565 */ MCD_OPC_Decode, 207, 19, 199, 1, // Opcode: VST2d32 +/* 3570 */ MCD_OPC_CheckPredicate, 21, 54, 12, 0, // Skip to: 6701 +/* 3575 */ MCD_OPC_Decode, 209, 19, 199, 1, // Opcode: VST2d32wb_register +/* 3580 */ MCD_OPC_FilterValue, 233, 3, 43, 12, 0, // Skip to: 6701 +/* 3586 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3603 +/* 3591 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3603 +/* 3598 */ MCD_OPC_Decode, 217, 18, 192, 1, // Opcode: VST1LNd32 +/* 3603 */ MCD_OPC_CheckPredicate, 21, 21, 12, 0, // Skip to: 6701 +/* 3608 */ MCD_OPC_Decode, 218, 18, 192, 1, // Opcode: VST1LNd32_UPD +/* 3613 */ MCD_OPC_FilterValue, 2, 11, 12, 0, // Skip to: 6701 +/* 3618 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3621 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 3726 +/* 3627 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 3630 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3678 +/* 3635 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3638 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3653 +/* 3643 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3668 +/* 3648 */ MCD_OPC_Decode, 238, 11, 199, 1, // Opcode: VLD2d8wb_fixed +/* 3653 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3668 +/* 3658 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3668 +/* 3663 */ MCD_OPC_Decode, 237, 11, 199, 1, // Opcode: VLD2d8 +/* 3668 */ MCD_OPC_CheckPredicate, 21, 212, 11, 0, // Skip to: 6701 +/* 3673 */ MCD_OPC_Decode, 239, 11, 199, 1, // Opcode: VLD2d8wb_register +/* 3678 */ MCD_OPC_FilterValue, 1, 202, 11, 0, // Skip to: 6701 +/* 3683 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3686 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3701 +/* 3691 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3716 +/* 3696 */ MCD_OPC_Decode, 235, 11, 199, 1, // Opcode: VLD2d32wb_fixed +/* 3701 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3716 +/* 3706 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3716 +/* 3711 */ MCD_OPC_Decode, 234, 11, 199, 1, // Opcode: VLD2d32 +/* 3716 */ MCD_OPC_CheckPredicate, 21, 164, 11, 0, // Skip to: 6701 +/* 3721 */ MCD_OPC_Decode, 236, 11, 199, 1, // Opcode: VLD2d32wb_register +/* 3726 */ MCD_OPC_FilterValue, 233, 3, 153, 11, 0, // Skip to: 6701 +/* 3732 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3749 +/* 3737 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3749 +/* 3744 */ MCD_OPC_Decode, 220, 10, 193, 1, // Opcode: VLD1LNd32 +/* 3749 */ MCD_OPC_CheckPredicate, 21, 131, 11, 0, // Skip to: 6701 +/* 3754 */ MCD_OPC_Decode, 221, 10, 193, 1, // Opcode: VLD1LNd32_UPD +/* 3759 */ MCD_OPC_FilterValue, 1, 121, 11, 0, // Skip to: 6701 +/* 3764 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 3767 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 3832 +/* 3772 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 3775 */ MCD_OPC_FilterValue, 0, 105, 11, 0, // Skip to: 6701 +/* 3780 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3783 */ MCD_OPC_FilterValue, 232, 3, 96, 11, 0, // Skip to: 6701 +/* 3789 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3792 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3807 +/* 3797 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3822 +/* 3802 */ MCD_OPC_Decode, 205, 19, 199, 1, // Opcode: VST2d16wb_fixed +/* 3807 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3822 +/* 3812 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3822 +/* 3817 */ MCD_OPC_Decode, 204, 19, 199, 1, // Opcode: VST2d16 +/* 3822 */ MCD_OPC_CheckPredicate, 21, 58, 11, 0, // Skip to: 6701 +/* 3827 */ MCD_OPC_Decode, 206, 19, 199, 1, // Opcode: VST2d16wb_register +/* 3832 */ MCD_OPC_FilterValue, 2, 48, 11, 0, // Skip to: 6701 +/* 3837 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 3840 */ MCD_OPC_FilterValue, 0, 40, 11, 0, // Skip to: 6701 +/* 3845 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3848 */ MCD_OPC_FilterValue, 232, 3, 31, 11, 0, // Skip to: 6701 +/* 3854 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3857 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3872 +/* 3862 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3887 +/* 3867 */ MCD_OPC_Decode, 232, 11, 199, 1, // Opcode: VLD2d16wb_fixed +/* 3872 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3887 +/* 3877 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3887 +/* 3882 */ MCD_OPC_Decode, 231, 11, 199, 1, // Opcode: VLD2d16 +/* 3887 */ MCD_OPC_CheckPredicate, 21, 249, 10, 0, // Skip to: 6701 +/* 3892 */ MCD_OPC_Decode, 233, 11, 199, 1, // Opcode: VLD2d16wb_register +/* 3897 */ MCD_OPC_FilterValue, 9, 27, 2, 0, // Skip to: 4441 +/* 3902 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 3905 */ MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 4221 +/* 3910 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 3913 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 4067 +/* 3918 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 3921 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4026 +/* 3927 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 3930 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3978 +/* 3935 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3938 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3953 +/* 3943 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3968 +/* 3948 */ MCD_OPC_Decode, 202, 19, 199, 1, // Opcode: VST2b8wb_fixed +/* 3953 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3968 +/* 3958 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3968 +/* 3963 */ MCD_OPC_Decode, 201, 19, 199, 1, // Opcode: VST2b8 +/* 3968 */ MCD_OPC_CheckPredicate, 21, 168, 10, 0, // Skip to: 6701 +/* 3973 */ MCD_OPC_Decode, 203, 19, 199, 1, // Opcode: VST2b8wb_register +/* 3978 */ MCD_OPC_FilterValue, 1, 158, 10, 0, // Skip to: 6701 +/* 3983 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 3986 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4001 +/* 3991 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4016 +/* 3996 */ MCD_OPC_Decode, 199, 19, 199, 1, // Opcode: VST2b32wb_fixed +/* 4001 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4016 +/* 4006 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4016 +/* 4011 */ MCD_OPC_Decode, 198, 19, 199, 1, // Opcode: VST2b32 +/* 4016 */ MCD_OPC_CheckPredicate, 21, 120, 10, 0, // Skip to: 6701 +/* 4021 */ MCD_OPC_Decode, 200, 19, 199, 1, // Opcode: VST2b32wb_register +/* 4026 */ MCD_OPC_FilterValue, 233, 3, 109, 10, 0, // Skip to: 6701 +/* 4032 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 4035 */ MCD_OPC_FilterValue, 0, 101, 10, 0, // Skip to: 6701 +/* 4040 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4057 +/* 4045 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4057 +/* 4052 */ MCD_OPC_Decode, 179, 19, 194, 1, // Opcode: VST2LNd32 +/* 4057 */ MCD_OPC_CheckPredicate, 21, 79, 10, 0, // Skip to: 6701 +/* 4062 */ MCD_OPC_Decode, 182, 19, 194, 1, // Opcode: VST2LNd32_UPD +/* 4067 */ MCD_OPC_FilterValue, 2, 69, 10, 0, // Skip to: 6701 +/* 4072 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4075 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4180 +/* 4081 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4084 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4132 +/* 4089 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4092 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4107 +/* 4097 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4122 +/* 4102 */ MCD_OPC_Decode, 229, 11, 199, 1, // Opcode: VLD2b8wb_fixed +/* 4107 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4122 +/* 4112 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4122 +/* 4117 */ MCD_OPC_Decode, 228, 11, 199, 1, // Opcode: VLD2b8 +/* 4122 */ MCD_OPC_CheckPredicate, 21, 14, 10, 0, // Skip to: 6701 +/* 4127 */ MCD_OPC_Decode, 230, 11, 199, 1, // Opcode: VLD2b8wb_register +/* 4132 */ MCD_OPC_FilterValue, 1, 4, 10, 0, // Skip to: 6701 +/* 4137 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4140 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4155 +/* 4145 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4170 +/* 4150 */ MCD_OPC_Decode, 226, 11, 199, 1, // Opcode: VLD2b32wb_fixed +/* 4155 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4170 +/* 4160 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4170 +/* 4165 */ MCD_OPC_Decode, 225, 11, 199, 1, // Opcode: VLD2b32 +/* 4170 */ MCD_OPC_CheckPredicate, 21, 222, 9, 0, // Skip to: 6701 +/* 4175 */ MCD_OPC_Decode, 227, 11, 199, 1, // Opcode: VLD2b32wb_register +/* 4180 */ MCD_OPC_FilterValue, 233, 3, 211, 9, 0, // Skip to: 6701 +/* 4186 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 4189 */ MCD_OPC_FilterValue, 0, 203, 9, 0, // Skip to: 6701 +/* 4194 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4211 +/* 4199 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4211 +/* 4206 */ MCD_OPC_Decode, 206, 11, 195, 1, // Opcode: VLD2LNd32 +/* 4211 */ MCD_OPC_CheckPredicate, 21, 181, 9, 0, // Skip to: 6701 +/* 4216 */ MCD_OPC_Decode, 209, 11, 195, 1, // Opcode: VLD2LNd32_UPD +/* 4221 */ MCD_OPC_FilterValue, 1, 171, 9, 0, // Skip to: 6701 +/* 4226 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 4229 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 4335 +/* 4234 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4237 */ MCD_OPC_FilterValue, 232, 3, 51, 0, 0, // Skip to: 4294 +/* 4243 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4246 */ MCD_OPC_FilterValue, 0, 146, 9, 0, // Skip to: 6701 +/* 4251 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4254 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4269 +/* 4259 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4284 +/* 4264 */ MCD_OPC_Decode, 196, 19, 199, 1, // Opcode: VST2b16wb_fixed +/* 4269 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4284 +/* 4274 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4284 +/* 4279 */ MCD_OPC_Decode, 195, 19, 199, 1, // Opcode: VST2b16 +/* 4284 */ MCD_OPC_CheckPredicate, 21, 108, 9, 0, // Skip to: 6701 +/* 4289 */ MCD_OPC_Decode, 197, 19, 199, 1, // Opcode: VST2b16wb_register +/* 4294 */ MCD_OPC_FilterValue, 233, 3, 97, 9, 0, // Skip to: 6701 +/* 4300 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 4303 */ MCD_OPC_FilterValue, 0, 89, 9, 0, // Skip to: 6701 +/* 4308 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4325 +/* 4313 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4325 +/* 4320 */ MCD_OPC_Decode, 191, 19, 194, 1, // Opcode: VST2LNq32 +/* 4325 */ MCD_OPC_CheckPredicate, 21, 67, 9, 0, // Skip to: 6701 +/* 4330 */ MCD_OPC_Decode, 194, 19, 194, 1, // Opcode: VST2LNq32_UPD +/* 4335 */ MCD_OPC_FilterValue, 2, 57, 9, 0, // Skip to: 6701 +/* 4340 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4343 */ MCD_OPC_FilterValue, 232, 3, 51, 0, 0, // Skip to: 4400 +/* 4349 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4352 */ MCD_OPC_FilterValue, 0, 40, 9, 0, // Skip to: 6701 +/* 4357 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4360 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4375 +/* 4365 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4390 +/* 4370 */ MCD_OPC_Decode, 223, 11, 199, 1, // Opcode: VLD2b16wb_fixed +/* 4375 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4390 +/* 4380 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4390 +/* 4385 */ MCD_OPC_Decode, 222, 11, 199, 1, // Opcode: VLD2b16 +/* 4390 */ MCD_OPC_CheckPredicate, 21, 2, 9, 0, // Skip to: 6701 +/* 4395 */ MCD_OPC_Decode, 224, 11, 199, 1, // Opcode: VLD2b16wb_register +/* 4400 */ MCD_OPC_FilterValue, 233, 3, 247, 8, 0, // Skip to: 6701 +/* 4406 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 4409 */ MCD_OPC_FilterValue, 0, 239, 8, 0, // Skip to: 6701 +/* 4414 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4431 +/* 4419 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4431 +/* 4426 */ MCD_OPC_Decode, 218, 11, 195, 1, // Opcode: VLD2LNq32 +/* 4431 */ MCD_OPC_CheckPredicate, 21, 217, 8, 0, // Skip to: 6701 +/* 4436 */ MCD_OPC_Decode, 221, 11, 195, 1, // Opcode: VLD2LNq32_UPD +/* 4441 */ MCD_OPC_FilterValue, 10, 123, 2, 0, // Skip to: 5081 +/* 4446 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 4449 */ MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 4765 +/* 4454 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 4457 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 4611 +/* 4462 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4465 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4570 +/* 4471 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4474 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4522 +/* 4479 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4482 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4497 +/* 4487 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4512 +/* 4492 */ MCD_OPC_Decode, 173, 19, 196, 1, // Opcode: VST1q8wb_fixed +/* 4497 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4512 +/* 4502 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4512 +/* 4507 */ MCD_OPC_Decode, 168, 19, 196, 1, // Opcode: VST1q8 +/* 4512 */ MCD_OPC_CheckPredicate, 21, 136, 8, 0, // Skip to: 6701 +/* 4517 */ MCD_OPC_Decode, 174, 19, 196, 1, // Opcode: VST1q8wb_register +/* 4522 */ MCD_OPC_FilterValue, 1, 126, 8, 0, // Skip to: 6701 +/* 4527 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4530 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4545 +/* 4535 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4560 +/* 4540 */ MCD_OPC_Decode, 159, 19, 196, 1, // Opcode: VST1q32wb_fixed +/* 4545 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4560 +/* 4550 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4560 +/* 4555 */ MCD_OPC_Decode, 154, 19, 196, 1, // Opcode: VST1q32 +/* 4560 */ MCD_OPC_CheckPredicate, 21, 88, 8, 0, // Skip to: 6701 +/* 4565 */ MCD_OPC_Decode, 160, 19, 196, 1, // Opcode: VST1q32wb_register +/* 4570 */ MCD_OPC_FilterValue, 233, 3, 77, 8, 0, // Skip to: 6701 +/* 4576 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 4579 */ MCD_OPC_FilterValue, 0, 69, 8, 0, // Skip to: 6701 +/* 4584 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4601 +/* 4589 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4601 +/* 4596 */ MCD_OPC_Decode, 235, 19, 197, 1, // Opcode: VST3LNd32 +/* 4601 */ MCD_OPC_CheckPredicate, 21, 47, 8, 0, // Skip to: 6701 +/* 4606 */ MCD_OPC_Decode, 238, 19, 197, 1, // Opcode: VST3LNd32_UPD +/* 4611 */ MCD_OPC_FilterValue, 2, 37, 8, 0, // Skip to: 6701 +/* 4616 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4619 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4724 +/* 4625 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4628 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4676 +/* 4633 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4636 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4651 +/* 4641 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4666 +/* 4646 */ MCD_OPC_Decode, 176, 11, 196, 1, // Opcode: VLD1q8wb_fixed +/* 4651 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4666 +/* 4656 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4666 +/* 4661 */ MCD_OPC_Decode, 171, 11, 196, 1, // Opcode: VLD1q8 +/* 4666 */ MCD_OPC_CheckPredicate, 21, 238, 7, 0, // Skip to: 6701 +/* 4671 */ MCD_OPC_Decode, 177, 11, 196, 1, // Opcode: VLD1q8wb_register +/* 4676 */ MCD_OPC_FilterValue, 1, 228, 7, 0, // Skip to: 6701 +/* 4681 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4684 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4699 +/* 4689 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4714 +/* 4694 */ MCD_OPC_Decode, 162, 11, 196, 1, // Opcode: VLD1q32wb_fixed +/* 4699 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4714 +/* 4704 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4714 +/* 4709 */ MCD_OPC_Decode, 157, 11, 196, 1, // Opcode: VLD1q32 +/* 4714 */ MCD_OPC_CheckPredicate, 21, 190, 7, 0, // Skip to: 6701 +/* 4719 */ MCD_OPC_Decode, 163, 11, 196, 1, // Opcode: VLD1q32wb_register +/* 4724 */ MCD_OPC_FilterValue, 233, 3, 179, 7, 0, // Skip to: 6701 +/* 4730 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 4733 */ MCD_OPC_FilterValue, 0, 171, 7, 0, // Skip to: 6701 +/* 4738 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4755 +/* 4743 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4755 +/* 4750 */ MCD_OPC_Decode, 158, 12, 198, 1, // Opcode: VLD3LNd32 +/* 4755 */ MCD_OPC_CheckPredicate, 21, 149, 7, 0, // Skip to: 6701 +/* 4760 */ MCD_OPC_Decode, 161, 12, 198, 1, // Opcode: VLD3LNd32_UPD +/* 4765 */ MCD_OPC_FilterValue, 1, 139, 7, 0, // Skip to: 6701 +/* 4770 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 4773 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 4927 +/* 4778 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4781 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4886 +/* 4787 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4790 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4838 +/* 4795 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4798 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4813 +/* 4803 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4828 +/* 4808 */ MCD_OPC_Decode, 152, 19, 196, 1, // Opcode: VST1q16wb_fixed +/* 4813 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4828 +/* 4818 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4828 +/* 4823 */ MCD_OPC_Decode, 147, 19, 196, 1, // Opcode: VST1q16 +/* 4828 */ MCD_OPC_CheckPredicate, 21, 76, 7, 0, // Skip to: 6701 +/* 4833 */ MCD_OPC_Decode, 153, 19, 196, 1, // Opcode: VST1q16wb_register +/* 4838 */ MCD_OPC_FilterValue, 1, 66, 7, 0, // Skip to: 6701 +/* 4843 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4846 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4861 +/* 4851 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4876 +/* 4856 */ MCD_OPC_Decode, 166, 19, 196, 1, // Opcode: VST1q64wb_fixed +/* 4861 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4876 +/* 4866 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4876 +/* 4871 */ MCD_OPC_Decode, 161, 19, 196, 1, // Opcode: VST1q64 +/* 4876 */ MCD_OPC_CheckPredicate, 21, 28, 7, 0, // Skip to: 6701 +/* 4881 */ MCD_OPC_Decode, 167, 19, 196, 1, // Opcode: VST1q64wb_register +/* 4886 */ MCD_OPC_FilterValue, 233, 3, 17, 7, 0, // Skip to: 6701 +/* 4892 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 4895 */ MCD_OPC_FilterValue, 0, 9, 7, 0, // Skip to: 6701 +/* 4900 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4917 +/* 4905 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4917 +/* 4912 */ MCD_OPC_Decode, 247, 19, 197, 1, // Opcode: VST3LNq32 +/* 4917 */ MCD_OPC_CheckPredicate, 21, 243, 6, 0, // Skip to: 6701 +/* 4922 */ MCD_OPC_Decode, 250, 19, 197, 1, // Opcode: VST3LNq32_UPD +/* 4927 */ MCD_OPC_FilterValue, 2, 233, 6, 0, // Skip to: 6701 +/* 4932 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 4935 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 5040 +/* 4941 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4944 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4992 +/* 4949 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 4952 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4967 +/* 4957 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4982 +/* 4962 */ MCD_OPC_Decode, 155, 11, 196, 1, // Opcode: VLD1q16wb_fixed +/* 4967 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4982 +/* 4972 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4982 +/* 4977 */ MCD_OPC_Decode, 150, 11, 196, 1, // Opcode: VLD1q16 +/* 4982 */ MCD_OPC_CheckPredicate, 21, 178, 6, 0, // Skip to: 6701 +/* 4987 */ MCD_OPC_Decode, 156, 11, 196, 1, // Opcode: VLD1q16wb_register +/* 4992 */ MCD_OPC_FilterValue, 1, 168, 6, 0, // Skip to: 6701 +/* 4997 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5000 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5015 +/* 5005 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5030 +/* 5010 */ MCD_OPC_Decode, 169, 11, 196, 1, // Opcode: VLD1q64wb_fixed +/* 5015 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5030 +/* 5020 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5030 +/* 5025 */ MCD_OPC_Decode, 164, 11, 196, 1, // Opcode: VLD1q64 +/* 5030 */ MCD_OPC_CheckPredicate, 21, 130, 6, 0, // Skip to: 6701 +/* 5035 */ MCD_OPC_Decode, 170, 11, 196, 1, // Opcode: VLD1q64wb_register +/* 5040 */ MCD_OPC_FilterValue, 233, 3, 119, 6, 0, // Skip to: 6701 +/* 5046 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 5049 */ MCD_OPC_FilterValue, 0, 111, 6, 0, // Skip to: 6701 +/* 5054 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5071 +/* 5059 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5071 +/* 5066 */ MCD_OPC_Decode, 170, 12, 198, 1, // Opcode: VLD3LNq32 +/* 5071 */ MCD_OPC_CheckPredicate, 21, 89, 6, 0, // Skip to: 6701 +/* 5076 */ MCD_OPC_Decode, 173, 12, 198, 1, // Opcode: VLD3LNq32_UPD +/* 5081 */ MCD_OPC_FilterValue, 11, 183, 0, 0, // Skip to: 5269 +/* 5086 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 5089 */ MCD_OPC_FilterValue, 0, 85, 0, 0, // Skip to: 5179 +/* 5094 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5097 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 5138 +/* 5102 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5105 */ MCD_OPC_FilterValue, 233, 3, 54, 6, 0, // Skip to: 6701 +/* 5111 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5128 +/* 5116 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5128 +/* 5123 */ MCD_OPC_Decode, 154, 20, 200, 1, // Opcode: VST4LNd32 +/* 5128 */ MCD_OPC_CheckPredicate, 21, 32, 6, 0, // Skip to: 6701 +/* 5133 */ MCD_OPC_Decode, 157, 20, 200, 1, // Opcode: VST4LNd32_UPD +/* 5138 */ MCD_OPC_FilterValue, 2, 22, 6, 0, // Skip to: 6701 +/* 5143 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5146 */ MCD_OPC_FilterValue, 233, 3, 13, 6, 0, // Skip to: 6701 +/* 5152 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5169 +/* 5157 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5169 +/* 5164 */ MCD_OPC_Decode, 229, 12, 201, 1, // Opcode: VLD4LNd32 +/* 5169 */ MCD_OPC_CheckPredicate, 21, 247, 5, 0, // Skip to: 6701 +/* 5174 */ MCD_OPC_Decode, 232, 12, 201, 1, // Opcode: VLD4LNd32_UPD +/* 5179 */ MCD_OPC_FilterValue, 1, 237, 5, 0, // Skip to: 6701 +/* 5184 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5187 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 5228 +/* 5192 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5195 */ MCD_OPC_FilterValue, 233, 3, 220, 5, 0, // Skip to: 6701 +/* 5201 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5218 +/* 5206 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5218 +/* 5213 */ MCD_OPC_Decode, 166, 20, 200, 1, // Opcode: VST4LNq32 +/* 5218 */ MCD_OPC_CheckPredicate, 21, 198, 5, 0, // Skip to: 6701 +/* 5223 */ MCD_OPC_Decode, 169, 20, 200, 1, // Opcode: VST4LNq32_UPD +/* 5228 */ MCD_OPC_FilterValue, 2, 188, 5, 0, // Skip to: 6701 +/* 5233 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5236 */ MCD_OPC_FilterValue, 233, 3, 179, 5, 0, // Skip to: 6701 +/* 5242 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5259 +/* 5247 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5259 +/* 5254 */ MCD_OPC_Decode, 241, 12, 201, 1, // Opcode: VLD4LNq32 +/* 5259 */ MCD_OPC_CheckPredicate, 21, 157, 5, 0, // Skip to: 6701 +/* 5264 */ MCD_OPC_Decode, 244, 12, 201, 1, // Opcode: VLD4LNq32_UPD +/* 5269 */ MCD_OPC_FilterValue, 12, 137, 1, 0, // Skip to: 5667 +/* 5274 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 5277 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 5342 +/* 5282 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5285 */ MCD_OPC_FilterValue, 2, 131, 5, 0, // Skip to: 6701 +/* 5290 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5293 */ MCD_OPC_FilterValue, 233, 3, 122, 5, 0, // Skip to: 6701 +/* 5299 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5302 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5317 +/* 5307 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5332 +/* 5312 */ MCD_OPC_Decode, 207, 10, 203, 1, // Opcode: VLD1DUPd8wb_fixed +/* 5317 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5332 +/* 5322 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5332 +/* 5327 */ MCD_OPC_Decode, 206, 10, 203, 1, // Opcode: VLD1DUPd8 +/* 5332 */ MCD_OPC_CheckPredicate, 21, 84, 5, 0, // Skip to: 6701 +/* 5337 */ MCD_OPC_Decode, 208, 10, 203, 1, // Opcode: VLD1DUPd8wb_register +/* 5342 */ MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 5407 +/* 5347 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5350 */ MCD_OPC_FilterValue, 2, 66, 5, 0, // Skip to: 6701 +/* 5355 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5358 */ MCD_OPC_FilterValue, 233, 3, 57, 5, 0, // Skip to: 6701 +/* 5364 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5367 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5382 +/* 5372 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5397 +/* 5377 */ MCD_OPC_Decode, 216, 10, 203, 1, // Opcode: VLD1DUPq8wb_fixed +/* 5382 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5397 +/* 5387 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5397 +/* 5392 */ MCD_OPC_Decode, 215, 10, 203, 1, // Opcode: VLD1DUPq8 +/* 5397 */ MCD_OPC_CheckPredicate, 21, 19, 5, 0, // Skip to: 6701 +/* 5402 */ MCD_OPC_Decode, 217, 10, 203, 1, // Opcode: VLD1DUPq8wb_register +/* 5407 */ MCD_OPC_FilterValue, 2, 60, 0, 0, // Skip to: 5472 +/* 5412 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5415 */ MCD_OPC_FilterValue, 2, 1, 5, 0, // Skip to: 6701 +/* 5420 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5423 */ MCD_OPC_FilterValue, 233, 3, 248, 4, 0, // Skip to: 6701 +/* 5429 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5432 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5447 +/* 5437 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5462 +/* 5442 */ MCD_OPC_Decode, 201, 10, 203, 1, // Opcode: VLD1DUPd16wb_fixed +/* 5447 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5462 +/* 5452 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5462 +/* 5457 */ MCD_OPC_Decode, 200, 10, 203, 1, // Opcode: VLD1DUPd16 +/* 5462 */ MCD_OPC_CheckPredicate, 21, 210, 4, 0, // Skip to: 6701 +/* 5467 */ MCD_OPC_Decode, 202, 10, 203, 1, // Opcode: VLD1DUPd16wb_register +/* 5472 */ MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 5537 +/* 5477 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5480 */ MCD_OPC_FilterValue, 2, 192, 4, 0, // Skip to: 6701 +/* 5485 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5488 */ MCD_OPC_FilterValue, 233, 3, 183, 4, 0, // Skip to: 6701 +/* 5494 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5497 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5512 +/* 5502 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5527 +/* 5507 */ MCD_OPC_Decode, 210, 10, 203, 1, // Opcode: VLD1DUPq16wb_fixed +/* 5512 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5527 +/* 5517 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5527 +/* 5522 */ MCD_OPC_Decode, 209, 10, 203, 1, // Opcode: VLD1DUPq16 +/* 5527 */ MCD_OPC_CheckPredicate, 21, 145, 4, 0, // Skip to: 6701 +/* 5532 */ MCD_OPC_Decode, 211, 10, 203, 1, // Opcode: VLD1DUPq16wb_register +/* 5537 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 5602 +/* 5542 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5545 */ MCD_OPC_FilterValue, 2, 127, 4, 0, // Skip to: 6701 +/* 5550 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5553 */ MCD_OPC_FilterValue, 233, 3, 118, 4, 0, // Skip to: 6701 +/* 5559 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5562 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5577 +/* 5567 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5592 +/* 5572 */ MCD_OPC_Decode, 204, 10, 203, 1, // Opcode: VLD1DUPd32wb_fixed +/* 5577 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5592 +/* 5582 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5592 +/* 5587 */ MCD_OPC_Decode, 203, 10, 203, 1, // Opcode: VLD1DUPd32 +/* 5592 */ MCD_OPC_CheckPredicate, 21, 80, 4, 0, // Skip to: 6701 +/* 5597 */ MCD_OPC_Decode, 205, 10, 203, 1, // Opcode: VLD1DUPd32wb_register +/* 5602 */ MCD_OPC_FilterValue, 5, 70, 4, 0, // Skip to: 6701 +/* 5607 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5610 */ MCD_OPC_FilterValue, 2, 62, 4, 0, // Skip to: 6701 +/* 5615 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5618 */ MCD_OPC_FilterValue, 233, 3, 53, 4, 0, // Skip to: 6701 +/* 5624 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5627 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5642 +/* 5632 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5657 +/* 5637 */ MCD_OPC_Decode, 213, 10, 203, 1, // Opcode: VLD1DUPq32wb_fixed +/* 5642 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5657 +/* 5647 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5657 +/* 5652 */ MCD_OPC_Decode, 212, 10, 203, 1, // Opcode: VLD1DUPq32 +/* 5657 */ MCD_OPC_CheckPredicate, 21, 15, 4, 0, // Skip to: 6701 +/* 5662 */ MCD_OPC_Decode, 214, 10, 203, 1, // Opcode: VLD1DUPq32wb_register +/* 5667 */ MCD_OPC_FilterValue, 13, 137, 1, 0, // Skip to: 6065 +/* 5672 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 5675 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 5740 +/* 5680 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5683 */ MCD_OPC_FilterValue, 2, 245, 3, 0, // Skip to: 6701 +/* 5688 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5691 */ MCD_OPC_FilterValue, 233, 3, 236, 3, 0, // Skip to: 6701 +/* 5697 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5700 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5715 +/* 5705 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5730 +/* 5710 */ MCD_OPC_Decode, 191, 11, 204, 1, // Opcode: VLD2DUPd8wb_fixed +/* 5715 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5730 +/* 5720 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5730 +/* 5725 */ MCD_OPC_Decode, 190, 11, 204, 1, // Opcode: VLD2DUPd8 +/* 5730 */ MCD_OPC_CheckPredicate, 21, 198, 3, 0, // Skip to: 6701 +/* 5735 */ MCD_OPC_Decode, 192, 11, 204, 1, // Opcode: VLD2DUPd8wb_register +/* 5740 */ MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 5805 +/* 5745 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5748 */ MCD_OPC_FilterValue, 2, 180, 3, 0, // Skip to: 6701 +/* 5753 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5756 */ MCD_OPC_FilterValue, 233, 3, 171, 3, 0, // Skip to: 6701 +/* 5762 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5765 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5780 +/* 5770 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5795 +/* 5775 */ MCD_OPC_Decode, 194, 11, 204, 1, // Opcode: VLD2DUPd8x2wb_fixed +/* 5780 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5795 +/* 5785 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5795 +/* 5790 */ MCD_OPC_Decode, 193, 11, 204, 1, // Opcode: VLD2DUPd8x2 +/* 5795 */ MCD_OPC_CheckPredicate, 21, 133, 3, 0, // Skip to: 6701 +/* 5800 */ MCD_OPC_Decode, 195, 11, 204, 1, // Opcode: VLD2DUPd8x2wb_register +/* 5805 */ MCD_OPC_FilterValue, 2, 60, 0, 0, // Skip to: 5870 +/* 5810 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5813 */ MCD_OPC_FilterValue, 2, 115, 3, 0, // Skip to: 6701 +/* 5818 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5821 */ MCD_OPC_FilterValue, 233, 3, 106, 3, 0, // Skip to: 6701 +/* 5827 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5830 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5845 +/* 5835 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5860 +/* 5840 */ MCD_OPC_Decode, 179, 11, 204, 1, // Opcode: VLD2DUPd16wb_fixed +/* 5845 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5860 +/* 5850 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5860 +/* 5855 */ MCD_OPC_Decode, 178, 11, 204, 1, // Opcode: VLD2DUPd16 +/* 5860 */ MCD_OPC_CheckPredicate, 21, 68, 3, 0, // Skip to: 6701 +/* 5865 */ MCD_OPC_Decode, 180, 11, 204, 1, // Opcode: VLD2DUPd16wb_register +/* 5870 */ MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 5935 +/* 5875 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5878 */ MCD_OPC_FilterValue, 2, 50, 3, 0, // Skip to: 6701 +/* 5883 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5886 */ MCD_OPC_FilterValue, 233, 3, 41, 3, 0, // Skip to: 6701 +/* 5892 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5895 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5910 +/* 5900 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5925 +/* 5905 */ MCD_OPC_Decode, 182, 11, 204, 1, // Opcode: VLD2DUPd16x2wb_fixed +/* 5910 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5925 +/* 5915 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5925 +/* 5920 */ MCD_OPC_Decode, 181, 11, 204, 1, // Opcode: VLD2DUPd16x2 +/* 5925 */ MCD_OPC_CheckPredicate, 21, 3, 3, 0, // Skip to: 6701 +/* 5930 */ MCD_OPC_Decode, 183, 11, 204, 1, // Opcode: VLD2DUPd16x2wb_register +/* 5935 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 6000 +/* 5940 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 5943 */ MCD_OPC_FilterValue, 2, 241, 2, 0, // Skip to: 6701 +/* 5948 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 5951 */ MCD_OPC_FilterValue, 233, 3, 232, 2, 0, // Skip to: 6701 +/* 5957 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 5960 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5975 +/* 5965 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5990 +/* 5970 */ MCD_OPC_Decode, 185, 11, 204, 1, // Opcode: VLD2DUPd32wb_fixed +/* 5975 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5990 +/* 5980 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5990 +/* 5985 */ MCD_OPC_Decode, 184, 11, 204, 1, // Opcode: VLD2DUPd32 +/* 5990 */ MCD_OPC_CheckPredicate, 21, 194, 2, 0, // Skip to: 6701 +/* 5995 */ MCD_OPC_Decode, 186, 11, 204, 1, // Opcode: VLD2DUPd32wb_register +/* 6000 */ MCD_OPC_FilterValue, 5, 184, 2, 0, // Skip to: 6701 +/* 6005 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6008 */ MCD_OPC_FilterValue, 2, 176, 2, 0, // Skip to: 6701 +/* 6013 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6016 */ MCD_OPC_FilterValue, 233, 3, 167, 2, 0, // Skip to: 6701 +/* 6022 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 6025 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 6040 +/* 6030 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 6055 +/* 6035 */ MCD_OPC_Decode, 188, 11, 204, 1, // Opcode: VLD2DUPd32x2wb_fixed +/* 6040 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 6055 +/* 6045 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 6055 +/* 6050 */ MCD_OPC_Decode, 187, 11, 204, 1, // Opcode: VLD2DUPd32x2 +/* 6055 */ MCD_OPC_CheckPredicate, 21, 129, 2, 0, // Skip to: 6701 +/* 6060 */ MCD_OPC_Decode, 189, 11, 204, 1, // Opcode: VLD2DUPd32x2wb_register +/* 6065 */ MCD_OPC_FilterValue, 14, 41, 1, 0, // Skip to: 6367 +/* 6070 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 6073 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 6122 +/* 6078 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6081 */ MCD_OPC_FilterValue, 2, 103, 2, 0, // Skip to: 6701 +/* 6086 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6089 */ MCD_OPC_FilterValue, 233, 3, 94, 2, 0, // Skip to: 6701 +/* 6095 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6112 +/* 6100 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6112 +/* 6107 */ MCD_OPC_Decode, 138, 12, 205, 1, // Opcode: VLD3DUPd8 +/* 6112 */ MCD_OPC_CheckPredicate, 21, 72, 2, 0, // Skip to: 6701 +/* 6117 */ MCD_OPC_Decode, 141, 12, 205, 1, // Opcode: VLD3DUPd8_UPD +/* 6122 */ MCD_OPC_FilterValue, 2, 44, 0, 0, // Skip to: 6171 +/* 6127 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6130 */ MCD_OPC_FilterValue, 2, 54, 2, 0, // Skip to: 6701 +/* 6135 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6138 */ MCD_OPC_FilterValue, 233, 3, 45, 2, 0, // Skip to: 6701 +/* 6144 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6161 +/* 6149 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6161 +/* 6156 */ MCD_OPC_Decode, 150, 12, 205, 1, // Opcode: VLD3DUPq8 +/* 6161 */ MCD_OPC_CheckPredicate, 21, 23, 2, 0, // Skip to: 6701 +/* 6166 */ MCD_OPC_Decode, 153, 12, 205, 1, // Opcode: VLD3DUPq8_UPD +/* 6171 */ MCD_OPC_FilterValue, 4, 44, 0, 0, // Skip to: 6220 +/* 6176 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6179 */ MCD_OPC_FilterValue, 2, 5, 2, 0, // Skip to: 6701 +/* 6184 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6187 */ MCD_OPC_FilterValue, 233, 3, 252, 1, 0, // Skip to: 6701 +/* 6193 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6210 +/* 6198 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6210 +/* 6205 */ MCD_OPC_Decode, 130, 12, 205, 1, // Opcode: VLD3DUPd16 +/* 6210 */ MCD_OPC_CheckPredicate, 21, 230, 1, 0, // Skip to: 6701 +/* 6215 */ MCD_OPC_Decode, 133, 12, 205, 1, // Opcode: VLD3DUPd16_UPD +/* 6220 */ MCD_OPC_FilterValue, 6, 44, 0, 0, // Skip to: 6269 +/* 6225 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6228 */ MCD_OPC_FilterValue, 2, 212, 1, 0, // Skip to: 6701 +/* 6233 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6236 */ MCD_OPC_FilterValue, 233, 3, 203, 1, 0, // Skip to: 6701 +/* 6242 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6259 +/* 6247 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6259 +/* 6254 */ MCD_OPC_Decode, 142, 12, 205, 1, // Opcode: VLD3DUPq16 +/* 6259 */ MCD_OPC_CheckPredicate, 21, 181, 1, 0, // Skip to: 6701 +/* 6264 */ MCD_OPC_Decode, 145, 12, 205, 1, // Opcode: VLD3DUPq16_UPD +/* 6269 */ MCD_OPC_FilterValue, 8, 44, 0, 0, // Skip to: 6318 +/* 6274 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6277 */ MCD_OPC_FilterValue, 2, 163, 1, 0, // Skip to: 6701 +/* 6282 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6285 */ MCD_OPC_FilterValue, 233, 3, 154, 1, 0, // Skip to: 6701 +/* 6291 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6308 +/* 6296 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6308 +/* 6303 */ MCD_OPC_Decode, 134, 12, 205, 1, // Opcode: VLD3DUPd32 +/* 6308 */ MCD_OPC_CheckPredicate, 21, 132, 1, 0, // Skip to: 6701 +/* 6313 */ MCD_OPC_Decode, 137, 12, 205, 1, // Opcode: VLD3DUPd32_UPD +/* 6318 */ MCD_OPC_FilterValue, 10, 122, 1, 0, // Skip to: 6701 +/* 6323 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6326 */ MCD_OPC_FilterValue, 2, 114, 1, 0, // Skip to: 6701 +/* 6331 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6334 */ MCD_OPC_FilterValue, 233, 3, 105, 1, 0, // Skip to: 6701 +/* 6340 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6357 +/* 6345 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6357 +/* 6352 */ MCD_OPC_Decode, 146, 12, 205, 1, // Opcode: VLD3DUPq32 +/* 6357 */ MCD_OPC_CheckPredicate, 21, 83, 1, 0, // Skip to: 6701 +/* 6362 */ MCD_OPC_Decode, 149, 12, 205, 1, // Opcode: VLD3DUPq32_UPD +/* 6367 */ MCD_OPC_FilterValue, 15, 73, 1, 0, // Skip to: 6701 +/* 6372 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 6375 */ MCD_OPC_FilterValue, 0, 158, 0, 0, // Skip to: 6538 +/* 6380 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 6383 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 6489 +/* 6388 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6391 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 6440 +/* 6396 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6399 */ MCD_OPC_FilterValue, 2, 41, 1, 0, // Skip to: 6701 +/* 6404 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6407 */ MCD_OPC_FilterValue, 233, 3, 32, 1, 0, // Skip to: 6701 +/* 6413 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6430 +/* 6418 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6430 +/* 6425 */ MCD_OPC_Decode, 209, 12, 206, 1, // Opcode: VLD4DUPd8 +/* 6430 */ MCD_OPC_CheckPredicate, 21, 10, 1, 0, // Skip to: 6701 +/* 6435 */ MCD_OPC_Decode, 212, 12, 206, 1, // Opcode: VLD4DUPd8_UPD +/* 6440 */ MCD_OPC_FilterValue, 1, 0, 1, 0, // Skip to: 6701 +/* 6445 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6448 */ MCD_OPC_FilterValue, 2, 248, 0, 0, // Skip to: 6701 +/* 6453 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6456 */ MCD_OPC_FilterValue, 233, 3, 239, 0, 0, // Skip to: 6701 +/* 6462 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6479 +/* 6467 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6479 +/* 6474 */ MCD_OPC_Decode, 201, 12, 206, 1, // Opcode: VLD4DUPd16 +/* 6479 */ MCD_OPC_CheckPredicate, 21, 217, 0, 0, // Skip to: 6701 +/* 6484 */ MCD_OPC_Decode, 204, 12, 206, 1, // Opcode: VLD4DUPd16_UPD +/* 6489 */ MCD_OPC_FilterValue, 1, 207, 0, 0, // Skip to: 6701 +/* 6494 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6497 */ MCD_OPC_FilterValue, 2, 199, 0, 0, // Skip to: 6701 +/* 6502 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6505 */ MCD_OPC_FilterValue, 233, 3, 190, 0, 0, // Skip to: 6701 +/* 6511 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6528 +/* 6516 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6528 +/* 6523 */ MCD_OPC_Decode, 205, 12, 206, 1, // Opcode: VLD4DUPd32 +/* 6528 */ MCD_OPC_CheckPredicate, 21, 168, 0, 0, // Skip to: 6701 +/* 6533 */ MCD_OPC_Decode, 208, 12, 206, 1, // Opcode: VLD4DUPd32_UPD +/* 6538 */ MCD_OPC_FilterValue, 1, 158, 0, 0, // Skip to: 6701 +/* 6543 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 6546 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 6652 +/* 6551 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 6554 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 6603 +/* 6559 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6562 */ MCD_OPC_FilterValue, 2, 134, 0, 0, // Skip to: 6701 +/* 6567 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6570 */ MCD_OPC_FilterValue, 233, 3, 125, 0, 0, // Skip to: 6701 +/* 6576 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6593 +/* 6581 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6593 +/* 6588 */ MCD_OPC_Decode, 221, 12, 206, 1, // Opcode: VLD4DUPq8 +/* 6593 */ MCD_OPC_CheckPredicate, 21, 103, 0, 0, // Skip to: 6701 +/* 6598 */ MCD_OPC_Decode, 224, 12, 206, 1, // Opcode: VLD4DUPq8_UPD +/* 6603 */ MCD_OPC_FilterValue, 1, 93, 0, 0, // Skip to: 6701 +/* 6608 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6611 */ MCD_OPC_FilterValue, 2, 85, 0, 0, // Skip to: 6701 +/* 6616 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6619 */ MCD_OPC_FilterValue, 233, 3, 76, 0, 0, // Skip to: 6701 +/* 6625 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6642 +/* 6630 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6642 +/* 6637 */ MCD_OPC_Decode, 213, 12, 206, 1, // Opcode: VLD4DUPq16 +/* 6642 */ MCD_OPC_CheckPredicate, 21, 54, 0, 0, // Skip to: 6701 +/* 6647 */ MCD_OPC_Decode, 216, 12, 206, 1, // Opcode: VLD4DUPq16_UPD +/* 6652 */ MCD_OPC_FilterValue, 1, 44, 0, 0, // Skip to: 6701 +/* 6657 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 6660 */ MCD_OPC_FilterValue, 2, 36, 0, 0, // Skip to: 6701 +/* 6665 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 6668 */ MCD_OPC_FilterValue, 233, 3, 27, 0, 0, // Skip to: 6701 +/* 6674 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6691 +/* 6679 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6691 +/* 6686 */ MCD_OPC_Decode, 217, 12, 206, 1, // Opcode: VLD4DUPq32 +/* 6691 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 6701 +/* 6696 */ MCD_OPC_Decode, 220, 12, 206, 1, // Opcode: VLD4DUPq32_UPD +/* 6701 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb16[] = { +/* 0 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 3 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25 +/* 8 */ MCD_OPC_CheckPredicate, 28, 181, 4, 0, // Skip to: 1218 +/* 13 */ MCD_OPC_CheckField, 6, 6, 0, 174, 4, 0, // Skip to: 1218 +/* 20 */ MCD_OPC_Decode, 236, 24, 207, 1, // Opcode: tMOVSr +/* 25 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 47 +/* 30 */ MCD_OPC_CheckPredicate, 28, 159, 4, 0, // Skip to: 1218 +/* 35 */ MCD_OPC_CheckField, 11, 1, 1, 152, 4, 0, // Skip to: 1218 +/* 42 */ MCD_OPC_Decode, 212, 24, 208, 1, // Opcode: tCMPi8 +/* 47 */ MCD_OPC_FilterValue, 4, 3, 1, 0, // Skip to: 311 +/* 52 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 55 */ MCD_OPC_FilterValue, 0, 236, 0, 0, // Skip to: 296 +/* 60 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... +/* 63 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 116 +/* 68 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 71 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 86 +/* 76 */ MCD_OPC_CheckPredicate, 28, 113, 4, 0, // Skip to: 1218 +/* 81 */ MCD_OPC_Decode, 140, 25, 207, 1, // Opcode: tTST +/* 86 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 101 +/* 91 */ MCD_OPC_CheckPredicate, 28, 98, 4, 0, // Skip to: 1218 +/* 96 */ MCD_OPC_Decode, 213, 24, 207, 1, // Opcode: tCMPr +/* 101 */ MCD_OPC_FilterValue, 3, 88, 4, 0, // Skip to: 1218 +/* 106 */ MCD_OPC_CheckPredicate, 28, 83, 4, 0, // Skip to: 1218 +/* 111 */ MCD_OPC_Decode, 210, 24, 207, 1, // Opcode: tCMNz +/* 116 */ MCD_OPC_FilterValue, 4, 51, 0, 0, // Skip to: 172 +/* 121 */ MCD_OPC_CheckPredicate, 28, 12, 0, 0, // Skip to: 138 +/* 126 */ MCD_OPC_CheckField, 3, 4, 13, 5, 0, 0, // Skip to: 138 +/* 133 */ MCD_OPC_Decode, 189, 24, 209, 1, // Opcode: tADDrSP +/* 138 */ MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 162 +/* 143 */ MCD_OPC_CheckField, 7, 1, 1, 12, 0, 0, // Skip to: 162 +/* 150 */ MCD_OPC_CheckField, 0, 3, 5, 5, 0, 0, // Skip to: 162 +/* 157 */ MCD_OPC_Decode, 193, 24, 209, 1, // Opcode: tADDspr +/* 162 */ MCD_OPC_CheckPredicate, 28, 27, 4, 0, // Skip to: 1218 +/* 167 */ MCD_OPC_Decode, 186, 24, 210, 1, // Opcode: tADDhirr +/* 172 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 187 +/* 177 */ MCD_OPC_CheckPredicate, 28, 12, 4, 0, // Skip to: 1218 +/* 182 */ MCD_OPC_Decode, 211, 24, 211, 1, // Opcode: tCMPhir +/* 187 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 202 +/* 192 */ MCD_OPC_CheckPredicate, 28, 253, 3, 0, // Skip to: 1218 +/* 197 */ MCD_OPC_Decode, 238, 24, 211, 1, // Opcode: tMOVr +/* 202 */ MCD_OPC_FilterValue, 7, 243, 3, 0, // Skip to: 1218 +/* 207 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 210 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 248 +/* 215 */ MCD_OPC_CheckPredicate, 29, 15, 0, 0, // Skip to: 235 +/* 220 */ MCD_OPC_CheckField, 2, 1, 1, 8, 0, 0, // Skip to: 235 +/* 227 */ MCD_OPC_SoftFail, 3, 0, +/* 230 */ MCD_OPC_Decode, 206, 24, 212, 1, // Opcode: tBXNS +/* 235 */ MCD_OPC_CheckPredicate, 28, 210, 3, 0, // Skip to: 1218 +/* 240 */ MCD_OPC_SoftFail, 7, 0, +/* 243 */ MCD_OPC_Decode, 205, 24, 212, 1, // Opcode: tBX +/* 248 */ MCD_OPC_FilterValue, 1, 197, 3, 0, // Skip to: 1218 +/* 253 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... +/* 256 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 278 +/* 261 */ MCD_OPC_CheckPredicate, 30, 184, 3, 0, // Skip to: 1218 +/* 266 */ MCD_OPC_CheckField, 0, 2, 0, 177, 3, 0, // Skip to: 1218 +/* 273 */ MCD_OPC_Decode, 204, 24, 212, 1, // Opcode: tBLXr +/* 278 */ MCD_OPC_FilterValue, 1, 167, 3, 0, // Skip to: 1218 +/* 283 */ MCD_OPC_CheckPredicate, 29, 162, 3, 0, // Skip to: 1218 +/* 288 */ MCD_OPC_SoftFail, 3, 0, +/* 291 */ MCD_OPC_Decode, 202, 24, 213, 1, // Opcode: tBLXNSr +/* 296 */ MCD_OPC_FilterValue, 1, 149, 3, 0, // Skip to: 1218 +/* 301 */ MCD_OPC_CheckPredicate, 28, 144, 3, 0, // Skip to: 1218 +/* 306 */ MCD_OPC_Decode, 229, 24, 214, 1, // Opcode: tLDRpci +/* 311 */ MCD_OPC_FilterValue, 5, 123, 0, 0, // Skip to: 439 +/* 316 */ MCD_OPC_ExtractField, 9, 3, // Inst{11-9} ... +/* 319 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 334 +/* 324 */ MCD_OPC_CheckPredicate, 28, 121, 3, 0, // Skip to: 1218 +/* 329 */ MCD_OPC_Decode, 130, 25, 215, 1, // Opcode: tSTRr +/* 334 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 349 +/* 339 */ MCD_OPC_CheckPredicate, 28, 106, 3, 0, // Skip to: 1218 +/* 344 */ MCD_OPC_Decode, 128, 25, 215, 1, // Opcode: tSTRHr +/* 349 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 364 +/* 354 */ MCD_OPC_CheckPredicate, 28, 91, 3, 0, // Skip to: 1218 +/* 359 */ MCD_OPC_Decode, 254, 24, 215, 1, // Opcode: tSTRBr +/* 364 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 379 +/* 369 */ MCD_OPC_CheckPredicate, 28, 76, 3, 0, // Skip to: 1218 +/* 374 */ MCD_OPC_Decode, 226, 24, 215, 1, // Opcode: tLDRSB +/* 379 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 394 +/* 384 */ MCD_OPC_CheckPredicate, 28, 61, 3, 0, // Skip to: 1218 +/* 389 */ MCD_OPC_Decode, 230, 24, 215, 1, // Opcode: tLDRr +/* 394 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 409 +/* 399 */ MCD_OPC_CheckPredicate, 28, 46, 3, 0, // Skip to: 1218 +/* 404 */ MCD_OPC_Decode, 225, 24, 215, 1, // Opcode: tLDRHr +/* 409 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 424 +/* 414 */ MCD_OPC_CheckPredicate, 28, 31, 3, 0, // Skip to: 1218 +/* 419 */ MCD_OPC_Decode, 223, 24, 215, 1, // Opcode: tLDRBr +/* 424 */ MCD_OPC_FilterValue, 7, 21, 3, 0, // Skip to: 1218 +/* 429 */ MCD_OPC_CheckPredicate, 28, 16, 3, 0, // Skip to: 1218 +/* 434 */ MCD_OPC_Decode, 227, 24, 215, 1, // Opcode: tLDRSH +/* 439 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 477 +/* 444 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 447 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 462 +/* 452 */ MCD_OPC_CheckPredicate, 28, 249, 2, 0, // Skip to: 1218 +/* 457 */ MCD_OPC_Decode, 129, 25, 216, 1, // Opcode: tSTRi +/* 462 */ MCD_OPC_FilterValue, 1, 239, 2, 0, // Skip to: 1218 +/* 467 */ MCD_OPC_CheckPredicate, 28, 234, 2, 0, // Skip to: 1218 +/* 472 */ MCD_OPC_Decode, 228, 24, 216, 1, // Opcode: tLDRi +/* 477 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 515 +/* 482 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 485 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 500 +/* 490 */ MCD_OPC_CheckPredicate, 28, 211, 2, 0, // Skip to: 1218 +/* 495 */ MCD_OPC_Decode, 253, 24, 216, 1, // Opcode: tSTRBi +/* 500 */ MCD_OPC_FilterValue, 1, 201, 2, 0, // Skip to: 1218 +/* 505 */ MCD_OPC_CheckPredicate, 28, 196, 2, 0, // Skip to: 1218 +/* 510 */ MCD_OPC_Decode, 222, 24, 216, 1, // Opcode: tLDRBi +/* 515 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 553 +/* 520 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 523 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 538 +/* 528 */ MCD_OPC_CheckPredicate, 28, 173, 2, 0, // Skip to: 1218 +/* 533 */ MCD_OPC_Decode, 255, 24, 216, 1, // Opcode: tSTRHi +/* 538 */ MCD_OPC_FilterValue, 1, 163, 2, 0, // Skip to: 1218 +/* 543 */ MCD_OPC_CheckPredicate, 28, 158, 2, 0, // Skip to: 1218 +/* 548 */ MCD_OPC_Decode, 224, 24, 216, 1, // Opcode: tLDRHi +/* 553 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 591 +/* 558 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 561 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 576 +/* 566 */ MCD_OPC_CheckPredicate, 28, 135, 2, 0, // Skip to: 1218 +/* 571 */ MCD_OPC_Decode, 131, 25, 217, 1, // Opcode: tSTRspi +/* 576 */ MCD_OPC_FilterValue, 1, 125, 2, 0, // Skip to: 1218 +/* 581 */ MCD_OPC_CheckPredicate, 28, 120, 2, 0, // Skip to: 1218 +/* 586 */ MCD_OPC_Decode, 231, 24, 217, 1, // Opcode: tLDRspi +/* 591 */ MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 629 +/* 596 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 599 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 614 +/* 604 */ MCD_OPC_CheckPredicate, 28, 97, 2, 0, // Skip to: 1218 +/* 609 */ MCD_OPC_Decode, 194, 24, 218, 1, // Opcode: tADR +/* 614 */ MCD_OPC_FilterValue, 1, 87, 2, 0, // Skip to: 1218 +/* 619 */ MCD_OPC_CheckPredicate, 28, 82, 2, 0, // Skip to: 1218 +/* 624 */ MCD_OPC_Decode, 190, 24, 218, 1, // Opcode: tADDrSPi +/* 629 */ MCD_OPC_FilterValue, 11, 187, 1, 0, // Skip to: 1077 +/* 634 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 637 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 790 +/* 642 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 645 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 775 +/* 650 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 653 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 714 +/* 658 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 676 +/* 666 */ MCD_OPC_CheckPredicate, 28, 35, 2, 0, // Skip to: 1218 +/* 671 */ MCD_OPC_Decode, 192, 24, 219, 1, // Opcode: tADDspi +/* 676 */ MCD_OPC_FilterValue, 1, 25, 2, 0, // Skip to: 1218 +/* 681 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 684 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 699 +/* 689 */ MCD_OPC_CheckPredicate, 31, 12, 2, 0, // Skip to: 1218 +/* 694 */ MCD_OPC_Decode, 138, 25, 207, 1, // Opcode: tSXTH +/* 699 */ MCD_OPC_FilterValue, 1, 2, 2, 0, // Skip to: 1218 +/* 704 */ MCD_OPC_CheckPredicate, 31, 253, 1, 0, // Skip to: 1218 +/* 709 */ MCD_OPC_Decode, 137, 25, 207, 1, // Opcode: tSXTB +/* 714 */ MCD_OPC_FilterValue, 1, 243, 1, 0, // Skip to: 1218 +/* 719 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 722 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 737 +/* 727 */ MCD_OPC_CheckPredicate, 28, 230, 1, 0, // Skip to: 1218 +/* 732 */ MCD_OPC_Decode, 135, 25, 219, 1, // Opcode: tSUBspi +/* 737 */ MCD_OPC_FilterValue, 1, 220, 1, 0, // Skip to: 1218 +/* 742 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 745 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 760 +/* 750 */ MCD_OPC_CheckPredicate, 31, 207, 1, 0, // Skip to: 1218 +/* 755 */ MCD_OPC_Decode, 143, 25, 207, 1, // Opcode: tUXTH +/* 760 */ MCD_OPC_FilterValue, 1, 197, 1, 0, // Skip to: 1218 +/* 765 */ MCD_OPC_CheckPredicate, 31, 192, 1, 0, // Skip to: 1218 +/* 770 */ MCD_OPC_Decode, 142, 25, 207, 1, // Opcode: tUXTB +/* 775 */ MCD_OPC_FilterValue, 1, 182, 1, 0, // Skip to: 1218 +/* 780 */ MCD_OPC_CheckPredicate, 32, 177, 1, 0, // Skip to: 1218 +/* 785 */ MCD_OPC_Decode, 209, 24, 220, 1, // Opcode: tCBZ +/* 790 */ MCD_OPC_FilterValue, 1, 95, 0, 0, // Skip to: 890 +/* 795 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 798 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 813 +/* 803 */ MCD_OPC_CheckPredicate, 28, 154, 1, 0, // Skip to: 1218 +/* 808 */ MCD_OPC_Decode, 244, 24, 221, 1, // Opcode: tPUSH +/* 813 */ MCD_OPC_FilterValue, 1, 144, 1, 0, // Skip to: 1218 +/* 818 */ MCD_OPC_ExtractField, 5, 4, // Inst{8-5} ... +/* 821 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 839 +/* 826 */ MCD_OPC_CheckPredicate, 33, 131, 1, 0, // Skip to: 1218 +/* 831 */ MCD_OPC_SoftFail, 7, 16, +/* 834 */ MCD_OPC_Decode, 149, 23, 222, 1, // Opcode: t2SETPAN +/* 839 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 868 +/* 844 */ MCD_OPC_CheckPredicate, 34, 113, 1, 0, // Skip to: 1218 +/* 849 */ MCD_OPC_CheckField, 4, 1, 1, 106, 1, 0, // Skip to: 1218 +/* 856 */ MCD_OPC_CheckField, 0, 3, 0, 99, 1, 0, // Skip to: 1218 +/* 863 */ MCD_OPC_Decode, 251, 24, 222, 1, // Opcode: tSETEND +/* 868 */ MCD_OPC_FilterValue, 3, 89, 1, 0, // Skip to: 1218 +/* 873 */ MCD_OPC_CheckPredicate, 28, 84, 1, 0, // Skip to: 1218 +/* 878 */ MCD_OPC_CheckField, 3, 1, 0, 77, 1, 0, // Skip to: 1218 +/* 885 */ MCD_OPC_Decode, 214, 24, 223, 1, // Opcode: tCPS +/* 890 */ MCD_OPC_FilterValue, 2, 114, 0, 0, // Skip to: 1009 +/* 895 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 898 */ MCD_OPC_FilterValue, 0, 91, 0, 0, // Skip to: 994 +/* 903 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 906 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 928 +/* 911 */ MCD_OPC_CheckPredicate, 31, 46, 1, 0, // Skip to: 1218 +/* 916 */ MCD_OPC_CheckField, 9, 1, 1, 39, 1, 0, // Skip to: 1218 +/* 923 */ MCD_OPC_Decode, 245, 24, 207, 1, // Opcode: tREV +/* 928 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 950 +/* 933 */ MCD_OPC_CheckPredicate, 31, 24, 1, 0, // Skip to: 1218 +/* 938 */ MCD_OPC_CheckField, 9, 1, 1, 17, 1, 0, // Skip to: 1218 +/* 945 */ MCD_OPC_Decode, 246, 24, 207, 1, // Opcode: tREV16 +/* 950 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 972 +/* 955 */ MCD_OPC_CheckPredicate, 35, 2, 1, 0, // Skip to: 1218 +/* 960 */ MCD_OPC_CheckField, 9, 1, 1, 251, 0, 0, // Skip to: 1218 +/* 967 */ MCD_OPC_Decode, 217, 24, 224, 1, // Opcode: tHLT +/* 972 */ MCD_OPC_FilterValue, 3, 241, 0, 0, // Skip to: 1218 +/* 977 */ MCD_OPC_CheckPredicate, 31, 236, 0, 0, // Skip to: 1218 +/* 982 */ MCD_OPC_CheckField, 9, 1, 1, 229, 0, 0, // Skip to: 1218 +/* 989 */ MCD_OPC_Decode, 247, 24, 207, 1, // Opcode: tREVSH +/* 994 */ MCD_OPC_FilterValue, 1, 219, 0, 0, // Skip to: 1218 +/* 999 */ MCD_OPC_CheckPredicate, 32, 214, 0, 0, // Skip to: 1218 +/* 1004 */ MCD_OPC_Decode, 208, 24, 220, 1, // Opcode: tCBNZ +/* 1009 */ MCD_OPC_FilterValue, 3, 204, 0, 0, // Skip to: 1218 +/* 1014 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 1017 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1032 +/* 1022 */ MCD_OPC_CheckPredicate, 28, 191, 0, 0, // Skip to: 1218 +/* 1027 */ MCD_OPC_Decode, 243, 24, 225, 1, // Opcode: tPOP +/* 1032 */ MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 1218 +/* 1037 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 1040 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1055 +/* 1045 */ MCD_OPC_CheckPredicate, 28, 168, 0, 0, // Skip to: 1218 +/* 1050 */ MCD_OPC_Decode, 200, 24, 226, 1, // Opcode: tBKPT +/* 1055 */ MCD_OPC_FilterValue, 1, 158, 0, 0, // Skip to: 1218 +/* 1060 */ MCD_OPC_CheckPredicate, 36, 153, 0, 0, // Skip to: 1218 +/* 1065 */ MCD_OPC_CheckField, 0, 4, 0, 146, 0, 0, // Skip to: 1218 +/* 1072 */ MCD_OPC_Decode, 216, 24, 227, 1, // Opcode: tHINT +/* 1077 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 1115 +/* 1082 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 1085 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1100 +/* 1090 */ MCD_OPC_CheckPredicate, 28, 123, 0, 0, // Skip to: 1218 +/* 1095 */ MCD_OPC_Decode, 252, 24, 228, 1, // Opcode: tSTMIA_UPD +/* 1100 */ MCD_OPC_FilterValue, 1, 113, 0, 0, // Skip to: 1218 +/* 1105 */ MCD_OPC_CheckPredicate, 28, 108, 0, 0, // Skip to: 1218 +/* 1110 */ MCD_OPC_Decode, 221, 24, 229, 1, // Opcode: tLDMIA +/* 1115 */ MCD_OPC_FilterValue, 13, 76, 0, 0, // Skip to: 1196 +/* 1120 */ MCD_OPC_ExtractField, 0, 12, // Inst{11-0} ... +/* 1123 */ MCD_OPC_FilterValue, 249, 29, 9, 0, 0, // Skip to: 1138 +/* 1129 */ MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 1153 +/* 1134 */ MCD_OPC_Decode, 144, 25, 51, // Opcode: t__brkdiv0 +/* 1138 */ MCD_OPC_FilterValue, 254, 29, 9, 0, 0, // Skip to: 1153 +/* 1144 */ MCD_OPC_CheckPredicate, 28, 4, 0, 0, // Skip to: 1153 +/* 1149 */ MCD_OPC_Decode, 139, 25, 51, // Opcode: tTRAP +/* 1153 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1156 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1171 +/* 1161 */ MCD_OPC_CheckPredicate, 28, 20, 0, 0, // Skip to: 1186 +/* 1166 */ MCD_OPC_Decode, 141, 25, 226, 1, // Opcode: tUDF +/* 1171 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1186 +/* 1176 */ MCD_OPC_CheckPredicate, 28, 5, 0, 0, // Skip to: 1186 +/* 1181 */ MCD_OPC_Decode, 136, 25, 226, 1, // Opcode: tSVC +/* 1186 */ MCD_OPC_CheckPredicate, 28, 27, 0, 0, // Skip to: 1218 +/* 1191 */ MCD_OPC_Decode, 207, 24, 230, 1, // Opcode: tBcc +/* 1196 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 1218 +/* 1201 */ MCD_OPC_CheckPredicate, 28, 12, 0, 0, // Skip to: 1218 +/* 1206 */ MCD_OPC_CheckField, 11, 1, 0, 5, 0, 0, // Skip to: 1218 +/* 1213 */ MCD_OPC_Decode, 198, 24, 231, 1, // Opcode: tB +/* 1218 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb32[] = { +/* 0 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 3 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 39 +/* 8 */ MCD_OPC_CheckPredicate, 37, 55, 0, 0, // Skip to: 68 +/* 13 */ MCD_OPC_CheckField, 27, 5, 30, 48, 0, 0, // Skip to: 68 +/* 20 */ MCD_OPC_CheckField, 14, 2, 3, 41, 0, 0, // Skip to: 68 +/* 27 */ MCD_OPC_CheckField, 0, 1, 0, 34, 0, 0, // Skip to: 68 +/* 34 */ MCD_OPC_Decode, 203, 24, 232, 1, // Opcode: tBLXi +/* 39 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 68 +/* 44 */ MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 68 +/* 49 */ MCD_OPC_CheckField, 27, 5, 30, 12, 0, 0, // Skip to: 68 +/* 56 */ MCD_OPC_CheckField, 14, 2, 3, 5, 0, 0, // Skip to: 68 +/* 63 */ MCD_OPC_Decode, 201, 24, 233, 1, // Opcode: tBL +/* 68 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb216[] = { +/* 0 */ MCD_OPC_CheckPredicate, 38, 13, 0, 0, // Skip to: 18 +/* 5 */ MCD_OPC_CheckField, 8, 8, 191, 1, 5, 0, 0, // Skip to: 18 +/* 13 */ MCD_OPC_Decode, 250, 21, 234, 1, // Opcode: t2IT +/* 18 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb232[] = { +/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... +/* 3 */ MCD_OPC_FilterValue, 29, 124, 8, 0, // Skip to: 2180 +/* 8 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 11 */ MCD_OPC_FilterValue, 0, 223, 1, 0, // Skip to: 495 +/* 16 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... +/* 19 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 73 +/* 24 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 27 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 50 +/* 32 */ MCD_OPC_CheckPredicate, 39, 210, 31, 0, // Skip to: 8183 +/* 37 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 201, 31, 0, // Skip to: 8183 +/* 46 */ MCD_OPC_Decode, 194, 23, 83, // Opcode: t2SRSDB +/* 50 */ MCD_OPC_FilterValue, 1, 192, 31, 0, // Skip to: 8183 +/* 55 */ MCD_OPC_CheckPredicate, 39, 187, 31, 0, // Skip to: 8183 +/* 60 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 178, 31, 0, // Skip to: 8183 +/* 69 */ MCD_OPC_Decode, 130, 23, 81, // Opcode: t2RFEDB +/* 73 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 125 +/* 78 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 81 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 110 +/* 86 */ MCD_OPC_CheckPredicate, 38, 156, 31, 0, // Skip to: 8183 +/* 91 */ MCD_OPC_CheckField, 15, 1, 0, 149, 31, 0, // Skip to: 8183 +/* 98 */ MCD_OPC_CheckField, 13, 1, 0, 142, 31, 0, // Skip to: 8183 +/* 105 */ MCD_OPC_Decode, 228, 23, 235, 1, // Opcode: t2STMIA +/* 110 */ MCD_OPC_FilterValue, 1, 132, 31, 0, // Skip to: 8183 +/* 115 */ MCD_OPC_CheckPredicate, 38, 127, 31, 0, // Skip to: 8183 +/* 120 */ MCD_OPC_Decode, 150, 22, 236, 1, // Opcode: t2LDMIA +/* 125 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 177 +/* 130 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 133 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 162 +/* 138 */ MCD_OPC_CheckPredicate, 38, 104, 31, 0, // Skip to: 8183 +/* 143 */ MCD_OPC_CheckField, 15, 1, 0, 97, 31, 0, // Skip to: 8183 +/* 150 */ MCD_OPC_CheckField, 13, 1, 0, 90, 31, 0, // Skip to: 8183 +/* 157 */ MCD_OPC_Decode, 226, 23, 235, 1, // Opcode: t2STMDB +/* 162 */ MCD_OPC_FilterValue, 1, 80, 31, 0, // Skip to: 8183 +/* 167 */ MCD_OPC_CheckPredicate, 38, 75, 31, 0, // Skip to: 8183 +/* 172 */ MCD_OPC_Decode, 148, 22, 236, 1, // Opcode: t2LDMDB +/* 177 */ MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 231 +/* 182 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 185 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 208 +/* 190 */ MCD_OPC_CheckPredicate, 39, 52, 31, 0, // Skip to: 8183 +/* 195 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 43, 31, 0, // Skip to: 8183 +/* 204 */ MCD_OPC_Decode, 196, 23, 83, // Opcode: t2SRSIA +/* 208 */ MCD_OPC_FilterValue, 1, 34, 31, 0, // Skip to: 8183 +/* 213 */ MCD_OPC_CheckPredicate, 39, 29, 31, 0, // Skip to: 8183 +/* 218 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 20, 31, 0, // Skip to: 8183 +/* 227 */ MCD_OPC_Decode, 132, 23, 81, // Opcode: t2RFEIA +/* 231 */ MCD_OPC_FilterValue, 4, 83, 0, 0, // Skip to: 319 +/* 236 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 261 +/* 241 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 261 +/* 248 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 261 +/* 256 */ MCD_OPC_Decode, 145, 24, 237, 1, // Opcode: t2TSTrr +/* 261 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 285 +/* 266 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 285 +/* 273 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 285 +/* 280 */ MCD_OPC_Decode, 146, 24, 238, 1, // Opcode: t2TSTrs +/* 285 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 309 +/* 290 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 309 +/* 297 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 309 +/* 304 */ MCD_OPC_Decode, 207, 21, 239, 1, // Opcode: t2ANDrr +/* 309 */ MCD_OPC_CheckPredicate, 38, 189, 30, 0, // Skip to: 8183 +/* 314 */ MCD_OPC_Decode, 208, 21, 240, 1, // Opcode: t2ANDrs +/* 319 */ MCD_OPC_FilterValue, 5, 83, 0, 0, // Skip to: 407 +/* 324 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 349 +/* 329 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 349 +/* 336 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 349 +/* 344 */ MCD_OPC_Decode, 141, 24, 237, 1, // Opcode: t2TEQrr +/* 349 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 373 +/* 354 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 373 +/* 361 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 373 +/* 368 */ MCD_OPC_Decode, 142, 24, 238, 1, // Opcode: t2TEQrs +/* 373 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 397 +/* 378 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 397 +/* 385 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 397 +/* 392 */ MCD_OPC_Decode, 245, 21, 239, 1, // Opcode: t2EORrr +/* 397 */ MCD_OPC_CheckPredicate, 38, 101, 30, 0, // Skip to: 8183 +/* 402 */ MCD_OPC_Decode, 246, 21, 240, 1, // Opcode: t2EORrs +/* 407 */ MCD_OPC_FilterValue, 6, 91, 30, 0, // Skip to: 8183 +/* 412 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 437 +/* 417 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 437 +/* 424 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 437 +/* 432 */ MCD_OPC_Decode, 224, 21, 237, 1, // Opcode: t2CMNzrr +/* 437 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 461 +/* 442 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 461 +/* 449 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 461 +/* 456 */ MCD_OPC_Decode, 225, 21, 238, 1, // Opcode: t2CMNzrs +/* 461 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 485 +/* 466 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 485 +/* 473 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 485 +/* 480 */ MCD_OPC_Decode, 203, 21, 241, 1, // Opcode: t2ADDrr +/* 485 */ MCD_OPC_CheckPredicate, 38, 13, 30, 0, // Skip to: 8183 +/* 490 */ MCD_OPC_Decode, 204, 21, 242, 1, // Opcode: t2ADDrs +/* 495 */ MCD_OPC_FilterValue, 1, 86, 1, 0, // Skip to: 842 +/* 500 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... +/* 503 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 557 +/* 508 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 511 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 534 +/* 516 */ MCD_OPC_CheckPredicate, 39, 238, 29, 0, // Skip to: 8183 +/* 521 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 229, 29, 0, // Skip to: 8183 +/* 530 */ MCD_OPC_Decode, 195, 23, 83, // Opcode: t2SRSDB_UPD +/* 534 */ MCD_OPC_FilterValue, 1, 220, 29, 0, // Skip to: 8183 +/* 539 */ MCD_OPC_CheckPredicate, 39, 215, 29, 0, // Skip to: 8183 +/* 544 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 206, 29, 0, // Skip to: 8183 +/* 553 */ MCD_OPC_Decode, 131, 23, 81, // Opcode: t2RFEDBW +/* 557 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 609 +/* 562 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 565 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 594 +/* 570 */ MCD_OPC_CheckPredicate, 38, 184, 29, 0, // Skip to: 8183 +/* 575 */ MCD_OPC_CheckField, 15, 1, 0, 177, 29, 0, // Skip to: 8183 +/* 582 */ MCD_OPC_CheckField, 13, 1, 0, 170, 29, 0, // Skip to: 8183 +/* 589 */ MCD_OPC_Decode, 229, 23, 243, 1, // Opcode: t2STMIA_UPD +/* 594 */ MCD_OPC_FilterValue, 1, 160, 29, 0, // Skip to: 8183 +/* 599 */ MCD_OPC_CheckPredicate, 38, 155, 29, 0, // Skip to: 8183 +/* 604 */ MCD_OPC_Decode, 151, 22, 244, 1, // Opcode: t2LDMIA_UPD +/* 609 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 661 +/* 614 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 617 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 646 +/* 622 */ MCD_OPC_CheckPredicate, 38, 132, 29, 0, // Skip to: 8183 +/* 627 */ MCD_OPC_CheckField, 15, 1, 0, 125, 29, 0, // Skip to: 8183 +/* 634 */ MCD_OPC_CheckField, 13, 1, 0, 118, 29, 0, // Skip to: 8183 +/* 641 */ MCD_OPC_Decode, 227, 23, 243, 1, // Opcode: t2STMDB_UPD +/* 646 */ MCD_OPC_FilterValue, 1, 108, 29, 0, // Skip to: 8183 +/* 651 */ MCD_OPC_CheckPredicate, 38, 103, 29, 0, // Skip to: 8183 +/* 656 */ MCD_OPC_Decode, 149, 22, 244, 1, // Opcode: t2LDMDB_UPD +/* 661 */ MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 715 +/* 666 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 669 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 692 +/* 674 */ MCD_OPC_CheckPredicate, 39, 80, 29, 0, // Skip to: 8183 +/* 679 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 71, 29, 0, // Skip to: 8183 +/* 688 */ MCD_OPC_Decode, 197, 23, 83, // Opcode: t2SRSIA_UPD +/* 692 */ MCD_OPC_FilterValue, 1, 62, 29, 0, // Skip to: 8183 +/* 697 */ MCD_OPC_CheckPredicate, 39, 57, 29, 0, // Skip to: 8183 +/* 702 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 48, 29, 0, // Skip to: 8183 +/* 711 */ MCD_OPC_Decode, 133, 23, 81, // Opcode: t2RFEIAW +/* 715 */ MCD_OPC_FilterValue, 4, 34, 0, 0, // Skip to: 754 +/* 720 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 744 +/* 725 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 744 +/* 732 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 744 +/* 739 */ MCD_OPC_Decode, 215, 21, 239, 1, // Opcode: t2BICrr +/* 744 */ MCD_OPC_CheckPredicate, 38, 10, 29, 0, // Skip to: 8183 +/* 749 */ MCD_OPC_Decode, 216, 21, 240, 1, // Opcode: t2BICrs +/* 754 */ MCD_OPC_FilterValue, 7, 0, 29, 0, // Skip to: 8183 +/* 759 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 784 +/* 764 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 784 +/* 771 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 784 +/* 779 */ MCD_OPC_Decode, 227, 21, 237, 1, // Opcode: t2CMPrr +/* 784 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 808 +/* 789 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 808 +/* 796 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 808 +/* 803 */ MCD_OPC_Decode, 228, 21, 238, 1, // Opcode: t2CMPrs +/* 808 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 832 +/* 813 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 832 +/* 820 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 832 +/* 827 */ MCD_OPC_Decode, 130, 24, 241, 1, // Opcode: t2SUBrr +/* 832 */ MCD_OPC_CheckPredicate, 38, 178, 28, 0, // Skip to: 8183 +/* 837 */ MCD_OPC_Decode, 131, 24, 242, 1, // Opcode: t2SUBrs +/* 842 */ MCD_OPC_FilterValue, 2, 70, 4, 0, // Skip to: 1941 +/* 847 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... +/* 850 */ MCD_OPC_FilterValue, 0, 212, 2, 0, // Skip to: 1579 +/* 855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 858 */ MCD_OPC_FilterValue, 0, 100, 1, 0, // Skip to: 1219 +/* 863 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 866 */ MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 984 +/* 871 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 874 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 899 +/* 879 */ MCD_OPC_CheckPredicate, 29, 90, 0, 0, // Skip to: 974 +/* 884 */ MCD_OPC_CheckField, 12, 4, 15, 83, 0, 0, // Skip to: 974 +/* 891 */ MCD_OPC_SoftFail, 63, 0, +/* 894 */ MCD_OPC_Decode, 147, 24, 245, 1, // Opcode: t2TT +/* 899 */ MCD_OPC_FilterValue, 1, 20, 0, 0, // Skip to: 924 +/* 904 */ MCD_OPC_CheckPredicate, 29, 65, 0, 0, // Skip to: 974 +/* 909 */ MCD_OPC_CheckField, 12, 4, 15, 58, 0, 0, // Skip to: 974 +/* 916 */ MCD_OPC_SoftFail, 63, 0, +/* 919 */ MCD_OPC_Decode, 150, 24, 245, 1, // Opcode: t2TTT +/* 924 */ MCD_OPC_FilterValue, 2, 20, 0, 0, // Skip to: 949 +/* 929 */ MCD_OPC_CheckPredicate, 29, 40, 0, 0, // Skip to: 974 +/* 934 */ MCD_OPC_CheckField, 12, 4, 15, 33, 0, 0, // Skip to: 974 +/* 941 */ MCD_OPC_SoftFail, 63, 0, +/* 944 */ MCD_OPC_Decode, 148, 24, 245, 1, // Opcode: t2TTA +/* 949 */ MCD_OPC_FilterValue, 3, 20, 0, 0, // Skip to: 974 +/* 954 */ MCD_OPC_CheckPredicate, 29, 15, 0, 0, // Skip to: 974 +/* 959 */ MCD_OPC_CheckField, 12, 4, 15, 8, 0, 0, // Skip to: 974 +/* 966 */ MCD_OPC_SoftFail, 63, 0, +/* 969 */ MCD_OPC_Decode, 149, 24, 245, 1, // Opcode: t2TTAT +/* 974 */ MCD_OPC_CheckPredicate, 32, 36, 28, 0, // Skip to: 8183 +/* 979 */ MCD_OPC_Decode, 239, 23, 246, 1, // Opcode: t2STREX +/* 984 */ MCD_OPC_FilterValue, 1, 26, 28, 0, // Skip to: 8183 +/* 989 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 992 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1014 +/* 997 */ MCD_OPC_CheckPredicate, 32, 13, 28, 0, // Skip to: 8183 +/* 1002 */ MCD_OPC_CheckField, 8, 4, 15, 6, 28, 0, // Skip to: 8183 +/* 1009 */ MCD_OPC_Decode, 240, 23, 247, 1, // Opcode: t2STREXB +/* 1014 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1036 +/* 1019 */ MCD_OPC_CheckPredicate, 32, 247, 27, 0, // Skip to: 8183 +/* 1024 */ MCD_OPC_CheckField, 8, 4, 15, 240, 27, 0, // Skip to: 8183 +/* 1031 */ MCD_OPC_Decode, 242, 23, 247, 1, // Opcode: t2STREXH +/* 1036 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1051 +/* 1041 */ MCD_OPC_CheckPredicate, 39, 225, 27, 0, // Skip to: 8183 +/* 1046 */ MCD_OPC_Decode, 241, 23, 248, 1, // Opcode: t2STREXD +/* 1051 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1080 +/* 1056 */ MCD_OPC_CheckPredicate, 40, 210, 27, 0, // Skip to: 8183 +/* 1061 */ MCD_OPC_CheckField, 8, 4, 15, 203, 27, 0, // Skip to: 8183 +/* 1068 */ MCD_OPC_CheckField, 0, 4, 15, 196, 27, 0, // Skip to: 8183 +/* 1075 */ MCD_OPC_Decode, 220, 23, 249, 1, // Opcode: t2STLB +/* 1080 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1109 +/* 1085 */ MCD_OPC_CheckPredicate, 40, 181, 27, 0, // Skip to: 8183 +/* 1090 */ MCD_OPC_CheckField, 8, 4, 15, 174, 27, 0, // Skip to: 8183 +/* 1097 */ MCD_OPC_CheckField, 0, 4, 15, 167, 27, 0, // Skip to: 8183 +/* 1104 */ MCD_OPC_Decode, 225, 23, 249, 1, // Opcode: t2STLH +/* 1109 */ MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 1138 +/* 1114 */ MCD_OPC_CheckPredicate, 40, 152, 27, 0, // Skip to: 8183 +/* 1119 */ MCD_OPC_CheckField, 8, 4, 15, 145, 27, 0, // Skip to: 8183 +/* 1126 */ MCD_OPC_CheckField, 0, 4, 15, 138, 27, 0, // Skip to: 8183 +/* 1133 */ MCD_OPC_Decode, 219, 23, 249, 1, // Opcode: t2STL +/* 1138 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1160 +/* 1143 */ MCD_OPC_CheckPredicate, 41, 123, 27, 0, // Skip to: 8183 +/* 1148 */ MCD_OPC_CheckField, 8, 4, 15, 116, 27, 0, // Skip to: 8183 +/* 1155 */ MCD_OPC_Decode, 222, 23, 247, 1, // Opcode: t2STLEXB +/* 1160 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 1182 +/* 1165 */ MCD_OPC_CheckPredicate, 41, 101, 27, 0, // Skip to: 8183 +/* 1170 */ MCD_OPC_CheckField, 8, 4, 15, 94, 27, 0, // Skip to: 8183 +/* 1177 */ MCD_OPC_Decode, 224, 23, 247, 1, // Opcode: t2STLEXH +/* 1182 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 1204 +/* 1187 */ MCD_OPC_CheckPredicate, 41, 79, 27, 0, // Skip to: 8183 +/* 1192 */ MCD_OPC_CheckField, 8, 4, 15, 72, 27, 0, // Skip to: 8183 +/* 1199 */ MCD_OPC_Decode, 221, 23, 247, 1, // Opcode: t2STLEX +/* 1204 */ MCD_OPC_FilterValue, 15, 62, 27, 0, // Skip to: 8183 +/* 1209 */ MCD_OPC_CheckPredicate, 42, 57, 27, 0, // Skip to: 8183 +/* 1214 */ MCD_OPC_Decode, 223, 23, 248, 1, // Opcode: t2STLEXD +/* 1219 */ MCD_OPC_FilterValue, 1, 47, 27, 0, // Skip to: 8183 +/* 1224 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 1227 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1249 +/* 1232 */ MCD_OPC_CheckPredicate, 32, 34, 27, 0, // Skip to: 8183 +/* 1237 */ MCD_OPC_CheckField, 8, 4, 15, 27, 27, 0, // Skip to: 8183 +/* 1244 */ MCD_OPC_Decode, 162, 22, 250, 1, // Opcode: t2LDREX +/* 1249 */ MCD_OPC_FilterValue, 1, 17, 27, 0, // Skip to: 8183 +/* 1254 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 1257 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 1280 +/* 1262 */ MCD_OPC_CheckPredicate, 38, 4, 27, 0, // Skip to: 8183 +/* 1267 */ MCD_OPC_CheckField, 8, 8, 240, 1, 252, 26, 0, // Skip to: 8183 +/* 1275 */ MCD_OPC_Decode, 138, 24, 251, 1, // Opcode: t2TBB +/* 1280 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 1303 +/* 1285 */ MCD_OPC_CheckPredicate, 38, 237, 26, 0, // Skip to: 8183 +/* 1290 */ MCD_OPC_CheckField, 8, 8, 240, 1, 229, 26, 0, // Skip to: 8183 +/* 1298 */ MCD_OPC_Decode, 139, 24, 251, 1, // Opcode: t2TBH +/* 1303 */ MCD_OPC_FilterValue, 4, 24, 0, 0, // Skip to: 1332 +/* 1308 */ MCD_OPC_CheckPredicate, 32, 214, 26, 0, // Skip to: 8183 +/* 1313 */ MCD_OPC_CheckField, 8, 4, 15, 207, 26, 0, // Skip to: 8183 +/* 1320 */ MCD_OPC_CheckField, 0, 4, 15, 200, 26, 0, // Skip to: 8183 +/* 1327 */ MCD_OPC_Decode, 163, 22, 249, 1, // Opcode: t2LDREXB +/* 1332 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 1361 +/* 1337 */ MCD_OPC_CheckPredicate, 32, 185, 26, 0, // Skip to: 8183 +/* 1342 */ MCD_OPC_CheckField, 8, 4, 15, 178, 26, 0, // Skip to: 8183 +/* 1349 */ MCD_OPC_CheckField, 0, 4, 15, 171, 26, 0, // Skip to: 8183 +/* 1356 */ MCD_OPC_Decode, 165, 22, 249, 1, // Opcode: t2LDREXH +/* 1361 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1383 +/* 1366 */ MCD_OPC_CheckPredicate, 39, 156, 26, 0, // Skip to: 8183 +/* 1371 */ MCD_OPC_CheckField, 0, 4, 15, 149, 26, 0, // Skip to: 8183 +/* 1378 */ MCD_OPC_Decode, 164, 22, 252, 1, // Opcode: t2LDREXD +/* 1383 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1412 +/* 1388 */ MCD_OPC_CheckPredicate, 40, 134, 26, 0, // Skip to: 8183 +/* 1393 */ MCD_OPC_CheckField, 8, 4, 15, 127, 26, 0, // Skip to: 8183 +/* 1400 */ MCD_OPC_CheckField, 0, 4, 15, 120, 26, 0, // Skip to: 8183 +/* 1407 */ MCD_OPC_Decode, 254, 21, 249, 1, // Opcode: t2LDAB +/* 1412 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1441 +/* 1417 */ MCD_OPC_CheckPredicate, 40, 105, 26, 0, // Skip to: 8183 +/* 1422 */ MCD_OPC_CheckField, 8, 4, 15, 98, 26, 0, // Skip to: 8183 +/* 1429 */ MCD_OPC_CheckField, 0, 4, 15, 91, 26, 0, // Skip to: 8183 +/* 1436 */ MCD_OPC_Decode, 131, 22, 249, 1, // Opcode: t2LDAH +/* 1441 */ MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 1470 +/* 1446 */ MCD_OPC_CheckPredicate, 40, 76, 26, 0, // Skip to: 8183 +/* 1451 */ MCD_OPC_CheckField, 8, 4, 15, 69, 26, 0, // Skip to: 8183 +/* 1458 */ MCD_OPC_CheckField, 0, 4, 15, 62, 26, 0, // Skip to: 8183 +/* 1465 */ MCD_OPC_Decode, 253, 21, 249, 1, // Opcode: t2LDA +/* 1470 */ MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 1499 +/* 1475 */ MCD_OPC_CheckPredicate, 41, 47, 26, 0, // Skip to: 8183 +/* 1480 */ MCD_OPC_CheckField, 8, 4, 15, 40, 26, 0, // Skip to: 8183 +/* 1487 */ MCD_OPC_CheckField, 0, 4, 15, 33, 26, 0, // Skip to: 8183 +/* 1494 */ MCD_OPC_Decode, 128, 22, 249, 1, // Opcode: t2LDAEXB +/* 1499 */ MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 1528 +/* 1504 */ MCD_OPC_CheckPredicate, 41, 18, 26, 0, // Skip to: 8183 +/* 1509 */ MCD_OPC_CheckField, 8, 4, 15, 11, 26, 0, // Skip to: 8183 +/* 1516 */ MCD_OPC_CheckField, 0, 4, 15, 4, 26, 0, // Skip to: 8183 +/* 1523 */ MCD_OPC_Decode, 130, 22, 249, 1, // Opcode: t2LDAEXH +/* 1528 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 1557 +/* 1533 */ MCD_OPC_CheckPredicate, 41, 245, 25, 0, // Skip to: 8183 +/* 1538 */ MCD_OPC_CheckField, 8, 4, 15, 238, 25, 0, // Skip to: 8183 +/* 1545 */ MCD_OPC_CheckField, 0, 4, 15, 231, 25, 0, // Skip to: 8183 +/* 1552 */ MCD_OPC_Decode, 255, 21, 249, 1, // Opcode: t2LDAEX +/* 1557 */ MCD_OPC_FilterValue, 15, 221, 25, 0, // Skip to: 8183 +/* 1562 */ MCD_OPC_CheckPredicate, 42, 216, 25, 0, // Skip to: 8183 +/* 1567 */ MCD_OPC_CheckField, 0, 4, 15, 209, 25, 0, // Skip to: 8183 +/* 1574 */ MCD_OPC_Decode, 129, 22, 252, 1, // Opcode: t2LDAEXD +/* 1579 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 1617 +/* 1584 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1587 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1602 +/* 1592 */ MCD_OPC_CheckPredicate, 38, 186, 25, 0, // Skip to: 8183 +/* 1597 */ MCD_OPC_Decode, 238, 23, 253, 1, // Opcode: t2STRDi8 +/* 1602 */ MCD_OPC_FilterValue, 1, 176, 25, 0, // Skip to: 8183 +/* 1607 */ MCD_OPC_CheckPredicate, 38, 171, 25, 0, // Skip to: 8183 +/* 1612 */ MCD_OPC_Decode, 161, 22, 253, 1, // Opcode: t2LDRDi8 +/* 1617 */ MCD_OPC_FilterValue, 2, 233, 0, 0, // Skip to: 1855 +/* 1622 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 1625 */ MCD_OPC_FilterValue, 0, 173, 0, 0, // Skip to: 1803 +/* 1630 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 1633 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 1673 +/* 1638 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 1641 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 1702 +/* 1646 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 1663 +/* 1651 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1663 +/* 1658 */ MCD_OPC_Decode, 207, 22, 254, 1, // Opcode: t2MOVr +/* 1663 */ MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 1702 +/* 1668 */ MCD_OPC_Decode, 229, 22, 239, 1, // Opcode: t2ORRrr +/* 1673 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 1702 +/* 1678 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1702 +/* 1683 */ MCD_OPC_CheckField, 16, 4, 15, 12, 0, 0, // Skip to: 1702 +/* 1690 */ MCD_OPC_CheckField, 12, 3, 0, 5, 0, 0, // Skip to: 1702 +/* 1697 */ MCD_OPC_Decode, 136, 23, 255, 1, // Opcode: t2RRX +/* 1702 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 1705 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1727 +/* 1710 */ MCD_OPC_CheckPredicate, 38, 78, 0, 0, // Skip to: 1793 +/* 1715 */ MCD_OPC_CheckField, 16, 4, 15, 71, 0, 0, // Skip to: 1793 +/* 1722 */ MCD_OPC_Decode, 194, 22, 128, 2, // Opcode: t2LSLri +/* 1727 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1749 +/* 1732 */ MCD_OPC_CheckPredicate, 38, 56, 0, 0, // Skip to: 1793 +/* 1737 */ MCD_OPC_CheckField, 16, 4, 15, 49, 0, 0, // Skip to: 1793 +/* 1744 */ MCD_OPC_Decode, 196, 22, 128, 2, // Opcode: t2LSRri +/* 1749 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1771 +/* 1754 */ MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 1793 +/* 1759 */ MCD_OPC_CheckField, 16, 4, 15, 27, 0, 0, // Skip to: 1793 +/* 1766 */ MCD_OPC_Decode, 209, 21, 128, 2, // Opcode: t2ASRri +/* 1771 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1793 +/* 1776 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 1793 +/* 1781 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1793 +/* 1788 */ MCD_OPC_Decode, 134, 23, 128, 2, // Opcode: t2RORri +/* 1793 */ MCD_OPC_CheckPredicate, 38, 241, 24, 0, // Skip to: 8183 +/* 1798 */ MCD_OPC_Decode, 230, 22, 240, 1, // Opcode: t2ORRrs +/* 1803 */ MCD_OPC_FilterValue, 1, 231, 24, 0, // Skip to: 8183 +/* 1808 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 1811 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1833 +/* 1816 */ MCD_OPC_CheckPredicate, 43, 218, 24, 0, // Skip to: 8183 +/* 1821 */ MCD_OPC_CheckField, 20, 1, 0, 211, 24, 0, // Skip to: 8183 +/* 1828 */ MCD_OPC_Decode, 231, 22, 129, 2, // Opcode: t2PKHBT +/* 1833 */ MCD_OPC_FilterValue, 2, 201, 24, 0, // Skip to: 8183 +/* 1838 */ MCD_OPC_CheckPredicate, 43, 196, 24, 0, // Skip to: 8183 +/* 1843 */ MCD_OPC_CheckField, 20, 1, 0, 189, 24, 0, // Skip to: 8183 +/* 1850 */ MCD_OPC_Decode, 232, 22, 129, 2, // Opcode: t2PKHTB +/* 1855 */ MCD_OPC_FilterValue, 3, 179, 24, 0, // Skip to: 8183 +/* 1860 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 1863 */ MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 1902 +/* 1868 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1892 +/* 1873 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 1892 +/* 1880 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 1892 +/* 1887 */ MCD_OPC_Decode, 199, 21, 239, 1, // Opcode: t2ADCrr +/* 1892 */ MCD_OPC_CheckPredicate, 38, 142, 24, 0, // Skip to: 8183 +/* 1897 */ MCD_OPC_Decode, 200, 21, 240, 1, // Opcode: t2ADCrs +/* 1902 */ MCD_OPC_FilterValue, 1, 132, 24, 0, // Skip to: 8183 +/* 1907 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1931 +/* 1912 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 1931 +/* 1919 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 1931 +/* 1926 */ MCD_OPC_Decode, 138, 23, 239, 1, // Opcode: t2RSBrr +/* 1931 */ MCD_OPC_CheckPredicate, 38, 103, 24, 0, // Skip to: 8183 +/* 1936 */ MCD_OPC_Decode, 139, 23, 240, 1, // Opcode: t2RSBrs +/* 1941 */ MCD_OPC_FilterValue, 3, 93, 24, 0, // Skip to: 8183 +/* 1946 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... +/* 1949 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1987 +/* 1954 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1957 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1972 +/* 1962 */ MCD_OPC_CheckPredicate, 38, 72, 24, 0, // Skip to: 8183 +/* 1967 */ MCD_OPC_Decode, 236, 23, 130, 2, // Opcode: t2STRD_POST +/* 1972 */ MCD_OPC_FilterValue, 1, 62, 24, 0, // Skip to: 8183 +/* 1977 */ MCD_OPC_CheckPredicate, 38, 57, 24, 0, // Skip to: 8183 +/* 1982 */ MCD_OPC_Decode, 159, 22, 131, 2, // Opcode: t2LDRD_POST +/* 1987 */ MCD_OPC_FilterValue, 1, 58, 0, 0, // Skip to: 2050 +/* 1992 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 1995 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2010 +/* 2000 */ MCD_OPC_CheckPredicate, 38, 34, 24, 0, // Skip to: 8183 +/* 2005 */ MCD_OPC_Decode, 237, 23, 132, 2, // Opcode: t2STRD_PRE +/* 2010 */ MCD_OPC_FilterValue, 1, 24, 24, 0, // Skip to: 8183 +/* 2015 */ MCD_OPC_CheckPredicate, 44, 20, 0, 0, // Skip to: 2040 +/* 2020 */ MCD_OPC_CheckField, 23, 1, 0, 13, 0, 0, // Skip to: 2040 +/* 2027 */ MCD_OPC_CheckField, 0, 20, 255, 210, 63, 4, 0, 0, // Skip to: 2040 +/* 2036 */ MCD_OPC_Decode, 150, 23, 51, // Opcode: t2SG +/* 2040 */ MCD_OPC_CheckPredicate, 38, 250, 23, 0, // Skip to: 8183 +/* 2045 */ MCD_OPC_Decode, 160, 22, 133, 2, // Opcode: t2LDRD_PRE +/* 2050 */ MCD_OPC_FilterValue, 2, 78, 0, 0, // Skip to: 2133 +/* 2055 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 2058 */ MCD_OPC_FilterValue, 0, 232, 23, 0, // Skip to: 8183 +/* 2063 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 2066 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2106 +/* 2071 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... +/* 2074 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2106 +/* 2079 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2096 +/* 2084 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2096 +/* 2091 */ MCD_OPC_Decode, 223, 22, 255, 1, // Opcode: t2MVNr +/* 2096 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 2106 +/* 2101 */ MCD_OPC_Decode, 226, 22, 239, 1, // Opcode: t2ORNrr +/* 2106 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2123 +/* 2111 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2123 +/* 2118 */ MCD_OPC_Decode, 224, 22, 134, 2, // Opcode: t2MVNs +/* 2123 */ MCD_OPC_CheckPredicate, 38, 167, 23, 0, // Skip to: 8183 +/* 2128 */ MCD_OPC_Decode, 227, 22, 240, 1, // Opcode: t2ORNrs +/* 2133 */ MCD_OPC_FilterValue, 3, 157, 23, 0, // Skip to: 8183 +/* 2138 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 2141 */ MCD_OPC_FilterValue, 0, 149, 23, 0, // Skip to: 8183 +/* 2146 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2170 +/* 2151 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 2170 +/* 2158 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 2170 +/* 2165 */ MCD_OPC_Decode, 144, 23, 239, 1, // Opcode: t2SBCrr +/* 2170 */ MCD_OPC_CheckPredicate, 38, 120, 23, 0, // Skip to: 8183 +/* 2175 */ MCD_OPC_Decode, 145, 23, 240, 1, // Opcode: t2SBCrs +/* 2180 */ MCD_OPC_FilterValue, 30, 153, 5, 0, // Skip to: 3618 +/* 2185 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 2188 */ MCD_OPC_FilterValue, 0, 179, 2, 0, // Skip to: 2884 +/* 2193 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 2196 */ MCD_OPC_FilterValue, 0, 160, 0, 0, // Skip to: 2361 +/* 2201 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 2204 */ MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 2243 +/* 2209 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2233 +/* 2214 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2233 +/* 2221 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2233 +/* 2228 */ MCD_OPC_Decode, 144, 24, 135, 2, // Opcode: t2TSTri +/* 2233 */ MCD_OPC_CheckPredicate, 38, 57, 23, 0, // Skip to: 8183 +/* 2238 */ MCD_OPC_Decode, 206, 21, 136, 2, // Opcode: t2ANDri +/* 2243 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2258 +/* 2248 */ MCD_OPC_CheckPredicate, 38, 42, 23, 0, // Skip to: 8183 +/* 2253 */ MCD_OPC_Decode, 214, 21, 136, 2, // Opcode: t2BICri +/* 2258 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 2290 +/* 2263 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2280 +/* 2268 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2280 +/* 2275 */ MCD_OPC_Decode, 205, 22, 137, 2, // Opcode: t2MOVi +/* 2280 */ MCD_OPC_CheckPredicate, 38, 10, 23, 0, // Skip to: 8183 +/* 2285 */ MCD_OPC_Decode, 228, 22, 136, 2, // Opcode: t2ORRri +/* 2290 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 2322 +/* 2295 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2312 +/* 2300 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2312 +/* 2307 */ MCD_OPC_Decode, 222, 22, 137, 2, // Opcode: t2MVNi +/* 2312 */ MCD_OPC_CheckPredicate, 38, 234, 22, 0, // Skip to: 8183 +/* 2317 */ MCD_OPC_Decode, 225, 22, 136, 2, // Opcode: t2ORNri +/* 2322 */ MCD_OPC_FilterValue, 4, 224, 22, 0, // Skip to: 8183 +/* 2327 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2351 +/* 2332 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2351 +/* 2339 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2351 +/* 2346 */ MCD_OPC_Decode, 140, 24, 135, 2, // Opcode: t2TEQri +/* 2351 */ MCD_OPC_CheckPredicate, 38, 195, 22, 0, // Skip to: 8183 +/* 2356 */ MCD_OPC_Decode, 244, 21, 136, 2, // Opcode: t2EORri +/* 2361 */ MCD_OPC_FilterValue, 1, 126, 0, 0, // Skip to: 2492 +/* 2366 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 2369 */ MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 2408 +/* 2374 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2398 +/* 2379 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2398 +/* 2386 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2398 +/* 2393 */ MCD_OPC_Decode, 223, 21, 135, 2, // Opcode: t2CMNri +/* 2398 */ MCD_OPC_CheckPredicate, 38, 148, 22, 0, // Skip to: 8183 +/* 2403 */ MCD_OPC_Decode, 201, 21, 138, 2, // Opcode: t2ADDri +/* 2408 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2423 +/* 2413 */ MCD_OPC_CheckPredicate, 38, 133, 22, 0, // Skip to: 8183 +/* 2418 */ MCD_OPC_Decode, 198, 21, 136, 2, // Opcode: t2ADCri +/* 2423 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2438 +/* 2428 */ MCD_OPC_CheckPredicate, 38, 118, 22, 0, // Skip to: 8183 +/* 2433 */ MCD_OPC_Decode, 143, 23, 136, 2, // Opcode: t2SBCri +/* 2438 */ MCD_OPC_FilterValue, 5, 34, 0, 0, // Skip to: 2477 +/* 2443 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2467 +/* 2448 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2467 +/* 2455 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2467 +/* 2462 */ MCD_OPC_Decode, 226, 21, 135, 2, // Opcode: t2CMPri +/* 2467 */ MCD_OPC_CheckPredicate, 38, 79, 22, 0, // Skip to: 8183 +/* 2472 */ MCD_OPC_Decode, 128, 24, 138, 2, // Opcode: t2SUBri +/* 2477 */ MCD_OPC_FilterValue, 6, 69, 22, 0, // Skip to: 8183 +/* 2482 */ MCD_OPC_CheckPredicate, 38, 64, 22, 0, // Skip to: 8183 +/* 2487 */ MCD_OPC_Decode, 137, 23, 136, 2, // Opcode: t2RSBri +/* 2492 */ MCD_OPC_FilterValue, 2, 132, 0, 0, // Skip to: 2629 +/* 2497 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2500 */ MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 2577 +/* 2505 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 2508 */ MCD_OPC_FilterValue, 0, 38, 22, 0, // Skip to: 8183 +/* 2513 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 2516 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2538 +/* 2521 */ MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 2560 +/* 2526 */ MCD_OPC_CheckField, 23, 1, 0, 27, 0, 0, // Skip to: 2560 +/* 2533 */ MCD_OPC_Decode, 202, 21, 139, 2, // Opcode: t2ADDri12 +/* 2538 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2560 +/* 2543 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2560 +/* 2548 */ MCD_OPC_CheckField, 23, 1, 1, 5, 0, 0, // Skip to: 2560 +/* 2555 */ MCD_OPC_Decode, 129, 24, 139, 2, // Opcode: t2SUBri12 +/* 2560 */ MCD_OPC_CheckPredicate, 38, 242, 21, 0, // Skip to: 8183 +/* 2565 */ MCD_OPC_CheckField, 16, 4, 15, 235, 21, 0, // Skip to: 8183 +/* 2572 */ MCD_OPC_Decode, 205, 21, 140, 2, // Opcode: t2ADR +/* 2577 */ MCD_OPC_FilterValue, 1, 225, 21, 0, // Skip to: 8183 +/* 2582 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 2585 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2607 +/* 2590 */ MCD_OPC_CheckPredicate, 32, 212, 21, 0, // Skip to: 8183 +/* 2595 */ MCD_OPC_CheckField, 20, 2, 0, 205, 21, 0, // Skip to: 8183 +/* 2602 */ MCD_OPC_Decode, 206, 22, 141, 2, // Opcode: t2MOVi16 +/* 2607 */ MCD_OPC_FilterValue, 1, 195, 21, 0, // Skip to: 8183 +/* 2612 */ MCD_OPC_CheckPredicate, 32, 190, 21, 0, // Skip to: 8183 +/* 2617 */ MCD_OPC_CheckField, 20, 2, 0, 183, 21, 0, // Skip to: 8183 +/* 2624 */ MCD_OPC_Decode, 204, 22, 141, 2, // Opcode: t2MOVTi16 +/* 2629 */ MCD_OPC_FilterValue, 3, 173, 21, 0, // Skip to: 8183 +/* 2634 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 2637 */ MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 2714 +/* 2642 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 2645 */ MCD_OPC_FilterValue, 0, 157, 21, 0, // Skip to: 8183 +/* 2650 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 2653 */ MCD_OPC_FilterValue, 0, 149, 21, 0, // Skip to: 8183 +/* 2658 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 2661 */ MCD_OPC_FilterValue, 0, 141, 21, 0, // Skip to: 8183 +/* 2666 */ MCD_OPC_CheckPredicate, 45, 33, 0, 0, // Skip to: 2704 +/* 2671 */ MCD_OPC_CheckField, 21, 1, 1, 26, 0, 0, // Skip to: 2704 +/* 2678 */ MCD_OPC_CheckField, 12, 3, 0, 19, 0, 0, // Skip to: 2704 +/* 2685 */ MCD_OPC_CheckField, 6, 2, 0, 12, 0, 0, // Skip to: 2704 +/* 2692 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 2704 +/* 2699 */ MCD_OPC_Decode, 199, 23, 142, 2, // Opcode: t2SSAT16 +/* 2704 */ MCD_OPC_CheckPredicate, 38, 98, 21, 0, // Skip to: 8183 +/* 2709 */ MCD_OPC_Decode, 198, 23, 143, 2, // Opcode: t2SSAT +/* 2714 */ MCD_OPC_FilterValue, 1, 66, 0, 0, // Skip to: 2785 +/* 2719 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 2722 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2737 +/* 2727 */ MCD_OPC_CheckPredicate, 38, 75, 21, 0, // Skip to: 8183 +/* 2732 */ MCD_OPC_Decode, 146, 23, 144, 2, // Opcode: t2SBFX +/* 2737 */ MCD_OPC_FilterValue, 2, 65, 21, 0, // Skip to: 8183 +/* 2742 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 2745 */ MCD_OPC_FilterValue, 0, 57, 21, 0, // Skip to: 8183 +/* 2750 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 2753 */ MCD_OPC_FilterValue, 0, 49, 21, 0, // Skip to: 8183 +/* 2758 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2775 +/* 2763 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2775 +/* 2770 */ MCD_OPC_Decode, 212, 21, 145, 2, // Opcode: t2BFC +/* 2775 */ MCD_OPC_CheckPredicate, 38, 27, 21, 0, // Skip to: 8183 +/* 2780 */ MCD_OPC_Decode, 213, 21, 146, 2, // Opcode: t2BFI +/* 2785 */ MCD_OPC_FilterValue, 2, 72, 0, 0, // Skip to: 2862 +/* 2790 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... +/* 2793 */ MCD_OPC_FilterValue, 0, 9, 21, 0, // Skip to: 8183 +/* 2798 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 2801 */ MCD_OPC_FilterValue, 0, 1, 21, 0, // Skip to: 8183 +/* 2806 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... +/* 2809 */ MCD_OPC_FilterValue, 0, 249, 20, 0, // Skip to: 8183 +/* 2814 */ MCD_OPC_CheckPredicate, 45, 33, 0, 0, // Skip to: 2852 +/* 2819 */ MCD_OPC_CheckField, 21, 1, 1, 26, 0, 0, // Skip to: 2852 +/* 2826 */ MCD_OPC_CheckField, 12, 3, 0, 19, 0, 0, // Skip to: 2852 +/* 2833 */ MCD_OPC_CheckField, 6, 2, 0, 12, 0, 0, // Skip to: 2852 +/* 2840 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 2852 +/* 2847 */ MCD_OPC_Decode, 175, 24, 142, 2, // Opcode: t2USAT16 +/* 2852 */ MCD_OPC_CheckPredicate, 38, 206, 20, 0, // Skip to: 8183 +/* 2857 */ MCD_OPC_Decode, 174, 24, 143, 2, // Opcode: t2USAT +/* 2862 */ MCD_OPC_FilterValue, 3, 196, 20, 0, // Skip to: 8183 +/* 2867 */ MCD_OPC_CheckPredicate, 38, 191, 20, 0, // Skip to: 8183 +/* 2872 */ MCD_OPC_CheckField, 20, 2, 0, 184, 20, 0, // Skip to: 8183 +/* 2879 */ MCD_OPC_Decode, 154, 24, 144, 2, // Opcode: t2UBFX +/* 2884 */ MCD_OPC_FilterValue, 1, 174, 20, 0, // Skip to: 8183 +/* 2889 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 2892 */ MCD_OPC_FilterValue, 0, 187, 2, 0, // Skip to: 3596 +/* 2897 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 2900 */ MCD_OPC_FilterValue, 0, 158, 20, 0, // Skip to: 8183 +/* 2905 */ MCD_OPC_ExtractField, 0, 12, // Inst{11-0} ... +/* 2908 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2937 +/* 2913 */ MCD_OPC_CheckPredicate, 46, 166, 0, 0, // Skip to: 3084 +/* 2918 */ MCD_OPC_CheckField, 16, 11, 143, 15, 158, 0, 0, // Skip to: 3084 +/* 2926 */ MCD_OPC_CheckField, 13, 1, 0, 151, 0, 0, // Skip to: 3084 +/* 2933 */ MCD_OPC_Decode, 239, 21, 51, // Opcode: t2DCPS1 +/* 2937 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 2966 +/* 2942 */ MCD_OPC_CheckPredicate, 46, 137, 0, 0, // Skip to: 3084 +/* 2947 */ MCD_OPC_CheckField, 16, 11, 143, 15, 129, 0, 0, // Skip to: 3084 +/* 2955 */ MCD_OPC_CheckField, 13, 1, 0, 122, 0, 0, // Skip to: 3084 +/* 2962 */ MCD_OPC_Decode, 240, 21, 51, // Opcode: t2DCPS2 +/* 2966 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 2995 +/* 2971 */ MCD_OPC_CheckPredicate, 46, 108, 0, 0, // Skip to: 3084 +/* 2976 */ MCD_OPC_CheckField, 16, 11, 143, 15, 100, 0, 0, // Skip to: 3084 +/* 2984 */ MCD_OPC_CheckField, 13, 1, 0, 93, 0, 0, // Skip to: 3084 +/* 2991 */ MCD_OPC_Decode, 241, 21, 51, // Opcode: t2DCPS3 +/* 2995 */ MCD_OPC_FilterValue, 18, 24, 0, 0, // Skip to: 3024 +/* 3000 */ MCD_OPC_CheckPredicate, 47, 79, 0, 0, // Skip to: 3084 +/* 3005 */ MCD_OPC_CheckField, 16, 11, 175, 7, 71, 0, 0, // Skip to: 3084 +/* 3013 */ MCD_OPC_CheckField, 13, 1, 0, 64, 0, 0, // Skip to: 3084 +/* 3020 */ MCD_OPC_Decode, 143, 24, 51, // Opcode: t2TSB +/* 3024 */ MCD_OPC_FilterValue, 128, 30, 24, 0, 0, // Skip to: 3054 +/* 3030 */ MCD_OPC_CheckPredicate, 39, 49, 0, 0, // Skip to: 3084 +/* 3035 */ MCD_OPC_CheckField, 20, 7, 60, 42, 0, 0, // Skip to: 3084 +/* 3042 */ MCD_OPC_CheckField, 13, 1, 0, 35, 0, 0, // Skip to: 3084 +/* 3049 */ MCD_OPC_Decode, 217, 21, 147, 2, // Opcode: t2BXJ +/* 3054 */ MCD_OPC_FilterValue, 175, 30, 24, 0, 0, // Skip to: 3084 +/* 3060 */ MCD_OPC_CheckPredicate, 48, 19, 0, 0, // Skip to: 3084 +/* 3065 */ MCD_OPC_CheckField, 16, 11, 191, 7, 11, 0, 0, // Skip to: 3084 +/* 3073 */ MCD_OPC_CheckField, 13, 1, 0, 4, 0, 0, // Skip to: 3084 +/* 3080 */ MCD_OPC_Decode, 221, 21, 51, // Opcode: t2CLREX +/* 3084 */ MCD_OPC_ExtractField, 16, 11, // Inst{26-16} ... +/* 3087 */ MCD_OPC_FilterValue, 175, 7, 131, 0, 0, // Skip to: 3224 +/* 3093 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 3096 */ MCD_OPC_FilterValue, 0, 68, 0, 0, // Skip to: 3169 +/* 3101 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 3104 */ MCD_OPC_FilterValue, 0, 24, 1, 0, // Skip to: 3389 +/* 3109 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3112 */ MCD_OPC_FilterValue, 0, 16, 1, 0, // Skip to: 3389 +/* 3117 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 3120 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 3152 +/* 3125 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3142 +/* 3130 */ MCD_OPC_CheckField, 4, 4, 15, 5, 0, 0, // Skip to: 3142 +/* 3137 */ MCD_OPC_Decode, 238, 21, 148, 2, // Opcode: t2DBG +/* 3142 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3152 +/* 3147 */ MCD_OPC_Decode, 247, 21, 226, 1, // Opcode: t2HINT +/* 3152 */ MCD_OPC_CheckPredicate, 39, 232, 0, 0, // Skip to: 3389 +/* 3157 */ MCD_OPC_CheckField, 0, 5, 0, 225, 0, 0, // Skip to: 3389 +/* 3164 */ MCD_OPC_Decode, 230, 21, 149, 2, // Opcode: t2CPS2p +/* 3169 */ MCD_OPC_FilterValue, 1, 215, 0, 0, // Skip to: 3389 +/* 3174 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 3177 */ MCD_OPC_FilterValue, 0, 207, 0, 0, // Skip to: 3389 +/* 3182 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3185 */ MCD_OPC_FilterValue, 0, 199, 0, 0, // Skip to: 3389 +/* 3190 */ MCD_OPC_CheckPredicate, 39, 19, 0, 0, // Skip to: 3214 +/* 3195 */ MCD_OPC_CheckField, 9, 2, 0, 12, 0, 0, // Skip to: 3214 +/* 3202 */ MCD_OPC_CheckField, 5, 3, 0, 5, 0, 0, // Skip to: 3214 +/* 3209 */ MCD_OPC_Decode, 229, 21, 149, 2, // Opcode: t2CPS1p +/* 3214 */ MCD_OPC_CheckPredicate, 39, 170, 0, 0, // Skip to: 3389 +/* 3219 */ MCD_OPC_Decode, 231, 21, 149, 2, // Opcode: t2CPS3p +/* 3224 */ MCD_OPC_FilterValue, 191, 7, 69, 0, 0, // Skip to: 3299 +/* 3230 */ MCD_OPC_ExtractField, 4, 8, // Inst{11-4} ... +/* 3233 */ MCD_OPC_FilterValue, 244, 1, 16, 0, 0, // Skip to: 3255 +/* 3239 */ MCD_OPC_CheckPredicate, 49, 145, 0, 0, // Skip to: 3389 +/* 3244 */ MCD_OPC_CheckField, 13, 1, 0, 138, 0, 0, // Skip to: 3389 +/* 3251 */ MCD_OPC_Decode, 243, 21, 61, // Opcode: t2DSB +/* 3255 */ MCD_OPC_FilterValue, 245, 1, 16, 0, 0, // Skip to: 3277 +/* 3261 */ MCD_OPC_CheckPredicate, 49, 123, 0, 0, // Skip to: 3389 +/* 3266 */ MCD_OPC_CheckField, 13, 1, 0, 116, 0, 0, // Skip to: 3389 +/* 3273 */ MCD_OPC_Decode, 242, 21, 61, // Opcode: t2DMB +/* 3277 */ MCD_OPC_FilterValue, 246, 1, 106, 0, 0, // Skip to: 3389 +/* 3283 */ MCD_OPC_CheckPredicate, 49, 101, 0, 0, // Skip to: 3389 +/* 3288 */ MCD_OPC_CheckField, 13, 1, 0, 94, 0, 0, // Skip to: 3389 +/* 3295 */ MCD_OPC_Decode, 249, 21, 62, // Opcode: t2ISB +/* 3299 */ MCD_OPC_FilterValue, 222, 7, 24, 0, 0, // Skip to: 3329 +/* 3305 */ MCD_OPC_CheckPredicate, 39, 79, 0, 0, // Skip to: 3389 +/* 3310 */ MCD_OPC_CheckField, 13, 1, 0, 72, 0, 0, // Skip to: 3389 +/* 3317 */ MCD_OPC_CheckField, 8, 4, 15, 65, 0, 0, // Skip to: 3389 +/* 3324 */ MCD_OPC_Decode, 255, 23, 226, 1, // Opcode: t2SUBS_PC_LR +/* 3329 */ MCD_OPC_FilterValue, 239, 7, 24, 0, 0, // Skip to: 3359 +/* 3335 */ MCD_OPC_CheckPredicate, 39, 49, 0, 0, // Skip to: 3389 +/* 3340 */ MCD_OPC_CheckField, 13, 1, 0, 42, 0, 0, // Skip to: 3389 +/* 3347 */ MCD_OPC_CheckField, 0, 8, 0, 35, 0, 0, // Skip to: 3389 +/* 3354 */ MCD_OPC_Decode, 214, 22, 150, 2, // Opcode: t2MRS_AR +/* 3359 */ MCD_OPC_FilterValue, 255, 7, 24, 0, 0, // Skip to: 3389 +/* 3365 */ MCD_OPC_CheckPredicate, 39, 19, 0, 0, // Skip to: 3389 +/* 3370 */ MCD_OPC_CheckField, 13, 1, 0, 12, 0, 0, // Skip to: 3389 +/* 3377 */ MCD_OPC_CheckField, 0, 8, 0, 5, 0, 0, // Skip to: 3389 +/* 3384 */ MCD_OPC_Decode, 217, 22, 150, 2, // Opcode: t2MRSsys_AR +/* 3389 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 3392 */ MCD_OPC_FilterValue, 0, 122, 0, 0, // Skip to: 3519 +/* 3397 */ MCD_OPC_ExtractField, 21, 6, // Inst{26-21} ... +/* 3400 */ MCD_OPC_FilterValue, 28, 47, 0, 0, // Skip to: 3452 +/* 3405 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... +/* 3408 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3430 +/* 3413 */ MCD_OPC_CheckPredicate, 39, 123, 0, 0, // Skip to: 3541 +/* 3418 */ MCD_OPC_CheckField, 0, 5, 0, 116, 0, 0, // Skip to: 3541 +/* 3425 */ MCD_OPC_Decode, 218, 22, 151, 2, // Opcode: t2MSR_AR +/* 3430 */ MCD_OPC_FilterValue, 1, 106, 0, 0, // Skip to: 3541 +/* 3435 */ MCD_OPC_CheckPredicate, 50, 101, 0, 0, // Skip to: 3541 +/* 3440 */ MCD_OPC_CheckField, 0, 4, 0, 94, 0, 0, // Skip to: 3541 +/* 3447 */ MCD_OPC_Decode, 220, 22, 152, 2, // Opcode: t2MSRbanked +/* 3452 */ MCD_OPC_FilterValue, 31, 24, 0, 0, // Skip to: 3481 +/* 3457 */ MCD_OPC_CheckPredicate, 50, 79, 0, 0, // Skip to: 3541 +/* 3462 */ MCD_OPC_CheckField, 5, 3, 1, 72, 0, 0, // Skip to: 3541 +/* 3469 */ MCD_OPC_CheckField, 0, 4, 0, 65, 0, 0, // Skip to: 3541 +/* 3476 */ MCD_OPC_Decode, 216, 22, 153, 2, // Opcode: t2MRSbanked +/* 3481 */ MCD_OPC_FilterValue, 63, 55, 0, 0, // Skip to: 3541 +/* 3486 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3489 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3504 +/* 3494 */ MCD_OPC_CheckPredicate, 51, 42, 0, 0, // Skip to: 3541 +/* 3499 */ MCD_OPC_Decode, 248, 21, 154, 2, // Opcode: t2HVC +/* 3504 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 3541 +/* 3509 */ MCD_OPC_CheckPredicate, 52, 27, 0, 0, // Skip to: 3541 +/* 3514 */ MCD_OPC_Decode, 157, 23, 155, 2, // Opcode: t2SMC +/* 3519 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3541 +/* 3524 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3541 +/* 3529 */ MCD_OPC_CheckField, 20, 7, 127, 5, 0, 0, // Skip to: 3541 +/* 3536 */ MCD_OPC_Decode, 155, 24, 154, 2, // Opcode: t2UDF +/* 3541 */ MCD_OPC_ExtractField, 21, 6, // Inst{26-21} ... +/* 3544 */ MCD_OPC_FilterValue, 28, 15, 0, 0, // Skip to: 3564 +/* 3549 */ MCD_OPC_CheckPredicate, 53, 32, 0, 0, // Skip to: 3586 +/* 3554 */ MCD_OPC_SoftFail, 128, 198, 64 /* 0x102300 */, 0, +/* 3559 */ MCD_OPC_Decode, 219, 22, 156, 2, // Opcode: t2MSR_M +/* 3564 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 3586 +/* 3569 */ MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 3586 +/* 3574 */ MCD_OPC_SoftFail, 128, 192, 64 /* 0x102000 */, 128, 128, 60 /* 0xf0000 */, +/* 3581 */ MCD_OPC_Decode, 215, 22, 157, 2, // Opcode: t2MRS_M +/* 3586 */ MCD_OPC_CheckPredicate, 38, 240, 17, 0, // Skip to: 8183 +/* 3591 */ MCD_OPC_Decode, 218, 21, 158, 2, // Opcode: t2Bcc +/* 3596 */ MCD_OPC_FilterValue, 1, 230, 17, 0, // Skip to: 8183 +/* 3601 */ MCD_OPC_CheckPredicate, 32, 225, 17, 0, // Skip to: 8183 +/* 3606 */ MCD_OPC_CheckField, 14, 1, 0, 218, 17, 0, // Skip to: 8183 +/* 3613 */ MCD_OPC_Decode, 211, 21, 159, 2, // Opcode: t2B +/* 3618 */ MCD_OPC_FilterValue, 31, 208, 17, 0, // Skip to: 8183 +/* 3623 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 3626 */ MCD_OPC_FilterValue, 0, 96, 6, 0, // Skip to: 5263 +/* 3631 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... +/* 3634 */ MCD_OPC_FilterValue, 0, 100, 1, 0, // Skip to: 3995 +/* 3639 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 3642 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 3772 +/* 3647 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 3650 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 3757 +/* 3655 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 3658 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3680 +/* 3663 */ MCD_OPC_CheckPredicate, 38, 163, 17, 0, // Skip to: 8183 +/* 3668 */ MCD_OPC_CheckField, 6, 4, 0, 156, 17, 0, // Skip to: 8183 +/* 3675 */ MCD_OPC_Decode, 235, 23, 160, 2, // Opcode: t2STRBs +/* 3680 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3702 +/* 3685 */ MCD_OPC_CheckPredicate, 38, 141, 17, 0, // Skip to: 8183 +/* 3690 */ MCD_OPC_CheckField, 8, 1, 1, 134, 17, 0, // Skip to: 8183 +/* 3697 */ MCD_OPC_Decode, 231, 23, 161, 2, // Opcode: t2STRB_POST +/* 3702 */ MCD_OPC_FilterValue, 3, 124, 17, 0, // Skip to: 8183 +/* 3707 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 3710 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 3742 +/* 3715 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3732 +/* 3720 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 3732 +/* 3727 */ MCD_OPC_Decode, 230, 23, 162, 2, // Opcode: t2STRBT +/* 3732 */ MCD_OPC_CheckPredicate, 38, 94, 17, 0, // Skip to: 8183 +/* 3737 */ MCD_OPC_Decode, 234, 23, 163, 2, // Opcode: t2STRBi8 +/* 3742 */ MCD_OPC_FilterValue, 1, 84, 17, 0, // Skip to: 8183 +/* 3747 */ MCD_OPC_CheckPredicate, 38, 79, 17, 0, // Skip to: 8183 +/* 3752 */ MCD_OPC_Decode, 232, 23, 161, 2, // Opcode: t2STRB_PRE +/* 3757 */ MCD_OPC_FilterValue, 1, 69, 17, 0, // Skip to: 8183 +/* 3762 */ MCD_OPC_CheckPredicate, 38, 64, 17, 0, // Skip to: 8183 +/* 3767 */ MCD_OPC_Decode, 233, 23, 164, 2, // Opcode: t2STRBi12 +/* 3772 */ MCD_OPC_FilterValue, 1, 54, 17, 0, // Skip to: 8183 +/* 3777 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 3780 */ MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 3928 +/* 3785 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 3788 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3828 +/* 3793 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 3796 */ MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 3960 +/* 3801 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3818 +/* 3806 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3818 +/* 3813 */ MCD_OPC_Decode, 239, 22, 165, 2, // Opcode: t2PLDs +/* 3818 */ MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 3960 +/* 3823 */ MCD_OPC_Decode, 158, 22, 165, 2, // Opcode: t2LDRBs +/* 3828 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3850 +/* 3833 */ MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 3960 +/* 3838 */ MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 3960 +/* 3845 */ MCD_OPC_Decode, 153, 22, 161, 2, // Opcode: t2LDRB_POST +/* 3850 */ MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 3960 +/* 3855 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 3858 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 3913 +/* 3863 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 3866 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3888 +/* 3871 */ MCD_OPC_CheckPredicate, 38, 27, 0, 0, // Skip to: 3903 +/* 3876 */ MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 3903 +/* 3883 */ MCD_OPC_Decode, 237, 22, 166, 2, // Opcode: t2PLDi8 +/* 3888 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3903 +/* 3893 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3903 +/* 3898 */ MCD_OPC_Decode, 152, 22, 167, 2, // Opcode: t2LDRBT +/* 3903 */ MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 3960 +/* 3908 */ MCD_OPC_Decode, 156, 22, 166, 2, // Opcode: t2LDRBi8 +/* 3913 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 3960 +/* 3918 */ MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 3960 +/* 3923 */ MCD_OPC_Decode, 154, 22, 161, 2, // Opcode: t2LDRB_PRE +/* 3928 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 3960 +/* 3933 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3950 +/* 3938 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3950 +/* 3945 */ MCD_OPC_Decode, 236, 22, 168, 2, // Opcode: t2PLDi12 +/* 3950 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3960 +/* 3955 */ MCD_OPC_Decode, 155, 22, 168, 2, // Opcode: t2LDRBi12 +/* 3960 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 3963 */ MCD_OPC_FilterValue, 15, 119, 16, 0, // Skip to: 8183 +/* 3968 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3985 +/* 3973 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3985 +/* 3980 */ MCD_OPC_Decode, 238, 22, 169, 2, // Opcode: t2PLDpci +/* 3985 */ MCD_OPC_CheckPredicate, 38, 97, 16, 0, // Skip to: 8183 +/* 3990 */ MCD_OPC_Decode, 157, 22, 169, 2, // Opcode: t2LDRBpci +/* 3995 */ MCD_OPC_FilterValue, 1, 226, 0, 0, // Skip to: 4226 +/* 4000 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4003 */ MCD_OPC_FilterValue, 1, 79, 16, 0, // Skip to: 8183 +/* 4008 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 4011 */ MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 4159 +/* 4016 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 4019 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4059 +/* 4024 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 4027 */ MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 4191 +/* 4032 */ MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4049 +/* 4037 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4049 +/* 4044 */ MCD_OPC_Decode, 243, 22, 165, 2, // Opcode: t2PLIs +/* 4049 */ MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 4191 +/* 4054 */ MCD_OPC_Decode, 179, 22, 165, 2, // Opcode: t2LDRSBs +/* 4059 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4081 +/* 4064 */ MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 4191 +/* 4069 */ MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 4191 +/* 4076 */ MCD_OPC_Decode, 174, 22, 161, 2, // Opcode: t2LDRSB_POST +/* 4081 */ MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 4191 +/* 4086 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 4089 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 4144 +/* 4094 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 4097 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4119 +/* 4102 */ MCD_OPC_CheckPredicate, 54, 27, 0, 0, // Skip to: 4134 +/* 4107 */ MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 4134 +/* 4114 */ MCD_OPC_Decode, 241, 22, 166, 2, // Opcode: t2PLIi8 +/* 4119 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 4134 +/* 4124 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 4134 +/* 4129 */ MCD_OPC_Decode, 173, 22, 167, 2, // Opcode: t2LDRSBT +/* 4134 */ MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 4191 +/* 4139 */ MCD_OPC_Decode, 177, 22, 166, 2, // Opcode: t2LDRSBi8 +/* 4144 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 4191 +/* 4149 */ MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 4191 +/* 4154 */ MCD_OPC_Decode, 175, 22, 161, 2, // Opcode: t2LDRSB_PRE +/* 4159 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 4191 +/* 4164 */ MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4181 +/* 4169 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4181 +/* 4176 */ MCD_OPC_Decode, 240, 22, 168, 2, // Opcode: t2PLIi12 +/* 4181 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 4191 +/* 4186 */ MCD_OPC_Decode, 176, 22, 168, 2, // Opcode: t2LDRSBi12 +/* 4191 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 4194 */ MCD_OPC_FilterValue, 15, 144, 15, 0, // Skip to: 8183 +/* 4199 */ MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4216 +/* 4204 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4216 +/* 4211 */ MCD_OPC_Decode, 242, 22, 169, 2, // Opcode: t2PLIpci +/* 4216 */ MCD_OPC_CheckPredicate, 38, 122, 15, 0, // Skip to: 8183 +/* 4221 */ MCD_OPC_Decode, 178, 22, 169, 2, // Opcode: t2LDRSBpci +/* 4226 */ MCD_OPC_FilterValue, 2, 207, 2, 0, // Skip to: 4950 +/* 4231 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 4234 */ MCD_OPC_FilterValue, 0, 159, 1, 0, // Skip to: 4654 +/* 4239 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... +/* 4242 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 4324 +/* 4247 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 4250 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4272 +/* 4255 */ MCD_OPC_CheckPredicate, 38, 83, 15, 0, // Skip to: 8183 +/* 4260 */ MCD_OPC_CheckField, 12, 4, 15, 76, 15, 0, // Skip to: 8183 +/* 4267 */ MCD_OPC_Decode, 195, 22, 239, 1, // Opcode: t2LSLrr +/* 4272 */ MCD_OPC_FilterValue, 1, 66, 15, 0, // Skip to: 8183 +/* 4277 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4280 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4302 +/* 4285 */ MCD_OPC_CheckPredicate, 45, 53, 15, 0, // Skip to: 8183 +/* 4290 */ MCD_OPC_CheckField, 12, 4, 15, 46, 15, 0, // Skip to: 8183 +/* 4297 */ MCD_OPC_Decode, 141, 23, 170, 2, // Opcode: t2SADD8 +/* 4302 */ MCD_OPC_FilterValue, 1, 36, 15, 0, // Skip to: 8183 +/* 4307 */ MCD_OPC_CheckPredicate, 45, 31, 15, 0, // Skip to: 8183 +/* 4312 */ MCD_OPC_CheckField, 12, 4, 15, 24, 15, 0, // Skip to: 8183 +/* 4319 */ MCD_OPC_Decode, 140, 23, 170, 2, // Opcode: t2SADD16 +/* 4324 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 4390 +/* 4329 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4332 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4361 +/* 4337 */ MCD_OPC_CheckPredicate, 45, 1, 15, 0, // Skip to: 8183 +/* 4342 */ MCD_OPC_CheckField, 23, 1, 1, 250, 14, 0, // Skip to: 8183 +/* 4349 */ MCD_OPC_CheckField, 12, 4, 15, 243, 14, 0, // Skip to: 8183 +/* 4356 */ MCD_OPC_Decode, 246, 22, 170, 2, // Opcode: t2QADD8 +/* 4361 */ MCD_OPC_FilterValue, 1, 233, 14, 0, // Skip to: 8183 +/* 4366 */ MCD_OPC_CheckPredicate, 45, 228, 14, 0, // Skip to: 8183 +/* 4371 */ MCD_OPC_CheckField, 23, 1, 1, 221, 14, 0, // Skip to: 8183 +/* 4378 */ MCD_OPC_CheckField, 12, 4, 15, 214, 14, 0, // Skip to: 8183 +/* 4385 */ MCD_OPC_Decode, 245, 22, 170, 2, // Opcode: t2QADD16 +/* 4390 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 4456 +/* 4395 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4398 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4427 +/* 4403 */ MCD_OPC_CheckPredicate, 45, 191, 14, 0, // Skip to: 8183 +/* 4408 */ MCD_OPC_CheckField, 23, 1, 1, 184, 14, 0, // Skip to: 8183 +/* 4415 */ MCD_OPC_CheckField, 12, 4, 15, 177, 14, 0, // Skip to: 8183 +/* 4422 */ MCD_OPC_Decode, 152, 23, 170, 2, // Opcode: t2SHADD8 +/* 4427 */ MCD_OPC_FilterValue, 1, 167, 14, 0, // Skip to: 8183 +/* 4432 */ MCD_OPC_CheckPredicate, 45, 162, 14, 0, // Skip to: 8183 +/* 4437 */ MCD_OPC_CheckField, 23, 1, 1, 155, 14, 0, // Skip to: 8183 +/* 4444 */ MCD_OPC_CheckField, 12, 4, 15, 148, 14, 0, // Skip to: 8183 +/* 4451 */ MCD_OPC_Decode, 151, 23, 170, 2, // Opcode: t2SHADD16 +/* 4456 */ MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 4522 +/* 4461 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4464 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4493 +/* 4469 */ MCD_OPC_CheckPredicate, 45, 125, 14, 0, // Skip to: 8183 +/* 4474 */ MCD_OPC_CheckField, 23, 1, 1, 118, 14, 0, // Skip to: 8183 +/* 4481 */ MCD_OPC_CheckField, 12, 4, 15, 111, 14, 0, // Skip to: 8183 +/* 4488 */ MCD_OPC_Decode, 152, 24, 170, 2, // Opcode: t2UADD8 +/* 4493 */ MCD_OPC_FilterValue, 1, 101, 14, 0, // Skip to: 8183 +/* 4498 */ MCD_OPC_CheckPredicate, 45, 96, 14, 0, // Skip to: 8183 +/* 4503 */ MCD_OPC_CheckField, 23, 1, 1, 89, 14, 0, // Skip to: 8183 +/* 4510 */ MCD_OPC_CheckField, 12, 4, 15, 82, 14, 0, // Skip to: 8183 +/* 4517 */ MCD_OPC_Decode, 151, 24, 170, 2, // Opcode: t2UADD16 +/* 4522 */ MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 4588 +/* 4527 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4530 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4559 +/* 4535 */ MCD_OPC_CheckPredicate, 45, 59, 14, 0, // Skip to: 8183 +/* 4540 */ MCD_OPC_CheckField, 23, 1, 1, 52, 14, 0, // Skip to: 8183 +/* 4547 */ MCD_OPC_CheckField, 12, 4, 15, 45, 14, 0, // Skip to: 8183 +/* 4554 */ MCD_OPC_Decode, 167, 24, 170, 2, // Opcode: t2UQADD8 +/* 4559 */ MCD_OPC_FilterValue, 1, 35, 14, 0, // Skip to: 8183 +/* 4564 */ MCD_OPC_CheckPredicate, 45, 30, 14, 0, // Skip to: 8183 +/* 4569 */ MCD_OPC_CheckField, 23, 1, 1, 23, 14, 0, // Skip to: 8183 +/* 4576 */ MCD_OPC_CheckField, 12, 4, 15, 16, 14, 0, // Skip to: 8183 +/* 4583 */ MCD_OPC_Decode, 166, 24, 170, 2, // Opcode: t2UQADD16 +/* 4588 */ MCD_OPC_FilterValue, 6, 6, 14, 0, // Skip to: 8183 +/* 4593 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4596 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4625 +/* 4601 */ MCD_OPC_CheckPredicate, 45, 249, 13, 0, // Skip to: 8183 +/* 4606 */ MCD_OPC_CheckField, 23, 1, 1, 242, 13, 0, // Skip to: 8183 +/* 4613 */ MCD_OPC_CheckField, 12, 4, 15, 235, 13, 0, // Skip to: 8183 +/* 4620 */ MCD_OPC_Decode, 158, 24, 170, 2, // Opcode: t2UHADD8 +/* 4625 */ MCD_OPC_FilterValue, 1, 225, 13, 0, // Skip to: 8183 +/* 4630 */ MCD_OPC_CheckPredicate, 45, 220, 13, 0, // Skip to: 8183 +/* 4635 */ MCD_OPC_CheckField, 23, 1, 1, 213, 13, 0, // Skip to: 8183 +/* 4642 */ MCD_OPC_CheckField, 12, 4, 15, 206, 13, 0, // Skip to: 8183 +/* 4649 */ MCD_OPC_Decode, 157, 24, 170, 2, // Opcode: t2UHADD16 +/* 4654 */ MCD_OPC_FilterValue, 1, 196, 13, 0, // Skip to: 8183 +/* 4659 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4662 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 4806 +/* 4667 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 4670 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4710 +/* 4675 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4678 */ MCD_OPC_FilterValue, 15, 172, 13, 0, // Skip to: 8183 +/* 4683 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4700 +/* 4688 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 4700 +/* 4695 */ MCD_OPC_Decode, 137, 24, 171, 2, // Opcode: t2SXTH +/* 4700 */ MCD_OPC_CheckPredicate, 43, 150, 13, 0, // Skip to: 8183 +/* 4705 */ MCD_OPC_Decode, 134, 24, 172, 2, // Opcode: t2SXTAH +/* 4710 */ MCD_OPC_FilterValue, 1, 140, 13, 0, // Skip to: 8183 +/* 4715 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... +/* 4718 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4740 +/* 4723 */ MCD_OPC_CheckPredicate, 45, 127, 13, 0, // Skip to: 8183 +/* 4728 */ MCD_OPC_CheckField, 12, 4, 15, 120, 13, 0, // Skip to: 8183 +/* 4735 */ MCD_OPC_Decode, 244, 22, 173, 2, // Opcode: t2QADD +/* 4740 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4762 +/* 4745 */ MCD_OPC_CheckPredicate, 45, 105, 13, 0, // Skip to: 8183 +/* 4750 */ MCD_OPC_CheckField, 12, 4, 15, 98, 13, 0, // Skip to: 8183 +/* 4757 */ MCD_OPC_Decode, 248, 22, 173, 2, // Opcode: t2QDADD +/* 4762 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4784 +/* 4767 */ MCD_OPC_CheckPredicate, 45, 83, 13, 0, // Skip to: 8183 +/* 4772 */ MCD_OPC_CheckField, 12, 4, 15, 76, 13, 0, // Skip to: 8183 +/* 4779 */ MCD_OPC_Decode, 251, 22, 173, 2, // Opcode: t2QSUB +/* 4784 */ MCD_OPC_FilterValue, 3, 66, 13, 0, // Skip to: 8183 +/* 4789 */ MCD_OPC_CheckPredicate, 45, 61, 13, 0, // Skip to: 8183 +/* 4794 */ MCD_OPC_CheckField, 12, 4, 15, 54, 13, 0, // Skip to: 8183 +/* 4801 */ MCD_OPC_Decode, 249, 22, 173, 2, // Opcode: t2QDSUB +/* 4806 */ MCD_OPC_FilterValue, 1, 44, 13, 0, // Skip to: 8183 +/* 4811 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 4814 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4854 +/* 4819 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 4822 */ MCD_OPC_FilterValue, 15, 28, 13, 0, // Skip to: 8183 +/* 4827 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4844 +/* 4832 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 4844 +/* 4839 */ MCD_OPC_Decode, 184, 24, 171, 2, // Opcode: t2UXTH +/* 4844 */ MCD_OPC_CheckPredicate, 43, 6, 13, 0, // Skip to: 8183 +/* 4849 */ MCD_OPC_Decode, 181, 24, 172, 2, // Opcode: t2UXTAH +/* 4854 */ MCD_OPC_FilterValue, 1, 252, 12, 0, // Skip to: 8183 +/* 4859 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... +/* 4862 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4884 +/* 4867 */ MCD_OPC_CheckPredicate, 38, 239, 12, 0, // Skip to: 8183 +/* 4872 */ MCD_OPC_CheckField, 12, 4, 15, 232, 12, 0, // Skip to: 8183 +/* 4879 */ MCD_OPC_Decode, 255, 22, 174, 2, // Opcode: t2REV +/* 4884 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4906 +/* 4889 */ MCD_OPC_CheckPredicate, 38, 217, 12, 0, // Skip to: 8183 +/* 4894 */ MCD_OPC_CheckField, 12, 4, 15, 210, 12, 0, // Skip to: 8183 +/* 4901 */ MCD_OPC_Decode, 128, 23, 174, 2, // Opcode: t2REV16 +/* 4906 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4928 +/* 4911 */ MCD_OPC_CheckPredicate, 38, 195, 12, 0, // Skip to: 8183 +/* 4916 */ MCD_OPC_CheckField, 12, 4, 15, 188, 12, 0, // Skip to: 8183 +/* 4923 */ MCD_OPC_Decode, 254, 22, 174, 2, // Opcode: t2RBIT +/* 4928 */ MCD_OPC_FilterValue, 3, 178, 12, 0, // Skip to: 8183 +/* 4933 */ MCD_OPC_CheckPredicate, 38, 173, 12, 0, // Skip to: 8183 +/* 4938 */ MCD_OPC_CheckField, 12, 4, 15, 166, 12, 0, // Skip to: 8183 +/* 4945 */ MCD_OPC_Decode, 129, 23, 174, 2, // Opcode: t2REVSH +/* 4950 */ MCD_OPC_FilterValue, 3, 156, 12, 0, // Skip to: 8183 +/* 4955 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 4958 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 5061 +/* 4963 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4966 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 5021 +/* 4971 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 4974 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5006 +/* 4979 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4996 +/* 4984 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4996 +/* 4991 */ MCD_OPC_Decode, 221, 22, 170, 2, // Opcode: t2MUL +/* 4996 */ MCD_OPC_CheckPredicate, 38, 110, 12, 0, // Skip to: 8183 +/* 5001 */ MCD_OPC_Decode, 202, 22, 175, 2, // Opcode: t2MLA +/* 5006 */ MCD_OPC_FilterValue, 1, 100, 12, 0, // Skip to: 8183 +/* 5011 */ MCD_OPC_CheckPredicate, 38, 95, 12, 0, // Skip to: 8183 +/* 5016 */ MCD_OPC_Decode, 187, 23, 176, 2, // Opcode: t2SMULL +/* 5021 */ MCD_OPC_FilterValue, 1, 85, 12, 0, // Skip to: 8183 +/* 5026 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 5029 */ MCD_OPC_FilterValue, 0, 77, 12, 0, // Skip to: 8183 +/* 5034 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5051 +/* 5039 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5051 +/* 5046 */ MCD_OPC_Decode, 185, 23, 170, 2, // Opcode: t2SMULBB +/* 5051 */ MCD_OPC_CheckPredicate, 45, 55, 12, 0, // Skip to: 8183 +/* 5056 */ MCD_OPC_Decode, 158, 23, 175, 2, // Opcode: t2SMLABB +/* 5061 */ MCD_OPC_FilterValue, 1, 65, 0, 0, // Skip to: 5131 +/* 5066 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5069 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5091 +/* 5074 */ MCD_OPC_CheckPredicate, 38, 32, 12, 0, // Skip to: 8183 +/* 5079 */ MCD_OPC_CheckField, 23, 1, 0, 25, 12, 0, // Skip to: 8183 +/* 5086 */ MCD_OPC_Decode, 203, 22, 175, 2, // Opcode: t2MLS +/* 5091 */ MCD_OPC_FilterValue, 1, 15, 12, 0, // Skip to: 8183 +/* 5096 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 5099 */ MCD_OPC_FilterValue, 0, 7, 12, 0, // Skip to: 8183 +/* 5104 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5121 +/* 5109 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5121 +/* 5116 */ MCD_OPC_Decode, 186, 23, 170, 2, // Opcode: t2SMULBT +/* 5121 */ MCD_OPC_CheckPredicate, 45, 241, 11, 0, // Skip to: 8183 +/* 5126 */ MCD_OPC_Decode, 159, 23, 175, 2, // Opcode: t2SMLABT +/* 5131 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 5179 +/* 5136 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5139 */ MCD_OPC_FilterValue, 1, 223, 11, 0, // Skip to: 8183 +/* 5144 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 5147 */ MCD_OPC_FilterValue, 0, 215, 11, 0, // Skip to: 8183 +/* 5152 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5169 +/* 5157 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5169 +/* 5164 */ MCD_OPC_Decode, 188, 23, 170, 2, // Opcode: t2SMULTB +/* 5169 */ MCD_OPC_CheckPredicate, 45, 193, 11, 0, // Skip to: 8183 +/* 5174 */ MCD_OPC_Decode, 169, 23, 175, 2, // Opcode: t2SMLATB +/* 5179 */ MCD_OPC_FilterValue, 3, 43, 0, 0, // Skip to: 5227 +/* 5184 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5187 */ MCD_OPC_FilterValue, 1, 175, 11, 0, // Skip to: 8183 +/* 5192 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 5195 */ MCD_OPC_FilterValue, 0, 167, 11, 0, // Skip to: 8183 +/* 5200 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5217 +/* 5205 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5217 +/* 5212 */ MCD_OPC_Decode, 189, 23, 170, 2, // Opcode: t2SMULTT +/* 5217 */ MCD_OPC_CheckPredicate, 45, 145, 11, 0, // Skip to: 8183 +/* 5222 */ MCD_OPC_Decode, 170, 23, 175, 2, // Opcode: t2SMLATT +/* 5227 */ MCD_OPC_FilterValue, 15, 135, 11, 0, // Skip to: 8183 +/* 5232 */ MCD_OPC_CheckPredicate, 55, 130, 11, 0, // Skip to: 8183 +/* 5237 */ MCD_OPC_CheckField, 23, 1, 1, 123, 11, 0, // Skip to: 8183 +/* 5244 */ MCD_OPC_CheckField, 20, 1, 1, 116, 11, 0, // Skip to: 8183 +/* 5251 */ MCD_OPC_CheckField, 12, 4, 15, 109, 11, 0, // Skip to: 8183 +/* 5258 */ MCD_OPC_Decode, 147, 23, 170, 2, // Opcode: t2SDIV +/* 5263 */ MCD_OPC_FilterValue, 1, 129, 4, 0, // Skip to: 6421 +/* 5268 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... +/* 5271 */ MCD_OPC_FilterValue, 0, 82, 1, 0, // Skip to: 5614 +/* 5276 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5279 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 5409 +/* 5284 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 5287 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 5394 +/* 5292 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 5295 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5317 +/* 5300 */ MCD_OPC_CheckPredicate, 38, 62, 11, 0, // Skip to: 8183 +/* 5305 */ MCD_OPC_CheckField, 6, 4, 0, 55, 11, 0, // Skip to: 8183 +/* 5312 */ MCD_OPC_Decode, 248, 23, 160, 2, // Opcode: t2STRHs +/* 5317 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5339 +/* 5322 */ MCD_OPC_CheckPredicate, 38, 40, 11, 0, // Skip to: 8183 +/* 5327 */ MCD_OPC_CheckField, 8, 1, 1, 33, 11, 0, // Skip to: 8183 +/* 5334 */ MCD_OPC_Decode, 244, 23, 161, 2, // Opcode: t2STRH_POST +/* 5339 */ MCD_OPC_FilterValue, 3, 23, 11, 0, // Skip to: 8183 +/* 5344 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5347 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5379 +/* 5352 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 5369 +/* 5357 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 5369 +/* 5364 */ MCD_OPC_Decode, 243, 23, 162, 2, // Opcode: t2STRHT +/* 5369 */ MCD_OPC_CheckPredicate, 38, 249, 10, 0, // Skip to: 8183 +/* 5374 */ MCD_OPC_Decode, 247, 23, 163, 2, // Opcode: t2STRHi8 +/* 5379 */ MCD_OPC_FilterValue, 1, 239, 10, 0, // Skip to: 8183 +/* 5384 */ MCD_OPC_CheckPredicate, 38, 234, 10, 0, // Skip to: 8183 +/* 5389 */ MCD_OPC_Decode, 245, 23, 161, 2, // Opcode: t2STRH_PRE +/* 5394 */ MCD_OPC_FilterValue, 1, 224, 10, 0, // Skip to: 8183 +/* 5399 */ MCD_OPC_CheckPredicate, 38, 219, 10, 0, // Skip to: 8183 +/* 5404 */ MCD_OPC_Decode, 246, 23, 164, 2, // Opcode: t2STRHi12 +/* 5409 */ MCD_OPC_FilterValue, 1, 209, 10, 0, // Skip to: 8183 +/* 5414 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 5417 */ MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 5565 +/* 5422 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 5425 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 5465 +/* 5430 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... +/* 5433 */ MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 5597 +/* 5438 */ MCD_OPC_CheckPredicate, 56, 12, 0, 0, // Skip to: 5455 +/* 5443 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5455 +/* 5450 */ MCD_OPC_Decode, 235, 22, 165, 2, // Opcode: t2PLDWs +/* 5455 */ MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 5597 +/* 5460 */ MCD_OPC_Decode, 172, 22, 165, 2, // Opcode: t2LDRHs +/* 5465 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5487 +/* 5470 */ MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 5597 +/* 5475 */ MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 5597 +/* 5482 */ MCD_OPC_Decode, 167, 22, 161, 2, // Opcode: t2LDRH_POST +/* 5487 */ MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 5597 +/* 5492 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5495 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 5550 +/* 5500 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 5503 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5525 +/* 5508 */ MCD_OPC_CheckPredicate, 56, 27, 0, 0, // Skip to: 5540 +/* 5513 */ MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 5540 +/* 5520 */ MCD_OPC_Decode, 234, 22, 166, 2, // Opcode: t2PLDWi8 +/* 5525 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5540 +/* 5530 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5540 +/* 5535 */ MCD_OPC_Decode, 166, 22, 167, 2, // Opcode: t2LDRHT +/* 5540 */ MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 5597 +/* 5545 */ MCD_OPC_Decode, 170, 22, 166, 2, // Opcode: t2LDRHi8 +/* 5550 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 5597 +/* 5555 */ MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 5597 +/* 5560 */ MCD_OPC_Decode, 168, 22, 161, 2, // Opcode: t2LDRH_PRE +/* 5565 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 5597 +/* 5570 */ MCD_OPC_CheckPredicate, 56, 12, 0, 0, // Skip to: 5587 +/* 5575 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5587 +/* 5582 */ MCD_OPC_Decode, 233, 22, 168, 2, // Opcode: t2PLDWi12 +/* 5587 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5597 +/* 5592 */ MCD_OPC_Decode, 169, 22, 168, 2, // Opcode: t2LDRHi12 +/* 5597 */ MCD_OPC_CheckPredicate, 38, 21, 10, 0, // Skip to: 8183 +/* 5602 */ MCD_OPC_CheckField, 16, 4, 15, 14, 10, 0, // Skip to: 8183 +/* 5609 */ MCD_OPC_Decode, 171, 22, 169, 2, // Opcode: t2LDRHpci +/* 5614 */ MCD_OPC_FilterValue, 1, 150, 0, 0, // Skip to: 5769 +/* 5619 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 5622 */ MCD_OPC_FilterValue, 1, 252, 9, 0, // Skip to: 8183 +/* 5627 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 5630 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 5737 +/* 5635 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 5638 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5660 +/* 5643 */ MCD_OPC_CheckPredicate, 38, 104, 0, 0, // Skip to: 5752 +/* 5648 */ MCD_OPC_CheckField, 6, 4, 0, 97, 0, 0, // Skip to: 5752 +/* 5655 */ MCD_OPC_Decode, 186, 22, 165, 2, // Opcode: t2LDRSHs +/* 5660 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5682 +/* 5665 */ MCD_OPC_CheckPredicate, 38, 82, 0, 0, // Skip to: 5752 +/* 5670 */ MCD_OPC_CheckField, 8, 1, 1, 75, 0, 0, // Skip to: 5752 +/* 5677 */ MCD_OPC_Decode, 181, 22, 161, 2, // Opcode: t2LDRSH_POST +/* 5682 */ MCD_OPC_FilterValue, 3, 65, 0, 0, // Skip to: 5752 +/* 5687 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 5690 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5722 +/* 5695 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 5712 +/* 5700 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 5712 +/* 5707 */ MCD_OPC_Decode, 180, 22, 167, 2, // Opcode: t2LDRSHT +/* 5712 */ MCD_OPC_CheckPredicate, 38, 35, 0, 0, // Skip to: 5752 +/* 5717 */ MCD_OPC_Decode, 184, 22, 166, 2, // Opcode: t2LDRSHi8 +/* 5722 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 5752 +/* 5727 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 5752 +/* 5732 */ MCD_OPC_Decode, 182, 22, 161, 2, // Opcode: t2LDRSH_PRE +/* 5737 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5752 +/* 5742 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5752 +/* 5747 */ MCD_OPC_Decode, 183, 22, 168, 2, // Opcode: t2LDRSHi12 +/* 5752 */ MCD_OPC_CheckPredicate, 38, 122, 9, 0, // Skip to: 8183 +/* 5757 */ MCD_OPC_CheckField, 16, 4, 15, 115, 9, 0, // Skip to: 8183 +/* 5764 */ MCD_OPC_Decode, 185, 22, 169, 2, // Opcode: t2LDRSHpci +/* 5769 */ MCD_OPC_FilterValue, 2, 156, 1, 0, // Skip to: 6186 +/* 5774 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 5777 */ MCD_OPC_FilterValue, 0, 242, 0, 0, // Skip to: 6024 +/* 5782 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... +/* 5785 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 5844 +/* 5790 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 5793 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5815 +/* 5798 */ MCD_OPC_CheckPredicate, 38, 76, 9, 0, // Skip to: 8183 +/* 5803 */ MCD_OPC_CheckField, 12, 4, 15, 69, 9, 0, // Skip to: 8183 +/* 5810 */ MCD_OPC_Decode, 197, 22, 239, 1, // Opcode: t2LSRrr +/* 5815 */ MCD_OPC_FilterValue, 1, 59, 9, 0, // Skip to: 8183 +/* 5820 */ MCD_OPC_CheckPredicate, 45, 54, 9, 0, // Skip to: 8183 +/* 5825 */ MCD_OPC_CheckField, 20, 1, 0, 47, 9, 0, // Skip to: 8183 +/* 5832 */ MCD_OPC_CheckField, 12, 4, 15, 40, 9, 0, // Skip to: 8183 +/* 5839 */ MCD_OPC_Decode, 142, 23, 170, 2, // Opcode: t2SASX +/* 5844 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 5880 +/* 5849 */ MCD_OPC_CheckPredicate, 45, 25, 9, 0, // Skip to: 8183 +/* 5854 */ MCD_OPC_CheckField, 23, 1, 1, 18, 9, 0, // Skip to: 8183 +/* 5861 */ MCD_OPC_CheckField, 20, 1, 0, 11, 9, 0, // Skip to: 8183 +/* 5868 */ MCD_OPC_CheckField, 12, 4, 15, 4, 9, 0, // Skip to: 8183 +/* 5875 */ MCD_OPC_Decode, 247, 22, 170, 2, // Opcode: t2QASX +/* 5880 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 5916 +/* 5885 */ MCD_OPC_CheckPredicate, 45, 245, 8, 0, // Skip to: 8183 +/* 5890 */ MCD_OPC_CheckField, 23, 1, 1, 238, 8, 0, // Skip to: 8183 +/* 5897 */ MCD_OPC_CheckField, 20, 1, 0, 231, 8, 0, // Skip to: 8183 +/* 5904 */ MCD_OPC_CheckField, 12, 4, 15, 224, 8, 0, // Skip to: 8183 +/* 5911 */ MCD_OPC_Decode, 153, 23, 170, 2, // Opcode: t2SHASX +/* 5916 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 5952 +/* 5921 */ MCD_OPC_CheckPredicate, 45, 209, 8, 0, // Skip to: 8183 +/* 5926 */ MCD_OPC_CheckField, 23, 1, 1, 202, 8, 0, // Skip to: 8183 +/* 5933 */ MCD_OPC_CheckField, 20, 1, 0, 195, 8, 0, // Skip to: 8183 +/* 5940 */ MCD_OPC_CheckField, 12, 4, 15, 188, 8, 0, // Skip to: 8183 +/* 5947 */ MCD_OPC_Decode, 153, 24, 170, 2, // Opcode: t2UASX +/* 5952 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 5988 +/* 5957 */ MCD_OPC_CheckPredicate, 45, 173, 8, 0, // Skip to: 8183 +/* 5962 */ MCD_OPC_CheckField, 23, 1, 1, 166, 8, 0, // Skip to: 8183 +/* 5969 */ MCD_OPC_CheckField, 20, 1, 0, 159, 8, 0, // Skip to: 8183 +/* 5976 */ MCD_OPC_CheckField, 12, 4, 15, 152, 8, 0, // Skip to: 8183 +/* 5983 */ MCD_OPC_Decode, 168, 24, 170, 2, // Opcode: t2UQASX +/* 5988 */ MCD_OPC_FilterValue, 6, 142, 8, 0, // Skip to: 8183 +/* 5993 */ MCD_OPC_CheckPredicate, 45, 137, 8, 0, // Skip to: 8183 +/* 5998 */ MCD_OPC_CheckField, 23, 1, 1, 130, 8, 0, // Skip to: 8183 +/* 6005 */ MCD_OPC_CheckField, 20, 1, 0, 123, 8, 0, // Skip to: 8183 +/* 6012 */ MCD_OPC_CheckField, 12, 4, 15, 116, 8, 0, // Skip to: 8183 +/* 6019 */ MCD_OPC_Decode, 159, 24, 170, 2, // Opcode: t2UHASX +/* 6024 */ MCD_OPC_FilterValue, 1, 106, 8, 0, // Skip to: 8183 +/* 6029 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6032 */ MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 6109 +/* 6037 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 6040 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6080 +/* 6045 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6048 */ MCD_OPC_FilterValue, 15, 82, 8, 0, // Skip to: 8183 +/* 6053 */ MCD_OPC_CheckPredicate, 43, 12, 0, 0, // Skip to: 6070 +/* 6058 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 6070 +/* 6065 */ MCD_OPC_Decode, 136, 24, 171, 2, // Opcode: t2SXTB16 +/* 6070 */ MCD_OPC_CheckPredicate, 43, 60, 8, 0, // Skip to: 8183 +/* 6075 */ MCD_OPC_Decode, 133, 24, 172, 2, // Opcode: t2SXTAB16 +/* 6080 */ MCD_OPC_FilterValue, 1, 50, 8, 0, // Skip to: 8183 +/* 6085 */ MCD_OPC_CheckPredicate, 45, 45, 8, 0, // Skip to: 8183 +/* 6090 */ MCD_OPC_CheckField, 12, 4, 15, 38, 8, 0, // Skip to: 8183 +/* 6097 */ MCD_OPC_CheckField, 4, 3, 0, 31, 8, 0, // Skip to: 8183 +/* 6104 */ MCD_OPC_Decode, 148, 23, 177, 2, // Opcode: t2SEL +/* 6109 */ MCD_OPC_FilterValue, 1, 21, 8, 0, // Skip to: 8183 +/* 6114 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 6117 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6157 +/* 6122 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 6125 */ MCD_OPC_FilterValue, 15, 5, 8, 0, // Skip to: 8183 +/* 6130 */ MCD_OPC_CheckPredicate, 43, 12, 0, 0, // Skip to: 6147 +/* 6135 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 6147 +/* 6142 */ MCD_OPC_Decode, 183, 24, 171, 2, // Opcode: t2UXTB16 +/* 6147 */ MCD_OPC_CheckPredicate, 43, 239, 7, 0, // Skip to: 8183 +/* 6152 */ MCD_OPC_Decode, 180, 24, 172, 2, // Opcode: t2UXTAB16 +/* 6157 */ MCD_OPC_FilterValue, 1, 229, 7, 0, // Skip to: 8183 +/* 6162 */ MCD_OPC_CheckPredicate, 38, 224, 7, 0, // Skip to: 8183 +/* 6167 */ MCD_OPC_CheckField, 12, 4, 15, 217, 7, 0, // Skip to: 8183 +/* 6174 */ MCD_OPC_CheckField, 4, 3, 0, 210, 7, 0, // Skip to: 8183 +/* 6181 */ MCD_OPC_Decode, 222, 21, 174, 2, // Opcode: t2CLZ +/* 6186 */ MCD_OPC_FilterValue, 3, 200, 7, 0, // Skip to: 8183 +/* 6191 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 6194 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 6297 +/* 6199 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6202 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 6257 +/* 6207 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 6210 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6242 +/* 6215 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6232 +/* 6220 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6232 +/* 6227 */ MCD_OPC_Decode, 183, 23, 170, 2, // Opcode: t2SMUAD +/* 6232 */ MCD_OPC_CheckPredicate, 45, 154, 7, 0, // Skip to: 8183 +/* 6237 */ MCD_OPC_Decode, 160, 23, 175, 2, // Opcode: t2SMLAD +/* 6242 */ MCD_OPC_FilterValue, 1, 144, 7, 0, // Skip to: 8183 +/* 6247 */ MCD_OPC_CheckPredicate, 38, 139, 7, 0, // Skip to: 8183 +/* 6252 */ MCD_OPC_Decode, 165, 24, 176, 2, // Opcode: t2UMULL +/* 6257 */ MCD_OPC_FilterValue, 1, 129, 7, 0, // Skip to: 8183 +/* 6262 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 6265 */ MCD_OPC_FilterValue, 0, 121, 7, 0, // Skip to: 8183 +/* 6270 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6287 +/* 6275 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6287 +/* 6282 */ MCD_OPC_Decode, 190, 23, 170, 2, // Opcode: t2SMULWB +/* 6287 */ MCD_OPC_CheckPredicate, 45, 99, 7, 0, // Skip to: 8183 +/* 6292 */ MCD_OPC_Decode, 171, 23, 175, 2, // Opcode: t2SMLAWB +/* 6297 */ MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 6385 +/* 6302 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6305 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6345 +/* 6310 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 6313 */ MCD_OPC_FilterValue, 0, 73, 7, 0, // Skip to: 8183 +/* 6318 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6335 +/* 6323 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6335 +/* 6330 */ MCD_OPC_Decode, 184, 23, 170, 2, // Opcode: t2SMUADX +/* 6335 */ MCD_OPC_CheckPredicate, 45, 51, 7, 0, // Skip to: 8183 +/* 6340 */ MCD_OPC_Decode, 161, 23, 175, 2, // Opcode: t2SMLADX +/* 6345 */ MCD_OPC_FilterValue, 1, 41, 7, 0, // Skip to: 8183 +/* 6350 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 6353 */ MCD_OPC_FilterValue, 0, 33, 7, 0, // Skip to: 8183 +/* 6358 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6375 +/* 6363 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6375 +/* 6370 */ MCD_OPC_Decode, 191, 23, 170, 2, // Opcode: t2SMULWT +/* 6375 */ MCD_OPC_CheckPredicate, 45, 11, 7, 0, // Skip to: 8183 +/* 6380 */ MCD_OPC_Decode, 172, 23, 175, 2, // Opcode: t2SMLAWT +/* 6385 */ MCD_OPC_FilterValue, 15, 1, 7, 0, // Skip to: 8183 +/* 6390 */ MCD_OPC_CheckPredicate, 55, 252, 6, 0, // Skip to: 8183 +/* 6395 */ MCD_OPC_CheckField, 23, 1, 1, 245, 6, 0, // Skip to: 8183 +/* 6402 */ MCD_OPC_CheckField, 20, 1, 1, 238, 6, 0, // Skip to: 8183 +/* 6409 */ MCD_OPC_CheckField, 12, 4, 15, 231, 6, 0, // Skip to: 8183 +/* 6416 */ MCD_OPC_Decode, 156, 24, 170, 2, // Opcode: t2UDIV +/* 6421 */ MCD_OPC_FilterValue, 2, 107, 5, 0, // Skip to: 7813 +/* 6426 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... +/* 6429 */ MCD_OPC_FilterValue, 0, 24, 1, 0, // Skip to: 6714 +/* 6434 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6437 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 6567 +/* 6442 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 6445 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 6552 +/* 6450 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 6453 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6475 +/* 6458 */ MCD_OPC_CheckPredicate, 38, 184, 6, 0, // Skip to: 8183 +/* 6463 */ MCD_OPC_CheckField, 6, 4, 0, 177, 6, 0, // Skip to: 8183 +/* 6470 */ MCD_OPC_Decode, 254, 23, 178, 2, // Opcode: t2STRs +/* 6475 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6497 +/* 6480 */ MCD_OPC_CheckPredicate, 38, 162, 6, 0, // Skip to: 8183 +/* 6485 */ MCD_OPC_CheckField, 8, 1, 1, 155, 6, 0, // Skip to: 8183 +/* 6492 */ MCD_OPC_Decode, 250, 23, 161, 2, // Opcode: t2STR_POST +/* 6497 */ MCD_OPC_FilterValue, 3, 145, 6, 0, // Skip to: 8183 +/* 6502 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 6505 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6537 +/* 6510 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 6527 +/* 6515 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 6527 +/* 6522 */ MCD_OPC_Decode, 249, 23, 162, 2, // Opcode: t2STRT +/* 6527 */ MCD_OPC_CheckPredicate, 38, 115, 6, 0, // Skip to: 8183 +/* 6532 */ MCD_OPC_Decode, 253, 23, 179, 2, // Opcode: t2STRi8 +/* 6537 */ MCD_OPC_FilterValue, 1, 105, 6, 0, // Skip to: 8183 +/* 6542 */ MCD_OPC_CheckPredicate, 38, 100, 6, 0, // Skip to: 8183 +/* 6547 */ MCD_OPC_Decode, 251, 23, 161, 2, // Opcode: t2STR_PRE +/* 6552 */ MCD_OPC_FilterValue, 1, 90, 6, 0, // Skip to: 8183 +/* 6557 */ MCD_OPC_CheckPredicate, 38, 85, 6, 0, // Skip to: 8183 +/* 6562 */ MCD_OPC_Decode, 252, 23, 180, 2, // Opcode: t2STRi12 +/* 6567 */ MCD_OPC_FilterValue, 1, 75, 6, 0, // Skip to: 8183 +/* 6572 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 6575 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 6682 +/* 6580 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 6583 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6605 +/* 6588 */ MCD_OPC_CheckPredicate, 38, 104, 0, 0, // Skip to: 6697 +/* 6593 */ MCD_OPC_CheckField, 6, 4, 0, 97, 0, 0, // Skip to: 6697 +/* 6600 */ MCD_OPC_Decode, 193, 22, 165, 2, // Opcode: t2LDRs +/* 6605 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6627 +/* 6610 */ MCD_OPC_CheckPredicate, 38, 82, 0, 0, // Skip to: 6697 +/* 6615 */ MCD_OPC_CheckField, 8, 1, 1, 75, 0, 0, // Skip to: 6697 +/* 6622 */ MCD_OPC_Decode, 188, 22, 161, 2, // Opcode: t2LDR_POST +/* 6627 */ MCD_OPC_FilterValue, 3, 65, 0, 0, // Skip to: 6697 +/* 6632 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... +/* 6635 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6667 +/* 6640 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 6657 +/* 6645 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 6657 +/* 6652 */ MCD_OPC_Decode, 187, 22, 167, 2, // Opcode: t2LDRT +/* 6657 */ MCD_OPC_CheckPredicate, 38, 35, 0, 0, // Skip to: 6697 +/* 6662 */ MCD_OPC_Decode, 191, 22, 166, 2, // Opcode: t2LDRi8 +/* 6667 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 6697 +/* 6672 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 6697 +/* 6677 */ MCD_OPC_Decode, 189, 22, 161, 2, // Opcode: t2LDR_PRE +/* 6682 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6697 +/* 6687 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 6697 +/* 6692 */ MCD_OPC_Decode, 190, 22, 168, 2, // Opcode: t2LDRi12 +/* 6697 */ MCD_OPC_CheckPredicate, 38, 201, 5, 0, // Skip to: 8183 +/* 6702 */ MCD_OPC_CheckField, 16, 4, 15, 194, 5, 0, // Skip to: 8183 +/* 6709 */ MCD_OPC_Decode, 192, 22, 169, 2, // Opcode: t2LDRpci +/* 6714 */ MCD_OPC_FilterValue, 2, 163, 2, 0, // Skip to: 7394 +/* 6719 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 6722 */ MCD_OPC_FilterValue, 0, 159, 1, 0, // Skip to: 7142 +/* 6727 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... +/* 6730 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 6812 +/* 6735 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 6738 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6760 +/* 6743 */ MCD_OPC_CheckPredicate, 38, 155, 5, 0, // Skip to: 8183 +/* 6748 */ MCD_OPC_CheckField, 12, 4, 15, 148, 5, 0, // Skip to: 8183 +/* 6755 */ MCD_OPC_Decode, 210, 21, 239, 1, // Opcode: t2ASRrr +/* 6760 */ MCD_OPC_FilterValue, 1, 138, 5, 0, // Skip to: 8183 +/* 6765 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6768 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6790 +/* 6773 */ MCD_OPC_CheckPredicate, 45, 125, 5, 0, // Skip to: 8183 +/* 6778 */ MCD_OPC_CheckField, 12, 4, 15, 118, 5, 0, // Skip to: 8183 +/* 6785 */ MCD_OPC_Decode, 202, 23, 170, 2, // Opcode: t2SSUB8 +/* 6790 */ MCD_OPC_FilterValue, 1, 108, 5, 0, // Skip to: 8183 +/* 6795 */ MCD_OPC_CheckPredicate, 45, 103, 5, 0, // Skip to: 8183 +/* 6800 */ MCD_OPC_CheckField, 12, 4, 15, 96, 5, 0, // Skip to: 8183 +/* 6807 */ MCD_OPC_Decode, 201, 23, 170, 2, // Opcode: t2SSUB16 +/* 6812 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 6878 +/* 6817 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6820 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6849 +/* 6825 */ MCD_OPC_CheckPredicate, 45, 73, 5, 0, // Skip to: 8183 +/* 6830 */ MCD_OPC_CheckField, 23, 1, 1, 66, 5, 0, // Skip to: 8183 +/* 6837 */ MCD_OPC_CheckField, 12, 4, 15, 59, 5, 0, // Skip to: 8183 +/* 6844 */ MCD_OPC_Decode, 253, 22, 170, 2, // Opcode: t2QSUB8 +/* 6849 */ MCD_OPC_FilterValue, 1, 49, 5, 0, // Skip to: 8183 +/* 6854 */ MCD_OPC_CheckPredicate, 45, 44, 5, 0, // Skip to: 8183 +/* 6859 */ MCD_OPC_CheckField, 23, 1, 1, 37, 5, 0, // Skip to: 8183 +/* 6866 */ MCD_OPC_CheckField, 12, 4, 15, 30, 5, 0, // Skip to: 8183 +/* 6873 */ MCD_OPC_Decode, 252, 22, 170, 2, // Opcode: t2QSUB16 +/* 6878 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 6944 +/* 6883 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6886 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6915 +/* 6891 */ MCD_OPC_CheckPredicate, 45, 7, 5, 0, // Skip to: 8183 +/* 6896 */ MCD_OPC_CheckField, 23, 1, 1, 0, 5, 0, // Skip to: 8183 +/* 6903 */ MCD_OPC_CheckField, 12, 4, 15, 249, 4, 0, // Skip to: 8183 +/* 6910 */ MCD_OPC_Decode, 156, 23, 170, 2, // Opcode: t2SHSUB8 +/* 6915 */ MCD_OPC_FilterValue, 1, 239, 4, 0, // Skip to: 8183 +/* 6920 */ MCD_OPC_CheckPredicate, 45, 234, 4, 0, // Skip to: 8183 +/* 6925 */ MCD_OPC_CheckField, 23, 1, 1, 227, 4, 0, // Skip to: 8183 +/* 6932 */ MCD_OPC_CheckField, 12, 4, 15, 220, 4, 0, // Skip to: 8183 +/* 6939 */ MCD_OPC_Decode, 155, 23, 170, 2, // Opcode: t2SHSUB16 +/* 6944 */ MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 7010 +/* 6949 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6952 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6981 +/* 6957 */ MCD_OPC_CheckPredicate, 45, 197, 4, 0, // Skip to: 8183 +/* 6962 */ MCD_OPC_CheckField, 23, 1, 1, 190, 4, 0, // Skip to: 8183 +/* 6969 */ MCD_OPC_CheckField, 12, 4, 15, 183, 4, 0, // Skip to: 8183 +/* 6976 */ MCD_OPC_Decode, 178, 24, 170, 2, // Opcode: t2USUB8 +/* 6981 */ MCD_OPC_FilterValue, 1, 173, 4, 0, // Skip to: 8183 +/* 6986 */ MCD_OPC_CheckPredicate, 45, 168, 4, 0, // Skip to: 8183 +/* 6991 */ MCD_OPC_CheckField, 23, 1, 1, 161, 4, 0, // Skip to: 8183 +/* 6998 */ MCD_OPC_CheckField, 12, 4, 15, 154, 4, 0, // Skip to: 8183 +/* 7005 */ MCD_OPC_Decode, 177, 24, 170, 2, // Opcode: t2USUB16 +/* 7010 */ MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 7076 +/* 7015 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7018 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7047 +/* 7023 */ MCD_OPC_CheckPredicate, 45, 131, 4, 0, // Skip to: 8183 +/* 7028 */ MCD_OPC_CheckField, 23, 1, 1, 124, 4, 0, // Skip to: 8183 +/* 7035 */ MCD_OPC_CheckField, 12, 4, 15, 117, 4, 0, // Skip to: 8183 +/* 7042 */ MCD_OPC_Decode, 171, 24, 170, 2, // Opcode: t2UQSUB8 +/* 7047 */ MCD_OPC_FilterValue, 1, 107, 4, 0, // Skip to: 8183 +/* 7052 */ MCD_OPC_CheckPredicate, 45, 102, 4, 0, // Skip to: 8183 +/* 7057 */ MCD_OPC_CheckField, 23, 1, 1, 95, 4, 0, // Skip to: 8183 +/* 7064 */ MCD_OPC_CheckField, 12, 4, 15, 88, 4, 0, // Skip to: 8183 +/* 7071 */ MCD_OPC_Decode, 170, 24, 170, 2, // Opcode: t2UQSUB16 +/* 7076 */ MCD_OPC_FilterValue, 6, 78, 4, 0, // Skip to: 8183 +/* 7081 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7084 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7113 +/* 7089 */ MCD_OPC_CheckPredicate, 45, 65, 4, 0, // Skip to: 8183 +/* 7094 */ MCD_OPC_CheckField, 23, 1, 1, 58, 4, 0, // Skip to: 8183 +/* 7101 */ MCD_OPC_CheckField, 12, 4, 15, 51, 4, 0, // Skip to: 8183 +/* 7108 */ MCD_OPC_Decode, 162, 24, 170, 2, // Opcode: t2UHSUB8 +/* 7113 */ MCD_OPC_FilterValue, 1, 41, 4, 0, // Skip to: 8183 +/* 7118 */ MCD_OPC_CheckPredicate, 45, 36, 4, 0, // Skip to: 8183 +/* 7123 */ MCD_OPC_CheckField, 23, 1, 1, 29, 4, 0, // Skip to: 8183 +/* 7130 */ MCD_OPC_CheckField, 12, 4, 15, 22, 4, 0, // Skip to: 8183 +/* 7137 */ MCD_OPC_Decode, 161, 24, 170, 2, // Opcode: t2UHSUB16 +/* 7142 */ MCD_OPC_FilterValue, 1, 12, 4, 0, // Skip to: 8183 +/* 7147 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7150 */ MCD_OPC_FilterValue, 0, 117, 0, 0, // Skip to: 7272 +/* 7155 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 7158 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7198 +/* 7163 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7166 */ MCD_OPC_FilterValue, 15, 244, 3, 0, // Skip to: 8183 +/* 7171 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 7188 +/* 7176 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 7188 +/* 7183 */ MCD_OPC_Decode, 135, 24, 171, 2, // Opcode: t2SXTB +/* 7188 */ MCD_OPC_CheckPredicate, 43, 222, 3, 0, // Skip to: 8183 +/* 7193 */ MCD_OPC_Decode, 132, 24, 172, 2, // Opcode: t2SXTAB +/* 7198 */ MCD_OPC_FilterValue, 1, 212, 3, 0, // Skip to: 8183 +/* 7203 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... +/* 7206 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7228 +/* 7211 */ MCD_OPC_CheckPredicate, 57, 199, 3, 0, // Skip to: 8183 +/* 7216 */ MCD_OPC_CheckField, 12, 4, 15, 192, 3, 0, // Skip to: 8183 +/* 7223 */ MCD_OPC_Decode, 232, 21, 170, 2, // Opcode: t2CRC32B +/* 7228 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 7250 +/* 7233 */ MCD_OPC_CheckPredicate, 57, 177, 3, 0, // Skip to: 8183 +/* 7238 */ MCD_OPC_CheckField, 12, 4, 15, 170, 3, 0, // Skip to: 8183 +/* 7245 */ MCD_OPC_Decode, 236, 21, 170, 2, // Opcode: t2CRC32H +/* 7250 */ MCD_OPC_FilterValue, 2, 160, 3, 0, // Skip to: 8183 +/* 7255 */ MCD_OPC_CheckPredicate, 57, 155, 3, 0, // Skip to: 8183 +/* 7260 */ MCD_OPC_CheckField, 12, 4, 15, 148, 3, 0, // Skip to: 8183 +/* 7267 */ MCD_OPC_Decode, 237, 21, 170, 2, // Opcode: t2CRC32W +/* 7272 */ MCD_OPC_FilterValue, 1, 138, 3, 0, // Skip to: 8183 +/* 7277 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 7280 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7320 +/* 7285 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 7288 */ MCD_OPC_FilterValue, 15, 122, 3, 0, // Skip to: 8183 +/* 7293 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 7310 +/* 7298 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 7310 +/* 7305 */ MCD_OPC_Decode, 182, 24, 171, 2, // Opcode: t2UXTB +/* 7310 */ MCD_OPC_CheckPredicate, 43, 100, 3, 0, // Skip to: 8183 +/* 7315 */ MCD_OPC_Decode, 179, 24, 172, 2, // Opcode: t2UXTAB +/* 7320 */ MCD_OPC_FilterValue, 1, 90, 3, 0, // Skip to: 8183 +/* 7325 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... +/* 7328 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7350 +/* 7333 */ MCD_OPC_CheckPredicate, 57, 77, 3, 0, // Skip to: 8183 +/* 7338 */ MCD_OPC_CheckField, 12, 4, 15, 70, 3, 0, // Skip to: 8183 +/* 7345 */ MCD_OPC_Decode, 233, 21, 170, 2, // Opcode: t2CRC32CB +/* 7350 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 7372 +/* 7355 */ MCD_OPC_CheckPredicate, 57, 55, 3, 0, // Skip to: 8183 +/* 7360 */ MCD_OPC_CheckField, 12, 4, 15, 48, 3, 0, // Skip to: 8183 +/* 7367 */ MCD_OPC_Decode, 234, 21, 170, 2, // Opcode: t2CRC32CH +/* 7372 */ MCD_OPC_FilterValue, 2, 38, 3, 0, // Skip to: 8183 +/* 7377 */ MCD_OPC_CheckPredicate, 57, 33, 3, 0, // Skip to: 8183 +/* 7382 */ MCD_OPC_CheckField, 12, 4, 15, 26, 3, 0, // Skip to: 8183 +/* 7389 */ MCD_OPC_Decode, 235, 21, 170, 2, // Opcode: t2CRC32CW +/* 7394 */ MCD_OPC_FilterValue, 3, 16, 3, 0, // Skip to: 8183 +/* 7399 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 7402 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 7505 +/* 7407 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7410 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 7465 +/* 7415 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 7418 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 7450 +/* 7423 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7440 +/* 7428 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7440 +/* 7435 */ MCD_OPC_Decode, 192, 23, 170, 2, // Opcode: t2SMUSD +/* 7440 */ MCD_OPC_CheckPredicate, 45, 226, 2, 0, // Skip to: 8183 +/* 7445 */ MCD_OPC_Decode, 173, 23, 175, 2, // Opcode: t2SMLSD +/* 7450 */ MCD_OPC_FilterValue, 1, 216, 2, 0, // Skip to: 8183 +/* 7455 */ MCD_OPC_CheckPredicate, 38, 211, 2, 0, // Skip to: 8183 +/* 7460 */ MCD_OPC_Decode, 162, 23, 181, 2, // Opcode: t2SMLAL +/* 7465 */ MCD_OPC_FilterValue, 1, 201, 2, 0, // Skip to: 8183 +/* 7470 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 7473 */ MCD_OPC_FilterValue, 0, 193, 2, 0, // Skip to: 8183 +/* 7478 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7495 +/* 7483 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7495 +/* 7490 */ MCD_OPC_Decode, 181, 23, 170, 2, // Opcode: t2SMMUL +/* 7495 */ MCD_OPC_CheckPredicate, 45, 171, 2, 0, // Skip to: 8183 +/* 7500 */ MCD_OPC_Decode, 177, 23, 175, 2, // Opcode: t2SMMLA +/* 7505 */ MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 7593 +/* 7510 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7513 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7553 +/* 7518 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 7521 */ MCD_OPC_FilterValue, 0, 145, 2, 0, // Skip to: 8183 +/* 7526 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7543 +/* 7531 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7543 +/* 7538 */ MCD_OPC_Decode, 193, 23, 170, 2, // Opcode: t2SMUSDX +/* 7543 */ MCD_OPC_CheckPredicate, 45, 123, 2, 0, // Skip to: 8183 +/* 7548 */ MCD_OPC_Decode, 174, 23, 175, 2, // Opcode: t2SMLSDX +/* 7553 */ MCD_OPC_FilterValue, 1, 113, 2, 0, // Skip to: 8183 +/* 7558 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 7561 */ MCD_OPC_FilterValue, 0, 105, 2, 0, // Skip to: 8183 +/* 7566 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7583 +/* 7571 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7583 +/* 7578 */ MCD_OPC_Decode, 182, 23, 170, 2, // Opcode: t2SMMULR +/* 7583 */ MCD_OPC_CheckPredicate, 45, 83, 2, 0, // Skip to: 8183 +/* 7588 */ MCD_OPC_Decode, 178, 23, 175, 2, // Opcode: t2SMMLAR +/* 7593 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 7622 +/* 7598 */ MCD_OPC_CheckPredicate, 45, 68, 2, 0, // Skip to: 8183 +/* 7603 */ MCD_OPC_CheckField, 23, 1, 1, 61, 2, 0, // Skip to: 8183 +/* 7610 */ MCD_OPC_CheckField, 20, 1, 0, 54, 2, 0, // Skip to: 8183 +/* 7617 */ MCD_OPC_Decode, 163, 23, 181, 2, // Opcode: t2SMLALBB +/* 7622 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 7651 +/* 7627 */ MCD_OPC_CheckPredicate, 45, 39, 2, 0, // Skip to: 8183 +/* 7632 */ MCD_OPC_CheckField, 23, 1, 1, 32, 2, 0, // Skip to: 8183 +/* 7639 */ MCD_OPC_CheckField, 20, 1, 0, 25, 2, 0, // Skip to: 8183 +/* 7646 */ MCD_OPC_Decode, 164, 23, 181, 2, // Opcode: t2SMLALBT +/* 7651 */ MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 7680 +/* 7656 */ MCD_OPC_CheckPredicate, 45, 10, 2, 0, // Skip to: 8183 +/* 7661 */ MCD_OPC_CheckField, 23, 1, 1, 3, 2, 0, // Skip to: 8183 +/* 7668 */ MCD_OPC_CheckField, 20, 1, 0, 252, 1, 0, // Skip to: 8183 +/* 7675 */ MCD_OPC_Decode, 167, 23, 181, 2, // Opcode: t2SMLALTB +/* 7680 */ MCD_OPC_FilterValue, 11, 24, 0, 0, // Skip to: 7709 +/* 7685 */ MCD_OPC_CheckPredicate, 45, 237, 1, 0, // Skip to: 8183 +/* 7690 */ MCD_OPC_CheckField, 23, 1, 1, 230, 1, 0, // Skip to: 8183 +/* 7697 */ MCD_OPC_CheckField, 20, 1, 0, 223, 1, 0, // Skip to: 8183 +/* 7704 */ MCD_OPC_Decode, 168, 23, 181, 2, // Opcode: t2SMLALTT +/* 7709 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 7761 +/* 7714 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7717 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7739 +/* 7722 */ MCD_OPC_CheckPredicate, 45, 200, 1, 0, // Skip to: 8183 +/* 7727 */ MCD_OPC_CheckField, 23, 1, 1, 193, 1, 0, // Skip to: 8183 +/* 7734 */ MCD_OPC_Decode, 165, 23, 181, 2, // Opcode: t2SMLALD +/* 7739 */ MCD_OPC_FilterValue, 1, 183, 1, 0, // Skip to: 8183 +/* 7744 */ MCD_OPC_CheckPredicate, 45, 178, 1, 0, // Skip to: 8183 +/* 7749 */ MCD_OPC_CheckField, 23, 1, 1, 171, 1, 0, // Skip to: 8183 +/* 7756 */ MCD_OPC_Decode, 175, 23, 181, 2, // Opcode: t2SMLSLD +/* 7761 */ MCD_OPC_FilterValue, 13, 161, 1, 0, // Skip to: 8183 +/* 7766 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7769 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7791 +/* 7774 */ MCD_OPC_CheckPredicate, 45, 148, 1, 0, // Skip to: 8183 +/* 7779 */ MCD_OPC_CheckField, 23, 1, 1, 141, 1, 0, // Skip to: 8183 +/* 7786 */ MCD_OPC_Decode, 166, 23, 181, 2, // Opcode: t2SMLALDX +/* 7791 */ MCD_OPC_FilterValue, 1, 131, 1, 0, // Skip to: 8183 +/* 7796 */ MCD_OPC_CheckPredicate, 45, 126, 1, 0, // Skip to: 8183 +/* 7801 */ MCD_OPC_CheckField, 23, 1, 1, 119, 1, 0, // Skip to: 8183 +/* 7808 */ MCD_OPC_Decode, 176, 23, 181, 2, // Opcode: t2SMLSLDX +/* 7813 */ MCD_OPC_FilterValue, 3, 109, 1, 0, // Skip to: 8183 +/* 7818 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... +/* 7821 */ MCD_OPC_FilterValue, 0, 131, 0, 0, // Skip to: 7957 +/* 7826 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... +/* 7829 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 7851 +/* 7834 */ MCD_OPC_CheckPredicate, 38, 88, 1, 0, // Skip to: 8183 +/* 7839 */ MCD_OPC_CheckField, 12, 4, 15, 81, 1, 0, // Skip to: 8183 +/* 7846 */ MCD_OPC_Decode, 135, 23, 239, 1, // Opcode: t2RORrr +/* 7851 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 7880 +/* 7856 */ MCD_OPC_CheckPredicate, 45, 66, 1, 0, // Skip to: 8183 +/* 7861 */ MCD_OPC_CheckField, 20, 1, 0, 59, 1, 0, // Skip to: 8183 +/* 7868 */ MCD_OPC_CheckField, 12, 4, 15, 52, 1, 0, // Skip to: 8183 +/* 7875 */ MCD_OPC_Decode, 200, 23, 170, 2, // Opcode: t2SSAX +/* 7880 */ MCD_OPC_FilterValue, 6, 50, 0, 0, // Skip to: 7935 +/* 7885 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7888 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7903 +/* 7893 */ MCD_OPC_CheckPredicate, 45, 29, 1, 0, // Skip to: 8183 +/* 7898 */ MCD_OPC_Decode, 179, 23, 175, 2, // Opcode: t2SMMLS +/* 7903 */ MCD_OPC_FilterValue, 1, 19, 1, 0, // Skip to: 8183 +/* 7908 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7925 +/* 7913 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7925 +/* 7920 */ MCD_OPC_Decode, 172, 24, 170, 2, // Opcode: t2USAD8 +/* 7925 */ MCD_OPC_CheckPredicate, 45, 253, 0, 0, // Skip to: 8183 +/* 7930 */ MCD_OPC_Decode, 173, 24, 175, 2, // Opcode: t2USADA8 +/* 7935 */ MCD_OPC_FilterValue, 7, 243, 0, 0, // Skip to: 8183 +/* 7940 */ MCD_OPC_CheckPredicate, 38, 238, 0, 0, // Skip to: 8183 +/* 7945 */ MCD_OPC_CheckField, 20, 1, 0, 231, 0, 0, // Skip to: 8183 +/* 7952 */ MCD_OPC_Decode, 164, 24, 181, 2, // Opcode: t2UMLAL +/* 7957 */ MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 8016 +/* 7962 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... +/* 7965 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 7994 +/* 7970 */ MCD_OPC_CheckPredicate, 45, 208, 0, 0, // Skip to: 8183 +/* 7975 */ MCD_OPC_CheckField, 20, 1, 0, 201, 0, 0, // Skip to: 8183 +/* 7982 */ MCD_OPC_CheckField, 12, 4, 15, 194, 0, 0, // Skip to: 8183 +/* 7989 */ MCD_OPC_Decode, 250, 22, 170, 2, // Opcode: t2QSAX +/* 7994 */ MCD_OPC_FilterValue, 6, 184, 0, 0, // Skip to: 8183 +/* 7999 */ MCD_OPC_CheckPredicate, 45, 179, 0, 0, // Skip to: 8183 +/* 8004 */ MCD_OPC_CheckField, 20, 1, 0, 172, 0, 0, // Skip to: 8183 +/* 8011 */ MCD_OPC_Decode, 180, 23, 175, 2, // Opcode: t2SMMLSR +/* 8016 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 8052 +/* 8021 */ MCD_OPC_CheckPredicate, 45, 157, 0, 0, // Skip to: 8183 +/* 8026 */ MCD_OPC_CheckField, 23, 4, 5, 150, 0, 0, // Skip to: 8183 +/* 8033 */ MCD_OPC_CheckField, 20, 1, 0, 143, 0, 0, // Skip to: 8183 +/* 8040 */ MCD_OPC_CheckField, 12, 4, 15, 136, 0, 0, // Skip to: 8183 +/* 8047 */ MCD_OPC_Decode, 154, 23, 170, 2, // Opcode: t2SHSAX +/* 8052 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 8088 +/* 8057 */ MCD_OPC_CheckPredicate, 45, 121, 0, 0, // Skip to: 8183 +/* 8062 */ MCD_OPC_CheckField, 23, 4, 5, 114, 0, 0, // Skip to: 8183 +/* 8069 */ MCD_OPC_CheckField, 20, 1, 0, 107, 0, 0, // Skip to: 8183 +/* 8076 */ MCD_OPC_CheckField, 12, 4, 15, 100, 0, 0, // Skip to: 8183 +/* 8083 */ MCD_OPC_Decode, 176, 24, 170, 2, // Opcode: t2USAX +/* 8088 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 8124 +/* 8093 */ MCD_OPC_CheckPredicate, 45, 85, 0, 0, // Skip to: 8183 +/* 8098 */ MCD_OPC_CheckField, 23, 4, 5, 78, 0, 0, // Skip to: 8183 +/* 8105 */ MCD_OPC_CheckField, 20, 1, 0, 71, 0, 0, // Skip to: 8183 +/* 8112 */ MCD_OPC_CheckField, 12, 4, 15, 64, 0, 0, // Skip to: 8183 +/* 8119 */ MCD_OPC_Decode, 169, 24, 170, 2, // Opcode: t2UQSAX +/* 8124 */ MCD_OPC_FilterValue, 6, 54, 0, 0, // Skip to: 8183 +/* 8129 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... +/* 8132 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 8161 +/* 8137 */ MCD_OPC_CheckPredicate, 45, 41, 0, 0, // Skip to: 8183 +/* 8142 */ MCD_OPC_CheckField, 20, 1, 0, 34, 0, 0, // Skip to: 8183 +/* 8149 */ MCD_OPC_CheckField, 12, 4, 15, 27, 0, 0, // Skip to: 8183 +/* 8156 */ MCD_OPC_Decode, 160, 24, 170, 2, // Opcode: t2UHSAX +/* 8161 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 8183 +/* 8166 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 8183 +/* 8171 */ MCD_OPC_CheckField, 20, 1, 0, 5, 0, 0, // Skip to: 8183 +/* 8178 */ MCD_OPC_Decode, 163, 24, 181, 2, // Opcode: t2UMAAL +/* 8183 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumb2CoProc32[] = { +/* 0 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... +/* 3 */ MCD_OPC_FilterValue, 236, 1, 175, 0, 0, // Skip to: 184 +/* 9 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 12 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 33 +/* 17 */ MCD_OPC_CheckPredicate, 38, 191, 2, 0, // Skip to: 725 +/* 22 */ MCD_OPC_CheckField, 23, 1, 1, 184, 2, 0, // Skip to: 725 +/* 29 */ MCD_OPC_Decode, 216, 23, 90, // Opcode: t2STC_OPTION +/* 33 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 54 +/* 38 */ MCD_OPC_CheckPredicate, 38, 170, 2, 0, // Skip to: 725 +/* 43 */ MCD_OPC_CheckField, 23, 1, 1, 163, 2, 0, // Skip to: 725 +/* 50 */ MCD_OPC_Decode, 145, 22, 90, // Opcode: t2LDC_OPTION +/* 54 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 68 +/* 59 */ MCD_OPC_CheckPredicate, 38, 149, 2, 0, // Skip to: 725 +/* 64 */ MCD_OPC_Decode, 217, 23, 90, // Opcode: t2STC_POST +/* 68 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 82 +/* 73 */ MCD_OPC_CheckPredicate, 38, 135, 2, 0, // Skip to: 725 +/* 78 */ MCD_OPC_Decode, 146, 22, 90, // Opcode: t2LDC_POST +/* 82 */ MCD_OPC_FilterValue, 4, 32, 0, 0, // Skip to: 119 +/* 87 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 90 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 105 +/* 95 */ MCD_OPC_CheckPredicate, 38, 113, 2, 0, // Skip to: 725 +/* 100 */ MCD_OPC_Decode, 200, 22, 182, 2, // Opcode: t2MCRR +/* 105 */ MCD_OPC_FilterValue, 1, 103, 2, 0, // Skip to: 725 +/* 110 */ MCD_OPC_CheckPredicate, 38, 98, 2, 0, // Skip to: 725 +/* 115 */ MCD_OPC_Decode, 212, 23, 90, // Opcode: t2STCL_OPTION +/* 119 */ MCD_OPC_FilterValue, 5, 32, 0, 0, // Skip to: 156 +/* 124 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 127 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 142 +/* 132 */ MCD_OPC_CheckPredicate, 38, 76, 2, 0, // Skip to: 725 +/* 137 */ MCD_OPC_Decode, 212, 22, 183, 2, // Opcode: t2MRRC +/* 142 */ MCD_OPC_FilterValue, 1, 66, 2, 0, // Skip to: 725 +/* 147 */ MCD_OPC_CheckPredicate, 38, 61, 2, 0, // Skip to: 725 +/* 152 */ MCD_OPC_Decode, 141, 22, 90, // Opcode: t2LDCL_OPTION +/* 156 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 170 +/* 161 */ MCD_OPC_CheckPredicate, 38, 47, 2, 0, // Skip to: 725 +/* 166 */ MCD_OPC_Decode, 213, 23, 90, // Opcode: t2STCL_POST +/* 170 */ MCD_OPC_FilterValue, 7, 38, 2, 0, // Skip to: 725 +/* 175 */ MCD_OPC_CheckPredicate, 38, 33, 2, 0, // Skip to: 725 +/* 180 */ MCD_OPC_Decode, 142, 22, 90, // Opcode: t2LDCL_POST +/* 184 */ MCD_OPC_FilterValue, 237, 1, 115, 0, 0, // Skip to: 305 +/* 190 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 193 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 207 +/* 198 */ MCD_OPC_CheckPredicate, 38, 10, 2, 0, // Skip to: 725 +/* 203 */ MCD_OPC_Decode, 215, 23, 90, // Opcode: t2STC_OFFSET +/* 207 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 221 +/* 212 */ MCD_OPC_CheckPredicate, 38, 252, 1, 0, // Skip to: 725 +/* 217 */ MCD_OPC_Decode, 144, 22, 90, // Opcode: t2LDC_OFFSET +/* 221 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 235 +/* 226 */ MCD_OPC_CheckPredicate, 38, 238, 1, 0, // Skip to: 725 +/* 231 */ MCD_OPC_Decode, 218, 23, 90, // Opcode: t2STC_PRE +/* 235 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 249 +/* 240 */ MCD_OPC_CheckPredicate, 38, 224, 1, 0, // Skip to: 725 +/* 245 */ MCD_OPC_Decode, 147, 22, 90, // Opcode: t2LDC_PRE +/* 249 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 263 +/* 254 */ MCD_OPC_CheckPredicate, 38, 210, 1, 0, // Skip to: 725 +/* 259 */ MCD_OPC_Decode, 211, 23, 90, // Opcode: t2STCL_OFFSET +/* 263 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 277 +/* 268 */ MCD_OPC_CheckPredicate, 38, 196, 1, 0, // Skip to: 725 +/* 273 */ MCD_OPC_Decode, 140, 22, 90, // Opcode: t2LDCL_OFFSET +/* 277 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 291 +/* 282 */ MCD_OPC_CheckPredicate, 38, 182, 1, 0, // Skip to: 725 +/* 287 */ MCD_OPC_Decode, 214, 23, 90, // Opcode: t2STCL_PRE +/* 291 */ MCD_OPC_FilterValue, 7, 173, 1, 0, // Skip to: 725 +/* 296 */ MCD_OPC_CheckPredicate, 38, 168, 1, 0, // Skip to: 725 +/* 301 */ MCD_OPC_Decode, 143, 22, 90, // Opcode: t2LDCL_PRE +/* 305 */ MCD_OPC_FilterValue, 238, 1, 53, 0, 0, // Skip to: 364 +/* 311 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 314 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 328 +/* 319 */ MCD_OPC_CheckPredicate, 58, 145, 1, 0, // Skip to: 725 +/* 324 */ MCD_OPC_Decode, 219, 21, 91, // Opcode: t2CDP +/* 328 */ MCD_OPC_FilterValue, 1, 136, 1, 0, // Skip to: 725 +/* 333 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 336 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 350 +/* 341 */ MCD_OPC_CheckPredicate, 38, 123, 1, 0, // Skip to: 725 +/* 346 */ MCD_OPC_Decode, 198, 22, 93, // Opcode: t2MCR +/* 350 */ MCD_OPC_FilterValue, 1, 114, 1, 0, // Skip to: 725 +/* 355 */ MCD_OPC_CheckPredicate, 38, 109, 1, 0, // Skip to: 725 +/* 360 */ MCD_OPC_Decode, 210, 22, 95, // Opcode: t2MRC +/* 364 */ MCD_OPC_FilterValue, 252, 1, 175, 0, 0, // Skip to: 545 +/* 370 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 373 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 394 +/* 378 */ MCD_OPC_CheckPredicate, 59, 86, 1, 0, // Skip to: 725 +/* 383 */ MCD_OPC_CheckField, 23, 1, 1, 79, 1, 0, // Skip to: 725 +/* 390 */ MCD_OPC_Decode, 208, 23, 90, // Opcode: t2STC2_OPTION +/* 394 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 415 +/* 399 */ MCD_OPC_CheckPredicate, 59, 65, 1, 0, // Skip to: 725 +/* 404 */ MCD_OPC_CheckField, 23, 1, 1, 58, 1, 0, // Skip to: 725 +/* 411 */ MCD_OPC_Decode, 137, 22, 90, // Opcode: t2LDC2_OPTION +/* 415 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 429 +/* 420 */ MCD_OPC_CheckPredicate, 59, 44, 1, 0, // Skip to: 725 +/* 425 */ MCD_OPC_Decode, 209, 23, 90, // Opcode: t2STC2_POST +/* 429 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 443 +/* 434 */ MCD_OPC_CheckPredicate, 59, 30, 1, 0, // Skip to: 725 +/* 439 */ MCD_OPC_Decode, 138, 22, 90, // Opcode: t2LDC2_POST +/* 443 */ MCD_OPC_FilterValue, 4, 32, 0, 0, // Skip to: 480 +/* 448 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 451 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 466 +/* 456 */ MCD_OPC_CheckPredicate, 58, 8, 1, 0, // Skip to: 725 +/* 461 */ MCD_OPC_Decode, 201, 22, 182, 2, // Opcode: t2MCRR2 +/* 466 */ MCD_OPC_FilterValue, 1, 254, 0, 0, // Skip to: 725 +/* 471 */ MCD_OPC_CheckPredicate, 59, 249, 0, 0, // Skip to: 725 +/* 476 */ MCD_OPC_Decode, 204, 23, 90, // Opcode: t2STC2L_OPTION +/* 480 */ MCD_OPC_FilterValue, 5, 32, 0, 0, // Skip to: 517 +/* 485 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 488 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 503 +/* 493 */ MCD_OPC_CheckPredicate, 58, 227, 0, 0, // Skip to: 725 +/* 498 */ MCD_OPC_Decode, 213, 22, 183, 2, // Opcode: t2MRRC2 +/* 503 */ MCD_OPC_FilterValue, 1, 217, 0, 0, // Skip to: 725 +/* 508 */ MCD_OPC_CheckPredicate, 59, 212, 0, 0, // Skip to: 725 +/* 513 */ MCD_OPC_Decode, 133, 22, 90, // Opcode: t2LDC2L_OPTION +/* 517 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 531 +/* 522 */ MCD_OPC_CheckPredicate, 59, 198, 0, 0, // Skip to: 725 +/* 527 */ MCD_OPC_Decode, 205, 23, 90, // Opcode: t2STC2L_POST +/* 531 */ MCD_OPC_FilterValue, 7, 189, 0, 0, // Skip to: 725 +/* 536 */ MCD_OPC_CheckPredicate, 59, 184, 0, 0, // Skip to: 725 +/* 541 */ MCD_OPC_Decode, 134, 22, 90, // Opcode: t2LDC2L_POST +/* 545 */ MCD_OPC_FilterValue, 253, 1, 115, 0, 0, // Skip to: 666 +/* 551 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... +/* 554 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 568 +/* 559 */ MCD_OPC_CheckPredicate, 59, 161, 0, 0, // Skip to: 725 +/* 564 */ MCD_OPC_Decode, 207, 23, 90, // Opcode: t2STC2_OFFSET +/* 568 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 582 +/* 573 */ MCD_OPC_CheckPredicate, 59, 147, 0, 0, // Skip to: 725 +/* 578 */ MCD_OPC_Decode, 136, 22, 90, // Opcode: t2LDC2_OFFSET +/* 582 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 596 +/* 587 */ MCD_OPC_CheckPredicate, 59, 133, 0, 0, // Skip to: 725 +/* 592 */ MCD_OPC_Decode, 210, 23, 90, // Opcode: t2STC2_PRE +/* 596 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 610 +/* 601 */ MCD_OPC_CheckPredicate, 59, 119, 0, 0, // Skip to: 725 +/* 606 */ MCD_OPC_Decode, 139, 22, 90, // Opcode: t2LDC2_PRE +/* 610 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 624 +/* 615 */ MCD_OPC_CheckPredicate, 59, 105, 0, 0, // Skip to: 725 +/* 620 */ MCD_OPC_Decode, 203, 23, 90, // Opcode: t2STC2L_OFFSET +/* 624 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 638 +/* 629 */ MCD_OPC_CheckPredicate, 59, 91, 0, 0, // Skip to: 725 +/* 634 */ MCD_OPC_Decode, 132, 22, 90, // Opcode: t2LDC2L_OFFSET +/* 638 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 652 +/* 643 */ MCD_OPC_CheckPredicate, 59, 77, 0, 0, // Skip to: 725 +/* 648 */ MCD_OPC_Decode, 206, 23, 90, // Opcode: t2STC2L_PRE +/* 652 */ MCD_OPC_FilterValue, 7, 68, 0, 0, // Skip to: 725 +/* 657 */ MCD_OPC_CheckPredicate, 59, 63, 0, 0, // Skip to: 725 +/* 662 */ MCD_OPC_Decode, 135, 22, 90, // Opcode: t2LDC2L_PRE +/* 666 */ MCD_OPC_FilterValue, 254, 1, 53, 0, 0, // Skip to: 725 +/* 672 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 675 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 689 +/* 680 */ MCD_OPC_CheckPredicate, 58, 40, 0, 0, // Skip to: 725 +/* 685 */ MCD_OPC_Decode, 220, 21, 91, // Opcode: t2CDP2 +/* 689 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 725 +/* 694 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 697 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 711 +/* 702 */ MCD_OPC_CheckPredicate, 58, 18, 0, 0, // Skip to: 725 +/* 707 */ MCD_OPC_Decode, 199, 22, 93, // Opcode: t2MCR2 +/* 711 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 725 +/* 716 */ MCD_OPC_CheckPredicate, 58, 4, 0, 0, // Skip to: 725 +/* 721 */ MCD_OPC_Decode, 211, 22, 95, // Opcode: t2MRC2 +/* 725 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableThumbSBit16[] = { +/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 3 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18 +/* 8 */ MCD_OPC_CheckPredicate, 28, 95, 1, 0, // Skip to: 364 +/* 13 */ MCD_OPC_Decode, 232, 24, 184, 2, // Opcode: tLSLri +/* 18 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 33 +/* 23 */ MCD_OPC_CheckPredicate, 28, 80, 1, 0, // Skip to: 364 +/* 28 */ MCD_OPC_Decode, 234, 24, 184, 2, // Opcode: tLSRri +/* 33 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 48 +/* 38 */ MCD_OPC_CheckPredicate, 28, 65, 1, 0, // Skip to: 364 +/* 43 */ MCD_OPC_Decode, 196, 24, 184, 2, // Opcode: tASRri +/* 48 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 116 +/* 53 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... +/* 56 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71 +/* 61 */ MCD_OPC_CheckPredicate, 28, 42, 1, 0, // Skip to: 364 +/* 66 */ MCD_OPC_Decode, 191, 24, 185, 2, // Opcode: tADDrr +/* 71 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 86 +/* 76 */ MCD_OPC_CheckPredicate, 28, 27, 1, 0, // Skip to: 364 +/* 81 */ MCD_OPC_Decode, 134, 25, 185, 2, // Opcode: tSUBrr +/* 86 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 101 +/* 91 */ MCD_OPC_CheckPredicate, 28, 12, 1, 0, // Skip to: 364 +/* 96 */ MCD_OPC_Decode, 187, 24, 186, 2, // Opcode: tADDi3 +/* 101 */ MCD_OPC_FilterValue, 3, 2, 1, 0, // Skip to: 364 +/* 106 */ MCD_OPC_CheckPredicate, 28, 253, 0, 0, // Skip to: 364 +/* 111 */ MCD_OPC_Decode, 132, 25, 186, 2, // Opcode: tSUBi3 +/* 116 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 131 +/* 121 */ MCD_OPC_CheckPredicate, 28, 238, 0, 0, // Skip to: 364 +/* 126 */ MCD_OPC_Decode, 237, 24, 208, 1, // Opcode: tMOVi8 +/* 131 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 146 +/* 136 */ MCD_OPC_CheckPredicate, 28, 223, 0, 0, // Skip to: 364 +/* 141 */ MCD_OPC_Decode, 188, 24, 187, 2, // Opcode: tADDi8 +/* 146 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 161 +/* 151 */ MCD_OPC_CheckPredicate, 28, 208, 0, 0, // Skip to: 364 +/* 156 */ MCD_OPC_Decode, 133, 25, 187, 2, // Opcode: tSUBi8 +/* 161 */ MCD_OPC_FilterValue, 8, 198, 0, 0, // Skip to: 364 +/* 166 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... +/* 169 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 184 +/* 174 */ MCD_OPC_CheckPredicate, 28, 185, 0, 0, // Skip to: 364 +/* 179 */ MCD_OPC_Decode, 195, 24, 188, 2, // Opcode: tAND +/* 184 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 199 +/* 189 */ MCD_OPC_CheckPredicate, 28, 170, 0, 0, // Skip to: 364 +/* 194 */ MCD_OPC_Decode, 215, 24, 188, 2, // Opcode: tEOR +/* 199 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 214 +/* 204 */ MCD_OPC_CheckPredicate, 28, 155, 0, 0, // Skip to: 364 +/* 209 */ MCD_OPC_Decode, 233, 24, 188, 2, // Opcode: tLSLrr +/* 214 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 229 +/* 219 */ MCD_OPC_CheckPredicate, 28, 140, 0, 0, // Skip to: 364 +/* 224 */ MCD_OPC_Decode, 235, 24, 188, 2, // Opcode: tLSRrr +/* 229 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 244 +/* 234 */ MCD_OPC_CheckPredicate, 28, 125, 0, 0, // Skip to: 364 +/* 239 */ MCD_OPC_Decode, 197, 24, 188, 2, // Opcode: tASRrr +/* 244 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 259 +/* 249 */ MCD_OPC_CheckPredicate, 28, 110, 0, 0, // Skip to: 364 +/* 254 */ MCD_OPC_Decode, 185, 24, 188, 2, // Opcode: tADC +/* 259 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 274 +/* 264 */ MCD_OPC_CheckPredicate, 28, 95, 0, 0, // Skip to: 364 +/* 269 */ MCD_OPC_Decode, 250, 24, 188, 2, // Opcode: tSBC +/* 274 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 289 +/* 279 */ MCD_OPC_CheckPredicate, 28, 80, 0, 0, // Skip to: 364 +/* 284 */ MCD_OPC_Decode, 248, 24, 188, 2, // Opcode: tROR +/* 289 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 304 +/* 294 */ MCD_OPC_CheckPredicate, 28, 65, 0, 0, // Skip to: 364 +/* 299 */ MCD_OPC_Decode, 249, 24, 207, 1, // Opcode: tRSB +/* 304 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 319 +/* 309 */ MCD_OPC_CheckPredicate, 28, 50, 0, 0, // Skip to: 364 +/* 314 */ MCD_OPC_Decode, 241, 24, 188, 2, // Opcode: tORR +/* 319 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 334 +/* 324 */ MCD_OPC_CheckPredicate, 28, 35, 0, 0, // Skip to: 364 +/* 329 */ MCD_OPC_Decode, 239, 24, 189, 2, // Opcode: tMUL +/* 334 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 349 +/* 339 */ MCD_OPC_CheckPredicate, 28, 20, 0, 0, // Skip to: 364 +/* 344 */ MCD_OPC_Decode, 199, 24, 188, 2, // Opcode: tBIC +/* 349 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 364 +/* 354 */ MCD_OPC_CheckPredicate, 28, 5, 0, 0, // Skip to: 364 +/* 359 */ MCD_OPC_Decode, 240, 24, 207, 1, // Opcode: tMVN +/* 364 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableVFP32[] = { +/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 3 */ MCD_OPC_FilterValue, 0, 21, 2, 0, // Skip to: 541 +/* 8 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 11 */ MCD_OPC_FilterValue, 9, 130, 0, 0, // Skip to: 146 +/* 16 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 19 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 34 +/* 24 */ MCD_OPC_CheckPredicate, 60, 247, 16, 0, // Skip to: 4372 +/* 29 */ MCD_OPC_Decode, 205, 20, 190, 2, // Opcode: VSTRH +/* 34 */ MCD_OPC_FilterValue, 14, 237, 16, 0, // Skip to: 4372 +/* 39 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 42 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 110 +/* 47 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 50 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 88 +/* 55 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 58 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73 +/* 63 */ MCD_OPC_CheckPredicate, 60, 208, 16, 0, // Skip to: 4372 +/* 68 */ MCD_OPC_Decode, 203, 13, 191, 2, // Opcode: VMLAH +/* 73 */ MCD_OPC_FilterValue, 1, 198, 16, 0, // Skip to: 4372 +/* 78 */ MCD_OPC_CheckPredicate, 60, 193, 16, 0, // Skip to: 4372 +/* 83 */ MCD_OPC_Decode, 254, 9, 192, 2, // Opcode: VDIVH +/* 88 */ MCD_OPC_FilterValue, 1, 183, 16, 0, // Skip to: 4372 +/* 93 */ MCD_OPC_CheckPredicate, 60, 178, 16, 0, // Skip to: 4372 +/* 98 */ MCD_OPC_CheckField, 23, 1, 0, 171, 16, 0, // Skip to: 4372 +/* 105 */ MCD_OPC_Decode, 234, 13, 191, 2, // Opcode: VMLSH +/* 110 */ MCD_OPC_FilterValue, 1, 161, 16, 0, // Skip to: 4372 +/* 115 */ MCD_OPC_CheckPredicate, 60, 156, 16, 0, // Skip to: 4372 +/* 120 */ MCD_OPC_CheckField, 22, 2, 0, 149, 16, 0, // Skip to: 4372 +/* 127 */ MCD_OPC_CheckField, 5, 2, 0, 142, 16, 0, // Skip to: 4372 +/* 134 */ MCD_OPC_CheckField, 0, 4, 0, 135, 16, 0, // Skip to: 4372 +/* 141 */ MCD_OPC_Decode, 139, 14, 193, 2, // Opcode: VMOVHR +/* 146 */ MCD_OPC_FilterValue, 10, 189, 0, 0, // Skip to: 340 +/* 151 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 154 */ MCD_OPC_FilterValue, 12, 54, 0, 0, // Skip to: 213 +/* 159 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 162 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 198 +/* 167 */ MCD_OPC_CheckPredicate, 27, 104, 16, 0, // Skip to: 4372 +/* 172 */ MCD_OPC_CheckField, 22, 1, 1, 97, 16, 0, // Skip to: 4372 +/* 179 */ MCD_OPC_CheckField, 6, 2, 0, 90, 16, 0, // Skip to: 4372 +/* 186 */ MCD_OPC_CheckField, 4, 1, 1, 83, 16, 0, // Skip to: 4372 +/* 193 */ MCD_OPC_Decode, 155, 14, 194, 2, // Opcode: VMOVSRR +/* 198 */ MCD_OPC_FilterValue, 1, 73, 16, 0, // Skip to: 4372 +/* 203 */ MCD_OPC_CheckPredicate, 27, 68, 16, 0, // Skip to: 4372 +/* 208 */ MCD_OPC_Decode, 202, 20, 195, 2, // Opcode: VSTMSIA +/* 213 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 228 +/* 218 */ MCD_OPC_CheckPredicate, 27, 53, 16, 0, // Skip to: 4372 +/* 223 */ MCD_OPC_Decode, 206, 20, 196, 2, // Opcode: VSTRS +/* 228 */ MCD_OPC_FilterValue, 14, 43, 16, 0, // Skip to: 4372 +/* 233 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 236 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 304 +/* 241 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 244 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 282 +/* 249 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 252 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 267 +/* 257 */ MCD_OPC_CheckPredicate, 27, 14, 16, 0, // Skip to: 4372 +/* 262 */ MCD_OPC_Decode, 214, 13, 197, 2, // Opcode: VMLAS +/* 267 */ MCD_OPC_FilterValue, 1, 4, 16, 0, // Skip to: 4372 +/* 272 */ MCD_OPC_CheckPredicate, 27, 255, 15, 0, // Skip to: 4372 +/* 277 */ MCD_OPC_Decode, 255, 9, 198, 2, // Opcode: VDIVS +/* 282 */ MCD_OPC_FilterValue, 1, 245, 15, 0, // Skip to: 4372 +/* 287 */ MCD_OPC_CheckPredicate, 27, 240, 15, 0, // Skip to: 4372 +/* 292 */ MCD_OPC_CheckField, 23, 1, 0, 233, 15, 0, // Skip to: 4372 +/* 299 */ MCD_OPC_Decode, 245, 13, 197, 2, // Opcode: VMLSS +/* 304 */ MCD_OPC_FilterValue, 1, 223, 15, 0, // Skip to: 4372 +/* 309 */ MCD_OPC_CheckPredicate, 27, 218, 15, 0, // Skip to: 4372 +/* 314 */ MCD_OPC_CheckField, 22, 2, 0, 211, 15, 0, // Skip to: 4372 +/* 321 */ MCD_OPC_CheckField, 5, 2, 0, 204, 15, 0, // Skip to: 4372 +/* 328 */ MCD_OPC_CheckField, 0, 4, 0, 197, 15, 0, // Skip to: 4372 +/* 335 */ MCD_OPC_Decode, 154, 14, 199, 2, // Opcode: VMOVSR +/* 340 */ MCD_OPC_FilterValue, 11, 187, 15, 0, // Skip to: 4372 +/* 345 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 348 */ MCD_OPC_FilterValue, 12, 84, 0, 0, // Skip to: 437 +/* 353 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 356 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 392 +/* 361 */ MCD_OPC_CheckPredicate, 27, 166, 15, 0, // Skip to: 4372 +/* 366 */ MCD_OPC_CheckField, 22, 1, 1, 159, 15, 0, // Skip to: 4372 +/* 373 */ MCD_OPC_CheckField, 6, 2, 0, 152, 15, 0, // Skip to: 4372 +/* 380 */ MCD_OPC_CheckField, 4, 1, 1, 145, 15, 0, // Skip to: 4372 +/* 387 */ MCD_OPC_Decode, 137, 14, 200, 2, // Opcode: VMOVDRR +/* 392 */ MCD_OPC_FilterValue, 1, 135, 15, 0, // Skip to: 4372 +/* 397 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 400 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 415 +/* 405 */ MCD_OPC_CheckPredicate, 27, 122, 15, 0, // Skip to: 4372 +/* 410 */ MCD_OPC_Decode, 198, 20, 201, 2, // Opcode: VSTMDIA +/* 415 */ MCD_OPC_FilterValue, 1, 112, 15, 0, // Skip to: 4372 +/* 420 */ MCD_OPC_CheckPredicate, 27, 107, 15, 0, // Skip to: 4372 +/* 425 */ MCD_OPC_CheckField, 22, 1, 0, 100, 15, 0, // Skip to: 4372 +/* 432 */ MCD_OPC_Decode, 216, 4, 202, 2, // Opcode: FSTMXIA +/* 437 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 452 +/* 442 */ MCD_OPC_CheckPredicate, 27, 85, 15, 0, // Skip to: 4372 +/* 447 */ MCD_OPC_Decode, 204, 20, 203, 2, // Opcode: VSTRD +/* 452 */ MCD_OPC_FilterValue, 14, 75, 15, 0, // Skip to: 4372 +/* 457 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 460 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 512 +/* 465 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 468 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 490 +/* 473 */ MCD_OPC_CheckPredicate, 61, 54, 15, 0, // Skip to: 4372 +/* 478 */ MCD_OPC_CheckField, 4, 1, 0, 47, 15, 0, // Skip to: 4372 +/* 485 */ MCD_OPC_Decode, 202, 13, 204, 2, // Opcode: VMLAD +/* 490 */ MCD_OPC_FilterValue, 1, 37, 15, 0, // Skip to: 4372 +/* 495 */ MCD_OPC_CheckPredicate, 61, 32, 15, 0, // Skip to: 4372 +/* 500 */ MCD_OPC_CheckField, 4, 1, 0, 25, 15, 0, // Skip to: 4372 +/* 507 */ MCD_OPC_Decode, 253, 9, 205, 2, // Opcode: VDIVD +/* 512 */ MCD_OPC_FilterValue, 1, 15, 15, 0, // Skip to: 4372 +/* 517 */ MCD_OPC_CheckPredicate, 61, 10, 15, 0, // Skip to: 4372 +/* 522 */ MCD_OPC_CheckField, 23, 1, 0, 3, 15, 0, // Skip to: 4372 +/* 529 */ MCD_OPC_CheckField, 4, 1, 0, 252, 14, 0, // Skip to: 4372 +/* 536 */ MCD_OPC_Decode, 233, 13, 204, 2, // Opcode: VMLSD +/* 541 */ MCD_OPC_FilterValue, 1, 76, 2, 0, // Skip to: 1134 +/* 546 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 549 */ MCD_OPC_FilterValue, 9, 146, 0, 0, // Skip to: 700 +/* 554 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 557 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 572 +/* 562 */ MCD_OPC_CheckPredicate, 60, 221, 14, 0, // Skip to: 4372 +/* 567 */ MCD_OPC_Decode, 152, 13, 190, 2, // Opcode: VLDRH +/* 572 */ MCD_OPC_FilterValue, 14, 211, 14, 0, // Skip to: 4372 +/* 577 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 580 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 664 +/* 585 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 588 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 626 +/* 593 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 596 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 611 +/* 601 */ MCD_OPC_CheckPredicate, 60, 182, 14, 0, // Skip to: 4372 +/* 606 */ MCD_OPC_Decode, 237, 14, 191, 2, // Opcode: VNMLSH +/* 611 */ MCD_OPC_FilterValue, 1, 172, 14, 0, // Skip to: 4372 +/* 616 */ MCD_OPC_CheckPredicate, 60, 167, 14, 0, // Skip to: 4372 +/* 621 */ MCD_OPC_Decode, 167, 10, 191, 2, // Opcode: VFNMSH +/* 626 */ MCD_OPC_FilterValue, 1, 157, 14, 0, // Skip to: 4372 +/* 631 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 634 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 649 +/* 639 */ MCD_OPC_CheckPredicate, 60, 144, 14, 0, // Skip to: 4372 +/* 644 */ MCD_OPC_Decode, 234, 14, 191, 2, // Opcode: VNMLAH +/* 649 */ MCD_OPC_FilterValue, 1, 134, 14, 0, // Skip to: 4372 +/* 654 */ MCD_OPC_CheckPredicate, 60, 129, 14, 0, // Skip to: 4372 +/* 659 */ MCD_OPC_Decode, 164, 10, 191, 2, // Opcode: VFNMAH +/* 664 */ MCD_OPC_FilterValue, 1, 119, 14, 0, // Skip to: 4372 +/* 669 */ MCD_OPC_CheckPredicate, 60, 114, 14, 0, // Skip to: 4372 +/* 674 */ MCD_OPC_CheckField, 22, 2, 0, 107, 14, 0, // Skip to: 4372 +/* 681 */ MCD_OPC_CheckField, 5, 2, 0, 100, 14, 0, // Skip to: 4372 +/* 688 */ MCD_OPC_CheckField, 0, 4, 0, 93, 14, 0, // Skip to: 4372 +/* 695 */ MCD_OPC_Decode, 149, 14, 206, 2, // Opcode: VMOVRH +/* 700 */ MCD_OPC_FilterValue, 10, 205, 0, 0, // Skip to: 910 +/* 705 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 708 */ MCD_OPC_FilterValue, 12, 54, 0, 0, // Skip to: 767 +/* 713 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 716 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 752 +/* 721 */ MCD_OPC_CheckPredicate, 27, 62, 14, 0, // Skip to: 4372 +/* 726 */ MCD_OPC_CheckField, 22, 1, 1, 55, 14, 0, // Skip to: 4372 +/* 733 */ MCD_OPC_CheckField, 6, 2, 0, 48, 14, 0, // Skip to: 4372 +/* 740 */ MCD_OPC_CheckField, 4, 1, 1, 41, 14, 0, // Skip to: 4372 +/* 747 */ MCD_OPC_Decode, 151, 14, 207, 2, // Opcode: VMOVRRS +/* 752 */ MCD_OPC_FilterValue, 1, 31, 14, 0, // Skip to: 4372 +/* 757 */ MCD_OPC_CheckPredicate, 27, 26, 14, 0, // Skip to: 4372 +/* 762 */ MCD_OPC_Decode, 149, 13, 195, 2, // Opcode: VLDMSIA +/* 767 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 782 +/* 772 */ MCD_OPC_CheckPredicate, 27, 11, 14, 0, // Skip to: 4372 +/* 777 */ MCD_OPC_Decode, 153, 13, 196, 2, // Opcode: VLDRS +/* 782 */ MCD_OPC_FilterValue, 14, 1, 14, 0, // Skip to: 4372 +/* 787 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 790 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 874 +/* 795 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 798 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 836 +/* 803 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 806 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 821 +/* 811 */ MCD_OPC_CheckPredicate, 27, 228, 13, 0, // Skip to: 4372 +/* 816 */ MCD_OPC_Decode, 238, 14, 197, 2, // Opcode: VNMLSS +/* 821 */ MCD_OPC_FilterValue, 1, 218, 13, 0, // Skip to: 4372 +/* 826 */ MCD_OPC_CheckPredicate, 62, 213, 13, 0, // Skip to: 4372 +/* 831 */ MCD_OPC_Decode, 168, 10, 197, 2, // Opcode: VFNMSS +/* 836 */ MCD_OPC_FilterValue, 1, 203, 13, 0, // Skip to: 4372 +/* 841 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 844 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 859 +/* 849 */ MCD_OPC_CheckPredicate, 27, 190, 13, 0, // Skip to: 4372 +/* 854 */ MCD_OPC_Decode, 235, 14, 197, 2, // Opcode: VNMLAS +/* 859 */ MCD_OPC_FilterValue, 1, 180, 13, 0, // Skip to: 4372 +/* 864 */ MCD_OPC_CheckPredicate, 62, 175, 13, 0, // Skip to: 4372 +/* 869 */ MCD_OPC_Decode, 165, 10, 197, 2, // Opcode: VFNMAS +/* 874 */ MCD_OPC_FilterValue, 1, 165, 13, 0, // Skip to: 4372 +/* 879 */ MCD_OPC_CheckPredicate, 27, 160, 13, 0, // Skip to: 4372 +/* 884 */ MCD_OPC_CheckField, 22, 2, 0, 153, 13, 0, // Skip to: 4372 +/* 891 */ MCD_OPC_CheckField, 5, 2, 0, 146, 13, 0, // Skip to: 4372 +/* 898 */ MCD_OPC_CheckField, 0, 4, 0, 139, 13, 0, // Skip to: 4372 +/* 905 */ MCD_OPC_Decode, 152, 14, 208, 2, // Opcode: VMOVRS +/* 910 */ MCD_OPC_FilterValue, 11, 129, 13, 0, // Skip to: 4372 +/* 915 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... +/* 918 */ MCD_OPC_FilterValue, 12, 84, 0, 0, // Skip to: 1007 +/* 923 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 926 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 962 +/* 931 */ MCD_OPC_CheckPredicate, 27, 108, 13, 0, // Skip to: 4372 +/* 936 */ MCD_OPC_CheckField, 22, 1, 1, 101, 13, 0, // Skip to: 4372 +/* 943 */ MCD_OPC_CheckField, 6, 2, 0, 94, 13, 0, // Skip to: 4372 +/* 950 */ MCD_OPC_CheckField, 4, 1, 1, 87, 13, 0, // Skip to: 4372 +/* 957 */ MCD_OPC_Decode, 150, 14, 209, 2, // Opcode: VMOVRRD +/* 962 */ MCD_OPC_FilterValue, 1, 77, 13, 0, // Skip to: 4372 +/* 967 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 970 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 985 +/* 975 */ MCD_OPC_CheckPredicate, 27, 64, 13, 0, // Skip to: 4372 +/* 980 */ MCD_OPC_Decode, 145, 13, 201, 2, // Opcode: VLDMDIA +/* 985 */ MCD_OPC_FilterValue, 1, 54, 13, 0, // Skip to: 4372 +/* 990 */ MCD_OPC_CheckPredicate, 27, 49, 13, 0, // Skip to: 4372 +/* 995 */ MCD_OPC_CheckField, 22, 1, 0, 42, 13, 0, // Skip to: 4372 +/* 1002 */ MCD_OPC_Decode, 212, 4, 202, 2, // Opcode: FLDMXIA +/* 1007 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1022 +/* 1012 */ MCD_OPC_CheckPredicate, 27, 27, 13, 0, // Skip to: 4372 +/* 1017 */ MCD_OPC_Decode, 151, 13, 203, 2, // Opcode: VLDRD +/* 1022 */ MCD_OPC_FilterValue, 14, 17, 13, 0, // Skip to: 4372 +/* 1027 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1030 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1082 +/* 1035 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 1038 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1060 +/* 1043 */ MCD_OPC_CheckPredicate, 61, 252, 12, 0, // Skip to: 4372 +/* 1048 */ MCD_OPC_CheckField, 4, 1, 0, 245, 12, 0, // Skip to: 4372 +/* 1055 */ MCD_OPC_Decode, 236, 14, 204, 2, // Opcode: VNMLSD +/* 1060 */ MCD_OPC_FilterValue, 1, 235, 12, 0, // Skip to: 4372 +/* 1065 */ MCD_OPC_CheckPredicate, 63, 230, 12, 0, // Skip to: 4372 +/* 1070 */ MCD_OPC_CheckField, 4, 1, 0, 223, 12, 0, // Skip to: 4372 +/* 1077 */ MCD_OPC_Decode, 166, 10, 204, 2, // Opcode: VFNMSD +/* 1082 */ MCD_OPC_FilterValue, 1, 213, 12, 0, // Skip to: 4372 +/* 1087 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 1090 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1112 +/* 1095 */ MCD_OPC_CheckPredicate, 61, 200, 12, 0, // Skip to: 4372 +/* 1100 */ MCD_OPC_CheckField, 4, 1, 0, 193, 12, 0, // Skip to: 4372 +/* 1107 */ MCD_OPC_Decode, 233, 14, 204, 2, // Opcode: VNMLAD +/* 1112 */ MCD_OPC_FilterValue, 1, 183, 12, 0, // Skip to: 4372 +/* 1117 */ MCD_OPC_CheckPredicate, 63, 178, 12, 0, // Skip to: 4372 +/* 1122 */ MCD_OPC_CheckField, 4, 1, 0, 171, 12, 0, // Skip to: 4372 +/* 1129 */ MCD_OPC_Decode, 163, 10, 204, 2, // Opcode: VFNMAD +/* 1134 */ MCD_OPC_FilterValue, 2, 132, 2, 0, // Skip to: 1783 +/* 1139 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... +/* 1142 */ MCD_OPC_FilterValue, 24, 25, 0, 0, // Skip to: 1172 +/* 1147 */ MCD_OPC_CheckPredicate, 64, 148, 12, 0, // Skip to: 4372 +/* 1152 */ MCD_OPC_CheckField, 22, 1, 0, 141, 12, 0, // Skip to: 4372 +/* 1159 */ MCD_OPC_CheckField, 0, 16, 128, 20, 133, 12, 0, // Skip to: 4372 +/* 1167 */ MCD_OPC_Decode, 155, 13, 210, 2, // Opcode: VLSTM +/* 1172 */ MCD_OPC_FilterValue, 25, 63, 0, 0, // Skip to: 1240 +/* 1177 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1180 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1195 +/* 1185 */ MCD_OPC_CheckPredicate, 27, 110, 12, 0, // Skip to: 4372 +/* 1190 */ MCD_OPC_Decode, 203, 20, 211, 2, // Opcode: VSTMSIA_UPD +/* 1195 */ MCD_OPC_FilterValue, 11, 100, 12, 0, // Skip to: 4372 +/* 1200 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1203 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1218 +/* 1208 */ MCD_OPC_CheckPredicate, 27, 87, 12, 0, // Skip to: 4372 +/* 1213 */ MCD_OPC_Decode, 199, 20, 212, 2, // Opcode: VSTMDIA_UPD +/* 1218 */ MCD_OPC_FilterValue, 1, 77, 12, 0, // Skip to: 4372 +/* 1223 */ MCD_OPC_CheckPredicate, 27, 72, 12, 0, // Skip to: 4372 +/* 1228 */ MCD_OPC_CheckField, 22, 1, 0, 65, 12, 0, // Skip to: 4372 +/* 1235 */ MCD_OPC_Decode, 217, 4, 213, 2, // Opcode: FSTMXIA_UPD +/* 1240 */ MCD_OPC_FilterValue, 26, 63, 0, 0, // Skip to: 1308 +/* 1245 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1248 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1263 +/* 1253 */ MCD_OPC_CheckPredicate, 27, 42, 12, 0, // Skip to: 4372 +/* 1258 */ MCD_OPC_Decode, 201, 20, 211, 2, // Opcode: VSTMSDB_UPD +/* 1263 */ MCD_OPC_FilterValue, 11, 32, 12, 0, // Skip to: 4372 +/* 1268 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1271 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1286 +/* 1276 */ MCD_OPC_CheckPredicate, 27, 19, 12, 0, // Skip to: 4372 +/* 1281 */ MCD_OPC_Decode, 197, 20, 212, 2, // Opcode: VSTMDDB_UPD +/* 1286 */ MCD_OPC_FilterValue, 1, 9, 12, 0, // Skip to: 4372 +/* 1291 */ MCD_OPC_CheckPredicate, 27, 4, 12, 0, // Skip to: 4372 +/* 1296 */ MCD_OPC_CheckField, 22, 1, 0, 253, 11, 0, // Skip to: 4372 +/* 1303 */ MCD_OPC_Decode, 215, 4, 213, 2, // Opcode: FSTMXDB_UPD +/* 1308 */ MCD_OPC_FilterValue, 28, 159, 0, 0, // Skip to: 1472 +/* 1313 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1316 */ MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 1368 +/* 1321 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1324 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1346 +/* 1329 */ MCD_OPC_CheckPredicate, 60, 222, 11, 0, // Skip to: 4372 +/* 1334 */ MCD_OPC_CheckField, 4, 1, 0, 215, 11, 0, // Skip to: 4372 +/* 1341 */ MCD_OPC_Decode, 180, 14, 192, 2, // Opcode: VMULH +/* 1346 */ MCD_OPC_FilterValue, 1, 205, 11, 0, // Skip to: 4372 +/* 1351 */ MCD_OPC_CheckPredicate, 60, 200, 11, 0, // Skip to: 4372 +/* 1356 */ MCD_OPC_CheckField, 4, 1, 0, 193, 11, 0, // Skip to: 4372 +/* 1363 */ MCD_OPC_Decode, 240, 14, 192, 2, // Opcode: VNMULH +/* 1368 */ MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 1420 +/* 1373 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1376 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1398 +/* 1381 */ MCD_OPC_CheckPredicate, 27, 170, 11, 0, // Skip to: 4372 +/* 1386 */ MCD_OPC_CheckField, 4, 1, 0, 163, 11, 0, // Skip to: 4372 +/* 1393 */ MCD_OPC_Decode, 193, 14, 198, 2, // Opcode: VMULS +/* 1398 */ MCD_OPC_FilterValue, 1, 153, 11, 0, // Skip to: 4372 +/* 1403 */ MCD_OPC_CheckPredicate, 27, 148, 11, 0, // Skip to: 4372 +/* 1408 */ MCD_OPC_CheckField, 4, 1, 0, 141, 11, 0, // Skip to: 4372 +/* 1415 */ MCD_OPC_Decode, 241, 14, 198, 2, // Opcode: VNMULS +/* 1420 */ MCD_OPC_FilterValue, 11, 131, 11, 0, // Skip to: 4372 +/* 1425 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1428 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1450 +/* 1433 */ MCD_OPC_CheckPredicate, 61, 118, 11, 0, // Skip to: 4372 +/* 1438 */ MCD_OPC_CheckField, 4, 1, 0, 111, 11, 0, // Skip to: 4372 +/* 1445 */ MCD_OPC_Decode, 179, 14, 205, 2, // Opcode: VMULD +/* 1450 */ MCD_OPC_FilterValue, 1, 101, 11, 0, // Skip to: 4372 +/* 1455 */ MCD_OPC_CheckPredicate, 61, 96, 11, 0, // Skip to: 4372 +/* 1460 */ MCD_OPC_CheckField, 4, 1, 0, 89, 11, 0, // Skip to: 4372 +/* 1467 */ MCD_OPC_Decode, 239, 14, 205, 2, // Opcode: VNMULD +/* 1472 */ MCD_OPC_FilterValue, 29, 79, 11, 0, // Skip to: 4372 +/* 1477 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1480 */ MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 1532 +/* 1485 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1488 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1510 +/* 1493 */ MCD_OPC_CheckPredicate, 60, 58, 11, 0, // Skip to: 4372 +/* 1498 */ MCD_OPC_CheckField, 4, 1, 0, 51, 11, 0, // Skip to: 4372 +/* 1505 */ MCD_OPC_Decode, 150, 10, 191, 2, // Opcode: VFMAH +/* 1510 */ MCD_OPC_FilterValue, 1, 41, 11, 0, // Skip to: 4372 +/* 1515 */ MCD_OPC_CheckPredicate, 60, 36, 11, 0, // Skip to: 4372 +/* 1520 */ MCD_OPC_CheckField, 4, 1, 0, 29, 11, 0, // Skip to: 4372 +/* 1527 */ MCD_OPC_Decode, 157, 10, 191, 2, // Opcode: VFMSH +/* 1532 */ MCD_OPC_FilterValue, 10, 194, 0, 0, // Skip to: 1731 +/* 1537 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 1540 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1578 +/* 1545 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1548 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1563 +/* 1553 */ MCD_OPC_CheckPredicate, 62, 254, 10, 0, // Skip to: 4372 +/* 1558 */ MCD_OPC_Decode, 151, 10, 197, 2, // Opcode: VFMAS +/* 1563 */ MCD_OPC_FilterValue, 1, 244, 10, 0, // Skip to: 4372 +/* 1568 */ MCD_OPC_CheckPredicate, 62, 239, 10, 0, // Skip to: 4372 +/* 1573 */ MCD_OPC_Decode, 158, 10, 197, 2, // Opcode: VFMSS +/* 1578 */ MCD_OPC_FilterValue, 1, 229, 10, 0, // Skip to: 4372 +/* 1583 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 1586 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1615 +/* 1591 */ MCD_OPC_CheckPredicate, 27, 216, 10, 0, // Skip to: 4372 +/* 1596 */ MCD_OPC_CheckField, 22, 1, 1, 209, 10, 0, // Skip to: 4372 +/* 1603 */ MCD_OPC_CheckField, 7, 1, 0, 202, 10, 0, // Skip to: 4372 +/* 1610 */ MCD_OPC_Decode, 178, 14, 214, 2, // Opcode: VMSR_FPSID +/* 1615 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 1644 +/* 1620 */ MCD_OPC_CheckPredicate, 27, 187, 10, 0, // Skip to: 4372 +/* 1625 */ MCD_OPC_CheckField, 22, 1, 1, 180, 10, 0, // Skip to: 4372 +/* 1632 */ MCD_OPC_CheckField, 7, 1, 0, 173, 10, 0, // Skip to: 4372 +/* 1639 */ MCD_OPC_Decode, 174, 14, 214, 2, // Opcode: VMSR +/* 1644 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1673 +/* 1649 */ MCD_OPC_CheckPredicate, 27, 158, 10, 0, // Skip to: 4372 +/* 1654 */ MCD_OPC_CheckField, 22, 1, 1, 151, 10, 0, // Skip to: 4372 +/* 1661 */ MCD_OPC_CheckField, 7, 1, 0, 144, 10, 0, // Skip to: 4372 +/* 1668 */ MCD_OPC_Decode, 175, 14, 214, 2, // Opcode: VMSR_FPEXC +/* 1673 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1702 +/* 1678 */ MCD_OPC_CheckPredicate, 27, 129, 10, 0, // Skip to: 4372 +/* 1683 */ MCD_OPC_CheckField, 22, 1, 1, 122, 10, 0, // Skip to: 4372 +/* 1690 */ MCD_OPC_CheckField, 7, 1, 0, 115, 10, 0, // Skip to: 4372 +/* 1697 */ MCD_OPC_Decode, 176, 14, 214, 2, // Opcode: VMSR_FPINST +/* 1702 */ MCD_OPC_FilterValue, 10, 105, 10, 0, // Skip to: 4372 +/* 1707 */ MCD_OPC_CheckPredicate, 27, 100, 10, 0, // Skip to: 4372 +/* 1712 */ MCD_OPC_CheckField, 22, 1, 1, 93, 10, 0, // Skip to: 4372 +/* 1719 */ MCD_OPC_CheckField, 7, 1, 0, 86, 10, 0, // Skip to: 4372 +/* 1726 */ MCD_OPC_Decode, 177, 14, 214, 2, // Opcode: VMSR_FPINST2 +/* 1731 */ MCD_OPC_FilterValue, 11, 76, 10, 0, // Skip to: 4372 +/* 1736 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1739 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1761 +/* 1744 */ MCD_OPC_CheckPredicate, 63, 63, 10, 0, // Skip to: 4372 +/* 1749 */ MCD_OPC_CheckField, 4, 1, 0, 56, 10, 0, // Skip to: 4372 +/* 1756 */ MCD_OPC_Decode, 149, 10, 204, 2, // Opcode: VFMAD +/* 1761 */ MCD_OPC_FilterValue, 1, 46, 10, 0, // Skip to: 4372 +/* 1766 */ MCD_OPC_CheckPredicate, 63, 41, 10, 0, // Skip to: 4372 +/* 1771 */ MCD_OPC_CheckField, 4, 1, 0, 34, 10, 0, // Skip to: 4372 +/* 1778 */ MCD_OPC_Decode, 156, 10, 204, 2, // Opcode: VFMSD +/* 1783 */ MCD_OPC_FilterValue, 3, 24, 10, 0, // Skip to: 4372 +/* 1788 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... +/* 1791 */ MCD_OPC_FilterValue, 24, 25, 0, 0, // Skip to: 1821 +/* 1796 */ MCD_OPC_CheckPredicate, 64, 11, 10, 0, // Skip to: 4372 +/* 1801 */ MCD_OPC_CheckField, 22, 1, 0, 4, 10, 0, // Skip to: 4372 +/* 1808 */ MCD_OPC_CheckField, 0, 16, 128, 20, 252, 9, 0, // Skip to: 4372 +/* 1816 */ MCD_OPC_Decode, 154, 13, 210, 2, // Opcode: VLLDM +/* 1821 */ MCD_OPC_FilterValue, 25, 63, 0, 0, // Skip to: 1889 +/* 1826 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1829 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1844 +/* 1834 */ MCD_OPC_CheckPredicate, 27, 229, 9, 0, // Skip to: 4372 +/* 1839 */ MCD_OPC_Decode, 150, 13, 211, 2, // Opcode: VLDMSIA_UPD +/* 1844 */ MCD_OPC_FilterValue, 11, 219, 9, 0, // Skip to: 4372 +/* 1849 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1852 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1867 +/* 1857 */ MCD_OPC_CheckPredicate, 27, 206, 9, 0, // Skip to: 4372 +/* 1862 */ MCD_OPC_Decode, 146, 13, 212, 2, // Opcode: VLDMDIA_UPD +/* 1867 */ MCD_OPC_FilterValue, 1, 196, 9, 0, // Skip to: 4372 +/* 1872 */ MCD_OPC_CheckPredicate, 27, 191, 9, 0, // Skip to: 4372 +/* 1877 */ MCD_OPC_CheckField, 22, 1, 0, 184, 9, 0, // Skip to: 4372 +/* 1884 */ MCD_OPC_Decode, 213, 4, 213, 2, // Opcode: FLDMXIA_UPD +/* 1889 */ MCD_OPC_FilterValue, 26, 63, 0, 0, // Skip to: 1957 +/* 1894 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1897 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1912 +/* 1902 */ MCD_OPC_CheckPredicate, 27, 161, 9, 0, // Skip to: 4372 +/* 1907 */ MCD_OPC_Decode, 148, 13, 211, 2, // Opcode: VLDMSDB_UPD +/* 1912 */ MCD_OPC_FilterValue, 11, 151, 9, 0, // Skip to: 4372 +/* 1917 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... +/* 1920 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1935 +/* 1925 */ MCD_OPC_CheckPredicate, 27, 138, 9, 0, // Skip to: 4372 +/* 1930 */ MCD_OPC_Decode, 144, 13, 212, 2, // Opcode: VLDMDDB_UPD +/* 1935 */ MCD_OPC_FilterValue, 1, 128, 9, 0, // Skip to: 4372 +/* 1940 */ MCD_OPC_CheckPredicate, 27, 123, 9, 0, // Skip to: 4372 +/* 1945 */ MCD_OPC_CheckField, 22, 1, 0, 116, 9, 0, // Skip to: 4372 +/* 1952 */ MCD_OPC_Decode, 211, 4, 213, 2, // Opcode: FLDMXDB_UPD +/* 1957 */ MCD_OPC_FilterValue, 28, 159, 0, 0, // Skip to: 2121 +/* 1962 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 1965 */ MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 2017 +/* 1970 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1973 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1995 +/* 1978 */ MCD_OPC_CheckPredicate, 60, 85, 9, 0, // Skip to: 4372 +/* 1983 */ MCD_OPC_CheckField, 4, 1, 0, 78, 9, 0, // Skip to: 4372 +/* 1990 */ MCD_OPC_Decode, 236, 7, 192, 2, // Opcode: VADDH +/* 1995 */ MCD_OPC_FilterValue, 1, 68, 9, 0, // Skip to: 4372 +/* 2000 */ MCD_OPC_CheckPredicate, 60, 63, 9, 0, // Skip to: 4372 +/* 2005 */ MCD_OPC_CheckField, 4, 1, 0, 56, 9, 0, // Skip to: 4372 +/* 2012 */ MCD_OPC_Decode, 208, 20, 192, 2, // Opcode: VSUBH +/* 2017 */ MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 2069 +/* 2022 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2025 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2047 +/* 2030 */ MCD_OPC_CheckPredicate, 27, 33, 9, 0, // Skip to: 4372 +/* 2035 */ MCD_OPC_CheckField, 4, 1, 0, 26, 9, 0, // Skip to: 4372 +/* 2042 */ MCD_OPC_Decode, 246, 7, 198, 2, // Opcode: VADDS +/* 2047 */ MCD_OPC_FilterValue, 1, 16, 9, 0, // Skip to: 4372 +/* 2052 */ MCD_OPC_CheckPredicate, 27, 11, 9, 0, // Skip to: 4372 +/* 2057 */ MCD_OPC_CheckField, 4, 1, 0, 4, 9, 0, // Skip to: 4372 +/* 2064 */ MCD_OPC_Decode, 218, 20, 198, 2, // Opcode: VSUBS +/* 2069 */ MCD_OPC_FilterValue, 11, 250, 8, 0, // Skip to: 4372 +/* 2074 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2077 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2099 +/* 2082 */ MCD_OPC_CheckPredicate, 61, 237, 8, 0, // Skip to: 4372 +/* 2087 */ MCD_OPC_CheckField, 4, 1, 0, 230, 8, 0, // Skip to: 4372 +/* 2094 */ MCD_OPC_Decode, 235, 7, 205, 2, // Opcode: VADDD +/* 2099 */ MCD_OPC_FilterValue, 1, 220, 8, 0, // Skip to: 4372 +/* 2104 */ MCD_OPC_CheckPredicate, 61, 215, 8, 0, // Skip to: 4372 +/* 2109 */ MCD_OPC_CheckField, 4, 1, 0, 208, 8, 0, // Skip to: 4372 +/* 2116 */ MCD_OPC_Decode, 207, 20, 205, 2, // Opcode: VSUBD +/* 2121 */ MCD_OPC_FilterValue, 29, 198, 8, 0, // Skip to: 4372 +/* 2126 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... +/* 2129 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 2151 +/* 2134 */ MCD_OPC_CheckPredicate, 60, 185, 8, 0, // Skip to: 4372 +/* 2139 */ MCD_OPC_CheckField, 4, 2, 0, 178, 8, 0, // Skip to: 4372 +/* 2146 */ MCD_OPC_Decode, 209, 4, 215, 2, // Opcode: FCONSTH +/* 2151 */ MCD_OPC_FilterValue, 37, 11, 1, 0, // Skip to: 2423 +/* 2156 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 2159 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2181 +/* 2164 */ MCD_OPC_CheckPredicate, 60, 155, 8, 0, // Skip to: 4372 +/* 2169 */ MCD_OPC_CheckField, 4, 1, 0, 148, 8, 0, // Skip to: 4372 +/* 2176 */ MCD_OPC_Decode, 221, 14, 216, 2, // Opcode: VNEGH +/* 2181 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2203 +/* 2186 */ MCD_OPC_CheckPredicate, 60, 133, 8, 0, // Skip to: 4372 +/* 2191 */ MCD_OPC_CheckField, 4, 1, 0, 126, 8, 0, // Skip to: 4372 +/* 2198 */ MCD_OPC_Decode, 146, 9, 216, 2, // Opcode: VCMPH +/* 2203 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2225 +/* 2208 */ MCD_OPC_CheckPredicate, 60, 111, 8, 0, // Skip to: 4372 +/* 2213 */ MCD_OPC_CheckField, 0, 6, 0, 104, 8, 0, // Skip to: 4372 +/* 2220 */ MCD_OPC_Decode, 149, 9, 217, 2, // Opcode: VCMPZH +/* 2225 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2247 +/* 2230 */ MCD_OPC_CheckPredicate, 60, 89, 8, 0, // Skip to: 4372 +/* 2235 */ MCD_OPC_CheckField, 4, 1, 0, 82, 8, 0, // Skip to: 4372 +/* 2242 */ MCD_OPC_Decode, 148, 17, 218, 2, // Opcode: VRINTRH +/* 2247 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 2269 +/* 2252 */ MCD_OPC_CheckPredicate, 60, 67, 8, 0, // Skip to: 4372 +/* 2257 */ MCD_OPC_CheckField, 4, 1, 0, 60, 8, 0, // Skip to: 4372 +/* 2264 */ MCD_OPC_Decode, 151, 17, 218, 2, // Opcode: VRINTXH +/* 2269 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 2291 +/* 2274 */ MCD_OPC_CheckPredicate, 60, 45, 8, 0, // Skip to: 4372 +/* 2279 */ MCD_OPC_CheckField, 4, 1, 0, 38, 8, 0, // Skip to: 4372 +/* 2286 */ MCD_OPC_Decode, 167, 21, 219, 2, // Opcode: VUITOH +/* 2291 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 2313 +/* 2296 */ MCD_OPC_CheckPredicate, 60, 23, 8, 0, // Skip to: 4372 +/* 2301 */ MCD_OPC_CheckField, 4, 1, 0, 16, 8, 0, // Skip to: 4372 +/* 2308 */ MCD_OPC_Decode, 172, 18, 220, 2, // Opcode: VSHTOH +/* 2313 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 2335 +/* 2318 */ MCD_OPC_CheckPredicate, 60, 1, 8, 0, // Skip to: 4372 +/* 2323 */ MCD_OPC_CheckField, 4, 1, 0, 250, 7, 0, // Skip to: 4372 +/* 2330 */ MCD_OPC_Decode, 164, 21, 220, 2, // Opcode: VUHTOH +/* 2335 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2357 +/* 2340 */ MCD_OPC_CheckPredicate, 60, 235, 7, 0, // Skip to: 4372 +/* 2345 */ MCD_OPC_CheckField, 4, 1, 0, 228, 7, 0, // Skip to: 4372 +/* 2352 */ MCD_OPC_Decode, 139, 21, 218, 2, // Opcode: VTOUIRH +/* 2357 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2379 +/* 2362 */ MCD_OPC_CheckPredicate, 60, 213, 7, 0, // Skip to: 4372 +/* 2367 */ MCD_OPC_CheckField, 4, 1, 0, 206, 7, 0, // Skip to: 4372 +/* 2374 */ MCD_OPC_Decode, 255, 20, 218, 2, // Opcode: VTOSIRH +/* 2379 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2401 +/* 2384 */ MCD_OPC_CheckPredicate, 60, 191, 7, 0, // Skip to: 4372 +/* 2389 */ MCD_OPC_CheckField, 4, 1, 0, 184, 7, 0, // Skip to: 4372 +/* 2396 */ MCD_OPC_Decode, 252, 20, 220, 2, // Opcode: VTOSHH +/* 2401 */ MCD_OPC_FilterValue, 15, 174, 7, 0, // Skip to: 4372 +/* 2406 */ MCD_OPC_CheckPredicate, 60, 169, 7, 0, // Skip to: 4372 +/* 2411 */ MCD_OPC_CheckField, 4, 1, 0, 162, 7, 0, // Skip to: 4372 +/* 2418 */ MCD_OPC_Decode, 136, 21, 220, 2, // Opcode: VTOUHH +/* 2423 */ MCD_OPC_FilterValue, 39, 11, 1, 0, // Skip to: 2695 +/* 2428 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 2431 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2453 +/* 2436 */ MCD_OPC_CheckPredicate, 60, 139, 7, 0, // Skip to: 4372 +/* 2441 */ MCD_OPC_CheckField, 4, 1, 0, 132, 7, 0, // Skip to: 4372 +/* 2448 */ MCD_OPC_Decode, 215, 7, 218, 2, // Opcode: VABSH +/* 2453 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2475 +/* 2458 */ MCD_OPC_CheckPredicate, 60, 117, 7, 0, // Skip to: 4372 +/* 2463 */ MCD_OPC_CheckField, 4, 1, 0, 110, 7, 0, // Skip to: 4372 +/* 2470 */ MCD_OPC_Decode, 189, 18, 218, 2, // Opcode: VSQRTH +/* 2475 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2497 +/* 2480 */ MCD_OPC_CheckPredicate, 60, 95, 7, 0, // Skip to: 4372 +/* 2485 */ MCD_OPC_CheckField, 4, 1, 0, 88, 7, 0, // Skip to: 4372 +/* 2492 */ MCD_OPC_Decode, 141, 9, 216, 2, // Opcode: VCMPEH +/* 2497 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2519 +/* 2502 */ MCD_OPC_CheckPredicate, 60, 73, 7, 0, // Skip to: 4372 +/* 2507 */ MCD_OPC_CheckField, 0, 6, 0, 66, 7, 0, // Skip to: 4372 +/* 2514 */ MCD_OPC_Decode, 144, 9, 217, 2, // Opcode: VCMPEZH +/* 2519 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2541 +/* 2524 */ MCD_OPC_CheckPredicate, 60, 51, 7, 0, // Skip to: 4372 +/* 2529 */ MCD_OPC_CheckField, 4, 1, 0, 44, 7, 0, // Skip to: 4372 +/* 2536 */ MCD_OPC_Decode, 158, 17, 218, 2, // Opcode: VRINTZH +/* 2541 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 2563 +/* 2546 */ MCD_OPC_CheckPredicate, 60, 29, 7, 0, // Skip to: 4372 +/* 2551 */ MCD_OPC_CheckField, 4, 1, 0, 22, 7, 0, // Skip to: 4372 +/* 2558 */ MCD_OPC_Decode, 175, 18, 219, 2, // Opcode: VSITOH +/* 2563 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 2585 +/* 2568 */ MCD_OPC_CheckPredicate, 60, 7, 7, 0, // Skip to: 4372 +/* 2573 */ MCD_OPC_CheckField, 4, 1, 0, 0, 7, 0, // Skip to: 4372 +/* 2580 */ MCD_OPC_Decode, 186, 18, 220, 2, // Opcode: VSLTOH +/* 2585 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 2607 +/* 2590 */ MCD_OPC_CheckPredicate, 60, 241, 6, 0, // Skip to: 4372 +/* 2595 */ MCD_OPC_CheckField, 4, 1, 0, 234, 6, 0, // Skip to: 4372 +/* 2602 */ MCD_OPC_Decode, 170, 21, 220, 2, // Opcode: VULTOH +/* 2607 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2629 +/* 2612 */ MCD_OPC_CheckPredicate, 60, 219, 6, 0, // Skip to: 4372 +/* 2617 */ MCD_OPC_CheckField, 4, 1, 0, 212, 6, 0, // Skip to: 4372 +/* 2624 */ MCD_OPC_Decode, 142, 21, 221, 2, // Opcode: VTOUIZH +/* 2629 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2651 +/* 2634 */ MCD_OPC_CheckPredicate, 60, 197, 6, 0, // Skip to: 4372 +/* 2639 */ MCD_OPC_CheckField, 4, 1, 0, 190, 6, 0, // Skip to: 4372 +/* 2646 */ MCD_OPC_Decode, 130, 21, 221, 2, // Opcode: VTOSIZH +/* 2651 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2673 +/* 2656 */ MCD_OPC_CheckPredicate, 60, 175, 6, 0, // Skip to: 4372 +/* 2661 */ MCD_OPC_CheckField, 4, 1, 0, 168, 6, 0, // Skip to: 4372 +/* 2668 */ MCD_OPC_Decode, 133, 21, 220, 2, // Opcode: VTOSLH +/* 2673 */ MCD_OPC_FilterValue, 15, 158, 6, 0, // Skip to: 4372 +/* 2678 */ MCD_OPC_CheckPredicate, 60, 153, 6, 0, // Skip to: 4372 +/* 2683 */ MCD_OPC_CheckField, 4, 1, 0, 146, 6, 0, // Skip to: 4372 +/* 2690 */ MCD_OPC_Decode, 145, 21, 220, 2, // Opcode: VTOULH +/* 2695 */ MCD_OPC_FilterValue, 40, 20, 1, 0, // Skip to: 2976 +/* 2700 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... +/* 2703 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2718 +/* 2708 */ MCD_OPC_CheckPredicate, 65, 123, 6, 0, // Skip to: 4372 +/* 2713 */ MCD_OPC_Decode, 210, 4, 222, 2, // Opcode: FCONSTS +/* 2718 */ MCD_OPC_FilterValue, 1, 113, 6, 0, // Skip to: 4372 +/* 2723 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 2726 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2755 +/* 2731 */ MCD_OPC_CheckPredicate, 27, 100, 6, 0, // Skip to: 4372 +/* 2736 */ MCD_OPC_CheckField, 22, 1, 1, 93, 6, 0, // Skip to: 4372 +/* 2743 */ MCD_OPC_CheckField, 0, 4, 0, 86, 6, 0, // Skip to: 4372 +/* 2750 */ MCD_OPC_Decode, 170, 14, 214, 2, // Opcode: VMRS_FPSID +/* 2755 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 2802 +/* 2760 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... +/* 2763 */ MCD_OPC_FilterValue, 0, 68, 6, 0, // Skip to: 4372 +/* 2768 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2771 */ MCD_OPC_FilterValue, 1, 60, 6, 0, // Skip to: 4372 +/* 2776 */ MCD_OPC_CheckPredicate, 27, 11, 0, 0, // Skip to: 2792 +/* 2781 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 2792 +/* 2788 */ MCD_OPC_Decode, 214, 4, 29, // Opcode: FMSTAT +/* 2792 */ MCD_OPC_CheckPredicate, 27, 39, 6, 0, // Skip to: 4372 +/* 2797 */ MCD_OPC_Decode, 166, 14, 214, 2, // Opcode: VMRS +/* 2802 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 2831 +/* 2807 */ MCD_OPC_CheckPredicate, 66, 24, 6, 0, // Skip to: 4372 +/* 2812 */ MCD_OPC_CheckField, 22, 1, 1, 17, 6, 0, // Skip to: 4372 +/* 2819 */ MCD_OPC_CheckField, 0, 4, 0, 10, 6, 0, // Skip to: 4372 +/* 2826 */ MCD_OPC_Decode, 173, 14, 214, 2, // Opcode: VMRS_MVFR2 +/* 2831 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 2860 +/* 2836 */ MCD_OPC_CheckPredicate, 27, 251, 5, 0, // Skip to: 4372 +/* 2841 */ MCD_OPC_CheckField, 22, 1, 1, 244, 5, 0, // Skip to: 4372 +/* 2848 */ MCD_OPC_CheckField, 0, 4, 0, 237, 5, 0, // Skip to: 4372 +/* 2855 */ MCD_OPC_Decode, 172, 14, 214, 2, // Opcode: VMRS_MVFR1 +/* 2860 */ MCD_OPC_FilterValue, 7, 24, 0, 0, // Skip to: 2889 +/* 2865 */ MCD_OPC_CheckPredicate, 27, 222, 5, 0, // Skip to: 4372 +/* 2870 */ MCD_OPC_CheckField, 22, 1, 1, 215, 5, 0, // Skip to: 4372 +/* 2877 */ MCD_OPC_CheckField, 0, 4, 0, 208, 5, 0, // Skip to: 4372 +/* 2884 */ MCD_OPC_Decode, 171, 14, 214, 2, // Opcode: VMRS_MVFR0 +/* 2889 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 2918 +/* 2894 */ MCD_OPC_CheckPredicate, 27, 193, 5, 0, // Skip to: 4372 +/* 2899 */ MCD_OPC_CheckField, 22, 1, 1, 186, 5, 0, // Skip to: 4372 +/* 2906 */ MCD_OPC_CheckField, 0, 4, 0, 179, 5, 0, // Skip to: 4372 +/* 2913 */ MCD_OPC_Decode, 167, 14, 214, 2, // Opcode: VMRS_FPEXC +/* 2918 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 2947 +/* 2923 */ MCD_OPC_CheckPredicate, 27, 164, 5, 0, // Skip to: 4372 +/* 2928 */ MCD_OPC_CheckField, 22, 1, 1, 157, 5, 0, // Skip to: 4372 +/* 2935 */ MCD_OPC_CheckField, 0, 4, 0, 150, 5, 0, // Skip to: 4372 +/* 2942 */ MCD_OPC_Decode, 168, 14, 214, 2, // Opcode: VMRS_FPINST +/* 2947 */ MCD_OPC_FilterValue, 10, 140, 5, 0, // Skip to: 4372 +/* 2952 */ MCD_OPC_CheckPredicate, 27, 135, 5, 0, // Skip to: 4372 +/* 2957 */ MCD_OPC_CheckField, 22, 1, 1, 128, 5, 0, // Skip to: 4372 +/* 2964 */ MCD_OPC_CheckField, 0, 4, 0, 121, 5, 0, // Skip to: 4372 +/* 2971 */ MCD_OPC_Decode, 169, 14, 214, 2, // Opcode: VMRS_FPINST2 +/* 2976 */ MCD_OPC_FilterValue, 41, 77, 1, 0, // Skip to: 3314 +/* 2981 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 2984 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3006 +/* 2989 */ MCD_OPC_CheckPredicate, 27, 98, 5, 0, // Skip to: 4372 +/* 2994 */ MCD_OPC_CheckField, 4, 1, 0, 91, 5, 0, // Skip to: 4372 +/* 3001 */ MCD_OPC_Decode, 153, 14, 218, 2, // Opcode: VMOVS +/* 3006 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3028 +/* 3011 */ MCD_OPC_CheckPredicate, 27, 76, 5, 0, // Skip to: 4372 +/* 3016 */ MCD_OPC_CheckField, 4, 1, 0, 69, 5, 0, // Skip to: 4372 +/* 3023 */ MCD_OPC_Decode, 222, 14, 218, 2, // Opcode: VNEGS +/* 3028 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3050 +/* 3033 */ MCD_OPC_CheckPredicate, 67, 54, 5, 0, // Skip to: 4372 +/* 3038 */ MCD_OPC_CheckField, 4, 1, 0, 47, 5, 0, // Skip to: 4372 +/* 3045 */ MCD_OPC_Decode, 169, 9, 218, 2, // Opcode: VCVTBHS +/* 3050 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3072 +/* 3055 */ MCD_OPC_CheckPredicate, 67, 32, 5, 0, // Skip to: 4372 +/* 3060 */ MCD_OPC_CheckField, 4, 1, 0, 25, 5, 0, // Skip to: 4372 +/* 3067 */ MCD_OPC_Decode, 170, 9, 218, 2, // Opcode: VCVTBSH +/* 3072 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3094 +/* 3077 */ MCD_OPC_CheckPredicate, 27, 10, 5, 0, // Skip to: 4372 +/* 3082 */ MCD_OPC_CheckField, 4, 1, 0, 3, 5, 0, // Skip to: 4372 +/* 3089 */ MCD_OPC_Decode, 147, 9, 218, 2, // Opcode: VCMPS +/* 3094 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3116 +/* 3099 */ MCD_OPC_CheckPredicate, 27, 244, 4, 0, // Skip to: 4372 +/* 3104 */ MCD_OPC_CheckField, 0, 6, 0, 237, 4, 0, // Skip to: 4372 +/* 3111 */ MCD_OPC_Decode, 150, 9, 223, 2, // Opcode: VCMPZS +/* 3116 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3138 +/* 3121 */ MCD_OPC_CheckPredicate, 66, 222, 4, 0, // Skip to: 4372 +/* 3126 */ MCD_OPC_CheckField, 4, 1, 0, 215, 4, 0, // Skip to: 4372 +/* 3133 */ MCD_OPC_Decode, 149, 17, 218, 2, // Opcode: VRINTRS +/* 3138 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3160 +/* 3143 */ MCD_OPC_CheckPredicate, 66, 200, 4, 0, // Skip to: 4372 +/* 3148 */ MCD_OPC_CheckField, 4, 1, 0, 193, 4, 0, // Skip to: 4372 +/* 3155 */ MCD_OPC_Decode, 156, 17, 218, 2, // Opcode: VRINTXS +/* 3160 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3182 +/* 3165 */ MCD_OPC_CheckPredicate, 27, 178, 4, 0, // Skip to: 4372 +/* 3170 */ MCD_OPC_CheckField, 4, 1, 0, 171, 4, 0, // Skip to: 4372 +/* 3177 */ MCD_OPC_Decode, 168, 21, 218, 2, // Opcode: VUITOS +/* 3182 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3204 +/* 3187 */ MCD_OPC_CheckPredicate, 27, 156, 4, 0, // Skip to: 4372 +/* 3192 */ MCD_OPC_CheckField, 4, 1, 0, 149, 4, 0, // Skip to: 4372 +/* 3199 */ MCD_OPC_Decode, 173, 18, 220, 2, // Opcode: VSHTOS +/* 3204 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3226 +/* 3209 */ MCD_OPC_CheckPredicate, 27, 134, 4, 0, // Skip to: 4372 +/* 3214 */ MCD_OPC_CheckField, 4, 1, 0, 127, 4, 0, // Skip to: 4372 +/* 3221 */ MCD_OPC_Decode, 165, 21, 220, 2, // Opcode: VUHTOS +/* 3226 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3248 +/* 3231 */ MCD_OPC_CheckPredicate, 27, 112, 4, 0, // Skip to: 4372 +/* 3236 */ MCD_OPC_CheckField, 4, 1, 0, 105, 4, 0, // Skip to: 4372 +/* 3243 */ MCD_OPC_Decode, 140, 21, 218, 2, // Opcode: VTOUIRS +/* 3248 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3270 +/* 3253 */ MCD_OPC_CheckPredicate, 27, 90, 4, 0, // Skip to: 4372 +/* 3258 */ MCD_OPC_CheckField, 4, 1, 0, 83, 4, 0, // Skip to: 4372 +/* 3265 */ MCD_OPC_Decode, 128, 21, 218, 2, // Opcode: VTOSIRS +/* 3270 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3292 +/* 3275 */ MCD_OPC_CheckPredicate, 27, 68, 4, 0, // Skip to: 4372 +/* 3280 */ MCD_OPC_CheckField, 4, 1, 0, 61, 4, 0, // Skip to: 4372 +/* 3287 */ MCD_OPC_Decode, 253, 20, 220, 2, // Opcode: VTOSHS +/* 3292 */ MCD_OPC_FilterValue, 15, 51, 4, 0, // Skip to: 4372 +/* 3297 */ MCD_OPC_CheckPredicate, 27, 46, 4, 0, // Skip to: 4372 +/* 3302 */ MCD_OPC_CheckField, 4, 1, 0, 39, 4, 0, // Skip to: 4372 +/* 3309 */ MCD_OPC_Decode, 137, 21, 220, 2, // Opcode: VTOUHS +/* 3314 */ MCD_OPC_FilterValue, 43, 77, 1, 0, // Skip to: 3652 +/* 3319 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 3322 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3344 +/* 3327 */ MCD_OPC_CheckPredicate, 27, 16, 4, 0, // Skip to: 4372 +/* 3332 */ MCD_OPC_CheckField, 4, 1, 0, 9, 4, 0, // Skip to: 4372 +/* 3339 */ MCD_OPC_Decode, 216, 7, 218, 2, // Opcode: VABSS +/* 3344 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3366 +/* 3349 */ MCD_OPC_CheckPredicate, 27, 250, 3, 0, // Skip to: 4372 +/* 3354 */ MCD_OPC_CheckField, 4, 1, 0, 243, 3, 0, // Skip to: 4372 +/* 3361 */ MCD_OPC_Decode, 190, 18, 218, 2, // Opcode: VSQRTS +/* 3366 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3388 +/* 3371 */ MCD_OPC_CheckPredicate, 67, 228, 3, 0, // Skip to: 4372 +/* 3376 */ MCD_OPC_CheckField, 4, 1, 0, 221, 3, 0, // Skip to: 4372 +/* 3383 */ MCD_OPC_Decode, 217, 9, 218, 2, // Opcode: VCVTTHS +/* 3388 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3410 +/* 3393 */ MCD_OPC_CheckPredicate, 67, 206, 3, 0, // Skip to: 4372 +/* 3398 */ MCD_OPC_CheckField, 4, 1, 0, 199, 3, 0, // Skip to: 4372 +/* 3405 */ MCD_OPC_Decode, 218, 9, 218, 2, // Opcode: VCVTTSH +/* 3410 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3432 +/* 3415 */ MCD_OPC_CheckPredicate, 27, 184, 3, 0, // Skip to: 4372 +/* 3420 */ MCD_OPC_CheckField, 4, 1, 0, 177, 3, 0, // Skip to: 4372 +/* 3427 */ MCD_OPC_Decode, 142, 9, 218, 2, // Opcode: VCMPES +/* 3432 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3454 +/* 3437 */ MCD_OPC_CheckPredicate, 27, 162, 3, 0, // Skip to: 4372 +/* 3442 */ MCD_OPC_CheckField, 0, 6, 0, 155, 3, 0, // Skip to: 4372 +/* 3449 */ MCD_OPC_Decode, 145, 9, 223, 2, // Opcode: VCMPEZS +/* 3454 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3476 +/* 3459 */ MCD_OPC_CheckPredicate, 66, 140, 3, 0, // Skip to: 4372 +/* 3464 */ MCD_OPC_CheckField, 4, 1, 0, 133, 3, 0, // Skip to: 4372 +/* 3471 */ MCD_OPC_Decode, 163, 17, 218, 2, // Opcode: VRINTZS +/* 3476 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3498 +/* 3481 */ MCD_OPC_CheckPredicate, 61, 118, 3, 0, // Skip to: 4372 +/* 3486 */ MCD_OPC_CheckField, 4, 1, 0, 111, 3, 0, // Skip to: 4372 +/* 3493 */ MCD_OPC_Decode, 171, 9, 224, 2, // Opcode: VCVTDS +/* 3498 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3520 +/* 3503 */ MCD_OPC_CheckPredicate, 27, 96, 3, 0, // Skip to: 4372 +/* 3508 */ MCD_OPC_CheckField, 4, 1, 0, 89, 3, 0, // Skip to: 4372 +/* 3515 */ MCD_OPC_Decode, 176, 18, 218, 2, // Opcode: VSITOS +/* 3520 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3542 +/* 3525 */ MCD_OPC_CheckPredicate, 27, 74, 3, 0, // Skip to: 4372 +/* 3530 */ MCD_OPC_CheckField, 4, 1, 0, 67, 3, 0, // Skip to: 4372 +/* 3537 */ MCD_OPC_Decode, 187, 18, 220, 2, // Opcode: VSLTOS +/* 3542 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3564 +/* 3547 */ MCD_OPC_CheckPredicate, 27, 52, 3, 0, // Skip to: 4372 +/* 3552 */ MCD_OPC_CheckField, 4, 1, 0, 45, 3, 0, // Skip to: 4372 +/* 3559 */ MCD_OPC_Decode, 171, 21, 220, 2, // Opcode: VULTOS +/* 3564 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3586 +/* 3569 */ MCD_OPC_CheckPredicate, 27, 30, 3, 0, // Skip to: 4372 +/* 3574 */ MCD_OPC_CheckField, 4, 1, 0, 23, 3, 0, // Skip to: 4372 +/* 3581 */ MCD_OPC_Decode, 143, 21, 218, 2, // Opcode: VTOUIZS +/* 3586 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3608 +/* 3591 */ MCD_OPC_CheckPredicate, 27, 8, 3, 0, // Skip to: 4372 +/* 3596 */ MCD_OPC_CheckField, 4, 1, 0, 1, 3, 0, // Skip to: 4372 +/* 3603 */ MCD_OPC_Decode, 131, 21, 218, 2, // Opcode: VTOSIZS +/* 3608 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3630 +/* 3613 */ MCD_OPC_CheckPredicate, 27, 242, 2, 0, // Skip to: 4372 +/* 3618 */ MCD_OPC_CheckField, 4, 1, 0, 235, 2, 0, // Skip to: 4372 +/* 3625 */ MCD_OPC_Decode, 134, 21, 220, 2, // Opcode: VTOSLS +/* 3630 */ MCD_OPC_FilterValue, 15, 225, 2, 0, // Skip to: 4372 +/* 3635 */ MCD_OPC_CheckPredicate, 27, 220, 2, 0, // Skip to: 4372 +/* 3640 */ MCD_OPC_CheckField, 4, 1, 0, 213, 2, 0, // Skip to: 4372 +/* 3647 */ MCD_OPC_Decode, 146, 21, 220, 2, // Opcode: VTOULS +/* 3652 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 3674 +/* 3657 */ MCD_OPC_CheckPredicate, 68, 198, 2, 0, // Skip to: 4372 +/* 3662 */ MCD_OPC_CheckField, 4, 2, 0, 191, 2, 0, // Skip to: 4372 +/* 3669 */ MCD_OPC_Decode, 208, 4, 225, 2, // Opcode: FCONSTD +/* 3674 */ MCD_OPC_FilterValue, 45, 77, 1, 0, // Skip to: 4012 +/* 3679 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 3682 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3704 +/* 3687 */ MCD_OPC_CheckPredicate, 61, 168, 2, 0, // Skip to: 4372 +/* 3692 */ MCD_OPC_CheckField, 4, 1, 0, 161, 2, 0, // Skip to: 4372 +/* 3699 */ MCD_OPC_Decode, 136, 14, 226, 2, // Opcode: VMOVD +/* 3704 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3726 +/* 3709 */ MCD_OPC_CheckPredicate, 61, 146, 2, 0, // Skip to: 4372 +/* 3714 */ MCD_OPC_CheckField, 4, 1, 0, 139, 2, 0, // Skip to: 4372 +/* 3721 */ MCD_OPC_Decode, 220, 14, 226, 2, // Opcode: VNEGD +/* 3726 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3748 +/* 3731 */ MCD_OPC_CheckPredicate, 69, 124, 2, 0, // Skip to: 4372 +/* 3736 */ MCD_OPC_CheckField, 4, 1, 0, 117, 2, 0, // Skip to: 4372 +/* 3743 */ MCD_OPC_Decode, 168, 9, 224, 2, // Opcode: VCVTBHD +/* 3748 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3770 +/* 3753 */ MCD_OPC_CheckPredicate, 69, 102, 2, 0, // Skip to: 4372 +/* 3758 */ MCD_OPC_CheckField, 4, 1, 0, 95, 2, 0, // Skip to: 4372 +/* 3765 */ MCD_OPC_Decode, 167, 9, 227, 2, // Opcode: VCVTBDH +/* 3770 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3792 +/* 3775 */ MCD_OPC_CheckPredicate, 61, 80, 2, 0, // Skip to: 4372 +/* 3780 */ MCD_OPC_CheckField, 4, 1, 0, 73, 2, 0, // Skip to: 4372 +/* 3787 */ MCD_OPC_Decode, 139, 9, 226, 2, // Opcode: VCMPD +/* 3792 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3814 +/* 3797 */ MCD_OPC_CheckPredicate, 61, 58, 2, 0, // Skip to: 4372 +/* 3802 */ MCD_OPC_CheckField, 0, 6, 0, 51, 2, 0, // Skip to: 4372 +/* 3809 */ MCD_OPC_Decode, 148, 9, 228, 2, // Opcode: VCMPZD +/* 3814 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3836 +/* 3819 */ MCD_OPC_CheckPredicate, 69, 36, 2, 0, // Skip to: 4372 +/* 3824 */ MCD_OPC_CheckField, 4, 1, 0, 29, 2, 0, // Skip to: 4372 +/* 3831 */ MCD_OPC_Decode, 147, 17, 226, 2, // Opcode: VRINTRD +/* 3836 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3858 +/* 3841 */ MCD_OPC_CheckPredicate, 69, 14, 2, 0, // Skip to: 4372 +/* 3846 */ MCD_OPC_CheckField, 4, 1, 0, 7, 2, 0, // Skip to: 4372 +/* 3853 */ MCD_OPC_Decode, 150, 17, 226, 2, // Opcode: VRINTXD +/* 3858 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3880 +/* 3863 */ MCD_OPC_CheckPredicate, 61, 248, 1, 0, // Skip to: 4372 +/* 3868 */ MCD_OPC_CheckField, 4, 1, 0, 241, 1, 0, // Skip to: 4372 +/* 3875 */ MCD_OPC_Decode, 166, 21, 224, 2, // Opcode: VUITOD +/* 3880 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3902 +/* 3885 */ MCD_OPC_CheckPredicate, 61, 226, 1, 0, // Skip to: 4372 +/* 3890 */ MCD_OPC_CheckField, 4, 1, 0, 219, 1, 0, // Skip to: 4372 +/* 3897 */ MCD_OPC_Decode, 171, 18, 229, 2, // Opcode: VSHTOD +/* 3902 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3924 +/* 3907 */ MCD_OPC_CheckPredicate, 61, 204, 1, 0, // Skip to: 4372 +/* 3912 */ MCD_OPC_CheckField, 4, 1, 0, 197, 1, 0, // Skip to: 4372 +/* 3919 */ MCD_OPC_Decode, 163, 21, 229, 2, // Opcode: VUHTOD +/* 3924 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3946 +/* 3929 */ MCD_OPC_CheckPredicate, 61, 182, 1, 0, // Skip to: 4372 +/* 3934 */ MCD_OPC_CheckField, 4, 1, 0, 175, 1, 0, // Skip to: 4372 +/* 3941 */ MCD_OPC_Decode, 138, 21, 227, 2, // Opcode: VTOUIRD +/* 3946 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3968 +/* 3951 */ MCD_OPC_CheckPredicate, 61, 160, 1, 0, // Skip to: 4372 +/* 3956 */ MCD_OPC_CheckField, 4, 1, 0, 153, 1, 0, // Skip to: 4372 +/* 3963 */ MCD_OPC_Decode, 254, 20, 227, 2, // Opcode: VTOSIRD +/* 3968 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3990 +/* 3973 */ MCD_OPC_CheckPredicate, 61, 138, 1, 0, // Skip to: 4372 +/* 3978 */ MCD_OPC_CheckField, 4, 1, 0, 131, 1, 0, // Skip to: 4372 +/* 3985 */ MCD_OPC_Decode, 251, 20, 229, 2, // Opcode: VTOSHD +/* 3990 */ MCD_OPC_FilterValue, 15, 121, 1, 0, // Skip to: 4372 +/* 3995 */ MCD_OPC_CheckPredicate, 61, 116, 1, 0, // Skip to: 4372 +/* 4000 */ MCD_OPC_CheckField, 4, 1, 0, 109, 1, 0, // Skip to: 4372 +/* 4007 */ MCD_OPC_Decode, 135, 21, 229, 2, // Opcode: VTOUHD +/* 4012 */ MCD_OPC_FilterValue, 47, 99, 1, 0, // Skip to: 4372 +/* 4017 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 4020 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4042 +/* 4025 */ MCD_OPC_CheckPredicate, 61, 86, 1, 0, // Skip to: 4372 +/* 4030 */ MCD_OPC_CheckField, 4, 1, 0, 79, 1, 0, // Skip to: 4372 +/* 4037 */ MCD_OPC_Decode, 214, 7, 226, 2, // Opcode: VABSD +/* 4042 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4064 +/* 4047 */ MCD_OPC_CheckPredicate, 61, 64, 1, 0, // Skip to: 4372 +/* 4052 */ MCD_OPC_CheckField, 4, 1, 0, 57, 1, 0, // Skip to: 4372 +/* 4059 */ MCD_OPC_Decode, 188, 18, 226, 2, // Opcode: VSQRTD +/* 4064 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4086 +/* 4069 */ MCD_OPC_CheckPredicate, 69, 42, 1, 0, // Skip to: 4372 +/* 4074 */ MCD_OPC_CheckField, 4, 1, 0, 35, 1, 0, // Skip to: 4372 +/* 4081 */ MCD_OPC_Decode, 216, 9, 224, 2, // Opcode: VCVTTHD +/* 4086 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 4108 +/* 4091 */ MCD_OPC_CheckPredicate, 69, 20, 1, 0, // Skip to: 4372 +/* 4096 */ MCD_OPC_CheckField, 4, 1, 0, 13, 1, 0, // Skip to: 4372 +/* 4103 */ MCD_OPC_Decode, 215, 9, 227, 2, // Opcode: VCVTTDH +/* 4108 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4130 +/* 4113 */ MCD_OPC_CheckPredicate, 61, 254, 0, 0, // Skip to: 4372 +/* 4118 */ MCD_OPC_CheckField, 4, 1, 0, 247, 0, 0, // Skip to: 4372 +/* 4125 */ MCD_OPC_Decode, 140, 9, 226, 2, // Opcode: VCMPED +/* 4130 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4152 +/* 4135 */ MCD_OPC_CheckPredicate, 61, 232, 0, 0, // Skip to: 4372 +/* 4140 */ MCD_OPC_CheckField, 0, 6, 0, 225, 0, 0, // Skip to: 4372 +/* 4147 */ MCD_OPC_Decode, 143, 9, 228, 2, // Opcode: VCMPEZD +/* 4152 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 4174 +/* 4157 */ MCD_OPC_CheckPredicate, 69, 210, 0, 0, // Skip to: 4372 +/* 4162 */ MCD_OPC_CheckField, 4, 1, 0, 203, 0, 0, // Skip to: 4372 +/* 4169 */ MCD_OPC_Decode, 157, 17, 226, 2, // Opcode: VRINTZD +/* 4174 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4196 +/* 4179 */ MCD_OPC_CheckPredicate, 61, 188, 0, 0, // Skip to: 4372 +/* 4184 */ MCD_OPC_CheckField, 4, 1, 0, 181, 0, 0, // Skip to: 4372 +/* 4191 */ MCD_OPC_Decode, 214, 9, 227, 2, // Opcode: VCVTSD +/* 4196 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4218 +/* 4201 */ MCD_OPC_CheckPredicate, 61, 166, 0, 0, // Skip to: 4372 +/* 4206 */ MCD_OPC_CheckField, 4, 1, 0, 159, 0, 0, // Skip to: 4372 +/* 4213 */ MCD_OPC_Decode, 174, 18, 224, 2, // Opcode: VSITOD +/* 4218 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4240 +/* 4223 */ MCD_OPC_CheckPredicate, 70, 144, 0, 0, // Skip to: 4372 +/* 4228 */ MCD_OPC_CheckField, 4, 1, 0, 137, 0, 0, // Skip to: 4372 +/* 4235 */ MCD_OPC_Decode, 199, 10, 227, 2, // Opcode: VJCVT +/* 4240 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4262 +/* 4245 */ MCD_OPC_CheckPredicate, 61, 122, 0, 0, // Skip to: 4372 +/* 4250 */ MCD_OPC_CheckField, 4, 1, 0, 115, 0, 0, // Skip to: 4372 +/* 4257 */ MCD_OPC_Decode, 185, 18, 229, 2, // Opcode: VSLTOD +/* 4262 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4284 +/* 4267 */ MCD_OPC_CheckPredicate, 61, 100, 0, 0, // Skip to: 4372 +/* 4272 */ MCD_OPC_CheckField, 4, 1, 0, 93, 0, 0, // Skip to: 4372 +/* 4279 */ MCD_OPC_Decode, 169, 21, 229, 2, // Opcode: VULTOD +/* 4284 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4306 +/* 4289 */ MCD_OPC_CheckPredicate, 61, 78, 0, 0, // Skip to: 4372 +/* 4294 */ MCD_OPC_CheckField, 4, 1, 0, 71, 0, 0, // Skip to: 4372 +/* 4301 */ MCD_OPC_Decode, 141, 21, 227, 2, // Opcode: VTOUIZD +/* 4306 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4328 +/* 4311 */ MCD_OPC_CheckPredicate, 61, 56, 0, 0, // Skip to: 4372 +/* 4316 */ MCD_OPC_CheckField, 4, 1, 0, 49, 0, 0, // Skip to: 4372 +/* 4323 */ MCD_OPC_Decode, 129, 21, 227, 2, // Opcode: VTOSIZD +/* 4328 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4350 +/* 4333 */ MCD_OPC_CheckPredicate, 61, 34, 0, 0, // Skip to: 4372 +/* 4338 */ MCD_OPC_CheckField, 4, 1, 0, 27, 0, 0, // Skip to: 4372 +/* 4345 */ MCD_OPC_Decode, 132, 21, 229, 2, // Opcode: VTOSLD +/* 4350 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 4372 +/* 4355 */ MCD_OPC_CheckPredicate, 61, 12, 0, 0, // Skip to: 4372 +/* 4360 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 4372 +/* 4367 */ MCD_OPC_Decode, 144, 21, 229, 2, // Opcode: VTOULD +/* 4372 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTableVFPV832[] = { +/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 3 */ MCD_OPC_FilterValue, 8, 87, 1, 0, // Skip to: 351 +/* 8 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 11 */ MCD_OPC_FilterValue, 0, 165, 0, 0, // Skip to: 181 +/* 16 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... +/* 19 */ MCD_OPC_FilterValue, 126, 105, 0, 0, // Skip to: 129 +/* 24 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 27 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 56 +/* 32 */ MCD_OPC_CheckPredicate, 71, 220, 9, 0, // Skip to: 2561 +/* 37 */ MCD_OPC_CheckField, 23, 1, 1, 213, 9, 0, // Skip to: 2561 +/* 44 */ MCD_OPC_CheckField, 4, 1, 0, 206, 9, 0, // Skip to: 2561 +/* 51 */ MCD_OPC_Decode, 152, 8, 230, 2, // Opcode: VCADDv4f16 +/* 56 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 85 +/* 61 */ MCD_OPC_CheckPredicate, 72, 191, 9, 0, // Skip to: 2561 +/* 66 */ MCD_OPC_CheckField, 23, 1, 1, 184, 9, 0, // Skip to: 2561 +/* 73 */ MCD_OPC_CheckField, 4, 1, 0, 177, 9, 0, // Skip to: 2561 +/* 80 */ MCD_OPC_Decode, 151, 8, 230, 2, // Opcode: VCADDv2f32 +/* 85 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 107 +/* 90 */ MCD_OPC_CheckPredicate, 71, 162, 9, 0, // Skip to: 2561 +/* 95 */ MCD_OPC_CheckField, 4, 1, 0, 155, 9, 0, // Skip to: 2561 +/* 102 */ MCD_OPC_Decode, 133, 9, 231, 2, // Opcode: VCMLAv4f16 +/* 107 */ MCD_OPC_FilterValue, 3, 145, 9, 0, // Skip to: 2561 +/* 112 */ MCD_OPC_CheckPredicate, 72, 140, 9, 0, // Skip to: 2561 +/* 117 */ MCD_OPC_CheckField, 4, 1, 0, 133, 9, 0, // Skip to: 2561 +/* 124 */ MCD_OPC_Decode, 131, 9, 231, 2, // Opcode: VCMLAv2f32 +/* 129 */ MCD_OPC_FilterValue, 127, 123, 9, 0, // Skip to: 2561 +/* 134 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 137 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 159 +/* 142 */ MCD_OPC_CheckPredicate, 71, 110, 9, 0, // Skip to: 2561 +/* 147 */ MCD_OPC_CheckField, 4, 1, 0, 103, 9, 0, // Skip to: 2561 +/* 154 */ MCD_OPC_Decode, 134, 9, 232, 2, // Opcode: VCMLAv4f16_indexed +/* 159 */ MCD_OPC_FilterValue, 1, 93, 9, 0, // Skip to: 2561 +/* 164 */ MCD_OPC_CheckPredicate, 72, 88, 9, 0, // Skip to: 2561 +/* 169 */ MCD_OPC_CheckField, 4, 1, 0, 81, 9, 0, // Skip to: 2561 +/* 176 */ MCD_OPC_Decode, 132, 9, 233, 2, // Opcode: VCMLAv2f32_indexed +/* 181 */ MCD_OPC_FilterValue, 1, 71, 9, 0, // Skip to: 2561 +/* 186 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... +/* 189 */ MCD_OPC_FilterValue, 126, 105, 0, 0, // Skip to: 299 +/* 194 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 197 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 226 +/* 202 */ MCD_OPC_CheckPredicate, 71, 50, 9, 0, // Skip to: 2561 +/* 207 */ MCD_OPC_CheckField, 23, 1, 1, 43, 9, 0, // Skip to: 2561 +/* 214 */ MCD_OPC_CheckField, 4, 1, 0, 36, 9, 0, // Skip to: 2561 +/* 221 */ MCD_OPC_Decode, 154, 8, 234, 2, // Opcode: VCADDv8f16 +/* 226 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 255 +/* 231 */ MCD_OPC_CheckPredicate, 72, 21, 9, 0, // Skip to: 2561 +/* 236 */ MCD_OPC_CheckField, 23, 1, 1, 14, 9, 0, // Skip to: 2561 +/* 243 */ MCD_OPC_CheckField, 4, 1, 0, 7, 9, 0, // Skip to: 2561 +/* 250 */ MCD_OPC_Decode, 153, 8, 234, 2, // Opcode: VCADDv4f32 +/* 255 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 277 +/* 260 */ MCD_OPC_CheckPredicate, 71, 248, 8, 0, // Skip to: 2561 +/* 265 */ MCD_OPC_CheckField, 4, 1, 0, 241, 8, 0, // Skip to: 2561 +/* 272 */ MCD_OPC_Decode, 137, 9, 235, 2, // Opcode: VCMLAv8f16 +/* 277 */ MCD_OPC_FilterValue, 3, 231, 8, 0, // Skip to: 2561 +/* 282 */ MCD_OPC_CheckPredicate, 72, 226, 8, 0, // Skip to: 2561 +/* 287 */ MCD_OPC_CheckField, 4, 1, 0, 219, 8, 0, // Skip to: 2561 +/* 294 */ MCD_OPC_Decode, 135, 9, 235, 2, // Opcode: VCMLAv4f32 +/* 299 */ MCD_OPC_FilterValue, 127, 209, 8, 0, // Skip to: 2561 +/* 304 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... +/* 307 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 329 +/* 312 */ MCD_OPC_CheckPredicate, 71, 196, 8, 0, // Skip to: 2561 +/* 317 */ MCD_OPC_CheckField, 4, 1, 0, 189, 8, 0, // Skip to: 2561 +/* 324 */ MCD_OPC_Decode, 138, 9, 236, 2, // Opcode: VCMLAv8f16_indexed +/* 329 */ MCD_OPC_FilterValue, 1, 179, 8, 0, // Skip to: 2561 +/* 334 */ MCD_OPC_CheckPredicate, 72, 174, 8, 0, // Skip to: 2561 +/* 339 */ MCD_OPC_CheckField, 4, 1, 0, 167, 8, 0, // Skip to: 2561 +/* 346 */ MCD_OPC_Decode, 136, 9, 233, 2, // Opcode: VCMLAv4f32_indexed +/* 351 */ MCD_OPC_FilterValue, 9, 123, 2, 0, // Skip to: 991 +/* 356 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 359 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 451 +/* 364 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 367 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 421 +/* 372 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 375 */ MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 398 +/* 381 */ MCD_OPC_CheckPredicate, 60, 127, 8, 0, // Skip to: 2561 +/* 386 */ MCD_OPC_CheckField, 4, 1, 0, 120, 8, 0, // Skip to: 2561 +/* 393 */ MCD_OPC_Decode, 233, 17, 237, 2, // Opcode: VSELEQH +/* 398 */ MCD_OPC_FilterValue, 253, 3, 109, 8, 0, // Skip to: 2561 +/* 404 */ MCD_OPC_CheckPredicate, 60, 104, 8, 0, // Skip to: 2561 +/* 409 */ MCD_OPC_CheckField, 4, 1, 0, 97, 8, 0, // Skip to: 2561 +/* 416 */ MCD_OPC_Decode, 157, 13, 237, 2, // Opcode: VMAXNMH +/* 421 */ MCD_OPC_FilterValue, 1, 87, 8, 0, // Skip to: 2561 +/* 426 */ MCD_OPC_CheckPredicate, 60, 82, 8, 0, // Skip to: 2561 +/* 431 */ MCD_OPC_CheckField, 23, 9, 253, 3, 74, 8, 0, // Skip to: 2561 +/* 439 */ MCD_OPC_CheckField, 4, 1, 0, 67, 8, 0, // Skip to: 2561 +/* 446 */ MCD_OPC_Decode, 180, 13, 237, 2, // Opcode: VMINNMH +/* 451 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 488 +/* 456 */ MCD_OPC_CheckPredicate, 60, 52, 8, 0, // Skip to: 2561 +/* 461 */ MCD_OPC_CheckField, 23, 9, 252, 3, 44, 8, 0, // Skip to: 2561 +/* 469 */ MCD_OPC_CheckField, 6, 1, 0, 37, 8, 0, // Skip to: 2561 +/* 476 */ MCD_OPC_CheckField, 4, 1, 0, 30, 8, 0, // Skip to: 2561 +/* 483 */ MCD_OPC_Decode, 242, 17, 237, 2, // Opcode: VSELVSH +/* 488 */ MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 525 +/* 493 */ MCD_OPC_CheckPredicate, 60, 15, 8, 0, // Skip to: 2561 +/* 498 */ MCD_OPC_CheckField, 23, 9, 252, 3, 7, 8, 0, // Skip to: 2561 +/* 506 */ MCD_OPC_CheckField, 6, 1, 0, 0, 8, 0, // Skip to: 2561 +/* 513 */ MCD_OPC_CheckField, 4, 1, 0, 249, 7, 0, // Skip to: 2561 +/* 520 */ MCD_OPC_Decode, 236, 17, 237, 2, // Opcode: VSELGEH +/* 525 */ MCD_OPC_FilterValue, 3, 239, 7, 0, // Skip to: 2561 +/* 530 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 533 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 563 +/* 538 */ MCD_OPC_CheckPredicate, 60, 226, 7, 0, // Skip to: 2561 +/* 543 */ MCD_OPC_CheckField, 23, 9, 252, 3, 218, 7, 0, // Skip to: 2561 +/* 551 */ MCD_OPC_CheckField, 4, 1, 0, 211, 7, 0, // Skip to: 2561 +/* 558 */ MCD_OPC_Decode, 239, 17, 237, 2, // Opcode: VSELGTH +/* 563 */ MCD_OPC_FilterValue, 1, 201, 7, 0, // Skip to: 2561 +/* 568 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 571 */ MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 608 +/* 576 */ MCD_OPC_CheckPredicate, 60, 188, 7, 0, // Skip to: 2561 +/* 581 */ MCD_OPC_CheckField, 23, 9, 253, 3, 180, 7, 0, // Skip to: 2561 +/* 589 */ MCD_OPC_CheckField, 7, 1, 0, 173, 7, 0, // Skip to: 2561 +/* 596 */ MCD_OPC_CheckField, 4, 1, 0, 166, 7, 0, // Skip to: 2561 +/* 603 */ MCD_OPC_Decode, 248, 16, 238, 2, // Opcode: VRINTAH +/* 608 */ MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 645 +/* 613 */ MCD_OPC_CheckPredicate, 60, 151, 7, 0, // Skip to: 2561 +/* 618 */ MCD_OPC_CheckField, 23, 9, 253, 3, 143, 7, 0, // Skip to: 2561 +/* 626 */ MCD_OPC_CheckField, 7, 1, 0, 136, 7, 0, // Skip to: 2561 +/* 633 */ MCD_OPC_CheckField, 4, 1, 0, 129, 7, 0, // Skip to: 2561 +/* 640 */ MCD_OPC_Decode, 134, 17, 238, 2, // Opcode: VRINTNH +/* 645 */ MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 682 +/* 650 */ MCD_OPC_CheckPredicate, 60, 114, 7, 0, // Skip to: 2561 +/* 655 */ MCD_OPC_CheckField, 23, 9, 253, 3, 106, 7, 0, // Skip to: 2561 +/* 663 */ MCD_OPC_CheckField, 7, 1, 0, 99, 7, 0, // Skip to: 2561 +/* 670 */ MCD_OPC_CheckField, 4, 1, 0, 92, 7, 0, // Skip to: 2561 +/* 677 */ MCD_OPC_Decode, 141, 17, 238, 2, // Opcode: VRINTPH +/* 682 */ MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 719 +/* 687 */ MCD_OPC_CheckPredicate, 60, 77, 7, 0, // Skip to: 2561 +/* 692 */ MCD_OPC_CheckField, 23, 9, 253, 3, 69, 7, 0, // Skip to: 2561 +/* 700 */ MCD_OPC_CheckField, 7, 1, 0, 62, 7, 0, // Skip to: 2561 +/* 707 */ MCD_OPC_CheckField, 4, 1, 0, 55, 7, 0, // Skip to: 2561 +/* 714 */ MCD_OPC_Decode, 255, 16, 238, 2, // Opcode: VRINTMH +/* 719 */ MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 787 +/* 724 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 727 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 757 +/* 732 */ MCD_OPC_CheckPredicate, 60, 32, 7, 0, // Skip to: 2561 +/* 737 */ MCD_OPC_CheckField, 23, 9, 253, 3, 24, 7, 0, // Skip to: 2561 +/* 745 */ MCD_OPC_CheckField, 4, 1, 0, 17, 7, 0, // Skip to: 2561 +/* 752 */ MCD_OPC_Decode, 165, 9, 239, 2, // Opcode: VCVTAUH +/* 757 */ MCD_OPC_FilterValue, 1, 7, 7, 0, // Skip to: 2561 +/* 762 */ MCD_OPC_CheckPredicate, 60, 2, 7, 0, // Skip to: 2561 +/* 767 */ MCD_OPC_CheckField, 23, 9, 253, 3, 250, 6, 0, // Skip to: 2561 +/* 775 */ MCD_OPC_CheckField, 4, 1, 0, 243, 6, 0, // Skip to: 2561 +/* 782 */ MCD_OPC_Decode, 162, 9, 239, 2, // Opcode: VCVTASH +/* 787 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 855 +/* 792 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 795 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 825 +/* 800 */ MCD_OPC_CheckPredicate, 60, 220, 6, 0, // Skip to: 2561 +/* 805 */ MCD_OPC_CheckField, 23, 9, 253, 3, 212, 6, 0, // Skip to: 2561 +/* 813 */ MCD_OPC_CheckField, 4, 1, 0, 205, 6, 0, // Skip to: 2561 +/* 820 */ MCD_OPC_Decode, 198, 9, 239, 2, // Opcode: VCVTNUH +/* 825 */ MCD_OPC_FilterValue, 1, 195, 6, 0, // Skip to: 2561 +/* 830 */ MCD_OPC_CheckPredicate, 60, 190, 6, 0, // Skip to: 2561 +/* 835 */ MCD_OPC_CheckField, 23, 9, 253, 3, 182, 6, 0, // Skip to: 2561 +/* 843 */ MCD_OPC_CheckField, 4, 1, 0, 175, 6, 0, // Skip to: 2561 +/* 850 */ MCD_OPC_Decode, 195, 9, 239, 2, // Opcode: VCVTNSH +/* 855 */ MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 923 +/* 860 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 863 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 893 +/* 868 */ MCD_OPC_CheckPredicate, 60, 152, 6, 0, // Skip to: 2561 +/* 873 */ MCD_OPC_CheckField, 23, 9, 253, 3, 144, 6, 0, // Skip to: 2561 +/* 881 */ MCD_OPC_CheckField, 4, 1, 0, 137, 6, 0, // Skip to: 2561 +/* 888 */ MCD_OPC_Decode, 212, 9, 239, 2, // Opcode: VCVTPUH +/* 893 */ MCD_OPC_FilterValue, 1, 127, 6, 0, // Skip to: 2561 +/* 898 */ MCD_OPC_CheckPredicate, 60, 122, 6, 0, // Skip to: 2561 +/* 903 */ MCD_OPC_CheckField, 23, 9, 253, 3, 114, 6, 0, // Skip to: 2561 +/* 911 */ MCD_OPC_CheckField, 4, 1, 0, 107, 6, 0, // Skip to: 2561 +/* 918 */ MCD_OPC_Decode, 209, 9, 239, 2, // Opcode: VCVTPSH +/* 923 */ MCD_OPC_FilterValue, 15, 97, 6, 0, // Skip to: 2561 +/* 928 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 931 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 961 +/* 936 */ MCD_OPC_CheckPredicate, 60, 84, 6, 0, // Skip to: 2561 +/* 941 */ MCD_OPC_CheckField, 23, 9, 253, 3, 76, 6, 0, // Skip to: 2561 +/* 949 */ MCD_OPC_CheckField, 4, 1, 0, 69, 6, 0, // Skip to: 2561 +/* 956 */ MCD_OPC_Decode, 184, 9, 239, 2, // Opcode: VCVTMUH +/* 961 */ MCD_OPC_FilterValue, 1, 59, 6, 0, // Skip to: 2561 +/* 966 */ MCD_OPC_CheckPredicate, 60, 54, 6, 0, // Skip to: 2561 +/* 971 */ MCD_OPC_CheckField, 23, 9, 253, 3, 46, 6, 0, // Skip to: 2561 +/* 979 */ MCD_OPC_CheckField, 4, 1, 0, 39, 6, 0, // Skip to: 2561 +/* 986 */ MCD_OPC_Decode, 181, 9, 239, 2, // Opcode: VCVTMSH +/* 991 */ MCD_OPC_FilterValue, 10, 191, 2, 0, // Skip to: 1699 +/* 996 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 999 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 1091 +/* 1004 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1007 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 1061 +/* 1012 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1015 */ MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 1038 +/* 1021 */ MCD_OPC_CheckPredicate, 66, 255, 5, 0, // Skip to: 2561 +/* 1026 */ MCD_OPC_CheckField, 4, 1, 0, 248, 5, 0, // Skip to: 2561 +/* 1033 */ MCD_OPC_Decode, 234, 17, 240, 2, // Opcode: VSELEQS +/* 1038 */ MCD_OPC_FilterValue, 253, 3, 237, 5, 0, // Skip to: 2561 +/* 1044 */ MCD_OPC_CheckPredicate, 66, 232, 5, 0, // Skip to: 2561 +/* 1049 */ MCD_OPC_CheckField, 4, 1, 0, 225, 5, 0, // Skip to: 2561 +/* 1056 */ MCD_OPC_Decode, 162, 13, 240, 2, // Opcode: VMAXNMS +/* 1061 */ MCD_OPC_FilterValue, 1, 215, 5, 0, // Skip to: 2561 +/* 1066 */ MCD_OPC_CheckPredicate, 66, 210, 5, 0, // Skip to: 2561 +/* 1071 */ MCD_OPC_CheckField, 23, 9, 253, 3, 202, 5, 0, // Skip to: 2561 +/* 1079 */ MCD_OPC_CheckField, 4, 1, 0, 195, 5, 0, // Skip to: 2561 +/* 1086 */ MCD_OPC_Decode, 185, 13, 240, 2, // Opcode: VMINNMS +/* 1091 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 1128 +/* 1096 */ MCD_OPC_CheckPredicate, 66, 180, 5, 0, // Skip to: 2561 +/* 1101 */ MCD_OPC_CheckField, 23, 9, 252, 3, 172, 5, 0, // Skip to: 2561 +/* 1109 */ MCD_OPC_CheckField, 6, 1, 0, 165, 5, 0, // Skip to: 2561 +/* 1116 */ MCD_OPC_CheckField, 4, 1, 0, 158, 5, 0, // Skip to: 2561 +/* 1123 */ MCD_OPC_Decode, 243, 17, 240, 2, // Opcode: VSELVSS +/* 1128 */ MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 1165 +/* 1133 */ MCD_OPC_CheckPredicate, 66, 143, 5, 0, // Skip to: 2561 +/* 1138 */ MCD_OPC_CheckField, 23, 9, 252, 3, 135, 5, 0, // Skip to: 2561 +/* 1146 */ MCD_OPC_CheckField, 6, 1, 0, 128, 5, 0, // Skip to: 2561 +/* 1153 */ MCD_OPC_CheckField, 4, 1, 0, 121, 5, 0, // Skip to: 2561 +/* 1160 */ MCD_OPC_Decode, 237, 17, 240, 2, // Opcode: VSELGES +/* 1165 */ MCD_OPC_FilterValue, 3, 111, 5, 0, // Skip to: 2561 +/* 1170 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1173 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1203 +/* 1178 */ MCD_OPC_CheckPredicate, 66, 98, 5, 0, // Skip to: 2561 +/* 1183 */ MCD_OPC_CheckField, 23, 9, 252, 3, 90, 5, 0, // Skip to: 2561 +/* 1191 */ MCD_OPC_CheckField, 4, 1, 0, 83, 5, 0, // Skip to: 2561 +/* 1198 */ MCD_OPC_Decode, 240, 17, 240, 2, // Opcode: VSELGTS +/* 1203 */ MCD_OPC_FilterValue, 1, 73, 5, 0, // Skip to: 2561 +/* 1208 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 1211 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 1279 +/* 1216 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 1219 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1249 +/* 1224 */ MCD_OPC_CheckPredicate, 60, 52, 5, 0, // Skip to: 2561 +/* 1229 */ MCD_OPC_CheckField, 23, 9, 253, 3, 44, 5, 0, // Skip to: 2561 +/* 1237 */ MCD_OPC_CheckField, 4, 1, 0, 37, 5, 0, // Skip to: 2561 +/* 1244 */ MCD_OPC_Decode, 138, 14, 238, 2, // Opcode: VMOVH +/* 1249 */ MCD_OPC_FilterValue, 1, 27, 5, 0, // Skip to: 2561 +/* 1254 */ MCD_OPC_CheckPredicate, 60, 22, 5, 0, // Skip to: 2561 +/* 1259 */ MCD_OPC_CheckField, 23, 9, 253, 3, 14, 5, 0, // Skip to: 2561 +/* 1267 */ MCD_OPC_CheckField, 4, 1, 0, 7, 5, 0, // Skip to: 2561 +/* 1274 */ MCD_OPC_Decode, 198, 10, 238, 2, // Opcode: VINSH +/* 1279 */ MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 1316 +/* 1284 */ MCD_OPC_CheckPredicate, 66, 248, 4, 0, // Skip to: 2561 +/* 1289 */ MCD_OPC_CheckField, 23, 9, 253, 3, 240, 4, 0, // Skip to: 2561 +/* 1297 */ MCD_OPC_CheckField, 7, 1, 0, 233, 4, 0, // Skip to: 2561 +/* 1304 */ MCD_OPC_CheckField, 4, 1, 0, 226, 4, 0, // Skip to: 2561 +/* 1311 */ MCD_OPC_Decode, 253, 16, 238, 2, // Opcode: VRINTAS +/* 1316 */ MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 1353 +/* 1321 */ MCD_OPC_CheckPredicate, 66, 211, 4, 0, // Skip to: 2561 +/* 1326 */ MCD_OPC_CheckField, 23, 9, 253, 3, 203, 4, 0, // Skip to: 2561 +/* 1334 */ MCD_OPC_CheckField, 7, 1, 0, 196, 4, 0, // Skip to: 2561 +/* 1341 */ MCD_OPC_CheckField, 4, 1, 0, 189, 4, 0, // Skip to: 2561 +/* 1348 */ MCD_OPC_Decode, 139, 17, 238, 2, // Opcode: VRINTNS +/* 1353 */ MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 1390 +/* 1358 */ MCD_OPC_CheckPredicate, 66, 174, 4, 0, // Skip to: 2561 +/* 1363 */ MCD_OPC_CheckField, 23, 9, 253, 3, 166, 4, 0, // Skip to: 2561 +/* 1371 */ MCD_OPC_CheckField, 7, 1, 0, 159, 4, 0, // Skip to: 2561 +/* 1378 */ MCD_OPC_CheckField, 4, 1, 0, 152, 4, 0, // Skip to: 2561 +/* 1385 */ MCD_OPC_Decode, 146, 17, 238, 2, // Opcode: VRINTPS +/* 1390 */ MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 1427 +/* 1395 */ MCD_OPC_CheckPredicate, 66, 137, 4, 0, // Skip to: 2561 +/* 1400 */ MCD_OPC_CheckField, 23, 9, 253, 3, 129, 4, 0, // Skip to: 2561 +/* 1408 */ MCD_OPC_CheckField, 7, 1, 0, 122, 4, 0, // Skip to: 2561 +/* 1415 */ MCD_OPC_CheckField, 4, 1, 0, 115, 4, 0, // Skip to: 2561 +/* 1422 */ MCD_OPC_Decode, 132, 17, 238, 2, // Opcode: VRINTMS +/* 1427 */ MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 1495 +/* 1432 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 1435 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1465 +/* 1440 */ MCD_OPC_CheckPredicate, 66, 92, 4, 0, // Skip to: 2561 +/* 1445 */ MCD_OPC_CheckField, 23, 9, 253, 3, 84, 4, 0, // Skip to: 2561 +/* 1453 */ MCD_OPC_CheckField, 4, 1, 0, 77, 4, 0, // Skip to: 2561 +/* 1460 */ MCD_OPC_Decode, 166, 9, 238, 2, // Opcode: VCVTAUS +/* 1465 */ MCD_OPC_FilterValue, 1, 67, 4, 0, // Skip to: 2561 +/* 1470 */ MCD_OPC_CheckPredicate, 66, 62, 4, 0, // Skip to: 2561 +/* 1475 */ MCD_OPC_CheckField, 23, 9, 253, 3, 54, 4, 0, // Skip to: 2561 +/* 1483 */ MCD_OPC_CheckField, 4, 1, 0, 47, 4, 0, // Skip to: 2561 +/* 1490 */ MCD_OPC_Decode, 163, 9, 238, 2, // Opcode: VCVTASS +/* 1495 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1563 +/* 1500 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 1503 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1533 +/* 1508 */ MCD_OPC_CheckPredicate, 66, 24, 4, 0, // Skip to: 2561 +/* 1513 */ MCD_OPC_CheckField, 23, 9, 253, 3, 16, 4, 0, // Skip to: 2561 +/* 1521 */ MCD_OPC_CheckField, 4, 1, 0, 9, 4, 0, // Skip to: 2561 +/* 1528 */ MCD_OPC_Decode, 199, 9, 238, 2, // Opcode: VCVTNUS +/* 1533 */ MCD_OPC_FilterValue, 1, 255, 3, 0, // Skip to: 2561 +/* 1538 */ MCD_OPC_CheckPredicate, 66, 250, 3, 0, // Skip to: 2561 +/* 1543 */ MCD_OPC_CheckField, 23, 9, 253, 3, 242, 3, 0, // Skip to: 2561 +/* 1551 */ MCD_OPC_CheckField, 4, 1, 0, 235, 3, 0, // Skip to: 2561 +/* 1558 */ MCD_OPC_Decode, 196, 9, 238, 2, // Opcode: VCVTNSS +/* 1563 */ MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 1631 +/* 1568 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 1571 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1601 +/* 1576 */ MCD_OPC_CheckPredicate, 66, 212, 3, 0, // Skip to: 2561 +/* 1581 */ MCD_OPC_CheckField, 23, 9, 253, 3, 204, 3, 0, // Skip to: 2561 +/* 1589 */ MCD_OPC_CheckField, 4, 1, 0, 197, 3, 0, // Skip to: 2561 +/* 1596 */ MCD_OPC_Decode, 213, 9, 238, 2, // Opcode: VCVTPUS +/* 1601 */ MCD_OPC_FilterValue, 1, 187, 3, 0, // Skip to: 2561 +/* 1606 */ MCD_OPC_CheckPredicate, 66, 182, 3, 0, // Skip to: 2561 +/* 1611 */ MCD_OPC_CheckField, 23, 9, 253, 3, 174, 3, 0, // Skip to: 2561 +/* 1619 */ MCD_OPC_CheckField, 4, 1, 0, 167, 3, 0, // Skip to: 2561 +/* 1626 */ MCD_OPC_Decode, 210, 9, 238, 2, // Opcode: VCVTPSS +/* 1631 */ MCD_OPC_FilterValue, 15, 157, 3, 0, // Skip to: 2561 +/* 1636 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 1639 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1669 +/* 1644 */ MCD_OPC_CheckPredicate, 66, 144, 3, 0, // Skip to: 2561 +/* 1649 */ MCD_OPC_CheckField, 23, 9, 253, 3, 136, 3, 0, // Skip to: 2561 +/* 1657 */ MCD_OPC_CheckField, 4, 1, 0, 129, 3, 0, // Skip to: 2561 +/* 1664 */ MCD_OPC_Decode, 185, 9, 238, 2, // Opcode: VCVTMUS +/* 1669 */ MCD_OPC_FilterValue, 1, 119, 3, 0, // Skip to: 2561 +/* 1674 */ MCD_OPC_CheckPredicate, 66, 114, 3, 0, // Skip to: 2561 +/* 1679 */ MCD_OPC_CheckField, 23, 9, 253, 3, 106, 3, 0, // Skip to: 2561 +/* 1687 */ MCD_OPC_CheckField, 4, 1, 0, 99, 3, 0, // Skip to: 2561 +/* 1694 */ MCD_OPC_Decode, 182, 9, 238, 2, // Opcode: VCVTMSS +/* 1699 */ MCD_OPC_FilterValue, 11, 113, 2, 0, // Skip to: 2329 +/* 1704 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 1707 */ MCD_OPC_FilterValue, 0, 84, 0, 0, // Skip to: 1796 +/* 1712 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1715 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1767 +/* 1720 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 1723 */ MCD_OPC_FilterValue, 252, 3, 16, 0, 0, // Skip to: 1745 +/* 1729 */ MCD_OPC_CheckPredicate, 69, 59, 3, 0, // Skip to: 2561 +/* 1734 */ MCD_OPC_CheckField, 4, 1, 0, 52, 3, 0, // Skip to: 2561 +/* 1741 */ MCD_OPC_Decode, 232, 17, 97, // Opcode: VSELEQD +/* 1745 */ MCD_OPC_FilterValue, 253, 3, 42, 3, 0, // Skip to: 2561 +/* 1751 */ MCD_OPC_CheckPredicate, 69, 37, 3, 0, // Skip to: 2561 +/* 1756 */ MCD_OPC_CheckField, 4, 1, 0, 30, 3, 0, // Skip to: 2561 +/* 1763 */ MCD_OPC_Decode, 156, 13, 97, // Opcode: VMAXNMD +/* 1767 */ MCD_OPC_FilterValue, 1, 21, 3, 0, // Skip to: 2561 +/* 1772 */ MCD_OPC_CheckPredicate, 69, 16, 3, 0, // Skip to: 2561 +/* 1777 */ MCD_OPC_CheckField, 23, 9, 253, 3, 8, 3, 0, // Skip to: 2561 +/* 1785 */ MCD_OPC_CheckField, 4, 1, 0, 1, 3, 0, // Skip to: 2561 +/* 1792 */ MCD_OPC_Decode, 179, 13, 97, // Opcode: VMINNMD +/* 1796 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 1832 +/* 1801 */ MCD_OPC_CheckPredicate, 69, 243, 2, 0, // Skip to: 2561 +/* 1806 */ MCD_OPC_CheckField, 23, 9, 252, 3, 235, 2, 0, // Skip to: 2561 +/* 1814 */ MCD_OPC_CheckField, 6, 1, 0, 228, 2, 0, // Skip to: 2561 +/* 1821 */ MCD_OPC_CheckField, 4, 1, 0, 221, 2, 0, // Skip to: 2561 +/* 1828 */ MCD_OPC_Decode, 241, 17, 97, // Opcode: VSELVSD +/* 1832 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1868 +/* 1837 */ MCD_OPC_CheckPredicate, 69, 207, 2, 0, // Skip to: 2561 +/* 1842 */ MCD_OPC_CheckField, 23, 9, 252, 3, 199, 2, 0, // Skip to: 2561 +/* 1850 */ MCD_OPC_CheckField, 6, 1, 0, 192, 2, 0, // Skip to: 2561 +/* 1857 */ MCD_OPC_CheckField, 4, 1, 0, 185, 2, 0, // Skip to: 2561 +/* 1864 */ MCD_OPC_Decode, 235, 17, 97, // Opcode: VSELGED +/* 1868 */ MCD_OPC_FilterValue, 3, 176, 2, 0, // Skip to: 2561 +/* 1873 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1876 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1905 +/* 1881 */ MCD_OPC_CheckPredicate, 69, 163, 2, 0, // Skip to: 2561 +/* 1886 */ MCD_OPC_CheckField, 23, 9, 252, 3, 155, 2, 0, // Skip to: 2561 +/* 1894 */ MCD_OPC_CheckField, 4, 1, 0, 148, 2, 0, // Skip to: 2561 +/* 1901 */ MCD_OPC_Decode, 238, 17, 97, // Opcode: VSELGTD +/* 1905 */ MCD_OPC_FilterValue, 1, 139, 2, 0, // Skip to: 2561 +/* 1910 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 1913 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 1949 +/* 1918 */ MCD_OPC_CheckPredicate, 69, 126, 2, 0, // Skip to: 2561 +/* 1923 */ MCD_OPC_CheckField, 23, 9, 253, 3, 118, 2, 0, // Skip to: 2561 +/* 1931 */ MCD_OPC_CheckField, 7, 1, 0, 111, 2, 0, // Skip to: 2561 +/* 1938 */ MCD_OPC_CheckField, 4, 1, 0, 104, 2, 0, // Skip to: 2561 +/* 1945 */ MCD_OPC_Decode, 247, 16, 126, // Opcode: VRINTAD +/* 1949 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 1985 +/* 1954 */ MCD_OPC_CheckPredicate, 69, 90, 2, 0, // Skip to: 2561 +/* 1959 */ MCD_OPC_CheckField, 23, 9, 253, 3, 82, 2, 0, // Skip to: 2561 +/* 1967 */ MCD_OPC_CheckField, 7, 1, 0, 75, 2, 0, // Skip to: 2561 +/* 1974 */ MCD_OPC_CheckField, 4, 1, 0, 68, 2, 0, // Skip to: 2561 +/* 1981 */ MCD_OPC_Decode, 133, 17, 126, // Opcode: VRINTND +/* 1985 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 2021 +/* 1990 */ MCD_OPC_CheckPredicate, 69, 54, 2, 0, // Skip to: 2561 +/* 1995 */ MCD_OPC_CheckField, 23, 9, 253, 3, 46, 2, 0, // Skip to: 2561 +/* 2003 */ MCD_OPC_CheckField, 7, 1, 0, 39, 2, 0, // Skip to: 2561 +/* 2010 */ MCD_OPC_CheckField, 4, 1, 0, 32, 2, 0, // Skip to: 2561 +/* 2017 */ MCD_OPC_Decode, 140, 17, 126, // Opcode: VRINTPD +/* 2021 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 2057 +/* 2026 */ MCD_OPC_CheckPredicate, 69, 18, 2, 0, // Skip to: 2561 +/* 2031 */ MCD_OPC_CheckField, 23, 9, 253, 3, 10, 2, 0, // Skip to: 2561 +/* 2039 */ MCD_OPC_CheckField, 7, 1, 0, 3, 2, 0, // Skip to: 2561 +/* 2046 */ MCD_OPC_CheckField, 4, 1, 0, 252, 1, 0, // Skip to: 2561 +/* 2053 */ MCD_OPC_Decode, 254, 16, 126, // Opcode: VRINTMD +/* 2057 */ MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 2125 +/* 2062 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 2065 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2095 +/* 2070 */ MCD_OPC_CheckPredicate, 69, 230, 1, 0, // Skip to: 2561 +/* 2075 */ MCD_OPC_CheckField, 23, 9, 253, 3, 222, 1, 0, // Skip to: 2561 +/* 2083 */ MCD_OPC_CheckField, 4, 1, 0, 215, 1, 0, // Skip to: 2561 +/* 2090 */ MCD_OPC_Decode, 164, 9, 241, 2, // Opcode: VCVTAUD +/* 2095 */ MCD_OPC_FilterValue, 1, 205, 1, 0, // Skip to: 2561 +/* 2100 */ MCD_OPC_CheckPredicate, 69, 200, 1, 0, // Skip to: 2561 +/* 2105 */ MCD_OPC_CheckField, 23, 9, 253, 3, 192, 1, 0, // Skip to: 2561 +/* 2113 */ MCD_OPC_CheckField, 4, 1, 0, 185, 1, 0, // Skip to: 2561 +/* 2120 */ MCD_OPC_Decode, 161, 9, 241, 2, // Opcode: VCVTASD +/* 2125 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 2193 +/* 2130 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 2133 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2163 +/* 2138 */ MCD_OPC_CheckPredicate, 69, 162, 1, 0, // Skip to: 2561 +/* 2143 */ MCD_OPC_CheckField, 23, 9, 253, 3, 154, 1, 0, // Skip to: 2561 +/* 2151 */ MCD_OPC_CheckField, 4, 1, 0, 147, 1, 0, // Skip to: 2561 +/* 2158 */ MCD_OPC_Decode, 197, 9, 241, 2, // Opcode: VCVTNUD +/* 2163 */ MCD_OPC_FilterValue, 1, 137, 1, 0, // Skip to: 2561 +/* 2168 */ MCD_OPC_CheckPredicate, 69, 132, 1, 0, // Skip to: 2561 +/* 2173 */ MCD_OPC_CheckField, 23, 9, 253, 3, 124, 1, 0, // Skip to: 2561 +/* 2181 */ MCD_OPC_CheckField, 4, 1, 0, 117, 1, 0, // Skip to: 2561 +/* 2188 */ MCD_OPC_Decode, 194, 9, 241, 2, // Opcode: VCVTNSD +/* 2193 */ MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 2261 +/* 2198 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 2201 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2231 +/* 2206 */ MCD_OPC_CheckPredicate, 69, 94, 1, 0, // Skip to: 2561 +/* 2211 */ MCD_OPC_CheckField, 23, 9, 253, 3, 86, 1, 0, // Skip to: 2561 +/* 2219 */ MCD_OPC_CheckField, 4, 1, 0, 79, 1, 0, // Skip to: 2561 +/* 2226 */ MCD_OPC_Decode, 211, 9, 241, 2, // Opcode: VCVTPUD +/* 2231 */ MCD_OPC_FilterValue, 1, 69, 1, 0, // Skip to: 2561 +/* 2236 */ MCD_OPC_CheckPredicate, 69, 64, 1, 0, // Skip to: 2561 +/* 2241 */ MCD_OPC_CheckField, 23, 9, 253, 3, 56, 1, 0, // Skip to: 2561 +/* 2249 */ MCD_OPC_CheckField, 4, 1, 0, 49, 1, 0, // Skip to: 2561 +/* 2256 */ MCD_OPC_Decode, 208, 9, 241, 2, // Opcode: VCVTPSD +/* 2261 */ MCD_OPC_FilterValue, 15, 39, 1, 0, // Skip to: 2561 +/* 2266 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... +/* 2269 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2299 +/* 2274 */ MCD_OPC_CheckPredicate, 69, 26, 1, 0, // Skip to: 2561 +/* 2279 */ MCD_OPC_CheckField, 23, 9, 253, 3, 18, 1, 0, // Skip to: 2561 +/* 2287 */ MCD_OPC_CheckField, 4, 1, 0, 11, 1, 0, // Skip to: 2561 +/* 2294 */ MCD_OPC_Decode, 183, 9, 241, 2, // Opcode: VCVTMUD +/* 2299 */ MCD_OPC_FilterValue, 1, 1, 1, 0, // Skip to: 2561 +/* 2304 */ MCD_OPC_CheckPredicate, 69, 252, 0, 0, // Skip to: 2561 +/* 2309 */ MCD_OPC_CheckField, 23, 9, 253, 3, 244, 0, 0, // Skip to: 2561 +/* 2317 */ MCD_OPC_CheckField, 4, 1, 0, 237, 0, 0, // Skip to: 2561 +/* 2324 */ MCD_OPC_Decode, 180, 9, 241, 2, // Opcode: VCVTMSD +/* 2329 */ MCD_OPC_FilterValue, 13, 227, 0, 0, // Skip to: 2561 +/* 2334 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 2337 */ MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 2449 +/* 2342 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2345 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 2397 +/* 2350 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2353 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2375 +/* 2359 */ MCD_OPC_CheckPredicate, 73, 197, 0, 0, // Skip to: 2561 +/* 2364 */ MCD_OPC_CheckField, 20, 2, 2, 190, 0, 0, // Skip to: 2561 +/* 2371 */ MCD_OPC_Decode, 228, 17, 105, // Opcode: VSDOTD +/* 2375 */ MCD_OPC_FilterValue, 252, 3, 180, 0, 0, // Skip to: 2561 +/* 2381 */ MCD_OPC_CheckPredicate, 73, 175, 0, 0, // Skip to: 2561 +/* 2386 */ MCD_OPC_CheckField, 20, 2, 2, 168, 0, 0, // Skip to: 2561 +/* 2393 */ MCD_OPC_Decode, 229, 17, 113, // Opcode: VSDOTDI +/* 2397 */ MCD_OPC_FilterValue, 1, 159, 0, 0, // Skip to: 2561 +/* 2402 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2405 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2427 +/* 2411 */ MCD_OPC_CheckPredicate, 73, 145, 0, 0, // Skip to: 2561 +/* 2416 */ MCD_OPC_CheckField, 20, 2, 2, 138, 0, 0, // Skip to: 2561 +/* 2423 */ MCD_OPC_Decode, 230, 17, 106, // Opcode: VSDOTQ +/* 2427 */ MCD_OPC_FilterValue, 252, 3, 128, 0, 0, // Skip to: 2561 +/* 2433 */ MCD_OPC_CheckPredicate, 73, 123, 0, 0, // Skip to: 2561 +/* 2438 */ MCD_OPC_CheckField, 20, 2, 2, 116, 0, 0, // Skip to: 2561 +/* 2445 */ MCD_OPC_Decode, 231, 17, 114, // Opcode: VSDOTQI +/* 2449 */ MCD_OPC_FilterValue, 1, 107, 0, 0, // Skip to: 2561 +/* 2454 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2457 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 2509 +/* 2462 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2465 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2487 +/* 2471 */ MCD_OPC_CheckPredicate, 73, 85, 0, 0, // Skip to: 2561 +/* 2476 */ MCD_OPC_CheckField, 20, 2, 2, 78, 0, 0, // Skip to: 2561 +/* 2483 */ MCD_OPC_Decode, 159, 21, 105, // Opcode: VUDOTD +/* 2487 */ MCD_OPC_FilterValue, 252, 3, 68, 0, 0, // Skip to: 2561 +/* 2493 */ MCD_OPC_CheckPredicate, 73, 63, 0, 0, // Skip to: 2561 +/* 2498 */ MCD_OPC_CheckField, 20, 2, 2, 56, 0, 0, // Skip to: 2561 +/* 2505 */ MCD_OPC_Decode, 160, 21, 113, // Opcode: VUDOTDI +/* 2509 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 2561 +/* 2514 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 2517 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2539 +/* 2523 */ MCD_OPC_CheckPredicate, 73, 33, 0, 0, // Skip to: 2561 +/* 2528 */ MCD_OPC_CheckField, 20, 2, 2, 26, 0, 0, // Skip to: 2561 +/* 2535 */ MCD_OPC_Decode, 161, 21, 106, // Opcode: VUDOTQ +/* 2539 */ MCD_OPC_FilterValue, 252, 3, 16, 0, 0, // Skip to: 2561 +/* 2545 */ MCD_OPC_CheckPredicate, 73, 11, 0, 0, // Skip to: 2561 +/* 2550 */ MCD_OPC_CheckField, 20, 2, 2, 4, 0, 0, // Skip to: 2561 +/* 2557 */ MCD_OPC_Decode, 162, 21, 114, // Opcode: VUDOTQI +/* 2561 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTablev8Crypto32[] = { +/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 3 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 83 +/* 8 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 11 */ MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 47 +/* 17 */ MCD_OPC_CheckPredicate, 24, 12, 2, 0, // Skip to: 546 +/* 22 */ MCD_OPC_CheckField, 8, 4, 12, 5, 2, 0, // Skip to: 546 +/* 29 */ MCD_OPC_CheckField, 6, 1, 1, 254, 1, 0, // Skip to: 546 +/* 36 */ MCD_OPC_CheckField, 4, 1, 0, 247, 1, 0, // Skip to: 546 +/* 43 */ MCD_OPC_Decode, 247, 5, 106, // Opcode: SHA1C +/* 47 */ MCD_OPC_FilterValue, 230, 3, 237, 1, 0, // Skip to: 546 +/* 53 */ MCD_OPC_CheckPredicate, 24, 232, 1, 0, // Skip to: 546 +/* 58 */ MCD_OPC_CheckField, 8, 4, 12, 225, 1, 0, // Skip to: 546 +/* 65 */ MCD_OPC_CheckField, 6, 1, 1, 218, 1, 0, // Skip to: 546 +/* 72 */ MCD_OPC_CheckField, 4, 1, 0, 211, 1, 0, // Skip to: 546 +/* 79 */ MCD_OPC_Decode, 253, 5, 106, // Opcode: SHA256H +/* 83 */ MCD_OPC_FilterValue, 1, 75, 0, 0, // Skip to: 163 +/* 88 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 91 */ MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 127 +/* 97 */ MCD_OPC_CheckPredicate, 24, 188, 1, 0, // Skip to: 546 +/* 102 */ MCD_OPC_CheckField, 8, 4, 12, 181, 1, 0, // Skip to: 546 +/* 109 */ MCD_OPC_CheckField, 6, 1, 1, 174, 1, 0, // Skip to: 546 +/* 116 */ MCD_OPC_CheckField, 4, 1, 0, 167, 1, 0, // Skip to: 546 +/* 123 */ MCD_OPC_Decode, 250, 5, 106, // Opcode: SHA1P +/* 127 */ MCD_OPC_FilterValue, 230, 3, 157, 1, 0, // Skip to: 546 +/* 133 */ MCD_OPC_CheckPredicate, 24, 152, 1, 0, // Skip to: 546 +/* 138 */ MCD_OPC_CheckField, 8, 4, 12, 145, 1, 0, // Skip to: 546 +/* 145 */ MCD_OPC_CheckField, 6, 1, 1, 138, 1, 0, // Skip to: 546 +/* 152 */ MCD_OPC_CheckField, 4, 1, 0, 131, 1, 0, // Skip to: 546 +/* 159 */ MCD_OPC_Decode, 254, 5, 106, // Opcode: SHA256H2 +/* 163 */ MCD_OPC_FilterValue, 2, 75, 0, 0, // Skip to: 243 +/* 168 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... +/* 171 */ MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 207 +/* 177 */ MCD_OPC_CheckPredicate, 24, 108, 1, 0, // Skip to: 546 +/* 182 */ MCD_OPC_CheckField, 8, 4, 12, 101, 1, 0, // Skip to: 546 +/* 189 */ MCD_OPC_CheckField, 6, 1, 1, 94, 1, 0, // Skip to: 546 +/* 196 */ MCD_OPC_CheckField, 4, 1, 0, 87, 1, 0, // Skip to: 546 +/* 203 */ MCD_OPC_Decode, 249, 5, 106, // Opcode: SHA1M +/* 207 */ MCD_OPC_FilterValue, 230, 3, 77, 1, 0, // Skip to: 546 +/* 213 */ MCD_OPC_CheckPredicate, 24, 72, 1, 0, // Skip to: 546 +/* 218 */ MCD_OPC_CheckField, 8, 4, 12, 65, 1, 0, // Skip to: 546 +/* 225 */ MCD_OPC_CheckField, 6, 1, 1, 58, 1, 0, // Skip to: 546 +/* 232 */ MCD_OPC_CheckField, 4, 1, 0, 51, 1, 0, // Skip to: 546 +/* 239 */ MCD_OPC_Decode, 128, 6, 106, // Opcode: SHA256SU1 +/* 243 */ MCD_OPC_FilterValue, 3, 42, 1, 0, // Skip to: 546 +/* 248 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 251 */ MCD_OPC_FilterValue, 2, 38, 0, 0, // Skip to: 294 +/* 256 */ MCD_OPC_CheckPredicate, 24, 29, 1, 0, // Skip to: 546 +/* 261 */ MCD_OPC_CheckField, 23, 9, 231, 3, 21, 1, 0, // Skip to: 546 +/* 269 */ MCD_OPC_CheckField, 16, 4, 9, 14, 1, 0, // Skip to: 546 +/* 276 */ MCD_OPC_CheckField, 6, 2, 3, 7, 1, 0, // Skip to: 546 +/* 283 */ MCD_OPC_CheckField, 4, 1, 0, 0, 1, 0, // Skip to: 546 +/* 290 */ MCD_OPC_Decode, 248, 5, 127, // Opcode: SHA1H +/* 294 */ MCD_OPC_FilterValue, 3, 211, 0, 0, // Skip to: 510 +/* 299 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 302 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 339 +/* 307 */ MCD_OPC_CheckPredicate, 24, 234, 0, 0, // Skip to: 546 +/* 312 */ MCD_OPC_CheckField, 23, 9, 231, 3, 226, 0, 0, // Skip to: 546 +/* 320 */ MCD_OPC_CheckField, 16, 4, 0, 219, 0, 0, // Skip to: 546 +/* 327 */ MCD_OPC_CheckField, 4, 1, 0, 212, 0, 0, // Skip to: 546 +/* 334 */ MCD_OPC_Decode, 155, 4, 133, 1, // Opcode: AESE +/* 339 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 376 +/* 344 */ MCD_OPC_CheckPredicate, 24, 197, 0, 0, // Skip to: 546 +/* 349 */ MCD_OPC_CheckField, 23, 9, 231, 3, 189, 0, 0, // Skip to: 546 +/* 357 */ MCD_OPC_CheckField, 16, 4, 0, 182, 0, 0, // Skip to: 546 +/* 364 */ MCD_OPC_CheckField, 4, 1, 0, 175, 0, 0, // Skip to: 546 +/* 371 */ MCD_OPC_Decode, 154, 4, 133, 1, // Opcode: AESD +/* 376 */ MCD_OPC_FilterValue, 2, 62, 0, 0, // Skip to: 443 +/* 381 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 384 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 413 +/* 389 */ MCD_OPC_CheckPredicate, 24, 152, 0, 0, // Skip to: 546 +/* 394 */ MCD_OPC_CheckField, 23, 9, 231, 3, 144, 0, 0, // Skip to: 546 +/* 402 */ MCD_OPC_CheckField, 4, 1, 0, 137, 0, 0, // Skip to: 546 +/* 409 */ MCD_OPC_Decode, 157, 4, 127, // Opcode: AESMC +/* 413 */ MCD_OPC_FilterValue, 10, 128, 0, 0, // Skip to: 546 +/* 418 */ MCD_OPC_CheckPredicate, 24, 123, 0, 0, // Skip to: 546 +/* 423 */ MCD_OPC_CheckField, 23, 9, 231, 3, 115, 0, 0, // Skip to: 546 +/* 431 */ MCD_OPC_CheckField, 4, 1, 0, 108, 0, 0, // Skip to: 546 +/* 438 */ MCD_OPC_Decode, 252, 5, 133, 1, // Opcode: SHA1SU1 +/* 443 */ MCD_OPC_FilterValue, 3, 98, 0, 0, // Skip to: 546 +/* 448 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 451 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 480 +/* 456 */ MCD_OPC_CheckPredicate, 24, 85, 0, 0, // Skip to: 546 +/* 461 */ MCD_OPC_CheckField, 23, 9, 231, 3, 77, 0, 0, // Skip to: 546 +/* 469 */ MCD_OPC_CheckField, 4, 1, 0, 70, 0, 0, // Skip to: 546 +/* 476 */ MCD_OPC_Decode, 156, 4, 127, // Opcode: AESIMC +/* 480 */ MCD_OPC_FilterValue, 10, 61, 0, 0, // Skip to: 546 +/* 485 */ MCD_OPC_CheckPredicate, 24, 56, 0, 0, // Skip to: 546 +/* 490 */ MCD_OPC_CheckField, 23, 9, 231, 3, 48, 0, 0, // Skip to: 546 +/* 498 */ MCD_OPC_CheckField, 4, 1, 0, 41, 0, 0, // Skip to: 546 +/* 505 */ MCD_OPC_Decode, 255, 5, 133, 1, // Opcode: SHA256SU0 +/* 510 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 546 +/* 515 */ MCD_OPC_CheckPredicate, 24, 26, 0, 0, // Skip to: 546 +/* 520 */ MCD_OPC_CheckField, 23, 9, 228, 3, 18, 0, 0, // Skip to: 546 +/* 528 */ MCD_OPC_CheckField, 6, 1, 1, 11, 0, 0, // Skip to: 546 +/* 535 */ MCD_OPC_CheckField, 4, 1, 0, 4, 0, 0, // Skip to: 546 +/* 542 */ MCD_OPC_Decode, 251, 5, 106, // Opcode: SHA1SU0 +/* 546 */ MCD_OPC_Fail, + 0 +}; + +static const uint8_t DecoderTablev8NEON32[] = { +/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... +/* 3 */ MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 275 +/* 8 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 11 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 77 +/* 16 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 19 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 48 +/* 24 */ MCD_OPC_CheckPredicate, 74, 110, 8, 0, // Skip to: 2187 +/* 29 */ MCD_OPC_CheckField, 23, 9, 231, 3, 102, 8, 0, // Skip to: 2187 +/* 37 */ MCD_OPC_CheckField, 4, 1, 0, 95, 8, 0, // Skip to: 2187 +/* 44 */ MCD_OPC_Decode, 154, 9, 126, // Opcode: VCVTANSDh +/* 48 */ MCD_OPC_FilterValue, 59, 86, 8, 0, // Skip to: 2187 +/* 53 */ MCD_OPC_CheckPredicate, 75, 81, 8, 0, // Skip to: 2187 +/* 58 */ MCD_OPC_CheckField, 23, 9, 231, 3, 73, 8, 0, // Skip to: 2187 +/* 66 */ MCD_OPC_CheckField, 4, 1, 0, 66, 8, 0, // Skip to: 2187 +/* 73 */ MCD_OPC_Decode, 153, 9, 126, // Opcode: VCVTANSDf +/* 77 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 143 +/* 82 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 85 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 114 +/* 90 */ MCD_OPC_CheckPredicate, 74, 44, 8, 0, // Skip to: 2187 +/* 95 */ MCD_OPC_CheckField, 23, 9, 231, 3, 36, 8, 0, // Skip to: 2187 +/* 103 */ MCD_OPC_CheckField, 4, 1, 0, 29, 8, 0, // Skip to: 2187 +/* 110 */ MCD_OPC_Decode, 156, 9, 127, // Opcode: VCVTANSQh +/* 114 */ MCD_OPC_FilterValue, 59, 20, 8, 0, // Skip to: 2187 +/* 119 */ MCD_OPC_CheckPredicate, 75, 15, 8, 0, // Skip to: 2187 +/* 124 */ MCD_OPC_CheckField, 23, 9, 231, 3, 7, 8, 0, // Skip to: 2187 +/* 132 */ MCD_OPC_CheckField, 4, 1, 0, 0, 8, 0, // Skip to: 2187 +/* 139 */ MCD_OPC_Decode, 155, 9, 127, // Opcode: VCVTANSQf +/* 143 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 209 +/* 148 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 151 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 180 +/* 156 */ MCD_OPC_CheckPredicate, 74, 234, 7, 0, // Skip to: 2187 +/* 161 */ MCD_OPC_CheckField, 23, 9, 231, 3, 226, 7, 0, // Skip to: 2187 +/* 169 */ MCD_OPC_CheckField, 4, 1, 0, 219, 7, 0, // Skip to: 2187 +/* 176 */ MCD_OPC_Decode, 158, 9, 126, // Opcode: VCVTANUDh +/* 180 */ MCD_OPC_FilterValue, 59, 210, 7, 0, // Skip to: 2187 +/* 185 */ MCD_OPC_CheckPredicate, 75, 205, 7, 0, // Skip to: 2187 +/* 190 */ MCD_OPC_CheckField, 23, 9, 231, 3, 197, 7, 0, // Skip to: 2187 +/* 198 */ MCD_OPC_CheckField, 4, 1, 0, 190, 7, 0, // Skip to: 2187 +/* 205 */ MCD_OPC_Decode, 157, 9, 126, // Opcode: VCVTANUDf +/* 209 */ MCD_OPC_FilterValue, 3, 181, 7, 0, // Skip to: 2187 +/* 214 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 217 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 246 +/* 222 */ MCD_OPC_CheckPredicate, 74, 168, 7, 0, // Skip to: 2187 +/* 227 */ MCD_OPC_CheckField, 23, 9, 231, 3, 160, 7, 0, // Skip to: 2187 +/* 235 */ MCD_OPC_CheckField, 4, 1, 0, 153, 7, 0, // Skip to: 2187 +/* 242 */ MCD_OPC_Decode, 160, 9, 127, // Opcode: VCVTANUQh +/* 246 */ MCD_OPC_FilterValue, 59, 144, 7, 0, // Skip to: 2187 +/* 251 */ MCD_OPC_CheckPredicate, 75, 139, 7, 0, // Skip to: 2187 +/* 256 */ MCD_OPC_CheckField, 23, 9, 231, 3, 131, 7, 0, // Skip to: 2187 +/* 264 */ MCD_OPC_CheckField, 4, 1, 0, 124, 7, 0, // Skip to: 2187 +/* 271 */ MCD_OPC_Decode, 159, 9, 127, // Opcode: VCVTANUQf +/* 275 */ MCD_OPC_FilterValue, 1, 11, 1, 0, // Skip to: 547 +/* 280 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 283 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 349 +/* 288 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 291 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 320 +/* 296 */ MCD_OPC_CheckPredicate, 74, 94, 7, 0, // Skip to: 2187 +/* 301 */ MCD_OPC_CheckField, 23, 9, 231, 3, 86, 7, 0, // Skip to: 2187 +/* 309 */ MCD_OPC_CheckField, 4, 1, 0, 79, 7, 0, // Skip to: 2187 +/* 316 */ MCD_OPC_Decode, 187, 9, 126, // Opcode: VCVTNNSDh +/* 320 */ MCD_OPC_FilterValue, 59, 70, 7, 0, // Skip to: 2187 +/* 325 */ MCD_OPC_CheckPredicate, 75, 65, 7, 0, // Skip to: 2187 +/* 330 */ MCD_OPC_CheckField, 23, 9, 231, 3, 57, 7, 0, // Skip to: 2187 +/* 338 */ MCD_OPC_CheckField, 4, 1, 0, 50, 7, 0, // Skip to: 2187 +/* 345 */ MCD_OPC_Decode, 186, 9, 126, // Opcode: VCVTNNSDf +/* 349 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 415 +/* 354 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 357 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 386 +/* 362 */ MCD_OPC_CheckPredicate, 74, 28, 7, 0, // Skip to: 2187 +/* 367 */ MCD_OPC_CheckField, 23, 9, 231, 3, 20, 7, 0, // Skip to: 2187 +/* 375 */ MCD_OPC_CheckField, 4, 1, 0, 13, 7, 0, // Skip to: 2187 +/* 382 */ MCD_OPC_Decode, 189, 9, 127, // Opcode: VCVTNNSQh +/* 386 */ MCD_OPC_FilterValue, 59, 4, 7, 0, // Skip to: 2187 +/* 391 */ MCD_OPC_CheckPredicate, 75, 255, 6, 0, // Skip to: 2187 +/* 396 */ MCD_OPC_CheckField, 23, 9, 231, 3, 247, 6, 0, // Skip to: 2187 +/* 404 */ MCD_OPC_CheckField, 4, 1, 0, 240, 6, 0, // Skip to: 2187 +/* 411 */ MCD_OPC_Decode, 188, 9, 127, // Opcode: VCVTNNSQf +/* 415 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 481 +/* 420 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 423 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 452 +/* 428 */ MCD_OPC_CheckPredicate, 74, 218, 6, 0, // Skip to: 2187 +/* 433 */ MCD_OPC_CheckField, 23, 9, 231, 3, 210, 6, 0, // Skip to: 2187 +/* 441 */ MCD_OPC_CheckField, 4, 1, 0, 203, 6, 0, // Skip to: 2187 +/* 448 */ MCD_OPC_Decode, 191, 9, 126, // Opcode: VCVTNNUDh +/* 452 */ MCD_OPC_FilterValue, 59, 194, 6, 0, // Skip to: 2187 +/* 457 */ MCD_OPC_CheckPredicate, 75, 189, 6, 0, // Skip to: 2187 +/* 462 */ MCD_OPC_CheckField, 23, 9, 231, 3, 181, 6, 0, // Skip to: 2187 +/* 470 */ MCD_OPC_CheckField, 4, 1, 0, 174, 6, 0, // Skip to: 2187 +/* 477 */ MCD_OPC_Decode, 190, 9, 126, // Opcode: VCVTNNUDf +/* 481 */ MCD_OPC_FilterValue, 3, 165, 6, 0, // Skip to: 2187 +/* 486 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 489 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 518 +/* 494 */ MCD_OPC_CheckPredicate, 74, 152, 6, 0, // Skip to: 2187 +/* 499 */ MCD_OPC_CheckField, 23, 9, 231, 3, 144, 6, 0, // Skip to: 2187 +/* 507 */ MCD_OPC_CheckField, 4, 1, 0, 137, 6, 0, // Skip to: 2187 +/* 514 */ MCD_OPC_Decode, 193, 9, 127, // Opcode: VCVTNNUQh +/* 518 */ MCD_OPC_FilterValue, 59, 128, 6, 0, // Skip to: 2187 +/* 523 */ MCD_OPC_CheckPredicate, 75, 123, 6, 0, // Skip to: 2187 +/* 528 */ MCD_OPC_CheckField, 23, 9, 231, 3, 115, 6, 0, // Skip to: 2187 +/* 536 */ MCD_OPC_CheckField, 4, 1, 0, 108, 6, 0, // Skip to: 2187 +/* 543 */ MCD_OPC_Decode, 192, 9, 127, // Opcode: VCVTNNUQf +/* 547 */ MCD_OPC_FilterValue, 2, 11, 1, 0, // Skip to: 819 +/* 552 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 555 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 621 +/* 560 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 563 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 592 +/* 568 */ MCD_OPC_CheckPredicate, 74, 78, 6, 0, // Skip to: 2187 +/* 573 */ MCD_OPC_CheckField, 23, 9, 231, 3, 70, 6, 0, // Skip to: 2187 +/* 581 */ MCD_OPC_CheckField, 4, 1, 0, 63, 6, 0, // Skip to: 2187 +/* 588 */ MCD_OPC_Decode, 201, 9, 126, // Opcode: VCVTPNSDh +/* 592 */ MCD_OPC_FilterValue, 59, 54, 6, 0, // Skip to: 2187 +/* 597 */ MCD_OPC_CheckPredicate, 75, 49, 6, 0, // Skip to: 2187 +/* 602 */ MCD_OPC_CheckField, 23, 9, 231, 3, 41, 6, 0, // Skip to: 2187 +/* 610 */ MCD_OPC_CheckField, 4, 1, 0, 34, 6, 0, // Skip to: 2187 +/* 617 */ MCD_OPC_Decode, 200, 9, 126, // Opcode: VCVTPNSDf +/* 621 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 687 +/* 626 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 629 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 658 +/* 634 */ MCD_OPC_CheckPredicate, 74, 12, 6, 0, // Skip to: 2187 +/* 639 */ MCD_OPC_CheckField, 23, 9, 231, 3, 4, 6, 0, // Skip to: 2187 +/* 647 */ MCD_OPC_CheckField, 4, 1, 0, 253, 5, 0, // Skip to: 2187 +/* 654 */ MCD_OPC_Decode, 203, 9, 127, // Opcode: VCVTPNSQh +/* 658 */ MCD_OPC_FilterValue, 59, 244, 5, 0, // Skip to: 2187 +/* 663 */ MCD_OPC_CheckPredicate, 75, 239, 5, 0, // Skip to: 2187 +/* 668 */ MCD_OPC_CheckField, 23, 9, 231, 3, 231, 5, 0, // Skip to: 2187 +/* 676 */ MCD_OPC_CheckField, 4, 1, 0, 224, 5, 0, // Skip to: 2187 +/* 683 */ MCD_OPC_Decode, 202, 9, 127, // Opcode: VCVTPNSQf +/* 687 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 753 +/* 692 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 695 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 724 +/* 700 */ MCD_OPC_CheckPredicate, 74, 202, 5, 0, // Skip to: 2187 +/* 705 */ MCD_OPC_CheckField, 23, 9, 231, 3, 194, 5, 0, // Skip to: 2187 +/* 713 */ MCD_OPC_CheckField, 4, 1, 0, 187, 5, 0, // Skip to: 2187 +/* 720 */ MCD_OPC_Decode, 205, 9, 126, // Opcode: VCVTPNUDh +/* 724 */ MCD_OPC_FilterValue, 59, 178, 5, 0, // Skip to: 2187 +/* 729 */ MCD_OPC_CheckPredicate, 75, 173, 5, 0, // Skip to: 2187 +/* 734 */ MCD_OPC_CheckField, 23, 9, 231, 3, 165, 5, 0, // Skip to: 2187 +/* 742 */ MCD_OPC_CheckField, 4, 1, 0, 158, 5, 0, // Skip to: 2187 +/* 749 */ MCD_OPC_Decode, 204, 9, 126, // Opcode: VCVTPNUDf +/* 753 */ MCD_OPC_FilterValue, 3, 149, 5, 0, // Skip to: 2187 +/* 758 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 761 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 790 +/* 766 */ MCD_OPC_CheckPredicate, 74, 136, 5, 0, // Skip to: 2187 +/* 771 */ MCD_OPC_CheckField, 23, 9, 231, 3, 128, 5, 0, // Skip to: 2187 +/* 779 */ MCD_OPC_CheckField, 4, 1, 0, 121, 5, 0, // Skip to: 2187 +/* 786 */ MCD_OPC_Decode, 207, 9, 127, // Opcode: VCVTPNUQh +/* 790 */ MCD_OPC_FilterValue, 59, 112, 5, 0, // Skip to: 2187 +/* 795 */ MCD_OPC_CheckPredicate, 75, 107, 5, 0, // Skip to: 2187 +/* 800 */ MCD_OPC_CheckField, 23, 9, 231, 3, 99, 5, 0, // Skip to: 2187 +/* 808 */ MCD_OPC_CheckField, 4, 1, 0, 92, 5, 0, // Skip to: 2187 +/* 815 */ MCD_OPC_Decode, 206, 9, 127, // Opcode: VCVTPNUQf +/* 819 */ MCD_OPC_FilterValue, 3, 11, 1, 0, // Skip to: 1091 +/* 824 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 827 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 893 +/* 832 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 835 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 864 +/* 840 */ MCD_OPC_CheckPredicate, 74, 62, 5, 0, // Skip to: 2187 +/* 845 */ MCD_OPC_CheckField, 23, 9, 231, 3, 54, 5, 0, // Skip to: 2187 +/* 853 */ MCD_OPC_CheckField, 4, 1, 0, 47, 5, 0, // Skip to: 2187 +/* 860 */ MCD_OPC_Decode, 173, 9, 126, // Opcode: VCVTMNSDh +/* 864 */ MCD_OPC_FilterValue, 59, 38, 5, 0, // Skip to: 2187 +/* 869 */ MCD_OPC_CheckPredicate, 75, 33, 5, 0, // Skip to: 2187 +/* 874 */ MCD_OPC_CheckField, 23, 9, 231, 3, 25, 5, 0, // Skip to: 2187 +/* 882 */ MCD_OPC_CheckField, 4, 1, 0, 18, 5, 0, // Skip to: 2187 +/* 889 */ MCD_OPC_Decode, 172, 9, 126, // Opcode: VCVTMNSDf +/* 893 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 959 +/* 898 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 901 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 930 +/* 906 */ MCD_OPC_CheckPredicate, 74, 252, 4, 0, // Skip to: 2187 +/* 911 */ MCD_OPC_CheckField, 23, 9, 231, 3, 244, 4, 0, // Skip to: 2187 +/* 919 */ MCD_OPC_CheckField, 4, 1, 0, 237, 4, 0, // Skip to: 2187 +/* 926 */ MCD_OPC_Decode, 175, 9, 127, // Opcode: VCVTMNSQh +/* 930 */ MCD_OPC_FilterValue, 59, 228, 4, 0, // Skip to: 2187 +/* 935 */ MCD_OPC_CheckPredicate, 75, 223, 4, 0, // Skip to: 2187 +/* 940 */ MCD_OPC_CheckField, 23, 9, 231, 3, 215, 4, 0, // Skip to: 2187 +/* 948 */ MCD_OPC_CheckField, 4, 1, 0, 208, 4, 0, // Skip to: 2187 +/* 955 */ MCD_OPC_Decode, 174, 9, 127, // Opcode: VCVTMNSQf +/* 959 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1025 +/* 964 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 967 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 996 +/* 972 */ MCD_OPC_CheckPredicate, 74, 186, 4, 0, // Skip to: 2187 +/* 977 */ MCD_OPC_CheckField, 23, 9, 231, 3, 178, 4, 0, // Skip to: 2187 +/* 985 */ MCD_OPC_CheckField, 4, 1, 0, 171, 4, 0, // Skip to: 2187 +/* 992 */ MCD_OPC_Decode, 177, 9, 126, // Opcode: VCVTMNUDh +/* 996 */ MCD_OPC_FilterValue, 59, 162, 4, 0, // Skip to: 2187 +/* 1001 */ MCD_OPC_CheckPredicate, 75, 157, 4, 0, // Skip to: 2187 +/* 1006 */ MCD_OPC_CheckField, 23, 9, 231, 3, 149, 4, 0, // Skip to: 2187 +/* 1014 */ MCD_OPC_CheckField, 4, 1, 0, 142, 4, 0, // Skip to: 2187 +/* 1021 */ MCD_OPC_Decode, 176, 9, 126, // Opcode: VCVTMNUDf +/* 1025 */ MCD_OPC_FilterValue, 3, 133, 4, 0, // Skip to: 2187 +/* 1030 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1033 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 1062 +/* 1038 */ MCD_OPC_CheckPredicate, 74, 120, 4, 0, // Skip to: 2187 +/* 1043 */ MCD_OPC_CheckField, 23, 9, 231, 3, 112, 4, 0, // Skip to: 2187 +/* 1051 */ MCD_OPC_CheckField, 4, 1, 0, 105, 4, 0, // Skip to: 2187 +/* 1058 */ MCD_OPC_Decode, 179, 9, 127, // Opcode: VCVTMNUQh +/* 1062 */ MCD_OPC_FilterValue, 59, 96, 4, 0, // Skip to: 2187 +/* 1067 */ MCD_OPC_CheckPredicate, 75, 91, 4, 0, // Skip to: 2187 +/* 1072 */ MCD_OPC_CheckField, 23, 9, 231, 3, 83, 4, 0, // Skip to: 2187 +/* 1080 */ MCD_OPC_CheckField, 4, 1, 0, 76, 4, 0, // Skip to: 2187 +/* 1087 */ MCD_OPC_Decode, 178, 9, 127, // Opcode: VCVTMNUQf +/* 1091 */ MCD_OPC_FilterValue, 4, 11, 1, 0, // Skip to: 1363 +/* 1096 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 1099 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1165 +/* 1104 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1107 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1136 +/* 1112 */ MCD_OPC_CheckPredicate, 74, 46, 4, 0, // Skip to: 2187 +/* 1117 */ MCD_OPC_CheckField, 23, 9, 231, 3, 38, 4, 0, // Skip to: 2187 +/* 1125 */ MCD_OPC_CheckField, 4, 1, 0, 31, 4, 0, // Skip to: 2187 +/* 1132 */ MCD_OPC_Decode, 136, 17, 126, // Opcode: VRINTNNDh +/* 1136 */ MCD_OPC_FilterValue, 58, 22, 4, 0, // Skip to: 2187 +/* 1141 */ MCD_OPC_CheckPredicate, 75, 17, 4, 0, // Skip to: 2187 +/* 1146 */ MCD_OPC_CheckField, 23, 9, 231, 3, 9, 4, 0, // Skip to: 2187 +/* 1154 */ MCD_OPC_CheckField, 4, 1, 0, 2, 4, 0, // Skip to: 2187 +/* 1161 */ MCD_OPC_Decode, 135, 17, 126, // Opcode: VRINTNNDf +/* 1165 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 1231 +/* 1170 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1173 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1202 +/* 1178 */ MCD_OPC_CheckPredicate, 74, 236, 3, 0, // Skip to: 2187 +/* 1183 */ MCD_OPC_CheckField, 23, 9, 231, 3, 228, 3, 0, // Skip to: 2187 +/* 1191 */ MCD_OPC_CheckField, 4, 1, 0, 221, 3, 0, // Skip to: 2187 +/* 1198 */ MCD_OPC_Decode, 138, 17, 127, // Opcode: VRINTNNQh +/* 1202 */ MCD_OPC_FilterValue, 58, 212, 3, 0, // Skip to: 2187 +/* 1207 */ MCD_OPC_CheckPredicate, 75, 207, 3, 0, // Skip to: 2187 +/* 1212 */ MCD_OPC_CheckField, 23, 9, 231, 3, 199, 3, 0, // Skip to: 2187 +/* 1220 */ MCD_OPC_CheckField, 4, 1, 0, 192, 3, 0, // Skip to: 2187 +/* 1227 */ MCD_OPC_Decode, 137, 17, 127, // Opcode: VRINTNNQf +/* 1231 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1297 +/* 1236 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1239 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1268 +/* 1244 */ MCD_OPC_CheckPredicate, 74, 170, 3, 0, // Skip to: 2187 +/* 1249 */ MCD_OPC_CheckField, 23, 9, 231, 3, 162, 3, 0, // Skip to: 2187 +/* 1257 */ MCD_OPC_CheckField, 4, 1, 0, 155, 3, 0, // Skip to: 2187 +/* 1264 */ MCD_OPC_Decode, 153, 17, 126, // Opcode: VRINTXNDh +/* 1268 */ MCD_OPC_FilterValue, 58, 146, 3, 0, // Skip to: 2187 +/* 1273 */ MCD_OPC_CheckPredicate, 75, 141, 3, 0, // Skip to: 2187 +/* 1278 */ MCD_OPC_CheckField, 23, 9, 231, 3, 133, 3, 0, // Skip to: 2187 +/* 1286 */ MCD_OPC_CheckField, 4, 1, 0, 126, 3, 0, // Skip to: 2187 +/* 1293 */ MCD_OPC_Decode, 152, 17, 126, // Opcode: VRINTXNDf +/* 1297 */ MCD_OPC_FilterValue, 3, 117, 3, 0, // Skip to: 2187 +/* 1302 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1305 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1334 +/* 1310 */ MCD_OPC_CheckPredicate, 74, 104, 3, 0, // Skip to: 2187 +/* 1315 */ MCD_OPC_CheckField, 23, 9, 231, 3, 96, 3, 0, // Skip to: 2187 +/* 1323 */ MCD_OPC_CheckField, 4, 1, 0, 89, 3, 0, // Skip to: 2187 +/* 1330 */ MCD_OPC_Decode, 155, 17, 127, // Opcode: VRINTXNQh +/* 1334 */ MCD_OPC_FilterValue, 58, 80, 3, 0, // Skip to: 2187 +/* 1339 */ MCD_OPC_CheckPredicate, 75, 75, 3, 0, // Skip to: 2187 +/* 1344 */ MCD_OPC_CheckField, 23, 9, 231, 3, 67, 3, 0, // Skip to: 2187 +/* 1352 */ MCD_OPC_CheckField, 4, 1, 0, 60, 3, 0, // Skip to: 2187 +/* 1359 */ MCD_OPC_Decode, 154, 17, 127, // Opcode: VRINTXNQf +/* 1363 */ MCD_OPC_FilterValue, 5, 11, 1, 0, // Skip to: 1635 +/* 1368 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 1371 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1437 +/* 1376 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1379 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1408 +/* 1384 */ MCD_OPC_CheckPredicate, 74, 30, 3, 0, // Skip to: 2187 +/* 1389 */ MCD_OPC_CheckField, 23, 9, 231, 3, 22, 3, 0, // Skip to: 2187 +/* 1397 */ MCD_OPC_CheckField, 4, 1, 0, 15, 3, 0, // Skip to: 2187 +/* 1404 */ MCD_OPC_Decode, 250, 16, 126, // Opcode: VRINTANDh +/* 1408 */ MCD_OPC_FilterValue, 58, 6, 3, 0, // Skip to: 2187 +/* 1413 */ MCD_OPC_CheckPredicate, 75, 1, 3, 0, // Skip to: 2187 +/* 1418 */ MCD_OPC_CheckField, 23, 9, 231, 3, 249, 2, 0, // Skip to: 2187 +/* 1426 */ MCD_OPC_CheckField, 4, 1, 0, 242, 2, 0, // Skip to: 2187 +/* 1433 */ MCD_OPC_Decode, 249, 16, 126, // Opcode: VRINTANDf +/* 1437 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 1503 +/* 1442 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1445 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1474 +/* 1450 */ MCD_OPC_CheckPredicate, 74, 220, 2, 0, // Skip to: 2187 +/* 1455 */ MCD_OPC_CheckField, 23, 9, 231, 3, 212, 2, 0, // Skip to: 2187 +/* 1463 */ MCD_OPC_CheckField, 4, 1, 0, 205, 2, 0, // Skip to: 2187 +/* 1470 */ MCD_OPC_Decode, 252, 16, 127, // Opcode: VRINTANQh +/* 1474 */ MCD_OPC_FilterValue, 58, 196, 2, 0, // Skip to: 2187 +/* 1479 */ MCD_OPC_CheckPredicate, 75, 191, 2, 0, // Skip to: 2187 +/* 1484 */ MCD_OPC_CheckField, 23, 9, 231, 3, 183, 2, 0, // Skip to: 2187 +/* 1492 */ MCD_OPC_CheckField, 4, 1, 0, 176, 2, 0, // Skip to: 2187 +/* 1499 */ MCD_OPC_Decode, 251, 16, 127, // Opcode: VRINTANQf +/* 1503 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1569 +/* 1508 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1511 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1540 +/* 1516 */ MCD_OPC_CheckPredicate, 74, 154, 2, 0, // Skip to: 2187 +/* 1521 */ MCD_OPC_CheckField, 23, 9, 231, 3, 146, 2, 0, // Skip to: 2187 +/* 1529 */ MCD_OPC_CheckField, 4, 1, 0, 139, 2, 0, // Skip to: 2187 +/* 1536 */ MCD_OPC_Decode, 160, 17, 126, // Opcode: VRINTZNDh +/* 1540 */ MCD_OPC_FilterValue, 58, 130, 2, 0, // Skip to: 2187 +/* 1545 */ MCD_OPC_CheckPredicate, 75, 125, 2, 0, // Skip to: 2187 +/* 1550 */ MCD_OPC_CheckField, 23, 9, 231, 3, 117, 2, 0, // Skip to: 2187 +/* 1558 */ MCD_OPC_CheckField, 4, 1, 0, 110, 2, 0, // Skip to: 2187 +/* 1565 */ MCD_OPC_Decode, 159, 17, 126, // Opcode: VRINTZNDf +/* 1569 */ MCD_OPC_FilterValue, 3, 101, 2, 0, // Skip to: 2187 +/* 1574 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1577 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1606 +/* 1582 */ MCD_OPC_CheckPredicate, 74, 88, 2, 0, // Skip to: 2187 +/* 1587 */ MCD_OPC_CheckField, 23, 9, 231, 3, 80, 2, 0, // Skip to: 2187 +/* 1595 */ MCD_OPC_CheckField, 4, 1, 0, 73, 2, 0, // Skip to: 2187 +/* 1602 */ MCD_OPC_Decode, 162, 17, 127, // Opcode: VRINTZNQh +/* 1606 */ MCD_OPC_FilterValue, 58, 64, 2, 0, // Skip to: 2187 +/* 1611 */ MCD_OPC_CheckPredicate, 75, 59, 2, 0, // Skip to: 2187 +/* 1616 */ MCD_OPC_CheckField, 23, 9, 231, 3, 51, 2, 0, // Skip to: 2187 +/* 1624 */ MCD_OPC_CheckField, 4, 1, 0, 44, 2, 0, // Skip to: 2187 +/* 1631 */ MCD_OPC_Decode, 161, 17, 127, // Opcode: VRINTZNQf +/* 1635 */ MCD_OPC_FilterValue, 6, 135, 0, 0, // Skip to: 1775 +/* 1640 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 1643 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1709 +/* 1648 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1651 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1680 +/* 1656 */ MCD_OPC_CheckPredicate, 74, 14, 2, 0, // Skip to: 2187 +/* 1661 */ MCD_OPC_CheckField, 23, 9, 231, 3, 6, 2, 0, // Skip to: 2187 +/* 1669 */ MCD_OPC_CheckField, 4, 1, 0, 255, 1, 0, // Skip to: 2187 +/* 1676 */ MCD_OPC_Decode, 129, 17, 126, // Opcode: VRINTMNDh +/* 1680 */ MCD_OPC_FilterValue, 58, 246, 1, 0, // Skip to: 2187 +/* 1685 */ MCD_OPC_CheckPredicate, 75, 241, 1, 0, // Skip to: 2187 +/* 1690 */ MCD_OPC_CheckField, 23, 9, 231, 3, 233, 1, 0, // Skip to: 2187 +/* 1698 */ MCD_OPC_CheckField, 4, 1, 0, 226, 1, 0, // Skip to: 2187 +/* 1705 */ MCD_OPC_Decode, 128, 17, 126, // Opcode: VRINTMNDf +/* 1709 */ MCD_OPC_FilterValue, 3, 217, 1, 0, // Skip to: 2187 +/* 1714 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1717 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1746 +/* 1722 */ MCD_OPC_CheckPredicate, 74, 204, 1, 0, // Skip to: 2187 +/* 1727 */ MCD_OPC_CheckField, 23, 9, 231, 3, 196, 1, 0, // Skip to: 2187 +/* 1735 */ MCD_OPC_CheckField, 4, 1, 0, 189, 1, 0, // Skip to: 2187 +/* 1742 */ MCD_OPC_Decode, 131, 17, 127, // Opcode: VRINTMNQh +/* 1746 */ MCD_OPC_FilterValue, 58, 180, 1, 0, // Skip to: 2187 +/* 1751 */ MCD_OPC_CheckPredicate, 75, 175, 1, 0, // Skip to: 2187 +/* 1756 */ MCD_OPC_CheckField, 23, 9, 231, 3, 167, 1, 0, // Skip to: 2187 +/* 1764 */ MCD_OPC_CheckField, 4, 1, 0, 160, 1, 0, // Skip to: 2187 +/* 1771 */ MCD_OPC_Decode, 130, 17, 127, // Opcode: VRINTMNQf +/* 1775 */ MCD_OPC_FilterValue, 7, 135, 0, 0, // Skip to: 1915 +/* 1780 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... +/* 1783 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1849 +/* 1788 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1791 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1820 +/* 1796 */ MCD_OPC_CheckPredicate, 74, 130, 1, 0, // Skip to: 2187 +/* 1801 */ MCD_OPC_CheckField, 23, 9, 231, 3, 122, 1, 0, // Skip to: 2187 +/* 1809 */ MCD_OPC_CheckField, 4, 1, 0, 115, 1, 0, // Skip to: 2187 +/* 1816 */ MCD_OPC_Decode, 143, 17, 126, // Opcode: VRINTPNDh +/* 1820 */ MCD_OPC_FilterValue, 58, 106, 1, 0, // Skip to: 2187 +/* 1825 */ MCD_OPC_CheckPredicate, 75, 101, 1, 0, // Skip to: 2187 +/* 1830 */ MCD_OPC_CheckField, 23, 9, 231, 3, 93, 1, 0, // Skip to: 2187 +/* 1838 */ MCD_OPC_CheckField, 4, 1, 0, 86, 1, 0, // Skip to: 2187 +/* 1845 */ MCD_OPC_Decode, 142, 17, 126, // Opcode: VRINTPNDf +/* 1849 */ MCD_OPC_FilterValue, 3, 77, 1, 0, // Skip to: 2187 +/* 1854 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 1857 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1886 +/* 1862 */ MCD_OPC_CheckPredicate, 74, 64, 1, 0, // Skip to: 2187 +/* 1867 */ MCD_OPC_CheckField, 23, 9, 231, 3, 56, 1, 0, // Skip to: 2187 +/* 1875 */ MCD_OPC_CheckField, 4, 1, 0, 49, 1, 0, // Skip to: 2187 +/* 1882 */ MCD_OPC_Decode, 145, 17, 127, // Opcode: VRINTPNQh +/* 1886 */ MCD_OPC_FilterValue, 58, 40, 1, 0, // Skip to: 2187 +/* 1891 */ MCD_OPC_CheckPredicate, 75, 35, 1, 0, // Skip to: 2187 +/* 1896 */ MCD_OPC_CheckField, 23, 9, 231, 3, 27, 1, 0, // Skip to: 2187 +/* 1904 */ MCD_OPC_CheckField, 4, 1, 0, 20, 1, 0, // Skip to: 2187 +/* 1911 */ MCD_OPC_Decode, 144, 17, 127, // Opcode: VRINTPNQf +/* 1915 */ MCD_OPC_FilterValue, 15, 11, 1, 0, // Skip to: 2187 +/* 1920 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 1923 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1989 +/* 1928 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1931 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1960 +/* 1936 */ MCD_OPC_CheckPredicate, 75, 246, 0, 0, // Skip to: 2187 +/* 1941 */ MCD_OPC_CheckField, 23, 9, 230, 3, 238, 0, 0, // Skip to: 2187 +/* 1949 */ MCD_OPC_CheckField, 4, 1, 1, 231, 0, 0, // Skip to: 2187 +/* 1956 */ MCD_OPC_Decode, 158, 13, 97, // Opcode: VMAXNMNDf +/* 1960 */ MCD_OPC_FilterValue, 1, 222, 0, 0, // Skip to: 2187 +/* 1965 */ MCD_OPC_CheckPredicate, 75, 217, 0, 0, // Skip to: 2187 +/* 1970 */ MCD_OPC_CheckField, 23, 9, 230, 3, 209, 0, 0, // Skip to: 2187 +/* 1978 */ MCD_OPC_CheckField, 4, 1, 1, 202, 0, 0, // Skip to: 2187 +/* 1985 */ MCD_OPC_Decode, 160, 13, 98, // Opcode: VMAXNMNQf +/* 1989 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 2055 +/* 1994 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 1997 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2026 +/* 2002 */ MCD_OPC_CheckPredicate, 74, 180, 0, 0, // Skip to: 2187 +/* 2007 */ MCD_OPC_CheckField, 23, 9, 230, 3, 172, 0, 0, // Skip to: 2187 +/* 2015 */ MCD_OPC_CheckField, 4, 1, 1, 165, 0, 0, // Skip to: 2187 +/* 2022 */ MCD_OPC_Decode, 159, 13, 97, // Opcode: VMAXNMNDh +/* 2026 */ MCD_OPC_FilterValue, 1, 156, 0, 0, // Skip to: 2187 +/* 2031 */ MCD_OPC_CheckPredicate, 74, 151, 0, 0, // Skip to: 2187 +/* 2036 */ MCD_OPC_CheckField, 23, 9, 230, 3, 143, 0, 0, // Skip to: 2187 +/* 2044 */ MCD_OPC_CheckField, 4, 1, 1, 136, 0, 0, // Skip to: 2187 +/* 2051 */ MCD_OPC_Decode, 161, 13, 98, // Opcode: VMAXNMNQh +/* 2055 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 2121 +/* 2060 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2063 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2092 +/* 2068 */ MCD_OPC_CheckPredicate, 75, 114, 0, 0, // Skip to: 2187 +/* 2073 */ MCD_OPC_CheckField, 23, 9, 230, 3, 106, 0, 0, // Skip to: 2187 +/* 2081 */ MCD_OPC_CheckField, 4, 1, 1, 99, 0, 0, // Skip to: 2187 +/* 2088 */ MCD_OPC_Decode, 181, 13, 97, // Opcode: VMINNMNDf +/* 2092 */ MCD_OPC_FilterValue, 1, 90, 0, 0, // Skip to: 2187 +/* 2097 */ MCD_OPC_CheckPredicate, 75, 85, 0, 0, // Skip to: 2187 +/* 2102 */ MCD_OPC_CheckField, 23, 9, 230, 3, 77, 0, 0, // Skip to: 2187 +/* 2110 */ MCD_OPC_CheckField, 4, 1, 1, 70, 0, 0, // Skip to: 2187 +/* 2117 */ MCD_OPC_Decode, 183, 13, 98, // Opcode: VMINNMNQf +/* 2121 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 2187 +/* 2126 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... +/* 2129 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2158 +/* 2134 */ MCD_OPC_CheckPredicate, 74, 48, 0, 0, // Skip to: 2187 +/* 2139 */ MCD_OPC_CheckField, 23, 9, 230, 3, 40, 0, 0, // Skip to: 2187 +/* 2147 */ MCD_OPC_CheckField, 4, 1, 1, 33, 0, 0, // Skip to: 2187 +/* 2154 */ MCD_OPC_Decode, 182, 13, 97, // Opcode: VMINNMNDh +/* 2158 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2187 +/* 2163 */ MCD_OPC_CheckPredicate, 74, 19, 0, 0, // Skip to: 2187 +/* 2168 */ MCD_OPC_CheckField, 23, 9, 230, 3, 11, 0, 0, // Skip to: 2187 +/* 2176 */ MCD_OPC_CheckField, 4, 1, 1, 4, 0, 0, // Skip to: 2187 +/* 2183 */ MCD_OPC_Decode, 184, 13, 98, // Opcode: VMINNMNQh +/* 2187 */ MCD_OPC_Fail, + 0 +}; + +static bool checkDecoderPredicate(unsigned Idx, MCInst *MI) +{ + switch (Idx) { + default: /* llvm_unreachable("Invalid index!");*/ + case 0: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb)); + case 1: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6Ops)); + case 2: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCRC)); + case 3: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TEOps)); + case 4: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && !ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); + case 5: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); + case 6: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps)); + case 7: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)); + case 8: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease)); + case 9: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex)); + case 10: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV4TOps)); + case 11: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps)); + case 12: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureTrustZone)); + case 13: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6T2Ops)); + case 14: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_4aOps)); + case 15: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)); + case 16: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMP)); + case 17: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)); + case 18: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDB)); + case 19: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureHWDivARM)); + case 20: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNaClTrap)); + case 21: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON)); + case 22: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); + case 23: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps)); + case 24: + return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCrypto)); + case 25: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFP16)); + case 26: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4)); + case 27: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP2)); + case 28: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb)); + case 29: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt)); + case 30: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps)); + case 31: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6Ops)); + case 32: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MBaselineOps)); + case 33: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps)); + case 34: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); + case 35: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); + case 36: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)); + case 37: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); + case 38: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)); + case 39: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); + case 40: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease)); + case 41: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex)); + case 42: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); + case 43: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)); + case 44: + return (ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt)); + case 45: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)); + case 46: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); + case 47: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_4aOps)); + case 48: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex)); + case 49: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDB)); + case 50: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)); + case 51: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)); + case 52: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureTrustZone)); + case 53: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); + case 54: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)); + case 55: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureHWDivThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MBaselineOps)); + case 56: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMP)); + case 57: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCRC)); + case 58: + return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && !ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); + case 59: + return (!ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)); + case 60: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); + case 61: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP2) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); + case 62: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4)); + case 63: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); + case 64: + return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MMainlineOps) && ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt)); + case 65: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP3)); + case 66: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8)); + case 67: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFP16)); + case 68: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP3) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); + case 69: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); + case 70: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps)); + case 71: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); + case 72: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps)); + case 73: + return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDotProd)); + case 74: + return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); + case 75: + return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON)); + } +} + +#define DecodeToMCInst(fname, fieldname, InsnType) \ +static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ + uint64_t Address, bool *Decoder) \ +{ \ + InsnType tmp; \ + /* printf("Idx = %u\n", Idx); */\ + switch (Idx) { \ + default: /* llvm_unreachable("Invalid index!");*/ \ + case 0: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 1: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 2: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 3: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 4: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 5: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 6: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 7: \ + if (!Check(&S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 8: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 9: \ + if (!Check(&S, DecodeCPSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 10: \ + tmp = fieldname(insn, 9, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 11: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 12: \ + if (!Check(&S, DecodeQADDInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 13: \ + if (!Check(&S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 14: \ + if (!Check(&S, DecodeSwap(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 15: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 8, 12) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 16: \ + if (!Check(&S, DecodeTSTInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 17: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 18: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 19: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 20: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 21: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 22: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 23: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 24: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 25: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 26: \ + tmp = 0; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 27: \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 28: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 29: \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 30: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 31: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 32: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 33: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 34: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 35: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 36: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 37: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 2) << 5; \ + tmp |= fieldname(insn, 8, 4) << 8; \ + if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 38: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 39: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 40: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 41: \ + if (!Check(&S, DecodeDoubleRegStore(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 42: \ + if (!Check(&S, DecodeDoubleRegLoad(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 43: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 23, 1) << 4; \ + if (!Check(&S, DecodePostIdxReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 44: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 8, 4) << 4; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 45: \ + if (!Check(&S, DecodeLDR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 46: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 8, 4) << 4; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 47: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 48: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 22, 2) << 12; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 49: \ + if (!Check(&S, DecodeArmMOVTWInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 50: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 51: \ + return S; \ + case 52: \ + if (!Check(&S, DecodeHINTInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 53: \ + tmp = 0; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 54: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 12); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 55: \ + if (!Check(&S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 56: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 57: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 58: \ + if (!Check(&S, DecodeSTRPreImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 59: \ + if (!Check(&S, DecodeLDRPreImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 60: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 61: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 62: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 63: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 64: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 65: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 66: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 7, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 67: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 68: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 69: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 70: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 71: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 72: \ + if (!Check(&S, DecodeSTRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 73: \ + if (!Check(&S, DecodeLDRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 74: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 6, 1) << 5; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 75: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 76: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 7, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 77: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 7) << 5; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + tmp |= fieldname(insn, 23, 1) << 12; \ + if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 78: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 5; \ + if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 79: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 5) << 0; \ + tmp |= fieldname(insn, 16, 5) << 5; \ + if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 80: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 81: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 82: \ + if (!Check(&S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 83: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 84: \ + if (!Check(&S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 85: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 24) << 1; \ + tmp |= fieldname(insn, 24, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 86: \ + if (!Check(&S, DecoderForMRRC2AndMCRR2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 87: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 88: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 89: \ + tmp = fieldname(insn, 0, 24); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 90: \ + if (!Check(&S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 91: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 92: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 93: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 94: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 95: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 96: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 97: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 98: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 99: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 100: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 101: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 102: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 103: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 104: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 105: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 106: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 107: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 108: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 109: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 110: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 111: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 112: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 3, 1) << 0; \ + tmp |= fieldname(insn, 5, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 113: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 114: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 115: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 116: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 117: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 118: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 119: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 120: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 9, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 121: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 122: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 123: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 124: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 9, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 125: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 126: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 127: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 128: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 129: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 130: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 131: \ + if (!Check(&S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 132: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 133: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 134: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 135: \ + if (!Check(&S, DecodeTBLInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 136: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 137: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 138: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 17, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 139: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 140: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 141: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 17, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 142: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 143: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 144: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 145: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 146: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 147: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 148: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 149: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 150: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 151: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 152: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 153: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 154: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 155: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 156: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 157: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 158: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 159: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 160: \ + if (!Check(&S, DecodeVCVTD(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 161: \ + if (!Check(&S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 162: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 163: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 164: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 165: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 166: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 167: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 168: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 169: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 170: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 171: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 172: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 173: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 174: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 175: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 176: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 177: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 178: \ + if (!Check(&S, DecodeVCVTQ(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 179: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 180: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 181: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 182: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 183: \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 184: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 185: \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 6, 1) << 0; \ + tmp |= fieldname(insn, 21, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 186: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 6, 1) << 0; \ + tmp |= fieldname(insn, 21, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 187: \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 5, 2) << 0; \ + tmp |= fieldname(insn, 21, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 188: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 5, 2) << 0; \ + tmp |= fieldname(insn, 21, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 189: \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 190: \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 191: \ + if (!Check(&S, DecodeVLDST4Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 192: \ + if (!Check(&S, DecodeVST1LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 193: \ + if (!Check(&S, DecodeVLD1LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 194: \ + if (!Check(&S, DecodeVST2LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 195: \ + if (!Check(&S, DecodeVLD2LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 196: \ + if (!Check(&S, DecodeVLDST1Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 197: \ + if (!Check(&S, DecodeVST3LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 198: \ + if (!Check(&S, DecodeVLD3LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 199: \ + if (!Check(&S, DecodeVLDST2Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 200: \ + if (!Check(&S, DecodeVST4LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 201: \ + if (!Check(&S, DecodeVLD4LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 202: \ + if (!Check(&S, DecodeVLDST3Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 203: \ + if (!Check(&S, DecodeVLD1DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 204: \ + if (!Check(&S, DecodeVLD2DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 205: \ + if (!Check(&S, DecodeVLD3DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 206: \ + if (!Check(&S, DecodeVLD4DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 207: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 208: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 209: \ + if (!Check(&S, DecodeThumbAddSPReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 210: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 211: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 3) << 0; \ + tmp |= fieldname(insn, 7, 1) << 3; \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 212: \ + tmp = fieldname(insn, 3, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 213: \ + tmp = fieldname(insn, 3, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 214: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeThumbAddrModePC(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 215: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 6); \ + if (!Check(&S, DecodeThumbAddrModeRR(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 216: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 8); \ + if (!Check(&S, DecodeThumbAddrModeIS(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 217: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeThumbAddrModeSP(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 218: \ + if (!Check(&S, DecodeThumbAddSpecialReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 219: \ + if (!Check(&S, DecodeThumbAddSPImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 220: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 3, 5) << 0; \ + tmp |= fieldname(insn, 9, 1) << 5; \ + if (!Check(&S, DecodeThumbCmpBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 221: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 8, 1) << 14; \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 222: \ + tmp = fieldname(insn, 3, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 223: \ + if (!Check(&S, DecodeThumbCPS(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 224: \ + tmp = fieldname(insn, 0, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 225: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 8, 1) << 15; \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 226: \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 227: \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 228: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 229: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 230: \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeThumbBCCTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 231: \ + tmp = fieldname(insn, 0, 11); \ + if (!Check(&S, DecodeThumbBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 232: \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 10) << 1; \ + tmp |= fieldname(insn, 11, 1) << 21; \ + tmp |= fieldname(insn, 13, 1) << 22; \ + tmp |= fieldname(insn, 16, 10) << 11; \ + tmp |= fieldname(insn, 26, 1) << 23; \ + if (!Check(&S, DecodeThumbBLXOffset(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 233: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 11) << 0; \ + tmp |= fieldname(insn, 11, 1) << 21; \ + tmp |= fieldname(insn, 13, 1) << 22; \ + tmp |= fieldname(insn, 16, 10) << 11; \ + tmp |= fieldname(insn, 26, 1) << 23; \ + if (!Check(&S, DecodeThumbBLTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 234: \ + if (!Check(&S, DecodeIT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 235: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 13) << 0; \ + tmp |= fieldname(insn, 14, 1) << 14; \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 236: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 237: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 238: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 239: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 240: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 241: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 242: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 243: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 13) << 0; \ + tmp |= fieldname(insn, 14, 1) << 14; \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 244: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 16); \ + if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 245: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 246: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 247: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 248: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 249: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 250: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 8; \ + if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 251: \ + if (!Check(&S, DecodeThumbTableBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 252: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 253: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeT2AddrModeImm8s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 254: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 255: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 256: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 257: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 258: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 259: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 260: \ + if (!Check(&S, DecodeT2STRDPreInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 261: \ + if (!Check(&S, DecodeT2LDRDPreInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 262: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 4, 4) << 5; \ + tmp |= fieldname(insn, 12, 3) << 9; \ + if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 263: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 264: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 265: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 266: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 267: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 3) << 8; \ + tmp |= fieldname(insn, 26, 1) << 11; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 268: \ + if (!Check(&S, DecodeT2Adr(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 269: \ + if (!Check(&S, DecodeT2MOVTWInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 270: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 271: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + tmp |= fieldname(insn, 21, 1) << 5; \ + if (!Check(&S, DecodeT2ShifterImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 272: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 273: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 5) << 5; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 274: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 5) << 5; \ + tmp |= fieldname(insn, 6, 2) << 0; \ + tmp |= fieldname(insn, 12, 3) << 2; \ + if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 275: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 276: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 277: \ + if (!Check(&S, DecodeT2CPSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 278: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 279: \ + tmp = 0; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 4; \ + if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 280: \ + tmp = 0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + tmp |= fieldname(insn, 8, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 5; \ + if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 281: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 4, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + tmp |= fieldname(insn, 20, 1) << 5; \ + if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 282: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 12; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 283: \ + tmp = fieldname(insn, 16, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 284: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 10, 2) << 10; \ + if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 285: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 286: \ + if (!Check(&S, DecodeThumb2BCCInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 287: \ + if (!Check(&S, DecodeT2BInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 288: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 2; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 16, 4) << 6; \ + if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 289: \ + if (!Check(&S, DecodeT2LdStPre(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 290: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 291: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 9, 1) << 8; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 292: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 293: \ + if (!Check(&S, DecodeT2LoadShift(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 294: \ + if (!Check(&S, DecodeT2LoadImm8(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 295: \ + if (!Check(&S, DecodeT2LoadT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 296: \ + if (!Check(&S, DecodeT2LoadImm12(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 297: \ + if (!Check(&S, DecodeT2LoadLabel(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 298: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 299: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 300: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 301: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 302: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 303: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 304: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 305: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 306: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 2; \ + tmp |= fieldname(insn, 4, 2) << 0; \ + tmp |= fieldname(insn, 16, 4) << 6; \ + if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 307: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 9, 1) << 8; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 308: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 12) << 0; \ + tmp |= fieldname(insn, 16, 4) << 13; \ + if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 309: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 310: \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 311: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 4); \ + if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 4, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 312: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 313: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 314: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 6, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 315: \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 8, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 316: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 317: \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 3, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 3); \ + if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 318: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeAddrMode5FP16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 319: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 320: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 321: \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 322: \ + if (!Check(&S, DecodeVMOVSRR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 323: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 4) << 9; \ + tmp |= fieldname(insn, 22, 1) << 8; \ + if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 324: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 325: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 326: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 327: \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 328: \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 329: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + tmp |= fieldname(insn, 22, 1) << 12; \ + if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 330: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 331: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 16, 4) << 9; \ + tmp |= fieldname(insn, 23, 1) << 8; \ + if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 332: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 333: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 334: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 335: \ + if (!Check(&S, DecodeVMOVRRS(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 336: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 337: \ + tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 338: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 339: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 8) << 0; \ + tmp |= fieldname(insn, 12, 4) << 9; \ + tmp |= fieldname(insn, 22, 1) << 8; \ + if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 340: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + tmp |= fieldname(insn, 22, 1) << 12; \ + if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 341: \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 1, 7) << 1; \ + tmp |= fieldname(insn, 12, 4) << 8; \ + if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 342: \ + if (!Check(&S, DecodeForVMRSandVMSR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 343: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 344: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 345: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 346: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 347: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 348: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 349: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 350: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 351: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 352: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 353: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 16, 4) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 354: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 355: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 356: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 357: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 28, 4); \ + if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 358: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 359: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 23, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 360: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 361: \ + if (!Check(&S, DecodeNEONComplexLane64Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 362: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 24, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 363: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 23, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 364: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 0; \ + tmp |= fieldname(insn, 22, 1) << 4; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 4; \ + tmp |= fieldname(insn, 16, 4) << 0; \ + if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 20, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 365: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 366: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 367: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 368: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 7, 1) << 0; \ + tmp |= fieldname(insn, 16, 4) << 1; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 1; \ + tmp |= fieldname(insn, 5, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 369: \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 4) << 1; \ + tmp |= fieldname(insn, 22, 1) << 0; \ + if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 0, 4) << 0; \ + tmp |= fieldname(insn, 5, 1) << 4; \ + if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + } \ +} + +#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ +static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ + InsnType insn, uint64_t Address) \ +{ \ + unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ + InsnType Val, FieldValue, PositiveMask, NegativeMask; \ + bool Pred, Fail, DecodeComplete = true; \ + uint32_t ExpectedValue; \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ + switch (*Ptr) { \ + default: \ + return MCDisassembler_Fail; \ + case MCD_OPC_ExtractField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + ++Ptr; \ + CurFieldValue = fieldname(insn, Start, Len); \ + break; \ + } \ + case MCD_OPC_FilterValue: { \ + /* Decode the field value. */ \ + Val = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ + if (Val != CurFieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckField: { \ + Start = *++Ptr; \ + Len = *++Ptr; \ + FieldValue = fieldname(insn, Start, Len); \ + /* Decode the field value. */ \ + ExpectedValue = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ + if (ExpectedValue != FieldValue) \ + Ptr += NumToSkip; \ + break; \ + } \ + case MCD_OPC_CheckPredicate: { \ + /* Decode the Predicate Index value. */ \ + PIdx = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + if (!(Pred = checkDecoderPredicate(PIdx, MI))) \ + Ptr += NumToSkip; \ + /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ + (void)Pred; \ + break; \ + } \ + case MCD_OPC_Decode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + MCInst_clear(MI); \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + /* assert(DecodeComplete); */ \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* assert(S == MCDisassembler_Fail); */ \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ + } \ + case MCD_OPC_SoftFail: { \ + /* Decode the mask values. */ \ + PositiveMask = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + NegativeMask = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ + if (Fail) \ + S = MCDisassembler_SoftFail; \ + break; \ + } \ + case MCD_OPC_Fail: { \ + return MCDisassembler_Fail; \ + } \ + } \ + } \ + /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ +} + + + +FieldFromInstruction(fieldFromInstruction_2, uint16_t) +DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t) +DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t) + +FieldFromInstruction(fieldFromInstruction_4, uint32_t) +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) + diff --git a/capstone/arch/ARM/ARMGenInstrInfo.inc b/capstone/arch/ARM/ARMGenInstrInfo.inc new file mode 100644 index 000000000..82178f342 --- /dev/null +++ b/capstone/arch/ARM/ARMGenInstrInfo.inc @@ -0,0 +1,6632 @@ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +|* Target Instruction Enum Values and Descriptors *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +#ifdef GET_INSTRINFO_ENUM +#undef GET_INSTRINFO_ENUM + +enum { + ARM_PHI = 0, + ARM_INLINEASM = 1, + ARM_CFI_INSTRUCTION = 2, + ARM_EH_LABEL = 3, + ARM_GC_LABEL = 4, + ARM_ANNOTATION_LABEL = 5, + ARM_KILL = 6, + ARM_EXTRACT_SUBREG = 7, + ARM_INSERT_SUBREG = 8, + ARM_IMPLICIT_DEF = 9, + ARM_SUBREG_TO_REG = 10, + ARM_COPY_TO_REGCLASS = 11, + ARM_DBG_VALUE = 12, + ARM_DBG_LABEL = 13, + ARM_REG_SEQUENCE = 14, + ARM_COPY = 15, + ARM_BUNDLE = 16, + ARM_LIFETIME_START = 17, + ARM_LIFETIME_END = 18, + ARM_STACKMAP = 19, + ARM_FENTRY_CALL = 20, + ARM_PATCHPOINT = 21, + ARM_LOAD_STACK_GUARD = 22, + ARM_STATEPOINT = 23, + ARM_LOCAL_ESCAPE = 24, + ARM_FAULTING_OP = 25, + ARM_PATCHABLE_OP = 26, + ARM_PATCHABLE_FUNCTION_ENTER = 27, + ARM_PATCHABLE_RET = 28, + ARM_PATCHABLE_FUNCTION_EXIT = 29, + ARM_PATCHABLE_TAIL_CALL = 30, + ARM_PATCHABLE_EVENT_CALL = 31, + ARM_PATCHABLE_TYPED_EVENT_CALL = 32, + ARM_ICALL_BRANCH_FUNNEL = 33, + ARM_G_ADD = 34, + ARM_G_SUB = 35, + ARM_G_MUL = 36, + ARM_G_SDIV = 37, + ARM_G_UDIV = 38, + ARM_G_SREM = 39, + ARM_G_UREM = 40, + ARM_G_AND = 41, + ARM_G_OR = 42, + ARM_G_XOR = 43, + ARM_G_IMPLICIT_DEF = 44, + ARM_G_PHI = 45, + ARM_G_FRAME_INDEX = 46, + ARM_G_GLOBAL_VALUE = 47, + ARM_G_EXTRACT = 48, + ARM_G_UNMERGE_VALUES = 49, + ARM_G_INSERT = 50, + ARM_G_MERGE_VALUES = 51, + ARM_G_PTRTOINT = 52, + ARM_G_INTTOPTR = 53, + ARM_G_BITCAST = 54, + ARM_G_LOAD = 55, + ARM_G_SEXTLOAD = 56, + ARM_G_ZEXTLOAD = 57, + ARM_G_STORE = 58, + ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, + ARM_G_ATOMIC_CMPXCHG = 60, + ARM_G_ATOMICRMW_XCHG = 61, + ARM_G_ATOMICRMW_ADD = 62, + ARM_G_ATOMICRMW_SUB = 63, + ARM_G_ATOMICRMW_AND = 64, + ARM_G_ATOMICRMW_NAND = 65, + ARM_G_ATOMICRMW_OR = 66, + ARM_G_ATOMICRMW_XOR = 67, + ARM_G_ATOMICRMW_MAX = 68, + ARM_G_ATOMICRMW_MIN = 69, + ARM_G_ATOMICRMW_UMAX = 70, + ARM_G_ATOMICRMW_UMIN = 71, + ARM_G_BRCOND = 72, + ARM_G_BRINDIRECT = 73, + ARM_G_INTRINSIC = 74, + ARM_G_INTRINSIC_W_SIDE_EFFECTS = 75, + ARM_G_ANYEXT = 76, + ARM_G_TRUNC = 77, + ARM_G_CONSTANT = 78, + ARM_G_FCONSTANT = 79, + ARM_G_VASTART = 80, + ARM_G_VAARG = 81, + ARM_G_SEXT = 82, + ARM_G_ZEXT = 83, + ARM_G_SHL = 84, + ARM_G_LSHR = 85, + ARM_G_ASHR = 86, + ARM_G_ICMP = 87, + ARM_G_FCMP = 88, + ARM_G_SELECT = 89, + ARM_G_UADDE = 90, + ARM_G_USUBE = 91, + ARM_G_SADDO = 92, + ARM_G_SSUBO = 93, + ARM_G_UMULO = 94, + ARM_G_SMULO = 95, + ARM_G_UMULH = 96, + ARM_G_SMULH = 97, + ARM_G_FADD = 98, + ARM_G_FSUB = 99, + ARM_G_FMUL = 100, + ARM_G_FMA = 101, + ARM_G_FDIV = 102, + ARM_G_FREM = 103, + ARM_G_FPOW = 104, + ARM_G_FEXP = 105, + ARM_G_FEXP2 = 106, + ARM_G_FLOG = 107, + ARM_G_FLOG2 = 108, + ARM_G_FNEG = 109, + ARM_G_FPEXT = 110, + ARM_G_FPTRUNC = 111, + ARM_G_FPTOSI = 112, + ARM_G_FPTOUI = 113, + ARM_G_SITOFP = 114, + ARM_G_UITOFP = 115, + ARM_G_FABS = 116, + ARM_G_GEP = 117, + ARM_G_PTR_MASK = 118, + ARM_G_BR = 119, + ARM_G_INSERT_VECTOR_ELT = 120, + ARM_G_EXTRACT_VECTOR_ELT = 121, + ARM_G_SHUFFLE_VECTOR = 122, + ARM_G_BSWAP = 123, + ARM_G_ADDRSPACE_CAST = 124, + ARM_G_BLOCK_ADDR = 125, + ARM_ABS = 126, + ARM_ADDSri = 127, + ARM_ADDSrr = 128, + ARM_ADDSrsi = 129, + ARM_ADDSrsr = 130, + ARM_ADJCALLSTACKDOWN = 131, + ARM_ADJCALLSTACKUP = 132, + ARM_ASRi = 133, + ARM_ASRr = 134, + ARM_B = 135, + ARM_BCCZi64 = 136, + ARM_BCCi64 = 137, + ARM_BMOVPCB_CALL = 138, + ARM_BMOVPCRX_CALL = 139, + ARM_BR_JTadd = 140, + ARM_BR_JTm_i12 = 141, + ARM_BR_JTm_rs = 142, + ARM_BR_JTr = 143, + ARM_BX_CALL = 144, + ARM_CMP_SWAP_16 = 145, + ARM_CMP_SWAP_32 = 146, + ARM_CMP_SWAP_64 = 147, + ARM_CMP_SWAP_8 = 148, + ARM_CONSTPOOL_ENTRY = 149, + ARM_COPY_STRUCT_BYVAL_I32 = 150, + ARM_CompilerBarrier = 151, + ARM_ITasm = 152, + ARM_Int_eh_sjlj_dispatchsetup = 153, + ARM_Int_eh_sjlj_setup_dispatch = 157, + ARM_JUMPTABLE_ADDRS = 158, + ARM_JUMPTABLE_INSTS = 159, + ARM_JUMPTABLE_TBB = 160, + ARM_JUMPTABLE_TBH = 161, + ARM_LDMIA_RET = 162, + ARM_LDRBT_POST = 163, + ARM_LDRConstPool = 164, + ARM_LDRLIT_ga_abs = 165, + ARM_LDRLIT_ga_pcrel = 166, + ARM_LDRLIT_ga_pcrel_ldr = 167, + ARM_LDRT_POST = 168, + ARM_LEApcrel = 169, + ARM_LEApcrelJT = 170, + ARM_LSLi = 171, + ARM_LSLr = 172, + ARM_LSRi = 173, + ARM_LSRr = 174, + ARM_MEMCPY = 175, + ARM_MLAv5 = 176, + ARM_MOVCCi = 177, + ARM_MOVCCi16 = 178, + ARM_MOVCCi32imm = 179, + ARM_MOVCCr = 180, + ARM_MOVCCsi = 181, + ARM_MOVCCsr = 182, + ARM_MOVPCRX = 183, + ARM_MOVTi16_ga_pcrel = 184, + ARM_MOV_ga_pcrel = 185, + ARM_MOV_ga_pcrel_ldr = 186, + ARM_MOVi16_ga_pcrel = 187, + ARM_MOVi32imm = 188, + ARM_MOVsra_flag = 189, + ARM_MOVsrl_flag = 190, + ARM_MULv5 = 191, + ARM_MVNCCi = 192, + ARM_PICADD = 193, + ARM_PICLDR = 194, + ARM_PICLDRB = 195, + ARM_PICLDRH = 196, + ARM_PICLDRSB = 197, + ARM_PICLDRSH = 198, + ARM_PICSTR = 199, + ARM_PICSTRB = 200, + ARM_PICSTRH = 201, + ARM_RORi = 202, + ARM_RORr = 203, + ARM_RRX = 204, + ARM_RRXi = 205, + ARM_RSBSri = 206, + ARM_RSBSrsi = 207, + ARM_RSBSrsr = 208, + ARM_SMLALv5 = 209, + ARM_SMULLv5 = 210, + ARM_SPACE = 211, + ARM_STRBT_POST = 212, + ARM_STRBi_preidx = 213, + ARM_STRBr_preidx = 214, + ARM_STRH_preidx = 215, + ARM_STRT_POST = 216, + ARM_STRi_preidx = 217, + ARM_STRr_preidx = 218, + ARM_SUBS_PC_LR = 219, + ARM_SUBSri = 220, + ARM_SUBSrr = 221, + ARM_SUBSrsi = 222, + ARM_SUBSrsr = 223, + ARM_TAILJMPd = 224, + ARM_TAILJMPr = 225, + ARM_TAILJMPr4 = 226, + ARM_TCRETURNdi = 227, + ARM_TCRETURNri = 228, + ARM_TPsoft = 229, + ARM_UMLALv5 = 230, + ARM_UMULLv5 = 231, + ARM_VLD1LNdAsm_16 = 232, + ARM_VLD1LNdAsm_32 = 233, + ARM_VLD1LNdAsm_8 = 234, + ARM_VLD1LNdWB_fixed_Asm_16 = 235, + ARM_VLD1LNdWB_fixed_Asm_32 = 236, + ARM_VLD1LNdWB_fixed_Asm_8 = 237, + ARM_VLD1LNdWB_register_Asm_16 = 238, + ARM_VLD1LNdWB_register_Asm_32 = 239, + ARM_VLD1LNdWB_register_Asm_8 = 240, + ARM_VLD2LNdAsm_16 = 241, + ARM_VLD2LNdAsm_32 = 242, + ARM_VLD2LNdAsm_8 = 243, + ARM_VLD2LNdWB_fixed_Asm_16 = 244, + ARM_VLD2LNdWB_fixed_Asm_32 = 245, + ARM_VLD2LNdWB_fixed_Asm_8 = 246, + ARM_VLD2LNdWB_register_Asm_16 = 247, + ARM_VLD2LNdWB_register_Asm_32 = 248, + ARM_VLD2LNdWB_register_Asm_8 = 249, + ARM_VLD2LNqAsm_16 = 250, + ARM_VLD2LNqAsm_32 = 251, + ARM_VLD2LNqWB_fixed_Asm_16 = 252, + ARM_VLD2LNqWB_fixed_Asm_32 = 253, + ARM_VLD2LNqWB_register_Asm_16 = 254, + ARM_VLD2LNqWB_register_Asm_32 = 255, + ARM_VLD3DUPdAsm_16 = 256, + ARM_VLD3DUPdAsm_32 = 257, + ARM_VLD3DUPdAsm_8 = 258, + ARM_VLD3DUPdWB_fixed_Asm_16 = 259, + ARM_VLD3DUPdWB_fixed_Asm_32 = 260, + ARM_VLD3DUPdWB_fixed_Asm_8 = 261, + ARM_VLD3DUPdWB_register_Asm_16 = 262, + ARM_VLD3DUPdWB_register_Asm_32 = 263, + ARM_VLD3DUPdWB_register_Asm_8 = 264, + ARM_VLD3DUPqAsm_16 = 265, + ARM_VLD3DUPqAsm_32 = 266, + ARM_VLD3DUPqAsm_8 = 267, + ARM_VLD3DUPqWB_fixed_Asm_16 = 268, + ARM_VLD3DUPqWB_fixed_Asm_32 = 269, + ARM_VLD3DUPqWB_fixed_Asm_8 = 270, + ARM_VLD3DUPqWB_register_Asm_16 = 271, + ARM_VLD3DUPqWB_register_Asm_32 = 272, + ARM_VLD3DUPqWB_register_Asm_8 = 273, + ARM_VLD3LNdAsm_16 = 274, + ARM_VLD3LNdAsm_32 = 275, + ARM_VLD3LNdAsm_8 = 276, + ARM_VLD3LNdWB_fixed_Asm_16 = 277, + ARM_VLD3LNdWB_fixed_Asm_32 = 278, + ARM_VLD3LNdWB_fixed_Asm_8 = 279, + ARM_VLD3LNdWB_register_Asm_16 = 280, + ARM_VLD3LNdWB_register_Asm_32 = 281, + ARM_VLD3LNdWB_register_Asm_8 = 282, + ARM_VLD3LNqAsm_16 = 283, + ARM_VLD3LNqAsm_32 = 284, + ARM_VLD3LNqWB_fixed_Asm_16 = 285, + ARM_VLD3LNqWB_fixed_Asm_32 = 286, + ARM_VLD3LNqWB_register_Asm_16 = 287, + ARM_VLD3LNqWB_register_Asm_32 = 288, + ARM_VLD3dAsm_16 = 289, + ARM_VLD3dAsm_32 = 290, + ARM_VLD3dAsm_8 = 291, + ARM_VLD3dWB_fixed_Asm_16 = 292, + ARM_VLD3dWB_fixed_Asm_32 = 293, + ARM_VLD3dWB_fixed_Asm_8 = 294, + ARM_VLD3dWB_register_Asm_16 = 295, + ARM_VLD3dWB_register_Asm_32 = 296, + ARM_VLD3dWB_register_Asm_8 = 297, + ARM_VLD3qAsm_16 = 298, + ARM_VLD3qAsm_32 = 299, + ARM_VLD3qAsm_8 = 300, + ARM_VLD3qWB_fixed_Asm_16 = 301, + ARM_VLD3qWB_fixed_Asm_32 = 302, + ARM_VLD3qWB_fixed_Asm_8 = 303, + ARM_VLD3qWB_register_Asm_16 = 304, + ARM_VLD3qWB_register_Asm_32 = 305, + ARM_VLD3qWB_register_Asm_8 = 306, + ARM_VLD4DUPdAsm_16 = 307, + ARM_VLD4DUPdAsm_32 = 308, + ARM_VLD4DUPdAsm_8 = 309, + ARM_VLD4DUPdWB_fixed_Asm_16 = 310, + ARM_VLD4DUPdWB_fixed_Asm_32 = 311, + ARM_VLD4DUPdWB_fixed_Asm_8 = 312, + ARM_VLD4DUPdWB_register_Asm_16 = 313, + ARM_VLD4DUPdWB_register_Asm_32 = 314, + ARM_VLD4DUPdWB_register_Asm_8 = 315, + ARM_VLD4DUPqAsm_16 = 316, + ARM_VLD4DUPqAsm_32 = 317, + ARM_VLD4DUPqAsm_8 = 318, + ARM_VLD4DUPqWB_fixed_Asm_16 = 319, + ARM_VLD4DUPqWB_fixed_Asm_32 = 320, + ARM_VLD4DUPqWB_fixed_Asm_8 = 321, + ARM_VLD4DUPqWB_register_Asm_16 = 322, + ARM_VLD4DUPqWB_register_Asm_32 = 323, + ARM_VLD4DUPqWB_register_Asm_8 = 324, + ARM_VLD4LNdAsm_16 = 325, + ARM_VLD4LNdAsm_32 = 326, + ARM_VLD4LNdAsm_8 = 327, + ARM_VLD4LNdWB_fixed_Asm_16 = 328, + ARM_VLD4LNdWB_fixed_Asm_32 = 329, + ARM_VLD4LNdWB_fixed_Asm_8 = 330, + ARM_VLD4LNdWB_register_Asm_16 = 331, + ARM_VLD4LNdWB_register_Asm_32 = 332, + ARM_VLD4LNdWB_register_Asm_8 = 333, + ARM_VLD4LNqAsm_16 = 334, + ARM_VLD4LNqAsm_32 = 335, + ARM_VLD4LNqWB_fixed_Asm_16 = 336, + ARM_VLD4LNqWB_fixed_Asm_32 = 337, + ARM_VLD4LNqWB_register_Asm_16 = 338, + ARM_VLD4LNqWB_register_Asm_32 = 339, + ARM_VLD4dAsm_16 = 340, + ARM_VLD4dAsm_32 = 341, + ARM_VLD4dAsm_8 = 342, + ARM_VLD4dWB_fixed_Asm_16 = 343, + ARM_VLD4dWB_fixed_Asm_32 = 344, + ARM_VLD4dWB_fixed_Asm_8 = 345, + ARM_VLD4dWB_register_Asm_16 = 346, + ARM_VLD4dWB_register_Asm_32 = 347, + ARM_VLD4dWB_register_Asm_8 = 348, + ARM_VLD4qAsm_16 = 349, + ARM_VLD4qAsm_32 = 350, + ARM_VLD4qAsm_8 = 351, + ARM_VLD4qWB_fixed_Asm_16 = 352, + ARM_VLD4qWB_fixed_Asm_32 = 353, + ARM_VLD4qWB_fixed_Asm_8 = 354, + ARM_VLD4qWB_register_Asm_16 = 355, + ARM_VLD4qWB_register_Asm_32 = 356, + ARM_VLD4qWB_register_Asm_8 = 357, + ARM_VMOVD0 = 358, + ARM_VMOVDcc = 359, + ARM_VMOVQ0 = 360, + ARM_VMOVScc = 361, + ARM_VST1LNdAsm_16 = 362, + ARM_VST1LNdAsm_32 = 363, + ARM_VST1LNdAsm_8 = 364, + ARM_VST1LNdWB_fixed_Asm_16 = 365, + ARM_VST1LNdWB_fixed_Asm_32 = 366, + ARM_VST1LNdWB_fixed_Asm_8 = 367, + ARM_VST1LNdWB_register_Asm_16 = 368, + ARM_VST1LNdWB_register_Asm_32 = 369, + ARM_VST1LNdWB_register_Asm_8 = 370, + ARM_VST2LNdAsm_16 = 371, + ARM_VST2LNdAsm_32 = 372, + ARM_VST2LNdAsm_8 = 373, + ARM_VST2LNdWB_fixed_Asm_16 = 374, + ARM_VST2LNdWB_fixed_Asm_32 = 375, + ARM_VST2LNdWB_fixed_Asm_8 = 376, + ARM_VST2LNdWB_register_Asm_16 = 377, + ARM_VST2LNdWB_register_Asm_32 = 378, + ARM_VST2LNdWB_register_Asm_8 = 379, + ARM_VST2LNqAsm_16 = 380, + ARM_VST2LNqAsm_32 = 381, + ARM_VST2LNqWB_fixed_Asm_16 = 382, + ARM_VST2LNqWB_fixed_Asm_32 = 383, + ARM_VST2LNqWB_register_Asm_16 = 384, + ARM_VST2LNqWB_register_Asm_32 = 385, + ARM_VST3LNdAsm_16 = 386, + ARM_VST3LNdAsm_32 = 387, + ARM_VST3LNdAsm_8 = 388, + ARM_VST3LNdWB_fixed_Asm_16 = 389, + ARM_VST3LNdWB_fixed_Asm_32 = 390, + ARM_VST3LNdWB_fixed_Asm_8 = 391, + ARM_VST3LNdWB_register_Asm_16 = 392, + ARM_VST3LNdWB_register_Asm_32 = 393, + ARM_VST3LNdWB_register_Asm_8 = 394, + ARM_VST3LNqAsm_16 = 395, + ARM_VST3LNqAsm_32 = 396, + ARM_VST3LNqWB_fixed_Asm_16 = 397, + ARM_VST3LNqWB_fixed_Asm_32 = 398, + ARM_VST3LNqWB_register_Asm_16 = 399, + ARM_VST3LNqWB_register_Asm_32 = 400, + ARM_VST3dAsm_16 = 401, + ARM_VST3dAsm_32 = 402, + ARM_VST3dAsm_8 = 403, + ARM_VST3dWB_fixed_Asm_16 = 404, + ARM_VST3dWB_fixed_Asm_32 = 405, + ARM_VST3dWB_fixed_Asm_8 = 406, + ARM_VST3dWB_register_Asm_16 = 407, + ARM_VST3dWB_register_Asm_32 = 408, + ARM_VST3dWB_register_Asm_8 = 409, + ARM_VST3qAsm_16 = 410, + ARM_VST3qAsm_32 = 411, + ARM_VST3qAsm_8 = 412, + ARM_VST3qWB_fixed_Asm_16 = 413, + ARM_VST3qWB_fixed_Asm_32 = 414, + ARM_VST3qWB_fixed_Asm_8 = 415, + ARM_VST3qWB_register_Asm_16 = 416, + ARM_VST3qWB_register_Asm_32 = 417, + ARM_VST3qWB_register_Asm_8 = 418, + ARM_VST4LNdAsm_16 = 419, + ARM_VST4LNdAsm_32 = 420, + ARM_VST4LNdAsm_8 = 421, + ARM_VST4LNdWB_fixed_Asm_16 = 422, + ARM_VST4LNdWB_fixed_Asm_32 = 423, + ARM_VST4LNdWB_fixed_Asm_8 = 424, + ARM_VST4LNdWB_register_Asm_16 = 425, + ARM_VST4LNdWB_register_Asm_32 = 426, + ARM_VST4LNdWB_register_Asm_8 = 427, + ARM_VST4LNqAsm_16 = 428, + ARM_VST4LNqAsm_32 = 429, + ARM_VST4LNqWB_fixed_Asm_16 = 430, + ARM_VST4LNqWB_fixed_Asm_32 = 431, + ARM_VST4LNqWB_register_Asm_16 = 432, + ARM_VST4LNqWB_register_Asm_32 = 433, + ARM_VST4dAsm_16 = 434, + ARM_VST4dAsm_32 = 435, + ARM_VST4dAsm_8 = 436, + ARM_VST4dWB_fixed_Asm_16 = 437, + ARM_VST4dWB_fixed_Asm_32 = 438, + ARM_VST4dWB_fixed_Asm_8 = 439, + ARM_VST4dWB_register_Asm_16 = 440, + ARM_VST4dWB_register_Asm_32 = 441, + ARM_VST4dWB_register_Asm_8 = 442, + ARM_VST4qAsm_16 = 443, + ARM_VST4qAsm_32 = 444, + ARM_VST4qAsm_8 = 445, + ARM_VST4qWB_fixed_Asm_16 = 446, + ARM_VST4qWB_fixed_Asm_32 = 447, + ARM_VST4qWB_fixed_Asm_8 = 448, + ARM_VST4qWB_register_Asm_16 = 449, + ARM_VST4qWB_register_Asm_32 = 450, + ARM_VST4qWB_register_Asm_8 = 451, + ARM_t2ABS = 454, + ARM_t2ADDSri = 455, + ARM_t2ADDSrr = 456, + ARM_t2ADDSrs = 457, + ARM_t2BR_JT = 458, + ARM_t2LDMIA_RET = 459, + ARM_t2LDRBpcrel = 460, + ARM_t2LDRConstPool = 461, + ARM_t2LDRHpcrel = 462, + ARM_t2LDRSBpcrel = 463, + ARM_t2LDRSHpcrel = 464, + ARM_t2LDRpci_pic = 465, + ARM_t2LDRpcrel = 466, + ARM_t2LEApcrel = 467, + ARM_t2LEApcrelJT = 468, + ARM_t2MOVCCasr = 469, + ARM_t2MOVCCi = 470, + ARM_t2MOVCCi16 = 471, + ARM_t2MOVCCi32imm = 472, + ARM_t2MOVCClsl = 473, + ARM_t2MOVCClsr = 474, + ARM_t2MOVCCr = 475, + ARM_t2MOVCCror = 476, + ARM_t2MOVSsi = 477, + ARM_t2MOVSsr = 478, + ARM_t2MOVTi16_ga_pcrel = 479, + ARM_t2MOV_ga_pcrel = 480, + ARM_t2MOVi16_ga_pcrel = 481, + ARM_t2MOVi32imm = 482, + ARM_t2MOVsi = 483, + ARM_t2MOVsr = 484, + ARM_t2MVNCCi = 485, + ARM_t2RSBSri = 486, + ARM_t2RSBSrs = 487, + ARM_t2STRB_preidx = 488, + ARM_t2STRH_preidx = 489, + ARM_t2STR_preidx = 490, + ARM_t2SUBSri = 491, + ARM_t2SUBSrr = 492, + ARM_t2SUBSrs = 493, + ARM_t2TBB_JT = 494, + ARM_t2TBH_JT = 495, + ARM_tADCS = 496, + ARM_tADDSi3 = 497, + ARM_tADDSi8 = 498, + ARM_tADDSrr = 499, + ARM_tADDframe = 500, + ARM_tADJCALLSTACKDOWN = 501, + ARM_tADJCALLSTACKUP = 502, + ARM_tBRIND = 503, + ARM_tBR_JTr = 504, + ARM_tBX_CALL = 505, + ARM_tBX_RET = 506, + ARM_tBX_RET_vararg = 507, + ARM_tBfar = 508, + ARM_tLDMIA_UPD = 509, + ARM_tLDRConstPool = 510, + ARM_tLDRLIT_ga_abs = 511, + ARM_tLDRLIT_ga_pcrel = 512, + ARM_tLDR_postidx = 513, + ARM_tLDRpci_pic = 514, + ARM_tLEApcrel = 515, + ARM_tLEApcrelJT = 516, + ARM_tMOVCCr_pseudo = 517, + ARM_tPOP_RET = 518, + ARM_tSBCS = 519, + ARM_tSUBSi3 = 520, + ARM_tSUBSi8 = 521, + ARM_tSUBSrr = 522, + ARM_tTAILJMPd = 523, + ARM_tTAILJMPdND = 524, + ARM_tTAILJMPr = 525, + ARM_tTBB_JT = 526, + ARM_tTBH_JT = 527, + ARM_tTPsoft = 528, + ARM_ADCri = 529, + ARM_ADCrr = 530, + ARM_ADCrsi = 531, + ARM_ADCrsr = 532, + ARM_ADDri = 533, + ARM_ADDrr = 534, + ARM_ADDrsi = 535, + ARM_ADDrsr = 536, + ARM_ADR = 537, + ARM_AESD = 538, + ARM_AESE = 539, + ARM_AESIMC = 540, + ARM_AESMC = 541, + ARM_ANDri = 542, + ARM_ANDrr = 543, + ARM_ANDrsi = 544, + ARM_ANDrsr = 545, + ARM_BFC = 546, + ARM_BFI = 547, + ARM_BICri = 548, + ARM_BICrr = 549, + ARM_BICrsi = 550, + ARM_BICrsr = 551, + ARM_BKPT = 552, + ARM_BL = 553, + ARM_BLX = 554, + ARM_BLX_pred = 555, + ARM_BLXi = 556, + ARM_BL_pred = 557, + ARM_BX = 558, + ARM_BXJ = 559, + ARM_BX_RET = 560, + ARM_BX_pred = 561, + ARM_Bcc = 562, + ARM_CDP = 563, + ARM_CDP2 = 564, + ARM_CLREX = 565, + ARM_CLZ = 566, + ARM_CMNri = 567, + ARM_CMNzrr = 568, + ARM_CMNzrsi = 569, + ARM_CMNzrsr = 570, + ARM_CMPri = 571, + ARM_CMPrr = 572, + ARM_CMPrsi = 573, + ARM_CMPrsr = 574, + ARM_CPS1p = 575, + ARM_CPS2p = 576, + ARM_CPS3p = 577, + ARM_CRC32B = 578, + ARM_CRC32CB = 579, + ARM_CRC32CH = 580, + ARM_CRC32CW = 581, + ARM_CRC32H = 582, + ARM_CRC32W = 583, + ARM_DBG = 584, + ARM_DMB = 585, + ARM_DSB = 586, + ARM_EORri = 587, + ARM_EORrr = 588, + ARM_EORrsi = 589, + ARM_EORrsr = 590, + ARM_ERET = 591, + ARM_FCONSTD = 592, + ARM_FCONSTH = 593, + ARM_FCONSTS = 594, + ARM_FLDMXDB_UPD = 595, + ARM_FLDMXIA = 596, + ARM_FLDMXIA_UPD = 597, + ARM_FMSTAT = 598, + ARM_FSTMXDB_UPD = 599, + ARM_FSTMXIA = 600, + ARM_FSTMXIA_UPD = 601, + ARM_HINT = 602, + ARM_HLT = 603, + ARM_HVC = 604, + ARM_ISB = 605, + ARM_LDA = 606, + ARM_LDAB = 607, + ARM_LDAEX = 608, + ARM_LDAEXB = 609, + ARM_LDAEXD = 610, + ARM_LDAEXH = 611, + ARM_LDAH = 612, + ARM_LDC2L_OFFSET = 613, + ARM_LDC2L_OPTION = 614, + ARM_LDC2L_POST = 615, + ARM_LDC2L_PRE = 616, + ARM_LDC2_OFFSET = 617, + ARM_LDC2_OPTION = 618, + ARM_LDC2_POST = 619, + ARM_LDC2_PRE = 620, + ARM_LDCL_OFFSET = 621, + ARM_LDCL_OPTION = 622, + ARM_LDCL_POST = 623, + ARM_LDCL_PRE = 624, + ARM_LDC_OFFSET = 625, + ARM_LDC_OPTION = 626, + ARM_LDC_POST = 627, + ARM_LDC_PRE = 628, + ARM_LDMDA = 629, + ARM_LDMDA_UPD = 630, + ARM_LDMDB = 631, + ARM_LDMDB_UPD = 632, + ARM_LDMIA = 633, + ARM_LDMIA_UPD = 634, + ARM_LDMIB = 635, + ARM_LDMIB_UPD = 636, + ARM_LDRBT_POST_IMM = 637, + ARM_LDRBT_POST_REG = 638, + ARM_LDRB_POST_IMM = 639, + ARM_LDRB_POST_REG = 640, + ARM_LDRB_PRE_IMM = 641, + ARM_LDRB_PRE_REG = 642, + ARM_LDRBi12 = 643, + ARM_LDRBrs = 644, + ARM_LDRD = 645, + ARM_LDRD_POST = 646, + ARM_LDRD_PRE = 647, + ARM_LDREX = 648, + ARM_LDREXB = 649, + ARM_LDREXD = 650, + ARM_LDREXH = 651, + ARM_LDRH = 652, + ARM_LDRHTi = 653, + ARM_LDRHTr = 654, + ARM_LDRH_POST = 655, + ARM_LDRH_PRE = 656, + ARM_LDRSB = 657, + ARM_LDRSBTi = 658, + ARM_LDRSBTr = 659, + ARM_LDRSB_POST = 660, + ARM_LDRSB_PRE = 661, + ARM_LDRSH = 662, + ARM_LDRSHTi = 663, + ARM_LDRSHTr = 664, + ARM_LDRSH_POST = 665, + ARM_LDRSH_PRE = 666, + ARM_LDRT_POST_IMM = 667, + ARM_LDRT_POST_REG = 668, + ARM_LDR_POST_IMM = 669, + ARM_LDR_POST_REG = 670, + ARM_LDR_PRE_IMM = 671, + ARM_LDR_PRE_REG = 672, + ARM_LDRcp = 673, + ARM_LDRi12 = 674, + ARM_LDRrs = 675, + ARM_MCR = 676, + ARM_MCR2 = 677, + ARM_MCRR = 678, + ARM_MCRR2 = 679, + ARM_MLA = 680, + ARM_MLS = 681, + ARM_MOVPCLR = 682, + ARM_MOVTi16 = 683, + ARM_MOVi = 684, + ARM_MOVi16 = 685, + ARM_MOVr = 686, + ARM_MOVr_TC = 687, + ARM_MOVsi = 688, + ARM_MOVsr = 689, + ARM_MRC = 690, + ARM_MRC2 = 691, + ARM_MRRC = 692, + ARM_MRRC2 = 693, + ARM_MRS = 694, + ARM_MRSbanked = 695, + ARM_MRSsys = 696, + ARM_MSR = 697, + ARM_MSRbanked = 698, + ARM_MSRi = 699, + ARM_MUL = 700, + ARM_MVNi = 701, + ARM_MVNr = 702, + ARM_MVNsi = 703, + ARM_MVNsr = 704, + ARM_ORRri = 705, + ARM_ORRrr = 706, + ARM_ORRrsi = 707, + ARM_ORRrsr = 708, + ARM_PKHBT = 709, + ARM_PKHTB = 710, + ARM_PLDWi12 = 711, + ARM_PLDWrs = 712, + ARM_PLDi12 = 713, + ARM_PLDrs = 714, + ARM_PLIi12 = 715, + ARM_PLIrs = 716, + ARM_QADD = 717, + ARM_QADD16 = 718, + ARM_QADD8 = 719, + ARM_QASX = 720, + ARM_QDADD = 721, + ARM_QDSUB = 722, + ARM_QSAX = 723, + ARM_QSUB = 724, + ARM_QSUB16 = 725, + ARM_QSUB8 = 726, + ARM_RBIT = 727, + ARM_REV = 728, + ARM_REV16 = 729, + ARM_REVSH = 730, + ARM_RFEDA = 731, + ARM_RFEDA_UPD = 732, + ARM_RFEDB = 733, + ARM_RFEDB_UPD = 734, + ARM_RFEIA = 735, + ARM_RFEIA_UPD = 736, + ARM_RFEIB = 737, + ARM_RFEIB_UPD = 738, + ARM_RSBri = 739, + ARM_RSBrr = 740, + ARM_RSBrsi = 741, + ARM_RSBrsr = 742, + ARM_RSCri = 743, + ARM_RSCrr = 744, + ARM_RSCrsi = 745, + ARM_RSCrsr = 746, + ARM_SADD16 = 747, + ARM_SADD8 = 748, + ARM_SASX = 749, + ARM_SBCri = 750, + ARM_SBCrr = 751, + ARM_SBCrsi = 752, + ARM_SBCrsr = 753, + ARM_SBFX = 754, + ARM_SDIV = 755, + ARM_SEL = 756, + ARM_SETEND = 757, + ARM_SETPAN = 758, + ARM_SHA1C = 759, + ARM_SHA1H = 760, + ARM_SHA1M = 761, + ARM_SHA1P = 762, + ARM_SHA1SU0 = 763, + ARM_SHA1SU1 = 764, + ARM_SHA256H = 765, + ARM_SHA256H2 = 766, + ARM_SHA256SU0 = 767, + ARM_SHA256SU1 = 768, + ARM_SHADD16 = 769, + ARM_SHADD8 = 770, + ARM_SHASX = 771, + ARM_SHSAX = 772, + ARM_SHSUB16 = 773, + ARM_SHSUB8 = 774, + ARM_SMC = 775, + ARM_SMLABB = 776, + ARM_SMLABT = 777, + ARM_SMLAD = 778, + ARM_SMLADX = 779, + ARM_SMLAL = 780, + ARM_SMLALBB = 781, + ARM_SMLALBT = 782, + ARM_SMLALD = 783, + ARM_SMLALDX = 784, + ARM_SMLALTB = 785, + ARM_SMLALTT = 786, + ARM_SMLATB = 787, + ARM_SMLATT = 788, + ARM_SMLAWB = 789, + ARM_SMLAWT = 790, + ARM_SMLSD = 791, + ARM_SMLSDX = 792, + ARM_SMLSLD = 793, + ARM_SMLSLDX = 794, + ARM_SMMLA = 795, + ARM_SMMLAR = 796, + ARM_SMMLS = 797, + ARM_SMMLSR = 798, + ARM_SMMUL = 799, + ARM_SMMULR = 800, + ARM_SMUAD = 801, + ARM_SMUADX = 802, + ARM_SMULBB = 803, + ARM_SMULBT = 804, + ARM_SMULL = 805, + ARM_SMULTB = 806, + ARM_SMULTT = 807, + ARM_SMULWB = 808, + ARM_SMULWT = 809, + ARM_SMUSD = 810, + ARM_SMUSDX = 811, + ARM_SRSDA = 812, + ARM_SRSDA_UPD = 813, + ARM_SRSDB = 814, + ARM_SRSDB_UPD = 815, + ARM_SRSIA = 816, + ARM_SRSIA_UPD = 817, + ARM_SRSIB = 818, + ARM_SRSIB_UPD = 819, + ARM_SSAT = 820, + ARM_SSAT16 = 821, + ARM_SSAX = 822, + ARM_SSUB16 = 823, + ARM_SSUB8 = 824, + ARM_STC2L_OFFSET = 825, + ARM_STC2L_OPTION = 826, + ARM_STC2L_POST = 827, + ARM_STC2L_PRE = 828, + ARM_STC2_OFFSET = 829, + ARM_STC2_OPTION = 830, + ARM_STC2_POST = 831, + ARM_STC2_PRE = 832, + ARM_STCL_OFFSET = 833, + ARM_STCL_OPTION = 834, + ARM_STCL_POST = 835, + ARM_STCL_PRE = 836, + ARM_STC_OFFSET = 837, + ARM_STC_OPTION = 838, + ARM_STC_POST = 839, + ARM_STC_PRE = 840, + ARM_STL = 841, + ARM_STLB = 842, + ARM_STLEX = 843, + ARM_STLEXB = 844, + ARM_STLEXD = 845, + ARM_STLEXH = 846, + ARM_STLH = 847, + ARM_STMDA = 848, + ARM_STMDA_UPD = 849, + ARM_STMDB = 850, + ARM_STMDB_UPD = 851, + ARM_STMIA = 852, + ARM_STMIA_UPD = 853, + ARM_STMIB = 854, + ARM_STMIB_UPD = 855, + ARM_STRBT_POST_IMM = 856, + ARM_STRBT_POST_REG = 857, + ARM_STRB_POST_IMM = 858, + ARM_STRB_POST_REG = 859, + ARM_STRB_PRE_IMM = 860, + ARM_STRB_PRE_REG = 861, + ARM_STRBi12 = 862, + ARM_STRBrs = 863, + ARM_STRD = 864, + ARM_STRD_POST = 865, + ARM_STRD_PRE = 866, + ARM_STREX = 867, + ARM_STREXB = 868, + ARM_STREXD = 869, + ARM_STREXH = 870, + ARM_STRH = 871, + ARM_STRHTi = 872, + ARM_STRHTr = 873, + ARM_STRH_POST = 874, + ARM_STRH_PRE = 875, + ARM_STRT_POST_IMM = 876, + ARM_STRT_POST_REG = 877, + ARM_STR_POST_IMM = 878, + ARM_STR_POST_REG = 879, + ARM_STR_PRE_IMM = 880, + ARM_STR_PRE_REG = 881, + ARM_STRi12 = 882, + ARM_STRrs = 883, + ARM_SUBri = 884, + ARM_SUBrr = 885, + ARM_SUBrsi = 886, + ARM_SUBrsr = 887, + ARM_SVC = 888, + ARM_SWP = 889, + ARM_SWPB = 890, + ARM_SXTAB = 891, + ARM_SXTAB16 = 892, + ARM_SXTAH = 893, + ARM_SXTB = 894, + ARM_SXTB16 = 895, + ARM_SXTH = 896, + ARM_TEQri = 897, + ARM_TEQrr = 898, + ARM_TEQrsi = 899, + ARM_TEQrsr = 900, + ARM_TRAP = 901, + ARM_TRAPNaCl = 902, + ARM_TSB = 903, + ARM_TSTri = 904, + ARM_TSTrr = 905, + ARM_TSTrsi = 906, + ARM_TSTrsr = 907, + ARM_UADD16 = 908, + ARM_UADD8 = 909, + ARM_UASX = 910, + ARM_UBFX = 911, + ARM_UDF = 912, + ARM_UDIV = 913, + ARM_UHADD16 = 914, + ARM_UHADD8 = 915, + ARM_UHASX = 916, + ARM_UHSAX = 917, + ARM_UHSUB16 = 918, + ARM_UHSUB8 = 919, + ARM_UMAAL = 920, + ARM_UMLAL = 921, + ARM_UMULL = 922, + ARM_UQADD16 = 923, + ARM_UQADD8 = 924, + ARM_UQASX = 925, + ARM_UQSAX = 926, + ARM_UQSUB16 = 927, + ARM_UQSUB8 = 928, + ARM_USAD8 = 929, + ARM_USADA8 = 930, + ARM_USAT = 931, + ARM_USAT16 = 932, + ARM_USAX = 933, + ARM_USUB16 = 934, + ARM_USUB8 = 935, + ARM_UXTAB = 936, + ARM_UXTAB16 = 937, + ARM_UXTAH = 938, + ARM_UXTB = 939, + ARM_UXTB16 = 940, + ARM_UXTH = 941, + ARM_VABALsv2i64 = 942, + ARM_VABALsv4i32 = 943, + ARM_VABALsv8i16 = 944, + ARM_VABALuv2i64 = 945, + ARM_VABALuv4i32 = 946, + ARM_VABALuv8i16 = 947, + ARM_VABAsv16i8 = 948, + ARM_VABAsv2i32 = 949, + ARM_VABAsv4i16 = 950, + ARM_VABAsv4i32 = 951, + ARM_VABAsv8i16 = 952, + ARM_VABAsv8i8 = 953, + ARM_VABAuv16i8 = 954, + ARM_VABAuv2i32 = 955, + ARM_VABAuv4i16 = 956, + ARM_VABAuv4i32 = 957, + ARM_VABAuv8i16 = 958, + ARM_VABAuv8i8 = 959, + ARM_VABDLsv2i64 = 960, + ARM_VABDLsv4i32 = 961, + ARM_VABDLsv8i16 = 962, + ARM_VABDLuv2i64 = 963, + ARM_VABDLuv4i32 = 964, + ARM_VABDLuv8i16 = 965, + ARM_VABDfd = 966, + ARM_VABDfq = 967, + ARM_VABDhd = 968, + ARM_VABDhq = 969, + ARM_VABDsv16i8 = 970, + ARM_VABDsv2i32 = 971, + ARM_VABDsv4i16 = 972, + ARM_VABDsv4i32 = 973, + ARM_VABDsv8i16 = 974, + ARM_VABDsv8i8 = 975, + ARM_VABDuv16i8 = 976, + ARM_VABDuv2i32 = 977, + ARM_VABDuv4i16 = 978, + ARM_VABDuv4i32 = 979, + ARM_VABDuv8i16 = 980, + ARM_VABDuv8i8 = 981, + ARM_VABSD = 982, + ARM_VABSH = 983, + ARM_VABSS = 984, + ARM_VABSfd = 985, + ARM_VABSfq = 986, + ARM_VABShd = 987, + ARM_VABShq = 988, + ARM_VABSv16i8 = 989, + ARM_VABSv2i32 = 990, + ARM_VABSv4i16 = 991, + ARM_VABSv4i32 = 992, + ARM_VABSv8i16 = 993, + ARM_VABSv8i8 = 994, + ARM_VACGEfd = 995, + ARM_VACGEfq = 996, + ARM_VACGEhd = 997, + ARM_VACGEhq = 998, + ARM_VACGTfd = 999, + ARM_VACGTfq = 1000, + ARM_VACGThd = 1001, + ARM_VACGThq = 1002, + ARM_VADDD = 1003, + ARM_VADDH = 1004, + ARM_VADDHNv2i32 = 1005, + ARM_VADDHNv4i16 = 1006, + ARM_VADDHNv8i8 = 1007, + ARM_VADDLsv2i64 = 1008, + ARM_VADDLsv4i32 = 1009, + ARM_VADDLsv8i16 = 1010, + ARM_VADDLuv2i64 = 1011, + ARM_VADDLuv4i32 = 1012, + ARM_VADDLuv8i16 = 1013, + ARM_VADDS = 1014, + ARM_VADDWsv2i64 = 1015, + ARM_VADDWsv4i32 = 1016, + ARM_VADDWsv8i16 = 1017, + ARM_VADDWuv2i64 = 1018, + ARM_VADDWuv4i32 = 1019, + ARM_VADDWuv8i16 = 1020, + ARM_VADDfd = 1021, + ARM_VADDfq = 1022, + ARM_VADDhd = 1023, + ARM_VADDhq = 1024, + ARM_VADDv16i8 = 1025, + ARM_VADDv1i64 = 1026, + ARM_VADDv2i32 = 1027, + ARM_VADDv2i64 = 1028, + ARM_VADDv4i16 = 1029, + ARM_VADDv4i32 = 1030, + ARM_VADDv8i16 = 1031, + ARM_VADDv8i8 = 1032, + ARM_VANDd = 1033, + ARM_VANDq = 1034, + ARM_VBICd = 1035, + ARM_VBICiv2i32 = 1036, + ARM_VBICiv4i16 = 1037, + ARM_VBICiv4i32 = 1038, + ARM_VBICiv8i16 = 1039, + ARM_VBICq = 1040, + ARM_VBIFd = 1041, + ARM_VBIFq = 1042, + ARM_VBITd = 1043, + ARM_VBITq = 1044, + ARM_VBSLd = 1045, + ARM_VBSLq = 1046, + ARM_VCADDv2f32 = 1047, + ARM_VCADDv4f16 = 1048, + ARM_VCADDv4f32 = 1049, + ARM_VCADDv8f16 = 1050, + ARM_VCEQfd = 1051, + ARM_VCEQfq = 1052, + ARM_VCEQhd = 1053, + ARM_VCEQhq = 1054, + ARM_VCEQv16i8 = 1055, + ARM_VCEQv2i32 = 1056, + ARM_VCEQv4i16 = 1057, + ARM_VCEQv4i32 = 1058, + ARM_VCEQv8i16 = 1059, + ARM_VCEQv8i8 = 1060, + ARM_VCEQzv16i8 = 1061, + ARM_VCEQzv2f32 = 1062, + ARM_VCEQzv2i32 = 1063, + ARM_VCEQzv4f16 = 1064, + ARM_VCEQzv4f32 = 1065, + ARM_VCEQzv4i16 = 1066, + ARM_VCEQzv4i32 = 1067, + ARM_VCEQzv8f16 = 1068, + ARM_VCEQzv8i16 = 1069, + ARM_VCEQzv8i8 = 1070, + ARM_VCGEfd = 1071, + ARM_VCGEfq = 1072, + ARM_VCGEhd = 1073, + ARM_VCGEhq = 1074, + ARM_VCGEsv16i8 = 1075, + ARM_VCGEsv2i32 = 1076, + ARM_VCGEsv4i16 = 1077, + ARM_VCGEsv4i32 = 1078, + ARM_VCGEsv8i16 = 1079, + ARM_VCGEsv8i8 = 1080, + ARM_VCGEuv16i8 = 1081, + ARM_VCGEuv2i32 = 1082, + ARM_VCGEuv4i16 = 1083, + ARM_VCGEuv4i32 = 1084, + ARM_VCGEuv8i16 = 1085, + ARM_VCGEuv8i8 = 1086, + ARM_VCGEzv16i8 = 1087, + ARM_VCGEzv2f32 = 1088, + ARM_VCGEzv2i32 = 1089, + ARM_VCGEzv4f16 = 1090, + ARM_VCGEzv4f32 = 1091, + ARM_VCGEzv4i16 = 1092, + ARM_VCGEzv4i32 = 1093, + ARM_VCGEzv8f16 = 1094, + ARM_VCGEzv8i16 = 1095, + ARM_VCGEzv8i8 = 1096, + ARM_VCGTfd = 1097, + ARM_VCGTfq = 1098, + ARM_VCGThd = 1099, + ARM_VCGThq = 1100, + ARM_VCGTsv16i8 = 1101, + ARM_VCGTsv2i32 = 1102, + ARM_VCGTsv4i16 = 1103, + ARM_VCGTsv4i32 = 1104, + ARM_VCGTsv8i16 = 1105, + ARM_VCGTsv8i8 = 1106, + ARM_VCGTuv16i8 = 1107, + ARM_VCGTuv2i32 = 1108, + ARM_VCGTuv4i16 = 1109, + ARM_VCGTuv4i32 = 1110, + ARM_VCGTuv8i16 = 1111, + ARM_VCGTuv8i8 = 1112, + ARM_VCGTzv16i8 = 1113, + ARM_VCGTzv2f32 = 1114, + ARM_VCGTzv2i32 = 1115, + ARM_VCGTzv4f16 = 1116, + ARM_VCGTzv4f32 = 1117, + ARM_VCGTzv4i16 = 1118, + ARM_VCGTzv4i32 = 1119, + ARM_VCGTzv8f16 = 1120, + ARM_VCGTzv8i16 = 1121, + ARM_VCGTzv8i8 = 1122, + ARM_VCLEzv16i8 = 1123, + ARM_VCLEzv2f32 = 1124, + ARM_VCLEzv2i32 = 1125, + ARM_VCLEzv4f16 = 1126, + ARM_VCLEzv4f32 = 1127, + ARM_VCLEzv4i16 = 1128, + ARM_VCLEzv4i32 = 1129, + ARM_VCLEzv8f16 = 1130, + ARM_VCLEzv8i16 = 1131, + ARM_VCLEzv8i8 = 1132, + ARM_VCLSv16i8 = 1133, + ARM_VCLSv2i32 = 1134, + ARM_VCLSv4i16 = 1135, + ARM_VCLSv4i32 = 1136, + ARM_VCLSv8i16 = 1137, + ARM_VCLSv8i8 = 1138, + ARM_VCLTzv16i8 = 1139, + ARM_VCLTzv2f32 = 1140, + ARM_VCLTzv2i32 = 1141, + ARM_VCLTzv4f16 = 1142, + ARM_VCLTzv4f32 = 1143, + ARM_VCLTzv4i16 = 1144, + ARM_VCLTzv4i32 = 1145, + ARM_VCLTzv8f16 = 1146, + ARM_VCLTzv8i16 = 1147, + ARM_VCLTzv8i8 = 1148, + ARM_VCLZv16i8 = 1149, + ARM_VCLZv2i32 = 1150, + ARM_VCLZv4i16 = 1151, + ARM_VCLZv4i32 = 1152, + ARM_VCLZv8i16 = 1153, + ARM_VCLZv8i8 = 1154, + ARM_VCMLAv2f32 = 1155, + ARM_VCMLAv2f32_indexed = 1156, + ARM_VCMLAv4f16 = 1157, + ARM_VCMLAv4f16_indexed = 1158, + ARM_VCMLAv4f32 = 1159, + ARM_VCMLAv4f32_indexed = 1160, + ARM_VCMLAv8f16 = 1161, + ARM_VCMLAv8f16_indexed = 1162, + ARM_VCMPD = 1163, + ARM_VCMPED = 1164, + ARM_VCMPEH = 1165, + ARM_VCMPES = 1166, + ARM_VCMPEZD = 1167, + ARM_VCMPEZH = 1168, + ARM_VCMPEZS = 1169, + ARM_VCMPH = 1170, + ARM_VCMPS = 1171, + ARM_VCMPZD = 1172, + ARM_VCMPZH = 1173, + ARM_VCMPZS = 1174, + ARM_VCNTd = 1175, + ARM_VCNTq = 1176, + ARM_VCVTANSDf = 1177, + ARM_VCVTANSDh = 1178, + ARM_VCVTANSQf = 1179, + ARM_VCVTANSQh = 1180, + ARM_VCVTANUDf = 1181, + ARM_VCVTANUDh = 1182, + ARM_VCVTANUQf = 1183, + ARM_VCVTANUQh = 1184, + ARM_VCVTASD = 1185, + ARM_VCVTASH = 1186, + ARM_VCVTASS = 1187, + ARM_VCVTAUD = 1188, + ARM_VCVTAUH = 1189, + ARM_VCVTAUS = 1190, + ARM_VCVTBDH = 1191, + ARM_VCVTBHD = 1192, + ARM_VCVTBHS = 1193, + ARM_VCVTBSH = 1194, + ARM_VCVTDS = 1195, + ARM_VCVTMNSDf = 1196, + ARM_VCVTMNSDh = 1197, + ARM_VCVTMNSQf = 1198, + ARM_VCVTMNSQh = 1199, + ARM_VCVTMNUDf = 1200, + ARM_VCVTMNUDh = 1201, + ARM_VCVTMNUQf = 1202, + ARM_VCVTMNUQh = 1203, + ARM_VCVTMSD = 1204, + ARM_VCVTMSH = 1205, + ARM_VCVTMSS = 1206, + ARM_VCVTMUD = 1207, + ARM_VCVTMUH = 1208, + ARM_VCVTMUS = 1209, + ARM_VCVTNNSDf = 1210, + ARM_VCVTNNSDh = 1211, + ARM_VCVTNNSQf = 1212, + ARM_VCVTNNSQh = 1213, + ARM_VCVTNNUDf = 1214, + ARM_VCVTNNUDh = 1215, + ARM_VCVTNNUQf = 1216, + ARM_VCVTNNUQh = 1217, + ARM_VCVTNSD = 1218, + ARM_VCVTNSH = 1219, + ARM_VCVTNSS = 1220, + ARM_VCVTNUD = 1221, + ARM_VCVTNUH = 1222, + ARM_VCVTNUS = 1223, + ARM_VCVTPNSDf = 1224, + ARM_VCVTPNSDh = 1225, + ARM_VCVTPNSQf = 1226, + ARM_VCVTPNSQh = 1227, + ARM_VCVTPNUDf = 1228, + ARM_VCVTPNUDh = 1229, + ARM_VCVTPNUQf = 1230, + ARM_VCVTPNUQh = 1231, + ARM_VCVTPSD = 1232, + ARM_VCVTPSH = 1233, + ARM_VCVTPSS = 1234, + ARM_VCVTPUD = 1235, + ARM_VCVTPUH = 1236, + ARM_VCVTPUS = 1237, + ARM_VCVTSD = 1238, + ARM_VCVTTDH = 1239, + ARM_VCVTTHD = 1240, + ARM_VCVTTHS = 1241, + ARM_VCVTTSH = 1242, + ARM_VCVTf2h = 1243, + ARM_VCVTf2sd = 1244, + ARM_VCVTf2sq = 1245, + ARM_VCVTf2ud = 1246, + ARM_VCVTf2uq = 1247, + ARM_VCVTf2xsd = 1248, + ARM_VCVTf2xsq = 1249, + ARM_VCVTf2xud = 1250, + ARM_VCVTf2xuq = 1251, + ARM_VCVTh2f = 1252, + ARM_VCVTh2sd = 1253, + ARM_VCVTh2sq = 1254, + ARM_VCVTh2ud = 1255, + ARM_VCVTh2uq = 1256, + ARM_VCVTh2xsd = 1257, + ARM_VCVTh2xsq = 1258, + ARM_VCVTh2xud = 1259, + ARM_VCVTh2xuq = 1260, + ARM_VCVTs2fd = 1261, + ARM_VCVTs2fq = 1262, + ARM_VCVTs2hd = 1263, + ARM_VCVTs2hq = 1264, + ARM_VCVTu2fd = 1265, + ARM_VCVTu2fq = 1266, + ARM_VCVTu2hd = 1267, + ARM_VCVTu2hq = 1268, + ARM_VCVTxs2fd = 1269, + ARM_VCVTxs2fq = 1270, + ARM_VCVTxs2hd = 1271, + ARM_VCVTxs2hq = 1272, + ARM_VCVTxu2fd = 1273, + ARM_VCVTxu2fq = 1274, + ARM_VCVTxu2hd = 1275, + ARM_VCVTxu2hq = 1276, + ARM_VDIVD = 1277, + ARM_VDIVH = 1278, + ARM_VDIVS = 1279, + ARM_VDUP16d = 1280, + ARM_VDUP16q = 1281, + ARM_VDUP32d = 1282, + ARM_VDUP32q = 1283, + ARM_VDUP8d = 1284, + ARM_VDUP8q = 1285, + ARM_VDUPLN16d = 1286, + ARM_VDUPLN16q = 1287, + ARM_VDUPLN32d = 1288, + ARM_VDUPLN32q = 1289, + ARM_VDUPLN8d = 1290, + ARM_VDUPLN8q = 1291, + ARM_VEORd = 1292, + ARM_VEORq = 1293, + ARM_VEXTd16 = 1294, + ARM_VEXTd32 = 1295, + ARM_VEXTd8 = 1296, + ARM_VEXTq16 = 1297, + ARM_VEXTq32 = 1298, + ARM_VEXTq64 = 1299, + ARM_VEXTq8 = 1300, + ARM_VFMAD = 1301, + ARM_VFMAH = 1302, + ARM_VFMAS = 1303, + ARM_VFMAfd = 1304, + ARM_VFMAfq = 1305, + ARM_VFMAhd = 1306, + ARM_VFMAhq = 1307, + ARM_VFMSD = 1308, + ARM_VFMSH = 1309, + ARM_VFMSS = 1310, + ARM_VFMSfd = 1311, + ARM_VFMSfq = 1312, + ARM_VFMShd = 1313, + ARM_VFMShq = 1314, + ARM_VFNMAD = 1315, + ARM_VFNMAH = 1316, + ARM_VFNMAS = 1317, + ARM_VFNMSD = 1318, + ARM_VFNMSH = 1319, + ARM_VFNMSS = 1320, + ARM_VGETLNi32 = 1321, + ARM_VGETLNs16 = 1322, + ARM_VGETLNs8 = 1323, + ARM_VGETLNu16 = 1324, + ARM_VGETLNu8 = 1325, + ARM_VHADDsv16i8 = 1326, + ARM_VHADDsv2i32 = 1327, + ARM_VHADDsv4i16 = 1328, + ARM_VHADDsv4i32 = 1329, + ARM_VHADDsv8i16 = 1330, + ARM_VHADDsv8i8 = 1331, + ARM_VHADDuv16i8 = 1332, + ARM_VHADDuv2i32 = 1333, + ARM_VHADDuv4i16 = 1334, + ARM_VHADDuv4i32 = 1335, + ARM_VHADDuv8i16 = 1336, + ARM_VHADDuv8i8 = 1337, + ARM_VHSUBsv16i8 = 1338, + ARM_VHSUBsv2i32 = 1339, + ARM_VHSUBsv4i16 = 1340, + ARM_VHSUBsv4i32 = 1341, + ARM_VHSUBsv8i16 = 1342, + ARM_VHSUBsv8i8 = 1343, + ARM_VHSUBuv16i8 = 1344, + ARM_VHSUBuv2i32 = 1345, + ARM_VHSUBuv4i16 = 1346, + ARM_VHSUBuv4i32 = 1347, + ARM_VHSUBuv8i16 = 1348, + ARM_VHSUBuv8i8 = 1349, + ARM_VINSH = 1350, + ARM_VJCVT = 1351, + ARM_VLD1DUPd16 = 1352, + ARM_VLD1DUPd16wb_fixed = 1353, + ARM_VLD1DUPd16wb_register = 1354, + ARM_VLD1DUPd32 = 1355, + ARM_VLD1DUPd32wb_fixed = 1356, + ARM_VLD1DUPd32wb_register = 1357, + ARM_VLD1DUPd8 = 1358, + ARM_VLD1DUPd8wb_fixed = 1359, + ARM_VLD1DUPd8wb_register = 1360, + ARM_VLD1DUPq16 = 1361, + ARM_VLD1DUPq16wb_fixed = 1362, + ARM_VLD1DUPq16wb_register = 1363, + ARM_VLD1DUPq32 = 1364, + ARM_VLD1DUPq32wb_fixed = 1365, + ARM_VLD1DUPq32wb_register = 1366, + ARM_VLD1DUPq8 = 1367, + ARM_VLD1DUPq8wb_fixed = 1368, + ARM_VLD1DUPq8wb_register = 1369, + ARM_VLD1LNd16 = 1370, + ARM_VLD1LNd16_UPD = 1371, + ARM_VLD1LNd32 = 1372, + ARM_VLD1LNd32_UPD = 1373, + ARM_VLD1LNd8 = 1374, + ARM_VLD1LNd8_UPD = 1375, + ARM_VLD1d16 = 1382, + ARM_VLD1d16Q = 1383, + ARM_VLD1d16Qwb_fixed = 1385, + ARM_VLD1d16Qwb_register = 1386, + ARM_VLD1d16T = 1387, + ARM_VLD1d16Twb_fixed = 1389, + ARM_VLD1d16Twb_register = 1390, + ARM_VLD1d16wb_fixed = 1391, + ARM_VLD1d16wb_register = 1392, + ARM_VLD1d32 = 1393, + ARM_VLD1d32Q = 1394, + ARM_VLD1d32Qwb_fixed = 1396, + ARM_VLD1d32Qwb_register = 1397, + ARM_VLD1d32T = 1398, + ARM_VLD1d32Twb_fixed = 1400, + ARM_VLD1d32Twb_register = 1401, + ARM_VLD1d32wb_fixed = 1402, + ARM_VLD1d32wb_register = 1403, + ARM_VLD1d64 = 1404, + ARM_VLD1d64Q = 1405, + ARM_VLD1d64Qwb_fixed = 1409, + ARM_VLD1d64Qwb_register = 1410, + ARM_VLD1d64T = 1411, + ARM_VLD1d64Twb_fixed = 1415, + ARM_VLD1d64Twb_register = 1416, + ARM_VLD1d64wb_fixed = 1417, + ARM_VLD1d64wb_register = 1418, + ARM_VLD1d8 = 1419, + ARM_VLD1d8Q = 1420, + ARM_VLD1d8Qwb_fixed = 1422, + ARM_VLD1d8Qwb_register = 1423, + ARM_VLD1d8T = 1424, + ARM_VLD1d8Twb_fixed = 1426, + ARM_VLD1d8Twb_register = 1427, + ARM_VLD1d8wb_fixed = 1428, + ARM_VLD1d8wb_register = 1429, + ARM_VLD1q16 = 1430, + ARM_VLD1q16wb_fixed = 1435, + ARM_VLD1q16wb_register = 1436, + ARM_VLD1q32 = 1437, + ARM_VLD1q32wb_fixed = 1442, + ARM_VLD1q32wb_register = 1443, + ARM_VLD1q64 = 1444, + ARM_VLD1q64wb_fixed = 1449, + ARM_VLD1q64wb_register = 1450, + ARM_VLD1q8 = 1451, + ARM_VLD1q8wb_fixed = 1456, + ARM_VLD1q8wb_register = 1457, + ARM_VLD2DUPd16 = 1458, + ARM_VLD2DUPd16wb_fixed = 1459, + ARM_VLD2DUPd16wb_register = 1460, + ARM_VLD2DUPd16x2 = 1461, + ARM_VLD2DUPd16x2wb_fixed = 1462, + ARM_VLD2DUPd16x2wb_register = 1463, + ARM_VLD2DUPd32 = 1464, + ARM_VLD2DUPd32wb_fixed = 1465, + ARM_VLD2DUPd32wb_register = 1466, + ARM_VLD2DUPd32x2 = 1467, + ARM_VLD2DUPd32x2wb_fixed = 1468, + ARM_VLD2DUPd32x2wb_register = 1469, + ARM_VLD2DUPd8 = 1470, + ARM_VLD2DUPd8wb_fixed = 1471, + ARM_VLD2DUPd8wb_register = 1472, + ARM_VLD2DUPd8x2 = 1473, + ARM_VLD2DUPd8x2wb_fixed = 1474, + ARM_VLD2DUPd8x2wb_register = 1475, + ARM_VLD2LNd16 = 1482, + ARM_VLD2LNd16_UPD = 1485, + ARM_VLD2LNd32 = 1486, + ARM_VLD2LNd32_UPD = 1489, + ARM_VLD2LNd8 = 1490, + ARM_VLD2LNd8_UPD = 1493, + ARM_VLD2LNq16 = 1494, + ARM_VLD2LNq16_UPD = 1497, + ARM_VLD2LNq32 = 1498, + ARM_VLD2LNq32_UPD = 1501, + ARM_VLD2b16 = 1502, + ARM_VLD2b16wb_fixed = 1503, + ARM_VLD2b16wb_register = 1504, + ARM_VLD2b32 = 1505, + ARM_VLD2b32wb_fixed = 1506, + ARM_VLD2b32wb_register = 1507, + ARM_VLD2b8 = 1508, + ARM_VLD2b8wb_fixed = 1509, + ARM_VLD2b8wb_register = 1510, + ARM_VLD2d16 = 1511, + ARM_VLD2d16wb_fixed = 1512, + ARM_VLD2d16wb_register = 1513, + ARM_VLD2d32 = 1514, + ARM_VLD2d32wb_fixed = 1515, + ARM_VLD2d32wb_register = 1516, + ARM_VLD2d8 = 1517, + ARM_VLD2d8wb_fixed = 1518, + ARM_VLD2d8wb_register = 1519, + ARM_VLD2q16 = 1520, + ARM_VLD2q16wb_fixed = 1524, + ARM_VLD2q16wb_register = 1525, + ARM_VLD2q32 = 1526, + ARM_VLD2q32wb_fixed = 1530, + ARM_VLD2q32wb_register = 1531, + ARM_VLD2q8 = 1532, + ARM_VLD2q8wb_fixed = 1536, + ARM_VLD2q8wb_register = 1537, + ARM_VLD3DUPd16 = 1538, + ARM_VLD3DUPd16_UPD = 1541, + ARM_VLD3DUPd32 = 1542, + ARM_VLD3DUPd32_UPD = 1545, + ARM_VLD3DUPd8 = 1546, + ARM_VLD3DUPd8_UPD = 1549, + ARM_VLD3DUPq16 = 1550, + ARM_VLD3DUPq16_UPD = 1553, + ARM_VLD3DUPq32 = 1554, + ARM_VLD3DUPq32_UPD = 1557, + ARM_VLD3DUPq8 = 1558, + ARM_VLD3DUPq8_UPD = 1561, + ARM_VLD3LNd16 = 1562, + ARM_VLD3LNd16_UPD = 1565, + ARM_VLD3LNd32 = 1566, + ARM_VLD3LNd32_UPD = 1569, + ARM_VLD3LNd8 = 1570, + ARM_VLD3LNd8_UPD = 1573, + ARM_VLD3LNq16 = 1574, + ARM_VLD3LNq16_UPD = 1577, + ARM_VLD3LNq32 = 1578, + ARM_VLD3LNq32_UPD = 1581, + ARM_VLD3d16 = 1582, + ARM_VLD3d16_UPD = 1585, + ARM_VLD3d32 = 1586, + ARM_VLD3d32_UPD = 1589, + ARM_VLD3d8 = 1590, + ARM_VLD3d8_UPD = 1593, + ARM_VLD3q16 = 1594, + ARM_VLD3q16_UPD = 1596, + ARM_VLD3q32 = 1599, + ARM_VLD3q32_UPD = 1601, + ARM_VLD3q8 = 1604, + ARM_VLD3q8_UPD = 1606, + ARM_VLD4DUPd16 = 1609, + ARM_VLD4DUPd16_UPD = 1612, + ARM_VLD4DUPd32 = 1613, + ARM_VLD4DUPd32_UPD = 1616, + ARM_VLD4DUPd8 = 1617, + ARM_VLD4DUPd8_UPD = 1620, + ARM_VLD4DUPq16 = 1621, + ARM_VLD4DUPq16_UPD = 1624, + ARM_VLD4DUPq32 = 1625, + ARM_VLD4DUPq32_UPD = 1628, + ARM_VLD4DUPq8 = 1629, + ARM_VLD4DUPq8_UPD = 1632, + ARM_VLD4LNd16 = 1633, + ARM_VLD4LNd16_UPD = 1636, + ARM_VLD4LNd32 = 1637, + ARM_VLD4LNd32_UPD = 1640, + ARM_VLD4LNd8 = 1641, + ARM_VLD4LNd8_UPD = 1644, + ARM_VLD4LNq16 = 1645, + ARM_VLD4LNq16_UPD = 1648, + ARM_VLD4LNq32 = 1649, + ARM_VLD4LNq32_UPD = 1652, + ARM_VLD4d16 = 1653, + ARM_VLD4d16_UPD = 1656, + ARM_VLD4d32 = 1657, + ARM_VLD4d32_UPD = 1660, + ARM_VLD4d8 = 1661, + ARM_VLD4d8_UPD = 1664, + ARM_VLD4q16 = 1665, + ARM_VLD4q16_UPD = 1667, + ARM_VLD4q32 = 1670, + ARM_VLD4q32_UPD = 1672, + ARM_VLD4q8 = 1675, + ARM_VLD4q8_UPD = 1677, + ARM_VLDMDDB_UPD = 1680, + ARM_VLDMDIA = 1681, + ARM_VLDMDIA_UPD = 1682, + ARM_VLDMQIA = 1683, + ARM_VLDMSDB_UPD = 1684, + ARM_VLDMSIA = 1685, + ARM_VLDMSIA_UPD = 1686, + ARM_VLDRD = 1687, + ARM_VLDRH = 1688, + ARM_VLDRS = 1689, + ARM_VLLDM = 1690, + ARM_VLSTM = 1691, + ARM_VMAXNMD = 1692, + ARM_VMAXNMH = 1693, + ARM_VMAXNMNDf = 1694, + ARM_VMAXNMNDh = 1695, + ARM_VMAXNMNQf = 1696, + ARM_VMAXNMNQh = 1697, + ARM_VMAXNMS = 1698, + ARM_VMAXfd = 1699, + ARM_VMAXfq = 1700, + ARM_VMAXhd = 1701, + ARM_VMAXhq = 1702, + ARM_VMAXsv16i8 = 1703, + ARM_VMAXsv2i32 = 1704, + ARM_VMAXsv4i16 = 1705, + ARM_VMAXsv4i32 = 1706, + ARM_VMAXsv8i16 = 1707, + ARM_VMAXsv8i8 = 1708, + ARM_VMAXuv16i8 = 1709, + ARM_VMAXuv2i32 = 1710, + ARM_VMAXuv4i16 = 1711, + ARM_VMAXuv4i32 = 1712, + ARM_VMAXuv8i16 = 1713, + ARM_VMAXuv8i8 = 1714, + ARM_VMINNMD = 1715, + ARM_VMINNMH = 1716, + ARM_VMINNMNDf = 1717, + ARM_VMINNMNDh = 1718, + ARM_VMINNMNQf = 1719, + ARM_VMINNMNQh = 1720, + ARM_VMINNMS = 1721, + ARM_VMINfd = 1722, + ARM_VMINfq = 1723, + ARM_VMINhd = 1724, + ARM_VMINhq = 1725, + ARM_VMINsv16i8 = 1726, + ARM_VMINsv2i32 = 1727, + ARM_VMINsv4i16 = 1728, + ARM_VMINsv4i32 = 1729, + ARM_VMINsv8i16 = 1730, + ARM_VMINsv8i8 = 1731, + ARM_VMINuv16i8 = 1732, + ARM_VMINuv2i32 = 1733, + ARM_VMINuv4i16 = 1734, + ARM_VMINuv4i32 = 1735, + ARM_VMINuv8i16 = 1736, + ARM_VMINuv8i8 = 1737, + ARM_VMLAD = 1738, + ARM_VMLAH = 1739, + ARM_VMLALslsv2i32 = 1740, + ARM_VMLALslsv4i16 = 1741, + ARM_VMLALsluv2i32 = 1742, + ARM_VMLALsluv4i16 = 1743, + ARM_VMLALsv2i64 = 1744, + ARM_VMLALsv4i32 = 1745, + ARM_VMLALsv8i16 = 1746, + ARM_VMLALuv2i64 = 1747, + ARM_VMLALuv4i32 = 1748, + ARM_VMLALuv8i16 = 1749, + ARM_VMLAS = 1750, + ARM_VMLAfd = 1751, + ARM_VMLAfq = 1752, + ARM_VMLAhd = 1753, + ARM_VMLAhq = 1754, + ARM_VMLAslfd = 1755, + ARM_VMLAslfq = 1756, + ARM_VMLAslhd = 1757, + ARM_VMLAslhq = 1758, + ARM_VMLAslv2i32 = 1759, + ARM_VMLAslv4i16 = 1760, + ARM_VMLAslv4i32 = 1761, + ARM_VMLAslv8i16 = 1762, + ARM_VMLAv16i8 = 1763, + ARM_VMLAv2i32 = 1764, + ARM_VMLAv4i16 = 1765, + ARM_VMLAv4i32 = 1766, + ARM_VMLAv8i16 = 1767, + ARM_VMLAv8i8 = 1768, + ARM_VMLSD = 1769, + ARM_VMLSH = 1770, + ARM_VMLSLslsv2i32 = 1771, + ARM_VMLSLslsv4i16 = 1772, + ARM_VMLSLsluv2i32 = 1773, + ARM_VMLSLsluv4i16 = 1774, + ARM_VMLSLsv2i64 = 1775, + ARM_VMLSLsv4i32 = 1776, + ARM_VMLSLsv8i16 = 1777, + ARM_VMLSLuv2i64 = 1778, + ARM_VMLSLuv4i32 = 1779, + ARM_VMLSLuv8i16 = 1780, + ARM_VMLSS = 1781, + ARM_VMLSfd = 1782, + ARM_VMLSfq = 1783, + ARM_VMLShd = 1784, + ARM_VMLShq = 1785, + ARM_VMLSslfd = 1786, + ARM_VMLSslfq = 1787, + ARM_VMLSslhd = 1788, + ARM_VMLSslhq = 1789, + ARM_VMLSslv2i32 = 1790, + ARM_VMLSslv4i16 = 1791, + ARM_VMLSslv4i32 = 1792, + ARM_VMLSslv8i16 = 1793, + ARM_VMLSv16i8 = 1794, + ARM_VMLSv2i32 = 1795, + ARM_VMLSv4i16 = 1796, + ARM_VMLSv4i32 = 1797, + ARM_VMLSv8i16 = 1798, + ARM_VMLSv8i8 = 1799, + ARM_VMOVD = 1800, + ARM_VMOVDRR = 1801, + ARM_VMOVH = 1802, + ARM_VMOVHR = 1803, + ARM_VMOVLsv2i64 = 1804, + ARM_VMOVLsv4i32 = 1805, + ARM_VMOVLsv8i16 = 1806, + ARM_VMOVLuv2i64 = 1807, + ARM_VMOVLuv4i32 = 1808, + ARM_VMOVLuv8i16 = 1809, + ARM_VMOVNv2i32 = 1810, + ARM_VMOVNv4i16 = 1811, + ARM_VMOVNv8i8 = 1812, + ARM_VMOVRH = 1813, + ARM_VMOVRRD = 1814, + ARM_VMOVRRS = 1815, + ARM_VMOVRS = 1816, + ARM_VMOVS = 1817, + ARM_VMOVSR = 1818, + ARM_VMOVSRR = 1819, + ARM_VMOVv16i8 = 1820, + ARM_VMOVv1i64 = 1821, + ARM_VMOVv2f32 = 1822, + ARM_VMOVv2i32 = 1823, + ARM_VMOVv2i64 = 1824, + ARM_VMOVv4f32 = 1825, + ARM_VMOVv4i16 = 1826, + ARM_VMOVv4i32 = 1827, + ARM_VMOVv8i16 = 1828, + ARM_VMOVv8i8 = 1829, + ARM_VMRS = 1830, + ARM_VMRS_FPEXC = 1831, + ARM_VMRS_FPINST = 1832, + ARM_VMRS_FPINST2 = 1833, + ARM_VMRS_FPSID = 1834, + ARM_VMRS_MVFR0 = 1835, + ARM_VMRS_MVFR1 = 1836, + ARM_VMRS_MVFR2 = 1837, + ARM_VMSR = 1838, + ARM_VMSR_FPEXC = 1839, + ARM_VMSR_FPINST = 1840, + ARM_VMSR_FPINST2 = 1841, + ARM_VMSR_FPSID = 1842, + ARM_VMULD = 1843, + ARM_VMULH = 1844, + ARM_VMULLp64 = 1845, + ARM_VMULLp8 = 1846, + ARM_VMULLslsv2i32 = 1847, + ARM_VMULLslsv4i16 = 1848, + ARM_VMULLsluv2i32 = 1849, + ARM_VMULLsluv4i16 = 1850, + ARM_VMULLsv2i64 = 1851, + ARM_VMULLsv4i32 = 1852, + ARM_VMULLsv8i16 = 1853, + ARM_VMULLuv2i64 = 1854, + ARM_VMULLuv4i32 = 1855, + ARM_VMULLuv8i16 = 1856, + ARM_VMULS = 1857, + ARM_VMULfd = 1858, + ARM_VMULfq = 1859, + ARM_VMULhd = 1860, + ARM_VMULhq = 1861, + ARM_VMULpd = 1862, + ARM_VMULpq = 1863, + ARM_VMULslfd = 1864, + ARM_VMULslfq = 1865, + ARM_VMULslhd = 1866, + ARM_VMULslhq = 1867, + ARM_VMULslv2i32 = 1868, + ARM_VMULslv4i16 = 1869, + ARM_VMULslv4i32 = 1870, + ARM_VMULslv8i16 = 1871, + ARM_VMULv16i8 = 1872, + ARM_VMULv2i32 = 1873, + ARM_VMULv4i16 = 1874, + ARM_VMULv4i32 = 1875, + ARM_VMULv8i16 = 1876, + ARM_VMULv8i8 = 1877, + ARM_VMVNd = 1878, + ARM_VMVNq = 1879, + ARM_VMVNv2i32 = 1880, + ARM_VMVNv4i16 = 1881, + ARM_VMVNv4i32 = 1882, + ARM_VMVNv8i16 = 1883, + ARM_VNEGD = 1884, + ARM_VNEGH = 1885, + ARM_VNEGS = 1886, + ARM_VNEGf32q = 1887, + ARM_VNEGfd = 1888, + ARM_VNEGhd = 1889, + ARM_VNEGhq = 1890, + ARM_VNEGs16d = 1891, + ARM_VNEGs16q = 1892, + ARM_VNEGs32d = 1893, + ARM_VNEGs32q = 1894, + ARM_VNEGs8d = 1895, + ARM_VNEGs8q = 1896, + ARM_VNMLAD = 1897, + ARM_VNMLAH = 1898, + ARM_VNMLAS = 1899, + ARM_VNMLSD = 1900, + ARM_VNMLSH = 1901, + ARM_VNMLSS = 1902, + ARM_VNMULD = 1903, + ARM_VNMULH = 1904, + ARM_VNMULS = 1905, + ARM_VORNd = 1906, + ARM_VORNq = 1907, + ARM_VORRd = 1908, + ARM_VORRiv2i32 = 1909, + ARM_VORRiv4i16 = 1910, + ARM_VORRiv4i32 = 1911, + ARM_VORRiv8i16 = 1912, + ARM_VORRq = 1913, + ARM_VPADALsv16i8 = 1914, + ARM_VPADALsv2i32 = 1915, + ARM_VPADALsv4i16 = 1916, + ARM_VPADALsv4i32 = 1917, + ARM_VPADALsv8i16 = 1918, + ARM_VPADALsv8i8 = 1919, + ARM_VPADALuv16i8 = 1920, + ARM_VPADALuv2i32 = 1921, + ARM_VPADALuv4i16 = 1922, + ARM_VPADALuv4i32 = 1923, + ARM_VPADALuv8i16 = 1924, + ARM_VPADALuv8i8 = 1925, + ARM_VPADDLsv16i8 = 1926, + ARM_VPADDLsv2i32 = 1927, + ARM_VPADDLsv4i16 = 1928, + ARM_VPADDLsv4i32 = 1929, + ARM_VPADDLsv8i16 = 1930, + ARM_VPADDLsv8i8 = 1931, + ARM_VPADDLuv16i8 = 1932, + ARM_VPADDLuv2i32 = 1933, + ARM_VPADDLuv4i16 = 1934, + ARM_VPADDLuv4i32 = 1935, + ARM_VPADDLuv8i16 = 1936, + ARM_VPADDLuv8i8 = 1937, + ARM_VPADDf = 1938, + ARM_VPADDh = 1939, + ARM_VPADDi16 = 1940, + ARM_VPADDi32 = 1941, + ARM_VPADDi8 = 1942, + ARM_VPMAXf = 1943, + ARM_VPMAXh = 1944, + ARM_VPMAXs16 = 1945, + ARM_VPMAXs32 = 1946, + ARM_VPMAXs8 = 1947, + ARM_VPMAXu16 = 1948, + ARM_VPMAXu32 = 1949, + ARM_VPMAXu8 = 1950, + ARM_VPMINf = 1951, + ARM_VPMINh = 1952, + ARM_VPMINs16 = 1953, + ARM_VPMINs32 = 1954, + ARM_VPMINs8 = 1955, + ARM_VPMINu16 = 1956, + ARM_VPMINu32 = 1957, + ARM_VPMINu8 = 1958, + ARM_VQABSv16i8 = 1959, + ARM_VQABSv2i32 = 1960, + ARM_VQABSv4i16 = 1961, + ARM_VQABSv4i32 = 1962, + ARM_VQABSv8i16 = 1963, + ARM_VQABSv8i8 = 1964, + ARM_VQADDsv16i8 = 1965, + ARM_VQADDsv1i64 = 1966, + ARM_VQADDsv2i32 = 1967, + ARM_VQADDsv2i64 = 1968, + ARM_VQADDsv4i16 = 1969, + ARM_VQADDsv4i32 = 1970, + ARM_VQADDsv8i16 = 1971, + ARM_VQADDsv8i8 = 1972, + ARM_VQADDuv16i8 = 1973, + ARM_VQADDuv1i64 = 1974, + ARM_VQADDuv2i32 = 1975, + ARM_VQADDuv2i64 = 1976, + ARM_VQADDuv4i16 = 1977, + ARM_VQADDuv4i32 = 1978, + ARM_VQADDuv8i16 = 1979, + ARM_VQADDuv8i8 = 1980, + ARM_VQDMLALslv2i32 = 1981, + ARM_VQDMLALslv4i16 = 1982, + ARM_VQDMLALv2i64 = 1983, + ARM_VQDMLALv4i32 = 1984, + ARM_VQDMLSLslv2i32 = 1985, + ARM_VQDMLSLslv4i16 = 1986, + ARM_VQDMLSLv2i64 = 1987, + ARM_VQDMLSLv4i32 = 1988, + ARM_VQDMULHslv2i32 = 1989, + ARM_VQDMULHslv4i16 = 1990, + ARM_VQDMULHslv4i32 = 1991, + ARM_VQDMULHslv8i16 = 1992, + ARM_VQDMULHv2i32 = 1993, + ARM_VQDMULHv4i16 = 1994, + ARM_VQDMULHv4i32 = 1995, + ARM_VQDMULHv8i16 = 1996, + ARM_VQDMULLslv2i32 = 1997, + ARM_VQDMULLslv4i16 = 1998, + ARM_VQDMULLv2i64 = 1999, + ARM_VQDMULLv4i32 = 2000, + ARM_VQMOVNsuv2i32 = 2001, + ARM_VQMOVNsuv4i16 = 2002, + ARM_VQMOVNsuv8i8 = 2003, + ARM_VQMOVNsv2i32 = 2004, + ARM_VQMOVNsv4i16 = 2005, + ARM_VQMOVNsv8i8 = 2006, + ARM_VQMOVNuv2i32 = 2007, + ARM_VQMOVNuv4i16 = 2008, + ARM_VQMOVNuv8i8 = 2009, + ARM_VQNEGv16i8 = 2010, + ARM_VQNEGv2i32 = 2011, + ARM_VQNEGv4i16 = 2012, + ARM_VQNEGv4i32 = 2013, + ARM_VQNEGv8i16 = 2014, + ARM_VQNEGv8i8 = 2015, + ARM_VQRDMLAHslv2i32 = 2016, + ARM_VQRDMLAHslv4i16 = 2017, + ARM_VQRDMLAHslv4i32 = 2018, + ARM_VQRDMLAHslv8i16 = 2019, + ARM_VQRDMLAHv2i32 = 2020, + ARM_VQRDMLAHv4i16 = 2021, + ARM_VQRDMLAHv4i32 = 2022, + ARM_VQRDMLAHv8i16 = 2023, + ARM_VQRDMLSHslv2i32 = 2024, + ARM_VQRDMLSHslv4i16 = 2025, + ARM_VQRDMLSHslv4i32 = 2026, + ARM_VQRDMLSHslv8i16 = 2027, + ARM_VQRDMLSHv2i32 = 2028, + ARM_VQRDMLSHv4i16 = 2029, + ARM_VQRDMLSHv4i32 = 2030, + ARM_VQRDMLSHv8i16 = 2031, + ARM_VQRDMULHslv2i32 = 2032, + ARM_VQRDMULHslv4i16 = 2033, + ARM_VQRDMULHslv4i32 = 2034, + ARM_VQRDMULHslv8i16 = 2035, + ARM_VQRDMULHv2i32 = 2036, + ARM_VQRDMULHv4i16 = 2037, + ARM_VQRDMULHv4i32 = 2038, + ARM_VQRDMULHv8i16 = 2039, + ARM_VQRSHLsv16i8 = 2040, + ARM_VQRSHLsv1i64 = 2041, + ARM_VQRSHLsv2i32 = 2042, + ARM_VQRSHLsv2i64 = 2043, + ARM_VQRSHLsv4i16 = 2044, + ARM_VQRSHLsv4i32 = 2045, + ARM_VQRSHLsv8i16 = 2046, + ARM_VQRSHLsv8i8 = 2047, + ARM_VQRSHLuv16i8 = 2048, + ARM_VQRSHLuv1i64 = 2049, + ARM_VQRSHLuv2i32 = 2050, + ARM_VQRSHLuv2i64 = 2051, + ARM_VQRSHLuv4i16 = 2052, + ARM_VQRSHLuv4i32 = 2053, + ARM_VQRSHLuv8i16 = 2054, + ARM_VQRSHLuv8i8 = 2055, + ARM_VQRSHRNsv2i32 = 2056, + ARM_VQRSHRNsv4i16 = 2057, + ARM_VQRSHRNsv8i8 = 2058, + ARM_VQRSHRNuv2i32 = 2059, + ARM_VQRSHRNuv4i16 = 2060, + ARM_VQRSHRNuv8i8 = 2061, + ARM_VQRSHRUNv2i32 = 2062, + ARM_VQRSHRUNv4i16 = 2063, + ARM_VQRSHRUNv8i8 = 2064, + ARM_VQSHLsiv16i8 = 2065, + ARM_VQSHLsiv1i64 = 2066, + ARM_VQSHLsiv2i32 = 2067, + ARM_VQSHLsiv2i64 = 2068, + ARM_VQSHLsiv4i16 = 2069, + ARM_VQSHLsiv4i32 = 2070, + ARM_VQSHLsiv8i16 = 2071, + ARM_VQSHLsiv8i8 = 2072, + ARM_VQSHLsuv16i8 = 2073, + ARM_VQSHLsuv1i64 = 2074, + ARM_VQSHLsuv2i32 = 2075, + ARM_VQSHLsuv2i64 = 2076, + ARM_VQSHLsuv4i16 = 2077, + ARM_VQSHLsuv4i32 = 2078, + ARM_VQSHLsuv8i16 = 2079, + ARM_VQSHLsuv8i8 = 2080, + ARM_VQSHLsv16i8 = 2081, + ARM_VQSHLsv1i64 = 2082, + ARM_VQSHLsv2i32 = 2083, + ARM_VQSHLsv2i64 = 2084, + ARM_VQSHLsv4i16 = 2085, + ARM_VQSHLsv4i32 = 2086, + ARM_VQSHLsv8i16 = 2087, + ARM_VQSHLsv8i8 = 2088, + ARM_VQSHLuiv16i8 = 2089, + ARM_VQSHLuiv1i64 = 2090, + ARM_VQSHLuiv2i32 = 2091, + ARM_VQSHLuiv2i64 = 2092, + ARM_VQSHLuiv4i16 = 2093, + ARM_VQSHLuiv4i32 = 2094, + ARM_VQSHLuiv8i16 = 2095, + ARM_VQSHLuiv8i8 = 2096, + ARM_VQSHLuv16i8 = 2097, + ARM_VQSHLuv1i64 = 2098, + ARM_VQSHLuv2i32 = 2099, + ARM_VQSHLuv2i64 = 2100, + ARM_VQSHLuv4i16 = 2101, + ARM_VQSHLuv4i32 = 2102, + ARM_VQSHLuv8i16 = 2103, + ARM_VQSHLuv8i8 = 2104, + ARM_VQSHRNsv2i32 = 2105, + ARM_VQSHRNsv4i16 = 2106, + ARM_VQSHRNsv8i8 = 2107, + ARM_VQSHRNuv2i32 = 2108, + ARM_VQSHRNuv4i16 = 2109, + ARM_VQSHRNuv8i8 = 2110, + ARM_VQSHRUNv2i32 = 2111, + ARM_VQSHRUNv4i16 = 2112, + ARM_VQSHRUNv8i8 = 2113, + ARM_VQSUBsv16i8 = 2114, + ARM_VQSUBsv1i64 = 2115, + ARM_VQSUBsv2i32 = 2116, + ARM_VQSUBsv2i64 = 2117, + ARM_VQSUBsv4i16 = 2118, + ARM_VQSUBsv4i32 = 2119, + ARM_VQSUBsv8i16 = 2120, + ARM_VQSUBsv8i8 = 2121, + ARM_VQSUBuv16i8 = 2122, + ARM_VQSUBuv1i64 = 2123, + ARM_VQSUBuv2i32 = 2124, + ARM_VQSUBuv2i64 = 2125, + ARM_VQSUBuv4i16 = 2126, + ARM_VQSUBuv4i32 = 2127, + ARM_VQSUBuv8i16 = 2128, + ARM_VQSUBuv8i8 = 2129, + ARM_VRADDHNv2i32 = 2130, + ARM_VRADDHNv4i16 = 2131, + ARM_VRADDHNv8i8 = 2132, + ARM_VRECPEd = 2133, + ARM_VRECPEfd = 2134, + ARM_VRECPEfq = 2135, + ARM_VRECPEhd = 2136, + ARM_VRECPEhq = 2137, + ARM_VRECPEq = 2138, + ARM_VRECPSfd = 2139, + ARM_VRECPSfq = 2140, + ARM_VRECPShd = 2141, + ARM_VRECPShq = 2142, + ARM_VREV16d8 = 2143, + ARM_VREV16q8 = 2144, + ARM_VREV32d16 = 2145, + ARM_VREV32d8 = 2146, + ARM_VREV32q16 = 2147, + ARM_VREV32q8 = 2148, + ARM_VREV64d16 = 2149, + ARM_VREV64d32 = 2150, + ARM_VREV64d8 = 2151, + ARM_VREV64q16 = 2152, + ARM_VREV64q32 = 2153, + ARM_VREV64q8 = 2154, + ARM_VRHADDsv16i8 = 2155, + ARM_VRHADDsv2i32 = 2156, + ARM_VRHADDsv4i16 = 2157, + ARM_VRHADDsv4i32 = 2158, + ARM_VRHADDsv8i16 = 2159, + ARM_VRHADDsv8i8 = 2160, + ARM_VRHADDuv16i8 = 2161, + ARM_VRHADDuv2i32 = 2162, + ARM_VRHADDuv4i16 = 2163, + ARM_VRHADDuv4i32 = 2164, + ARM_VRHADDuv8i16 = 2165, + ARM_VRHADDuv8i8 = 2166, + ARM_VRINTAD = 2167, + ARM_VRINTAH = 2168, + ARM_VRINTANDf = 2169, + ARM_VRINTANDh = 2170, + ARM_VRINTANQf = 2171, + ARM_VRINTANQh = 2172, + ARM_VRINTAS = 2173, + ARM_VRINTMD = 2174, + ARM_VRINTMH = 2175, + ARM_VRINTMNDf = 2176, + ARM_VRINTMNDh = 2177, + ARM_VRINTMNQf = 2178, + ARM_VRINTMNQh = 2179, + ARM_VRINTMS = 2180, + ARM_VRINTND = 2181, + ARM_VRINTNH = 2182, + ARM_VRINTNNDf = 2183, + ARM_VRINTNNDh = 2184, + ARM_VRINTNNQf = 2185, + ARM_VRINTNNQh = 2186, + ARM_VRINTNS = 2187, + ARM_VRINTPD = 2188, + ARM_VRINTPH = 2189, + ARM_VRINTPNDf = 2190, + ARM_VRINTPNDh = 2191, + ARM_VRINTPNQf = 2192, + ARM_VRINTPNQh = 2193, + ARM_VRINTPS = 2194, + ARM_VRINTRD = 2195, + ARM_VRINTRH = 2196, + ARM_VRINTRS = 2197, + ARM_VRINTXD = 2198, + ARM_VRINTXH = 2199, + ARM_VRINTXNDf = 2200, + ARM_VRINTXNDh = 2201, + ARM_VRINTXNQf = 2202, + ARM_VRINTXNQh = 2203, + ARM_VRINTXS = 2204, + ARM_VRINTZD = 2205, + ARM_VRINTZH = 2206, + ARM_VRINTZNDf = 2207, + ARM_VRINTZNDh = 2208, + ARM_VRINTZNQf = 2209, + ARM_VRINTZNQh = 2210, + ARM_VRINTZS = 2211, + ARM_VRSHLsv16i8 = 2212, + ARM_VRSHLsv1i64 = 2213, + ARM_VRSHLsv2i32 = 2214, + ARM_VRSHLsv2i64 = 2215, + ARM_VRSHLsv4i16 = 2216, + ARM_VRSHLsv4i32 = 2217, + ARM_VRSHLsv8i16 = 2218, + ARM_VRSHLsv8i8 = 2219, + ARM_VRSHLuv16i8 = 2220, + ARM_VRSHLuv1i64 = 2221, + ARM_VRSHLuv2i32 = 2222, + ARM_VRSHLuv2i64 = 2223, + ARM_VRSHLuv4i16 = 2224, + ARM_VRSHLuv4i32 = 2225, + ARM_VRSHLuv8i16 = 2226, + ARM_VRSHLuv8i8 = 2227, + ARM_VRSHRNv2i32 = 2228, + ARM_VRSHRNv4i16 = 2229, + ARM_VRSHRNv8i8 = 2230, + ARM_VRSHRsv16i8 = 2231, + ARM_VRSHRsv1i64 = 2232, + ARM_VRSHRsv2i32 = 2233, + ARM_VRSHRsv2i64 = 2234, + ARM_VRSHRsv4i16 = 2235, + ARM_VRSHRsv4i32 = 2236, + ARM_VRSHRsv8i16 = 2237, + ARM_VRSHRsv8i8 = 2238, + ARM_VRSHRuv16i8 = 2239, + ARM_VRSHRuv1i64 = 2240, + ARM_VRSHRuv2i32 = 2241, + ARM_VRSHRuv2i64 = 2242, + ARM_VRSHRuv4i16 = 2243, + ARM_VRSHRuv4i32 = 2244, + ARM_VRSHRuv8i16 = 2245, + ARM_VRSHRuv8i8 = 2246, + ARM_VRSQRTEd = 2247, + ARM_VRSQRTEfd = 2248, + ARM_VRSQRTEfq = 2249, + ARM_VRSQRTEhd = 2250, + ARM_VRSQRTEhq = 2251, + ARM_VRSQRTEq = 2252, + ARM_VRSQRTSfd = 2253, + ARM_VRSQRTSfq = 2254, + ARM_VRSQRTShd = 2255, + ARM_VRSQRTShq = 2256, + ARM_VRSRAsv16i8 = 2257, + ARM_VRSRAsv1i64 = 2258, + ARM_VRSRAsv2i32 = 2259, + ARM_VRSRAsv2i64 = 2260, + ARM_VRSRAsv4i16 = 2261, + ARM_VRSRAsv4i32 = 2262, + ARM_VRSRAsv8i16 = 2263, + ARM_VRSRAsv8i8 = 2264, + ARM_VRSRAuv16i8 = 2265, + ARM_VRSRAuv1i64 = 2266, + ARM_VRSRAuv2i32 = 2267, + ARM_VRSRAuv2i64 = 2268, + ARM_VRSRAuv4i16 = 2269, + ARM_VRSRAuv4i32 = 2270, + ARM_VRSRAuv8i16 = 2271, + ARM_VRSRAuv8i8 = 2272, + ARM_VRSUBHNv2i32 = 2273, + ARM_VRSUBHNv4i16 = 2274, + ARM_VRSUBHNv8i8 = 2275, + ARM_VSDOTD = 2276, + ARM_VSDOTDI = 2277, + ARM_VSDOTQ = 2278, + ARM_VSDOTQI = 2279, + ARM_VSELEQD = 2280, + ARM_VSELEQH = 2281, + ARM_VSELEQS = 2282, + ARM_VSELGED = 2283, + ARM_VSELGEH = 2284, + ARM_VSELGES = 2285, + ARM_VSELGTD = 2286, + ARM_VSELGTH = 2287, + ARM_VSELGTS = 2288, + ARM_VSELVSD = 2289, + ARM_VSELVSH = 2290, + ARM_VSELVSS = 2291, + ARM_VSETLNi16 = 2292, + ARM_VSETLNi32 = 2293, + ARM_VSETLNi8 = 2294, + ARM_VSHLLi16 = 2295, + ARM_VSHLLi32 = 2296, + ARM_VSHLLi8 = 2297, + ARM_VSHLLsv2i64 = 2298, + ARM_VSHLLsv4i32 = 2299, + ARM_VSHLLsv8i16 = 2300, + ARM_VSHLLuv2i64 = 2301, + ARM_VSHLLuv4i32 = 2302, + ARM_VSHLLuv8i16 = 2303, + ARM_VSHLiv16i8 = 2304, + ARM_VSHLiv1i64 = 2305, + ARM_VSHLiv2i32 = 2306, + ARM_VSHLiv2i64 = 2307, + ARM_VSHLiv4i16 = 2308, + ARM_VSHLiv4i32 = 2309, + ARM_VSHLiv8i16 = 2310, + ARM_VSHLiv8i8 = 2311, + ARM_VSHLsv16i8 = 2312, + ARM_VSHLsv1i64 = 2313, + ARM_VSHLsv2i32 = 2314, + ARM_VSHLsv2i64 = 2315, + ARM_VSHLsv4i16 = 2316, + ARM_VSHLsv4i32 = 2317, + ARM_VSHLsv8i16 = 2318, + ARM_VSHLsv8i8 = 2319, + ARM_VSHLuv16i8 = 2320, + ARM_VSHLuv1i64 = 2321, + ARM_VSHLuv2i32 = 2322, + ARM_VSHLuv2i64 = 2323, + ARM_VSHLuv4i16 = 2324, + ARM_VSHLuv4i32 = 2325, + ARM_VSHLuv8i16 = 2326, + ARM_VSHLuv8i8 = 2327, + ARM_VSHRNv2i32 = 2328, + ARM_VSHRNv4i16 = 2329, + ARM_VSHRNv8i8 = 2330, + ARM_VSHRsv16i8 = 2331, + ARM_VSHRsv1i64 = 2332, + ARM_VSHRsv2i32 = 2333, + ARM_VSHRsv2i64 = 2334, + ARM_VSHRsv4i16 = 2335, + ARM_VSHRsv4i32 = 2336, + ARM_VSHRsv8i16 = 2337, + ARM_VSHRsv8i8 = 2338, + ARM_VSHRuv16i8 = 2339, + ARM_VSHRuv1i64 = 2340, + ARM_VSHRuv2i32 = 2341, + ARM_VSHRuv2i64 = 2342, + ARM_VSHRuv4i16 = 2343, + ARM_VSHRuv4i32 = 2344, + ARM_VSHRuv8i16 = 2345, + ARM_VSHRuv8i8 = 2346, + ARM_VSHTOD = 2347, + ARM_VSHTOH = 2348, + ARM_VSHTOS = 2349, + ARM_VSITOD = 2350, + ARM_VSITOH = 2351, + ARM_VSITOS = 2352, + ARM_VSLIv16i8 = 2353, + ARM_VSLIv1i64 = 2354, + ARM_VSLIv2i32 = 2355, + ARM_VSLIv2i64 = 2356, + ARM_VSLIv4i16 = 2357, + ARM_VSLIv4i32 = 2358, + ARM_VSLIv8i16 = 2359, + ARM_VSLIv8i8 = 2360, + ARM_VSLTOD = 2361, + ARM_VSLTOH = 2362, + ARM_VSLTOS = 2363, + ARM_VSQRTD = 2364, + ARM_VSQRTH = 2365, + ARM_VSQRTS = 2366, + ARM_VSRAsv16i8 = 2367, + ARM_VSRAsv1i64 = 2368, + ARM_VSRAsv2i32 = 2369, + ARM_VSRAsv2i64 = 2370, + ARM_VSRAsv4i16 = 2371, + ARM_VSRAsv4i32 = 2372, + ARM_VSRAsv8i16 = 2373, + ARM_VSRAsv8i8 = 2374, + ARM_VSRAuv16i8 = 2375, + ARM_VSRAuv1i64 = 2376, + ARM_VSRAuv2i32 = 2377, + ARM_VSRAuv2i64 = 2378, + ARM_VSRAuv4i16 = 2379, + ARM_VSRAuv4i32 = 2380, + ARM_VSRAuv8i16 = 2381, + ARM_VSRAuv8i8 = 2382, + ARM_VSRIv16i8 = 2383, + ARM_VSRIv1i64 = 2384, + ARM_VSRIv2i32 = 2385, + ARM_VSRIv2i64 = 2386, + ARM_VSRIv4i16 = 2387, + ARM_VSRIv4i32 = 2388, + ARM_VSRIv8i16 = 2389, + ARM_VSRIv8i8 = 2390, + ARM_VST1LNd16 = 2391, + ARM_VST1LNd16_UPD = 2392, + ARM_VST1LNd32 = 2393, + ARM_VST1LNd32_UPD = 2394, + ARM_VST1LNd8 = 2395, + ARM_VST1LNd8_UPD = 2396, + ARM_VST1d16 = 2403, + ARM_VST1d16Q = 2404, + ARM_VST1d16Qwb_fixed = 2406, + ARM_VST1d16Qwb_register = 2407, + ARM_VST1d16T = 2408, + ARM_VST1d16Twb_fixed = 2410, + ARM_VST1d16Twb_register = 2411, + ARM_VST1d16wb_fixed = 2412, + ARM_VST1d16wb_register = 2413, + ARM_VST1d32 = 2414, + ARM_VST1d32Q = 2415, + ARM_VST1d32Qwb_fixed = 2417, + ARM_VST1d32Qwb_register = 2418, + ARM_VST1d32T = 2419, + ARM_VST1d32Twb_fixed = 2421, + ARM_VST1d32Twb_register = 2422, + ARM_VST1d32wb_fixed = 2423, + ARM_VST1d32wb_register = 2424, + ARM_VST1d64 = 2425, + ARM_VST1d64Q = 2426, + ARM_VST1d64Qwb_fixed = 2430, + ARM_VST1d64Qwb_register = 2431, + ARM_VST1d64T = 2432, + ARM_VST1d64Twb_fixed = 2436, + ARM_VST1d64Twb_register = 2437, + ARM_VST1d64wb_fixed = 2438, + ARM_VST1d64wb_register = 2439, + ARM_VST1d8 = 2440, + ARM_VST1d8Q = 2441, + ARM_VST1d8Qwb_fixed = 2443, + ARM_VST1d8Qwb_register = 2444, + ARM_VST1d8T = 2445, + ARM_VST1d8Twb_fixed = 2447, + ARM_VST1d8Twb_register = 2448, + ARM_VST1d8wb_fixed = 2449, + ARM_VST1d8wb_register = 2450, + ARM_VST1q16 = 2451, + ARM_VST1q16wb_fixed = 2456, + ARM_VST1q16wb_register = 2457, + ARM_VST1q32 = 2458, + ARM_VST1q32wb_fixed = 2463, + ARM_VST1q32wb_register = 2464, + ARM_VST1q64 = 2465, + ARM_VST1q64wb_fixed = 2470, + ARM_VST1q64wb_register = 2471, + ARM_VST1q8 = 2472, + ARM_VST1q8wb_fixed = 2477, + ARM_VST1q8wb_register = 2478, + ARM_VST2LNd16 = 2479, + ARM_VST2LNd16_UPD = 2482, + ARM_VST2LNd32 = 2483, + ARM_VST2LNd32_UPD = 2486, + ARM_VST2LNd8 = 2487, + ARM_VST2LNd8_UPD = 2490, + ARM_VST2LNq16 = 2491, + ARM_VST2LNq16_UPD = 2494, + ARM_VST2LNq32 = 2495, + ARM_VST2LNq32_UPD = 2498, + ARM_VST2b16 = 2499, + ARM_VST2b16wb_fixed = 2500, + ARM_VST2b16wb_register = 2501, + ARM_VST2b32 = 2502, + ARM_VST2b32wb_fixed = 2503, + ARM_VST2b32wb_register = 2504, + ARM_VST2b8 = 2505, + ARM_VST2b8wb_fixed = 2506, + ARM_VST2b8wb_register = 2507, + ARM_VST2d16 = 2508, + ARM_VST2d16wb_fixed = 2509, + ARM_VST2d16wb_register = 2510, + ARM_VST2d32 = 2511, + ARM_VST2d32wb_fixed = 2512, + ARM_VST2d32wb_register = 2513, + ARM_VST2d8 = 2514, + ARM_VST2d8wb_fixed = 2515, + ARM_VST2d8wb_register = 2516, + ARM_VST2q16 = 2517, + ARM_VST2q16wb_fixed = 2521, + ARM_VST2q16wb_register = 2522, + ARM_VST2q32 = 2523, + ARM_VST2q32wb_fixed = 2527, + ARM_VST2q32wb_register = 2528, + ARM_VST2q8 = 2529, + ARM_VST2q8wb_fixed = 2533, + ARM_VST2q8wb_register = 2534, + ARM_VST3LNd16 = 2535, + ARM_VST3LNd16_UPD = 2538, + ARM_VST3LNd32 = 2539, + ARM_VST3LNd32_UPD = 2542, + ARM_VST3LNd8 = 2543, + ARM_VST3LNd8_UPD = 2546, + ARM_VST3LNq16 = 2547, + ARM_VST3LNq16_UPD = 2550, + ARM_VST3LNq32 = 2551, + ARM_VST3LNq32_UPD = 2554, + ARM_VST3d16 = 2555, + ARM_VST3d16_UPD = 2558, + ARM_VST3d32 = 2559, + ARM_VST3d32_UPD = 2562, + ARM_VST3d8 = 2563, + ARM_VST3d8_UPD = 2566, + ARM_VST3q16 = 2567, + ARM_VST3q16_UPD = 2569, + ARM_VST3q32 = 2572, + ARM_VST3q32_UPD = 2574, + ARM_VST3q8 = 2577, + ARM_VST3q8_UPD = 2579, + ARM_VST4LNd16 = 2582, + ARM_VST4LNd16_UPD = 2585, + ARM_VST4LNd32 = 2586, + ARM_VST4LNd32_UPD = 2589, + ARM_VST4LNd8 = 2590, + ARM_VST4LNd8_UPD = 2593, + ARM_VST4LNq16 = 2594, + ARM_VST4LNq16_UPD = 2597, + ARM_VST4LNq32 = 2598, + ARM_VST4LNq32_UPD = 2601, + ARM_VST4d16 = 2602, + ARM_VST4d16_UPD = 2605, + ARM_VST4d32 = 2606, + ARM_VST4d32_UPD = 2609, + ARM_VST4d8 = 2610, + ARM_VST4d8_UPD = 2613, + ARM_VST4q16 = 2614, + ARM_VST4q16_UPD = 2616, + ARM_VST4q32 = 2619, + ARM_VST4q32_UPD = 2621, + ARM_VST4q8 = 2624, + ARM_VST4q8_UPD = 2626, + ARM_VSTMDDB_UPD = 2629, + ARM_VSTMDIA = 2630, + ARM_VSTMDIA_UPD = 2631, + ARM_VSTMQIA = 2632, + ARM_VSTMSDB_UPD = 2633, + ARM_VSTMSIA = 2634, + ARM_VSTMSIA_UPD = 2635, + ARM_VSTRD = 2636, + ARM_VSTRH = 2637, + ARM_VSTRS = 2638, + ARM_VSUBD = 2639, + ARM_VSUBH = 2640, + ARM_VSUBHNv2i32 = 2641, + ARM_VSUBHNv4i16 = 2642, + ARM_VSUBHNv8i8 = 2643, + ARM_VSUBLsv2i64 = 2644, + ARM_VSUBLsv4i32 = 2645, + ARM_VSUBLsv8i16 = 2646, + ARM_VSUBLuv2i64 = 2647, + ARM_VSUBLuv4i32 = 2648, + ARM_VSUBLuv8i16 = 2649, + ARM_VSUBS = 2650, + ARM_VSUBWsv2i64 = 2651, + ARM_VSUBWsv4i32 = 2652, + ARM_VSUBWsv8i16 = 2653, + ARM_VSUBWuv2i64 = 2654, + ARM_VSUBWuv4i32 = 2655, + ARM_VSUBWuv8i16 = 2656, + ARM_VSUBfd = 2657, + ARM_VSUBfq = 2658, + ARM_VSUBhd = 2659, + ARM_VSUBhq = 2660, + ARM_VSUBv16i8 = 2661, + ARM_VSUBv1i64 = 2662, + ARM_VSUBv2i32 = 2663, + ARM_VSUBv2i64 = 2664, + ARM_VSUBv4i16 = 2665, + ARM_VSUBv4i32 = 2666, + ARM_VSUBv8i16 = 2667, + ARM_VSUBv8i8 = 2668, + ARM_VSWPd = 2669, + ARM_VSWPq = 2670, + ARM_VTBL1 = 2671, + ARM_VTBL2 = 2672, + ARM_VTBL3 = 2673, + ARM_VTBL4 = 2675, + ARM_VTBX1 = 2677, + ARM_VTBX2 = 2678, + ARM_VTBX3 = 2679, + ARM_VTBX4 = 2681, + ARM_VTOSHD = 2683, + ARM_VTOSHH = 2684, + ARM_VTOSHS = 2685, + ARM_VTOSIRD = 2686, + ARM_VTOSIRH = 2687, + ARM_VTOSIRS = 2688, + ARM_VTOSIZD = 2689, + ARM_VTOSIZH = 2690, + ARM_VTOSIZS = 2691, + ARM_VTOSLD = 2692, + ARM_VTOSLH = 2693, + ARM_VTOSLS = 2694, + ARM_VTOUHD = 2695, + ARM_VTOUHH = 2696, + ARM_VTOUHS = 2697, + ARM_VTOUIRD = 2698, + ARM_VTOUIRH = 2699, + ARM_VTOUIRS = 2700, + ARM_VTOUIZD = 2701, + ARM_VTOUIZH = 2702, + ARM_VTOUIZS = 2703, + ARM_VTOULD = 2704, + ARM_VTOULH = 2705, + ARM_VTOULS = 2706, + ARM_VTRNd16 = 2707, + ARM_VTRNd32 = 2708, + ARM_VTRNd8 = 2709, + ARM_VTRNq16 = 2710, + ARM_VTRNq32 = 2711, + ARM_VTRNq8 = 2712, + ARM_VTSTv16i8 = 2713, + ARM_VTSTv2i32 = 2714, + ARM_VTSTv4i16 = 2715, + ARM_VTSTv4i32 = 2716, + ARM_VTSTv8i16 = 2717, + ARM_VTSTv8i8 = 2718, + ARM_VUDOTD = 2719, + ARM_VUDOTDI = 2720, + ARM_VUDOTQ = 2721, + ARM_VUDOTQI = 2722, + ARM_VUHTOD = 2723, + ARM_VUHTOH = 2724, + ARM_VUHTOS = 2725, + ARM_VUITOD = 2726, + ARM_VUITOH = 2727, + ARM_VUITOS = 2728, + ARM_VULTOD = 2729, + ARM_VULTOH = 2730, + ARM_VULTOS = 2731, + ARM_VUZPd16 = 2732, + ARM_VUZPd8 = 2733, + ARM_VUZPq16 = 2734, + ARM_VUZPq32 = 2735, + ARM_VUZPq8 = 2736, + ARM_VZIPd16 = 2737, + ARM_VZIPd8 = 2738, + ARM_VZIPq16 = 2739, + ARM_VZIPq32 = 2740, + ARM_VZIPq8 = 2741, + ARM_sysLDMDA = 2742, + ARM_sysLDMDA_UPD = 2743, + ARM_sysLDMDB = 2744, + ARM_sysLDMDB_UPD = 2745, + ARM_sysLDMIA = 2746, + ARM_sysLDMIA_UPD = 2747, + ARM_sysLDMIB = 2748, + ARM_sysLDMIB_UPD = 2749, + ARM_sysSTMDA = 2750, + ARM_sysSTMDA_UPD = 2751, + ARM_sysSTMDB = 2752, + ARM_sysSTMDB_UPD = 2753, + ARM_sysSTMIA = 2754, + ARM_sysSTMIA_UPD = 2755, + ARM_sysSTMIB = 2756, + ARM_sysSTMIB_UPD = 2757, + ARM_t2ADCri = 2758, + ARM_t2ADCrr = 2759, + ARM_t2ADCrs = 2760, + ARM_t2ADDri = 2761, + ARM_t2ADDri12 = 2762, + ARM_t2ADDrr = 2763, + ARM_t2ADDrs = 2764, + ARM_t2ADR = 2765, + ARM_t2ANDri = 2766, + ARM_t2ANDrr = 2767, + ARM_t2ANDrs = 2768, + ARM_t2ASRri = 2769, + ARM_t2ASRrr = 2770, + ARM_t2B = 2771, + ARM_t2BFC = 2772, + ARM_t2BFI = 2773, + ARM_t2BICri = 2774, + ARM_t2BICrr = 2775, + ARM_t2BICrs = 2776, + ARM_t2BXJ = 2777, + ARM_t2Bcc = 2778, + ARM_t2CDP = 2779, + ARM_t2CDP2 = 2780, + ARM_t2CLREX = 2781, + ARM_t2CLZ = 2782, + ARM_t2CMNri = 2783, + ARM_t2CMNzrr = 2784, + ARM_t2CMNzrs = 2785, + ARM_t2CMPri = 2786, + ARM_t2CMPrr = 2787, + ARM_t2CMPrs = 2788, + ARM_t2CPS1p = 2789, + ARM_t2CPS2p = 2790, + ARM_t2CPS3p = 2791, + ARM_t2CRC32B = 2792, + ARM_t2CRC32CB = 2793, + ARM_t2CRC32CH = 2794, + ARM_t2CRC32CW = 2795, + ARM_t2CRC32H = 2796, + ARM_t2CRC32W = 2797, + ARM_t2DBG = 2798, + ARM_t2DCPS1 = 2799, + ARM_t2DCPS2 = 2800, + ARM_t2DCPS3 = 2801, + ARM_t2DMB = 2802, + ARM_t2DSB = 2803, + ARM_t2EORri = 2804, + ARM_t2EORrr = 2805, + ARM_t2EORrs = 2806, + ARM_t2HINT = 2807, + ARM_t2HVC = 2808, + ARM_t2ISB = 2809, + ARM_t2IT = 2810, + ARM_t2LDA = 2813, + ARM_t2LDAB = 2814, + ARM_t2LDAEX = 2815, + ARM_t2LDAEXB = 2816, + ARM_t2LDAEXD = 2817, + ARM_t2LDAEXH = 2818, + ARM_t2LDAH = 2819, + ARM_t2LDC2L_OFFSET = 2820, + ARM_t2LDC2L_OPTION = 2821, + ARM_t2LDC2L_POST = 2822, + ARM_t2LDC2L_PRE = 2823, + ARM_t2LDC2_OFFSET = 2824, + ARM_t2LDC2_OPTION = 2825, + ARM_t2LDC2_POST = 2826, + ARM_t2LDC2_PRE = 2827, + ARM_t2LDCL_OFFSET = 2828, + ARM_t2LDCL_OPTION = 2829, + ARM_t2LDCL_POST = 2830, + ARM_t2LDCL_PRE = 2831, + ARM_t2LDC_OFFSET = 2832, + ARM_t2LDC_OPTION = 2833, + ARM_t2LDC_POST = 2834, + ARM_t2LDC_PRE = 2835, + ARM_t2LDMDB = 2836, + ARM_t2LDMDB_UPD = 2837, + ARM_t2LDMIA = 2838, + ARM_t2LDMIA_UPD = 2839, + ARM_t2LDRBT = 2840, + ARM_t2LDRB_POST = 2841, + ARM_t2LDRB_PRE = 2842, + ARM_t2LDRBi12 = 2843, + ARM_t2LDRBi8 = 2844, + ARM_t2LDRBpci = 2845, + ARM_t2LDRBs = 2846, + ARM_t2LDRD_POST = 2847, + ARM_t2LDRD_PRE = 2848, + ARM_t2LDRDi8 = 2849, + ARM_t2LDREX = 2850, + ARM_t2LDREXB = 2851, + ARM_t2LDREXD = 2852, + ARM_t2LDREXH = 2853, + ARM_t2LDRHT = 2854, + ARM_t2LDRH_POST = 2855, + ARM_t2LDRH_PRE = 2856, + ARM_t2LDRHi12 = 2857, + ARM_t2LDRHi8 = 2858, + ARM_t2LDRHpci = 2859, + ARM_t2LDRHs = 2860, + ARM_t2LDRSBT = 2861, + ARM_t2LDRSB_POST = 2862, + ARM_t2LDRSB_PRE = 2863, + ARM_t2LDRSBi12 = 2864, + ARM_t2LDRSBi8 = 2865, + ARM_t2LDRSBpci = 2866, + ARM_t2LDRSBs = 2867, + ARM_t2LDRSHT = 2868, + ARM_t2LDRSH_POST = 2869, + ARM_t2LDRSH_PRE = 2870, + ARM_t2LDRSHi12 = 2871, + ARM_t2LDRSHi8 = 2872, + ARM_t2LDRSHpci = 2873, + ARM_t2LDRSHs = 2874, + ARM_t2LDRT = 2875, + ARM_t2LDR_POST = 2876, + ARM_t2LDR_PRE = 2877, + ARM_t2LDRi12 = 2878, + ARM_t2LDRi8 = 2879, + ARM_t2LDRpci = 2880, + ARM_t2LDRs = 2881, + ARM_t2LSLri = 2882, + ARM_t2LSLrr = 2883, + ARM_t2LSRri = 2884, + ARM_t2LSRrr = 2885, + ARM_t2MCR = 2886, + ARM_t2MCR2 = 2887, + ARM_t2MCRR = 2888, + ARM_t2MCRR2 = 2889, + ARM_t2MLA = 2890, + ARM_t2MLS = 2891, + ARM_t2MOVTi16 = 2892, + ARM_t2MOVi = 2893, + ARM_t2MOVi16 = 2894, + ARM_t2MOVr = 2895, + ARM_t2MOVsra_flag = 2896, + ARM_t2MOVsrl_flag = 2897, + ARM_t2MRC = 2898, + ARM_t2MRC2 = 2899, + ARM_t2MRRC = 2900, + ARM_t2MRRC2 = 2901, + ARM_t2MRS_AR = 2902, + ARM_t2MRS_M = 2903, + ARM_t2MRSbanked = 2904, + ARM_t2MRSsys_AR = 2905, + ARM_t2MSR_AR = 2906, + ARM_t2MSR_M = 2907, + ARM_t2MSRbanked = 2908, + ARM_t2MUL = 2909, + ARM_t2MVNi = 2910, + ARM_t2MVNr = 2911, + ARM_t2MVNs = 2912, + ARM_t2ORNri = 2913, + ARM_t2ORNrr = 2914, + ARM_t2ORNrs = 2915, + ARM_t2ORRri = 2916, + ARM_t2ORRrr = 2917, + ARM_t2ORRrs = 2918, + ARM_t2PKHBT = 2919, + ARM_t2PKHTB = 2920, + ARM_t2PLDWi12 = 2921, + ARM_t2PLDWi8 = 2922, + ARM_t2PLDWs = 2923, + ARM_t2PLDi12 = 2924, + ARM_t2PLDi8 = 2925, + ARM_t2PLDpci = 2926, + ARM_t2PLDs = 2927, + ARM_t2PLIi12 = 2928, + ARM_t2PLIi8 = 2929, + ARM_t2PLIpci = 2930, + ARM_t2PLIs = 2931, + ARM_t2QADD = 2932, + ARM_t2QADD16 = 2933, + ARM_t2QADD8 = 2934, + ARM_t2QASX = 2935, + ARM_t2QDADD = 2936, + ARM_t2QDSUB = 2937, + ARM_t2QSAX = 2938, + ARM_t2QSUB = 2939, + ARM_t2QSUB16 = 2940, + ARM_t2QSUB8 = 2941, + ARM_t2RBIT = 2942, + ARM_t2REV = 2943, + ARM_t2REV16 = 2944, + ARM_t2REVSH = 2945, + ARM_t2RFEDB = 2946, + ARM_t2RFEDBW = 2947, + ARM_t2RFEIA = 2948, + ARM_t2RFEIAW = 2949, + ARM_t2RORri = 2950, + ARM_t2RORrr = 2951, + ARM_t2RRX = 2952, + ARM_t2RSBri = 2953, + ARM_t2RSBrr = 2954, + ARM_t2RSBrs = 2955, + ARM_t2SADD16 = 2956, + ARM_t2SADD8 = 2957, + ARM_t2SASX = 2958, + ARM_t2SBCri = 2959, + ARM_t2SBCrr = 2960, + ARM_t2SBCrs = 2961, + ARM_t2SBFX = 2962, + ARM_t2SDIV = 2963, + ARM_t2SEL = 2964, + ARM_t2SETPAN = 2965, + ARM_t2SG = 2966, + ARM_t2SHADD16 = 2967, + ARM_t2SHADD8 = 2968, + ARM_t2SHASX = 2969, + ARM_t2SHSAX = 2970, + ARM_t2SHSUB16 = 2971, + ARM_t2SHSUB8 = 2972, + ARM_t2SMC = 2973, + ARM_t2SMLABB = 2974, + ARM_t2SMLABT = 2975, + ARM_t2SMLAD = 2976, + ARM_t2SMLADX = 2977, + ARM_t2SMLAL = 2978, + ARM_t2SMLALBB = 2979, + ARM_t2SMLALBT = 2980, + ARM_t2SMLALD = 2981, + ARM_t2SMLALDX = 2982, + ARM_t2SMLALTB = 2983, + ARM_t2SMLALTT = 2984, + ARM_t2SMLATB = 2985, + ARM_t2SMLATT = 2986, + ARM_t2SMLAWB = 2987, + ARM_t2SMLAWT = 2988, + ARM_t2SMLSD = 2989, + ARM_t2SMLSDX = 2990, + ARM_t2SMLSLD = 2991, + ARM_t2SMLSLDX = 2992, + ARM_t2SMMLA = 2993, + ARM_t2SMMLAR = 2994, + ARM_t2SMMLS = 2995, + ARM_t2SMMLSR = 2996, + ARM_t2SMMUL = 2997, + ARM_t2SMMULR = 2998, + ARM_t2SMUAD = 2999, + ARM_t2SMUADX = 3000, + ARM_t2SMULBB = 3001, + ARM_t2SMULBT = 3002, + ARM_t2SMULL = 3003, + ARM_t2SMULTB = 3004, + ARM_t2SMULTT = 3005, + ARM_t2SMULWB = 3006, + ARM_t2SMULWT = 3007, + ARM_t2SMUSD = 3008, + ARM_t2SMUSDX = 3009, + ARM_t2SRSDB = 3010, + ARM_t2SRSDB_UPD = 3011, + ARM_t2SRSIA = 3012, + ARM_t2SRSIA_UPD = 3013, + ARM_t2SSAT = 3014, + ARM_t2SSAT16 = 3015, + ARM_t2SSAX = 3016, + ARM_t2SSUB16 = 3017, + ARM_t2SSUB8 = 3018, + ARM_t2STC2L_OFFSET = 3019, + ARM_t2STC2L_OPTION = 3020, + ARM_t2STC2L_POST = 3021, + ARM_t2STC2L_PRE = 3022, + ARM_t2STC2_OFFSET = 3023, + ARM_t2STC2_OPTION = 3024, + ARM_t2STC2_POST = 3025, + ARM_t2STC2_PRE = 3026, + ARM_t2STCL_OFFSET = 3027, + ARM_t2STCL_OPTION = 3028, + ARM_t2STCL_POST = 3029, + ARM_t2STCL_PRE = 3030, + ARM_t2STC_OFFSET = 3031, + ARM_t2STC_OPTION = 3032, + ARM_t2STC_POST = 3033, + ARM_t2STC_PRE = 3034, + ARM_t2STL = 3035, + ARM_t2STLB = 3036, + ARM_t2STLEX = 3037, + ARM_t2STLEXB = 3038, + ARM_t2STLEXD = 3039, + ARM_t2STLEXH = 3040, + ARM_t2STLH = 3041, + ARM_t2STMDB = 3042, + ARM_t2STMDB_UPD = 3043, + ARM_t2STMIA = 3044, + ARM_t2STMIA_UPD = 3045, + ARM_t2STRBT = 3046, + ARM_t2STRB_POST = 3047, + ARM_t2STRB_PRE = 3048, + ARM_t2STRBi12 = 3049, + ARM_t2STRBi8 = 3050, + ARM_t2STRBs = 3051, + ARM_t2STRD_POST = 3052, + ARM_t2STRD_PRE = 3053, + ARM_t2STRDi8 = 3054, + ARM_t2STREX = 3055, + ARM_t2STREXB = 3056, + ARM_t2STREXD = 3057, + ARM_t2STREXH = 3058, + ARM_t2STRHT = 3059, + ARM_t2STRH_POST = 3060, + ARM_t2STRH_PRE = 3061, + ARM_t2STRHi12 = 3062, + ARM_t2STRHi8 = 3063, + ARM_t2STRHs = 3064, + ARM_t2STRT = 3065, + ARM_t2STR_POST = 3066, + ARM_t2STR_PRE = 3067, + ARM_t2STRi12 = 3068, + ARM_t2STRi8 = 3069, + ARM_t2STRs = 3070, + ARM_t2SUBS_PC_LR = 3071, + ARM_t2SUBri = 3072, + ARM_t2SUBri12 = 3073, + ARM_t2SUBrr = 3074, + ARM_t2SUBrs = 3075, + ARM_t2SXTAB = 3076, + ARM_t2SXTAB16 = 3077, + ARM_t2SXTAH = 3078, + ARM_t2SXTB = 3079, + ARM_t2SXTB16 = 3080, + ARM_t2SXTH = 3081, + ARM_t2TBB = 3082, + ARM_t2TBH = 3083, + ARM_t2TEQri = 3084, + ARM_t2TEQrr = 3085, + ARM_t2TEQrs = 3086, + ARM_t2TSB = 3087, + ARM_t2TSTri = 3088, + ARM_t2TSTrr = 3089, + ARM_t2TSTrs = 3090, + ARM_t2TT = 3091, + ARM_t2TTA = 3092, + ARM_t2TTAT = 3093, + ARM_t2TTT = 3094, + ARM_t2UADD16 = 3095, + ARM_t2UADD8 = 3096, + ARM_t2UASX = 3097, + ARM_t2UBFX = 3098, + ARM_t2UDF = 3099, + ARM_t2UDIV = 3100, + ARM_t2UHADD16 = 3101, + ARM_t2UHADD8 = 3102, + ARM_t2UHASX = 3103, + ARM_t2UHSAX = 3104, + ARM_t2UHSUB16 = 3105, + ARM_t2UHSUB8 = 3106, + ARM_t2UMAAL = 3107, + ARM_t2UMLAL = 3108, + ARM_t2UMULL = 3109, + ARM_t2UQADD16 = 3110, + ARM_t2UQADD8 = 3111, + ARM_t2UQASX = 3112, + ARM_t2UQSAX = 3113, + ARM_t2UQSUB16 = 3114, + ARM_t2UQSUB8 = 3115, + ARM_t2USAD8 = 3116, + ARM_t2USADA8 = 3117, + ARM_t2USAT = 3118, + ARM_t2USAT16 = 3119, + ARM_t2USAX = 3120, + ARM_t2USUB16 = 3121, + ARM_t2USUB8 = 3122, + ARM_t2UXTAB = 3123, + ARM_t2UXTAB16 = 3124, + ARM_t2UXTAH = 3125, + ARM_t2UXTB = 3126, + ARM_t2UXTB16 = 3127, + ARM_t2UXTH = 3128, + ARM_tADC = 3129, + ARM_tADDhirr = 3130, + ARM_tADDi3 = 3131, + ARM_tADDi8 = 3132, + ARM_tADDrSP = 3133, + ARM_tADDrSPi = 3134, + ARM_tADDrr = 3135, + ARM_tADDspi = 3136, + ARM_tADDspr = 3137, + ARM_tADR = 3138, + ARM_tAND = 3139, + ARM_tASRri = 3140, + ARM_tASRrr = 3141, + ARM_tB = 3142, + ARM_tBIC = 3143, + ARM_tBKPT = 3144, + ARM_tBL = 3145, + ARM_tBLXNSr = 3146, + ARM_tBLXi = 3147, + ARM_tBLXr = 3148, + ARM_tBX = 3149, + ARM_tBXNS = 3150, + ARM_tBcc = 3151, + ARM_tCBNZ = 3152, + ARM_tCBZ = 3153, + ARM_tCMNz = 3154, + ARM_tCMPhir = 3155, + ARM_tCMPi8 = 3156, + ARM_tCMPr = 3157, + ARM_tCPS = 3158, + ARM_tEOR = 3159, + ARM_tHINT = 3160, + ARM_tHLT = 3161, + ARM_tLDMIA = 3165, + ARM_tLDRBi = 3166, + ARM_tLDRBr = 3167, + ARM_tLDRHi = 3168, + ARM_tLDRHr = 3169, + ARM_tLDRSB = 3170, + ARM_tLDRSH = 3171, + ARM_tLDRi = 3172, + ARM_tLDRpci = 3173, + ARM_tLDRr = 3174, + ARM_tLDRspi = 3175, + ARM_tLSLri = 3176, + ARM_tLSLrr = 3177, + ARM_tLSRri = 3178, + ARM_tLSRrr = 3179, + ARM_tMOVSr = 3180, + ARM_tMOVi8 = 3181, + ARM_tMOVr = 3182, + ARM_tMUL = 3183, + ARM_tMVN = 3184, + ARM_tORR = 3185, + ARM_tPICADD = 3186, + ARM_tPOP = 3187, + ARM_tPUSH = 3188, + ARM_tREV = 3189, + ARM_tREV16 = 3190, + ARM_tREVSH = 3191, + ARM_tROR = 3192, + ARM_tRSB = 3193, + ARM_tSBC = 3194, + ARM_tSETEND = 3195, + ARM_tSTMIA_UPD = 3196, + ARM_tSTRBi = 3197, + ARM_tSTRBr = 3198, + ARM_tSTRHi = 3199, + ARM_tSTRHr = 3200, + ARM_tSTRi = 3201, + ARM_tSTRr = 3202, + ARM_tSTRspi = 3203, + ARM_tSUBi3 = 3204, + ARM_tSUBi8 = 3205, + ARM_tSUBrr = 3206, + ARM_tSUBspi = 3207, + ARM_tSVC = 3208, + ARM_tSXTB = 3209, + ARM_tSXTH = 3210, + ARM_tTRAP = 3211, + ARM_tTST = 3212, + ARM_tUDF = 3213, + ARM_tUXTB = 3214, + ARM_tUXTH = 3215, + ARM_t__brkdiv0 = 3216, + ARM_INSTRUCTION_LIST_END = 3217 +}; + +#endif // GET_INSTRINFO_ENUM + +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +#define nullptr 0 + +static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, }; +static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, }; +static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, }; +static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, }; +static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, }; +static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, }; +static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, }; +static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, }; +static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, }; +static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, }; +static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, }; +static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, }; +static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, }; +static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, }; +static const MCOperandInfo OperandInfo31[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo32[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo34[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo35[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo38[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; +static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; +static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; +static const MCOperandInfo OperandInfo42[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo44[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo45[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo46[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo47[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo48[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo49[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo50[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo53[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo54[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo55[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo56[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo58[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo59[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo64[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo70[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo71[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo73[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo74[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo75[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo76[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo77[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo78[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo79[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo80[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo81[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo82[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo83[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo84[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo85[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo86[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo87[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo88[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo89[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo90[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo91[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo92[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo93[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo94[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo95[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo96[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo97[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo98[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo100[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo101[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo102[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo103[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo104[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo105[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo106[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo107[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo108[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo109[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo110[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo111[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo112[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo113[] = { { ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo116[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo118[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo119[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo121[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo122[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo123[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo124[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo125[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo126[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo127[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo128[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo130[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo131[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo132[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo133[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo134[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, }; +static const MCOperandInfo OperandInfo135[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo136[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo137[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo138[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo139[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo140[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo141[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo142[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo143[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo144[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo145[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo146[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo147[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo148[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo149[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo150[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo151[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo152[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo153[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo154[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo155[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo156[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo157[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo158[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo159[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo160[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo161[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo162[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo163[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo166[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo167[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo168[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo169[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, }; +static const MCOperandInfo OperandInfo170[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, }; +static const MCOperandInfo OperandInfo171[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo172[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo173[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo174[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo175[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo176[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo177[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo178[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo179[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo180[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo181[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo182[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo183[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo184[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo185[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo186[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo187[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo188[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo189[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo190[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo191[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo192[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo193[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo194[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo196[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo199[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo200[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo201[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo203[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo204[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo205[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo206[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo207[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo208[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo209[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo210[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo211[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo214[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo215[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo217[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo218[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo220[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo221[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo222[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo223[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo226[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo228[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo229[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo230[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo231[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo232[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo233[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo234[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo235[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo237[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo238[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo239[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo240[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo241[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo242[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo243[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo244[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo245[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo246[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo247[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo248[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo249[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo250[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo251[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo252[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo253[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo254[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo255[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo256[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo257[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo258[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo259[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo260[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo263[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo264[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo267[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo268[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo269[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo270[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo271[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo272[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo273[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo274[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo275[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo276[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo277[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo278[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo279[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo280[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo281[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo282[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo283[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo284[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo285[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo286[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo287[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo288[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo289[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo290[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo291[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo292[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo293[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo294[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo295[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo296[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo297[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo298[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo299[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo300[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo301[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo302[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo303[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo304[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo305[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo306[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo307[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo308[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo309[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo310[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo311[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo312[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo313[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo316[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo317[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo318[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo319[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo320[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo321[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo322[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo323[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo324[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo325[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo326[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo328[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo329[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo331[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo332[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo333[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo335[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo336[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo337[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo338[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo339[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo340[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo341[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo342[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo343[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo344[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo345[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo346[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo347[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo348[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo349[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo350[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo351[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo352[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo353[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo354[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo355[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo356[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo357[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo358[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo359[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo360[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo361[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo362[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo363[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo364[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo365[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo366[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo367[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo368[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo369[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo370[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo371[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo372[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo373[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo374[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo375[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo376[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo377[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo378[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo379[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo380[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo381[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo382[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo383[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo384[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo385[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo386[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo387[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo388[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo389[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo390[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo391[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo392[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo393[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo394[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo395[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo396[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo397[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo398[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo399[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo400[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo401[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo402[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo403[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo404[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo405[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo406[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; +static const MCOperandInfo OperandInfo407[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo408[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo409[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; +static const MCOperandInfo OperandInfo410[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo411[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo412[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo413[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo414[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo415[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo416[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo417[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo418[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo419[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; + +static const MCInstrDesc ARMInsts[] = { + { 1, OperandInfo2 }, + { 0, nullptr }, + { 1, OperandInfo3 }, + { 1, OperandInfo3 }, + { 1, OperandInfo3 }, + { 1, OperandInfo3 }, + { 0, nullptr }, + { 3, OperandInfo4 }, + { 4, OperandInfo5 }, + { 1, OperandInfo2 }, + { 4, OperandInfo6 }, + { 3, OperandInfo4 }, + { 0, nullptr }, + { 1, OperandInfo2 }, + { 2, OperandInfo7 }, + { 2, OperandInfo7 }, + { 0, nullptr }, + { 1, OperandInfo3 }, + { 1, OperandInfo3 }, + { 2, OperandInfo8 }, + { 1, OperandInfo2 }, + { 6, OperandInfo9 }, + { 1, OperandInfo10 }, + { 0, nullptr }, + { 2, OperandInfo11 }, + { 1, OperandInfo2 }, + { 1, OperandInfo2 }, + { 0, nullptr }, + { 0, nullptr }, + { 0, nullptr }, + { 0, nullptr }, + { 2, OperandInfo11 }, + { 3, OperandInfo12 }, + { 1, OperandInfo2 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 1, OperandInfo14 }, + { 1, OperandInfo14 }, + { 2, OperandInfo15 }, + { 2, OperandInfo15 }, + { 3, OperandInfo16 }, + { 2, OperandInfo17 }, + { 4, OperandInfo18 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 5, OperandInfo19 }, + { 4, OperandInfo20 }, + { 3, OperandInfo21 }, + { 3, OperandInfo21 }, + { 3, OperandInfo21 }, + { 3, OperandInfo21 }, + { 3, OperandInfo21 }, + { 3, OperandInfo21 }, + { 3, OperandInfo21 }, + { 3, OperandInfo21 }, + { 3, OperandInfo21 }, + { 3, OperandInfo21 }, + { 3, OperandInfo21 }, + { 2, OperandInfo15 }, + { 1, OperandInfo14 }, + { 1, OperandInfo2 }, + { 1, OperandInfo2 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo15 }, + { 2, OperandInfo15 }, + { 1, OperandInfo14 }, + { 3, OperandInfo16 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 4, OperandInfo22 }, + { 4, OperandInfo22 }, + { 4, OperandInfo20 }, + { 5, OperandInfo23 }, + { 5, OperandInfo23 }, + { 4, OperandInfo20 }, + { 4, OperandInfo20 }, + { 4, OperandInfo20 }, + { 4, OperandInfo20 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 4, OperandInfo24 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 3, OperandInfo13 }, + { 2, OperandInfo25 }, + { 2, OperandInfo25 }, + { 2, OperandInfo25 }, + { 2, OperandInfo25 }, + { 2, OperandInfo25 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo17 }, + { 2, OperandInfo25 }, + { 3, OperandInfo26 }, + { 3, OperandInfo27 }, + { 1, OperandInfo2 }, + { 4, OperandInfo28 }, + { 3, OperandInfo29 }, + { 4, OperandInfo30 }, + { 2, OperandInfo25 }, + { 2, OperandInfo17 }, + { 2, OperandInfo15 }, + { 2, OperandInfo31 }, + { 5, OperandInfo32 }, + { 5, OperandInfo33 }, + { 6, OperandInfo34 }, + { 7, OperandInfo35 }, + { 4, OperandInfo36 }, + { 4, OperandInfo36 }, + { 6, OperandInfo37 }, + { 6, OperandInfo38 }, + { 1, OperandInfo39 }, + { 4, OperandInfo40 }, + { 6, OperandInfo41 }, + { 1, OperandInfo39 }, + { 1, OperandInfo42 }, + { 3, OperandInfo43 }, + { 3, OperandInfo44 }, + { 4, OperandInfo45 }, + { 2, OperandInfo46 }, + { 1, OperandInfo42 }, + { 5, OperandInfo47 }, + { 5, OperandInfo47 }, + { 5, OperandInfo48 }, + { 5, OperandInfo47 }, + { 3, OperandInfo4 }, + { 4, OperandInfo49 }, + { 1, OperandInfo3 }, + { 2, OperandInfo7 }, + { 0, nullptr }, + { 2, OperandInfo31 }, + { 2, OperandInfo31 }, + { 2, OperandInfo31 }, + { 0, nullptr }, + { 3, OperandInfo4 }, + { 3, OperandInfo4 }, + { 3, OperandInfo4 }, + { 3, OperandInfo4 }, + { 5, OperandInfo50 }, + { 4, OperandInfo51 }, + { 4, OperandInfo52 }, + { 2, OperandInfo46 }, + { 2, OperandInfo46 }, + { 2, OperandInfo46 }, + { 4, OperandInfo51 }, + { 4, OperandInfo53 }, + { 4, OperandInfo53 }, + { 6, OperandInfo37 }, + { 6, OperandInfo38 }, + { 6, OperandInfo37 }, + { 6, OperandInfo38 }, + { 5, OperandInfo54 }, + { 7, OperandInfo55 }, + { 5, OperandInfo56 }, + { 5, OperandInfo56 }, + { 5, OperandInfo57 }, + { 5, OperandInfo58 }, + { 6, OperandInfo59 }, + { 7, OperandInfo60 }, + { 1, OperandInfo61 }, + { 4, OperandInfo62 }, + { 2, OperandInfo46 }, + { 2, OperandInfo46 }, + { 3, OperandInfo63 }, + { 2, OperandInfo46 }, + { 2, OperandInfo31 }, + { 2, OperandInfo31 }, + { 6, OperandInfo64 }, + { 5, OperandInfo56 }, + { 5, OperandInfo32 }, + { 5, OperandInfo65 }, + { 5, OperandInfo65 }, + { 5, OperandInfo65 }, + { 5, OperandInfo65 }, + { 5, OperandInfo65 }, + { 5, OperandInfo65 }, + { 5, OperandInfo65 }, + { 5, OperandInfo65 }, + { 6, OperandInfo37 }, + { 6, OperandInfo38 }, + { 2, OperandInfo31 }, + { 5, OperandInfo66 }, + { 5, OperandInfo32 }, + { 6, OperandInfo34 }, + { 7, OperandInfo35 }, + { 9, OperandInfo67 }, + { 7, OperandInfo68 }, + { 3, OperandInfo69 }, + { 4, OperandInfo51 }, + { 7, OperandInfo70 }, + { 7, OperandInfo70 }, + { 7, OperandInfo71 }, + { 4, OperandInfo51 }, + { 7, OperandInfo70 }, + { 7, OperandInfo70 }, + { 3, OperandInfo72 }, + { 5, OperandInfo32 }, + { 5, OperandInfo33 }, + { 6, OperandInfo34 }, + { 7, OperandInfo35 }, + { 1, OperandInfo39 }, + { 1, OperandInfo73 }, + { 1, OperandInfo61 }, + { 1, OperandInfo3 }, + { 1, OperandInfo73 }, + { 0, nullptr }, + { 9, OperandInfo67 }, + { 7, OperandInfo68 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 7, OperandInfo75 }, + { 7, OperandInfo75 }, + { 7, OperandInfo75 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 7, OperandInfo75 }, + { 7, OperandInfo75 }, + { 7, OperandInfo75 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 7, OperandInfo75 }, + { 7, OperandInfo75 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 6, OperandInfo77 }, + { 6, OperandInfo77 }, + { 6, OperandInfo77 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 6, OperandInfo77 }, + { 6, OperandInfo77 }, + { 6, OperandInfo77 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 7, OperandInfo75 }, + { 7, OperandInfo75 }, + { 7, OperandInfo75 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 6, OperandInfo74 }, + { 7, OperandInfo75 }, + { 7, OperandInfo75 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 6, OperandInfo77 }, + { 6, OperandInfo77 }, + { 6, OperandInfo77 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 6, OperandInfo77 }, + { 6, OperandInfo77 }, + { 6, OperandInfo77 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, OperandInfo76 }, + { 5, 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5, OperandInfo354 }, + { 6, OperandInfo355 }, + { 7, OperandInfo356 }, + { 4, OperandInfo357 }, + { 6, OperandInfo350 }, + { 6, OperandInfo351 }, + { 7, OperandInfo352 }, + { 6, OperandInfo350 }, + { 6, OperandInfo351 }, + { 3, OperandInfo107 }, + { 5, OperandInfo90 }, + { 6, OperandInfo358 }, + { 6, OperandInfo350 }, + { 6, OperandInfo351 }, + { 7, OperandInfo352 }, + { 3, OperandInfo163 }, + { 3, OperandInfo107 }, + { 8, OperandInfo121 }, + { 8, OperandInfo121 }, + { 2, OperandInfo105 }, + { 4, OperandInfo359 }, + { 4, OperandInfo86 }, + { 4, OperandInfo360 }, + { 5, OperandInfo361 }, + { 4, OperandInfo86 }, + { 4, OperandInfo360 }, + { 5, OperandInfo361 }, + { 1, OperandInfo2 }, + { 2, OperandInfo7 }, + { 3, OperandInfo4 }, + { 3, OperandInfo362 }, + { 3, OperandInfo362 }, + { 3, OperandInfo362 }, + { 3, OperandInfo362 }, + { 3, OperandInfo362 }, + { 3, OperandInfo362 }, + { 3, OperandInfo128 }, + { 2, OperandInfo105 }, + { 2, OperandInfo105 }, + { 2, OperandInfo105 }, + { 3, OperandInfo128 }, + { 3, OperandInfo128 }, + { 6, OperandInfo350 }, + { 6, OperandInfo351 }, + { 7, OperandInfo352 }, + { 3, OperandInfo128 }, + { 1, OperandInfo2 }, + { 3, OperandInfo128 }, + { 2, OperandInfo7 }, + { 2, OperandInfo363 }, + { 2, OperandInfo363 }, + { 4, OperandInfo364 }, + { 4, OperandInfo364 }, + { 4, OperandInfo364 }, + { 4, OperandInfo364 }, + { 5, OperandInfo365 }, + { 4, OperandInfo364 }, + { 4, OperandInfo364 }, + { 6, OperandInfo136 }, + { 6, OperandInfo137 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo137 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo137 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo137 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 4, OperandInfo132 }, + { 5, OperandInfo50 }, + { 4, OperandInfo132 }, + { 5, OperandInfo50 }, + { 5, OperandInfo366 }, + { 6, OperandInfo139 }, + { 6, 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OperandInfo350 }, + { 6, OperandInfo351 }, + { 6, OperandInfo350 }, + { 6, OperandInfo351 }, + { 8, OperandInfo148 }, + { 8, OperandInfo148 }, + { 7, OperandInfo372 }, + { 7, OperandInfo372 }, + { 6, OperandInfo373 }, + { 6, OperandInfo373 }, + { 5, OperandInfo90 }, + { 5, OperandInfo374 }, + { 4, OperandInfo357 }, + { 5, OperandInfo375 }, + { 4, OperandInfo359 }, + { 4, OperandInfo359 }, + { 8, OperandInfo159 }, + { 8, OperandInfo159 }, + { 7, OperandInfo376 }, + { 7, OperandInfo376 }, + { 3, OperandInfo103 }, + { 4, OperandInfo357 }, + { 4, OperandInfo357 }, + { 3, OperandInfo103 }, + { 4, OperandInfo377 }, + { 4, OperandInfo377 }, + { 4, OperandInfo377 }, + { 5, OperandInfo378 }, + { 5, OperandInfo374 }, + { 5, OperandInfo379 }, + { 6, OperandInfo380 }, + { 6, OperandInfo350 }, + { 6, OperandInfo351 }, + { 7, OperandInfo352 }, + { 6, OperandInfo350 }, + { 6, OperandInfo351 }, + { 7, OperandInfo352 }, + { 6, OperandInfo381 }, + { 6, OperandInfo381 }, + { 4, OperandInfo382 }, + { 4, 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OperandInfo378 }, + { 6, OperandInfo373 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 3, OperandInfo128 }, + { 3, OperandInfo128 }, + { 3, OperandInfo128 }, + { 3, OperandInfo128 }, + { 6, OperandInfo386 }, + { 5, OperandInfo387 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 6, OperandInfo136 }, + { 6, OperandInfo137 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo137 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo137 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 6, OperandInfo137 }, + { 6, OperandInfo136 }, + { 6, OperandInfo136 }, + { 4, OperandInfo364 }, + { 4, OperandInfo364 }, + { 5, OperandInfo388 }, + { 5, OperandInfo388 }, + { 6, OperandInfo389 }, + { 5, OperandInfo388 }, + { 4, OperandInfo364 }, + { 4, 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OperandInfo395 }, + { 4, OperandInfo395 }, + { 4, OperandInfo86 }, + { 4, OperandInfo360 }, + { 5, OperandInfo361 }, + { 3, OperandInfo128 }, + { 4, OperandInfo86 }, + { 4, OperandInfo360 }, + { 5, OperandInfo361 }, + { 4, OperandInfo396 }, + { 4, OperandInfo396 }, + { 4, OperandInfo396 }, + { 4, OperandInfo396 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 6, OperandInfo384 }, + { 1, OperandInfo2 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 8, OperandInfo385 }, + { 8, OperandInfo385 }, + { 6, OperandInfo373 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 6, OperandInfo373 }, + { 6, OperandInfo386 }, + { 5, OperandInfo387 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 5, OperandInfo378 }, + { 6, OperandInfo381 }, + { 6, OperandInfo381 }, + { 6, OperandInfo381 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 6, OperandInfo397 }, + { 5, OperandInfo58 }, + { 6, OperandInfo398 }, + { 6, OperandInfo399 }, + { 5, OperandInfo400 }, + { 5, OperandInfo401 }, + { 6, OperandInfo402 }, + { 5, OperandInfo403 }, + { 5, OperandInfo404 }, + { 4, OperandInfo405 }, + { 6, OperandInfo397 }, + { 6, OperandInfo398 }, + { 6, OperandInfo397 }, + { 3, OperandInfo107 }, + { 6, OperandInfo397 }, + { 1, OperandInfo2 }, + { 3, OperandInfo406 }, + { 3, OperandInfo407 }, + { 3, OperandInfo406 }, + { 3, OperandInfo408 }, + { 3, OperandInfo103 }, + { 3, OperandInfo103 }, + { 3, OperandInfo107 }, + { 2, OperandInfo409 }, + { 2, OperandInfo409 }, + { 4, OperandInfo410 }, + { 4, OperandInfo123 }, + { 4, OperandInfo108 }, + { 4, OperandInfo410 }, + { 2, OperandInfo7 }, + { 6, OperandInfo397 }, + { 3, OperandInfo128 }, + { 1, OperandInfo2 }, + { 2, OperandInfo31 }, + { 2, OperandInfo31 }, + { 2, OperandInfo363 }, + { 4, OperandInfo411 }, + { 5, OperandInfo412 }, + { 5, OperandInfo413 }, + { 5, OperandInfo412 }, + { 5, OperandInfo413 }, + { 5, OperandInfo413 }, + { 5, OperandInfo413 }, + { 5, OperandInfo412 }, + { 4, OperandInfo405 }, + { 5, OperandInfo413 }, + { 5, OperandInfo414 }, + { 6, OperandInfo398 }, + { 6, OperandInfo397 }, + { 6, OperandInfo398 }, + { 6, OperandInfo397 }, + { 2, OperandInfo363 }, + { 5, OperandInfo415 }, + { 4, OperandInfo123 }, + { 6, OperandInfo416 }, + { 5, OperandInfo417 }, + { 6, OperandInfo397 }, + { 3, OperandInfo418 }, + { 3, OperandInfo112 }, + { 3, OperandInfo112 }, + { 4, OperandInfo410 }, + { 4, OperandInfo410 }, + { 4, OperandInfo410 }, + { 6, OperandInfo397 }, + { 5, OperandInfo417 }, + { 6, OperandInfo397 }, + { 1, OperandInfo2 }, + { 5, OperandInfo419 }, + { 5, OperandInfo412 }, + { 5, OperandInfo413 }, + { 5, OperandInfo412 }, + { 5, OperandInfo413 }, + { 5, OperandInfo412 }, + { 5, OperandInfo413 }, + { 5, OperandInfo414 }, + { 6, OperandInfo398 }, + { 6, OperandInfo399 }, + { 6, OperandInfo402 }, + { 5, OperandInfo403 }, + { 3, OperandInfo128 }, + { 4, OperandInfo410 }, + { 4, OperandInfo410 }, + { 0, nullptr }, + { 4, OperandInfo410 }, + { 1, OperandInfo2 }, + { 4, OperandInfo410 }, + { 4, OperandInfo410 }, + { 0, nullptr }, +}; + +#endif // GET_INSTRINFO_MC_DESC diff --git a/capstone/arch/ARM/ARMGenRegisterInfo.inc b/capstone/arch/ARM/ARMGenRegisterInfo.inc new file mode 100644 index 000000000..5463e06d3 --- /dev/null +++ b/capstone/arch/ARM/ARMGenRegisterInfo.inc @@ -0,0 +1,2102 @@ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + +#ifdef GET_REGINFO_ENUM +#undef GET_REGINFO_ENUM + +enum { + ARM_NoRegister, + ARM_APSR = 1, + ARM_APSR_NZCV = 2, + ARM_CPSR = 3, + ARM_FPEXC = 4, + ARM_FPINST = 5, + ARM_FPSCR = 6, + ARM_FPSCR_NZCV = 7, + ARM_FPSID = 8, + ARM_ITSTATE = 9, + ARM_LR = 10, + ARM_PC = 11, + ARM_SP = 12, + ARM_SPSR = 13, + ARM_D0 = 14, + ARM_D1 = 15, + ARM_D2 = 16, + ARM_D3 = 17, + ARM_D4 = 18, + ARM_D5 = 19, + ARM_D6 = 20, + ARM_D7 = 21, + ARM_D8 = 22, + ARM_D9 = 23, + ARM_D10 = 24, + ARM_D11 = 25, + ARM_D12 = 26, + ARM_D13 = 27, + ARM_D14 = 28, + ARM_D15 = 29, + ARM_D16 = 30, + ARM_D17 = 31, + ARM_D18 = 32, + ARM_D19 = 33, + ARM_D20 = 34, + ARM_D21 = 35, + ARM_D22 = 36, + ARM_D23 = 37, + ARM_D24 = 38, + ARM_D25 = 39, + ARM_D26 = 40, + ARM_D27 = 41, + ARM_D28 = 42, + ARM_D29 = 43, + ARM_D30 = 44, + ARM_D31 = 45, + ARM_FPINST2 = 46, + ARM_MVFR0 = 47, + ARM_MVFR1 = 48, + ARM_MVFR2 = 49, + ARM_Q0 = 50, + ARM_Q1 = 51, + ARM_Q2 = 52, + ARM_Q3 = 53, + ARM_Q4 = 54, + ARM_Q5 = 55, + ARM_Q6 = 56, + ARM_Q7 = 57, + ARM_Q8 = 58, + ARM_Q9 = 59, + ARM_Q10 = 60, + ARM_Q11 = 61, + ARM_Q12 = 62, + ARM_Q13 = 63, + ARM_Q14 = 64, + ARM_Q15 = 65, + ARM_R0 = 66, + ARM_R1 = 67, + ARM_R2 = 68, + ARM_R3 = 69, + ARM_R4 = 70, + ARM_R5 = 71, + ARM_R6 = 72, + ARM_R7 = 73, + ARM_R8 = 74, + ARM_R9 = 75, + ARM_R10 = 76, + ARM_R11 = 77, + ARM_R12 = 78, + ARM_S0 = 79, + ARM_S1 = 80, + ARM_S2 = 81, + ARM_S3 = 82, + ARM_S4 = 83, + ARM_S5 = 84, + ARM_S6 = 85, + ARM_S7 = 86, + ARM_S8 = 87, + ARM_S9 = 88, + ARM_S10 = 89, + ARM_S11 = 90, + ARM_S12 = 91, + ARM_S13 = 92, + ARM_S14 = 93, + ARM_S15 = 94, + ARM_S16 = 95, + ARM_S17 = 96, + ARM_S18 = 97, + ARM_S19 = 98, + ARM_S20 = 99, + ARM_S21 = 100, + ARM_S22 = 101, + ARM_S23 = 102, + ARM_S24 = 103, + ARM_S25 = 104, + ARM_S26 = 105, + ARM_S27 = 106, + ARM_S28 = 107, + ARM_S29 = 108, + ARM_S30 = 109, + ARM_S31 = 110, + ARM_D0_D2 = 111, + ARM_D1_D3 = 112, + ARM_D2_D4 = 113, + ARM_D3_D5 = 114, + ARM_D4_D6 = 115, + ARM_D5_D7 = 116, + ARM_D6_D8 = 117, + ARM_D7_D9 = 118, + ARM_D8_D10 = 119, + ARM_D9_D11 = 120, + ARM_D10_D12 = 121, + ARM_D11_D13 = 122, + ARM_D12_D14 = 123, + ARM_D13_D15 = 124, + ARM_D14_D16 = 125, + ARM_D15_D17 = 126, + ARM_D16_D18 = 127, + ARM_D17_D19 = 128, + ARM_D18_D20 = 129, + ARM_D19_D21 = 130, + ARM_D20_D22 = 131, + ARM_D21_D23 = 132, + ARM_D22_D24 = 133, + ARM_D23_D25 = 134, + ARM_D24_D26 = 135, + ARM_D25_D27 = 136, + ARM_D26_D28 = 137, + ARM_D27_D29 = 138, + ARM_D28_D30 = 139, + ARM_D29_D31 = 140, + ARM_Q0_Q1 = 141, + ARM_Q1_Q2 = 142, + ARM_Q2_Q3 = 143, + ARM_Q3_Q4 = 144, + ARM_Q4_Q5 = 145, + ARM_Q5_Q6 = 146, + ARM_Q6_Q7 = 147, + ARM_Q7_Q8 = 148, + ARM_Q8_Q9 = 149, + ARM_Q9_Q10 = 150, + ARM_Q10_Q11 = 151, + ARM_Q11_Q12 = 152, + ARM_Q12_Q13 = 153, + ARM_Q13_Q14 = 154, + ARM_Q14_Q15 = 155, + ARM_Q0_Q1_Q2_Q3 = 156, + ARM_Q1_Q2_Q3_Q4 = 157, + ARM_Q2_Q3_Q4_Q5 = 158, + ARM_Q3_Q4_Q5_Q6 = 159, + ARM_Q4_Q5_Q6_Q7 = 160, + ARM_Q5_Q6_Q7_Q8 = 161, + ARM_Q6_Q7_Q8_Q9 = 162, + ARM_Q7_Q8_Q9_Q10 = 163, + ARM_Q8_Q9_Q10_Q11 = 164, + ARM_Q9_Q10_Q11_Q12 = 165, + ARM_Q10_Q11_Q12_Q13 = 166, + ARM_Q11_Q12_Q13_Q14 = 167, + ARM_Q12_Q13_Q14_Q15 = 168, + ARM_R12_SP = 169, + ARM_R0_R1 = 170, + ARM_R2_R3 = 171, + ARM_R4_R5 = 172, + ARM_R6_R7 = 173, + ARM_R8_R9 = 174, + ARM_R10_R11 = 175, + ARM_D0_D1_D2 = 176, + ARM_D1_D2_D3 = 177, + ARM_D2_D3_D4 = 178, + ARM_D3_D4_D5 = 179, + ARM_D4_D5_D6 = 180, + ARM_D5_D6_D7 = 181, + ARM_D6_D7_D8 = 182, + ARM_D7_D8_D9 = 183, + ARM_D8_D9_D10 = 184, + ARM_D9_D10_D11 = 185, + ARM_D10_D11_D12 = 186, + ARM_D11_D12_D13 = 187, + ARM_D12_D13_D14 = 188, + ARM_D13_D14_D15 = 189, + ARM_D14_D15_D16 = 190, + ARM_D15_D16_D17 = 191, + ARM_D16_D17_D18 = 192, + ARM_D17_D18_D19 = 193, + ARM_D18_D19_D20 = 194, + ARM_D19_D20_D21 = 195, + ARM_D20_D21_D22 = 196, + ARM_D21_D22_D23 = 197, + ARM_D22_D23_D24 = 198, + ARM_D23_D24_D25 = 199, + ARM_D24_D25_D26 = 200, + ARM_D25_D26_D27 = 201, + ARM_D26_D27_D28 = 202, + ARM_D27_D28_D29 = 203, + ARM_D28_D29_D30 = 204, + ARM_D29_D30_D31 = 205, + ARM_D0_D2_D4 = 206, + ARM_D1_D3_D5 = 207, + ARM_D2_D4_D6 = 208, + ARM_D3_D5_D7 = 209, + ARM_D4_D6_D8 = 210, + ARM_D5_D7_D9 = 211, + ARM_D6_D8_D10 = 212, + ARM_D7_D9_D11 = 213, + ARM_D8_D10_D12 = 214, + ARM_D9_D11_D13 = 215, + ARM_D10_D12_D14 = 216, + ARM_D11_D13_D15 = 217, + ARM_D12_D14_D16 = 218, + ARM_D13_D15_D17 = 219, + ARM_D14_D16_D18 = 220, + ARM_D15_D17_D19 = 221, + ARM_D16_D18_D20 = 222, + ARM_D17_D19_D21 = 223, + ARM_D18_D20_D22 = 224, + ARM_D19_D21_D23 = 225, + ARM_D20_D22_D24 = 226, + ARM_D21_D23_D25 = 227, + ARM_D22_D24_D26 = 228, + ARM_D23_D25_D27 = 229, + ARM_D24_D26_D28 = 230, + ARM_D25_D27_D29 = 231, + ARM_D26_D28_D30 = 232, + ARM_D27_D29_D31 = 233, + ARM_D0_D2_D4_D6 = 234, + ARM_D1_D3_D5_D7 = 235, + ARM_D2_D4_D6_D8 = 236, + ARM_D3_D5_D7_D9 = 237, + ARM_D4_D6_D8_D10 = 238, + ARM_D5_D7_D9_D11 = 239, + ARM_D6_D8_D10_D12 = 240, + ARM_D7_D9_D11_D13 = 241, + ARM_D8_D10_D12_D14 = 242, + ARM_D9_D11_D13_D15 = 243, + ARM_D10_D12_D14_D16 = 244, + ARM_D11_D13_D15_D17 = 245, + ARM_D12_D14_D16_D18 = 246, + ARM_D13_D15_D17_D19 = 247, + ARM_D14_D16_D18_D20 = 248, + ARM_D15_D17_D19_D21 = 249, + ARM_D16_D18_D20_D22 = 250, + ARM_D17_D19_D21_D23 = 251, + ARM_D18_D20_D22_D24 = 252, + ARM_D19_D21_D23_D25 = 253, + ARM_D20_D22_D24_D26 = 254, + ARM_D21_D23_D25_D27 = 255, + ARM_D22_D24_D26_D28 = 256, + ARM_D23_D25_D27_D29 = 257, + ARM_D24_D26_D28_D30 = 258, + ARM_D25_D27_D29_D31 = 259, + ARM_D1_D2 = 260, + ARM_D3_D4 = 261, + ARM_D5_D6 = 262, + ARM_D7_D8 = 263, + ARM_D9_D10 = 264, + ARM_D11_D12 = 265, + ARM_D13_D14 = 266, + ARM_D15_D16 = 267, + ARM_D17_D18 = 268, + ARM_D19_D20 = 269, + ARM_D21_D22 = 270, + ARM_D23_D24 = 271, + ARM_D25_D26 = 272, + ARM_D27_D28 = 273, + ARM_D29_D30 = 274, + ARM_D1_D2_D3_D4 = 275, + ARM_D3_D4_D5_D6 = 276, + ARM_D5_D6_D7_D8 = 277, + ARM_D7_D8_D9_D10 = 278, + ARM_D9_D10_D11_D12 = 279, + ARM_D11_D12_D13_D14 = 280, + ARM_D13_D14_D15_D16 = 281, + ARM_D15_D16_D17_D18 = 282, + ARM_D17_D18_D19_D20 = 283, + ARM_D19_D20_D21_D22 = 284, + ARM_D21_D22_D23_D24 = 285, + ARM_D23_D24_D25_D26 = 286, + ARM_D25_D26_D27_D28 = 287, + ARM_D27_D28_D29_D30 = 288, + ARM_NUM_TARGET_REGS // 289 +}; + +// Register classes +enum { + ARM_HPRRegClassID = 0, + ARM_SPRRegClassID = 1, + ARM_GPRRegClassID = 2, + ARM_GPRwithAPSRRegClassID = 3, + ARM_SPR_8RegClassID = 4, + ARM_GPRnopcRegClassID = 5, + ARM_rGPRRegClassID = 6, + ARM_tGPRwithpcRegClassID = 7, + ARM_hGPRRegClassID = 8, + ARM_tGPRRegClassID = 9, + ARM_GPRnopc_and_hGPRRegClassID = 10, + ARM_hGPR_and_rGPRRegClassID = 11, + ARM_tcGPRRegClassID = 12, + ARM_tGPR_and_tcGPRRegClassID = 13, + ARM_CCRRegClassID = 14, + ARM_GPRspRegClassID = 15, + ARM_hGPR_and_tGPRwithpcRegClassID = 16, + ARM_hGPR_and_tcGPRRegClassID = 17, + ARM_DPRRegClassID = 18, + ARM_DPR_VFP2RegClassID = 19, + ARM_DPR_8RegClassID = 20, + ARM_GPRPairRegClassID = 21, + ARM_GPRPair_with_gsub_1_in_rGPRRegClassID = 22, + ARM_GPRPair_with_gsub_0_in_tGPRRegClassID = 23, + ARM_GPRPair_with_gsub_0_in_hGPRRegClassID = 24, + ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID = 25, + ARM_GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 26, + ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID = 27, + ARM_GPRPair_with_gsub_1_in_GPRspRegClassID = 28, + ARM_DPairSpcRegClassID = 29, + ARM_DPairSpc_with_ssub_0RegClassID = 30, + ARM_DPairSpc_with_ssub_4RegClassID = 31, + ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID = 32, + ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID = 33, + ARM_DPairRegClassID = 34, + ARM_DPair_with_ssub_0RegClassID = 35, + ARM_QPRRegClassID = 36, + ARM_DPair_with_ssub_2RegClassID = 37, + ARM_DPair_with_dsub_0_in_DPR_8RegClassID = 38, + ARM_QPR_VFP2RegClassID = 39, + ARM_DPair_with_dsub_1_in_DPR_8RegClassID = 40, + ARM_QPR_8RegClassID = 41, + ARM_DTripleRegClassID = 42, + ARM_DTripleSpcRegClassID = 43, + ARM_DTripleSpc_with_ssub_0RegClassID = 44, + ARM_DTriple_with_ssub_0RegClassID = 45, + ARM_DTriple_with_qsub_0_in_QPRRegClassID = 46, + ARM_DTriple_with_ssub_2RegClassID = 47, + ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 48, + ARM_DTripleSpc_with_ssub_4RegClassID = 49, + ARM_DTriple_with_ssub_4RegClassID = 50, + ARM_DTripleSpc_with_ssub_8RegClassID = 51, + ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 52, + ARM_DTriple_with_dsub_0_in_DPR_8RegClassID = 53, + ARM_DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 54, + ARM_DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 55, + ARM_DTriple_with_dsub_1_in_DPR_8RegClassID = 56, + ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 57, + ARM_DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID = 58, + ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 59, + ARM_DTriple_with_dsub_2_in_DPR_8RegClassID = 60, + ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 61, + ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 62, + ARM_DTriple_with_qsub_0_in_QPR_8RegClassID = 63, + ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 64, + ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 65, + ARM_DQuadSpcRegClassID = 66, + ARM_DQuadSpc_with_ssub_0RegClassID = 67, + ARM_DQuadSpc_with_ssub_4RegClassID = 68, + ARM_DQuadSpc_with_ssub_8RegClassID = 69, + ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 70, + ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 71, + ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 72, + ARM_DQuadRegClassID = 73, + ARM_DQuad_with_ssub_0RegClassID = 74, + ARM_DQuad_with_ssub_2RegClassID = 75, + ARM_QQPRRegClassID = 76, + ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 77, + ARM_DQuad_with_ssub_4RegClassID = 78, + ARM_DQuad_with_ssub_6RegClassID = 79, + ARM_DQuad_with_dsub_0_in_DPR_8RegClassID = 80, + ARM_DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 81, + ARM_DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82, + ARM_DQuad_with_dsub_1_in_DPR_8RegClassID = 83, + ARM_DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 84, + ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 85, + ARM_DQuad_with_dsub_2_in_DPR_8RegClassID = 86, + ARM_DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 87, + ARM_DQuad_with_dsub_3_in_DPR_8RegClassID = 88, + ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89, + ARM_DQuad_with_qsub_0_in_QPR_8RegClassID = 90, + ARM_DQuad_with_qsub_1_in_QPR_8RegClassID = 91, + ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 92, + ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 93, + ARM_QQQQPRRegClassID = 94, + ARM_QQQQPR_with_ssub_0RegClassID = 95, + ARM_QQQQPR_with_ssub_4RegClassID = 96, + ARM_QQQQPR_with_ssub_8RegClassID = 97, + ARM_QQQQPR_with_ssub_12RegClassID = 98, + ARM_QQQQPR_with_dsub_0_in_DPR_8RegClassID = 99, + ARM_QQQQPR_with_dsub_2_in_DPR_8RegClassID = 100, + ARM_QQQQPR_with_dsub_4_in_DPR_8RegClassID = 101, + ARM_QQQQPR_with_dsub_6_in_DPR_8RegClassID = 102, +}; + +// Subregister indices +enum { + ARM_NoSubRegister, + ARM_dsub_0, // 1 + ARM_dsub_1, // 2 + ARM_dsub_2, // 3 + ARM_dsub_3, // 4 + ARM_dsub_4, // 5 + ARM_dsub_5, // 6 + ARM_dsub_6, // 7 + ARM_dsub_7, // 8 + ARM_gsub_0, // 9 + ARM_gsub_1, // 10 + ARM_qqsub_0, // 11 + ARM_qqsub_1, // 12 + ARM_qsub_0, // 13 + ARM_qsub_1, // 14 + ARM_qsub_2, // 15 + ARM_qsub_3, // 16 + ARM_ssub_0, // 17 + ARM_ssub_1, // 18 + ARM_ssub_2, // 19 + ARM_ssub_3, // 20 + ARM_ssub_4, // 21 + ARM_ssub_5, // 22 + ARM_ssub_6, // 23 + ARM_ssub_7, // 24 + ARM_ssub_8, // 25 + ARM_ssub_9, // 26 + ARM_ssub_10, // 27 + ARM_ssub_11, // 28 + ARM_ssub_12, // 29 + ARM_ssub_13, // 30 + ARM_dsub_7_then_ssub_0, // 31 + ARM_dsub_7_then_ssub_1, // 32 + ARM_ssub_0_ssub_1_ssub_4_ssub_5, // 33 + ARM_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, // 34 + ARM_ssub_2_ssub_3_ssub_6_ssub_7, // 35 + ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, // 36 + ARM_ssub_2_ssub_3_ssub_4_ssub_5, // 37 + ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, // 38 + ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 39 + ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40 + ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7, // 41 + ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 42 + ARM_ssub_4_ssub_5_ssub_8_ssub_9, // 43 + ARM_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 44 + ARM_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 45 + ARM_ssub_6_ssub_7_dsub_5, // 46 + ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47 + ARM_ssub_6_ssub_7_dsub_5_dsub_7, // 48 + ARM_ssub_6_ssub_7_ssub_8_ssub_9, // 49 + ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50 + ARM_ssub_8_ssub_9_ssub_12_ssub_13, // 51 + ARM_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52 + ARM_dsub_5_dsub_7, // 53 + ARM_dsub_5_ssub_12_ssub_13_dsub_7, // 54 + ARM_dsub_5_ssub_12_ssub_13, // 55 + ARM_ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56 + ARM_NUM_TARGET_SUBREGS +}; + +#endif // GET_REGINFO_ENUM + +#ifdef GET_REGINFO_MC_DESC +#undef GET_REGINFO_MC_DESC + + +static const MCPhysReg ARMRegDiffLists[] = { + /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, + /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, + /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, + /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, + /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0, + /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0, + /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0, + /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0, + /* 91 */ 40, 1, 1, 1, 1, 1, 0, + /* 98 */ 65196, 1, 1, 1, 1, 1, 0, + /* 105 */ 40, 1, 1, 1, 1, 0, + /* 111 */ 42, 1, 1, 1, 1, 0, + /* 117 */ 42, 1, 1, 1, 0, + /* 122 */ 64510, 1, 1, 1, 0, + /* 127 */ 65015, 1, 1, 1, 0, + /* 132 */ 65282, 1, 1, 1, 0, + /* 137 */ 65348, 1, 1, 1, 0, + /* 142 */ 13, 1, 1, 0, + /* 146 */ 42, 1, 1, 0, + /* 150 */ 65388, 1, 1, 0, + /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0, + /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0, + /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0, + /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0, + /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0, + /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0, + /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0, + /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0, + /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0, + /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0, + /* 254 */ 65489, 133, 65416, 1, 1, 0, + /* 260 */ 65490, 133, 65416, 1, 1, 0, + /* 266 */ 65491, 133, 65416, 1, 1, 0, + /* 272 */ 65492, 133, 65416, 1, 1, 0, + /* 278 */ 65493, 133, 65416, 1, 1, 0, + /* 284 */ 65494, 133, 65416, 1, 1, 0, + /* 290 */ 65495, 133, 65416, 1, 1, 0, + /* 296 */ 65496, 133, 65416, 1, 1, 0, + /* 302 */ 65497, 133, 65416, 1, 1, 0, + /* 308 */ 65498, 133, 65416, 1, 1, 0, + /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0, + /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0, + /* 332 */ 65136, 1, 3, 1, 3, 1, 0, + /* 339 */ 65326, 1, 3, 1, 0, + /* 344 */ 13, 1, 0, + /* 347 */ 14, 1, 0, + /* 350 */ 65, 1, 0, + /* 353 */ 65500, 65, 1, 65471, 66, 1, 0, + /* 360 */ 65291, 66, 1, 65470, 67, 1, 0, + /* 367 */ 65439, 65, 1, 65472, 67, 1, 0, + /* 374 */ 65501, 67, 1, 65469, 68, 1, 0, + /* 381 */ 65439, 66, 1, 65471, 68, 1, 0, + /* 388 */ 65292, 68, 1, 65468, 69, 1, 0, + /* 395 */ 65439, 67, 1, 65470, 69, 1, 0, + /* 402 */ 65502, 69, 1, 65467, 70, 1, 0, + /* 409 */ 65439, 68, 1, 65469, 70, 1, 0, + /* 416 */ 65293, 70, 1, 65466, 71, 1, 0, + /* 423 */ 65439, 69, 1, 65468, 71, 1, 0, + /* 430 */ 65503, 71, 1, 65465, 72, 1, 0, + /* 437 */ 65439, 70, 1, 65467, 72, 1, 0, + /* 444 */ 65294, 72, 1, 65464, 73, 1, 0, + /* 451 */ 65439, 71, 1, 65466, 73, 1, 0, + /* 458 */ 65504, 73, 1, 65463, 74, 1, 0, + /* 465 */ 65439, 72, 1, 65465, 74, 1, 0, + /* 472 */ 65295, 74, 1, 65462, 75, 1, 0, + /* 479 */ 65439, 73, 1, 65464, 75, 1, 0, + /* 486 */ 65505, 75, 1, 65461, 76, 1, 0, + /* 493 */ 65439, 74, 1, 65463, 76, 1, 0, + /* 500 */ 65296, 76, 1, 65460, 77, 1, 0, + /* 507 */ 65439, 75, 1, 65462, 77, 1, 0, + /* 514 */ 65506, 77, 1, 65459, 78, 1, 0, + /* 521 */ 65439, 76, 1, 65461, 78, 1, 0, + /* 528 */ 65297, 78, 1, 65458, 79, 1, 0, + /* 535 */ 65439, 77, 1, 65460, 79, 1, 0, + /* 542 */ 65507, 79, 1, 65457, 80, 1, 0, + /* 549 */ 65439, 78, 1, 65459, 80, 1, 0, + /* 556 */ 65045, 1, 0, + /* 559 */ 65260, 1, 0, + /* 562 */ 65299, 1, 0, + /* 565 */ 65300, 1, 0, + /* 568 */ 65301, 1, 0, + /* 571 */ 65302, 1, 0, + /* 574 */ 65303, 1, 0, + /* 577 */ 65304, 1, 0, + /* 580 */ 65305, 1, 0, + /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0, + /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0, + /* 600 */ 65488, 13, 121, 65416, 1, 0, + /* 606 */ 65489, 13, 121, 65416, 1, 0, + /* 612 */ 65490, 13, 121, 65416, 1, 0, + /* 618 */ 65491, 13, 121, 65416, 1, 0, + /* 624 */ 65492, 13, 121, 65416, 1, 0, + /* 630 */ 65493, 13, 121, 65416, 1, 0, + /* 636 */ 65494, 13, 121, 65416, 1, 0, + /* 642 */ 65495, 13, 121, 65416, 1, 0, + /* 648 */ 65496, 13, 121, 65416, 1, 0, + /* 654 */ 65497, 13, 121, 65416, 1, 0, + /* 660 */ 65498, 13, 121, 65416, 1, 0, + /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0, + /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0, + /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0, + /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0, + /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0, + /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0, + /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0, + /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0, + /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0, + /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0, + /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0, + /* 765 */ 65488, 133, 65416, 1, 0, + /* 770 */ 65499, 134, 65416, 1, 0, + /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0, + /* 783 */ 65432, 1, 0, + /* 786 */ 65433, 1, 0, + /* 789 */ 65434, 1, 0, + /* 792 */ 65435, 1, 0, + /* 795 */ 65436, 1, 0, + /* 798 */ 65437, 1, 0, + /* 801 */ 65464, 1, 0, + /* 804 */ 65508, 1, 0, + /* 807 */ 65509, 1, 0, + /* 810 */ 65510, 1, 0, + /* 813 */ 65511, 1, 0, + /* 816 */ 65512, 1, 0, + /* 819 */ 65513, 1, 0, + /* 822 */ 65514, 1, 0, + /* 825 */ 65515, 1, 0, + /* 828 */ 65520, 1, 0, + /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0, + /* 839 */ 65136, 1, 3, 1, 2, 0, + /* 845 */ 65326, 1, 2, 0, + /* 849 */ 65080, 1, 3, 1, 2, 2, 0, + /* 856 */ 65136, 1, 2, 2, 0, + /* 861 */ 65080, 1, 2, 2, 2, 0, + /* 867 */ 65330, 2, 2, 2, 0, + /* 872 */ 65080, 1, 3, 2, 2, 0, + /* 878 */ 65358, 2, 2, 0, + /* 882 */ 65080, 1, 3, 1, 3, 2, 0, + /* 889 */ 65136, 1, 3, 2, 0, + /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0, + /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0, + /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0, + /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0, + /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0, + /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0, + /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0, + /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0, + /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0, + /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0, + /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0, + /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0, + /* 1038 */ 65344, 2, 2, 93, 2, 0, + /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0, + /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0, + /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0, + /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0, + /* 1080 */ 65439, 2, 0, + /* 1083 */ 65453, 2, 0, + /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0, + /* 1094 */ 65136, 1, 3, 1, 3, 0, + /* 1100 */ 65326, 1, 3, 0, + /* 1104 */ 5, 0, + /* 1106 */ 140, 65486, 13, 0, + /* 1110 */ 14, 0, + /* 1112 */ 126, 65501, 15, 0, + /* 1116 */ 10, 66, 0, + /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0, + /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0, + /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0, + /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0, + /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0, + /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0, + /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0, + /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0, + /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0, + /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0, + /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0, + /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0, + /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0, + /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0, + /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0, + /* 1359 */ 91, 0, + /* 1361 */ 98, 0, + /* 1363 */ 99, 0, + /* 1365 */ 100, 0, + /* 1367 */ 101, 0, + /* 1369 */ 102, 0, + /* 1371 */ 103, 0, + /* 1373 */ 104, 0, + /* 1375 */ 65374, 1, 1, 20, 75, 135, 0, + /* 1382 */ 65374, 1, 1, 21, 74, 136, 0, + /* 1389 */ 65374, 1, 1, 22, 73, 137, 0, + /* 1396 */ 65374, 1, 1, 23, 72, 138, 0, + /* 1403 */ 65374, 1, 1, 24, 71, 139, 0, + /* 1410 */ 65374, 1, 1, 25, 70, 140, 0, + /* 1417 */ 65374, 1, 1, 26, 69, 141, 0, + /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0, + /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0, + /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0, + /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0, + /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0, + /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0, + /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0, + /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0, + /* 1526 */ 157, 0, + /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0, + /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0, + /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0, + /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0, + /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0, + /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0, + /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0, + /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0, + /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0, + /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0, + /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0, + /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0, + /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0, + /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0, + /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0, + /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0, + /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0, + /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0, + /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0, + /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0, + /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0, + /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0, + /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0, + /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0, + /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0, + /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0, + /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0, + /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0, + /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0, + /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0, + /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0, + /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0, + /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0, + /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0, + /* 2455 */ 65487, 13, 121, 65416, 0, + /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0, + /* 2468 */ 65466, 1, 65486, 133, 65416, 0, + /* 2474 */ 65487, 133, 65416, 0, + /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, + /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, + /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0, + /* 2509 */ 65452, 1, 65500, 134, 65417, 0, + /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0, + /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0, + /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0, + /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0, + /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0, + /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0, + /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0, + /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0, + /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0, + /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0, + /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0, + /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0, + /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0, + /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0, + /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0, + /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0, + /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0, + /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0, + /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0, + /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0, + /* 2832 */ 26, 65446, 92, 65445, 0, + /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0, + /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0, + /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0, + /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0, + /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, + /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, + /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0, + /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0, + /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, + /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, + /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0, + /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0, + /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, + /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, + /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0, + /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0, + /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, + /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, + /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, + /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, + /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0, + /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, + /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, + /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, + /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, + /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0, + /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, + /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, + /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, + /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, + /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, + /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0, + /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, + /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, + /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, + /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, + /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, + /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0, + /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, + /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, + /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, + /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, + /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, + /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0, + /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, + /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, + /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, + /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, + /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, + /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0, + /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, + /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, + /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, + /* 3839 */ 65298, 80, 1, 65456, 0, + /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, + /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, + /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0, + /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, + /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, + /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0, + /* 3948 */ 65439, 80, 1, 65457, 0, + /* 3953 */ 28, 65457, 0, + /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, + /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, + /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, + /* 4002 */ 26, 65458, 80, 65457, 0, + /* 4007 */ 65439, 79, 1, 65458, 0, + /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0, + /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0, + /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0, + /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0, + /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0, + /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0, + /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0, + /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0, + /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0, + /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0, + /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0, + /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0, + /* 4114 */ 65445, 65470, 0, + /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0, + /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0, + /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0, + /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0, + /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0, + /* 4182 */ 65534, 0, + /* 4184 */ 65535, 0, +}; + +static const uint16_t ARMSubRegIdxLists[] = { + /* 0 */ 1, 2, 0, + /* 3 */ 1, 17, 18, 2, 0, + /* 8 */ 1, 3, 0, + /* 11 */ 1, 17, 18, 3, 0, + /* 16 */ 9, 10, 0, + /* 19 */ 17, 18, 0, + /* 22 */ 1, 17, 18, 2, 19, 20, 0, + /* 29 */ 1, 17, 18, 3, 21, 22, 0, + /* 36 */ 1, 2, 3, 13, 33, 37, 0, + /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0, + /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0, + /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0, + /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0, + /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0, + /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, + /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, + /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0, + /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0, + /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0, + /* 188 */ 1, 3, 5, 33, 43, 0, + /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0, + /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0, + /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0, + /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0, + /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0, + /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0, + /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0, + /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0, + /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, + /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, + /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, + /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, + /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, +}; + +static const MCRegisterDesc ARMRegDesc[] = { + { 12, 0, 0, 0, 0, 0 }, + { 1235, 16, 16, 2, 66945, 0 }, + { 1268, 16, 16, 2, 66945, 0 }, + { 1240, 16, 16, 2, 66945, 0 }, + { 1199, 16, 16, 2, 66945, 0 }, + { 1250, 16, 16, 2, 66945, 0 }, + { 1226, 16, 16, 2, 17664, 0 }, + { 1257, 16, 16, 2, 17664, 0 }, + { 1205, 16, 16, 2, 66913, 0 }, + { 1211, 16, 16, 2, 66913, 0 }, + { 1232, 16, 16, 2, 66913, 0 }, + { 1196, 16, 16, 2, 66913, 0 }, + { 1223, 16, 1526, 2, 66913, 0 }, + { 1245, 16, 16, 2, 66913, 0 }, + { 119, 350, 4013, 19, 13250, 8 }, + { 248, 357, 2479, 19, 13250, 8 }, + { 363, 364, 3957, 19, 13250, 8 }, + { 479, 378, 3845, 19, 13250, 8 }, + { 605, 392, 3893, 19, 13250, 8 }, + { 723, 406, 3724, 19, 13250, 8 }, + { 837, 420, 3780, 19, 13250, 8 }, + { 943, 434, 3604, 19, 13250, 8 }, + { 1057, 448, 3664, 19, 13250, 8 }, + { 1163, 462, 3484, 19, 13250, 8 }, + { 9, 476, 3544, 19, 13250, 8 }, + { 141, 490, 3364, 19, 13250, 8 }, + { 282, 504, 3424, 19, 13250, 8 }, + { 408, 518, 3244, 19, 13250, 8 }, + { 523, 532, 3304, 19, 13250, 8 }, + { 649, 546, 3149, 19, 13250, 8 }, + { 768, 16, 3208, 2, 17761, 0 }, + { 882, 16, 3078, 2, 17761, 0 }, + { 988, 16, 3113, 2, 17761, 0 }, + { 1102, 16, 3008, 2, 17761, 0 }, + { 59, 16, 3043, 2, 17761, 0 }, + { 192, 16, 2938, 2, 17761, 0 }, + { 336, 16, 2973, 2, 17761, 0 }, + { 456, 16, 2868, 2, 17761, 0 }, + { 575, 16, 2903, 2, 17761, 0 }, + { 697, 16, 2797, 2, 17761, 0 }, + { 804, 16, 2837, 2, 17761, 0 }, + { 914, 16, 2363, 2, 17761, 0 }, + { 1024, 16, 2411, 2, 17761, 0 }, + { 1134, 16, 2384, 2, 17761, 0 }, + { 95, 16, 2429, 2, 17761, 0 }, + { 224, 16, 2789, 2, 17761, 0 }, + { 390, 16, 16, 2, 17761, 0 }, + { 125, 16, 16, 2, 17761, 0 }, + { 257, 16, 16, 2, 17761, 0 }, + { 381, 16, 16, 2, 17761, 0 }, + { 122, 353, 1112, 22, 2196, 11 }, + { 254, 374, 775, 22, 2196, 11 }, + { 378, 402, 314, 22, 2196, 11 }, + { 500, 430, 244, 22, 2196, 11 }, + { 629, 458, 234, 22, 2196, 11 }, + { 744, 486, 224, 22, 2196, 11 }, + { 861, 514, 214, 22, 2196, 11 }, + { 964, 542, 204, 22, 2196, 11 }, + { 1081, 804, 194, 0, 12818, 20 }, + { 1184, 807, 184, 0, 12818, 20 }, + { 35, 810, 174, 0, 12818, 20 }, + { 168, 813, 164, 0, 12818, 20 }, + { 312, 816, 154, 0, 12818, 20 }, + { 436, 819, 591, 0, 12818, 20 }, + { 555, 822, 2447, 0, 12818, 20 }, + { 677, 825, 1106, 0, 12818, 20 }, + { 128, 16, 1373, 2, 66913, 0 }, + { 260, 16, 1371, 2, 66913, 0 }, + { 384, 16, 1371, 2, 66913, 0 }, + { 506, 16, 1369, 2, 66913, 0 }, + { 632, 16, 1369, 2, 66913, 0 }, + { 750, 16, 1367, 2, 66913, 0 }, + { 864, 16, 1367, 2, 66913, 0 }, + { 970, 16, 1365, 2, 66913, 0 }, + { 1084, 16, 1365, 2, 66913, 0 }, + { 1190, 16, 1363, 2, 66913, 0 }, + { 39, 16, 1363, 2, 66913, 0 }, + { 176, 16, 1361, 2, 66913, 0 }, + { 316, 16, 1359, 2, 66913, 0 }, + { 131, 16, 4021, 2, 65585, 0 }, + { 269, 16, 4012, 2, 65585, 0 }, + { 387, 16, 2490, 2, 65585, 0 }, + { 509, 16, 2478, 2, 65585, 0 }, + { 635, 16, 3974, 2, 65585, 0 }, + { 753, 16, 3956, 2, 65585, 0 }, + { 867, 16, 3863, 2, 65585, 0 }, + { 973, 16, 3844, 2, 65585, 0 }, + { 1087, 16, 3914, 2, 65585, 0 }, + { 1193, 16, 3892, 2, 65585, 0 }, + { 43, 16, 3745, 2, 65585, 0 }, + { 180, 16, 3723, 2, 65585, 0 }, + { 320, 16, 3803, 2, 65585, 0 }, + { 440, 16, 3779, 2, 65585, 0 }, + { 559, 16, 3627, 2, 65585, 0 }, + { 681, 16, 3603, 2, 65585, 0 }, + { 788, 16, 3687, 2, 65585, 0 }, + { 898, 16, 3663, 2, 65585, 0 }, + { 1008, 16, 3507, 2, 65585, 0 }, + { 1118, 16, 3483, 2, 65585, 0 }, + { 79, 16, 3567, 2, 65585, 0 }, + { 212, 16, 3543, 2, 65585, 0 }, + { 356, 16, 3387, 2, 65585, 0 }, + { 472, 16, 3363, 2, 65585, 0 }, + { 595, 16, 3447, 2, 65585, 0 }, + { 713, 16, 3423, 2, 65585, 0 }, + { 824, 16, 3267, 2, 65585, 0 }, + { 930, 16, 3243, 2, 65585, 0 }, + { 1044, 16, 3327, 2, 65585, 0 }, + { 1150, 16, 3303, 2, 65585, 0 }, + { 115, 16, 3172, 2, 65585, 0 }, + { 244, 16, 3148, 2, 65585, 0 }, + { 360, 367, 4015, 29, 5426, 23 }, + { 476, 381, 2502, 29, 5426, 23 }, + { 602, 395, 3992, 29, 5426, 23 }, + { 720, 409, 3882, 29, 5426, 23 }, + { 834, 423, 3936, 29, 5426, 23 }, + { 940, 437, 3767, 29, 5426, 23 }, + { 1054, 451, 3827, 29, 5426, 23 }, + { 1160, 465, 3651, 29, 5426, 23 }, + { 6, 479, 3711, 29, 5426, 23 }, + { 151, 493, 3531, 29, 5426, 23 }, + { 278, 507, 3591, 29, 5426, 23 }, + { 404, 521, 3411, 29, 5426, 23 }, + { 519, 535, 3471, 29, 5426, 23 }, + { 645, 549, 3291, 29, 5426, 23 }, + { 764, 4007, 3351, 11, 17602, 35 }, + { 878, 3948, 3196, 11, 13522, 35 }, + { 984, 1080, 3231, 8, 17329, 39 }, + { 1098, 1080, 3101, 8, 17329, 39 }, + { 55, 1080, 3136, 8, 17329, 39 }, + { 204, 1080, 3031, 8, 17329, 39 }, + { 332, 1080, 3066, 8, 17329, 39 }, + { 452, 1080, 2961, 8, 17329, 39 }, + { 571, 1080, 2996, 8, 17329, 39 }, + { 693, 1080, 2891, 8, 17329, 39 }, + { 800, 1080, 2926, 8, 17329, 39 }, + { 910, 1080, 2820, 8, 17329, 39 }, + { 1020, 1080, 2858, 8, 17329, 39 }, + { 1130, 1080, 2401, 8, 17329, 39 }, + { 91, 1080, 2440, 8, 17329, 39 }, + { 236, 1080, 2791, 8, 17329, 39 }, + { 251, 1339, 1114, 168, 1044, 57 }, + { 375, 1319, 347, 168, 1044, 57 }, + { 497, 1299, 142, 168, 1044, 57 }, + { 626, 1279, 142, 168, 1044, 57 }, + { 741, 1259, 142, 168, 1044, 57 }, + { 858, 1239, 142, 168, 1044, 57 }, + { 961, 1219, 142, 168, 1044, 57 }, + { 1078, 1203, 142, 88, 1456, 74 }, + { 1181, 1191, 142, 76, 2114, 87 }, + { 32, 1179, 142, 76, 2114, 87 }, + { 164, 1167, 142, 76, 2114, 87 }, + { 308, 1155, 142, 76, 2114, 87 }, + { 432, 1143, 142, 76, 2114, 87 }, + { 551, 1131, 344, 76, 2114, 87 }, + { 673, 1119, 1108, 76, 2114, 87 }, + { 491, 2156, 16, 474, 4, 149 }, + { 620, 2101, 16, 474, 4, 149 }, + { 735, 2046, 16, 474, 4, 149 }, + { 852, 1991, 16, 474, 4, 149 }, + { 955, 1936, 16, 474, 4, 149 }, + { 1072, 1885, 16, 423, 272, 166 }, + { 1175, 1838, 16, 376, 512, 181 }, + { 26, 1795, 16, 333, 720, 194 }, + { 158, 1756, 16, 294, 1186, 205 }, + { 301, 1717, 16, 294, 1186, 205 }, + { 424, 1678, 16, 294, 1186, 205 }, + { 543, 1639, 16, 294, 1186, 205 }, + { 665, 1600, 16, 294, 1186, 205 }, + { 1219, 4114, 16, 16, 17856, 2 }, + { 263, 783, 16, 16, 8946, 5 }, + { 503, 786, 16, 16, 8946, 5 }, + { 747, 789, 16, 16, 8946, 5 }, + { 967, 792, 16, 16, 8946, 5 }, + { 1187, 795, 16, 16, 8946, 5 }, + { 172, 798, 16, 16, 8946, 5 }, + { 366, 1513, 1113, 63, 1570, 28 }, + { 482, 4169, 2511, 63, 1570, 28 }, + { 611, 1500, 778, 63, 1570, 28 }, + { 726, 4156, 770, 63, 1570, 28 }, + { 843, 1487, 317, 63, 1570, 28 }, + { 946, 4143, 660, 63, 1570, 28 }, + { 1063, 1474, 308, 63, 1570, 28 }, + { 1166, 4130, 654, 63, 1570, 28 }, + { 16, 1461, 302, 63, 1570, 28 }, + { 134, 4117, 648, 63, 1570, 28 }, + { 289, 1448, 296, 63, 1570, 28 }, + { 412, 4101, 642, 63, 1570, 28 }, + { 531, 1435, 290, 63, 1570, 28 }, + { 653, 4088, 636, 63, 1570, 28 }, + { 776, 1424, 284, 52, 1680, 42 }, + { 886, 4079, 630, 43, 1872, 48 }, + { 996, 1417, 278, 36, 2401, 53 }, + { 1106, 4072, 624, 36, 2401, 53 }, + { 67, 1410, 272, 36, 2401, 53 }, + { 184, 4065, 618, 36, 2401, 53 }, + { 344, 1403, 266, 36, 2401, 53 }, + { 460, 4058, 612, 36, 2401, 53 }, + { 583, 1396, 260, 36, 2401, 53 }, + { 701, 4051, 606, 36, 2401, 53 }, + { 812, 1389, 254, 36, 2401, 53 }, + { 918, 4044, 600, 36, 2401, 53 }, + { 1032, 1382, 765, 36, 2401, 53 }, + { 1138, 4037, 2455, 36, 2401, 53 }, + { 103, 1375, 2474, 36, 2401, 53 }, + { 216, 4030, 1107, 36, 2401, 53 }, + { 599, 1026, 4018, 212, 5314, 92 }, + { 717, 1014, 3953, 212, 5314, 92 }, + { 831, 1002, 4002, 212, 5314, 92 }, + { 937, 990, 3909, 212, 5314, 92 }, + { 1051, 978, 3909, 212, 5314, 92 }, + { 1157, 966, 3798, 212, 5314, 92 }, + { 3, 954, 3798, 212, 5314, 92 }, + { 148, 942, 3682, 212, 5314, 92 }, + { 275, 930, 3682, 212, 5314, 92 }, + { 401, 918, 3562, 212, 5314, 92 }, + { 515, 906, 3562, 212, 5314, 92 }, + { 641, 894, 3442, 212, 5314, 92 }, + { 760, 1070, 3442, 202, 17506, 99 }, + { 874, 1060, 3322, 202, 13426, 99 }, + { 980, 1052, 3322, 194, 14226, 105 }, + { 1094, 1044, 3226, 194, 13698, 105 }, + { 51, 1038, 3226, 188, 14049, 110 }, + { 200, 1038, 3131, 188, 14049, 110 }, + { 328, 1038, 3131, 188, 14049, 110 }, + { 448, 1038, 3061, 188, 14049, 110 }, + { 567, 1038, 3061, 188, 14049, 110 }, + { 689, 1038, 2991, 188, 14049, 110 }, + { 796, 1038, 2991, 188, 14049, 110 }, + { 906, 1038, 2921, 188, 14049, 110 }, + { 1016, 1038, 2921, 188, 14049, 110 }, + { 1126, 1038, 2832, 188, 14049, 110 }, + { 87, 1038, 2855, 188, 14049, 110 }, + { 232, 1038, 2794, 188, 14049, 110 }, + { 828, 2677, 4010, 276, 5170, 114 }, + { 934, 2659, 3951, 276, 5170, 114 }, + { 1048, 2641, 3951, 276, 5170, 114 }, + { 1154, 2623, 3842, 276, 5170, 114 }, + { 0, 2605, 3842, 276, 5170, 114 }, + { 145, 2587, 3743, 276, 5170, 114 }, + { 272, 2569, 3743, 276, 5170, 114 }, + { 398, 2551, 3625, 276, 5170, 114 }, + { 512, 2533, 3625, 276, 5170, 114 }, + { 638, 2515, 3505, 276, 5170, 114 }, + { 756, 2773, 3505, 260, 17378, 123 }, + { 870, 2757, 3385, 260, 13298, 123 }, + { 976, 2743, 3385, 246, 14114, 131 }, + { 1090, 2729, 3265, 246, 13586, 131 }, + { 47, 2717, 3265, 234, 13954, 138 }, + { 196, 2705, 3170, 234, 13778, 138 }, + { 324, 2695, 3170, 224, 13873, 144 }, + { 444, 2695, 3099, 224, 13873, 144 }, + { 563, 2695, 3099, 224, 13873, 144 }, + { 685, 2695, 3029, 224, 13873, 144 }, + { 792, 2695, 3029, 224, 13873, 144 }, + { 902, 2695, 2959, 224, 13873, 144 }, + { 1012, 2695, 2959, 224, 13873, 144 }, + { 1122, 2695, 2856, 224, 13873, 144 }, + { 83, 2695, 2856, 224, 13873, 144 }, + { 228, 2695, 2795, 224, 13873, 144 }, + { 369, 360, 2509, 22, 1956, 11 }, + { 614, 388, 583, 22, 1956, 11 }, + { 846, 416, 756, 22, 1956, 11 }, + { 1066, 444, 747, 22, 1956, 11 }, + { 19, 472, 738, 22, 1956, 11 }, + { 293, 500, 729, 22, 1956, 11 }, + { 535, 528, 720, 22, 1956, 11 }, + { 780, 3839, 711, 3, 2336, 16 }, + { 1000, 562, 702, 0, 8898, 20 }, + { 71, 565, 693, 0, 8898, 20 }, + { 348, 568, 684, 0, 8898, 20 }, + { 587, 571, 675, 0, 8898, 20 }, + { 816, 574, 666, 0, 8898, 20 }, + { 1036, 577, 2460, 0, 8898, 20 }, + { 107, 580, 2468, 0, 8898, 20 }, + { 608, 2343, 2488, 148, 900, 57 }, + { 840, 2323, 588, 148, 900, 57 }, + { 1060, 2303, 588, 148, 900, 57 }, + { 13, 2283, 588, 148, 900, 57 }, + { 286, 2263, 588, 148, 900, 57 }, + { 527, 2243, 588, 148, 900, 57 }, + { 772, 2225, 588, 130, 1328, 66 }, + { 992, 2211, 588, 116, 1776, 81 }, + { 63, 1588, 588, 104, 2034, 87 }, + { 340, 1576, 588, 104, 2034, 87 }, + { 579, 1564, 588, 104, 2034, 87 }, + { 808, 1552, 588, 104, 2034, 87 }, + { 1028, 1540, 588, 104, 2034, 87 }, + { 99, 1528, 2382, 104, 2034, 87 }, +}; + + // HPR Register Class... + static const MCPhysReg HPR[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, + }; + // HPR Bit set. + static const uint8_t HPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + // SPR Register Class... + static const MCPhysReg SPR[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, + }; + // SPR Bit set. + static const uint8_t SPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, + }; + // GPR Register Class... + static const MCPhysReg GPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, + }; + // GPR Bit set. + static const uint8_t GPRBits[] = { + 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, + }; + // GPRwithAPSR Register Class... + static const MCPhysReg GPRwithAPSR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV, + }; + // GPRwithAPSR Bit set. + static const uint8_t GPRwithAPSRBits[] = { + 0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, + }; + // SPR_8 Register Class... + static const MCPhysReg SPR_8[] = { + ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, + }; + // SPR_8 Bit set. + static const uint8_t SPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, + }; + // GPRnopc Register Class... + static const MCPhysReg GPRnopc[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, + }; + // GPRnopc Bit set. + static const uint8_t GPRnopcBits[] = { + 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, + }; + // rGPR Register Class... + static const MCPhysReg rGPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, + }; + // rGPR Bit set. + static const uint8_t rGPRBits[] = { + 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, + }; + // tGPRwithpc Register Class... + static const MCPhysReg tGPRwithpc[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_PC, + }; + // tGPRwithpc Bit set. + static const uint8_t tGPRwithpcBits[] = { + 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, + }; + // hGPR Register Class... + static const MCPhysReg hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, + }; + // hGPR Bit set. + static const uint8_t hGPRBits[] = { + 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, + }; + // tGPR Register Class... + static const MCPhysReg tGPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, + }; + // tGPR Bit set. + static const uint8_t tGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, + }; + // GPRnopc_and_hGPR Register Class... + static const MCPhysReg GPRnopc_and_hGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, + }; + // GPRnopc_and_hGPR Bit set. + static const uint8_t GPRnopc_and_hGPRBits[] = { + 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, + }; + // hGPR_and_rGPR Register Class... + static const MCPhysReg hGPR_and_rGPR[] = { + ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, + }; + // hGPR_and_rGPR Bit set. + static const uint8_t hGPR_and_rGPRBits[] = { + 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, + }; + // tcGPR Register Class... + static const MCPhysReg tcGPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12, + }; + // tcGPR Bit set. + static const uint8_t tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, + }; + // tGPR_and_tcGPR Register Class... + static const MCPhysReg tGPR_and_tcGPR[] = { + ARM_R0, ARM_R1, ARM_R2, ARM_R3, + }; + // tGPR_and_tcGPR Bit set. + static const uint8_t tGPR_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, + }; + // CCR Register Class... + static const MCPhysReg CCR[] = { + ARM_CPSR, + }; + // CCR Bit set. + static const uint8_t CCRBits[] = { + 0x08, + }; + // GPRsp Register Class... + static const MCPhysReg GPRsp[] = { + ARM_SP, + }; + // GPRsp Bit set. + static const uint8_t GPRspBits[] = { + 0x00, 0x10, + }; + // hGPR_and_tGPRwithpc Register Class... + static const MCPhysReg hGPR_and_tGPRwithpc[] = { + ARM_PC, + }; + // hGPR_and_tGPRwithpc Bit set. + static const uint8_t hGPR_and_tGPRwithpcBits[] = { + 0x00, 0x08, + }; + // hGPR_and_tcGPR Register Class... + static const MCPhysReg hGPR_and_tcGPR[] = { + ARM_R12, + }; + // hGPR_and_tcGPR Bit set. + static const uint8_t hGPR_and_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + }; + // DPR Register Class... + static const MCPhysReg DPR[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, + }; + // DPR Bit set. + static const uint8_t DPRBits[] = { + 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, + }; + // DPR_VFP2 Register Class... + static const MCPhysReg DPR_VFP2[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, + }; + // DPR_VFP2 Bit set. + static const uint8_t DPR_VFP2Bits[] = { + 0x00, 0xc0, 0xff, 0x3f, + }; + // DPR_8 Register Class... + static const MCPhysReg DPR_8[] = { + ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, + }; + // DPR_8 Bit set. + static const uint8_t DPR_8Bits[] = { + 0x00, 0xc0, 0x3f, + }; + // GPRPair Register Class... + static const MCPhysReg GPRPair[] = { + ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, + }; + // GPRPair Bit set. + static const uint8_t GPRPairBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, + }; + // GPRPair_with_gsub_1_in_rGPR Register Class... + static const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = { + ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, + }; + // GPRPair_with_gsub_1_in_rGPR Bit set. + static const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, + }; + // GPRPair_with_gsub_0_in_tGPR Register Class... + static const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = { + ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, + }; + // GPRPair_with_gsub_0_in_tGPR Bit set. + static const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, + }; + // GPRPair_with_gsub_0_in_hGPR Register Class... + static const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = { + ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, + }; + // GPRPair_with_gsub_0_in_hGPR Bit set. + static const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, + }; + // GPRPair_with_gsub_0_in_tcGPR Register Class... + static const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = { + ARM_R0_R1, ARM_R2_R3, ARM_R12_SP, + }; + // GPRPair_with_gsub_0_in_tcGPR Bit set. + static const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, + }; + // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class... + static const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = { + ARM_R8_R9, ARM_R10_R11, + }; + // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set. + static const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, + }; + // GPRPair_with_gsub_1_in_tcGPR Register Class... + static const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = { + ARM_R0_R1, ARM_R2_R3, + }; + // GPRPair_with_gsub_1_in_tcGPR Bit set. + static const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, + }; + // GPRPair_with_gsub_1_in_GPRsp Register Class... + static const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = { + ARM_R12_SP, + }; + // GPRPair_with_gsub_1_in_GPRsp Bit set. + static const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + }; + // DPairSpc Register Class... + static const MCPhysReg DPairSpc[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31, + }; + // DPairSpc Bit set. + static const uint8_t DPairSpcBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, + }; + // DPairSpc_with_ssub_0 Register Class... + static const MCPhysReg DPairSpc_with_ssub_0[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, + }; + // DPairSpc_with_ssub_0 Bit set. + static const uint8_t DPairSpc_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, + }; + // DPairSpc_with_ssub_4 Register Class... + static const MCPhysReg DPairSpc_with_ssub_4[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, + }; + // DPairSpc_with_ssub_4 Bit set. + static const uint8_t DPairSpc_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, + }; + // DPairSpc_with_dsub_0_in_DPR_8 Register Class... + static const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, + }; + // DPairSpc_with_dsub_0_in_DPR_8 Bit set. + static const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, + }; + // DPairSpc_with_dsub_2_in_DPR_8 Register Class... + static const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = { + ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, + }; + // DPairSpc_with_dsub_2_in_DPR_8 Bit set. + static const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, + }; + // DPair Register Class... + static const MCPhysReg DPair[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, ARM_Q15, + }; + // DPair Bit set. + static const uint8_t DPairBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, + }; + // DPair_with_ssub_0 Register Class... + static const MCPhysReg DPair_with_ssub_0[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, + }; + // DPair_with_ssub_0 Bit set. + static const uint8_t DPair_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, + }; + // QPR Register Class... + static const MCPhysReg QPR[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, + }; + // QPR Bit set. + static const uint8_t QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, + }; + // DPair_with_ssub_2 Register Class... + static const MCPhysReg DPair_with_ssub_2[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, + }; + // DPair_with_ssub_2 Bit set. + static const uint8_t DPair_with_ssub_2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, + }; + // DPair_with_dsub_0_in_DPR_8 Register Class... + static const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, + }; + // DPair_with_dsub_0_in_DPR_8 Bit set. + static const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, + }; + // QPR_VFP2 Register Class... + static const MCPhysReg QPR_VFP2[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, + }; + // QPR_VFP2 Bit set. + static const uint8_t QPR_VFP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, + }; + // DPair_with_dsub_1_in_DPR_8 Register Class... + static const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = { + ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, + }; + // DPair_with_dsub_1_in_DPR_8 Bit set. + static const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + }; + // QPR_8 Register Class... + static const MCPhysReg QPR_8[] = { + ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, + }; + // QPR_8 Bit set. + static const uint8_t QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, + }; + // DTriple Register Class... + static const MCPhysReg DTriple[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, ARM_D28_D29_D30, ARM_D29_D30_D31, + }; + // DTriple Bit set. + static const uint8_t DTripleBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, + }; + // DTripleSpc Register Class... + static const MCPhysReg DTripleSpc[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, + }; + // DTripleSpc Bit set. + static const uint8_t DTripleSpcBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, + }; + // DTripleSpc_with_ssub_0 Register Class... + static const MCPhysReg DTripleSpc_with_ssub_0[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, + }; + // DTripleSpc_with_ssub_0 Bit set. + static const uint8_t DTripleSpc_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, + }; + // DTriple_with_ssub_0 Register Class... + static const MCPhysReg DTriple_with_ssub_0[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, + }; + // DTriple_with_ssub_0 Bit set. + static const uint8_t DTriple_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, + }; + // DTriple_with_qsub_0_in_QPR Register Class... + static const MCPhysReg DTriple_with_qsub_0_in_QPR[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30, + }; + // DTriple_with_qsub_0_in_QPR Bit set. + static const uint8_t DTriple_with_qsub_0_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, + }; + // DTriple_with_ssub_2 Register Class... + static const MCPhysReg DTriple_with_ssub_2[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, + }; + // DTriple_with_ssub_2 Bit set. + static const uint8_t DTriple_with_ssub_2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, + }; + // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... + static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31, + }; + // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. + static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, + }; + // DTripleSpc_with_ssub_4 Register Class... + static const MCPhysReg DTripleSpc_with_ssub_4[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, + }; + // DTripleSpc_with_ssub_4 Bit set. + static const uint8_t DTripleSpc_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, + }; + // DTriple_with_ssub_4 Register Class... + static const MCPhysReg DTriple_with_ssub_4[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, + }; + // DTriple_with_ssub_4 Bit set. + static const uint8_t DTriple_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, + }; + // DTripleSpc_with_ssub_8 Register Class... + static const MCPhysReg DTripleSpc_with_ssub_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + }; + // DTripleSpc_with_ssub_8 Bit set. + static const uint8_t DTripleSpc_with_ssub_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, + }; + // DTripleSpc_with_dsub_0_in_DPR_8 Register Class... + static const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + }; + // DTripleSpc_with_dsub_0_in_DPR_8 Bit set. + static const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, + }; + // DTriple_with_dsub_0_in_DPR_8 Register Class... + static const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, + }; + // DTriple_with_dsub_0_in_DPR_8 Bit set. + static const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, + }; + // DTriple_with_qsub_0_in_QPR_VFP2 Register Class... + static const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, + }; + // DTriple_with_qsub_0_in_QPR_VFP2 Bit set. + static const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, + }; + // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... + static const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, + }; + // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. + static const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, + }; + // DTriple_with_dsub_1_in_DPR_8 Register Class... + static const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, + }; + // DTriple_with_dsub_1_in_DPR_8 Bit set. + static const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, + }; + // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class... + static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, + }; + // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set. + static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, + }; + // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Register Class... + static const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, + }; + // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Bit set. + static const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, + }; + // DTripleSpc_with_dsub_2_in_DPR_8 Register Class... + static const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, + }; + // DTripleSpc_with_dsub_2_in_DPR_8 Bit set. + static const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, + }; + // DTriple_with_dsub_2_in_DPR_8 Register Class... + static const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = { + ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, + }; + // DTriple_with_dsub_2_in_DPR_8 Bit set. + static const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, + }; + // DTripleSpc_with_dsub_4_in_DPR_8 Register Class... + static const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + }; + // DTripleSpc_with_dsub_4_in_DPR_8 Bit set. + static const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, + }; + // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... + static const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, + }; + // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. + static const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, + }; + // DTriple_with_qsub_0_in_QPR_8 Register Class... + static const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, + }; + // DTriple_with_qsub_0_in_QPR_8 Bit set. + static const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, + }; + // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class... + static const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = { + ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, + }; + // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set. + static const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, + }; + // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... + static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { + ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, + }; + // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. + static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, + }; + // DQuadSpc Register Class... + static const MCPhysReg DQuadSpc[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, + }; + // DQuadSpc Bit set. + static const uint8_t DQuadSpcBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, + }; + // DQuadSpc_with_ssub_0 Register Class... + static const MCPhysReg DQuadSpc_with_ssub_0[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, + }; + // DQuadSpc_with_ssub_0 Bit set. + static const uint8_t DQuadSpc_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, + }; + // DQuadSpc_with_ssub_4 Register Class... + static const MCPhysReg DQuadSpc_with_ssub_4[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, + }; + // DQuadSpc_with_ssub_4 Bit set. + static const uint8_t DQuadSpc_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, + }; + // DQuadSpc_with_ssub_8 Register Class... + static const MCPhysReg DQuadSpc_with_ssub_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, + }; + // DQuadSpc_with_ssub_8 Bit set. + static const uint8_t DQuadSpc_with_ssub_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, + }; + // DQuadSpc_with_dsub_0_in_DPR_8 Register Class... + static const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, + }; + // DQuadSpc_with_dsub_0_in_DPR_8 Bit set. + static const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, + }; + // DQuadSpc_with_dsub_2_in_DPR_8 Register Class... + static const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, + }; + // DQuadSpc_with_dsub_2_in_DPR_8 Bit set. + static const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, + }; + // DQuadSpc_with_dsub_4_in_DPR_8 Register Class... + static const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = { + ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, + }; + // DQuadSpc_with_dsub_4_in_DPR_8 Bit set. + static const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, + }; + // DQuad Register Class... + static const MCPhysReg DQuad[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, ARM_Q14_Q15, + }; + // DQuad Bit set. + static const uint8_t DQuadBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, + }; + // DQuad_with_ssub_0 Register Class... + static const MCPhysReg DQuad_with_ssub_0[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, + }; + // DQuad_with_ssub_0 Bit set. + static const uint8_t DQuad_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, + }; + // DQuad_with_ssub_2 Register Class... + static const MCPhysReg DQuad_with_ssub_2[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, + }; + // DQuad_with_ssub_2 Bit set. + static const uint8_t DQuad_with_ssub_2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, + }; + // QQPR Register Class... + static const MCPhysReg QQPR[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15, + }; + // QQPR Bit set. + static const uint8_t QQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, + }; + // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... + static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30, + }; + // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. + static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, + }; + // DQuad_with_ssub_4 Register Class... + static const MCPhysReg DQuad_with_ssub_4[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, + }; + // DQuad_with_ssub_4 Bit set. + static const uint8_t DQuad_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, + }; + // DQuad_with_ssub_6 Register Class... + static const MCPhysReg DQuad_with_ssub_6[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, + }; + // DQuad_with_ssub_6 Bit set. + static const uint8_t DQuad_with_ssub_6Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, + }; + // DQuad_with_dsub_0_in_DPR_8 Register Class... + static const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, + }; + // DQuad_with_dsub_0_in_DPR_8 Bit set. + static const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, + }; + // DQuad_with_qsub_0_in_QPR_VFP2 Register Class... + static const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, + }; + // DQuad_with_qsub_0_in_QPR_VFP2 Bit set. + static const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... + static const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, + }; + // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. + static const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, + }; + // DQuad_with_dsub_1_in_DPR_8 Register Class... + static const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, + }; + // DQuad_with_dsub_1_in_DPR_8 Bit set. + static const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, + }; + // DQuad_with_qsub_1_in_QPR_VFP2 Register Class... + static const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, + }; + // DQuad_with_qsub_1_in_QPR_VFP2 Bit set. + static const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, + }; + // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class... + static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, + }; + // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set. + static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, + }; + // DQuad_with_dsub_2_in_DPR_8 Register Class... + static const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, + }; + // DQuad_with_dsub_2_in_DPR_8 Bit set. + static const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, + }; + // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... + static const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, + }; + // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. + static const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, + }; + // DQuad_with_dsub_3_in_DPR_8 Register Class... + static const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = { + ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, + }; + // DQuad_with_dsub_3_in_DPR_8 Bit set. + static const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, + }; + // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... + static const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, + }; + // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. + static const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, + }; + // DQuad_with_qsub_0_in_QPR_8 Register Class... + static const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, + }; + // DQuad_with_qsub_0_in_QPR_8 Bit set. + static const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, + }; + // DQuad_with_qsub_1_in_QPR_8 Register Class... + static const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = { + ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, + }; + // DQuad_with_qsub_1_in_QPR_8 Bit set. + static const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, + }; + // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... + static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, + }; + // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. + static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, + }; + // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... + static const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { + ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, + }; + // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. + static const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, + }; + // QQQQPR Register Class... + static const MCPhysReg QQQQPR[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, ARM_Q12_Q13_Q14_Q15, + }; + // QQQQPR Bit set. + static const uint8_t QQQQPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, + }; + // QQQQPR_with_ssub_0 Register Class... + static const MCPhysReg QQQQPR_with_ssub_0[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, + }; + // QQQQPR_with_ssub_0 Bit set. + static const uint8_t QQQQPR_with_ssub_0Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, + }; + // QQQQPR_with_ssub_4 Register Class... + static const MCPhysReg QQQQPR_with_ssub_4[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, + }; + // QQQQPR_with_ssub_4 Bit set. + static const uint8_t QQQQPR_with_ssub_4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, + }; + // QQQQPR_with_ssub_8 Register Class... + static const MCPhysReg QQQQPR_with_ssub_8[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, + }; + // QQQQPR_with_ssub_8 Bit set. + static const uint8_t QQQQPR_with_ssub_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, + }; + // QQQQPR_with_ssub_12 Register Class... + static const MCPhysReg QQQQPR_with_ssub_12[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, + }; + // QQQQPR_with_ssub_12 Bit set. + static const uint8_t QQQQPR_with_ssub_12Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, + }; + // QQQQPR_with_dsub_0_in_DPR_8 Register Class... + static const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, + }; + // QQQQPR_with_dsub_0_in_DPR_8 Bit set. + static const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, + }; + // QQQQPR_with_dsub_2_in_DPR_8 Register Class... + static const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, + }; + // QQQQPR_with_dsub_2_in_DPR_8 Bit set. + static const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + }; + // QQQQPR_with_dsub_4_in_DPR_8 Register Class... + static const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, + }; + // QQQQPR_with_dsub_4_in_DPR_8 Bit set. + static const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, + }; + // QQQQPR_with_dsub_6_in_DPR_8 Register Class... + static const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = { + ARM_Q0_Q1_Q2_Q3, + }; + // QQQQPR_with_dsub_6_in_DPR_8 Bit set. + static const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, + }; + + +static const MCRegisterClass ARMMCRegisterClasses[] = { + { HPR, HPRBits, sizeof(HPRBits) }, + { SPR, SPRBits, sizeof(SPRBits) }, + { GPR, GPRBits, sizeof(GPRBits) }, + { GPRwithAPSR, GPRwithAPSRBits, sizeof(GPRwithAPSRBits) }, + { SPR_8, SPR_8Bits, sizeof(SPR_8Bits) }, + { GPRnopc, GPRnopcBits, sizeof(GPRnopcBits) }, + { rGPR, rGPRBits, sizeof(rGPRBits) }, + { tGPRwithpc, tGPRwithpcBits, sizeof(tGPRwithpcBits) }, + { hGPR, hGPRBits, sizeof(hGPRBits) }, + { tGPR, tGPRBits, sizeof(tGPRBits) }, + { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, sizeof(GPRnopc_and_hGPRBits) }, + { hGPR_and_rGPR, hGPR_and_rGPRBits, sizeof(hGPR_and_rGPRBits) }, + { tcGPR, tcGPRBits, sizeof(tcGPRBits) }, + { tGPR_and_tcGPR, tGPR_and_tcGPRBits, sizeof(tGPR_and_tcGPRBits) }, + { CCR, CCRBits, sizeof(CCRBits) }, + { GPRsp, GPRspBits, sizeof(GPRspBits) }, + { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, sizeof(hGPR_and_tGPRwithpcBits) }, + { hGPR_and_tcGPR, hGPR_and_tcGPRBits, sizeof(hGPR_and_tcGPRBits) }, + { DPR, DPRBits, sizeof(DPRBits) }, + { DPR_VFP2, DPR_VFP2Bits, sizeof(DPR_VFP2Bits) }, + { DPR_8, DPR_8Bits, sizeof(DPR_8Bits) }, + { GPRPair, GPRPairBits, sizeof(GPRPairBits) }, + { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, sizeof(GPRPair_with_gsub_1_in_rGPRBits) }, + { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, sizeof(GPRPair_with_gsub_0_in_tGPRBits) }, + { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, sizeof(GPRPair_with_gsub_0_in_hGPRBits) }, + { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, sizeof(GPRPair_with_gsub_0_in_tcGPRBits) }, + { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits) }, + { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, sizeof(GPRPair_with_gsub_1_in_tcGPRBits) }, + { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, sizeof(GPRPair_with_gsub_1_in_GPRspBits) }, + { DPairSpc, DPairSpcBits, sizeof(DPairSpcBits) }, + { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, sizeof(DPairSpc_with_ssub_0Bits) }, + { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, sizeof(DPairSpc_with_ssub_4Bits) }, + { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits) }, + { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits) }, + { DPair, DPairBits, sizeof(DPairBits) }, + { DPair_with_ssub_0, DPair_with_ssub_0Bits, sizeof(DPair_with_ssub_0Bits) }, + { QPR, QPRBits, sizeof(QPRBits) }, + { DPair_with_ssub_2, DPair_with_ssub_2Bits, sizeof(DPair_with_ssub_2Bits) }, + { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, sizeof(DPair_with_dsub_0_in_DPR_8Bits) }, + { QPR_VFP2, QPR_VFP2Bits, sizeof(QPR_VFP2Bits) }, + { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, sizeof(DPair_with_dsub_1_in_DPR_8Bits) }, + { QPR_8, QPR_8Bits, sizeof(QPR_8Bits) }, + { DTriple, DTripleBits, sizeof(DTripleBits) }, + { DTripleSpc, DTripleSpcBits, sizeof(DTripleSpcBits) }, + { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, sizeof(DTripleSpc_with_ssub_0Bits) }, + { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, sizeof(DTriple_with_ssub_0Bits) }, + { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_qsub_0_in_QPRBits) }, + { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, sizeof(DTriple_with_ssub_2Bits) }, + { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, sizeof(DTripleSpc_with_ssub_4Bits) }, + { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, sizeof(DTriple_with_ssub_4Bits) }, + { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, sizeof(DTripleSpc_with_ssub_8Bits) }, + { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits) }, + { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, sizeof(DTriple_with_dsub_0_in_DPR_8Bits) }, + { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits) }, + { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, sizeof(DTriple_with_dsub_1_in_DPR_8Bits) }, + { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits) }, + { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits) }, + { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits) }, + { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, sizeof(DTriple_with_dsub_2_in_DPR_8Bits) }, + { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits) }, + { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, sizeof(DTriple_with_qsub_0_in_QPR_8Bits) }, + { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits) }, + { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) }, + { DQuadSpc, DQuadSpcBits, sizeof(DQuadSpcBits) }, + { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, sizeof(DQuadSpc_with_ssub_0Bits) }, + { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, sizeof(DQuadSpc_with_ssub_4Bits) }, + { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, sizeof(DQuadSpc_with_ssub_8Bits) }, + { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits) }, + { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits) }, + { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits) }, + { DQuad, DQuadBits, sizeof(DQuadBits) }, + { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, sizeof(DQuad_with_ssub_0Bits) }, + { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, sizeof(DQuad_with_ssub_2Bits) }, + { QQPR, QQPRBits, sizeof(QQPRBits) }, + { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, sizeof(DQuad_with_ssub_4Bits) }, + { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, sizeof(DQuad_with_ssub_6Bits) }, + { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, sizeof(DQuad_with_dsub_0_in_DPR_8Bits) }, + { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits) }, + { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, sizeof(DQuad_with_dsub_1_in_DPR_8Bits) }, + { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits) }, + { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits) }, + { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, sizeof(DQuad_with_dsub_2_in_DPR_8Bits) }, + { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, sizeof(DQuad_with_dsub_3_in_DPR_8Bits) }, + { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, sizeof(DQuad_with_qsub_0_in_QPR_8Bits) }, + { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, sizeof(DQuad_with_qsub_1_in_QPR_8Bits) }, + { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) }, + { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, + { QQQQPR, QQQQPRBits, sizeof(QQQQPRBits) }, + { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, sizeof(QQQQPR_with_ssub_0Bits) }, + { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, sizeof(QQQQPR_with_ssub_4Bits) }, + { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, sizeof(QQQQPR_with_ssub_8Bits) }, + { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, sizeof(QQQQPR_with_ssub_12Bits) }, + { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits) }, + { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits) }, + { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits) }, + { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits) }, +}; + +#endif // GET_REGINFO_MC_DESC diff --git a/capstone/arch/ARM/ARMGenRegisterName.inc b/capstone/arch/ARM/ARMGenRegisterName.inc new file mode 100644 index 000000000..22c7d05fb --- /dev/null +++ b/capstone/arch/ARM/ARMGenRegisterName.inc @@ -0,0 +1,231 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo) +{ + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0, + /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, + /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, + /* 39 */ 'd', '1', '0', 0, + /* 43 */ 'q', '1', '0', 0, + /* 47 */ 's', '1', '0', 0, + /* 51 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0, + /* 67 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, + /* 83 */ 'd', '2', '0', 0, + /* 87 */ 's', '2', '0', 0, + /* 91 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0, + /* 107 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, + /* 123 */ 'd', '3', '0', 0, + /* 127 */ 's', '3', '0', 0, + /* 131 */ 'd', '0', 0, + /* 134 */ 'q', '0', 0, + /* 137 */ 'm', 'v', 'f', 'r', '0', 0, + /* 143 */ 's', '0', 0, + /* 146 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, + /* 157 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0, + /* 170 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, + /* 184 */ 'R', '1', '0', '_', 'R', '1', '1', 0, + /* 192 */ 'd', '1', '1', 0, + /* 196 */ 'q', '1', '1', 0, + /* 200 */ 's', '1', '1', 0, + /* 204 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, + /* 216 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0, + /* 232 */ 'd', '2', '1', 0, + /* 236 */ 's', '2', '1', 0, + /* 240 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, + /* 252 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0, + /* 268 */ 'd', '3', '1', 0, + /* 272 */ 's', '3', '1', 0, + /* 276 */ 'Q', '0', '_', 'Q', '1', 0, + /* 282 */ 'R', '0', '_', 'R', '1', 0, + /* 288 */ 'd', '1', 0, + /* 291 */ 'q', '1', 0, + /* 294 */ 'm', 'v', 'f', 'r', '1', 0, + /* 300 */ 's', '1', 0, + /* 303 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0, + /* 317 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, + /* 332 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, + /* 347 */ 'd', '1', '2', 0, + /* 351 */ 'q', '1', '2', 0, + /* 355 */ 's', '1', '2', 0, + /* 359 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0, + /* 375 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, + /* 391 */ 'd', '2', '2', 0, + /* 395 */ 's', '2', '2', 0, + /* 399 */ 'D', '0', '_', 'D', '2', 0, + /* 405 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, + /* 414 */ 'Q', '1', '_', 'Q', '2', 0, + /* 420 */ 'd', '2', 0, + /* 423 */ 'q', '2', 0, + /* 426 */ 'm', 'v', 'f', 'r', '2', 0, + /* 432 */ 's', '2', 0, + /* 435 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0, + /* 443 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0, + /* 457 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, + /* 469 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, + /* 485 */ 'd', '1', '3', 0, + /* 489 */ 'q', '1', '3', 0, + /* 493 */ 's', '1', '3', 0, + /* 497 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0, + /* 513 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, + /* 525 */ 'd', '2', '3', 0, + /* 529 */ 's', '2', '3', 0, + /* 533 */ 'D', '1', '_', 'D', '3', 0, + /* 539 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, + /* 548 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, + /* 560 */ 'R', '2', '_', 'R', '3', 0, + /* 566 */ 'd', '3', 0, + /* 569 */ 'q', '3', 0, + /* 572 */ 'r', '3', 0, + /* 575 */ 's', '3', 0, + /* 578 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0, + /* 593 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, + /* 609 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, + /* 625 */ 'd', '1', '4', 0, + /* 629 */ 'q', '1', '4', 0, + /* 633 */ 's', '1', '4', 0, + /* 637 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0, + /* 653 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, + /* 669 */ 'd', '2', '4', 0, + /* 673 */ 's', '2', '4', 0, + /* 677 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0, + /* 686 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, + /* 698 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, + /* 710 */ 'd', '4', 0, + /* 713 */ 'q', '4', 0, + /* 716 */ 'r', '4', 0, + /* 719 */ 's', '4', 0, + /* 722 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0, + /* 737 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, + /* 749 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, + /* 765 */ 'd', '1', '5', 0, + /* 769 */ 'q', '1', '5', 0, + /* 773 */ 's', '1', '5', 0, + /* 777 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0, + /* 793 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, + /* 805 */ 'd', '2', '5', 0, + /* 809 */ 's', '2', '5', 0, + /* 813 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0, + /* 822 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, + /* 831 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, + /* 843 */ 'R', '4', '_', 'R', '5', 0, + /* 849 */ 'd', '5', 0, + /* 852 */ 'q', '5', 0, + /* 855 */ 'r', '5', 0, + /* 858 */ 's', '5', 0, + /* 861 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0, + /* 877 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, + /* 893 */ 'd', '1', '6', 0, + /* 897 */ 's', '1', '6', 0, + /* 901 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0, + /* 917 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, + /* 933 */ 'd', '2', '6', 0, + /* 937 */ 's', '2', '6', 0, + /* 941 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0, + /* 953 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, + /* 965 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, + /* 977 */ 'd', '6', 0, + /* 980 */ 'q', '6', 0, + /* 983 */ 'r', '6', 0, + /* 986 */ 's', '6', 0, + /* 989 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0, + /* 1005 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, + /* 1017 */ 'd', '1', '7', 0, + /* 1021 */ 's', '1', '7', 0, + /* 1025 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0, + /* 1041 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, + /* 1053 */ 'd', '2', '7', 0, + /* 1057 */ 's', '2', '7', 0, + /* 1061 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0, + /* 1073 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, + /* 1082 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, + /* 1094 */ 'R', '6', '_', 'R', '7', 0, + /* 1100 */ 'd', '7', 0, + /* 1103 */ 'q', '7', 0, + /* 1106 */ 'r', '7', 0, + /* 1109 */ 's', '7', 0, + /* 1112 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0, + /* 1128 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, + /* 1144 */ 'd', '1', '8', 0, + /* 1148 */ 's', '1', '8', 0, + /* 1152 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0, + /* 1168 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, + /* 1184 */ 'd', '2', '8', 0, + /* 1188 */ 's', '2', '8', 0, + /* 1192 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0, + /* 1204 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, + /* 1216 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, + /* 1228 */ 'd', '8', 0, + /* 1231 */ 'q', '8', 0, + /* 1234 */ 'r', '8', 0, + /* 1237 */ 's', '8', 0, + /* 1240 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0, + /* 1256 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, + /* 1268 */ 'd', '1', '9', 0, + /* 1272 */ 's', '1', '9', 0, + /* 1276 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0, + /* 1292 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, + /* 1304 */ 'd', '2', '9', 0, + /* 1308 */ 's', '2', '9', 0, + /* 1312 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0, + /* 1324 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, + /* 1333 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, + /* 1345 */ 'R', '8', '_', 'R', '9', 0, + /* 1351 */ 'd', '9', 0, + /* 1354 */ 'q', '9', 0, + /* 1357 */ 's', '9', 0, + /* 1360 */ 'R', '1', '2', '_', 'S', 'P', 0, + /* 1367 */ 's', 'b', 0, + /* 1370 */ 'p', 'c', 0, + /* 1373 */ 'f', 'p', 'e', 'x', 'c', 0, + /* 1379 */ 'f', 'p', 's', 'i', 'd', 0, + /* 1385 */ 'i', 't', 's', 't', 'a', 't', 'e', 0, + /* 1393 */ 's', 'l', 0, + /* 1396 */ 'f', 'p', 0, + /* 1399 */ 'i', 'p', 0, + /* 1402 */ 's', 'p', 0, + /* 1405 */ 'f', 'p', 's', 'c', 'r', 0, + /* 1411 */ 'l', 'r', 0, + /* 1414 */ 'a', 'p', 's', 'r', 0, + /* 1419 */ 'c', 'p', 's', 'r', 0, + /* 1424 */ 's', 'p', 's', 'r', 0, + /* 1429 */ 'f', 'p', 'i', 'n', 's', 't', 0, + /* 1436 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0, + /* 1447 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0, + }; + + static const uint16_t RegAsmOffset[] = { + 1414, 1447, 1419, 1373, 1429, 1405, 1436, 1379, 1385, 1411, 1370, 1402, 1424, 131, + 288, 420, 566, 710, 849, 977, 1100, 1228, 1351, 39, 192, 347, 485, 625, + 765, 893, 1017, 1144, 1268, 83, 232, 391, 525, 669, 805, 933, 1053, 1184, + 1304, 123, 268, 435, 137, 294, 426, 134, 291, 423, 569, 713, 852, 980, + 1103, 1231, 1354, 43, 196, 351, 489, 629, 769, 140, 297, 429, 572, 716, + 855, 983, 1106, 1234, 1367, 1393, 1396, 1399, 143, 300, 432, 575, 719, 858, + 986, 1109, 1237, 1357, 47, 200, 355, 493, 633, 773, 897, 1021, 1148, 1272, + 87, 236, 395, 529, 673, 809, 937, 1057, 1188, 1308, 127, 272, 399, 533, + 680, 816, 947, 1067, 1198, 1318, 6, 163, 309, 449, 585, 729, 869, 997, + 1120, 1248, 59, 224, 367, 505, 645, 785, 909, 1033, 1160, 1284, 99, 260, + 276, 414, 554, 704, 837, 971, 1088, 1222, 1339, 32, 176, 339, 477, 617, + 757, 548, 698, 831, 965, 1082, 1216, 1333, 26, 170, 332, 469, 609, 749, + 1360, 282, 560, 843, 1094, 1345, 184, 405, 539, 689, 822, 956, 1073, 1207, + 1324, 16, 146, 320, 457, 597, 737, 881, 1005, 1132, 1256, 71, 204, 379, + 513, 657, 793, 921, 1041, 1172, 1292, 111, 240, 677, 813, 944, 1064, 1195, + 1315, 3, 160, 306, 446, 581, 725, 865, 993, 1116, 1244, 55, 220, 363, + 501, 641, 781, 905, 1029, 1156, 1280, 95, 256, 941, 1061, 1192, 1312, 0, + 157, 303, 443, 578, 722, 861, 989, 1112, 1240, 51, 216, 359, 497, 637, + 777, 901, 1025, 1152, 1276, 91, 252, 408, 692, 959, 1210, 19, 324, 601, + 885, 1136, 75, 383, 661, 925, 1176, 115, 686, 953, 1204, 13, 317, 593, + 877, 1128, 67, 375, 653, 917, 1168, 107, + }; + + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} diff --git a/capstone/arch/ARM/ARMGenRegisterName_digit.inc b/capstone/arch/ARM/ARMGenRegisterName_digit.inc new file mode 100644 index 000000000..c45010301 --- /dev/null +++ b/capstone/arch/ARM/ARMGenRegisterName_digit.inc @@ -0,0 +1,231 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName_digit(unsigned RegNo) +{ + +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0, + /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, + /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, + /* 39 */ 'd', '1', '0', 0, + /* 43 */ 'q', '1', '0', 0, + /* 47 */ 'r', '1', '0', 0, + /* 51 */ 's', '1', '0', 0, + /* 55 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0, + /* 71 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, + /* 87 */ 'd', '2', '0', 0, + /* 91 */ 's', '2', '0', 0, + /* 95 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0, + /* 111 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, + /* 127 */ 'd', '3', '0', 0, + /* 131 */ 's', '3', '0', 0, + /* 135 */ 'd', '0', 0, + /* 138 */ 'q', '0', 0, + /* 141 */ 'm', 'v', 'f', 'r', '0', 0, + /* 147 */ 's', '0', 0, + /* 150 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, + /* 161 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0, + /* 174 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, + /* 188 */ 'R', '1', '0', '_', 'R', '1', '1', 0, + /* 196 */ 'd', '1', '1', 0, + /* 200 */ 'q', '1', '1', 0, + /* 204 */ 'r', '1', '1', 0, + /* 208 */ 's', '1', '1', 0, + /* 212 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, + /* 224 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0, + /* 240 */ 'd', '2', '1', 0, + /* 244 */ 's', '2', '1', 0, + /* 248 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, + /* 260 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0, + /* 276 */ 'd', '3', '1', 0, + /* 280 */ 's', '3', '1', 0, + /* 284 */ 'Q', '0', '_', 'Q', '1', 0, + /* 290 */ 'R', '0', '_', 'R', '1', 0, + /* 296 */ 'd', '1', 0, + /* 299 */ 'q', '1', 0, + /* 302 */ 'm', 'v', 'f', 'r', '1', 0, + /* 308 */ 's', '1', 0, + /* 311 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0, + /* 325 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, + /* 340 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, + /* 355 */ 'd', '1', '2', 0, + /* 359 */ 'q', '1', '2', 0, + /* 363 */ 'r', '1', '2', 0, + /* 367 */ 's', '1', '2', 0, + /* 371 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0, + /* 387 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, + /* 403 */ 'd', '2', '2', 0, + /* 407 */ 's', '2', '2', 0, + /* 411 */ 'D', '0', '_', 'D', '2', 0, + /* 417 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, + /* 426 */ 'Q', '1', '_', 'Q', '2', 0, + /* 432 */ 'd', '2', 0, + /* 435 */ 'q', '2', 0, + /* 438 */ 'm', 'v', 'f', 'r', '2', 0, + /* 444 */ 's', '2', 0, + /* 447 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0, + /* 455 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0, + /* 469 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, + /* 481 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, + /* 497 */ 'd', '1', '3', 0, + /* 501 */ 'q', '1', '3', 0, + /* 505 */ 'r', '1', '3', 0, + /* 509 */ 's', '1', '3', 0, + /* 513 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0, + /* 529 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, + /* 541 */ 'd', '2', '3', 0, + /* 545 */ 's', '2', '3', 0, + /* 549 */ 'D', '1', '_', 'D', '3', 0, + /* 555 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, + /* 564 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, + /* 576 */ 'R', '2', '_', 'R', '3', 0, + /* 582 */ 'd', '3', 0, + /* 585 */ 'q', '3', 0, + /* 588 */ 'r', '3', 0, + /* 591 */ 's', '3', 0, + /* 594 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0, + /* 609 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, + /* 625 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, + /* 641 */ 'd', '1', '4', 0, + /* 645 */ 'q', '1', '4', 0, + /* 649 */ 'r', '1', '4', 0, + /* 653 */ 's', '1', '4', 0, + /* 657 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0, + /* 673 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, + /* 689 */ 'd', '2', '4', 0, + /* 693 */ 's', '2', '4', 0, + /* 697 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0, + /* 706 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, + /* 718 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, + /* 730 */ 'd', '4', 0, + /* 733 */ 'q', '4', 0, + /* 736 */ 'r', '4', 0, + /* 739 */ 's', '4', 0, + /* 742 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0, + /* 757 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, + /* 769 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, + /* 785 */ 'd', '1', '5', 0, + /* 789 */ 'q', '1', '5', 0, + /* 793 */ 's', '1', '5', 0, + /* 797 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0, + /* 813 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, + /* 825 */ 'd', '2', '5', 0, + /* 829 */ 's', '2', '5', 0, + /* 833 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0, + /* 842 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, + /* 851 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, + /* 863 */ 'R', '4', '_', 'R', '5', 0, + /* 869 */ 'd', '5', 0, + /* 872 */ 'q', '5', 0, + /* 875 */ 'r', '5', 0, + /* 878 */ 's', '5', 0, + /* 881 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0, + /* 897 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, + /* 913 */ 'd', '1', '6', 0, + /* 917 */ 's', '1', '6', 0, + /* 921 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0, + /* 937 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, + /* 953 */ 'd', '2', '6', 0, + /* 957 */ 's', '2', '6', 0, + /* 961 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0, + /* 973 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, + /* 985 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, + /* 997 */ 'd', '6', 0, + /* 1000 */ 'q', '6', 0, + /* 1003 */ 'r', '6', 0, + /* 1006 */ 's', '6', 0, + /* 1009 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0, + /* 1025 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, + /* 1037 */ 'd', '1', '7', 0, + /* 1041 */ 's', '1', '7', 0, + /* 1045 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0, + /* 1061 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, + /* 1073 */ 'd', '2', '7', 0, + /* 1077 */ 's', '2', '7', 0, + /* 1081 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0, + /* 1093 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, + /* 1102 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, + /* 1114 */ 'R', '6', '_', 'R', '7', 0, + /* 1120 */ 'd', '7', 0, + /* 1123 */ 'q', '7', 0, + /* 1126 */ 'r', '7', 0, + /* 1129 */ 's', '7', 0, + /* 1132 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0, + /* 1148 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, + /* 1164 */ 'd', '1', '8', 0, + /* 1168 */ 's', '1', '8', 0, + /* 1172 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0, + /* 1188 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, + /* 1204 */ 'd', '2', '8', 0, + /* 1208 */ 's', '2', '8', 0, + /* 1212 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0, + /* 1224 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, + /* 1236 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, + /* 1248 */ 'd', '8', 0, + /* 1251 */ 'q', '8', 0, + /* 1254 */ 'r', '8', 0, + /* 1257 */ 's', '8', 0, + /* 1260 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0, + /* 1276 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, + /* 1288 */ 'd', '1', '9', 0, + /* 1292 */ 's', '1', '9', 0, + /* 1296 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0, + /* 1312 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, + /* 1324 */ 'd', '2', '9', 0, + /* 1328 */ 's', '2', '9', 0, + /* 1332 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0, + /* 1344 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, + /* 1353 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, + /* 1365 */ 'R', '8', '_', 'R', '9', 0, + /* 1371 */ 'd', '9', 0, + /* 1374 */ 'q', '9', 0, + /* 1377 */ 'r', '9', 0, + /* 1380 */ 's', '9', 0, + /* 1383 */ 'R', '1', '2', '_', 'S', 'P', 0, + /* 1390 */ 'p', 'c', 0, + /* 1393 */ 'f', 'p', 'e', 'x', 'c', 0, + /* 1399 */ 'f', 'p', 's', 'i', 'd', 0, + /* 1405 */ 'i', 't', 's', 't', 'a', 't', 'e', 0, + /* 1413 */ 'f', 'p', 's', 'c', 'r', 0, + /* 1419 */ 'a', 'p', 's', 'r', 0, + /* 1424 */ 'c', 'p', 's', 'r', 0, + /* 1429 */ 's', 'p', 's', 'r', 0, + /* 1434 */ 'f', 'p', 'i', 'n', 's', 't', 0, + /* 1441 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0, + /* 1452 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0, + }; + + static const uint16_t RegAsmOffset[] = { + 1419, 1452, 1424, 1393, 1434, 1413, 1441, 1399, 1405, 649, 1390, 505, 1429, 135, + 296, 432, 582, 730, 869, 997, 1120, 1248, 1371, 39, 196, 355, 497, 641, + 785, 913, 1037, 1164, 1288, 87, 240, 403, 541, 689, 825, 953, 1073, 1204, + 1324, 127, 276, 447, 141, 302, 438, 138, 299, 435, 585, 733, 872, 1000, + 1123, 1251, 1374, 43, 200, 359, 501, 645, 789, 144, 305, 441, 588, 736, + 875, 1003, 1126, 1254, 1377, 47, 204, 363, 147, 308, 444, 591, 739, 878, + 1006, 1129, 1257, 1380, 51, 208, 367, 509, 653, 793, 917, 1041, 1168, 1292, + 91, 244, 407, 545, 693, 829, 957, 1077, 1208, 1328, 131, 280, 411, 549, + 700, 836, 967, 1087, 1218, 1338, 6, 167, 317, 461, 601, 749, 889, 1017, + 1140, 1268, 63, 232, 379, 521, 665, 805, 929, 1053, 1180, 1304, 103, 268, + 284, 426, 570, 724, 857, 991, 1108, 1242, 1359, 32, 180, 347, 489, 633, + 777, 564, 718, 851, 985, 1102, 1236, 1353, 26, 174, 340, 481, 625, 769, + 1383, 290, 576, 863, 1114, 1365, 188, 417, 555, 709, 842, 976, 1093, 1227, + 1344, 16, 150, 328, 469, 613, 757, 901, 1025, 1152, 1276, 75, 212, 391, + 529, 677, 813, 941, 1061, 1192, 1312, 115, 248, 697, 833, 964, 1084, 1215, + 1335, 3, 164, 314, 458, 597, 745, 885, 1013, 1136, 1264, 59, 228, 375, + 517, 661, 801, 925, 1049, 1176, 1300, 99, 264, 961, 1081, 1212, 1332, 0, + 161, 311, 455, 594, 742, 881, 1009, 1132, 1260, 55, 224, 371, 513, 657, + 797, 921, 1045, 1172, 1296, 95, 260, 420, 712, 979, 1230, 19, 332, 617, + 905, 1156, 79, 395, 681, 945, 1196, 119, 706, 973, 1224, 13, 325, 609, + 897, 1148, 71, 387, 673, 937, 1188, 111, + }; + + return AsmStrs+RegAsmOffset[RegNo-1]; +#else + return NULL; +#endif +} diff --git a/capstone/arch/ARM/ARMGenSubtargetInfo.inc b/capstone/arch/ARM/ARMGenSubtargetInfo.inc new file mode 100644 index 000000000..45bfad856 --- /dev/null +++ b/capstone/arch/ARM/ARMGenSubtargetInfo.inc @@ -0,0 +1,162 @@ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +|* Subtarget Enumeration Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +enum { + ARM_ARMv2 = 0, + ARM_ARMv2a = 1, + ARM_ARMv3 = 2, + ARM_ARMv3m = 3, + ARM_ARMv4 = 4, + ARM_ARMv4t = 5, + ARM_ARMv5t = 6, + ARM_ARMv5te = 7, + ARM_ARMv5tej = 8, + ARM_ARMv6 = 9, + ARM_ARMv6j = 10, + ARM_ARMv6k = 11, + ARM_ARMv6kz = 12, + ARM_ARMv6m = 13, + ARM_ARMv6sm = 14, + ARM_ARMv6t2 = 15, + ARM_ARMv7a = 16, + ARM_ARMv7em = 17, + ARM_ARMv7k = 18, + ARM_ARMv7m = 19, + ARM_ARMv7r = 20, + ARM_ARMv7s = 21, + ARM_ARMv7ve = 22, + ARM_ARMv8a = 23, + ARM_ARMv8mBaseline = 24, + ARM_ARMv8mMainline = 25, + ARM_ARMv8r = 26, + ARM_ARMv81a = 27, + ARM_ARMv82a = 28, + ARM_ARMv83a = 29, + ARM_ARMv84a = 30, + ARM_Feature8MSecExt = 31, + ARM_FeatureAClass = 32, + ARM_FeatureAES = 33, + ARM_FeatureAcquireRelease = 34, + ARM_FeatureAvoidMOVsShOp = 35, + ARM_FeatureAvoidPartialCPSR = 36, + ARM_FeatureCRC = 37, + ARM_FeatureCheapPredicableCPSR = 38, + ARM_FeatureCheckVLDnAlign = 39, + ARM_FeatureCrypto = 40, + ARM_FeatureD16 = 41, + ARM_FeatureDB = 42, + ARM_FeatureDFB = 43, + ARM_FeatureDSP = 44, + ARM_FeatureDontWidenVMOVS = 45, + ARM_FeatureDotProd = 46, + ARM_FeatureExecuteOnly = 47, + ARM_FeatureExpandMLx = 48, + ARM_FeatureFP16 = 49, + ARM_FeatureFPAO = 50, + ARM_FeatureFPARMv8 = 51, + ARM_FeatureFullFP16 = 52, + ARM_FeatureFuseAES = 53, + ARM_FeatureFuseLiterals = 54, + ARM_FeatureHWDivARM = 55, + ARM_FeatureHWDivThumb = 56, + ARM_FeatureHasNoBranchPredictor = 57, + ARM_FeatureHasRetAddrStack = 58, + ARM_FeatureHasSlowFPVMLx = 59, + ARM_FeatureHasVMLxHazards = 60, + ARM_FeatureLongCalls = 61, + ARM_FeatureMClass = 62, + ARM_FeatureMP = 63, + ARM_FeatureMuxedUnits = 64, + ARM_FeatureNEON = 65, + ARM_FeatureNEONForFP = 66, + ARM_FeatureNEONForFPMovs = 67, + ARM_FeatureNaClTrap = 68, + ARM_FeatureNoARM = 69, + ARM_FeatureNoMovt = 70, + ARM_FeatureNoNegativeImmediates = 71, + ARM_FeatureNoPostRASched = 72, + ARM_FeatureNonpipelinedVFP = 73, + ARM_FeaturePerfMon = 74, + ARM_FeaturePref32BitThumb = 75, + ARM_FeaturePrefISHSTBarrier = 76, + ARM_FeaturePreferVMOVSR = 77, + ARM_FeatureProfUnpredicate = 78, + ARM_FeatureRAS = 79, + ARM_FeatureRClass = 80, + ARM_FeatureReadTp = 81, + ARM_FeatureReserveR9 = 82, + ARM_FeatureSHA2 = 83, + ARM_FeatureSlowFPBrcc = 84, + ARM_FeatureSlowLoadDSubreg = 85, + ARM_FeatureSlowOddRegister = 86, + ARM_FeatureSlowVDUP32 = 87, + ARM_FeatureSlowVGETLNi32 = 88, + ARM_FeatureSplatVFPToNeon = 89, + ARM_FeatureStrictAlign = 90, + ARM_FeatureThumb2 = 91, + ARM_FeatureTrustZone = 92, + ARM_FeatureUseAA = 93, + ARM_FeatureUseMISched = 94, + ARM_FeatureV7Clrex = 95, + ARM_FeatureVFP2 = 96, + ARM_FeatureVFP3 = 97, + ARM_FeatureVFP4 = 98, + ARM_FeatureVFPOnlySP = 99, + ARM_FeatureVMLxForwarding = 100, + ARM_FeatureVirtualization = 101, + ARM_FeatureZCZeroing = 102, + ARM_HasV4TOps = 103, + ARM_HasV5TEOps = 104, + ARM_HasV5TOps = 105, + ARM_HasV6KOps = 106, + ARM_HasV6MOps = 107, + ARM_HasV6Ops = 108, + ARM_HasV6T2Ops = 109, + ARM_HasV7Ops = 110, + ARM_HasV8MBaselineOps = 111, + ARM_HasV8MMainlineOps = 112, + ARM_HasV8Ops = 113, + ARM_HasV8_1aOps = 114, + ARM_HasV8_2aOps = 115, + ARM_HasV8_3aOps = 116, + ARM_HasV8_4aOps = 117, + ARM_IWMMXT = 118, + ARM_IWMMXT2 = 119, + ARM_ModeSoftFloat = 120, + ARM_ModeThumb = 121, + ARM_ProcA5 = 122, + ARM_ProcA7 = 123, + ARM_ProcA8 = 124, + ARM_ProcA9 = 125, + ARM_ProcA12 = 126, + ARM_ProcA15 = 127, + ARM_ProcA17 = 128, + ARM_ProcA32 = 129, + ARM_ProcA35 = 130, + ARM_ProcA53 = 131, + ARM_ProcA55 = 132, + ARM_ProcA57 = 133, + ARM_ProcA72 = 134, + ARM_ProcA73 = 135, + ARM_ProcA75 = 136, + ARM_ProcExynosM1 = 137, + ARM_ProcKrait = 138, + ARM_ProcKryo = 139, + ARM_ProcM3 = 140, + ARM_ProcR4 = 141, + ARM_ProcR5 = 142, + ARM_ProcR7 = 143, + ARM_ProcR52 = 144, + ARM_ProcSwift = 145, + ARM_XScale = 146, +}; + diff --git a/capstone/arch/ARM/ARMGenSystemRegister.inc b/capstone/arch/ARM/ARMGenSystemRegister.inc new file mode 100644 index 000000000..4c5ce124d --- /dev/null +++ b/capstone/arch/ARM/ARMGenSystemRegister.inc @@ -0,0 +1,270 @@ + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +|* GenSystemRegister Source Fragment *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ + + +enum BankedRegValues { + elr_hyp = 0, + lr_abt = 1, + lr_fiq = 2, + lr_irq = 3, + lr_mon = 4, + lr_svc = 5, + lr_und = 6, + lr_usr = 7, + r10_fiq = 8, + r10_usr = 9, + r11_fiq = 10, + r11_usr = 11, + r12_fiq = 12, + r12_usr = 13, + r8_fiq = 14, + r8_usr = 15, + r9_fiq = 16, + r9_usr = 17, + sp_abt = 18, + sp_fiq = 19, + sp_hyp = 20, + sp_irq = 21, + sp_mon = 22, + sp_svc = 23, + sp_und = 24, + sp_usr = 25, + spsr_abt = 26, + spsr_fiq = 27, + spsr_hyp = 28, + spsr_irq = 29, + spsr_mon = 30, + spsr_svc = 31, + spsr_und = 32, +}; + +static const MClassSysReg MClassSysRegsList[] = { + { "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400, {ARM_FeatureDSP} }, // 0 + { "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00, {ARM_FeatureDSP} }, // 1 + { "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401, {ARM_FeatureDSP} }, // 2 + { "iapsr_nzcvqg", ARM_SYSREG_IAPSR_NZCVQG, 0xC01, 0x301, 0xC01, {ARM_FeatureDSP} }, // 3 + { "eapsr_g", ARM_SYSREG_EAPSR_G, 0x402, 0x2, 0x402, {ARM_FeatureDSP} }, // 4 + { "eapsr_nzcvqg", ARM_SYSREG_EAPSR_NZCVQG, 0xC02, 0x302, 0xC02, {ARM_FeatureDSP} }, // 5 + { "xpsr_g", ARM_SYSREG_XPSR_G, 0x403, 0x3, 0x403, {ARM_FeatureDSP} }, // 6 + { "xpsr_nzcvqg", ARM_SYSREG_XPSR_NZCVQG, 0xC03, 0x303, 0xC03, {ARM_FeatureDSP} }, // 7 + { "apsr", ARM_SYSREG_APSR, 0x800, 0x100, 0x800, { 0 } }, // 8 + { "apsr_nzcvq", ARM_SYSREG_APSR_NZCVQ, 0x1800, 0x200, 0x800, { 0 } }, // 9 + { "iapsr", ARM_SYSREG_IAPSR, 0x801, 0x101, 0x801, { 0 } }, // 10 + { "iapsr_nzcvq", ARM_SYSREG_IAPSR_NZCVQ, 0x1801, 0x201, 0x801, { 0 } }, // 11 + { "eapsr", ARM_SYSREG_EAPSR, 0x802, 0x102, 0x802, { 0 } }, // 12 + { "eapsr_nzcvq", ARM_SYSREG_EAPSR_NZCVQ, 0x1802, 0x202, 0x802, { 0 } }, // 13 + { "xpsr", ARM_SYSREG_XPSR, 0x803, 0x103, 0x803, { 0 } }, // 14 + { "xpsr_nzcvq", ARM_SYSREG_XPSR_NZCVQ, 0x1803, 0x203, 0x803, { 0 } }, // 15 + { "ipsr", ARM_SYSREG_IPSR, 0x805, 0x105, 0x805, { 0 } }, // 16 + { "epsr", ARM_SYSREG_EPSR, 0x806, 0x106, 0x806, { 0 } }, // 17 + { "iepsr", ARM_SYSREG_IEPSR, 0x807, 0x107, 0x807, { 0 } }, // 18 + { "msp", ARM_SYSREG_MSP, 0x808, 0x108, 0x808, { 0 } }, // 19 + { "psp", ARM_SYSREG_PSP, 0x809, 0x109, 0x809, { 0 } }, // 20 + { "msplim", ARM_SYSREG_MSPLIM, 0x80A, 0x10A, 0x80A, {ARM_HasV8MBaselineOps} }, // 21 + { "psplim", ARM_SYSREG_PSPLIM, 0x80B, 0x10B, 0x80B, {ARM_HasV8MBaselineOps} }, // 22 + { "primask", ARM_SYSREG_PRIMASK, 0x810, 0x110, 0x810, { 0 } }, // 23 + { "basepri", ARM_SYSREG_BASEPRI, 0x811, 0x111, 0x811, {ARM_HasV7Ops} }, // 24 + { "basepri_max", ARM_SYSREG_BASEPRI_MAX, 0x812, 0x112, 0x812, {ARM_HasV7Ops} }, // 25 + { "faultmask", ARM_SYSREG_FAULTMASK, 0x813, 0x113, 0x813, {ARM_HasV7Ops} }, // 26 + { "control", ARM_SYSREG_CONTROL, 0x814, 0x114, 0x814, { 0 } }, // 27 + { "msp_ns", ARM_SYSREG_MSP_NS, 0x888, 0x188, 0x888, {ARM_Feature8MSecExt} }, // 28 + { "psp_ns", ARM_SYSREG_PSP_NS, 0x889, 0x189, 0x889, {ARM_Feature8MSecExt} }, // 29 + { "msplim_ns", ARM_SYSREG_MSPLIM_NS, 0x88A, 0x18A, 0x88A, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 30 + { "psplim_ns", ARM_SYSREG_PSPLIM_NS, 0x88B, 0x18B, 0x88B, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 31 + { "primask_ns", ARM_SYSREG_PRIMASK_NS, 0x890, 0x190, 0x890, { 0 } }, // 32 + { "basepri_ns", ARM_SYSREG_BASEPRI_NS, 0x891, 0x191, 0x891, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 33 + { "faultmask_ns", ARM_SYSREG_FAULTMASK_NS, 0x893, 0x193, 0x893, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 34 + { "control_ns", ARM_SYSREG_CONTROL_NS, 0x894, 0x194, 0x894, {ARM_Feature8MSecExt} }, // 35 + { "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898, {ARM_Feature8MSecExt} }, // 36 +}; + +static const BankedReg BankedRegsList[] = { + { "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0 + { "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1 + { "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2 + { "r11_usr", ARM_SYSREG_R11_USR, 0x3 }, // 3 + { "r12_usr", ARM_SYSREG_R12_USR, 0x4 }, // 4 + { "sp_usr", ARM_SYSREG_SP_USR, 0x5 }, // 5 + { "lr_usr", ARM_SYSREG_LR_USR, 0x6 }, // 6 + { "r8_fiq", ARM_SYSREG_R8_FIQ, 0x8 }, // 7 + { "r9_fiq", ARM_SYSREG_R9_FIQ, 0x9 }, // 8 + { "r10_fiq", ARM_SYSREG_R10_FIQ, 0xA }, // 9 + { "r11_fiq", ARM_SYSREG_R11_FIQ, 0xB }, // 10 + { "r12_fiq", ARM_SYSREG_R12_FIQ, 0xC }, // 11 + { "sp_fiq", ARM_SYSREG_SP_FIQ, 0xD }, // 12 + { "lr_fiq", ARM_SYSREG_LR_FIQ, 0xE }, // 13 + { "lr_irq", ARM_SYSREG_LR_IRQ, 0x10 }, // 14 + { "sp_irq", ARM_SYSREG_SP_IRQ, 0x11 }, // 15 + { "lr_svc", ARM_SYSREG_LR_SVC, 0x12 }, // 16 + { "sp_svc", ARM_SYSREG_SP_SVC, 0x13 }, // 17 + { "lr_abt", ARM_SYSREG_LR_ABT, 0x14 }, // 18 + { "sp_abt", ARM_SYSREG_SP_ABT, 0x15 }, // 19 + { "lr_und", ARM_SYSREG_LR_UND, 0x16 }, // 20 + { "sp_und", ARM_SYSREG_SP_UND, 0x17 }, // 21 + { "lr_mon", ARM_SYSREG_LR_MON, 0x1C }, // 22 + { "sp_mon", ARM_SYSREG_SP_MON, 0x1D }, // 23 + { "elr_hyp", ARM_SYSREG_ELR_HYP, 0x1E }, // 24 + { "sp_hyp", ARM_SYSREG_SP_HYP, 0x1F }, // 25 + { "spsr_fiq", ARM_SYSREG_SPSR_FIQ, 0x2E }, // 26 + { "spsr_irq", ARM_SYSREG_SPSR_IRQ, 0x30 }, // 27 + { "spsr_svc", ARM_SYSREG_SPSR_SVC, 0x32 }, // 28 + { "spsr_abt", ARM_SYSREG_SPSR_ABT, 0x34 }, // 29 + { "spsr_und", ARM_SYSREG_SPSR_UND, 0x36 }, // 30 + { "spsr_mon", ARM_SYSREG_SPSR_MON, 0x3C }, // 31 + { "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32 +}; + +const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x0, 0 }, + { 0x1, 2 }, + { 0x2, 4 }, + { 0x3, 6 }, + { 0x100, 8 }, + { 0x101, 10 }, + { 0x102, 12 }, + { 0x103, 14 }, + { 0x105, 16 }, + { 0x106, 17 }, + { 0x107, 18 }, + { 0x108, 19 }, + { 0x109, 20 }, + { 0x10A, 21 }, + { 0x10B, 22 }, + { 0x110, 23 }, + { 0x111, 24 }, + { 0x112, 25 }, + { 0x113, 26 }, + { 0x114, 27 }, + { 0x188, 28 }, + { 0x189, 29 }, + { 0x18A, 30 }, + { 0x18B, 31 }, + { 0x190, 32 }, + { 0x191, 33 }, + { 0x193, 34 }, + { 0x194, 35 }, + { 0x198, 36 }, + { 0x200, 9 }, + { 0x201, 11 }, + { 0x202, 13 }, + { 0x203, 15 }, + { 0x300, 1 }, + { 0x301, 3 }, + { 0x302, 5 }, + { 0x303, 7 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); + if (i == -1) + return NULL; + else + return &MClassSysRegsList[Index[i].index]; +} + +const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x400, 0 }, + { 0x401, 2 }, + { 0x402, 4 }, + { 0x403, 6 }, + { 0x800, 8 }, + { 0x801, 10 }, + { 0x802, 12 }, + { 0x803, 14 }, + { 0x805, 16 }, + { 0x806, 17 }, + { 0x807, 18 }, + { 0x808, 19 }, + { 0x809, 20 }, + { 0x80A, 21 }, + { 0x80B, 22 }, + { 0x810, 23 }, + { 0x811, 24 }, + { 0x812, 25 }, + { 0x813, 26 }, + { 0x814, 27 }, + { 0x888, 28 }, + { 0x889, 29 }, + { 0x88A, 30 }, + { 0x88B, 31 }, + { 0x890, 32 }, + { 0x891, 33 }, + { 0x893, 34 }, + { 0x894, 35 }, + { 0x898, 36 }, + { 0xC00, 1 }, + { 0xC01, 3 }, + { 0xC02, 5 }, + { 0xC03, 7 }, + { 0x1800, 9 }, + { 0x1801, 11 }, + { 0x1802, 13 }, + { 0x1803, 15 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); + if (i == -1) + return NULL; + else + return &MClassSysRegsList[Index[i].index]; +} + +const BankedReg *lookupBankedRegByEncoding(uint8_t encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x0, 0 }, + { 0x1, 1 }, + { 0x2, 2 }, + { 0x3, 3 }, + { 0x4, 4 }, + { 0x5, 5 }, + { 0x6, 6 }, + { 0x8, 7 }, + { 0x9, 8 }, + { 0xA, 9 }, + { 0xB, 10 }, + { 0xC, 11 }, + { 0xD, 12 }, + { 0xE, 13 }, + { 0x10, 14 }, + { 0x11, 15 }, + { 0x12, 16 }, + { 0x13, 17 }, + { 0x14, 18 }, + { 0x15, 19 }, + { 0x16, 20 }, + { 0x17, 21 }, + { 0x1C, 22 }, + { 0x1D, 23 }, + { 0x1E, 24 }, + { 0x1F, 25 }, + { 0x2E, 26 }, + { 0x30, 27 }, + { 0x32, 28 }, + { 0x34, 29 }, + { 0x36, 30 }, + { 0x3C, 31 }, + { 0x3E, 32 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); + if (i == -1) + return NULL; + else + return &BankedRegsList[Index[i].index]; +} + diff --git a/capstone/arch/ARM/ARMInstPrinter.c b/capstone/arch/ARM/ARMInstPrinter.c new file mode 100644 index 000000000..47263ed68 --- /dev/null +++ b/capstone/arch/ARM/ARMInstPrinter.c @@ -0,0 +1,3361 @@ +//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an ARM MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +#ifdef CAPSTONE_HAS_ARM + +#include <stdio.h> // DEBUG +#include <stdlib.h> +#include <string.h> +#include <capstone/platform.h> + +#include "ARMInstPrinter.h" +#include "ARMAddressingModes.h" +#include "ARMBaseInfo.h" +#include "ARMDisassembler.h" +#include "../../MCInst.h" +#include "../../SStream.h" +#include "../../MCRegisterInfo.h" +#include "../../utils.h" +#include "ARMMapping.h" + +#define GET_SUBTARGETINFO_ENUM +#include "ARMGenSubtargetInfo.inc" + +#include "ARMGenSystemRegister.inc" + +static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo); + +// Autogenerated by tblgen. +static void printInstruction(MCInst *MI, SStream *O); +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); +static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O); + +static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O); +static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O); +static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O); +static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O); +static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); +static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0); +static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O); +static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O); +static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); +static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O); +static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O); +static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); + +static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O); +static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O); +static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O); +static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned); +static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O); +static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O); +static void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale); +static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O); +static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O); +static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O); +static void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); +static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); +static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); +static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O); +static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O); +static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O); +static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O); +static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O); +static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O); +static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O); +static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O); +static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O); +static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O); +static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O); +static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O); +static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); + +static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); +static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); +static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, int64_t Angle, int64_t Remainder); +static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); + + +#ifndef CAPSTONE_DIET +// copy & normalize access info +static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index) +{ + const uint8_t *arr = ARM_get_op_access(h, id); + + if (!arr || arr[index] == CS_AC_IGNORE) + return 0; + + return arr[index]; +} +#endif + +static void set_mem_access(MCInst *MI, bool status) +{ + if (MI->csh->detail != CS_OPT_ON) + return; + + MI->csh->doing_mem = status; + if (status) { +#ifndef CAPSTONE_DIET + uint8_t access; +#endif + + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; + +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->ac_idx++; +#endif + } else { + // done, create the next operand slot + MI->flat_insn->detail->arm.op_count++; + } +} + +static void op_addImm(MCInst *MI, int v) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; + MI->flat_insn->detail->arm.op_count++; + } +} + +#define GET_INSTRINFO_ENUM +#include "ARMGenInstrInfo.inc" + +static void printCustomAliasOperand(MCInst *MI, + unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS); + +#define PRINT_ALIAS_INSTR +#include "ARMGenAsmWriter.inc" +#include "ARMGenRegisterName.inc" +#include "ARMGenRegisterName_digit.inc" + +void ARM_getRegName(cs_struct *handle, int value) +{ + if (value == CS_OPT_SYNTAX_NOREGNAME) { + handle->get_regname = getRegisterName_digit; + handle->reg_name = ARM_reg_name2;; + } else { + handle->get_regname = getRegisterName; + handle->reg_name = ARM_reg_name;; + } +} + +/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. +/// +/// getSORegOffset returns an integer from 0-31, representing '32' as 0. +static unsigned translateShiftImm(unsigned imm) +{ + // lsr #32 and asr #32 exist, but should be encoded as a 0. + //assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); + if (imm == 0) + return 32; + return imm; +} + +/// Prints the shift value with an immediate value. +static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm) +{ + if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) + return; + + SStream_concat0(O, ", "); + + //assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0"); + SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc; + else + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc; + } + + if (ShOpc != ARM_AM_rrx) { + SStream_concat0(O, " "); + SStream_concat(O, "#%u", translateShiftImm(ShImm)); + if (MI->csh->detail) { + if (MI->csh->doing_mem) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm); + else + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm); + } + } +} + +static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo) +{ +#ifndef CAPSTONE_DIET + SStream_concat0(OS, h->get_regname(RegNo)); +#endif +} + +// TODO +static const name_map insn_update_flgs[] = { + { ARM_INS_CMN, "cmn" }, + { ARM_INS_CMP, "cmp" }, + { ARM_INS_TEQ, "teq" }, + { ARM_INS_TST, "tst" }, + + { ARM_INS_ADC, "adcs" }, + { ARM_INS_ADD, "adds" }, + { ARM_INS_AND, "ands" }, + { ARM_INS_ASR, "asrs" }, + { ARM_INS_BIC, "bics" }, + { ARM_INS_EOR, "eors" }, + { ARM_INS_LSL, "lsls" }, + { ARM_INS_LSR, "lsrs" }, + { ARM_INS_MLA, "mlas" }, + { ARM_INS_MOV, "movs" }, + { ARM_INS_MUL, "muls" }, + { ARM_INS_MVN, "mvns" }, + { ARM_INS_ORN, "orns" }, + { ARM_INS_ORR, "orrs" }, + { ARM_INS_ROR, "rors" }, + { ARM_INS_RRX, "rrxs" }, + { ARM_INS_RSB, "rsbs" }, + { ARM_INS_RSC, "rscs" }, + { ARM_INS_SBC, "sbcs" }, + { ARM_INS_SMLAL, "smlals" }, + { ARM_INS_SMULL, "smulls" }, + { ARM_INS_SUB, "subs" }, + { ARM_INS_UMLAL, "umlals" }, + { ARM_INS_UMULL, "umulls" }, + + { ARM_INS_UADD8, "uadd8" }, +}; + +void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) +{ + if (((cs_struct *)ud)->detail != CS_OPT_ON) + return; + + // check if this insn requests write-back + if (mci->writeback || (strrchr(insn_asm, '!')) != NULL) { + insn->detail->arm.writeback = true; + } else if (mci->csh->mode & CS_MODE_THUMB) { + // handle some special instructions with writeback + //printf(">> Opcode = %u\n", mci->Opcode); + switch(mci->Opcode) { + default: + break; + case ARM_t2LDC2L_PRE: + case ARM_t2LDC2_PRE: + case ARM_t2LDCL_PRE: + case ARM_t2LDC_PRE: + + case ARM_t2LDRB_PRE: + case ARM_t2LDRD_PRE: + case ARM_t2LDRH_PRE: + case ARM_t2LDRSB_PRE: + case ARM_t2LDRSH_PRE: + case ARM_t2LDR_PRE: + + case ARM_t2STC2L_PRE: + case ARM_t2STC2_PRE: + case ARM_t2STCL_PRE: + case ARM_t2STC_PRE: + + case ARM_t2STRB_PRE: + case ARM_t2STRD_PRE: + case ARM_t2STRH_PRE: + case ARM_t2STR_PRE: + + case ARM_t2LDC2L_POST: + case ARM_t2LDC2_POST: + case ARM_t2LDCL_POST: + case ARM_t2LDC_POST: + + case ARM_t2LDRB_POST: + case ARM_t2LDRD_POST: + case ARM_t2LDRH_POST: + case ARM_t2LDRSB_POST: + case ARM_t2LDRSH_POST: + case ARM_t2LDR_POST: + + case ARM_t2STC2L_POST: + case ARM_t2STC2_POST: + case ARM_t2STCL_POST: + case ARM_t2STC_POST: + + case ARM_t2STRB_POST: + case ARM_t2STRD_POST: + case ARM_t2STRH_POST: + case ARM_t2STR_POST: + insn->detail->arm.writeback = true; + break; + } + } else { // ARM mode + // handle some special instructions with writeback + //printf(">> Opcode = %u\n", mci->Opcode); + switch(mci->Opcode) { + default: + break; + case ARM_LDC2L_PRE: + case ARM_LDC2_PRE: + case ARM_LDCL_PRE: + case ARM_LDC_PRE: + + case ARM_LDRD_PRE: + case ARM_LDRH_PRE: + case ARM_LDRSB_PRE: + case ARM_LDRSH_PRE: + + case ARM_STC2L_PRE: + case ARM_STC2_PRE: + case ARM_STCL_PRE: + case ARM_STC_PRE: + + case ARM_STRD_PRE: + case ARM_STRH_PRE: + + case ARM_LDC2L_POST: + case ARM_LDC2_POST: + case ARM_LDCL_POST: + case ARM_LDC_POST: + + case ARM_LDRBT_POST: + case ARM_LDRD_POST: + case ARM_LDRH_POST: + case ARM_LDRSB_POST: + case ARM_LDRSH_POST: + + case ARM_STC2L_POST: + case ARM_STC2_POST: + case ARM_STCL_POST: + case ARM_STC_POST: + + case ARM_STRBT_POST: + case ARM_STRD_POST: + case ARM_STRH_POST: + + case ARM_LDRB_POST_IMM: + case ARM_LDR_POST_IMM: + case ARM_LDR_POST_REG: + case ARM_STRB_POST_IMM: + + case ARM_STR_POST_IMM: + case ARM_STR_POST_REG: + + insn->detail->arm.writeback = true; + break; + } + } + + // check if this insn requests update flags + if (insn->detail->arm.update_flags == false) { + // some insn still update flags, regardless of tabgen info + unsigned int i, j; + + for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) { + if (insn->id == insn_update_flgs[i].id && + !strncmp(insn_asm, insn_update_flgs[i].name, + strlen(insn_update_flgs[i].name))) { + insn->detail->arm.update_flags = true; + // we have to update regs_write array as well + for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) { + if (insn->detail->regs_write[j] == 0) { + insn->detail->regs_write[j] = ARM_REG_CPSR; + break; + } + } + break; + } + } + } + + // instruction should not have invalid CC + if (insn->detail->arm.cc == ARM_CC_INVALID) { + insn->detail->arm.cc = ARM_CC_AL; + } + + // manual fix for some special instructions + // printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode); + switch(mci->Opcode) { + default: + break; + case ARM_MOVPCLR: + insn->detail->arm.operands[0].type = ARM_OP_REG; + insn->detail->arm.operands[0].reg = ARM_REG_PC; + insn->detail->arm.operands[0].access = CS_AC_WRITE; + insn->detail->arm.operands[1].type = ARM_OP_REG; + insn->detail->arm.operands[1].reg = ARM_REG_LR; + insn->detail->arm.operands[1].access = CS_AC_READ; + insn->detail->arm.op_count = 2; + break; + } +} + +void ARM_printInst(MCInst *MI, SStream *O, void *Info) +{ + MCRegisterInfo *MRI = (MCRegisterInfo *)Info; + unsigned Opcode = MCInst_getOpcode(MI), tmp, i; + + //printf(">>> Opcode = %u\n", Opcode); + switch (Opcode) { + // Check for MOVs and print canonical forms, instead. + case ARM_MOVsr: { + // FIXME: Thumb variants? + unsigned int opc; + MCOperand *Dst = MCInst_getOperand(MI, 0); + MCOperand *MO1 = MCInst_getOperand(MI, 1); + MCOperand *MO2 = MCInst_getOperand(MI, 2); + MCOperand *MO3 = MCInst_getOperand(MI, 3); + + opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); + SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); + + switch (opc) { + default: break; + case ARM_AM_asr: + MCInst_setOpcodePub(MI, ARM_INS_ASR); + break; + case ARM_AM_lsl: + MCInst_setOpcodePub(MI, ARM_INS_LSL); + break; + case ARM_AM_lsr: + MCInst_setOpcodePub(MI, ARM_INS_LSR); + break; + case ARM_AM_ror: + MCInst_setOpcodePub(MI, ARM_INS_ROR); + break; + case ARM_AM_rrx: + MCInst_setOpcodePub(MI, ARM_INS_RRX); + break; + } + + printSBitModifierOperand(MI, 6, O); + printPredicateOperand(MI, 4, O); + + SStream_concat0(O, "\t"); + printRegName(MI->csh, O, MCOperand_getReg(Dst)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + + return; + } + + case ARM_MOVsi: { + // FIXME: Thumb variants? + unsigned int opc; + MCOperand *Dst = MCInst_getOperand(MI, 0); + MCOperand *MO1 = MCInst_getOperand(MI, 1); + MCOperand *MO2 = MCInst_getOperand(MI, 2); + + opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)); + SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); + + switch(opc) { + default: + break; + case ARM_AM_asr: + MCInst_setOpcodePub(MI, ARM_INS_ASR); + break; + case ARM_AM_lsl: + MCInst_setOpcodePub(MI, ARM_INS_LSL); + break; + case ARM_AM_lsr: + MCInst_setOpcodePub(MI, ARM_INS_LSR); + break; + case ARM_AM_ror: + MCInst_setOpcodePub(MI, ARM_INS_ROR); + break; + case ARM_AM_rrx: + MCInst_setOpcodePub(MI, ARM_INS_RRX); + break; + } + + printSBitModifierOperand(MI, 5, O); + printPredicateOperand(MI, 3, O); + + SStream_concat0(O, "\t"); + printRegName(MI->csh, O, MCOperand_getReg(Dst)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + + if (opc == ARM_AM_rrx) { + //printAnnotation(O, Annot); + return; + } + + SStream_concat0(O, ", "); + tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2))); + printUInt32Bang(O, tmp); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = + (arm_shifter)opc; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; + } + + return; + } + + // A8.6.123 PUSH + case ARM_STMDB_UPD: + case ARM_t2STMDB_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && + MCInst_getNumOperands(MI) > 5) { + // Should only print PUSH if there are at least two registers in the list. + SStream_concat0(O, "push"); + MCInst_setOpcodePub(MI, ARM_INS_PUSH); + printPredicateOperand(MI, 2, O); + + if (Opcode == ARM_t2STMDB_UPD) + SStream_concat0(O, ".w"); + + SStream_concat0(O, "\t"); + + if (MI->csh->detail) { + MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_read_count++; + MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_write_count++; + } + + printRegisterList(MI, 4, O); + return; + } else + break; + + case ARM_STR_PRE_IMM: + if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) { + SStream_concat0(O, "push"); + MCInst_setOpcodePub(MI, ARM_INS_PUSH); + + printPredicateOperand(MI, 4, O); + + SStream_concat0(O, "\t{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1))); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; +#endif + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1)); +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "}"); + + return; + } else + break; + + // A8.6.122 POP + case ARM_LDMIA_UPD: + case ARM_t2LDMIA_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && + MCInst_getNumOperands(MI) > 5) { + // Should only print POP if there are at least two registers in the list. + SStream_concat0(O, "pop"); + MCInst_setOpcodePub(MI, ARM_INS_POP); + + printPredicateOperand(MI, 2, O); + if (Opcode == ARM_t2LDMIA_UPD) + SStream_concat0(O, ".w"); + + SStream_concat0(O, "\t"); + + // unlike LDM, POP only write to registers, so skip the 1st access code + MI->ac_idx = 1; + if (MI->csh->detail) { + MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_read_count++; + MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_write_count++; + } + + printRegisterList(MI, 4, O); + + return; + } + break; + + case ARM_LDR_POST_IMM: + if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) { + MCOperand *MO2 = MCInst_getOperand(MI, 4); + + if (getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) { + SStream_concat0(O, "pop"); + MCInst_setOpcodePub(MI, ARM_INS_POP); + printPredicateOperand(MI, 5, O); + SStream_concat0(O, "\t{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; + MI->flat_insn->detail->arm.op_count++; + // this instruction implicitly read/write SP register + MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_read_count++; + MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; + MI->flat_insn->detail->regs_write_count++; + } + SStream_concat0(O, "}"); + return; + } + } + break; + + // A8.6.355 VPUSH + case ARM_VSTMSDB_UPD: + case ARM_VSTMDDB_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { + SStream_concat0(O, "vpush"); + MCInst_setOpcodePub(MI, ARM_INS_VPUSH); + printPredicateOperand(MI, 2, O); + SStream_concat0(O, "\t"); + printRegisterList(MI, 4, O); + return; + } + break; + + // A8.6.354 VPOP + case ARM_VLDMSIA_UPD: + case ARM_VLDMDIA_UPD: + if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { + SStream_concat0(O, "vpop"); + MCInst_setOpcodePub(MI, ARM_INS_VPOP); + printPredicateOperand(MI, 2, O); + SStream_concat0(O, "\t"); + printRegisterList(MI, 4, O); + return; + } + break; + + case ARM_tLDMIA: { + bool Writeback = true; + unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0)); + unsigned i; + + for (i = 3; i < MCInst_getNumOperands(MI); ++i) { + if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg) + Writeback = false; + } + + SStream_concat0(O, "ldm"); + MCInst_setOpcodePub(MI, ARM_INS_LDM); + + printPredicateOperand(MI, 1, O); + SStream_concat0(O, "\t"); + printRegName(MI->csh, O, BaseReg); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ | CS_AC_WRITE; + MI->flat_insn->detail->arm.op_count++; + } + + if (Writeback) { + MI->writeback = true; + SStream_concat0(O, "!"); + } + + SStream_concat0(O, ", "); + printRegisterList(MI, 3, O); + return; + } + + // Combine 2 GPRs from disassember into a GPRPair to match with instr def. + // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, + // a single GPRPair reg operand is used in the .td file to replace the two + // GPRs. However, when decoding them, the two GRPs cannot be automatically + // expressed as a GPRPair, so we have to manually merge them. + // FIXME: We would really like to be able to tablegen'erate this. + case ARM_LDREXD: + case ARM_STREXD: + case ARM_LDAEXD: + case ARM_STLEXD: { + const MCRegisterClass *MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID); + bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD; + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0)); + + if (MCRegisterClass_contains(MRC, Reg)) { + MCInst NewMI; + + MCInst_Init(&NewMI); + MCInst_setOpcode(&NewMI, Opcode); + + if (isStore) + MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0)); + + MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0, + MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID))); + + // Copy the rest operands into NewMI. + for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i) + MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i)); + + printInstruction(&NewMI, O); + return; + } + break; + } + + case ARM_TSB: + case ARM_t2TSB: + SStream_concat0(O, "tsb\tcsync"); + MCInst_setOpcodePub(MI, ARM_INS_TSB); + // TODO: add csync to operands[]? + return; + } + + MI->MRI = MRI; + + if (!printAliasInstr(MI, O)) { + printInstruction(MI, O); + } +} + +static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) +{ + int32_t imm; + MCOperand *Op = MCInst_getOperand(MI, OpNo); + + if (MCOperand_isReg(Op)) { + unsigned Reg = MCOperand_getReg(Op); + + printRegName(MI->csh, O, Reg); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg; + else + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg; + } else { +#ifndef CAPSTONE_DIET + uint8_t access; +#endif + + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm.op_count++; + } + } + } else if (MCOperand_isImm(Op)) { + unsigned int opc = MCInst_getOpcode(MI); + + imm = (int32_t)MCOperand_getImm(Op); + + // relative branch only has relative offset, so we have to update it + // to reflect absolute address. + // Note: in ARM, PC is always 2 instructions ahead, so we have to + // add 8 in ARM mode, or 4 in Thumb mode + // printf(">> opcode: %u\n", MCInst_getOpcode(MI)); + if (ARM_rel_branch(MI->csh, opc)) { + uint32_t address; + + // only do this for relative branch + if (MI->csh->mode & CS_MODE_THUMB) { + address = (uint32_t)MI->address + 4; + if (ARM_blx_to_arm_mode(MI->csh, opc)) { + // here need to align down to the nearest 4-byte address +#define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width) + address = _ALIGN_DOWN(address, 4); +#undef _ALIGN_DOWN + } + } else { + address = (uint32_t)MI->address + 8; + } + + imm += address; + printUInt32Bang(O, imm); + } else { + switch(MI->flat_insn->id) { + default: + if (MI->csh->imm_unsigned) + printUInt32Bang(O, imm); + else + printInt32Bang(O, imm); + break; + case ARM_INS_AND: + case ARM_INS_ORR: + case ARM_INS_EOR: + case ARM_INS_BIC: + case ARM_INS_MVN: + // do not print number in negative form + printUInt32Bang(O, imm); + break; + } + } + + if (MI->csh->detail) { + if (MI->csh->doing_mem) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm; + else { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; + MI->flat_insn->detail->arm.op_count++; + } + } + } +} + +static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + int32_t OffImm; + bool isSub; + SStream_concat0(O, "[pc, "); + + OffImm = (int32_t)MCOperand_getImm(MO1); + isSub = OffImm < 0; + + // Special value for #-0. All others are normal. + if (OffImm == INT32_MIN) + OffImm = 0; + + if (isSub) { + SStream_concat(O, "#-0x%x", -OffImm); + } else { + printUInt32Bang(O, OffImm); + } + + SStream_concat0(O, "]"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } +} + +// so_reg is a 4-operand unit corresponding to register forms of the A5.1 +// "Addressing Mode 1 - Data-processing operands" forms. This includes: +// REG 0 0 - e.g. R5 +// REG REG 0,SH_OPC - e.g. R5, ROR R3 +// REG 0 IMM,SH_OPC - e.g. R5, LSL #3 +static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + MCOperand *MO3 = MCInst_getOperand(MI, OpNum + 2); + ARM_AM_ShiftOpc ShOpc; + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1; + MI->flat_insn->detail->arm.op_count++; + } + + // Print the shift opc. + ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); + SStream_concat0(O, ", "); + SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); + if (ShOpc == ARM_AM_rrx) + return; + + SStream_concat0(O, " "); + + printRegName(MI->csh, O, MCOperand_getReg(MO2)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2); +} + +static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + + // Print the shift opc. + printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), + getSORegOffset((unsigned int)MCOperand_getImm(MO2))); +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #2 +//===--------------------------------------------------------------------===// + +static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); + MCOperand *MO3 = MCInst_getOperand(MI, Op + 2); + unsigned int imm3 = (unsigned int)MCOperand_getImm(MO3); + ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3)); + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + } + + if (!MCOperand_getReg(MO2)) { + unsigned tmp = getAM2Offset(imm3); + if (tmp) { // Don't print +0. + subtracted = getAM2Op(imm3); + + SStream_concat0(O, ", "); + if (tmp > HEX_THRESHOLD) + SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp); + else + SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op(imm3); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; + } + } + + SStream_concat0(O, "]"); + set_mem_access(MI, false); + + return; + } + + SStream_concat0(O, ", "); + SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; + } + + printRegImmShift(MI, O, getAM2ShiftOpc(imm3), getAM2Offset(imm3)); + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); + + SStream_concat0(O, ", lsl #1]"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = 1; + } + + set_mem_access(MI, false); +} + +static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, Op); + + if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, Op, O); + return; + } + +//#ifndef NDEBUG +// const MCOperand &MO3 = MI->getOperand(Op + 2); +// unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); +// assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op"); +//#endif + + printAM2PreOrOffsetIndexOp(MI, Op, O); +} + +static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2)); + + if (!MCOperand_getReg(MO1)) { + unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2)); + if (ImmOffs > HEX_THRESHOLD) + SStream_concat(O, "#%s0x%x", + ARM_AM_getAddrOpcStr(subtracted), ImmOffs); + else + SStream_concat(O, "#%s%u", + ARM_AM_getAddrOpcStr(subtracted), ImmOffs); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; + MI->flat_insn->detail->arm.op_count++; + } + return; + } + + SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; + MI->flat_insn->detail->arm.op_count++; + } + + printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)), + getAM2Offset((unsigned int)MCOperand_getImm(MO2))); +} + +//===--------------------------------------------------------------------===// +// Addressing Mode #3 +//===--------------------------------------------------------------------===// + +static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, + bool AlwaysPrintImm0) +{ + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op+1); + MCOperand *MO3 = MCInst_getOperand(MI, Op+2); + ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3)); + unsigned ImmOffs; + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + if (MCOperand_getReg(MO2)) { + SStream_concat0(O, ", "); + SStream_concat0(O, ARM_AM_getAddrOpcStr(sign)); + + printRegName(MI->csh, O, MCOperand_getReg(MO2)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); + if (sign == ARM_AM_sub) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; + } + } + + SStream_concat0(O, "]"); + set_mem_access(MI, false); + + return; + } + + // If the op is sub we have to print the immediate even if it is 0 + ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3)); + + if (AlwaysPrintImm0 || ImmOffs || (sign == ARM_AM_sub)) { + if (ImmOffs > HEX_THRESHOLD) + SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs); + else + SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs); + } + + if (MI->csh->detail) { + if (sign == ARM_AM_sub) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; + } else + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs; + } + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O, + bool AlwaysPrintImm0) +{ + MCOperand *MO1 = MCInst_getOperand(MI, Op); + + if (!MCOperand_isReg(MO1)) { // For label symbolic references. + printOperand(MI, Op, O); + return; + } + + printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); +} + +static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2)); + unsigned ImmOffs; + + if (MCOperand_getReg(MO1)) { + SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; + MI->flat_insn->detail->arm.op_count++; + } + + return; + } + + ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2)); + if (ImmOffs > HEX_THRESHOLD) + SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); + else + SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, OpNum); + unsigned Imm = (unsigned int)MCOperand_getImm(MO); + + if ((Imm & 0xff) > HEX_THRESHOLD) + SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); + else + SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + + SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-")); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, OpNum); + int Imm = (int)MCOperand_getImm(MO); + + if (((Imm & 0xff) << 2) > HEX_THRESHOLD) { + SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); + } else { + SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); + } + + if (MI->csh->detail) { + int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((Imm & 0xff) << 2); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool AlwaysPrintImm0) +{ + unsigned ImmOffs; + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + ARM_AM_AddrOpc Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2)); + + if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, OpNum, O); + return; + } + + SStream_concat0(O, "["); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + } + + ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2)); + if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) { + if (ImmOffs * 4 > HEX_THRESHOLD) + SStream_concat(O, ", #%s0x%x", + ARM_AM_getAddrOpcStr(Op), + ImmOffs * 4); + else + SStream_concat(O, ", #%s%u", + ARM_AM_getAddrOpcStr(Op), + ImmOffs * 4); + + if (MI->csh->detail) { + if (Op) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4; + else + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4; + } + } + + SStream_concat0(O, "]"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool AlwaysPrintImm0) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + unsigned ImmOffs = getAM5FP16Offset((unsigned)MCOperand_getImm(MO2)); + unsigned Op = getAM5FP16Op((unsigned)MCOperand_getImm(MO2)); + + if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, OpNum, O); + return; + } + + SStream_concat0(O, "["); + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + } + + if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) { + if (ImmOffs * 2 > HEX_THRESHOLD) + SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2); + else + SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2); + + if (MI->csh->detail) { + if (Op) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 2; + else + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 2; + } + } + + SStream_concat0(O, "]"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + unsigned tmp; + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + tmp = (unsigned int)MCOperand_getImm(MO2); + if (tmp) { + if (tmp << 3 > HEX_THRESHOLD) + SStream_concat(O, ":0x%x", (tmp << 3)); + else + SStream_concat(O, ":%u", (tmp << 3)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3; + } + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, OpNum); + + if (MCOperand_getReg(MO) == 0) { + MI->writeback = true; + SStream_concat0(O, "!"); + } else { + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO); + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + } +} + +static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, OpNum); + uint32_t v = ~(uint32_t)MCOperand_getImm(MO); + int32_t lsb = CountTrailingZeros_32(v); + int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; + + //assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); + printUInt32Bang(O, lsb); + + if (width > HEX_THRESHOLD) + SStream_concat(O, ", #0x%x", width); + else + SStream_concat(O, ", #%u", width); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb; + MI->flat_insn->detail->arm.op_count++; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, ARM_MB_MemBOptToString(val, + ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1); + } +} + +static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val)); +} + +static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, ARM_TSB_TraceSyncBOptToString(val)); + // TODO: add to detail? +} + +static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + bool isASR = (ShiftOp & (1 << 5)) != 0; + unsigned Amt = ShiftOp & 0x1f; + + if (isASR) { + unsigned tmp = Amt == 0 ? 32 : Amt; + if (tmp > HEX_THRESHOLD) + SStream_concat(O, ", asr #0x%x", tmp); + else + SStream_concat(O, ", asr #%u", tmp); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; + } + } else if (Amt) { + if (Amt > HEX_THRESHOLD) + SStream_concat(O, ", lsl #0x%x", Amt); + else + SStream_concat(O, ", lsl #%u", Amt); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt; + } + } +} + +static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + if (Imm == 0) + return; + + //assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); + if (Imm > HEX_THRESHOLD) + SStream_concat(O, ", lsl #0x%x", Imm); + else + SStream_concat(O, ", lsl #%u", Imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; + } +} + +static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + // A shift amount of 32 is encoded as 0. + if (Imm == 0) + Imm = 32; + + //assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); + if (Imm > HEX_THRESHOLD) + SStream_concat(O, ", asr #0x%x", Imm); + else + SStream_concat(O, ", asr #%u", Imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; + } +} + +// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct +static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned i, e; +#ifndef CAPSTONE_DIET + uint8_t access = 0; +#endif + + SStream_concat0(O, "{"); + +#ifndef CAPSTONE_DIET + if (MI->csh->detail) { + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + } +#endif + + for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) { + if (i != OpNum) + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + } + + SStream_concat0(O, "}"); + +#ifndef CAPSTONE_DIET + if (MI->csh->detail) { + MI->ac_idx++; + } +#endif +} + +static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + + printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0); + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1); + MI->flat_insn->detail->arm.op_count++; + } +} + +// SETEND BE/LE +static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNum); + + if (MCOperand_getImm(Op)) { + SStream_concat0(O, "be"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE; + MI->flat_insn->detail->arm.op_count++; + } + } else { + SStream_concat0(O, "le"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE; + MI->flat_insn->detail->arm.op_count++; + } + } +} + +static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned int mode = (unsigned int)MCOperand_getImm(Op); + + SStream_concat0(O, ARM_PROC_IModToString(mode)); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.cps_mode = mode; + } +} + +static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned IFlags = (unsigned int)MCOperand_getImm(Op); + int i; + + for (i = 2; i >= 0; --i) + if (IFlags & (1 << i)) { + SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i)); + } + + if (IFlags == 0) { + SStream_concat0(O, "none"); + IFlags = ARM_CPSFLAG_NONE; + } + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.cps_flag = IFlags; + } +} + +static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4; + unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf; + unsigned reg; + + if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) { + const MClassSysReg *TheReg; + unsigned SYSm = (unsigned)MCOperand_getImm(Op) & 0xFFF; // 12-bit SYMm + unsigned Opcode = MCInst_getOpcode(MI); + + if (Opcode == ARM_t2MSR_M && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)) { + TheReg = lookupMClassSysRegBy12bitSYSmValue(SYSm); + if (TheReg && MClassSysReg_isInRequiredFeatures(TheReg, ARM_FeatureDSP)) { + SStream_concat0(O, TheReg->Name); + ARM_addSysReg(MI, TheReg->sysreg); + return; + } + } + + // Handle the basic 8-bit mask. + SYSm &= 0xff; + if (Opcode == ARM_t2MSR_M && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)) { + // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an + // alias for MSR APSR_nzcvq. + TheReg = lookupMClassSysRegAPSRNonDeprecated(SYSm); + if (TheReg) { + SStream_concat0(O, TheReg->Name); + ARM_addSysReg(MI, TheReg->sysreg); + return; + } + } + + TheReg = lookupMClassSysRegBy8bitSYSmValue(SYSm); + if (TheReg) { + SStream_concat0(O, TheReg->Name); + ARM_addSysReg(MI, TheReg->sysreg); + return; + } + + if (SYSm > HEX_THRESHOLD) + SStream_concat(O, "%x", SYSm); + else + SStream_concat(O, "%u", SYSm); + + if (MI->csh->detail) + MCOperand_CreateImm0(MI, SYSm); + + return; + } + + // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as + // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. + if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { + SStream_concat0(O, "apsr_"); + switch (Mask) { + default: // llvm_unreachable("Unexpected mask value!"); + case 4: SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return; + case 8: SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return; + case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return; + } + } + + if (SpecRegRBit) { + SStream_concat0(O, "spsr"); + } else { + SStream_concat0(O, "cpsr"); + } + + reg = 0; + if (Mask) { + SStream_concat0(O, "_"); + + if (Mask & 8) { + SStream_concat0(O, "f"); + reg += ARM_SYSREG_SPSR_F; + } + + if (Mask & 4) { + SStream_concat0(O, "s"); + reg += ARM_SYSREG_SPSR_S; + } + + if (Mask & 2) { + SStream_concat0(O, "x"); + reg += ARM_SYSREG_SPSR_X; + } + + if (Mask & 1) { + SStream_concat0(O, "c"); + reg += ARM_SYSREG_SPSR_C; + } + + ARM_addSysReg(MI, reg); + } +} + +static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + const BankedReg *TheReg = lookupBankedRegByEncoding(Banked); + + SStream_concat0(O, TheReg->Name); + ARM_addSysReg(MI, TheReg->sysreg); +} + +static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + // Handle the undefined 15 CC value here for printing so we don't abort(). + if ((unsigned)CC == 15) { + SStream_concat0(O, "<und>"); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.cc = ARM_CC_INVALID; + } else { + if (CC != ARMCC_AL) { + SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); + } + + if (MI->csh->detail) + MI->flat_insn->detail->arm.cc = CC + 1; + } +} + +static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.cc = CC + 1; +} + +static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) { + //assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR && + // "Expect ARM CPSR register!"); + SStream_concat0(O, "s"); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.update_flags = true; + } +} + +static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + printUInt32(O, tmp); + + if (MI->csh->detail) { + if (MI->csh->doing_mem) { + MI->flat_insn->detail->arm.op_count--; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = (int8_t)tmp; + MI->ac_idx--; // consecutive operands share the same access right + } else { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } + } +} + +static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + SStream_concat(O, "p%u", imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + SStream_concat(O, "c%u", imm); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + if (tmp > HEX_THRESHOLD) + SStream_concat(O, "{0x%x}", tmp); + else + SStream_concat(O, "{%u}", tmp); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned scale) +{ + MCOperand *MO = MCInst_getOperand(MI, OpNum); + + int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale; + + if (OffImm == INT32_MIN) { + SStream_concat0(O, "#-0"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; + MI->flat_insn->detail->arm.op_count++; + } + } else { + if (OffImm < 0) + SStream_concat(O, "#-0x%x", -OffImm); + else { + if (OffImm > HEX_THRESHOLD) + SStream_concat(O, "#0x%x", OffImm); + else + SStream_concat(O, "#%u", OffImm); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; + MI->flat_insn->detail->arm.op_count++; + } + } +} + +static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4; + + printUInt32Bang(O, tmp); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned tmp = Imm == 0 ? 32 : Imm; + + printUInt32Bang(O, tmp); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O) +{ + // (3 - the number of trailing zeros) is the number of then / else. + unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum - 1)); + unsigned CondBit0 = Firstcond & 1; + unsigned NumTZ = CountTrailingZeros_32(Mask); + //assert(NumTZ <= 3 && "Invalid IT mask!"); + unsigned Pos, e; + + for (Pos = 3, e = NumTZ; Pos > e; --Pos) { + bool T = ((Mask >> Pos) & 1) == CondBit0; + if (T) + SStream_concat0(O, "t"); + else + SStream_concat0(O, "e"); + // TODO: detail for this t/e + } +} + +static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); + unsigned RegNum; + + if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, Op, O); + return; + } + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + RegNum = MCOperand_getReg(MO2); + if (RegNum) { + SStream_concat0(O, ", "); + printRegName(MI->csh, O, RegNum); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum; + } + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O, + unsigned Scale) +{ + MCOperand *MO1 = MCInst_getOperand(MI, Op); + MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); + unsigned ImmOffs, tmp; + + if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, Op, O); + return; + } + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + ImmOffs = (unsigned int)MCOperand_getImm(MO2); + if (ImmOffs) { + tmp = ImmOffs * Scale; + SStream_concat0(O, ", "); + printUInt32Bang(O, tmp); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; + } + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O) +{ + printThumbAddrModeImm5SOperand(MI, Op, O, 1); +} + +static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O) +{ + printThumbAddrModeImm5SOperand(MI, Op, O, 2); +} + +static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O) +{ + printThumbAddrModeImm5SOperand(MI, Op, O, 4); +} + +static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O) +{ + printThumbAddrModeImm5SOperand(MI, Op, O, 4); +} + +// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 +// register with shift forms. +// REG 0 0 - e.g. R5 +// REG IMM, SH_OPC - e.g. R5, LSL #3 +static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + unsigned Reg = MCOperand_getReg(MO1); + + printRegName(MI->csh, O, Reg); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; + MI->flat_insn->detail->arm.op_count++; + } + + // Print the shift opc. + //assert(MO2.isImm() && "Not a valid t2_so_reg value!"); + printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), + getSORegOffset((unsigned int)MCOperand_getImm(MO2))); +} + +static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, + SStream *O, bool AlwaysPrintImm0) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); + int32_t OffImm; + bool isSub; + + if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. + printOperand(MI, OpNum, O); + return; + } + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + OffImm = (int32_t)MCOperand_getImm(MO2); + isSub = OffImm < 0; + + // Special value for #-0. All others are normal. + if (OffImm == INT32_MIN) + OffImm = 0; + + if (isSub) { + if (OffImm < -HEX_THRESHOLD) + SStream_concat(O, ", #-0x%x", -OffImm); + else + SStream_concat(O, ", #-%u", -OffImm); + } else if (AlwaysPrintImm0 || OffImm > 0) { + if (OffImm >= 0) { + if (OffImm > HEX_THRESHOLD) + SStream_concat(O, ", #0x%x", OffImm); + else + SStream_concat(O, ", #%u", OffImm); + } else { + if (OffImm < -HEX_THRESHOLD) + SStream_concat(O, ", #-0x%x", -OffImm); + else + SStream_concat(O, ", #-%u", -OffImm); + } + } + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, + bool AlwaysPrintImm0) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); + int32_t OffImm; + bool isSub; + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + OffImm = (int32_t)MCOperand_getImm(MO2); + isSub = OffImm < 0; + + // Don't print +0. + if (OffImm == INT32_MIN) + OffImm = 0; + + if (isSub) + SStream_concat(O, ", #-0x%x", -OffImm); + else if (AlwaysPrintImm0 || OffImm > 0) { + if (OffImm > HEX_THRESHOLD) + SStream_concat(O, ", #0x%x", OffImm); + else + SStream_concat(O, ", #%u", OffImm); + } + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printT2AddrModeImm8s4Operand(MCInst *MI, + unsigned OpNum, SStream *O, bool AlwaysPrintImm0) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + int32_t OffImm; + bool isSub; + + if (!MCOperand_isReg(MO1)) { // For label symbolic references. + printOperand(MI, OpNum, O); + return; + } + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + OffImm = (int32_t)MCOperand_getImm(MO2); + isSub = OffImm < 0; + + //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); + + // Don't print +0. + if (OffImm == INT32_MIN) + OffImm = 0; + + if (isSub) { + SStream_concat(O, ", #-0x%x", -OffImm); + } else if (AlwaysPrintImm0 || OffImm > 0) { + if (OffImm > HEX_THRESHOLD) + SStream_concat(O, ", #0x%x", OffImm); + else + SStream_concat(O, ", #%u", OffImm); + } + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); + unsigned tmp; + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + if (MCOperand_getImm(MO2)) { + SStream_concat0(O, ", "); + tmp = (unsigned int)MCOperand_getImm(MO2) * 4; + printUInt32Bang(O, tmp); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; + } + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printT2AddrModeImm8OffsetOperand(MCInst *MI, + unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + int32_t OffImm = (int32_t)MCOperand_getImm(MO1); + + SStream_concat0(O, ", "); + if (OffImm == INT32_MIN) { + SStream_concat0(O, "#-0"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; + MI->flat_insn->detail->arm.op_count++; + } + } else { + printInt32Bang(O, OffImm); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; + MI->flat_insn->detail->arm.op_count++; + } + } +} + +static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, + unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + int32_t OffImm = (int32_t)MCOperand_getImm(MO1); + + //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); + + SStream_concat0(O, ", "); + + if (OffImm == INT32_MIN) { + SStream_concat0(O, "#-0"); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; + MI->flat_insn->detail->arm.op_count++; + } + } else { + printInt32Bang(O, OffImm); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; + MI->flat_insn->detail->arm.op_count++; + } + } +} + +static void printT2AddrModeSoRegOperand(MCInst *MI, + unsigned OpNum, SStream *O) +{ + MCOperand *MO1 = MCInst_getOperand(MI, OpNum); + MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); + MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2); + unsigned ShAmt; + + SStream_concat0(O, "["); + set_mem_access(MI, true); + + printRegName(MI->csh, O, MCOperand_getReg(MO1)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); + + //assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!"); + SStream_concat0(O, ", "); + printRegName(MI->csh, O, MCOperand_getReg(MO2)); + + if (MI->csh->detail) + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); + + ShAmt = (unsigned int)MCOperand_getImm(MO3); + if (ShAmt) { + //assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); + SStream_concat0(O, ", lsl "); + SStream_concat(O, "#%u", ShAmt); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = ShAmt; + } + } + + SStream_concat0(O, "]"); + set_mem_access(MI, false); +} + +static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *MO = MCInst_getOperand(MI, OpNum); + +#if defined(_KERNEL_MODE) + // Issue #681: Windows kernel does not support formatting float point + SStream_concat(O, "#<float_point_unsupported>"); +#else + SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO))); +#endif + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO)); + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned EltBits; + uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits); + + if (Val > HEX_THRESHOLD) + SStream_concat(O, "#0x%"PRIx64, Val); + else + SStream_concat(O, "#%"PRIu64, Val); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + printUInt32Bang(O, Imm + 1); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + if (Imm == 0) + return; + + SStream_concat0(O, ", ror #"); + + switch (Imm) { + default: //assert (0 && "illegal ror immediate!"); + case 1: SStream_concat0(O, "8"); break; + case 2: SStream_concat0(O, "16"); break; + case 3: SStream_concat0(O, "24"); break; + } + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8; + } +} + +static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) +{ + MCOperand *Op = MCInst_getOperand(MI, OpNum); + unsigned Bits = MCOperand_getImm(Op) & 0xFF; + unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7; + int32_t Rotated; + bool PrintUnsigned = false; + + switch (MCInst_getOpcode(MI)) { + case ARM_MOVi: + // Movs to PC should be treated unsigned + PrintUnsigned = (MCOperand_getReg(MCInst_getOperand(MI, OpNum - 1)) == ARM_PC); + break; + case ARM_MSRi: + // Movs to special registers should be treated unsigned + PrintUnsigned = true; + break; + } + + Rotated = rotr32(Bits, Rot); + if (getSOImmVal(Rotated) == MCOperand_getImm(Op)) { + // #rot has the least possible value + if (PrintUnsigned) { + if (Rotated > HEX_THRESHOLD || Rotated < -HEX_THRESHOLD) + SStream_concat(O, "#0x%x", Rotated); + else + SStream_concat(O, "#%u", Rotated); + } else if (Rotated >= 0) { + if (Rotated > HEX_THRESHOLD) + SStream_concat(O, "#0x%x", Rotated); + else + SStream_concat(O, "#%u", Rotated); + } else { + SStream_concat(O, "#0x%x", Rotated); + } + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rotated; + MI->flat_insn->detail->arm.op_count++; + } + + return; + } + + // Explicit #bits, #rot implied + SStream_concat(O, "#%u, #%u", Bits, Rot); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Bits; + MI->flat_insn->detail->arm.op_count++; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rot; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned tmp; + + tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + printUInt32Bang(O, tmp); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned tmp; + + tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + printUInt32Bang(O, tmp); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } +} + +static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + if (tmp > HEX_THRESHOLD) + SStream_concat(O, "[0x%x]", tmp); + else + SStream_concat(O, "[%u]", tmp); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp; + } +} + +static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O) +{ + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif + } + + SStream_concat0(O, "}"); +} + +static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; +#endif + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); + +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, Reg0); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, Reg1); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; +#endif + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); + +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, Reg0); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, Reg1); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D<n>. + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D<n>. + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[]}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; +#endif + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); + +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, Reg0); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, Reg1); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[]}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D<n>. + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[]}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D<n>. + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[]}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; +#endif + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); + unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); + +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, Reg0); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, Reg1); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[]}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListThreeSpacedAllLanes(MCInst *MI, + unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D<n>. + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[]}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListFourSpacedAllLanes(MCInst *MI, + unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D<n>. + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[], "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "[]}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D<n>. + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O) +{ +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); +#endif + + // Normally, it's not safe to use register enum values directly with + // addition to get the next register, but for VFP registers, the + // sort order is guaranteed because they're all of the form D<n>. + SStream_concat0(O, "{"); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, ", "); + + printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); + + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; +#ifndef CAPSTONE_DIET + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; +#endif + MI->flat_insn->detail->arm.op_count++; + } + + SStream_concat0(O, "}"); + +#ifndef CAPSTONE_DIET + MI->ac_idx++; +#endif +} + +static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, int64_t Angle, int64_t Remainder) +{ + unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); + unsigned tmp = (unsigned)((Val * Angle) + Remainder); + + printUInt32Bang(O, tmp); + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; + MI->flat_insn->detail->arm.op_count++; + } +} + +void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm.vector_data = vd; + } +} + +void ARM_addVectorDataSize(MCInst *MI, int size) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm.vector_size = size; + } +} + +void ARM_addReg(MCInst *MI, int reg) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; + MI->flat_insn->detail->arm.op_count++; + } +} + +void ARM_addUserMode(MCInst *MI) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm.usermode = true; + } +} + +void ARM_addSysReg(MCInst *MI, arm_sysreg reg) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG; + MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; + MI->flat_insn->detail->arm.op_count++; + } +} + +#endif diff --git a/capstone/arch/ARM/ARMInstPrinter.h b/capstone/arch/ARM/ARMInstPrinter.h new file mode 100644 index 000000000..4332d1a91 --- /dev/null +++ b/capstone/arch/ARM/ARMInstPrinter.h @@ -0,0 +1,43 @@ +//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an ARM MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +#ifndef CS_ARMINSTPRINTER_H +#define CS_ARMINSTPRINTER_H + +#include "../../MCInst.h" +#include "../../MCRegisterInfo.h" +#include "../../SStream.h" + +void ARM_printInst(MCInst *MI, SStream *O, void *Info); +void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem, MCInst *mci); + +// setup handle->get_regname +void ARM_getRegName(cs_struct *handle, int value); + +// specify vector data type for vector instructions +void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd); + +void ARM_addVectorDataSize(MCInst *MI, int size); + +void ARM_addReg(MCInst *MI, int reg); + +// load usermode registers (LDM, STM) +void ARM_addUserMode(MCInst *MI); + +// sysreg for MRS/MSR +void ARM_addSysReg(MCInst *MI, arm_sysreg reg); + +#endif diff --git a/capstone/arch/ARM/ARMMapping.c b/capstone/arch/ARM/ARMMapping.c new file mode 100644 index 000000000..a8d8698c0 --- /dev/null +++ b/capstone/arch/ARM/ARMMapping.c @@ -0,0 +1,551 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +#ifdef CAPSTONE_HAS_ARM + +#include <stdio.h> // debug +#include <string.h> + +#include "../../cs_priv.h" + +#include "ARMMapping.h" + +#define GET_INSTRINFO_ENUM +#include "ARMGenInstrInfo.inc" + +#ifndef CAPSTONE_DIET +static const name_map reg_name_maps[] = { + { ARM_REG_INVALID, NULL }, + { ARM_REG_APSR, "apsr"}, + { ARM_REG_APSR_NZCV, "apsr_nzcv"}, + { ARM_REG_CPSR, "cpsr"}, + { ARM_REG_FPEXC, "fpexc"}, + { ARM_REG_FPINST, "fpinst"}, + { ARM_REG_FPSCR, "fpscr"}, + { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"}, + { ARM_REG_FPSID, "fpsid"}, + { ARM_REG_ITSTATE, "itstate"}, + { ARM_REG_LR, "lr"}, + { ARM_REG_PC, "pc"}, + { ARM_REG_SP, "sp"}, + { ARM_REG_SPSR, "spsr"}, + { ARM_REG_D0, "d0"}, + { ARM_REG_D1, "d1"}, + { ARM_REG_D2, "d2"}, + { ARM_REG_D3, "d3"}, + { ARM_REG_D4, "d4"}, + { ARM_REG_D5, "d5"}, + { ARM_REG_D6, "d6"}, + { ARM_REG_D7, "d7"}, + { ARM_REG_D8, "d8"}, + { ARM_REG_D9, "d9"}, + { ARM_REG_D10, "d10"}, + { ARM_REG_D11, "d11"}, + { ARM_REG_D12, "d12"}, + { ARM_REG_D13, "d13"}, + { ARM_REG_D14, "d14"}, + { ARM_REG_D15, "d15"}, + { ARM_REG_D16, "d16"}, + { ARM_REG_D17, "d17"}, + { ARM_REG_D18, "d18"}, + { ARM_REG_D19, "d19"}, + { ARM_REG_D20, "d20"}, + { ARM_REG_D21, "d21"}, + { ARM_REG_D22, "d22"}, + { ARM_REG_D23, "d23"}, + { ARM_REG_D24, "d24"}, + { ARM_REG_D25, "d25"}, + { ARM_REG_D26, "d26"}, + { ARM_REG_D27, "d27"}, + { ARM_REG_D28, "d28"}, + { ARM_REG_D29, "d29"}, + { ARM_REG_D30, "d30"}, + { ARM_REG_D31, "d31"}, + { ARM_REG_FPINST2, "fpinst2"}, + { ARM_REG_MVFR0, "mvfr0"}, + { ARM_REG_MVFR1, "mvfr1"}, + { ARM_REG_MVFR2, "mvfr2"}, + { ARM_REG_Q0, "q0"}, + { ARM_REG_Q1, "q1"}, + { ARM_REG_Q2, "q2"}, + { ARM_REG_Q3, "q3"}, + { ARM_REG_Q4, "q4"}, + { ARM_REG_Q5, "q5"}, + { ARM_REG_Q6, "q6"}, + { ARM_REG_Q7, "q7"}, + { ARM_REG_Q8, "q8"}, + { ARM_REG_Q9, "q9"}, + { ARM_REG_Q10, "q10"}, + { ARM_REG_Q11, "q11"}, + { ARM_REG_Q12, "q12"}, + { ARM_REG_Q13, "q13"}, + { ARM_REG_Q14, "q14"}, + { ARM_REG_Q15, "q15"}, + { ARM_REG_R0, "r0"}, + { ARM_REG_R1, "r1"}, + { ARM_REG_R2, "r2"}, + { ARM_REG_R3, "r3"}, + { ARM_REG_R4, "r4"}, + { ARM_REG_R5, "r5"}, + { ARM_REG_R6, "r6"}, + { ARM_REG_R7, "r7"}, + { ARM_REG_R8, "r8"}, + { ARM_REG_R9, "sb"}, + { ARM_REG_R10, "sl"}, + { ARM_REG_R11, "fp"}, + { ARM_REG_R12, "ip"}, + { ARM_REG_S0, "s0"}, + { ARM_REG_S1, "s1"}, + { ARM_REG_S2, "s2"}, + { ARM_REG_S3, "s3"}, + { ARM_REG_S4, "s4"}, + { ARM_REG_S5, "s5"}, + { ARM_REG_S6, "s6"}, + { ARM_REG_S7, "s7"}, + { ARM_REG_S8, "s8"}, + { ARM_REG_S9, "s9"}, + { ARM_REG_S10, "s10"}, + { ARM_REG_S11, "s11"}, + { ARM_REG_S12, "s12"}, + { ARM_REG_S13, "s13"}, + { ARM_REG_S14, "s14"}, + { ARM_REG_S15, "s15"}, + { ARM_REG_S16, "s16"}, + { ARM_REG_S17, "s17"}, + { ARM_REG_S18, "s18"}, + { ARM_REG_S19, "s19"}, + { ARM_REG_S20, "s20"}, + { ARM_REG_S21, "s21"}, + { ARM_REG_S22, "s22"}, + { ARM_REG_S23, "s23"}, + { ARM_REG_S24, "s24"}, + { ARM_REG_S25, "s25"}, + { ARM_REG_S26, "s26"}, + { ARM_REG_S27, "s27"}, + { ARM_REG_S28, "s28"}, + { ARM_REG_S29, "s29"}, + { ARM_REG_S30, "s30"}, + { ARM_REG_S31, "s31"}, +}; +static const name_map reg_name_maps2[] = { + { ARM_REG_INVALID, NULL }, + { ARM_REG_APSR, "apsr"}, + { ARM_REG_APSR_NZCV, "apsr_nzcv"}, + { ARM_REG_CPSR, "cpsr"}, + { ARM_REG_FPEXC, "fpexc"}, + { ARM_REG_FPINST, "fpinst"}, + { ARM_REG_FPSCR, "fpscr"}, + { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"}, + { ARM_REG_FPSID, "fpsid"}, + { ARM_REG_ITSTATE, "itstate"}, + { ARM_REG_LR, "lr"}, + { ARM_REG_PC, "pc"}, + { ARM_REG_SP, "sp"}, + { ARM_REG_SPSR, "spsr"}, + { ARM_REG_D0, "d0"}, + { ARM_REG_D1, "d1"}, + { ARM_REG_D2, "d2"}, + { ARM_REG_D3, "d3"}, + { ARM_REG_D4, "d4"}, + { ARM_REG_D5, "d5"}, + { ARM_REG_D6, "d6"}, + { ARM_REG_D7, "d7"}, + { ARM_REG_D8, "d8"}, + { ARM_REG_D9, "d9"}, + { ARM_REG_D10, "d10"}, + { ARM_REG_D11, "d11"}, + { ARM_REG_D12, "d12"}, + { ARM_REG_D13, "d13"}, + { ARM_REG_D14, "d14"}, + { ARM_REG_D15, "d15"}, + { ARM_REG_D16, "d16"}, + { ARM_REG_D17, "d17"}, + { ARM_REG_D18, "d18"}, + { ARM_REG_D19, "d19"}, + { ARM_REG_D20, "d20"}, + { ARM_REG_D21, "d21"}, + { ARM_REG_D22, "d22"}, + { ARM_REG_D23, "d23"}, + { ARM_REG_D24, "d24"}, + { ARM_REG_D25, "d25"}, + { ARM_REG_D26, "d26"}, + { ARM_REG_D27, "d27"}, + { ARM_REG_D28, "d28"}, + { ARM_REG_D29, "d29"}, + { ARM_REG_D30, "d30"}, + { ARM_REG_D31, "d31"}, + { ARM_REG_FPINST2, "fpinst2"}, + { ARM_REG_MVFR0, "mvfr0"}, + { ARM_REG_MVFR1, "mvfr1"}, + { ARM_REG_MVFR2, "mvfr2"}, + { ARM_REG_Q0, "q0"}, + { ARM_REG_Q1, "q1"}, + { ARM_REG_Q2, "q2"}, + { ARM_REG_Q3, "q3"}, + { ARM_REG_Q4, "q4"}, + { ARM_REG_Q5, "q5"}, + { ARM_REG_Q6, "q6"}, + { ARM_REG_Q7, "q7"}, + { ARM_REG_Q8, "q8"}, + { ARM_REG_Q9, "q9"}, + { ARM_REG_Q10, "q10"}, + { ARM_REG_Q11, "q11"}, + { ARM_REG_Q12, "q12"}, + { ARM_REG_Q13, "q13"}, + { ARM_REG_Q14, "q14"}, + { ARM_REG_Q15, "q15"}, + { ARM_REG_R0, "r0"}, + { ARM_REG_R1, "r1"}, + { ARM_REG_R2, "r2"}, + { ARM_REG_R3, "r3"}, + { ARM_REG_R4, "r4"}, + { ARM_REG_R5, "r5"}, + { ARM_REG_R6, "r6"}, + { ARM_REG_R7, "r7"}, + { ARM_REG_R8, "r8"}, + { ARM_REG_R9, "r9"}, + { ARM_REG_R10, "r10"}, + { ARM_REG_R11, "r11"}, + { ARM_REG_R12, "r12"}, + { ARM_REG_S0, "s0"}, + { ARM_REG_S1, "s1"}, + { ARM_REG_S2, "s2"}, + { ARM_REG_S3, "s3"}, + { ARM_REG_S4, "s4"}, + { ARM_REG_S5, "s5"}, + { ARM_REG_S6, "s6"}, + { ARM_REG_S7, "s7"}, + { ARM_REG_S8, "s8"}, + { ARM_REG_S9, "s9"}, + { ARM_REG_S10, "s10"}, + { ARM_REG_S11, "s11"}, + { ARM_REG_S12, "s12"}, + { ARM_REG_S13, "s13"}, + { ARM_REG_S14, "s14"}, + { ARM_REG_S15, "s15"}, + { ARM_REG_S16, "s16"}, + { ARM_REG_S17, "s17"}, + { ARM_REG_S18, "s18"}, + { ARM_REG_S19, "s19"}, + { ARM_REG_S20, "s20"}, + { ARM_REG_S21, "s21"}, + { ARM_REG_S22, "s22"}, + { ARM_REG_S23, "s23"}, + { ARM_REG_S24, "s24"}, + { ARM_REG_S25, "s25"}, + { ARM_REG_S26, "s26"}, + { ARM_REG_S27, "s27"}, + { ARM_REG_S28, "s28"}, + { ARM_REG_S29, "s29"}, + { ARM_REG_S30, "s30"}, + { ARM_REG_S31, "s31"}, +}; +#endif + +const char *ARM_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= ARR_SIZE(reg_name_maps)) + return NULL; + + return reg_name_maps[reg].name; +#else + return NULL; +#endif +} + +const char *ARM_reg_name2(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= ARR_SIZE(reg_name_maps2)) + return NULL; + + return reg_name_maps2[reg].name; +#else + return NULL; +#endif +} + +static const insn_map insns[] = { + // dummy item + { + 0, 0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif + }, +#include "ARMMappingInsn.inc" +}; + +// look for @id in @insns +// return -1 if not found +static unsigned int find_insn(unsigned int id) +{ + // binary searching since the IDs are sorted in order + unsigned int left, right, m; + unsigned int max = ARR_SIZE(insns); + + right = max - 1; + + if (id < insns[0].id || id > insns[right].id) + // not found + return -1; + + left = 0; + + while(left <= right) { + m = (left + right) / 2; + if (id == insns[m].id) { + return m; + } + + if (id < insns[m].id) + right = m - 1; + else + left = m + 1; + } + + // not found + // printf("NOT FOUNDDDDDDDDDDDDDDD id = %u\n", id); + return -1; +} + +void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ + unsigned int i = find_insn(id); + if (i != -1) { + insn->id = insns[i].mapid; + + // printf("id = %u, mapid = %u\n", id, insn->id); + + if (h->detail) { +#ifndef CAPSTONE_DIET + cs_struct handle; + handle.detail = h->detail; + + memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); + insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); + + memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); + insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); + + memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); + insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); + + insn->detail->arm.update_flags = cs_reg_write((csh)&handle, insn, ARM_REG_CPSR); + + if (insns[i].branch || insns[i].indirect_branch) { + // this insn also belongs to JUMP group. add JUMP group + insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP; + insn->detail->groups_count++; + } +#endif + } + } +} + +#ifndef CAPSTONE_DIET +static const char * const insn_name_maps[] = { + NULL, // ARM_INS_INVALID +#include "ARMMappingInsnName.inc" +}; +#endif + +const char *ARM_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + if (id >= ARM_INS_ENDING) + return NULL; + + return insn_name_maps[id]; +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + // generic groups + { ARM_GRP_INVALID, NULL }, + { ARM_GRP_JUMP, "jump" }, + { ARM_GRP_CALL, "call" }, + { ARM_GRP_INT, "int" }, + { ARM_GRP_PRIVILEGE, "privilege" }, + { ARM_GRP_BRANCH_RELATIVE, "branch_relative" }, + + // architecture-specific groups + { ARM_GRP_CRYPTO, "crypto" }, + { ARM_GRP_DATABARRIER, "databarrier" }, + { ARM_GRP_DIVIDE, "divide" }, + { ARM_GRP_FPARMV8, "fparmv8" }, + { ARM_GRP_MULTPRO, "multpro" }, + { ARM_GRP_NEON, "neon" }, + { ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK" }, + { ARM_GRP_THUMB2DSP, "THUMB2DSP" }, + { ARM_GRP_TRUSTZONE, "TRUSTZONE" }, + { ARM_GRP_V4T, "v4t" }, + { ARM_GRP_V5T, "v5t" }, + { ARM_GRP_V5TE, "v5te" }, + { ARM_GRP_V6, "v6" }, + { ARM_GRP_V6T2, "v6t2" }, + { ARM_GRP_V7, "v7" }, + { ARM_GRP_V8, "v8" }, + { ARM_GRP_VFP2, "vfp2" }, + { ARM_GRP_VFP3, "vfp3" }, + { ARM_GRP_VFP4, "vfp4" }, + { ARM_GRP_ARM, "arm" }, + { ARM_GRP_MCLASS, "mclass" }, + { ARM_GRP_NOTMCLASS, "notmclass" }, + { ARM_GRP_THUMB, "thumb" }, + { ARM_GRP_THUMB1ONLY, "thumb1only" }, + { ARM_GRP_THUMB2, "thumb2" }, + { ARM_GRP_PREV8, "prev8" }, + { ARM_GRP_FPVMLX, "fpvmlx" }, + { ARM_GRP_MULOPS, "mulops" }, + { ARM_GRP_CRC, "crc" }, + { ARM_GRP_DPVFP, "dpvfp" }, + { ARM_GRP_V6M, "v6m" }, + { ARM_GRP_VIRTUALIZATION, "virtualization" }, +}; +#endif + +const char *ARM_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +// list all relative branch instructions +// ie: insns[i].branch && !insns[i].indirect_branch +static const unsigned int insn_rel[] = { + ARM_BL, + ARM_BLX_pred, + ARM_Bcc, + ARM_t2B, + ARM_t2Bcc, + ARM_tB, + ARM_tBcc, + ARM_tCBNZ, + ARM_tCBZ, + ARM_BL_pred, + ARM_BLXi, + ARM_tBL, + ARM_tBLXi, + 0 +}; + +static const unsigned int insn_blx_rel_to_arm[] = { + ARM_tBLXi, + 0 +}; + +// check if this insn is relative branch +bool ARM_rel_branch(cs_struct *h, unsigned int id) +{ + int i; + + for (i = 0; insn_rel[i]; i++) { + if (id == insn_rel[i]) { + return true; + } + } + + // not found + return false; +} + +bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) { + int i; + + for (i = 0; insn_blx_rel_to_arm[i]; i++) + if (id == insn_blx_rel_to_arm[i]) + return true; + + // not found + return false; + +} + +#ifndef CAPSTONE_DIET +// map instruction to its characteristics +typedef struct insn_op { + uint8_t access[7]; +} insn_op; + +static const insn_op insn_ops[] = { + { + // NULL item + { 0 } + }, + +#include "ARMMappingInsnOp.inc" +}; + +// given internal insn id, return operand access info +const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id) +{ + int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); + if (i != 0) { + return insn_ops[i].access; + } + + return NULL; +} + +void ARM_reg_access(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count) +{ + uint8_t i; + uint8_t read_count, write_count; + cs_arm *arm = &(insn->detail->arm); + + read_count = insn->detail->regs_read_count; + write_count = insn->detail->regs_write_count; + + // implicit registers + memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); + memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); + + // explicit registers + for (i = 0; i < arm->op_count; i++) { + cs_arm_op *op = &(arm->operands[i]); + switch((int)op->type) { + case ARM_OP_REG: + if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { + regs_read[read_count] = (uint16_t)op->reg; + read_count++; + } + if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { + regs_write[write_count] = (uint16_t)op->reg; + write_count++; + } + break; + case ARM_OP_MEM: + // registers appeared in memory references always being read + if ((op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { + regs_read[read_count] = (uint16_t)op->mem.base; + read_count++; + } + if ((op->mem.index != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { + regs_read[read_count] = (uint16_t)op->mem.index; + read_count++; + } + if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) { + regs_write[write_count] = (uint16_t)op->mem.base; + write_count++; + } + default: + break; + } + } + + *regs_read_count = read_count; + *regs_write_count = write_count; +} +#endif + +#endif diff --git a/capstone/arch/ARM/ARMMapping.h b/capstone/arch/ARM/ARMMapping.h new file mode 100644 index 000000000..1f413d0ce --- /dev/null +++ b/capstone/arch/ARM/ARMMapping.h @@ -0,0 +1,40 @@ +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +#ifndef CS_ARM_MAP_H +#define CS_ARM_MAP_H + +#include "../../include/capstone/capstone.h" +#include "../../utils.h" + +// return name of regiser in friendly string +const char *ARM_reg_name(csh handle, unsigned int reg); +const char *ARM_reg_name2(csh handle, unsigned int reg); + +// given internal insn id, return public instruction ID +void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); + +const char *ARM_insn_name(csh handle, unsigned int id); + +const char *ARM_group_name(csh handle, unsigned int id); + +// check if this insn is relative branch +bool ARM_rel_branch(cs_struct *h, unsigned int insn_id); + +bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id); + +const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id); + +void ARM_reg_access(const cs_insn *insn, + cs_regs regs_read, uint8_t *regs_read_count, + cs_regs regs_write, uint8_t *regs_write_count); + +typedef struct BankedReg { + const char *Name; + arm_sysreg sysreg; + uint16_t Encoding; +} BankedReg; + +const BankedReg *lookupBankedRegByEncoding(uint8_t encoding); + +#endif diff --git a/capstone/arch/ARM/ARMMappingInsn.inc b/capstone/arch/ARM/ARMMappingInsn.inc new file mode 100644 index 000000000..0bb23c67d --- /dev/null +++ b/capstone/arch/ARM/ARMMappingInsn.inc @@ -0,0 +1,18772 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + + +{ + ARM_ASRi, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_ASRr, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_ITasm, ARM_INS_IT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRBT_POST, ARM_INS_LDRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRConstPool, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRT_POST, ARM_INS_LDRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_LSLi, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_LSLr, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_LSRi, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_LSRr, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_RORi, ARM_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_RORr, ARM_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_RRXi, ARM_INS_RRX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_STRBT_POST, ARM_INS_STRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_STRT_POST, ARM_INS_STRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNdAsm_16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNdAsm_32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNdAsm_8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNdWB_fixed_Asm_16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNdWB_fixed_Asm_32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNdWB_fixed_Asm_8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNdWB_register_Asm_16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNdWB_register_Asm_32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNdWB_register_Asm_8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNdAsm_16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNdAsm_32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNdAsm_8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNdWB_fixed_Asm_16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNdWB_fixed_Asm_32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNdWB_fixed_Asm_8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNdWB_register_Asm_16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNdWB_register_Asm_32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNdWB_register_Asm_8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNqAsm_16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNqAsm_32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNqWB_fixed_Asm_16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNqWB_fixed_Asm_32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNqWB_register_Asm_16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNqWB_register_Asm_32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPdAsm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPdAsm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPdAsm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPdWB_fixed_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPdWB_fixed_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPdWB_fixed_Asm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPdWB_register_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPdWB_register_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPdWB_register_Asm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPqAsm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPqAsm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPqAsm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPqWB_fixed_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPqWB_fixed_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPqWB_fixed_Asm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPqWB_register_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPqWB_register_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPqWB_register_Asm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNdAsm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNdAsm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNdAsm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNdWB_fixed_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNdWB_fixed_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNdWB_fixed_Asm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNdWB_register_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNdWB_register_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNdWB_register_Asm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNqAsm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNqAsm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNqWB_fixed_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNqWB_fixed_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNqWB_register_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNqWB_register_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3dAsm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3dAsm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3dAsm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3dWB_fixed_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3dWB_fixed_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3dWB_fixed_Asm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3dWB_register_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3dWB_register_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3dWB_register_Asm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3qAsm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3qAsm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3qAsm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3qWB_fixed_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3qWB_fixed_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3qWB_fixed_Asm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3qWB_register_Asm_16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3qWB_register_Asm_32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3qWB_register_Asm_8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPdAsm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPdAsm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPdAsm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPdWB_fixed_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPdWB_fixed_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPdWB_fixed_Asm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPdWB_register_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPdWB_register_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPdWB_register_Asm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPqAsm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPqAsm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPqAsm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPqWB_fixed_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPqWB_fixed_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPqWB_fixed_Asm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPqWB_register_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPqWB_register_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPqWB_register_Asm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNdAsm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNdAsm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNdAsm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNdWB_fixed_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNdWB_fixed_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNdWB_fixed_Asm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNdWB_register_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNdWB_register_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNdWB_register_Asm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNqAsm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNqAsm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNqWB_fixed_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNqWB_fixed_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNqWB_register_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNqWB_register_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4dAsm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4dAsm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4dAsm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4dWB_fixed_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4dWB_fixed_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4dWB_fixed_Asm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4dWB_register_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4dWB_register_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4dWB_register_Asm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4qAsm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4qAsm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4qAsm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4qWB_fixed_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4qWB_fixed_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4qWB_fixed_Asm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4qWB_register_Asm_16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4qWB_register_Asm_32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4qWB_register_Asm_8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNdAsm_16, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNdAsm_32, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNdAsm_8, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNdWB_fixed_Asm_16, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNdWB_fixed_Asm_32, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNdWB_fixed_Asm_8, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNdWB_register_Asm_16, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNdWB_register_Asm_32, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNdWB_register_Asm_8, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNdAsm_16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNdAsm_32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNdAsm_8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNdWB_fixed_Asm_16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNdWB_fixed_Asm_32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNdWB_fixed_Asm_8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNdWB_register_Asm_16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNdWB_register_Asm_32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNdWB_register_Asm_8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNqAsm_16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNqAsm_32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNqWB_fixed_Asm_16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNqWB_fixed_Asm_32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNqWB_register_Asm_16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNqWB_register_Asm_32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNdAsm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNdAsm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNdAsm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNdWB_fixed_Asm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNdWB_fixed_Asm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNdWB_fixed_Asm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNdWB_register_Asm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNdWB_register_Asm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNdWB_register_Asm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNqAsm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNqAsm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNqWB_fixed_Asm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNqWB_fixed_Asm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNqWB_register_Asm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNqWB_register_Asm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3dAsm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3dAsm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3dAsm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3dWB_fixed_Asm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3dWB_fixed_Asm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3dWB_fixed_Asm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3dWB_register_Asm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3dWB_register_Asm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3dWB_register_Asm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3qAsm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3qAsm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3qAsm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3qWB_fixed_Asm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3qWB_fixed_Asm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3qWB_fixed_Asm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3qWB_register_Asm_16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3qWB_register_Asm_32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3qWB_register_Asm_8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNdAsm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNdAsm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNdAsm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNdWB_fixed_Asm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNdWB_fixed_Asm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNdWB_fixed_Asm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNdWB_register_Asm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNdWB_register_Asm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNdWB_register_Asm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNqAsm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNqAsm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNqWB_fixed_Asm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNqWB_fixed_Asm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNqWB_register_Asm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNqWB_register_Asm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4dAsm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4dAsm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4dAsm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4dWB_fixed_Asm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4dWB_fixed_Asm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4dWB_fixed_Asm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4dWB_register_Asm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4dWB_register_Asm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4dWB_register_Asm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4qAsm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4qAsm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4qAsm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4qWB_fixed_Asm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4qWB_fixed_Asm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4qWB_fixed_Asm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4qWB_register_Asm_16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4qWB_register_Asm_32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4qWB_register_Asm_8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRBpcrel, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRConstPool, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRHpcrel, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSBpcrel, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSHpcrel, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRpcrel, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MOVSsi, ARM_INS_MOVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MOVSsr, ARM_INS_MOVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MOVsi, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MOVsr, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRConstPool, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_ADCri, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ADCrr, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ADCrsi, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ADCrsr, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ADDri, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ADDrr, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ADDrsi, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ADDrsr, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ADR, ARM_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_AESD, ARM_INS_AESD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_AESE, ARM_INS_AESE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_AESIMC, ARM_INS_AESIMC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_AESMC, ARM_INS_AESMC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_ANDri, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ANDrr, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ANDrsi, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ANDrsr, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_BFC, ARM_INS_BFC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif +}, + +{ + ARM_BFI, ARM_INS_BFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif +}, + +{ + ARM_BICri, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_BICrr, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_BICrsi, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_BICrsr, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_BKPT, ARM_INS_BKPT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_BL, ARM_INS_BL, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 +#endif +}, + +{ + ARM_BLX, ARM_INS_BLX, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_V5T, 0 }, 0, 1 +#endif +}, + +{ + ARM_BLX_pred, ARM_INS_BLX, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 1 +#endif +}, + +{ + ARM_BLXi, ARM_INS_BLX, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 1, 0 +#endif +}, + +{ + ARM_BL_pred, ARM_INS_BL, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 +#endif +}, + +{ + ARM_BX, ARM_INS_BX, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 +#endif +}, + +{ + ARM_BXJ, ARM_INS_BXJ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, 0 }, 0, 1 +#endif +}, + +{ + ARM_BX_RET, ARM_INS_BX, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 +#endif +}, + +{ + ARM_BX_pred, ARM_INS_BX, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 +#endif +}, + +{ + ARM_Bcc, ARM_INS_B, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 +#endif +}, + +{ + ARM_CDP, ARM_INS_CDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_CDP2, ARM_INS_CDP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_CLREX, ARM_INS_CLREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 +#endif +}, + +{ + ARM_CLZ, ARM_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 +#endif +}, + +{ + ARM_CMNri, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CMNzrr, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CMNzrsi, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CMNzrsr, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CMPri, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CMPrr, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CMPrsi, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CMPrsr, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CPS1p, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CPS2p, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CPS3p, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_CRC32B, ARM_INS_CRC32B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_CRC32CB, ARM_INS_CRC32CB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_CRC32CH, ARM_INS_CRC32CH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_CRC32CW, ARM_INS_CRC32CW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_CRC32H, ARM_INS_CRC32H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_CRC32W, ARM_INS_CRC32W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_DBG, ARM_INS_DBG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 +#endif +}, + +{ + ARM_DMB, ARM_INS_DMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 +#endif +}, + +{ + ARM_DSB, ARM_INS_DSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 +#endif +}, + +{ + ARM_EORri, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_EORrr, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_EORrsi, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_EORrsr, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ERET, ARM_INS_ERET, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 +#endif +}, + +{ + ARM_FCONSTD, ARM_INS_FCONSTD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP3, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_FCONSTH, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_FCONSTS, ARM_INS_FCONSTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP3, 0 }, 0, 0 +#endif +}, + +{ + ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_FLDMXIA, ARM_INS_FLDMIAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_FMSTAT, ARM_INS_FMSTAT, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR_NZCV, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_FSTMXIA, ARM_INS_FSTMIAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_HINT, ARM_INS_HINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_HLT, ARM_INS_HLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_HVC, ARM_INS_HVC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 +#endif +}, + +{ + ARM_ISB, ARM_INS_ISB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDA, ARM_INS_LDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDAB, ARM_INS_LDAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDAEX, ARM_INS_LDAEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDAEXB, ARM_INS_LDAEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDAEXD, ARM_INS_LDAEXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDAEXH, ARM_INS_LDAEXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDAH, ARM_INS_LDAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC2L_OFFSET, ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC2L_OPTION, ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC2L_POST, ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC2L_PRE, ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC2_OFFSET, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC2_OPTION, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC2_POST, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC2_PRE, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDCL_OFFSET, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDCL_OPTION, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDCL_POST, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDCL_PRE, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC_OFFSET, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC_OPTION, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC_POST, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDC_PRE, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDMDA, ARM_INS_LDMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDMDA_UPD, ARM_INS_LDMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDMDB, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDMDB_UPD, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDMIA, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDMIA_UPD, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDMIB, ARM_INS_LDMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDMIB_UPD, ARM_INS_LDMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRBT_POST_IMM, ARM_INS_LDRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRBT_POST_REG, ARM_INS_LDRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRB_POST_IMM, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRB_POST_REG, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRB_PRE_IMM, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRB_PRE_REG, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRBi12, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRBrs, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRD, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRD_POST, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRD_PRE, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDREX, ARM_INS_LDREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDREXB, ARM_INS_LDREXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDREXD, ARM_INS_LDREXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDREXH, ARM_INS_LDREXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRH, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRHTi, ARM_INS_LDRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRHTr, ARM_INS_LDRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRH_POST, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRH_PRE, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRSB, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRSBTi, ARM_INS_LDRSBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRSBTr, ARM_INS_LDRSBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRSB_POST, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRSB_PRE, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRSH, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRSHTi, ARM_INS_LDRSHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRSHTr, ARM_INS_LDRSHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRSH_POST, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRSH_PRE, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRT_POST_IMM, ARM_INS_LDRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRT_POST_REG, ARM_INS_LDRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDR_POST_IMM, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDR_POST_REG, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDR_PRE_IMM, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDR_PRE_REG, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRcp, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRi12, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_LDRrs, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MCR, ARM_INS_MCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MCR2, ARM_INS_MCR2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_MCRR, ARM_INS_MCRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MCRR2, ARM_INS_MCRR2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_MLA, ARM_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_MLS, ARM_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_MOVPCLR, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MOVTi16, ARM_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif +}, + +{ + ARM_MOVi, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MOVi16, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif +}, + +{ + ARM_MOVr, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MOVr_TC, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MOVsi, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MOVsr, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MRC, ARM_INS_MRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MRC2, ARM_INS_MRC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_MRRC, ARM_INS_MRRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MRRC2, ARM_INS_MRRC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_MRS, ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MRSbanked, ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 +#endif +}, + +{ + ARM_MRSsys, ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MSR, ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MSRbanked, ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 +#endif +}, + +{ + ARM_MSRi, ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MUL, ARM_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_MVNi, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MVNr, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MVNsi, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_MVNsr, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ORRri, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ORRrr, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ORRrsi, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_ORRrsr, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_PKHBT, ARM_INS_PKHBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_PKHTB, ARM_INS_PKHTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_PLDWi12, ARM_INS_PLDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 +#endif +}, + +{ + ARM_PLDWrs, ARM_INS_PLDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 +#endif +}, + +{ + ARM_PLDi12, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_PLDrs, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_PLIi12, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 +#endif +}, + +{ + ARM_PLIrs, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 +#endif +}, + +{ + ARM_QADD, ARM_INS_QADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_QADD16, ARM_INS_QADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_QADD8, ARM_INS_QADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_QASX, ARM_INS_QASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_QDADD, ARM_INS_QDADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_QDSUB, ARM_INS_QDSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_QSAX, ARM_INS_QSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_QSUB, ARM_INS_QSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_QSUB16, ARM_INS_QSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_QSUB8, ARM_INS_QSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RBIT, ARM_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif +}, + +{ + ARM_REV, ARM_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_REV16, ARM_INS_REV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_REVSH, ARM_INS_REVSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_RFEDA, ARM_INS_RFEDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RFEDA_UPD, ARM_INS_RFEDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RFEDB, ARM_INS_RFEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RFEDB_UPD, ARM_INS_RFEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RFEIA, ARM_INS_RFEIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RFEIA_UPD, ARM_INS_RFEIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RFEIB, ARM_INS_RFEIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RFEIB_UPD, ARM_INS_RFEIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RSBri, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RSBrr, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RSBrsi, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RSBrsr, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RSCri, ARM_INS_RSC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RSCrr, ARM_INS_RSC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RSCrsi, ARM_INS_RSC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_RSCrsr, ARM_INS_RSC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SADD16, ARM_INS_SADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SADD8, ARM_INS_SADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SASX, ARM_INS_SASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SBCri, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SBCrr, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SBCrsi, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SBCrsr, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SBFX, ARM_INS_SBFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif +}, + +{ + ARM_SDIV, ARM_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SEL, ARM_INS_SEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SETEND, ARM_INS_SETEND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SETPAN, ARM_INS_SETPAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_SHA1C, ARM_INS_SHA1C, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHA1H, ARM_INS_SHA1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHA1M, ARM_INS_SHA1M, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHA1P, ARM_INS_SHA1P, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHA1SU0, ARM_INS_SHA1SU0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHA1SU1, ARM_INS_SHA1SU1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHA256H, ARM_INS_SHA256H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHA256H2, ARM_INS_SHA256H2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHA256SU0, ARM_INS_SHA256SU0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHA256SU1, ARM_INS_SHA256SU1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHADD16, ARM_INS_SHADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHADD8, ARM_INS_SHADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHASX, ARM_INS_SHASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHSAX, ARM_INS_SHSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHSUB16, ARM_INS_SHSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SHSUB8, ARM_INS_SHSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMC, ARM_INS_SMC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLABB, ARM_INS_SMLABB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLABT, ARM_INS_SMLABT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLAD, ARM_INS_SMLAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLADX, ARM_INS_SMLADX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLAL, ARM_INS_SMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLALBB, ARM_INS_SMLALBB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLALBT, ARM_INS_SMLALBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLALD, ARM_INS_SMLALD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLALDX, ARM_INS_SMLALDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLALTB, ARM_INS_SMLALTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLALTT, ARM_INS_SMLALTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLATB, ARM_INS_SMLATB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLATT, ARM_INS_SMLATT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLAWB, ARM_INS_SMLAWB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLAWT, ARM_INS_SMLAWT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLSD, ARM_INS_SMLSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLSDX, ARM_INS_SMLSDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLSLD, ARM_INS_SMLSLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMLSLDX, ARM_INS_SMLSLDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMMLA, ARM_INS_SMMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMMLAR, ARM_INS_SMMLAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMMLS, ARM_INS_SMMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMMLSR, ARM_INS_SMMLSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMMUL, ARM_INS_SMMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMMULR, ARM_INS_SMMULR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMUAD, ARM_INS_SMUAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMUADX, ARM_INS_SMUADX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMULBB, ARM_INS_SMULBB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMULBT, ARM_INS_SMULBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMULL, ARM_INS_SMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMULTB, ARM_INS_SMULTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMULTT, ARM_INS_SMULTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMULWB, ARM_INS_SMULWB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMULWT, ARM_INS_SMULWT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMUSD, ARM_INS_SMUSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SMUSDX, ARM_INS_SMUSDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SRSDA, ARM_INS_SRSDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SRSDA_UPD, ARM_INS_SRSDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SRSDB, ARM_INS_SRSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SRSDB_UPD, ARM_INS_SRSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SRSIA, ARM_INS_SRSIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SRSIA_UPD, ARM_INS_SRSIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SRSIB, ARM_INS_SRSIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SRSIB_UPD, ARM_INS_SRSIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SSAT, ARM_INS_SSAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SSAT16, ARM_INS_SSAT16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SSAX, ARM_INS_SSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SSUB16, ARM_INS_SSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SSUB8, ARM_INS_SSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC2L_OFFSET, ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC2L_OPTION, ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC2L_POST, ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC2L_PRE, ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC2_OFFSET, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC2_OPTION, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC2_POST, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC2_PRE, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STCL_OFFSET, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STCL_OPTION, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STCL_POST, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STCL_PRE, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC_OFFSET, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC_OPTION, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC_POST, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STC_PRE, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STL, ARM_INS_STL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STLB, ARM_INS_STLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STLEX, ARM_INS_STLEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STLEXB, ARM_INS_STLEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STLEXD, ARM_INS_STLEXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STLEXH, ARM_INS_STLEXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STLH, ARM_INS_STLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_STMDA, ARM_INS_STMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STMDA_UPD, ARM_INS_STMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STMDB, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STMDB_UPD, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STMIA, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STMIA_UPD, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STMIB, ARM_INS_STMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STMIB_UPD, ARM_INS_STMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRBT_POST_IMM, ARM_INS_STRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRBT_POST_REG, ARM_INS_STRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRB_POST_IMM, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRB_POST_REG, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRB_PRE_IMM, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRB_PRE_REG, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRBi12, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRBrs, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRD, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRD_POST, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRD_PRE, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STREX, ARM_INS_STREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STREXB, ARM_INS_STREXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STREXD, ARM_INS_STREXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STREXH, ARM_INS_STREXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRH, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRHTi, ARM_INS_STRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRHTr, ARM_INS_STRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRH_POST, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRH_PRE, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRT_POST_IMM, ARM_INS_STRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRT_POST_REG, ARM_INS_STRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STR_POST_IMM, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STR_POST_REG, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STR_PRE_IMM, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STR_PRE_REG, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRi12, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_STRrs, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SUBri, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SUBrr, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SUBrsi, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SUBrsr, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_SVC, ARM_INS_SVC, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + ARM_SWP, ARM_INS_SWP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_SWPB, ARM_INS_SWPB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_SXTAB, ARM_INS_SXTAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SXTAB16, ARM_INS_SXTAB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SXTAH, ARM_INS_SXTAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SXTB, ARM_INS_SXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SXTB16, ARM_INS_SXTB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_SXTH, ARM_INS_SXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_TEQri, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_TEQrr, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_TEQrsi, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_TEQrsr, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_TRAP, ARM_INS_TRAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_TRAPNaCl, ARM_INS_TRAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_TSB, ARM_INS_TSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_TSTri, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_TSTrr, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_TSTrsi, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_TSTrsr, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UADD16, ARM_INS_UADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UADD8, ARM_INS_UADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UASX, ARM_INS_UASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UBFX, ARM_INS_UBFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 +#endif +}, + +{ + ARM_UDF, ARM_INS_UDF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UDIV, ARM_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UHADD16, ARM_INS_UHADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UHADD8, ARM_INS_UHADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UHASX, ARM_INS_UHASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UHSAX, ARM_INS_UHSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UHSUB16, ARM_INS_UHSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UHSUB8, ARM_INS_UHSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UMAAL, ARM_INS_UMAAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_UMLAL, ARM_INS_UMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_UMULL, ARM_INS_UMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_UQADD16, ARM_INS_UQADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UQADD8, ARM_INS_UQADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UQASX, ARM_INS_UQASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UQSAX, ARM_INS_UQSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UQSUB16, ARM_INS_UQSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UQSUB8, ARM_INS_UQSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_USAD8, ARM_INS_USAD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_USADA8, ARM_INS_USADA8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_USAT, ARM_INS_USAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_USAT16, ARM_INS_USAT16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_USAX, ARM_INS_USAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_USUB16, ARM_INS_USUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_USUB8, ARM_INS_USUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_UXTAB, ARM_INS_UXTAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_UXTAB16, ARM_INS_UXTAB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_UXTAH, ARM_INS_UXTAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_UXTB, ARM_INS_UXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_UXTB16, ARM_INS_UXTB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_UXTH, ARM_INS_UXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABALsv2i64, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABALsv4i32, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABALsv8i16, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABALuv2i64, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABALuv4i32, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABALuv8i16, ARM_INS_VABAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAsv16i8, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAsv2i32, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAsv4i16, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAsv4i32, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAsv8i16, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAsv8i8, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAuv16i8, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAuv2i32, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAuv4i16, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAuv4i32, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAuv8i16, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABAuv8i8, ARM_INS_VABA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDLsv2i64, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDLsv4i32, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDLsv8i16, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDLuv2i64, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDLuv4i32, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDLuv8i16, ARM_INS_VABDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDfd, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDfq, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDhd, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDhq, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDsv16i8, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDsv2i32, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDsv4i16, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDsv4i32, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDsv8i16, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDsv8i8, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDuv16i8, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDuv2i32, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDuv4i16, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDuv4i32, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDuv8i16, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABDuv8i8, ARM_INS_VABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSD, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSH, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSS, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSfd, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSfq, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABShd, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VABShq, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSv16i8, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSv2i32, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSv4i16, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSv4i32, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSv8i16, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VABSv8i8, ARM_INS_VABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VACGEfd, ARM_INS_VACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VACGEfq, ARM_INS_VACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VACGEhd, ARM_INS_VACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VACGEhq, ARM_INS_VACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VACGTfd, ARM_INS_VACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VACGTfq, ARM_INS_VACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VACGThd, ARM_INS_VACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VACGThq, ARM_INS_VACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDD, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDH, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDHNv2i32, ARM_INS_VADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDHNv4i16, ARM_INS_VADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDHNv8i8, ARM_INS_VADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDLsv2i64, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDLsv4i32, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDLsv8i16, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDLuv2i64, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDLuv4i32, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDLuv8i16, ARM_INS_VADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDS, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDWsv2i64, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDWsv4i32, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDWsv8i16, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDWuv2i64, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDWuv4i32, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDWuv8i16, ARM_INS_VADDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDfd, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDfq, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDhd, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDhq, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDv16i8, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDv1i64, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDv2i32, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDv2i64, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDv4i16, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDv4i32, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDv8i16, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VADDv8i8, ARM_INS_VADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VANDd, ARM_INS_VAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VANDq, ARM_INS_VAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBICd, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBICiv2i32, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBICiv4i16, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBICiv4i32, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBICiv8i16, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBICq, ARM_INS_VBIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBIFd, ARM_INS_VBIF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBIFq, ARM_INS_VBIF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBITd, ARM_INS_VBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBITq, ARM_INS_VBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBSLd, ARM_INS_VBSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VBSLq, ARM_INS_VBSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCADDv2f32, ARM_INS_VCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCADDv4f16, ARM_INS_VCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCADDv4f32, ARM_INS_VCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCADDv8f16, ARM_INS_VCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQfd, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQfq, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQhd, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQhq, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQv16i8, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQv2i32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQv4i16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQv4i32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQv8i16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQv8i8, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQzv16i8, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQzv2f32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQzv2i32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQzv4f16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQzv4f32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQzv4i16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQzv4i32, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQzv8f16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQzv8i16, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCEQzv8i8, ARM_INS_VCEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEfd, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEfq, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEhd, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEhq, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEsv16i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEsv2i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEsv4i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEsv4i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEsv8i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEsv8i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEuv16i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEuv2i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEuv4i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEuv4i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEuv8i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEuv8i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEzv16i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEzv2f32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEzv2i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEzv4f16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEzv4f32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEzv4i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEzv4i32, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEzv8f16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEzv8i16, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGEzv8i8, ARM_INS_VCGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTfd, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTfq, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGThd, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGThq, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTsv16i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTsv2i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTsv4i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTsv4i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTsv8i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTsv8i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTuv16i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTuv2i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTuv4i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTuv4i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTuv8i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTuv8i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTzv16i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTzv2f32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTzv2i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTzv4f16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTzv4f32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTzv4i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTzv4i32, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTzv8f16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTzv8i16, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCGTzv8i8, ARM_INS_VCGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLEzv16i8, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLEzv2f32, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLEzv2i32, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLEzv4f16, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLEzv4f32, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLEzv4i16, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLEzv4i32, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLEzv8f16, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLEzv8i16, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLEzv8i8, ARM_INS_VCLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLSv16i8, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLSv2i32, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLSv4i16, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLSv4i32, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLSv8i16, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLSv8i8, ARM_INS_VCLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLTzv16i8, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLTzv2f32, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLTzv2i32, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLTzv4f16, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLTzv4f32, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLTzv4i16, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLTzv4i32, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLTzv8f16, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLTzv8i16, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLTzv8i8, ARM_INS_VCLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLZv16i8, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLZv2i32, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLZv4i16, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLZv4i32, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLZv8i16, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCLZv8i8, ARM_INS_VCLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMLAv2f32, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMLAv2f32_indexed, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMLAv4f16, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMLAv4f16_indexed, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMLAv4f32, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMLAv4f32_indexed, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMLAv8f16, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMLAv8f16_indexed, ARM_INS_VCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPD, ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPED, ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPEH, ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPES, ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPEZD, ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPEZH, ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPEZS, ARM_INS_VCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPH, ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPS, ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPZD, ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPZH, ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCMPZS, ARM_INS_VCMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCNTd, ARM_INS_VCNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCNTq, ARM_INS_VCNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTANSDf, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTANSDh, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTANSQf, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTANSQh, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTANUDf, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTANUDh, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTANUQf, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTANUQh, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTASD, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTASH, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTASS, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTAUD, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTAUH, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTAUS, ARM_INS_VCVTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTBDH, ARM_INS_VCVTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTBHD, ARM_INS_VCVTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTBHS, ARM_INS_VCVTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTBSH, ARM_INS_VCVTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTDS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMNSDf, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMNSDh, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMNSQf, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMNSQh, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMNUDf, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMNUDh, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMNUQf, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMNUQh, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMSD, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMSH, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMSS, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMUD, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMUH, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTMUS, ARM_INS_VCVTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNNSDf, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNNSDh, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNNSQf, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNNSQh, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNNUDf, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNNUDh, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNNUQf, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNNUQh, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNSD, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNSH, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNSS, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNUD, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNUH, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTNUS, ARM_INS_VCVTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPNSDf, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPNSDh, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPNSQf, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPNSQh, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPNUDf, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPNUDh, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPNUQf, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPNUQh, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPSD, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPSH, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPSS, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPUD, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPUH, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTPUS, ARM_INS_VCVTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTSD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTTDH, ARM_INS_VCVTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTTHD, ARM_INS_VCVTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTTHS, ARM_INS_VCVTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTTSH, ARM_INS_VCVTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTf2h, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTf2sd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTf2sq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTf2ud, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTf2uq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTf2xsd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTf2xsq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTf2xud, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTf2xuq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTh2f, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTh2sd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTh2sq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTh2ud, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTh2uq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTh2xsd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTh2xsq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTh2xud, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTh2xuq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTs2fd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTs2fq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTs2hd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTs2hq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTu2fd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTu2fq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTu2hd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTu2hq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTxs2fd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTxs2fq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTxs2hd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTxs2hq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTxu2fd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTxu2fq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTxu2hd, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VCVTxu2hq, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VDIVD, ARM_INS_VDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDIVH, ARM_INS_VDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VDIVS, ARM_INS_VDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUP16d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUP16q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUP32d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUP32q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUP8d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUP8q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUPLN16d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUPLN16q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUPLN32d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUPLN32q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUPLN8d, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VDUPLN8q, ARM_INS_VDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VEORd, ARM_INS_VEOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VEORq, ARM_INS_VEOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VEXTd16, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VEXTd32, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VEXTd8, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VEXTq16, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VEXTq32, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VEXTq64, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VEXTq8, ARM_INS_VEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMAD, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMAH, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMAS, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMAfd, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMAfq, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMAhd, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMAhq, ARM_INS_VFMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMSD, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMSH, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMSS, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMSfd, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMSfq, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMShd, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VFMShq, ARM_INS_VFMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VFNMAD, ARM_INS_VFNMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFNMAH, ARM_INS_VFNMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VFNMAS, ARM_INS_VFNMA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFNMSD, ARM_INS_VFNMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VFNMSH, ARM_INS_VFNMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VFNMSS, ARM_INS_VFNMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 +#endif +}, + +{ + ARM_VGETLNi32, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VGETLNs16, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VGETLNs8, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VGETLNu16, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VGETLNu8, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDsv16i8, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDsv2i32, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDsv4i16, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDsv4i32, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDsv8i16, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDsv8i8, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDuv16i8, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDuv2i32, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDuv4i16, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDuv4i32, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDuv8i16, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHADDuv8i8, ARM_INS_VHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBsv16i8, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBsv2i32, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBsv4i16, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBsv4i32, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBsv8i16, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBsv8i8, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBuv16i8, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBuv2i32, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBuv4i16, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBuv4i32, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBuv8i16, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VHSUBuv8i8, ARM_INS_VHSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VINSH, ARM_INS_VINS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VJCVT, ARM_INS_VJCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPd16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPd16wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPd32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPd32wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPd8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPd8wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPq16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPq16wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPq32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPq32wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPq8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1DUPq8wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNd16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNd16_UPD, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNd32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNd32_UPD, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNd8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1LNd8_UPD, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d16Q, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d16Qwb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d16T, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d16Twb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d16Twb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d16wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d16wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d32Q, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d32Qwb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d32T, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d32Twb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d32Twb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d32wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d32wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d64, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d64Q, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d64Qwb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d64T, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d64Twb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d64Twb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d64wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d64wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d8Q, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d8Qwb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d8T, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d8Twb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d8Twb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d8wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1d8wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q16, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q16wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q16wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q32, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q32wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q32wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q64, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q64wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q64wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q8, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q8wb_fixed, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD1q8wb_register, ARM_INS_VLD1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd16wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd16x2, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd32wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd32x2, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd8wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd8x2, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNd16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNd16_UPD, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNd32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNd32_UPD, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNd8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNd8_UPD, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNq16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNq16_UPD, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNq32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2LNq32_UPD, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2b16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2b16wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2b16wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2b32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2b32wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2b32wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2b8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2b8wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2b8wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2d16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2d16wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2d16wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2d32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2d32wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2d32wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2d8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2d8wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2d8wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2q16, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2q16wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2q16wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2q32, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2q32wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2q32wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2q8, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2q8wb_fixed, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD2q8wb_register, ARM_INS_VLD2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPd16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPd16_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPd32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPd32_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPd8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPd8_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPq16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPq16_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPq32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPq32_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPq8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3DUPq8_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNd16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNd16_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNd32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNd32_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNd8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNd8_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNq16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNq16_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNq32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3LNq32_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3d16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3d16_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3d32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3d32_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3d8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3d8_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3q16, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3q16_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3q32, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3q32_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3q8, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD3q8_UPD, ARM_INS_VLD3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPd16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPd16_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPd32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPd32_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPd8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPd8_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPq16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPq16_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPq32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPq32_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPq8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4DUPq8_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNd16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNd16_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNd32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNd32_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNd8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNd8_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNq16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNq16_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNq32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4LNq32_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4d16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4d16_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4d32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4d32_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4d8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4d8_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4q16, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4q16_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4q32, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4q32_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4q8, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLD4q8_UPD, ARM_INS_VLD4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLDMDDB_UPD, ARM_INS_VLDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLDMDIA, ARM_INS_VLDMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLDMDIA_UPD, ARM_INS_VLDMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLDMSDB_UPD, ARM_INS_VLDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLDMSIA, ARM_INS_VLDMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLDMSIA_UPD, ARM_INS_VLDMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLDRD, ARM_INS_VLDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLDRH, ARM_INS_VLDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLDRS, ARM_INS_VLDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VLLDM, ARM_INS_VLLDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VLSTM, ARM_INS_VLSTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXNMD, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXNMH, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXNMNDf, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXNMNDh, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXNMNQf, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXNMNQh, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXNMS, ARM_INS_VMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXfd, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXfq, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXhd, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXhq, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXsv16i8, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXsv2i32, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXsv4i16, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXsv4i32, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXsv8i16, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXsv8i8, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXuv16i8, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXuv2i32, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXuv4i16, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXuv4i32, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXuv8i16, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMAXuv8i8, ARM_INS_VMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINNMD, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINNMH, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINNMNDf, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINNMNDh, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINNMNQf, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINNMNQh, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINNMS, ARM_INS_VMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINfd, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINfq, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINhd, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINhq, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINsv16i8, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINsv2i32, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINsv4i16, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINsv4i32, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINsv8i16, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINsv8i8, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINuv16i8, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINuv2i32, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINuv4i16, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINuv4i32, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINuv8i16, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMINuv8i8, ARM_INS_VMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAD, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAH, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLALslsv2i32, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLALslsv4i16, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLALsluv2i32, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLALsluv4i16, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLALsv2i64, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLALsv4i32, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLALsv8i16, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLALuv2i64, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLALuv4i32, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLALuv8i16, ARM_INS_VMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAS, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAfd, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAfq, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAhd, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAhq, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAslfd, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAslfq, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAslhd, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAslhq, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAslv2i32, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAslv4i16, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAslv4i32, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAslv8i16, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAv16i8, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAv2i32, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAv4i16, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAv4i32, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAv8i16, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLAv8i8, ARM_INS_VMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSD, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSH, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSLslsv2i32, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSLslsv4i16, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSLsluv2i32, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSLsluv4i16, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSLsv2i64, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSLsv4i32, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSLsv8i16, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSLuv2i64, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSLuv4i32, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSLuv8i16, ARM_INS_VMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSS, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSfd, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSfq, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLShd, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLShq, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSslfd, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSslfq, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSslhd, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSslhq, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSslv2i32, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSslv4i16, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSslv4i32, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSslv8i16, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSv16i8, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSv2i32, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSv4i16, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSv4i32, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSv8i16, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMLSv8i8, ARM_INS_VMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVD, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVDRR, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVH, ARM_INS_VMOVX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVHR, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVLsv2i64, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVLsv4i32, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVLsv8i16, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVLuv2i64, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVLuv4i32, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVLuv8i16, ARM_INS_VMOVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVNv2i32, ARM_INS_VMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVNv4i16, ARM_INS_VMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVNv8i8, ARM_INS_VMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVRH, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVRRD, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVRRS, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVRS, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVS, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVSR, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVSRR, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVv16i8, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVv1i64, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVv2f32, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVv2i32, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVv2i64, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVv4f32, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVv4i16, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVv4i32, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVv8i16, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMOVv8i8, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMRS, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMRS_FPEXC, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMRS_FPINST, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMRS_FPINST2, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMRS_FPSID, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMRS_MVFR0, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMRS_MVFR1, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMRS_MVFR2, ARM_INS_VMRS, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMSR, ARM_INS_VMSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMSR_FPEXC, ARM_INS_VMSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMSR_FPINST, ARM_INS_VMSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMSR_FPINST2, ARM_INS_VMSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMSR_FPSID, ARM_INS_VMSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULD, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULH, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLp64, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLp8, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLslsv2i32, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLslsv4i16, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLsluv2i32, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLsluv4i16, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLsv2i64, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLsv4i32, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLsv8i16, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLuv2i64, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLuv4i32, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULLuv8i16, ARM_INS_VMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULS, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULfd, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULfq, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULhd, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULhq, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULpd, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULpq, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULslfd, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULslfq, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULslhd, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULslhq, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULslv2i32, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULslv4i16, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULslv4i32, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULslv8i16, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULv16i8, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULv2i32, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULv4i16, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULv4i32, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULv8i16, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMULv8i8, ARM_INS_VMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMVNd, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMVNq, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMVNv2i32, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMVNv4i16, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMVNv4i32, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VMVNv8i16, ARM_INS_VMVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGD, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGH, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGS, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGf32q, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGfd, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGhd, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGhq, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGs16d, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGs16q, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGs32d, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGs32q, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGs8d, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNEGs8q, ARM_INS_VNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNMLAD, ARM_INS_VNMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNMLAH, ARM_INS_VNMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VNMLAS, ARM_INS_VNMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNMLSD, ARM_INS_VNMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNMLSH, ARM_INS_VNMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VNMLSS, ARM_INS_VNMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNMULD, ARM_INS_VNMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VNMULH, ARM_INS_VNMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VNMULS, ARM_INS_VNMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VORNd, ARM_INS_VORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VORNq, ARM_INS_VORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VORRd, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VORRiv2i32, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VORRiv4i16, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VORRiv4i32, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VORRiv8i16, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VORRq, ARM_INS_VORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALsv16i8, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALsv2i32, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALsv4i16, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALsv4i32, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALsv8i16, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALsv8i8, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALuv16i8, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALuv2i32, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALuv4i16, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALuv4i32, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALuv8i16, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADALuv8i8, ARM_INS_VPADAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLsv16i8, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLsv2i32, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLsv4i16, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLsv4i32, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLsv8i16, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLsv8i8, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLuv16i8, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLuv2i32, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLuv4i16, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLuv4i32, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLuv8i16, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDLuv8i8, ARM_INS_VPADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDf, ARM_INS_VPADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDh, ARM_INS_VPADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDi16, ARM_INS_VPADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDi32, ARM_INS_VPADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPADDi8, ARM_INS_VPADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMAXf, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMAXh, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMAXs16, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMAXs32, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMAXs8, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMAXu16, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMAXu32, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMAXu8, ARM_INS_VPMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMINf, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMINh, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMINs16, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMINs32, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMINs8, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMINu16, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMINu32, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VPMINu8, ARM_INS_VPMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQABSv16i8, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQABSv2i32, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQABSv4i16, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQABSv4i32, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQABSv8i16, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQABSv8i8, ARM_INS_VQABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDsv16i8, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDsv1i64, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDsv2i32, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDsv2i64, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDsv4i16, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDsv4i32, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDsv8i16, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDsv8i8, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDuv16i8, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDuv1i64, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDuv2i32, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDuv2i64, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDuv4i16, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDuv4i32, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDuv8i16, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQADDuv8i8, ARM_INS_VQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMLALv2i64, ARM_INS_VQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMLALv4i32, ARM_INS_VQDMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULHslv2i32, ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULHslv4i16, ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULHslv4i32, ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULHslv8i16, ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULHv2i32, ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULHv4i16, ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULHv4i32, ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULHv8i16, ARM_INS_VQDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULLslv2i32, ARM_INS_VQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULLslv4i16, ARM_INS_VQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULLv2i64, ARM_INS_VQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQDMULLv4i32, ARM_INS_VQDMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQMOVNsv2i32, ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQMOVNsv4i16, ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQMOVNsv8i8, ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQMOVNuv2i32, ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQMOVNuv4i16, ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQMOVNuv8i8, ARM_INS_VQMOVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQNEGv16i8, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQNEGv2i32, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQNEGv4i16, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQNEGv4i32, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQNEGv8i16, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQNEGv8i8, ARM_INS_VQNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLAHslv2i32, ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLAHslv4i16, ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLAHslv4i32, ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLAHslv8i16, ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLAHv2i32, ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLAHv4i16, ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLAHv4i32, ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLAHv8i16, ARM_INS_VQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLSHslv2i32, ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLSHslv4i16, ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLSHslv4i32, ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLSHslv8i16, ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLSHv2i32, ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLSHv4i16, ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLSHv4i32, ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMLSHv8i16, ARM_INS_VQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLsv16i8, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLsv1i64, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLsv2i32, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLsv2i64, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLsv4i16, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLsv4i32, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLsv8i16, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLsv8i8, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLuv16i8, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLuv1i64, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLuv2i32, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLuv2i64, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLuv4i16, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLuv4i32, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLuv8i16, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHLuv8i8, ARM_INS_VQRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsiv16i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsiv1i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsiv2i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsiv2i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsiv4i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsiv4i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsiv8i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsiv8i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsuv16i8, ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsuv1i64, ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsuv2i32, ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsuv2i64, ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsuv4i16, ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsuv4i32, ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsuv8i16, ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsuv8i8, ARM_INS_VQSHLU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsv16i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsv1i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsv2i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsv2i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsv4i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsv4i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsv8i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLsv8i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuiv16i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuiv1i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuiv2i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuiv2i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuiv4i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuiv4i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuiv8i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuiv8i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuv16i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuv1i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuv2i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuv2i64, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuv4i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuv4i32, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuv8i16, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHLuv8i8, ARM_INS_VQSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHRNsv2i32, ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHRNsv4i16, ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHRNsv8i8, ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHRNuv2i32, ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHRNuv4i16, ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHRNuv8i8, ARM_INS_VQSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBsv16i8, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBsv1i64, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBsv2i32, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBsv2i64, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBsv4i16, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBsv4i32, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBsv8i16, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBsv8i8, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBuv16i8, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBuv1i64, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBuv2i32, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBuv2i64, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBuv4i16, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBuv4i32, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBuv8i16, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VQSUBuv8i8, ARM_INS_VQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRADDHNv2i32, ARM_INS_VRADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRADDHNv4i16, ARM_INS_VRADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRADDHNv8i8, ARM_INS_VRADDHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRECPEd, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRECPEfd, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRECPEfq, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRECPEhd, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRECPEhq, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRECPEq, ARM_INS_VRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRECPSfd, ARM_INS_VRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRECPSfq, ARM_INS_VRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRECPShd, ARM_INS_VRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRECPShq, ARM_INS_VRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV16d8, ARM_INS_VREV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV16q8, ARM_INS_VREV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV32d16, ARM_INS_VREV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV32d8, ARM_INS_VREV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV32q16, ARM_INS_VREV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV32q8, ARM_INS_VREV32, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV64d16, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV64d32, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV64d8, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV64q16, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV64q32, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VREV64q8, ARM_INS_VREV64, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDsv16i8, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDsv2i32, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDsv4i16, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDsv4i32, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDsv8i16, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDsv8i8, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDuv16i8, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDuv2i32, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDuv4i16, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDuv4i32, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDuv8i16, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRHADDuv8i8, ARM_INS_VRHADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTAD, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTAH, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTANDf, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTANDh, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTANQf, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTANQh, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTAS, ARM_INS_VRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTMD, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTMH, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTMNDf, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTMNDh, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTMNQf, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTMNQh, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTMS, ARM_INS_VRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTND, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTNH, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTNNDf, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTNNDh, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTNNQf, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTNNQh, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTNS, ARM_INS_VRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTPD, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTPH, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTPNDf, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTPNDh, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTPNQf, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTPNQh, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTPS, ARM_INS_VRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTRD, ARM_INS_VRINTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTRH, ARM_INS_VRINTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTRS, ARM_INS_VRINTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTXD, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTXH, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTXNDf, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTXNDh, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTXNQf, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTXNQh, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTXS, ARM_INS_VRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTZD, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTZH, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTZNDf, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTZNDh, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTZNQf, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTZNQh, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRINTZS, ARM_INS_VRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLsv16i8, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLsv1i64, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLsv2i32, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLsv2i64, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLsv4i16, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLsv4i32, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLsv8i16, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLsv8i8, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLuv16i8, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLuv1i64, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLuv2i32, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLuv2i64, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLuv4i16, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLuv4i32, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLuv8i16, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHLuv8i8, ARM_INS_VRSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRNv2i32, ARM_INS_VRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRNv4i16, ARM_INS_VRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRNv8i8, ARM_INS_VRSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRsv16i8, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRsv1i64, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRsv2i32, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRsv2i64, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRsv4i16, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRsv4i32, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRsv8i16, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRsv8i8, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRuv16i8, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRuv1i64, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRuv2i32, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRuv2i64, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRuv4i16, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRuv4i32, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRuv8i16, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSHRuv8i8, ARM_INS_VRSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSQRTEd, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSQRTEfd, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSQRTEfq, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSQRTEhd, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSQRTEhq, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSQRTEq, ARM_INS_VRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSQRTSfd, ARM_INS_VRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSQRTSfq, ARM_INS_VRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSQRTShd, ARM_INS_VRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSQRTShq, ARM_INS_VRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAsv16i8, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAsv1i64, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAsv2i32, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAsv2i64, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAsv4i16, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAsv4i32, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAsv8i16, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAsv8i8, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAuv16i8, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAuv1i64, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAuv2i32, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAuv2i64, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAuv4i16, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAuv4i32, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAuv8i16, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSRAuv8i8, ARM_INS_VRSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSDOTD, ARM_INS_VSDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSDOTDI, ARM_INS_VSDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSDOTQ, ARM_INS_VSDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSDOTQI, ARM_INS_VSDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELEQD, ARM_INS_VSELEQ, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELEQH, ARM_INS_VSELEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELEQS, ARM_INS_VSELEQ, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELGED, ARM_INS_VSELGE, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELGEH, ARM_INS_VSELGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELGES, ARM_INS_VSELGE, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELGTD, ARM_INS_VSELGT, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELGTH, ARM_INS_VSELGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELGTS, ARM_INS_VSELGT, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELVSD, ARM_INS_VSELVS, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELVSH, ARM_INS_VSELVS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSELVSS, ARM_INS_VSELVS, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSETLNi16, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSETLNi32, ARM_INS_FMDHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSETLNi8, ARM_INS_VMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLLi16, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLLi32, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLLi8, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLLsv2i64, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLLsv4i32, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLLsv8i16, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLLuv2i64, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLLuv4i32, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLLuv8i16, ARM_INS_VSHLL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLiv16i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLiv1i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLiv2i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLiv2i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLiv4i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLiv4i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLiv8i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLiv8i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLsv16i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLsv1i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLsv2i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLsv2i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLsv4i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLsv4i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLsv8i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLsv8i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLuv16i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLuv1i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLuv2i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLuv2i64, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLuv4i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLuv4i32, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLuv8i16, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHLuv8i8, ARM_INS_VSHL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRNv2i32, ARM_INS_VSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRNv4i16, ARM_INS_VSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRNv8i8, ARM_INS_VSHRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRsv16i8, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRsv1i64, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRsv2i32, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRsv2i64, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRsv4i16, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRsv4i32, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRsv8i16, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRsv8i8, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRuv16i8, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRuv1i64, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRuv2i32, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRuv2i64, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRuv4i16, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRuv4i32, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRuv8i16, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHRuv8i8, ARM_INS_VSHR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHTOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHTOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSHTOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSITOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSITOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSITOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLIv16i8, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLIv1i64, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLIv2i32, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLIv2i64, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLIv4i16, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLIv4i32, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLIv8i16, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLIv8i8, ARM_INS_VSLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLTOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLTOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSLTOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSQRTD, ARM_INS_VSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSQRTH, ARM_INS_VSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSQRTS, ARM_INS_VSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAsv16i8, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAsv1i64, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAsv2i32, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAsv2i64, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAsv4i16, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAsv4i32, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAsv8i16, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAsv8i8, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAuv16i8, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAuv1i64, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAuv2i32, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAuv2i64, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAuv4i16, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAuv4i32, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAuv8i16, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRAuv8i8, ARM_INS_VSRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRIv16i8, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRIv1i64, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRIv2i32, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRIv2i64, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRIv4i16, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRIv4i32, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRIv8i16, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSRIv8i8, ARM_INS_VSRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNd16, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNd16_UPD, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNd32, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNd32_UPD, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNd8, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1LNd8_UPD, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d16, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d16Q, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d16Qwb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d16Qwb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d16T, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d16Twb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d16Twb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d16wb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d16wb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d32, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d32Q, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d32Qwb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d32Qwb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d32T, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d32Twb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d32Twb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d32wb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d32wb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d64, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d64Q, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d64Qwb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d64Qwb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d64T, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d64Twb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d64Twb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d64wb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d64wb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d8, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d8Q, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d8Qwb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d8Qwb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d8T, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d8Twb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d8Twb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d8wb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1d8wb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q16, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q16wb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q16wb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q32, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q32wb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q32wb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q64, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q64wb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q64wb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q8, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q8wb_fixed, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST1q8wb_register, ARM_INS_VST1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNd16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNd16_UPD, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNd32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNd32_UPD, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNd8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNd8_UPD, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNq16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNq16_UPD, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNq32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2LNq32_UPD, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2b16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2b16wb_fixed, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2b16wb_register, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2b32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2b32wb_fixed, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2b32wb_register, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2b8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2b8wb_fixed, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2b8wb_register, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2d16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2d16wb_fixed, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2d16wb_register, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2d32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2d32wb_fixed, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2d32wb_register, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2d8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2d8wb_fixed, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2d8wb_register, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2q16, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2q16wb_fixed, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2q16wb_register, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2q32, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2q32wb_fixed, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2q32wb_register, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2q8, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2q8wb_fixed, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST2q8wb_register, ARM_INS_VST2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNd16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNd16_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNd32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNd32_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNd8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNd8_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNq16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNq16_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNq32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3LNq32_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3d16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3d16_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3d32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3d32_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3d8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3d8_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3q16, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3q16_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3q32, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3q32_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3q8, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST3q8_UPD, ARM_INS_VST3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNd16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNd16_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNd32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNd32_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNd8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNd8_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNq16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNq16_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNq32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4LNq32_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4d16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4d16_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4d32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4d32_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4d8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4d8_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4q16, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4q16_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4q32, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4q32_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4q8, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VST4q8_UPD, ARM_INS_VST4, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSTMDDB_UPD, ARM_INS_VSTMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSTMDIA, ARM_INS_VSTMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSTMDIA_UPD, ARM_INS_VSTMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSTMSDB_UPD, ARM_INS_VSTMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSTMSIA, ARM_INS_VSTMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSTMSIA_UPD, ARM_INS_VSTMIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSTRD, ARM_INS_VSTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSTRH, ARM_INS_VSTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSTRS, ARM_INS_VSTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBD, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBH, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBHNv2i32, ARM_INS_VSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBHNv4i16, ARM_INS_VSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBHNv8i8, ARM_INS_VSUBHN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBLsv2i64, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBLsv4i32, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBLsv8i16, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBLuv2i64, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBLuv4i32, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBLuv8i16, ARM_INS_VSUBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBS, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBWsv2i64, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBWsv4i32, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBWsv8i16, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBWuv2i64, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBWuv4i32, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBWuv8i16, ARM_INS_VSUBW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBfd, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBfq, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBhd, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBhq, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBv16i8, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBv1i64, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBv2i32, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBv2i64, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBv4i16, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBv4i32, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBv8i16, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSUBv8i8, ARM_INS_VSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSWPd, ARM_INS_VSWP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VSWPq, ARM_INS_VSWP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTBL1, ARM_INS_VTBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTBL2, ARM_INS_VTBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTBL3, ARM_INS_VTBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTBL4, ARM_INS_VTBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTBX1, ARM_INS_VTBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTBX2, ARM_INS_VTBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTBX3, ARM_INS_VTBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTBX4, ARM_INS_VTBX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSHD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSHH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSHS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSIRD, ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSIRH, ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSIRS, ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSIZD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSIZH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSIZS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSLD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSLH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOSLS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOUHD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOUHH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOUHS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOUIRD, ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOUIRH, ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOUIRS, ARM_INS_VCVTR, +#ifndef CAPSTONE_DIET + { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOUIZD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOUIZH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOUIZS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOULD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOULH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VTOULS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTRNd16, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTRNd32, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTRNd8, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTRNq16, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTRNq32, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTRNq8, ARM_INS_VTRN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTSTv16i8, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTSTv2i32, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTSTv4i16, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTSTv4i32, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTSTv8i16, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VTSTv8i8, ARM_INS_VTST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VUDOTD, ARM_INS_VUDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VUDOTDI, ARM_INS_VUDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VUDOTQ, ARM_INS_VUDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VUDOTQI, ARM_INS_VUDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VUHTOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VUHTOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VUHTOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VUITOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VUITOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VUITOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VULTOD, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 +#endif +}, + +{ + ARM_VULTOH, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_VULTOS, ARM_INS_VCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 +#endif +}, + +{ + ARM_VUZPd16, ARM_INS_VUZP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VUZPd8, ARM_INS_VUZP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VUZPq16, ARM_INS_VUZP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VUZPq32, ARM_INS_VUZP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VUZPq8, ARM_INS_VUZP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VZIPd16, ARM_INS_VZIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VZIPd8, ARM_INS_VZIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VZIPq16, ARM_INS_VZIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VZIPq32, ARM_INS_VZIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_VZIPq8, ARM_INS_VZIP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysLDMDA, ARM_INS_LDMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysLDMDA_UPD, ARM_INS_LDMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysLDMDB, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysLDMDB_UPD, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysLDMIA, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysLDMIA_UPD, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysLDMIB, ARM_INS_LDMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysLDMIB_UPD, ARM_INS_LDMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysSTMDA, ARM_INS_STMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysSTMDA_UPD, ARM_INS_STMDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysSTMDB, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysSTMDB_UPD, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysSTMIA, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysSTMIA_UPD, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysSTMIB, ARM_INS_STMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_sysSTMIB_UPD, ARM_INS_STMIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ADCri, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ADCrr, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ADCrs, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ADDri, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ADDri12, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ADDrr, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ADDrs, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ADR, ARM_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ANDri, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ANDrr, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ANDrs, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ASRri, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ASRrr, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2B, ARM_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 +#endif +}, + +{ + ARM_t2BFC, ARM_INS_BFC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2BFI, ARM_INS_BFI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2BICri, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2BICrr, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2BICrs, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2BXJ, ARM_INS_BXJ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, ARM_GRP_PREV8, 0 }, 0, 1 +#endif +}, + +{ + ARM_t2Bcc, ARM_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 +#endif +}, + +{ + ARM_t2CDP, ARM_INS_CDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CDP2, ARM_INS_CDP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CLREX, ARM_INS_CLREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CLZ, ARM_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CMNri, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CMNzrr, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CMNzrs, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CMPri, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CMPrr, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CMPrs, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CPS1p, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CPS2p, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CPS3p, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CRC32B, ARM_INS_CRC32B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CRC32CB, ARM_INS_CRC32CB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CRC32CH, ARM_INS_CRC32CH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CRC32CW, ARM_INS_CRC32CW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CRC32H, ARM_INS_CRC32H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2CRC32W, ARM_INS_CRC32W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2DBG, ARM_INS_DBG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2DCPS1, ARM_INS_DCPS1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2DCPS2, ARM_INS_DCPS2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2DCPS3, ARM_INS_DCPS3, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2DMB, ARM_INS_DMB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2DSB, ARM_INS_DSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2EORri, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2EORrr, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2EORrs, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2HINT, ARM_INS_HINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2HVC, ARM_INS_HVC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ISB, ARM_INS_ISB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2IT, ARM_INS_IT, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_ITSTATE, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDA, ARM_INS_LDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDAB, ARM_INS_LDAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDAEX, ARM_INS_LDAEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDAEXB, ARM_INS_LDAEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDAEXD, ARM_INS_LDAEXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDAEXH, ARM_INS_LDAEXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDAH, ARM_INS_LDAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC2L_OPTION, ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC2L_POST, ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC2L_PRE, ARM_INS_LDC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC2_OFFSET, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC2_OPTION, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC2_POST, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC2_PRE, ARM_INS_LDC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDCL_OFFSET, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDCL_OPTION, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDCL_POST, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDCL_PRE, ARM_INS_LDCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC_OFFSET, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC_OPTION, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC_POST, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDC_PRE, ARM_INS_LDC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDMDB, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDMDB_UPD, ARM_INS_LDMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDMIA, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDMIA_UPD, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRBT, ARM_INS_LDRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRB_POST, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRB_PRE, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRBi12, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRBi8, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRBpci, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRBs, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRD_POST, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRD_PRE, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRDi8, ARM_INS_LDRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDREX, ARM_INS_LDREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDREXB, ARM_INS_LDREXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDREXD, ARM_INS_LDREXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDREXH, ARM_INS_LDREXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRHT, ARM_INS_LDRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRH_POST, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRH_PRE, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRHi12, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRHi8, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRHpci, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRHs, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSBT, ARM_INS_LDRSBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSB_POST, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSB_PRE, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSBi12, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSBi8, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSBpci, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSBs, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSHT, ARM_INS_LDRSHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSH_POST, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSH_PRE, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSHi12, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSHi8, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSHpci, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRSHs, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRT, ARM_INS_LDRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDR_POST, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDR_PRE, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRi12, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRi8, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRpci, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LDRs, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LSLri, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LSLrr, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LSRri, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2LSRrr, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MCR, ARM_INS_MCR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MCR2, ARM_INS_MCR2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MCRR, ARM_INS_MCRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MCRR2, ARM_INS_MCRR2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MLA, ARM_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MLS, ARM_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MOVTi16, ARM_INS_MOVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MOVi, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MOVi16, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MOVr, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MOVsra_flag, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MOVsrl_flag, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MRC, ARM_INS_MRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MRC2, ARM_INS_MRC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MRRC, ARM_INS_MRRC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MRRC2, ARM_INS_MRRC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MRS_AR, ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MRS_M, ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MRSbanked, ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MRSsys_AR, ARM_INS_MRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MSR_AR, ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MSR_M, ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MSRbanked, ARM_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MUL, ARM_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MVNi, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MVNr, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2MVNs, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ORNri, ARM_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ORNrr, ARM_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ORNrs, ARM_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ORRri, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ORRrr, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2ORRrs, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PKHBT, ARM_INS_PKHBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PKHTB, ARM_INS_PKHTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLDWi12, ARM_INS_PLDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLDWi8, ARM_INS_PLDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLDWs, ARM_INS_PLDW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLDi12, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLDi8, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLDpci, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLDs, ARM_INS_PLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLIi12, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLIi8, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLIpci, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2PLIs, ARM_INS_PLI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2QADD, ARM_INS_QADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2QADD16, ARM_INS_QADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2QADD8, ARM_INS_QADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2QASX, ARM_INS_QASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2QDADD, ARM_INS_QDADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2QDSUB, ARM_INS_QDSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2QSAX, ARM_INS_QSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2QSUB, ARM_INS_QSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2QSUB16, ARM_INS_QSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2QSUB8, ARM_INS_QSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RBIT, ARM_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2REV, ARM_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2REV16, ARM_INS_REV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2REVSH, ARM_INS_REVSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RFEDB, ARM_INS_RFEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RFEDBW, ARM_INS_RFEDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RFEIA, ARM_INS_RFEIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RFEIAW, ARM_INS_RFEIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RORri, ARM_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RORrr, ARM_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RRX, ARM_INS_RRX, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RSBri, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RSBrr, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2RSBrs, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SADD16, ARM_INS_SADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SADD8, ARM_INS_SADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SASX, ARM_INS_SASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SBCri, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SBCrr, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SBCrs, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SBFX, ARM_INS_SBFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SDIV, ARM_INS_SDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SEL, ARM_INS_SEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SETPAN, ARM_INS_SETPAN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SG, ARM_INS_SG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SHADD16, ARM_INS_SHADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SHADD8, ARM_INS_SHADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SHASX, ARM_INS_SHASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SHSAX, ARM_INS_SHSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SHSUB16, ARM_INS_SHSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SHSUB8, ARM_INS_SHSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMC, ARM_INS_SMC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLABB, ARM_INS_SMLABB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLABT, ARM_INS_SMLABT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLAD, ARM_INS_SMLAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLADX, ARM_INS_SMLADX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLAL, ARM_INS_SMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLALBB, ARM_INS_SMLALBB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLALBT, ARM_INS_SMLALBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLALD, ARM_INS_SMLALD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLALDX, ARM_INS_SMLALDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLALTB, ARM_INS_SMLALTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLALTT, ARM_INS_SMLALTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLATB, ARM_INS_SMLATB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLATT, ARM_INS_SMLATT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLAWB, ARM_INS_SMLAWB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLAWT, ARM_INS_SMLAWT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLSD, ARM_INS_SMLSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLSDX, ARM_INS_SMLSDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLSLD, ARM_INS_SMLSLD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMLSLDX, ARM_INS_SMLSLDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMMLA, ARM_INS_SMMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMMLAR, ARM_INS_SMMLAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMMLS, ARM_INS_SMMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMMLSR, ARM_INS_SMMLSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMMUL, ARM_INS_SMMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMMULR, ARM_INS_SMMULR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMUAD, ARM_INS_SMUAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMUADX, ARM_INS_SMUADX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMULBB, ARM_INS_SMULBB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMULBT, ARM_INS_SMULBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMULL, ARM_INS_SMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMULTB, ARM_INS_SMULTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMULTT, ARM_INS_SMULTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMULWB, ARM_INS_SMULWB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMULWT, ARM_INS_SMULWT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMUSD, ARM_INS_SMUSD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SMUSDX, ARM_INS_SMUSDX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SRSDB, ARM_INS_SRSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SRSDB_UPD, ARM_INS_SRSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SRSIA, ARM_INS_SRSIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SRSIA_UPD, ARM_INS_SRSIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SSAT, ARM_INS_SSAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SSAT16, ARM_INS_SSAT16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SSAX, ARM_INS_SSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SSUB16, ARM_INS_SSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SSUB8, ARM_INS_SSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC2L_OFFSET, ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC2L_OPTION, ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC2L_POST, ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC2L_PRE, ARM_INS_STC2L, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC2_OFFSET, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC2_OPTION, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC2_POST, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC2_PRE, ARM_INS_STC2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STCL_OFFSET, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STCL_OPTION, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STCL_POST, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STCL_PRE, ARM_INS_STCL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC_OFFSET, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC_OPTION, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC_POST, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STC_PRE, ARM_INS_STC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STL, ARM_INS_STL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STLB, ARM_INS_STLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STLEX, ARM_INS_STLEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STLEXB, ARM_INS_STLEXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STLEXD, ARM_INS_STLEXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STLEXH, ARM_INS_STLEXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STLH, ARM_INS_STLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STMDB, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STMDB_UPD, ARM_INS_STMDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STMIA, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STMIA_UPD, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRBT, ARM_INS_STRBT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRB_POST, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRB_PRE, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRBi12, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRBi8, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRBs, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRD_POST, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRD_PRE, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRDi8, ARM_INS_STRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STREX, ARM_INS_STREX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STREXB, ARM_INS_STREXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STREXD, ARM_INS_STREXD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STREXH, ARM_INS_STREXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRHT, ARM_INS_STRHT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRH_POST, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRH_PRE, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRHi12, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRHi8, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRHs, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRT, ARM_INS_STRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STR_POST, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STR_PRE, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRi12, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRi8, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2STRs, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SUBS_PC_LR, ARM_INS_SUBS, +#ifndef CAPSTONE_DIET + { ARM_REG_SPSR, ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_REG_CPSR, ARM_REG_PC, 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SUBri, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SUBri12, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SUBrr, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SUBrs, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SXTAB, ARM_INS_SXTAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SXTAB16, ARM_INS_SXTAB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SXTAH, ARM_INS_SXTAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SXTB, ARM_INS_SXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SXTB16, ARM_INS_SXTB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_T2EXTRACTPACK, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2SXTH, ARM_INS_SXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TBB, ARM_INS_TBB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 +#endif +}, + +{ + ARM_t2TBH, ARM_INS_TBH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 +#endif +}, + +{ + ARM_t2TEQri, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TEQrr, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TEQrs, ARM_INS_TEQ, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TSB, ARM_INS_TSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TSTri, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TSTrr, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TSTrs, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TT, ARM_INS_TT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TTA, ARM_INS_TTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TTAT, ARM_INS_TTAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2TTT, ARM_INS_TTT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UADD16, ARM_INS_UADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UADD8, ARM_INS_UADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UASX, ARM_INS_UASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UBFX, ARM_INS_UBFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UDF, ARM_INS_UDF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UDIV, ARM_INS_UDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UHADD16, ARM_INS_UHADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UHADD8, ARM_INS_UHADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UHASX, ARM_INS_UHASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UHSAX, ARM_INS_UHSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UHSUB16, ARM_INS_UHSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UHSUB8, ARM_INS_UHSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UMAAL, ARM_INS_UMAAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UMLAL, ARM_INS_UMLAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UMULL, ARM_INS_UMULL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UQADD16, ARM_INS_UQADD16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UQADD8, ARM_INS_UQADD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UQASX, ARM_INS_UQASX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UQSAX, ARM_INS_UQSAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UQSUB16, ARM_INS_UQSUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UQSUB8, ARM_INS_UQSUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2USAD8, ARM_INS_USAD8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2USADA8, ARM_INS_USADA8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2USAT, ARM_INS_USAT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2USAT16, ARM_INS_USAT16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2USAX, ARM_INS_USAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2USUB16, ARM_INS_USUB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2USUB8, ARM_INS_USUB8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UXTAB, ARM_INS_UXTAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UXTAB16, ARM_INS_UXTAB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UXTAH, ARM_INS_UXTAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UXTB, ARM_INS_UXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UXTB16, ARM_INS_UXTB16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_t2UXTH, ARM_INS_UXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 +#endif +}, + +{ + ARM_tADC, ARM_INS_ADC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tADDhirr, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tADDi3, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tADDi8, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tADDrSP, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tADDrSPi, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tADDrr, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tADDspi, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tADDspr, ARM_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tADR, ARM_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tAND, ARM_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tASRri, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tASRrr, ARM_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tB, ARM_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 +#endif +}, + +{ + ARM_tBIC, ARM_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tBKPT, ARM_INS_BKPT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tBL, ARM_INS_BL, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_CALL, 0 }, 1, 0 +#endif +}, + +{ + ARM_tBLXNSr, ARM_INS_BLXNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_tBLXi, ARM_INS_BLX, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, ARM_GRP_CALL, 0 }, 1, 0 +#endif +}, + +{ + ARM_tBLXr, ARM_INS_BLX, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_CALL, 0 }, 0, 1 +#endif +}, + +{ + ARM_tBX, ARM_INS_BX, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_THUMB, 0 }, 0, 1 +#endif +}, + +{ + ARM_tBXNS, ARM_INS_BXNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + ARM_tBcc, ARM_INS_B, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 +#endif +}, + +{ + ARM_tCBNZ, ARM_INS_CBNZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 +#endif +}, + +{ + ARM_tCBZ, ARM_INS_CBZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 +#endif +}, + +{ + ARM_tCMNz, ARM_INS_CMN, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tCMPhir, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tCMPi8, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tCMPr, ARM_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tCPS, ARM_INS_CPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tEOR, ARM_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tHINT, ARM_INS_HINT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6M, 0 }, 0, 0 +#endif +}, + +{ + ARM_tHLT, ARM_INS_HLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDMIA, ARM_INS_LDM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRBi, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRBr, ARM_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRHi, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRHr, ARM_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRSB, ARM_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRSH, ARM_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRi, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRpci, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRr, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLDRspi, ARM_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLSLri, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLSLrr, ARM_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLSRri, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tLSRrr, ARM_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tMOVSr, ARM_INS_MOVS, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tMOVi8, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tMOVr, ARM_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tMUL, ARM_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tMVN, ARM_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tORR, ARM_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tPOP, ARM_INS_POP, +#ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tPUSH, ARM_INS_PUSH, +#ifndef CAPSTONE_DIET + { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tREV, ARM_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_tREV16, ARM_INS_REV16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_tREVSH, ARM_INS_REVSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_tROR, ARM_INS_ROR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tRSB, ARM_INS_RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSBC, ARM_INS_SBC, +#ifndef CAPSTONE_DIET + { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSETEND, ARM_INS_SETEND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6, ARM_GRP_NOTMCLASS, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSTMIA_UPD, ARM_INS_STM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSTRBi, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSTRBr, ARM_INS_STRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSTRHi, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSTRHr, ARM_INS_STRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSTRi, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSTRr, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSTRspi, ARM_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSUBi3, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSUBi8, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSUBrr, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSUBspi, ARM_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSVC, ARM_INS_SVC, +#ifndef CAPSTONE_DIET + { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_INT, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSXTB, ARM_INS_SXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_tSXTH, ARM_INS_SXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_tTRAP, ARM_INS_TRAP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 +#endif +}, + +{ + ARM_tTST, ARM_INS_TST, +#ifndef CAPSTONE_DIET + { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 +#endif +}, + +{ + ARM_tUDF, ARM_INS_UDF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 +#endif +}, + +{ + ARM_tUXTB, ARM_INS_UXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + +{ + ARM_tUXTH, ARM_INS_UXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 +#endif +}, + diff --git a/capstone/arch/ARM/ARMMappingInsnName.inc b/capstone/arch/ARM/ARMMappingInsnName.inc new file mode 100644 index 000000000..405d03fbb --- /dev/null +++ b/capstone/arch/ARM/ARMMappingInsnName.inc @@ -0,0 +1,475 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + + "adc", // ARM_INS_ADC, + "add", // ARM_INS_ADD, + "addw", // ARM_INS_ADDW, + "adr", // ARM_INS_ADR, + "aesd", // ARM_INS_AESD, + "aese", // ARM_INS_AESE, + "aesimc", // ARM_INS_AESIMC, + "aesmc", // ARM_INS_AESMC, + "and", // ARM_INS_AND, + "asr", // ARM_INS_ASR, + "b", // ARM_INS_B, + "bfc", // ARM_INS_BFC, + "bfi", // ARM_INS_BFI, + "bic", // ARM_INS_BIC, + "bkpt", // ARM_INS_BKPT, + "bl", // ARM_INS_BL, + "blx", // ARM_INS_BLX, + "blxns", // ARM_INS_BLXNS, + "bx", // ARM_INS_BX, + "bxj", // ARM_INS_BXJ, + "bxns", // ARM_INS_BXNS, + "cbnz", // ARM_INS_CBNZ, + "cbz", // ARM_INS_CBZ, + "cdp", // ARM_INS_CDP, + "cdp2", // ARM_INS_CDP2, + "clrex", // ARM_INS_CLREX, + "clz", // ARM_INS_CLZ, + "cmn", // ARM_INS_CMN, + "cmp", // ARM_INS_CMP, + "cps", // ARM_INS_CPS, + "crc32b", // ARM_INS_CRC32B, + "crc32cb", // ARM_INS_CRC32CB, + "crc32ch", // ARM_INS_CRC32CH, + "crc32cw", // ARM_INS_CRC32CW, + "crc32h", // ARM_INS_CRC32H, + "crc32w", // ARM_INS_CRC32W, + "csdb", // ARM_INS_CSDB, + "dbg", // ARM_INS_DBG, + "dcps1", // ARM_INS_DCPS1, + "dcps2", // ARM_INS_DCPS2, + "dcps3", // ARM_INS_DCPS3, + "dfb", // ARM_INS_DFB, + "dmb", // ARM_INS_DMB, + "dsb", // ARM_INS_DSB, + "eor", // ARM_INS_EOR, + "eret", // ARM_INS_ERET, + "esb", // ARM_INS_ESB, + "faddd", // ARM_INS_FADDD, + "fadds", // ARM_INS_FADDS, + "fcmpzd", // ARM_INS_FCMPZD, + "fcmpzs", // ARM_INS_FCMPZS, + "fconstd", // ARM_INS_FCONSTD, + "fconsts", // ARM_INS_FCONSTS, + "fldmdbx", // ARM_INS_FLDMDBX, + "fldmiax", // ARM_INS_FLDMIAX, + "fmdhr", // ARM_INS_FMDHR, + "fmdlr", // ARM_INS_FMDLR, + "fmstat", // ARM_INS_FMSTAT, + "fstmdbx", // ARM_INS_FSTMDBX, + "fstmiax", // ARM_INS_FSTMIAX, + "fsubd", // ARM_INS_FSUBD, + "fsubs", // ARM_INS_FSUBS, + "hint", // ARM_INS_HINT, + "hlt", // ARM_INS_HLT, + "hvc", // ARM_INS_HVC, + "isb", // ARM_INS_ISB, + "it", // ARM_INS_IT, + "lda", // ARM_INS_LDA, + "ldab", // ARM_INS_LDAB, + "ldaex", // ARM_INS_LDAEX, + "ldaexb", // ARM_INS_LDAEXB, + "ldaexd", // ARM_INS_LDAEXD, + "ldaexh", // ARM_INS_LDAEXH, + "ldah", // ARM_INS_LDAH, + "ldc", // ARM_INS_LDC, + "ldc2", // ARM_INS_LDC2, + "ldc2l", // ARM_INS_LDC2L, + "ldcl", // ARM_INS_LDCL, + "ldm", // ARM_INS_LDM, + "ldmda", // ARM_INS_LDMDA, + "ldmdb", // ARM_INS_LDMDB, + "ldmib", // ARM_INS_LDMIB, + "ldr", // ARM_INS_LDR, + "ldrb", // ARM_INS_LDRB, + "ldrbt", // ARM_INS_LDRBT, + "ldrd", // ARM_INS_LDRD, + "ldrex", // ARM_INS_LDREX, + "ldrexb", // ARM_INS_LDREXB, + "ldrexd", // ARM_INS_LDREXD, + "ldrexh", // ARM_INS_LDREXH, + "ldrh", // ARM_INS_LDRH, + "ldrht", // ARM_INS_LDRHT, + "ldrsb", // ARM_INS_LDRSB, + "ldrsbt", // ARM_INS_LDRSBT, + "ldrsh", // ARM_INS_LDRSH, + "ldrsht", // ARM_INS_LDRSHT, + "ldrt", // ARM_INS_LDRT, + "lsl", // ARM_INS_LSL, + "lsr", // ARM_INS_LSR, + "mcr", // ARM_INS_MCR, + "mcr2", // ARM_INS_MCR2, + "mcrr", // ARM_INS_MCRR, + "mcrr2", // ARM_INS_MCRR2, + "mla", // ARM_INS_MLA, + "mls", // ARM_INS_MLS, + "mov", // ARM_INS_MOV, + "movs", // ARM_INS_MOVS, + "movt", // ARM_INS_MOVT, + "movw", // ARM_INS_MOVW, + "mrc", // ARM_INS_MRC, + "mrc2", // ARM_INS_MRC2, + "mrrc", // ARM_INS_MRRC, + "mrrc2", // ARM_INS_MRRC2, + "mrs", // ARM_INS_MRS, + "msr", // ARM_INS_MSR, + "mul", // ARM_INS_MUL, + "mvn", // ARM_INS_MVN, + "neg", // ARM_INS_NEG, + "nop", // ARM_INS_NOP, + "orn", // ARM_INS_ORN, + "orr", // ARM_INS_ORR, + "pkhbt", // ARM_INS_PKHBT, + "pkhtb", // ARM_INS_PKHTB, + "pld", // ARM_INS_PLD, + "pldw", // ARM_INS_PLDW, + "pli", // ARM_INS_PLI, + "pop", // ARM_INS_POP, + "push", // ARM_INS_PUSH, + "qadd", // ARM_INS_QADD, + "qadd16", // ARM_INS_QADD16, + "qadd8", // ARM_INS_QADD8, + "qasx", // ARM_INS_QASX, + "qdadd", // ARM_INS_QDADD, + "qdsub", // ARM_INS_QDSUB, + "qsax", // ARM_INS_QSAX, + "qsub", // ARM_INS_QSUB, + "qsub16", // ARM_INS_QSUB16, + "qsub8", // ARM_INS_QSUB8, + "rbit", // ARM_INS_RBIT, + "rev", // ARM_INS_REV, + "rev16", // ARM_INS_REV16, + "revsh", // ARM_INS_REVSH, + "rfeda", // ARM_INS_RFEDA, + "rfedb", // ARM_INS_RFEDB, + "rfeia", // ARM_INS_RFEIA, + "rfeib", // ARM_INS_RFEIB, + "ror", // ARM_INS_ROR, + "rrx", // ARM_INS_RRX, + "rsb", // ARM_INS_RSB, + "rsc", // ARM_INS_RSC, + "sadd16", // ARM_INS_SADD16, + "sadd8", // ARM_INS_SADD8, + "sasx", // ARM_INS_SASX, + "sbc", // ARM_INS_SBC, + "sbfx", // ARM_INS_SBFX, + "sdiv", // ARM_INS_SDIV, + "sel", // ARM_INS_SEL, + "setend", // ARM_INS_SETEND, + "setpan", // ARM_INS_SETPAN, + "sev", // ARM_INS_SEV, + "sevl", // ARM_INS_SEVL, + "sg", // ARM_INS_SG, + "sha1c", // ARM_INS_SHA1C, + "sha1h", // ARM_INS_SHA1H, + "sha1m", // ARM_INS_SHA1M, + "sha1p", // ARM_INS_SHA1P, + "sha1su0", // ARM_INS_SHA1SU0, + "sha1su1", // ARM_INS_SHA1SU1, + "sha256h", // ARM_INS_SHA256H, + "sha256h2", // ARM_INS_SHA256H2, + "sha256su0", // ARM_INS_SHA256SU0, + "sha256su1", // ARM_INS_SHA256SU1, + "shadd16", // ARM_INS_SHADD16, + "shadd8", // ARM_INS_SHADD8, + "shasx", // ARM_INS_SHASX, + "shsax", // ARM_INS_SHSAX, + "shsub16", // ARM_INS_SHSUB16, + "shsub8", // ARM_INS_SHSUB8, + "smc", // ARM_INS_SMC, + "smlabb", // ARM_INS_SMLABB, + "smlabt", // ARM_INS_SMLABT, + "smlad", // ARM_INS_SMLAD, + "smladx", // ARM_INS_SMLADX, + "smlal", // ARM_INS_SMLAL, + "smlalbb", // ARM_INS_SMLALBB, + "smlalbt", // ARM_INS_SMLALBT, + "smlald", // ARM_INS_SMLALD, + "smlaldx", // ARM_INS_SMLALDX, + "smlaltb", // ARM_INS_SMLALTB, + "smlaltt", // ARM_INS_SMLALTT, + "smlatb", // ARM_INS_SMLATB, + "smlatt", // ARM_INS_SMLATT, + "smlawb", // ARM_INS_SMLAWB, + "smlawt", // ARM_INS_SMLAWT, + "smlsd", // ARM_INS_SMLSD, + "smlsdx", // ARM_INS_SMLSDX, + "smlsld", // ARM_INS_SMLSLD, + "smlsldx", // ARM_INS_SMLSLDX, + "smmla", // ARM_INS_SMMLA, + "smmlar", // ARM_INS_SMMLAR, + "smmls", // ARM_INS_SMMLS, + "smmlsr", // ARM_INS_SMMLSR, + "smmul", // ARM_INS_SMMUL, + "smmulr", // ARM_INS_SMMULR, + "smuad", // ARM_INS_SMUAD, + "smuadx", // ARM_INS_SMUADX, + "smulbb", // ARM_INS_SMULBB, + "smulbt", // ARM_INS_SMULBT, + "smull", // ARM_INS_SMULL, + "smultb", // ARM_INS_SMULTB, + "smultt", // ARM_INS_SMULTT, + "smulwb", // ARM_INS_SMULWB, + "smulwt", // ARM_INS_SMULWT, + "smusd", // ARM_INS_SMUSD, + "smusdx", // ARM_INS_SMUSDX, + "srsda", // ARM_INS_SRSDA, + "srsdb", // ARM_INS_SRSDB, + "srsia", // ARM_INS_SRSIA, + "srsib", // ARM_INS_SRSIB, + "ssat", // ARM_INS_SSAT, + "ssat16", // ARM_INS_SSAT16, + "ssax", // ARM_INS_SSAX, + "ssub16", // ARM_INS_SSUB16, + "ssub8", // ARM_INS_SSUB8, + "stc", // ARM_INS_STC, + "stc2", // ARM_INS_STC2, + "stc2l", // ARM_INS_STC2L, + "stcl", // ARM_INS_STCL, + "stl", // ARM_INS_STL, + "stlb", // ARM_INS_STLB, + "stlex", // ARM_INS_STLEX, + "stlexb", // ARM_INS_STLEXB, + "stlexd", // ARM_INS_STLEXD, + "stlexh", // ARM_INS_STLEXH, + "stlh", // ARM_INS_STLH, + "stm", // ARM_INS_STM, + "stmda", // ARM_INS_STMDA, + "stmdb", // ARM_INS_STMDB, + "stmib", // ARM_INS_STMIB, + "str", // ARM_INS_STR, + "strb", // ARM_INS_STRB, + "strbt", // ARM_INS_STRBT, + "strd", // ARM_INS_STRD, + "strex", // ARM_INS_STREX, + "strexb", // ARM_INS_STREXB, + "strexd", // ARM_INS_STREXD, + "strexh", // ARM_INS_STREXH, + "strh", // ARM_INS_STRH, + "strht", // ARM_INS_STRHT, + "strt", // ARM_INS_STRT, + "sub", // ARM_INS_SUB, + "subs", // ARM_INS_SUBS, + "subw", // ARM_INS_SUBW, + "svc", // ARM_INS_SVC, + "swp", // ARM_INS_SWP, + "swpb", // ARM_INS_SWPB, + "sxtab", // ARM_INS_SXTAB, + "sxtab16", // ARM_INS_SXTAB16, + "sxtah", // ARM_INS_SXTAH, + "sxtb", // ARM_INS_SXTB, + "sxtb16", // ARM_INS_SXTB16, + "sxth", // ARM_INS_SXTH, + "tbb", // ARM_INS_TBB, + "tbh", // ARM_INS_TBH, + "teq", // ARM_INS_TEQ, + "trap", // ARM_INS_TRAP, + "tsb", // ARM_INS_TSB, + "tst", // ARM_INS_TST, + "tt", // ARM_INS_TT, + "tta", // ARM_INS_TTA, + "ttat", // ARM_INS_TTAT, + "ttt", // ARM_INS_TTT, + "uadd16", // ARM_INS_UADD16, + "uadd8", // ARM_INS_UADD8, + "uasx", // ARM_INS_UASX, + "ubfx", // ARM_INS_UBFX, + "udf", // ARM_INS_UDF, + "udiv", // ARM_INS_UDIV, + "uhadd16", // ARM_INS_UHADD16, + "uhadd8", // ARM_INS_UHADD8, + "uhasx", // ARM_INS_UHASX, + "uhsax", // ARM_INS_UHSAX, + "uhsub16", // ARM_INS_UHSUB16, + "uhsub8", // ARM_INS_UHSUB8, + "umaal", // ARM_INS_UMAAL, + "umlal", // ARM_INS_UMLAL, + "umull", // ARM_INS_UMULL, + "uqadd16", // ARM_INS_UQADD16, + "uqadd8", // ARM_INS_UQADD8, + "uqasx", // ARM_INS_UQASX, + "uqsax", // ARM_INS_UQSAX, + "uqsub16", // ARM_INS_UQSUB16, + "uqsub8", // ARM_INS_UQSUB8, + "usad8", // ARM_INS_USAD8, + "usada8", // ARM_INS_USADA8, + "usat", // ARM_INS_USAT, + "usat16", // ARM_INS_USAT16, + "usax", // ARM_INS_USAX, + "usub16", // ARM_INS_USUB16, + "usub8", // ARM_INS_USUB8, + "uxtab", // ARM_INS_UXTAB, + "uxtab16", // ARM_INS_UXTAB16, + "uxtah", // ARM_INS_UXTAH, + "uxtb", // ARM_INS_UXTB, + "uxtb16", // ARM_INS_UXTB16, + "uxth", // ARM_INS_UXTH, + "vaba", // ARM_INS_VABA, + "vabal", // ARM_INS_VABAL, + "vabd", // ARM_INS_VABD, + "vabdl", // ARM_INS_VABDL, + "vabs", // ARM_INS_VABS, + "vacge", // ARM_INS_VACGE, + "vacgt", // ARM_INS_VACGT, + "vacle", // ARM_INS_VACLE, + "vaclt", // ARM_INS_VACLT, + "vadd", // ARM_INS_VADD, + "vaddhn", // ARM_INS_VADDHN, + "vaddl", // ARM_INS_VADDL, + "vaddw", // ARM_INS_VADDW, + "vand", // ARM_INS_VAND, + "vbic", // ARM_INS_VBIC, + "vbif", // ARM_INS_VBIF, + "vbit", // ARM_INS_VBIT, + "vbsl", // ARM_INS_VBSL, + "vcadd", // ARM_INS_VCADD, + "vceq", // ARM_INS_VCEQ, + "vcge", // ARM_INS_VCGE, + "vcgt", // ARM_INS_VCGT, + "vcle", // ARM_INS_VCLE, + "vcls", // ARM_INS_VCLS, + "vclt", // ARM_INS_VCLT, + "vclz", // ARM_INS_VCLZ, + "vcmla", // ARM_INS_VCMLA, + "vcmp", // ARM_INS_VCMP, + "vcmpe", // ARM_INS_VCMPE, + "vcnt", // ARM_INS_VCNT, + "vcvt", // ARM_INS_VCVT, + "vcvta", // ARM_INS_VCVTA, + "vcvtb", // ARM_INS_VCVTB, + "vcvtm", // ARM_INS_VCVTM, + "vcvtn", // ARM_INS_VCVTN, + "vcvtp", // ARM_INS_VCVTP, + "vcvtr", // ARM_INS_VCVTR, + "vcvtt", // ARM_INS_VCVTT, + "vdiv", // ARM_INS_VDIV, + "vdup", // ARM_INS_VDUP, + "veor", // ARM_INS_VEOR, + "vext", // ARM_INS_VEXT, + "vfma", // ARM_INS_VFMA, + "vfms", // ARM_INS_VFMS, + "vfnma", // ARM_INS_VFNMA, + "vfnms", // ARM_INS_VFNMS, + "vhadd", // ARM_INS_VHADD, + "vhsub", // ARM_INS_VHSUB, + "vins", // ARM_INS_VINS, + "vjcvt", // ARM_INS_VJCVT, + "vld1", // ARM_INS_VLD1, + "vld2", // ARM_INS_VLD2, + "vld3", // ARM_INS_VLD3, + "vld4", // ARM_INS_VLD4, + "vldmdb", // ARM_INS_VLDMDB, + "vldmia", // ARM_INS_VLDMIA, + "vldr", // ARM_INS_VLDR, + "vlldm", // ARM_INS_VLLDM, + "vlstm", // ARM_INS_VLSTM, + "vmax", // ARM_INS_VMAX, + "vmaxnm", // ARM_INS_VMAXNM, + "vmin", // ARM_INS_VMIN, + "vminnm", // ARM_INS_VMINNM, + "vmla", // ARM_INS_VMLA, + "vmlal", // ARM_INS_VMLAL, + "vmls", // ARM_INS_VMLS, + "vmlsl", // ARM_INS_VMLSL, + "vmov", // ARM_INS_VMOV, + "vmovl", // ARM_INS_VMOVL, + "vmovn", // ARM_INS_VMOVN, + "vmovx", // ARM_INS_VMOVX, + "vmrs", // ARM_INS_VMRS, + "vmsr", // ARM_INS_VMSR, + "vmul", // ARM_INS_VMUL, + "vmull", // ARM_INS_VMULL, + "vmvn", // ARM_INS_VMVN, + "vneg", // ARM_INS_VNEG, + "vnmla", // ARM_INS_VNMLA, + "vnmls", // ARM_INS_VNMLS, + "vnmul", // ARM_INS_VNMUL, + "vorn", // ARM_INS_VORN, + "vorr", // ARM_INS_VORR, + "vpadal", // ARM_INS_VPADAL, + "vpadd", // ARM_INS_VPADD, + "vpaddl", // ARM_INS_VPADDL, + "vpmax", // ARM_INS_VPMAX, + "vpmin", // ARM_INS_VPMIN, + "vpop", // ARM_INS_VPOP, + "vpush", // ARM_INS_VPUSH, + "vqabs", // ARM_INS_VQABS, + "vqadd", // ARM_INS_VQADD, + "vqdmlal", // ARM_INS_VQDMLAL, + "vqdmlsl", // ARM_INS_VQDMLSL, + "vqdmulh", // ARM_INS_VQDMULH, + "vqdmull", // ARM_INS_VQDMULL, + "vqmovn", // ARM_INS_VQMOVN, + "vqmovun", // ARM_INS_VQMOVUN, + "vqneg", // ARM_INS_VQNEG, + "vqrdmlah", // ARM_INS_VQRDMLAH, + "vqrdmlsh", // ARM_INS_VQRDMLSH, + "vqrdmulh", // ARM_INS_VQRDMULH, + "vqrshl", // ARM_INS_VQRSHL, + "vqrshrn", // ARM_INS_VQRSHRN, + "vqrshrun", // ARM_INS_VQRSHRUN, + "vqshl", // ARM_INS_VQSHL, + "vqshlu", // ARM_INS_VQSHLU, + "vqshrn", // ARM_INS_VQSHRN, + "vqshrun", // ARM_INS_VQSHRUN, + "vqsub", // ARM_INS_VQSUB, + "vraddhn", // ARM_INS_VRADDHN, + "vrecpe", // ARM_INS_VRECPE, + "vrecps", // ARM_INS_VRECPS, + "vrev16", // ARM_INS_VREV16, + "vrev32", // ARM_INS_VREV32, + "vrev64", // ARM_INS_VREV64, + "vrhadd", // ARM_INS_VRHADD, + "vrinta", // ARM_INS_VRINTA, + "vrintm", // ARM_INS_VRINTM, + "vrintn", // ARM_INS_VRINTN, + "vrintp", // ARM_INS_VRINTP, + "vrintr", // ARM_INS_VRINTR, + "vrintx", // ARM_INS_VRINTX, + "vrintz", // ARM_INS_VRINTZ, + "vrshl", // ARM_INS_VRSHL, + "vrshr", // ARM_INS_VRSHR, + "vrshrn", // ARM_INS_VRSHRN, + "vrsqrte", // ARM_INS_VRSQRTE, + "vrsqrts", // ARM_INS_VRSQRTS, + "vrsra", // ARM_INS_VRSRA, + "vrsubhn", // ARM_INS_VRSUBHN, + "vsdot", // ARM_INS_VSDOT, + "vseleq", // ARM_INS_VSELEQ, + "vselge", // ARM_INS_VSELGE, + "vselgt", // ARM_INS_VSELGT, + "vselvs", // ARM_INS_VSELVS, + "vshl", // ARM_INS_VSHL, + "vshll", // ARM_INS_VSHLL, + "vshr", // ARM_INS_VSHR, + "vshrn", // ARM_INS_VSHRN, + "vsli", // ARM_INS_VSLI, + "vsqrt", // ARM_INS_VSQRT, + "vsra", // ARM_INS_VSRA, + "vsri", // ARM_INS_VSRI, + "vst1", // ARM_INS_VST1, + "vst2", // ARM_INS_VST2, + "vst3", // ARM_INS_VST3, + "vst4", // ARM_INS_VST4, + "vstmdb", // ARM_INS_VSTMDB, + "vstmia", // ARM_INS_VSTMIA, + "vstr", // ARM_INS_VSTR, + "vsub", // ARM_INS_VSUB, + "vsubhn", // ARM_INS_VSUBHN, + "vsubl", // ARM_INS_VSUBL, + "vsubw", // ARM_INS_VSUBW, + "vswp", // ARM_INS_VSWP, + "vtbl", // ARM_INS_VTBL, + "vtbx", // ARM_INS_VTBX, + "vtrn", // ARM_INS_VTRN, + "vtst", // ARM_INS_VTST, + "vudot", // ARM_INS_VUDOT, + "vuzp", // ARM_INS_VUZP, + "vzip", // ARM_INS_VZIP, + "wfe", // ARM_INS_WFE, + "wfi", // ARM_INS_WFI, + "yield", // ARM_INS_YIELD, diff --git a/capstone/arch/ARM/ARMMappingInsnOp.inc b/capstone/arch/ARM/ARMMappingInsnOp.inc new file mode 100644 index 000000000..767ab6aa9 --- /dev/null +++ b/capstone/arch/ARM/ARMMappingInsnOp.inc @@ -0,0 +1,10729 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + + +{ /* ARM_ASRi, ARM_INS_ASR: asr */ + { 0 } +}, + +{ /* ARM_ASRr, ARM_INS_ASR: asr */ + { 0 } +}, + +{ /* ARM_ITasm, ARM_INS_IT: it */ + { 0 } +}, + +{ /* ARM_LDRBT_POST, ARM_INS_LDRBT: ldrbt */ + { 0 } +}, + +{ /* ARM_LDRConstPool, ARM_INS_LDR: ldr */ + { 0 } +}, + +{ /* ARM_LDRT_POST, ARM_INS_LDRT: ldrt */ + { 0 } +}, + +{ /* ARM_LSLi, ARM_INS_LSL: lsl */ + { 0 } +}, + +{ /* ARM_LSLr, ARM_INS_LSL: lsl */ + { 0 } +}, + +{ /* ARM_LSRi, ARM_INS_LSR: lsr */ + { 0 } +}, + +{ /* ARM_LSRr, ARM_INS_LSR: lsr */ + { 0 } +}, + +{ /* ARM_RORi, ARM_INS_ROR: ror */ + { 0 } +}, + +{ /* ARM_RORr, ARM_INS_ROR: ror */ + { 0 } +}, + +{ /* ARM_RRXi, ARM_INS_RRX: rrx */ + { 0 } +}, + +{ /* ARM_STRBT_POST, ARM_INS_STRBT: strbt */ + { 0 } +}, + +{ /* ARM_STRT_POST, ARM_INS_STRT: strt */ + { 0 } +}, + +{ /* ARM_VLD1LNdAsm_16, ARM_INS_VLD1: vld1 */ + { 0 } +}, + +{ /* ARM_VLD1LNdAsm_32, ARM_INS_VLD1: vld1 */ + { 0 } +}, + +{ /* ARM_VLD1LNdAsm_8, ARM_INS_VLD1: vld1 */ + { 0 } +}, + +{ /* ARM_VLD1LNdWB_fixed_Asm_16, ARM_INS_VLD1: vld1 */ + { 0 } +}, + +{ /* ARM_VLD1LNdWB_fixed_Asm_32, ARM_INS_VLD1: vld1 */ + { 0 } +}, + +{ /* ARM_VLD1LNdWB_fixed_Asm_8, ARM_INS_VLD1: vld1 */ + { 0 } +}, + +{ /* ARM_VLD1LNdWB_register_Asm_16, ARM_INS_VLD1: vld1 */ + { 0 } +}, + +{ /* ARM_VLD1LNdWB_register_Asm_32, ARM_INS_VLD1: vld1 */ + { 0 } +}, + +{ /* ARM_VLD1LNdWB_register_Asm_8, ARM_INS_VLD1: vld1 */ + { 0 } +}, + +{ /* ARM_VLD2LNdAsm_16, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNdAsm_32, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNdAsm_8, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNdWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNdWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNdWB_fixed_Asm_8, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNdWB_register_Asm_16, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNdWB_register_Asm_32, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNdWB_register_Asm_8, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNqAsm_16, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNqAsm_32, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNqWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNqWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNqWB_register_Asm_16, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD2LNqWB_register_Asm_32, ARM_INS_VLD2: vld2 */ + { 0 } +}, + +{ /* ARM_VLD3DUPdAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPdAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPdAsm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPqAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPqAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPqAsm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPqWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3DUPqWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNdAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNdAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNdAsm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNqAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNqAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3LNqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3dAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3dAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3dAsm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3dWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3dWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3dWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3dWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3dWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3dWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3qAsm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3qAsm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3qAsm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3qWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3qWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3qWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3qWB_register_Asm_16, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3qWB_register_Asm_32, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD3qWB_register_Asm_8, ARM_INS_VLD3: vld3 */ + { 0 } +}, + +{ /* ARM_VLD4DUPdAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPdAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPdAsm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPqAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPqAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPqAsm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPqWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4DUPqWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNdAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNdAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNdAsm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNqAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNqAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4LNqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4dAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4dAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4dAsm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4dWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4dWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4dWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4dWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4dWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4dWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4qAsm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4qAsm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4qAsm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4qWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4qWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4qWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4qWB_register_Asm_16, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4qWB_register_Asm_32, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VLD4qWB_register_Asm_8, ARM_INS_VLD4: vld4 */ + { 0 } +}, + +{ /* ARM_VST1LNdAsm_16, ARM_INS_VST1: vst1 */ + { 0 } +}, + +{ /* ARM_VST1LNdAsm_32, ARM_INS_VST1: vst1 */ + { 0 } +}, + +{ /* ARM_VST1LNdAsm_8, ARM_INS_VST1: vst1 */ + { 0 } +}, + +{ /* ARM_VST1LNdWB_fixed_Asm_16, ARM_INS_VST1: vst1 */ + { 0 } +}, + +{ /* ARM_VST1LNdWB_fixed_Asm_32, ARM_INS_VST1: vst1 */ + { 0 } +}, + +{ /* ARM_VST1LNdWB_fixed_Asm_8, ARM_INS_VST1: vst1 */ + { 0 } +}, + +{ /* ARM_VST1LNdWB_register_Asm_16, ARM_INS_VST1: vst1 */ + { 0 } +}, + +{ /* ARM_VST1LNdWB_register_Asm_32, ARM_INS_VST1: vst1 */ + { 0 } +}, + +{ /* ARM_VST1LNdWB_register_Asm_8, ARM_INS_VST1: vst1 */ + { 0 } +}, + +{ /* ARM_VST2LNdAsm_16, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNdAsm_32, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNdAsm_8, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNdWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNdWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNdWB_fixed_Asm_8, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNdWB_register_Asm_16, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNdWB_register_Asm_32, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNdWB_register_Asm_8, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNqAsm_16, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNqAsm_32, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNqWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNqWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNqWB_register_Asm_16, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST2LNqWB_register_Asm_32, ARM_INS_VST2: vst2 */ + { 0 } +}, + +{ /* ARM_VST3LNdAsm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNdAsm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNdAsm_8, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNdWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNdWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNdWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNdWB_register_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNdWB_register_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNdWB_register_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNqAsm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNqAsm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNqWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNqWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNqWB_register_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3LNqWB_register_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3dAsm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3dAsm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3dAsm_8, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3dWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3dWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3dWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3dWB_register_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3dWB_register_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3dWB_register_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3qAsm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3qAsm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3qAsm_8, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3qWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3qWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3qWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3qWB_register_Asm_16, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3qWB_register_Asm_32, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST3qWB_register_Asm_8, ARM_INS_VST3: vst3 */ + { 0 } +}, + +{ /* ARM_VST4LNdAsm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNdAsm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNdAsm_8, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNdWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNdWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNdWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNdWB_register_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNdWB_register_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNdWB_register_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNqAsm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNqAsm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNqWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNqWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNqWB_register_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4LNqWB_register_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4dAsm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4dAsm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4dAsm_8, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4dWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4dWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4dWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4dWB_register_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4dWB_register_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4dWB_register_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4qAsm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4qAsm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4qAsm_8, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4qWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4qWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4qWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4qWB_register_Asm_16, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4qWB_register_Asm_32, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_VST4qWB_register_Asm_8, ARM_INS_VST4: vst4 */ + { 0 } +}, + +{ /* ARM_t2LDRBpcrel, ARM_INS_LDRB: ldrb */ + { 0 } +}, + +{ /* ARM_t2LDRConstPool, ARM_INS_LDR: ldr */ + { 0 } +}, + +{ /* ARM_t2LDRHpcrel, ARM_INS_LDRH: ldrh */ + { 0 } +}, + +{ /* ARM_t2LDRSBpcrel, ARM_INS_LDRSB: ldrsb */ + { 0 } +}, + +{ /* ARM_t2LDRSHpcrel, ARM_INS_LDRSH: ldrsh */ + { 0 } +}, + +{ /* ARM_t2LDRpcrel, ARM_INS_LDR: ldr */ + { 0 } +}, + +{ /* ARM_t2MOVSsi, ARM_INS_MOVS: movs */ + { 0 } +}, + +{ /* ARM_t2MOVSsr, ARM_INS_MOVS: movs */ + { 0 } +}, + +{ /* ARM_t2MOVsi, ARM_INS_MOV: mov */ + { 0 } +}, + +{ /* ARM_t2MOVsr, ARM_INS_MOV: mov */ + { 0 } +}, + +{ /* ARM_tLDRConstPool, ARM_INS_LDR: ldr */ + { 0 } +}, + +{ /* ARM_ADCri, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_ADCrr, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_ADCrsi, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_ADCrsr, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_ADDri, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_ADDrr, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_ADDrsi, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_ADDrsr, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_ADR, ARM_INS_ADR: adr */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_AESD, ARM_INS_AESD: aesd */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_AESE, ARM_INS_AESE: aese */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_AESIMC, ARM_INS_AESIMC: aesimc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_AESMC, ARM_INS_AESMC: aesmc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_ANDri, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_ANDrr, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_ANDrsi, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_ANDrsr, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_BFC, ARM_INS_BFC: bfc */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_BFI, ARM_INS_BFI: bfi */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_BICri, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_BICrr, ARM_INS_BIC: bic */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_BICrsi, ARM_INS_BIC: bic */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_BICrsr, ARM_INS_BIC: bic */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_BKPT, ARM_INS_BKPT: bkpt */ + { 0 } +}, + +{ /* ARM_BL, ARM_INS_BL: bl */ + { 0 } +}, + +{ /* ARM_BLX, ARM_INS_BLX: blx */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_BLX_pred, ARM_INS_BLX: blx */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_BLXi, ARM_INS_BLX: blx */ + { 0 } +}, + +{ /* ARM_BL_pred, ARM_INS_BL: bl */ + { 0 } +}, + +{ /* ARM_BX, ARM_INS_BX: bx */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_BXJ, ARM_INS_BXJ: bxj */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_BX_RET, ARM_INS_BX: bx */ + { 0 } +}, + +{ /* ARM_BX_pred, ARM_INS_BX: bx */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_Bcc, ARM_INS_B: b */ + { 0 } +}, + +{ /* ARM_CDP, ARM_INS_CDP: cdp */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_CDP2, ARM_INS_CDP2: cdp2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_CLREX, ARM_INS_CLREX: clrex */ + { 0 } +}, + +{ /* ARM_CLZ, ARM_INS_CLZ: clz */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_CMNri, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_CMNzrr, ARM_INS_CMN: cmn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_CMNzrsi, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_CMNzrsr, ARM_INS_CMN: cmn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_CMPri, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_CMPrr, ARM_INS_CMP: cmp */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_CMPrsi, ARM_INS_CMP: cmp */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_CMPrsr, ARM_INS_CMP: cmp */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_CPS1p, ARM_INS_CPS: cps */ + { 0 } +}, + +{ /* ARM_CPS2p, ARM_INS_CPS: cps */ + { 0 } +}, + +{ /* ARM_CPS3p, ARM_INS_CPS: cps */ + { 0 } +}, + +{ /* ARM_CRC32B, ARM_INS_CRC32B: crc32b */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_CRC32H, ARM_INS_CRC32H: crc32h */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_CRC32W, ARM_INS_CRC32W: crc32w */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_DBG, ARM_INS_DBG: dbg */ + { 0 } +}, + +{ /* ARM_DMB, ARM_INS_DMB: dmb */ + { 0 } +}, + +{ /* ARM_DSB, ARM_INS_DFB: dfb */ + { 0 } +}, + +{ /* ARM_EORri, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_EORrr, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_EORrsi, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_EORrsr, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_ERET, ARM_INS_ERET: eret */ + { 0 } +}, + +{ /* ARM_FCONSTD, ARM_INS_FCONSTD: fconstd */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_FCONSTH, ARM_INS_VMOV: vmov */ + { 0 } +}, + +{ /* ARM_FCONSTS, ARM_INS_FCONSTS: fconsts */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_FMSTAT, ARM_INS_FMSTAT: fmstat */ + { 0 } +}, + +{ /* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_HINT, ARM_INS_CSDB: csdb */ + { 0 } +}, + +{ /* ARM_HLT, ARM_INS_HLT: hlt */ + { 0 } +}, + +{ /* ARM_HVC, ARM_INS_HVC: hvc */ + { 0 } +}, + +{ /* ARM_ISB, ARM_INS_ISB: isb */ + { 0 } +}, + +{ /* ARM_LDA, ARM_INS_LDA: lda */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDAB, ARM_INS_LDAB: ldab */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDAEX, ARM_INS_LDAEX: ldaex */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDAH, ARM_INS_LDAH: ldah */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC_OPTION, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC_POST, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDC_PRE, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDMDA, ARM_INS_LDMDA: ldmda */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDMDB, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDMIA, ARM_INS_LDM: ldm */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDMIA_UPD, ARM_INS_LDM: ldm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDMIB, ARM_INS_LDMIB: ldmib */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRBi12, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRBrs, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRD, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDRD_POST, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDREX, ARM_INS_LDREX: ldrex */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDREXB, ARM_INS_LDREXB: ldrexb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDREXD, ARM_INS_LDREXD: ldrexd */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDREXH, ARM_INS_LDREXH: ldrexh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRH, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDRHTi, ARM_INS_LDRHT: ldrht */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRHTr, ARM_INS_LDRHT: ldrht */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRH_POST, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDRSB, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDRSH, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDR_POST_REG, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt $addr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRi12, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_LDRrs, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_MCR, ARM_INS_MCR: mcr */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_MCR2, ARM_INS_MCR2: mcr2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_MCRR, ARM_INS_MCRR: mcrr */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_MLA, ARM_INS_MLA: mla */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_MLS, ARM_INS_MLS: mls */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_MOVPCLR, ARM_INS_MOV: mov */ + { 0 } +}, + +{ /* ARM_MOVTi16, ARM_INS_MOVT: movt */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_MOVi, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_MOVi16, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_MOVr, ARM_INS_MOV: mov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_MOVr_TC, ARM_INS_MOV: mov */ + { 0 } +}, + +{ /* ARM_MOVsi, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_MOVsr, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_MRC, ARM_INS_MRC: mrc */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_MRC2, ARM_INS_MRC2: mrc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_MRRC, ARM_INS_MRRC: mrrc */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_MRS, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_MRSbanked, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_MRSsys, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_MSR, ARM_INS_MSR: msr */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_MSRbanked, ARM_INS_MSR: msr */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_MSRi, ARM_INS_MSR: msr */ + { 0 } +}, + +{ /* ARM_MUL, ARM_INS_MUL: mul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_MVNi, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_MVNr, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_MVNsi, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_MVNsr, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_ORRri, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_ORRrr, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_ORRrsi, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_ORRrsr, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_PKHBT, ARM_INS_PKHBT: pkhbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_PKHTB, ARM_INS_PKHTB: pkhtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_PLDWi12, ARM_INS_PLDW: pldw */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_PLDWrs, ARM_INS_PLDW: pldw */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_PLDi12, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_PLDrs, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_PLIi12, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_PLIrs, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_QADD, ARM_INS_QADD: qadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_QADD16, ARM_INS_QADD16: qadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_QADD8, ARM_INS_QADD8: qadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_QASX, ARM_INS_QASX: qasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_QDADD, ARM_INS_QDADD: qdadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_QDSUB, ARM_INS_QDSUB: qdsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_QSAX, ARM_INS_QSAX: qsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_QSUB, ARM_INS_QSUB: qsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_QSUB16, ARM_INS_QSUB16: qsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_QSUB8, ARM_INS_QSUB8: qsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_RBIT, ARM_INS_RBIT: rbit */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_REV, ARM_INS_REV: rev */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_REV16, ARM_INS_REV16: rev16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_REVSH, ARM_INS_REVSH: revsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_RFEDA, ARM_INS_RFEDA: rfeda */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_RFEDB, ARM_INS_RFEDB: rfedb */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_RFEIA, ARM_INS_RFEIA: rfeia */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_RFEIB, ARM_INS_RFEIB: rfeib */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_RSBri, ARM_INS_NEG: neg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_RSBrr, ARM_INS_RSB: rsb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_RSBrsi, ARM_INS_RSB: rsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_RSBrsr, ARM_INS_RSB: rsb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_RSCri, ARM_INS_RSC: rsc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_RSCrr, ARM_INS_RSC: rsc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_RSCrsi, ARM_INS_RSC: rsc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_RSCrsr, ARM_INS_RSC: rsc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SADD16, ARM_INS_SADD16: sadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SADD8, ARM_INS_SADD8: sadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SASX, ARM_INS_SASX: sasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SBCri, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SBCrr, ARM_INS_SBC: sbc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SBCrsi, ARM_INS_SBC: sbc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SBCrsr, ARM_INS_SBC: sbc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SBFX, ARM_INS_SBFX: sbfx */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SDIV, ARM_INS_SDIV: sdiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SEL, ARM_INS_SEL: sel */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SETEND, ARM_INS_SETEND: setend */ + { 0 } +}, + +{ /* ARM_SETPAN, ARM_INS_SETPAN: setpan */ + { 0 } +}, + +{ /* ARM_SHA1C, ARM_INS_SHA1C: sha1c */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHA1H, ARM_INS_SHA1H: sha1h */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SHA1M, ARM_INS_SHA1M: sha1m */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHA1P, ARM_INS_SHA1P: sha1p */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SHA256H, ARM_INS_SHA256H: sha256h */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHADD16, ARM_INS_SHADD16: shadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHADD8, ARM_INS_SHADD8: shadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHASX, ARM_INS_SHASX: shasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHSAX, ARM_INS_SHSAX: shsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMC, ARM_INS_SMC: smc */ + { 0 } +}, + +{ /* ARM_SMLABB, ARM_INS_SMLABB: smlabb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLABT, ARM_INS_SMLABT: smlabt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLAD, ARM_INS_SMLAD: smlad */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLADX, ARM_INS_SMLADX: smladx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLAL, ARM_INS_SMLAL: smlal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLALD, ARM_INS_SMLALD: smlald */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLATB, ARM_INS_SMLATB: smlatb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLATT, ARM_INS_SMLATT: smlatt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLSD, ARM_INS_SMLSD: smlsd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMMLA, ARM_INS_SMMLA: smmla */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMMLS, ARM_INS_SMMLS: smmls */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMMUL, ARM_INS_SMMUL: smmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMMULR, ARM_INS_SMMULR: smmulr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMUAD, ARM_INS_SMUAD: smuad */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMUADX, ARM_INS_SMUADX: smuadx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMULBB, ARM_INS_SMULBB: smulbb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMULBT, ARM_INS_SMULBT: smulbt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMULL, ARM_INS_SMULL: smull */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMULTB, ARM_INS_SMULTB: smultb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMULTT, ARM_INS_SMULTT: smultt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMULWB, ARM_INS_SMULWB: smulwb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMULWT, ARM_INS_SMULWT: smulwt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMUSD, ARM_INS_SMUSD: smusd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SRSDA, ARM_INS_SRSDA: srsda */ + { 0 } +}, + +{ /* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda */ + { 0 } +}, + +{ /* ARM_SRSDB, ARM_INS_SRSDB: srsdb */ + { 0 } +}, + +{ /* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb */ + { 0 } +}, + +{ /* ARM_SRSIA, ARM_INS_SRSIA: srsia */ + { 0 } +}, + +{ /* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia */ + { 0 } +}, + +{ /* ARM_SRSIB, ARM_INS_SRSIB: srsib */ + { 0 } +}, + +{ /* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib */ + { 0 } +}, + +{ /* ARM_SSAT, ARM_INS_SSAT: ssat */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_SSAT16, ARM_INS_SSAT16: ssat16 */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* ARM_SSAX, ARM_INS_SSAX: ssax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SSUB16, ARM_INS_SSUB16: ssub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SSUB8, ARM_INS_SSUB8: ssub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC2_POST, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC2_PRE, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STCL_OPTION, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STCL_POST, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STCL_PRE, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC_OFFSET, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC_OPTION, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC_POST, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STC_PRE, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STL, ARM_INS_STL: stl */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STLB, ARM_INS_STLB: stlb */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STLEX, ARM_INS_STLEX: stlex */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STLEXB, ARM_INS_STLEXB: stlexb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STLEXD, ARM_INS_STLEXD: stlexd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STLEXH, ARM_INS_STLEXH: stlexh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STLH, ARM_INS_STLH: stlh */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STMDA, ARM_INS_STMDA: stmda */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STMDA_UPD, ARM_INS_STMDA: stmda */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_STMDB, ARM_INS_STMDB: stmdb */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STMDB_UPD, ARM_INS_PUSH: push */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_STMIA, ARM_INS_STM: stm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STMIA_UPD, ARM_INS_STM: stm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_STMIB, ARM_INS_STMIB: stmib */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STMIB_UPD, ARM_INS_STMIB: stmib */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STRB_POST_IMM, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRB_POST_REG, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRB_PRE_REG, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRBi12, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRBrs, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRD, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STRD_POST, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STRD_PRE, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STREX, ARM_INS_STREX: strex */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STREXB, ARM_INS_STREXB: strexb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STREXD, ARM_INS_STREXD: strexd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STREXH, ARM_INS_STREXH: strexh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STRH, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRHTi, ARM_INS_STRHT: strht */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STRHTr, ARM_INS_STRHT: strht */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STRH_POST, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_STRH_PRE, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRT_POST_IMM, ARM_INS_STRT: strt */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRT_POST_REG, ARM_INS_STRT: strt */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STR_POST_IMM, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STR_POST_REG, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STR_PRE_IMM, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STR_PRE_REG, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRi12, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_STRrs, ARM_INS_STR: str */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_SUBri, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SUBrr, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SUBrsi, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SUBrsr, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SVC, ARM_INS_SVC: svc */ + { 0 } +}, + +{ /* ARM_SWP, ARM_INS_SWP: swp */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SWPB, ARM_INS_SWPB: swpb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_SXTAB, ARM_INS_SXTAB: sxtab */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SXTAH, ARM_INS_SXTAH: sxtah */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_SXTB, ARM_INS_SXTB: sxtb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_SXTB16, ARM_INS_SXTB16: sxtb16 */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_SXTH, ARM_INS_SXTH: sxth */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_TEQri, ARM_INS_TEQ: teq */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_TEQrr, ARM_INS_TEQ: teq */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_TEQrsi, ARM_INS_TEQ: teq */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_TEQrsr, ARM_INS_TEQ: teq */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_TRAP, ARM_INS_TRAP: trap */ + { 0 } +}, + +{ /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ + { 0 } +}, + +{ /* ARM_TSB, ARM_INS_TSB: tsb */ + { 0 } +}, + +{ /* ARM_TSTri, ARM_INS_TST: tst */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_TSTrr, ARM_INS_TST: tst */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_TSTrsi, ARM_INS_TST: tst */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_TSTrsr, ARM_INS_TST: tst */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UADD16, ARM_INS_UADD16: uadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UADD8, ARM_INS_UADD8: uadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UASX, ARM_INS_UASX: uasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UBFX, ARM_INS_UBFX: ubfx */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_UDF, ARM_INS_UDF: udf */ + { 0 } +}, + +{ /* ARM_UDIV, ARM_INS_UDIV: udiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UHADD16, ARM_INS_UHADD16: uhadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UHADD8, ARM_INS_UHADD8: uhadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UHASX, ARM_INS_UHASX: uhasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UHSAX, ARM_INS_UHSAX: uhsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UMAAL, ARM_INS_UMAAL: umaal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UMLAL, ARM_INS_UMLAL: umlal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UMULL, ARM_INS_UMULL: umull */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UQADD16, ARM_INS_UQADD16: uqadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UQADD8, ARM_INS_UQADD8: uqadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UQASX, ARM_INS_UQASX: uqasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UQSAX, ARM_INS_UQSAX: uqsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_USAD8, ARM_INS_USAD8: usad8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_USADA8, ARM_INS_USADA8: usada8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_USAT, ARM_INS_USAT: usat */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_USAT16, ARM_INS_USAT16: usat16 */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* ARM_USAX, ARM_INS_USAX: usax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_USUB16, ARM_INS_USUB16: usub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_USUB8, ARM_INS_USUB8: usub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_UXTAB, ARM_INS_UXTAB: uxtab */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_UXTAH, ARM_INS_UXTAH: uxtah */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_UXTB, ARM_INS_UXTB: uxtb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_UXTB16, ARM_INS_UXTB16: uxtb16 */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_UXTH, ARM_INS_UXTH: uxth */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VABALsv2i64, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABALsv4i32, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABALsv8i16, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABALuv2i64, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABALuv4i32, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABALuv8i16, ARM_INS_VABAL: vabal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAsv16i8, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAsv2i32, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAsv4i16, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAsv4i32, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAsv8i16, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAsv8i8, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAuv16i8, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAuv2i32, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAuv4i16, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAuv4i32, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAuv8i16, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABAuv8i8, ARM_INS_VABA: vaba */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDfd, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDfq, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDhd, ARM_INS_VABD: vabd */ + { 0 } +}, + +{ /* ARM_VABDhq, ARM_INS_VABD: vabd */ + { 0 } +}, + +{ /* ARM_VABDsv16i8, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDsv2i32, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDsv4i16, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDsv4i32, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDsv8i16, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDsv8i8, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDuv16i8, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDuv2i32, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDuv4i16, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDuv4i32, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDuv8i16, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABDuv8i8, ARM_INS_VABD: vabd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VABSD, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VABSH, ARM_INS_VABS: vabs */ + { 0 } +}, + +{ /* ARM_VABSS, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VABSfd, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VABSfq, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VABShd, ARM_INS_VABS: vabs */ + { 0 } +}, + +{ /* ARM_VABShq, ARM_INS_VABS: vabs */ + { 0 } +}, + +{ /* ARM_VABSv16i8, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VABSv2i32, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VABSv4i16, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VABSv4i32, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VABSv8i16, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VABSv8i8, ARM_INS_VABS: vabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VACGEfd, ARM_INS_VACGE: vacge */ + { 0 } +}, + +{ /* ARM_VACGEfq, ARM_INS_VACGE: vacge */ + { 0 } +}, + +{ /* ARM_VACGEhd, ARM_INS_VACGE: vacge */ + { 0 } +}, + +{ /* ARM_VACGEhq, ARM_INS_VACGE: vacge */ + { 0 } +}, + +{ /* ARM_VACGTfd, ARM_INS_VACGT: vacgt */ + { 0 } +}, + +{ /* ARM_VACGTfq, ARM_INS_VACGT: vacgt */ + { 0 } +}, + +{ /* ARM_VACGThd, ARM_INS_VACGT: vacgt */ + { 0 } +}, + +{ /* ARM_VACGThq, ARM_INS_VACGT: vacgt */ + { 0 } +}, + +{ /* ARM_VADDD, ARM_INS_FADDD: faddd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDH, ARM_INS_VADD: vadd */ + { 0 } +}, + +{ /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDS, ARM_INS_FADDS: fadds */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDfd, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDfq, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDhd, ARM_INS_VADD: vadd */ + { 0 } +}, + +{ /* ARM_VADDhq, ARM_INS_VADD: vadd */ + { 0 } +}, + +{ /* ARM_VADDv16i8, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDv1i64, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDv2i32, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDv2i64, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDv4i16, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDv4i32, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDv8i16, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VADDv8i8, ARM_INS_VADD: vadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VANDd, ARM_INS_VAND: vand */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VANDq, ARM_INS_VAND: vand */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VBICd, ARM_INS_VBIC: vbic */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VBICiv2i32, ARM_INS_VAND: vand */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VBICiv4i16, ARM_INS_VAND: vand */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VBICiv4i32, ARM_INS_VAND: vand */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VBICiv8i16, ARM_INS_VAND: vand */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VBICq, ARM_INS_VBIC: vbic */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VBIFd, ARM_INS_VBIF: vbif */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VBIFq, ARM_INS_VBIF: vbif */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VBITd, ARM_INS_VBIT: vbit */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VBITq, ARM_INS_VBIT: vbit */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VBSLd, ARM_INS_VBSL: vbsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VBSLq, ARM_INS_VBSL: vbsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCADDv2f32, ARM_INS_VCADD: vcadd */ + { 0 } +}, + +{ /* ARM_VCADDv4f16, ARM_INS_VCADD: vcadd */ + { 0 } +}, + +{ /* ARM_VCADDv4f32, ARM_INS_VCADD: vcadd */ + { 0 } +}, + +{ /* ARM_VCADDv8f16, ARM_INS_VCADD: vcadd */ + { 0 } +}, + +{ /* ARM_VCEQfd, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQfq, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQhd, ARM_INS_VCEQ: vceq */ + { 0 } +}, + +{ /* ARM_VCEQhq, ARM_INS_VCEQ: vceq */ + { 0 } +}, + +{ /* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQzv4f16, ARM_INS_VCEQ: vceq */ + { 0 } +}, + +{ /* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQzv8f16, ARM_INS_VCEQ: vceq */ + { 0 } +}, + +{ /* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEfd, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEfq, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEhd, ARM_INS_VCGE: vcge */ + { 0 } +}, + +{ /* ARM_VCGEhq, ARM_INS_VCGE: vcge */ + { 0 } +}, + +{ /* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEzv4f16, ARM_INS_VCGE: vcge */ + { 0 } +}, + +{ /* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEzv8f16, ARM_INS_VCGE: vcge */ + { 0 } +}, + +{ /* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTfd, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTfq, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGThd, ARM_INS_VCGT: vcgt */ + { 0 } +}, + +{ /* ARM_VCGThq, ARM_INS_VCGT: vcgt */ + { 0 } +}, + +{ /* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTzv4f16, ARM_INS_VCGT: vcgt */ + { 0 } +}, + +{ /* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTzv8f16, ARM_INS_VCGT: vcgt */ + { 0 } +}, + +{ /* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLEzv4f16, ARM_INS_VCLE: vcle */ + { 0 } +}, + +{ /* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLEzv8f16, ARM_INS_VCLE: vcle */ + { 0 } +}, + +{ /* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLTzv4f16, ARM_INS_VCLT: vclt */ + { 0 } +}, + +{ /* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLTzv8f16, ARM_INS_VCLT: vclt */ + { 0 } +}, + +{ /* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCMLAv2f32, ARM_INS_VCMLA: vcmla */ + { 0 } +}, + +{ /* ARM_VCMLAv2f32_indexed, ARM_INS_VCMLA: vcmla */ + { 0 } +}, + +{ /* ARM_VCMLAv4f16, ARM_INS_VCMLA: vcmla */ + { 0 } +}, + +{ /* ARM_VCMLAv4f16_indexed, ARM_INS_VCMLA: vcmla */ + { 0 } +}, + +{ /* ARM_VCMLAv4f32, ARM_INS_VCMLA: vcmla */ + { 0 } +}, + +{ /* ARM_VCMLAv4f32_indexed, ARM_INS_VCMLA: vcmla */ + { 0 } +}, + +{ /* ARM_VCMLAv8f16, ARM_INS_VCMLA: vcmla */ + { 0 } +}, + +{ /* ARM_VCMLAv8f16_indexed, ARM_INS_VCMLA: vcmla */ + { 0 } +}, + +{ /* ARM_VCMPD, ARM_INS_VCMP: vcmp */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCMPED, ARM_INS_VCMPE: vcmpe */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCMPEH, ARM_INS_VCMPE: vcmpe */ + { 0 } +}, + +{ /* ARM_VCMPES, ARM_INS_VCMPE: vcmpe */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VCMPEZH, ARM_INS_VCMPE: vcmpe */ + { 0 } +}, + +{ /* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VCMPH, ARM_INS_VCMP: vcmp */ + { 0 } +}, + +{ /* ARM_VCMPS, ARM_INS_VCMP: vcmp */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VCMPZD, ARM_INS_FCMPZD: fcmpzd */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VCMPZH, ARM_INS_VCMP: vcmp */ + { 0 } +}, + +{ /* ARM_VCMPZS, ARM_INS_FCMPZS: fcmpzs */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VCNTd, ARM_INS_VCNT: vcnt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCNTq, ARM_INS_VCNT: vcnt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTANSDf, ARM_INS_VCVTA: vcvta */ + { 0 } +}, + +{ /* ARM_VCVTANSDh, ARM_INS_VCVTA: vcvta */ + { 0 } +}, + +{ /* ARM_VCVTANSQf, ARM_INS_VCVTA: vcvta */ + { 0 } +}, + +{ /* ARM_VCVTANSQh, ARM_INS_VCVTA: vcvta */ + { 0 } +}, + +{ /* ARM_VCVTANUDf, ARM_INS_VCVTA: vcvta */ + { 0 } +}, + +{ /* ARM_VCVTANUDh, ARM_INS_VCVTA: vcvta */ + { 0 } +}, + +{ /* ARM_VCVTANUQf, ARM_INS_VCVTA: vcvta */ + { 0 } +}, + +{ /* ARM_VCVTANUQh, ARM_INS_VCVTA: vcvta */ + { 0 } +}, + +{ /* ARM_VCVTASD, ARM_INS_VCVTA: vcvta */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTASH, ARM_INS_VCVTA: vcvta */ + { 0 } +}, + +{ /* ARM_VCVTASS, ARM_INS_VCVTA: vcvta */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTAUH, ARM_INS_VCVTA: vcvta */ + { 0 } +}, + +{ /* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTDS, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTMNSDf, ARM_INS_VCVTM: vcvtm */ + { 0 } +}, + +{ /* ARM_VCVTMNSDh, ARM_INS_VCVTM: vcvtm */ + { 0 } +}, + +{ /* ARM_VCVTMNSQf, ARM_INS_VCVTM: vcvtm */ + { 0 } +}, + +{ /* ARM_VCVTMNSQh, ARM_INS_VCVTM: vcvtm */ + { 0 } +}, + +{ /* ARM_VCVTMNUDf, ARM_INS_VCVTM: vcvtm */ + { 0 } +}, + +{ /* ARM_VCVTMNUDh, ARM_INS_VCVTM: vcvtm */ + { 0 } +}, + +{ /* ARM_VCVTMNUQf, ARM_INS_VCVTM: vcvtm */ + { 0 } +}, + +{ /* ARM_VCVTMNUQh, ARM_INS_VCVTM: vcvtm */ + { 0 } +}, + +{ /* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTMSH, ARM_INS_VCVTM: vcvtm */ + { 0 } +}, + +{ /* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTMUH, ARM_INS_VCVTM: vcvtm */ + { 0 } +}, + +{ /* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTNNSDf, ARM_INS_VCVTN: vcvtn */ + { 0 } +}, + +{ /* ARM_VCVTNNSDh, ARM_INS_VCVTN: vcvtn */ + { 0 } +}, + +{ /* ARM_VCVTNNSQf, ARM_INS_VCVTN: vcvtn */ + { 0 } +}, + +{ /* ARM_VCVTNNSQh, ARM_INS_VCVTN: vcvtn */ + { 0 } +}, + +{ /* ARM_VCVTNNUDf, ARM_INS_VCVTN: vcvtn */ + { 0 } +}, + +{ /* ARM_VCVTNNUDh, ARM_INS_VCVTN: vcvtn */ + { 0 } +}, + +{ /* ARM_VCVTNNUQf, ARM_INS_VCVTN: vcvtn */ + { 0 } +}, + +{ /* ARM_VCVTNNUQh, ARM_INS_VCVTN: vcvtn */ + { 0 } +}, + +{ /* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTNSH, ARM_INS_VCVTN: vcvtn */ + { 0 } +}, + +{ /* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTNUH, ARM_INS_VCVTN: vcvtn */ + { 0 } +}, + +{ /* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTPNSDf, ARM_INS_VCVTP: vcvtp */ + { 0 } +}, + +{ /* ARM_VCVTPNSDh, ARM_INS_VCVTP: vcvtp */ + { 0 } +}, + +{ /* ARM_VCVTPNSQf, ARM_INS_VCVTP: vcvtp */ + { 0 } +}, + +{ /* ARM_VCVTPNSQh, ARM_INS_VCVTP: vcvtp */ + { 0 } +}, + +{ /* ARM_VCVTPNUDf, ARM_INS_VCVTP: vcvtp */ + { 0 } +}, + +{ /* ARM_VCVTPNUDh, ARM_INS_VCVTP: vcvtp */ + { 0 } +}, + +{ /* ARM_VCVTPNUQf, ARM_INS_VCVTP: vcvtp */ + { 0 } +}, + +{ /* ARM_VCVTPNUQh, ARM_INS_VCVTP: vcvtp */ + { 0 } +}, + +{ /* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTPSH, ARM_INS_VCVTP: vcvtp */ + { 0 } +}, + +{ /* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTPUH, ARM_INS_VCVTP: vcvtp */ + { 0 } +}, + +{ /* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTSD, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTf2h, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTh2f, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTh2sd, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTh2sq, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTh2ud, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTh2uq, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTh2xsd, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTh2xsq, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTh2xud, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTh2xuq, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTs2hd, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTs2hq, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTu2hd, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTu2hq, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTxs2hd, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTxs2hq, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VCVTxu2hd, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VCVTxu2hq, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VDIVD, ARM_INS_VDIV: vdiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VDIVH, ARM_INS_VDIV: vdiv */ + { 0 } +}, + +{ /* ARM_VDIVS, ARM_INS_VDIV: vdiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUP16d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUP16q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUP32d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUP32q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUP8d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUP8q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUPLN16d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUPLN16q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUPLN32d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUPLN32q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUPLN8d, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VDUPLN8q, ARM_INS_VDUP: vdup */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VEORd, ARM_INS_VEOR: veor */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VEORq, ARM_INS_VEOR: veor */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VEXTd16, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VEXTd32, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VEXTd8, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VEXTq16, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VEXTq32, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VEXTq64, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VEXTq8, ARM_INS_VEXT: vext */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFMAD, ARM_INS_VFMA: vfma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFMAH, ARM_INS_VFMA: vfma */ + { 0 } +}, + +{ /* ARM_VFMAS, ARM_INS_VFMA: vfma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFMAfd, ARM_INS_VFMA: vfma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFMAfq, ARM_INS_VFMA: vfma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFMAhd, ARM_INS_VFMA: vfma */ + { 0 } +}, + +{ /* ARM_VFMAhq, ARM_INS_VFMA: vfma */ + { 0 } +}, + +{ /* ARM_VFMSD, ARM_INS_VFMS: vfms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFMSH, ARM_INS_VFMS: vfms */ + { 0 } +}, + +{ /* ARM_VFMSS, ARM_INS_VFMS: vfms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFMSfd, ARM_INS_VFMS: vfms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFMSfq, ARM_INS_VFMS: vfms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFMShd, ARM_INS_VFMS: vfms */ + { 0 } +}, + +{ /* ARM_VFMShq, ARM_INS_VFMS: vfms */ + { 0 } +}, + +{ /* ARM_VFNMAD, ARM_INS_VFNMA: vfnma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFNMAH, ARM_INS_VFNMA: vfnma */ + { 0 } +}, + +{ /* ARM_VFNMAS, ARM_INS_VFNMA: vfnma */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VFNMSH, ARM_INS_VFNMS: vfnms */ + { 0 } +}, + +{ /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VGETLNi32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VGETLNs16, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VGETLNs8, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VGETLNu16, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VGETLNu8, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VINSH, ARM_INS_VINS: vins */ + { 0 } +}, + +{ /* ARM_VJCVT, ARM_INS_VJCVT: vjcvt */ + { 0 } +}, + +{ /* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1LNd16, ARM_INS_VLD1: vld1 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD1LNd32, ARM_INS_VLD1: vld1 */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD1LNd8, ARM_INS_VLD1: vld1 */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD1d16, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d16Q, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d16T, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d32, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d32Q, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d32T, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d64, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d64Q, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d64T, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d8, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d8Q, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d8T, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q16, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q32, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q64, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q8, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD2b16, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2b32, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2b8, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2d16, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2d32, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2d8, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2q16, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2q32, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2q8, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD3d16, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD3d32, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD3d8, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD3q16, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD3q32, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD3q8, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4d16, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4d32, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4d8, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4q16, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4q32, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLD4q8, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4 */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLDRD, ARM_INS_VLDR: vldr */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLDRH, ARM_INS_VLDR: vldr */ + { 0 } +}, + +{ /* ARM_VLDRS, ARM_INS_VLDR: vldr */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VLLDM, ARM_INS_VLLDM: vlldm */ + { 0 } +}, + +{ /* ARM_VLSTM, ARM_INS_VLSTM: vlstm */ + { 0 } +}, + +{ /* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXNMH, ARM_INS_VMAXNM: vmaxnm */ + { 0 } +}, + +{ /* ARM_VMAXNMNDf, ARM_INS_VMAXNM: vmaxnm */ + { 0 } +}, + +{ /* ARM_VMAXNMNDh, ARM_INS_VMAXNM: vmaxnm */ + { 0 } +}, + +{ /* ARM_VMAXNMNQf, ARM_INS_VMAXNM: vmaxnm */ + { 0 } +}, + +{ /* ARM_VMAXNMNQh, ARM_INS_VMAXNM: vmaxnm */ + { 0 } +}, + +{ /* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXfd, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXfq, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXhd, ARM_INS_VMAX: vmax */ + { 0 } +}, + +{ /* ARM_VMAXhq, ARM_INS_VMAX: vmax */ + { 0 } +}, + +{ /* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINNMD, ARM_INS_VMINNM: vminnm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINNMH, ARM_INS_VMINNM: vminnm */ + { 0 } +}, + +{ /* ARM_VMINNMNDf, ARM_INS_VMINNM: vminnm */ + { 0 } +}, + +{ /* ARM_VMINNMNDh, ARM_INS_VMINNM: vminnm */ + { 0 } +}, + +{ /* ARM_VMINNMNQf, ARM_INS_VMINNM: vminnm */ + { 0 } +}, + +{ /* ARM_VMINNMNQh, ARM_INS_VMINNM: vminnm */ + { 0 } +}, + +{ /* ARM_VMINNMS, ARM_INS_VMINNM: vminnm */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINfd, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINfq, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINhd, ARM_INS_VMIN: vmin */ + { 0 } +}, + +{ /* ARM_VMINhq, ARM_INS_VMIN: vmin */ + { 0 } +}, + +{ /* ARM_VMINsv16i8, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINsv2i32, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINsv4i16, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINsv4i32, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINsv8i16, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINsv8i8, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINuv16i8, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINuv2i32, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINuv4i16, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINuv4i32, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINuv8i16, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMINuv8i8, ARM_INS_VMIN: vmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAD, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAH, ARM_INS_VMLA: vmla */ + { 0 } +}, + +{ /* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAS, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAfd, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAfq, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAhd, ARM_INS_VMLA: vmla */ + { 0 } +}, + +{ /* ARM_VMLAhq, ARM_INS_VMLA: vmla */ + { 0 } +}, + +{ /* ARM_VMLAslfd, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAslfq, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAslhd, ARM_INS_VMLA: vmla */ + { 0 } +}, + +{ /* ARM_VMLAslhq, ARM_INS_VMLA: vmla */ + { 0 } +}, + +{ /* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAv16i8, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAv2i32, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAv4i16, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAv4i32, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAv8i16, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLAv8i8, ARM_INS_VMLA: vmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSD, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSH, ARM_INS_VMLS: vmls */ + { 0 } +}, + +{ /* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSS, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSfd, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSfq, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLShd, ARM_INS_VMLS: vmls */ + { 0 } +}, + +{ /* ARM_VMLShq, ARM_INS_VMLS: vmls */ + { 0 } +}, + +{ /* ARM_VMLSslfd, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSslfq, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSslhd, ARM_INS_VMLS: vmls */ + { 0 } +}, + +{ /* ARM_VMLSslhq, ARM_INS_VMLS: vmls */ + { 0 } +}, + +{ /* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSv16i8, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSv2i32, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSv4i16, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSv4i32, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSv8i16, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMLSv8i8, ARM_INS_VMLS: vmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVD, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVDRR, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVH, ARM_INS_VMOVX: vmovx */ + { 0 } +}, + +{ /* ARM_VMOVHR, ARM_INS_VMOV: vmov */ + { 0 } +}, + +{ /* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVRH, ARM_INS_VMOV: vmov */ + { 0 } +}, + +{ /* ARM_VMOVRRD, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVRRS, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVRS, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVS, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVSR, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVSRR, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMOVv16i8, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMOVv1i64, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMOVv2f32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMOVv2i32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMOVv2i64, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMOVv4f32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMOVv4i16, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMOVv4i32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMOVv8i16, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMOVv8i8, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMRS, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMRS_FPEXC, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMRS_FPINST, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMRS_FPINST2, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMRS_FPSID, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMRS_MVFR0, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMRS_MVFR1, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMRS_MVFR2, ARM_INS_VMRS: vmrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMSR, ARM_INS_VMSR: vmsr */ + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMSR_FPEXC, ARM_INS_VMSR: vmsr */ + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMSR_FPINST, ARM_INS_VMSR: vmsr */ + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMSR_FPINST2, ARM_INS_VMSR: vmsr */ + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMSR_FPSID, ARM_INS_VMSR: vmsr */ + { CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULD, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULH, ARM_INS_VMUL: vmul */ + { 0 } +}, + +{ /* ARM_VMULLp64, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLp8, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULS, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULfd, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULfq, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULhd, ARM_INS_VMUL: vmul */ + { 0 } +}, + +{ /* ARM_VMULhq, ARM_INS_VMUL: vmul */ + { 0 } +}, + +{ /* ARM_VMULpd, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULpq, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULslfd, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULslfq, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULslhd, ARM_INS_VMUL: vmul */ + { 0 } +}, + +{ /* ARM_VMULslhq, ARM_INS_VMUL: vmul */ + { 0 } +}, + +{ /* ARM_VMULslv2i32, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULslv4i16, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULslv4i32, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULslv8i16, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULv16i8, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULv2i32, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULv4i16, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULv4i32, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULv8i16, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMULv8i8, ARM_INS_VMUL: vmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VMVNd, ARM_INS_VMVN: vmvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMVNq, ARM_INS_VMVN: vmvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VMVNv2i32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMVNv4i32, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_VNEGD, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VNEGH, ARM_INS_VNEG: vneg */ + { 0 } +}, + +{ /* ARM_VNEGS, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VNEGf32q, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VNEGfd, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VNEGhd, ARM_INS_VNEG: vneg */ + { 0 } +}, + +{ /* ARM_VNEGhq, ARM_INS_VNEG: vneg */ + { 0 } +}, + +{ /* ARM_VNEGs16d, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VNEGs16q, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VNEGs32d, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VNEGs32q, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VNEGs8d, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VNEGs8q, ARM_INS_VNEG: vneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VNMLAD, ARM_INS_VNMLA: vnmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VNMLAH, ARM_INS_VNMLA: vnmla */ + { 0 } +}, + +{ /* ARM_VNMLAS, ARM_INS_VNMLA: vnmla */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VNMLSD, ARM_INS_VNMLS: vnmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VNMLSH, ARM_INS_VNMLS: vnmls */ + { 0 } +}, + +{ /* ARM_VNMLSS, ARM_INS_VNMLS: vnmls */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VNMULD, ARM_INS_VNMUL: vnmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VNMULH, ARM_INS_VNMUL: vnmul */ + { 0 } +}, + +{ /* ARM_VNMULS, ARM_INS_VNMUL: vnmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VORNd, ARM_INS_VORN: vorn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VORNq, ARM_INS_VORN: vorn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VORRd, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VORRiv2i32, ARM_INS_VORR: vorr */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VORRiv4i16, ARM_INS_VORR: vorr */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VORRiv4i32, ARM_INS_VORR: vorr */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VORRiv8i16, ARM_INS_VORR: vorr */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VORRq, ARM_INS_VMOV: vmov */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDf, ARM_INS_VPADD: vpadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDh, ARM_INS_VPADD: vpadd */ + { 0 } +}, + +{ /* ARM_VPADDi16, ARM_INS_VPADD: vpadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDi32, ARM_INS_VPADD: vpadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPADDi8, ARM_INS_VPADD: vpadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMAXf, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMAXh, ARM_INS_VPMAX: vpmax */ + { 0 } +}, + +{ /* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMINf, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMINh, ARM_INS_VPMIN: vpmin */ + { 0 } +}, + +{ /* ARM_VPMINs16, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMINs32, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMINs8, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMINu16, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMINu32, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VPMINu8, ARM_INS_VPMIN: vpmin */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRDMLAHslv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } +}, + +{ /* ARM_VQRDMLAHslv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } +}, + +{ /* ARM_VQRDMLAHslv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } +}, + +{ /* ARM_VQRDMLAHslv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } +}, + +{ /* ARM_VQRDMLAHv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } +}, + +{ /* ARM_VQRDMLAHv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } +}, + +{ /* ARM_VQRDMLAHv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } +}, + +{ /* ARM_VQRDMLAHv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ + { 0 } +}, + +{ /* ARM_VQRDMLSHslv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } +}, + +{ /* ARM_VQRDMLSHslv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } +}, + +{ /* ARM_VQRDMLSHslv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } +}, + +{ /* ARM_VQRDMLSHslv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } +}, + +{ /* ARM_VQRDMLSHv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } +}, + +{ /* ARM_VQRDMLSHv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } +}, + +{ /* ARM_VQRDMLSHv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } +}, + +{ /* ARM_VQRDMLSHv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ + { 0 } +}, + +{ /* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRECPEhd, ARM_INS_VRECPE: vrecpe */ + { 0 } +}, + +{ /* ARM_VRECPEhq, ARM_INS_VRECPE: vrecpe */ + { 0 } +}, + +{ /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRECPShd, ARM_INS_VRECPS: vrecps */ + { 0 } +}, + +{ /* ARM_VRECPShq, ARM_INS_VRECPS: vrecps */ + { 0 } +}, + +{ /* ARM_VREV16d8, ARM_INS_VREV16: vrev16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV16q8, ARM_INS_VREV16: vrev16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV32d16, ARM_INS_VREV32: vrev32 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV32d8, ARM_INS_VREV32: vrev32 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV32q16, ARM_INS_VREV32: vrev32 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV32q8, ARM_INS_VREV32: vrev32 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV64d16, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV64d32, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV64d8, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV64q16, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV64q32, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VREV64q8, ARM_INS_VREV64: vrev64 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTAD, ARM_INS_VRINTA: vrinta */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTAH, ARM_INS_VRINTA: vrinta */ + { 0 } +}, + +{ /* ARM_VRINTANDf, ARM_INS_VRINTA: vrinta */ + { 0 } +}, + +{ /* ARM_VRINTANDh, ARM_INS_VRINTA: vrinta */ + { 0 } +}, + +{ /* ARM_VRINTANQf, ARM_INS_VRINTA: vrinta */ + { 0 } +}, + +{ /* ARM_VRINTANQh, ARM_INS_VRINTA: vrinta */ + { 0 } +}, + +{ /* ARM_VRINTAS, ARM_INS_VRINTA: vrinta */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTMD, ARM_INS_VRINTM: vrintm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTMH, ARM_INS_VRINTM: vrintm */ + { 0 } +}, + +{ /* ARM_VRINTMNDf, ARM_INS_VRINTM: vrintm */ + { 0 } +}, + +{ /* ARM_VRINTMNDh, ARM_INS_VRINTM: vrintm */ + { 0 } +}, + +{ /* ARM_VRINTMNQf, ARM_INS_VRINTM: vrintm */ + { 0 } +}, + +{ /* ARM_VRINTMNQh, ARM_INS_VRINTM: vrintm */ + { 0 } +}, + +{ /* ARM_VRINTMS, ARM_INS_VRINTM: vrintm */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTND, ARM_INS_VRINTN: vrintn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTNH, ARM_INS_VRINTN: vrintn */ + { 0 } +}, + +{ /* ARM_VRINTNNDf, ARM_INS_VRINTN: vrintn */ + { 0 } +}, + +{ /* ARM_VRINTNNDh, ARM_INS_VRINTN: vrintn */ + { 0 } +}, + +{ /* ARM_VRINTNNQf, ARM_INS_VRINTN: vrintn */ + { 0 } +}, + +{ /* ARM_VRINTNNQh, ARM_INS_VRINTN: vrintn */ + { 0 } +}, + +{ /* ARM_VRINTNS, ARM_INS_VRINTN: vrintn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTPD, ARM_INS_VRINTP: vrintp */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTPH, ARM_INS_VRINTP: vrintp */ + { 0 } +}, + +{ /* ARM_VRINTPNDf, ARM_INS_VRINTP: vrintp */ + { 0 } +}, + +{ /* ARM_VRINTPNDh, ARM_INS_VRINTP: vrintp */ + { 0 } +}, + +{ /* ARM_VRINTPNQf, ARM_INS_VRINTP: vrintp */ + { 0 } +}, + +{ /* ARM_VRINTPNQh, ARM_INS_VRINTP: vrintp */ + { 0 } +}, + +{ /* ARM_VRINTPS, ARM_INS_VRINTP: vrintp */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTRD, ARM_INS_VRINTR: vrintr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTRH, ARM_INS_VRINTR: vrintr */ + { 0 } +}, + +{ /* ARM_VRINTRS, ARM_INS_VRINTR: vrintr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTXD, ARM_INS_VRINTX: vrintx */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTXH, ARM_INS_VRINTX: vrintx */ + { 0 } +}, + +{ /* ARM_VRINTXNDf, ARM_INS_VRINTX: vrintx */ + { 0 } +}, + +{ /* ARM_VRINTXNDh, ARM_INS_VRINTX: vrintx */ + { 0 } +}, + +{ /* ARM_VRINTXNQf, ARM_INS_VRINTX: vrintx */ + { 0 } +}, + +{ /* ARM_VRINTXNQh, ARM_INS_VRINTX: vrintx */ + { 0 } +}, + +{ /* ARM_VRINTXS, ARM_INS_VRINTX: vrintx */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTZD, ARM_INS_VRINTZ: vrintz */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRINTZH, ARM_INS_VRINTZ: vrintz */ + { 0 } +}, + +{ /* ARM_VRINTZNDf, ARM_INS_VRINTZ: vrintz */ + { 0 } +}, + +{ /* ARM_VRINTZNDh, ARM_INS_VRINTZ: vrintz */ + { 0 } +}, + +{ /* ARM_VRINTZNQf, ARM_INS_VRINTZ: vrintz */ + { 0 } +}, + +{ /* ARM_VRINTZNQh, ARM_INS_VRINTZ: vrintz */ + { 0 } +}, + +{ /* ARM_VRINTZS, ARM_INS_VRINTZ: vrintz */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSQRTEhd, ARM_INS_VRSQRTE: vrsqrte */ + { 0 } +}, + +{ /* ARM_VRSQRTEhq, ARM_INS_VRSQRTE: vrsqrte */ + { 0 } +}, + +{ /* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSQRTShd, ARM_INS_VRSQRTS: vrsqrts */ + { 0 } +}, + +{ /* ARM_VRSQRTShq, ARM_INS_VRSQRTS: vrsqrts */ + { 0 } +}, + +{ /* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSDOTD, ARM_INS_VSDOT: vsdot */ + { 0 } +}, + +{ /* ARM_VSDOTDI, ARM_INS_VSDOT: vsdot */ + { 0 } +}, + +{ /* ARM_VSDOTQ, ARM_INS_VSDOT: vsdot */ + { 0 } +}, + +{ /* ARM_VSDOTQI, ARM_INS_VSDOT: vsdot */ + { 0 } +}, + +{ /* ARM_VSELEQD, ARM_INS_VSELEQ: vseleq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSELEQH, ARM_INS_VSELEQ: vseleq */ + { 0 } +}, + +{ /* ARM_VSELEQS, ARM_INS_VSELEQ: vseleq */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSELGED, ARM_INS_VSELGE: vselge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSELGEH, ARM_INS_VSELGE: vselge */ + { 0 } +}, + +{ /* ARM_VSELGES, ARM_INS_VSELGE: vselge */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSELGTD, ARM_INS_VSELGT: vselgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSELGTH, ARM_INS_VSELGT: vselgt */ + { 0 } +}, + +{ /* ARM_VSELGTS, ARM_INS_VSELGT: vselgt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSELVSD, ARM_INS_VSELVS: vselvs */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSELVSH, ARM_INS_VSELVS: vselvs */ + { 0 } +}, + +{ /* ARM_VSELVSS, ARM_INS_VSELVS: vselvs */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSETLNi16, ARM_INS_VMOV: vmov */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSETLNi32, ARM_INS_FMDHR: fmdhr */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSETLNi8, ARM_INS_VMOV: vmov */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLLi16, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLLi32, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLLi8, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSHTOD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VSHTOH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VSHTOS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VSITOD, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSITOH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VSITOS, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSLIv16i8, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSLIv1i64, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSLIv2i32, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSLIv2i64, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSLIv4i16, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSLIv4i32, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSLIv8i16, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSLIv8i8, ARM_INS_VSLI: vsli */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSLTOD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VSLTOH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VSLTOS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VSQRTD, ARM_INS_VSQRT: vsqrt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSQRTH, ARM_INS_VSQRT: vsqrt */ + { 0 } +}, + +{ /* ARM_VSQRTS, ARM_INS_VSQRT: vsqrt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRIv16i8, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRIv1i64, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRIv2i32, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRIv2i64, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRIv4i16, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRIv4i32, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRIv8i16, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VSRIv8i8, ARM_INS_VSRI: vsri */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1LNd16, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1 */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VST1LNd32, ARM_INS_VST1: vst1 */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1 */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VST1LNd8, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1 */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d16, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d16Q, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d16T, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d16wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d32, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d32Q, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d32T, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d32wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d64, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d64Q, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d64T, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d64wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d8, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d8Q, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d8T, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1d8wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q16, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q16wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q32, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q32wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q64, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q64wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q8, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST1q8wb_register, ARM_INS_VST1: vst1 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2b16, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2b16wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2b32, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2b32wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2b8, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2b8wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2d16, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2d16wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2d32, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2d32wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2d8, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2d8wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2q16, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2q16wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2q32, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2q32wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2q8, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST2q8wb_register, ARM_INS_VST2: vst2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3d16, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3d16_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3d32, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3d32_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3d8, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3d8_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3q16, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3q16_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3q32, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3q32_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3q8, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST3q8_UPD, ARM_INS_VST3: vst3 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4d16, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4d16_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4d32, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4d32_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4d8, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4d8_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4q16, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4q16_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4q32, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4q32_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4q8, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VST4q8_UPD, ARM_INS_VST4: vst4 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSTMDDB_UPD, ARM_INS_VPUSH: vpush */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VSTMDIA, ARM_INS_VSTMIA: vstmia */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VSTMDIA_UPD, ARM_INS_VSTMIA: vstmia */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VSTMSDB_UPD, ARM_INS_VPUSH: vpush */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VSTMSIA, ARM_INS_VSTMIA: vstmia */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VSTMSIA_UPD, ARM_INS_VSTMIA: vstmia */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VSTRD, ARM_INS_VSTR: vstr */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VSTRH, ARM_INS_VSTR: vstr */ + { 0 } +}, + +{ /* ARM_VSTRS, ARM_INS_VSTR: vstr */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBD, ARM_INS_FSUBD: fsubd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBH, ARM_INS_VSUB: vsub */ + { 0 } +}, + +{ /* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBS, ARM_INS_FSUBS: fsubs */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBfd, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBfq, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBhd, ARM_INS_VSUB: vsub */ + { 0 } +}, + +{ /* ARM_VSUBhq, ARM_INS_VSUB: vsub */ + { 0 } +}, + +{ /* ARM_VSUBv16i8, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBv1i64, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBv2i32, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBv2i64, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBv4i16, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBv4i32, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBv8i16, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSUBv8i8, ARM_INS_VSUB: vsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VSWPd, ARM_INS_VSWP: vswp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VSWPq, ARM_INS_VSWP: vswp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTBL1, ARM_INS_VTBL: vtbl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTBL2, ARM_INS_VTBL: vtbl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTBL3, ARM_INS_VTBL: vtbl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTBL4, ARM_INS_VTBL: vtbl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTBX1, ARM_INS_VTBX: vtbx */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTBX2, ARM_INS_VTBX: vtbx */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTBX3, ARM_INS_VTBX: vtbx */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTBX4, ARM_INS_VTBX: vtbx */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTOSHD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTOSHH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VTOSHS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTOSIRD, ARM_INS_VCVTR: vcvtr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VTOSIRH, ARM_INS_VCVTR: vcvtr */ + { 0 } +}, + +{ /* ARM_VTOSIRS, ARM_INS_VCVTR: vcvtr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VTOSIZD, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VTOSIZH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VTOSIZS, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VTOSLD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTOSLH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VTOSLS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTOUHD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTOUHH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VTOUHS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTOUIRD, ARM_INS_VCVTR: vcvtr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VTOUIRH, ARM_INS_VCVTR: vcvtr */ + { 0 } +}, + +{ /* ARM_VTOUIRS, ARM_INS_VCVTR: vcvtr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VTOUIZD, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VTOUIZH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VTOUIZS, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VTOULD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTOULH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VTOULS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTRNd16, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTRNd32, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTRNd8, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTRNq16, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTRNq32, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTRNq8, ARM_INS_VTRN: vtrn */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VTSTv16i8, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTSTv2i32, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTSTv4i16, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTSTv4i32, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTSTv8i16, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VTSTv8i8, ARM_INS_VTST: vtst */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_VUDOTD, ARM_INS_VUDOT: vudot */ + { 0 } +}, + +{ /* ARM_VUDOTDI, ARM_INS_VUDOT: vudot */ + { 0 } +}, + +{ /* ARM_VUDOTQ, ARM_INS_VUDOT: vudot */ + { 0 } +}, + +{ /* ARM_VUDOTQI, ARM_INS_VUDOT: vudot */ + { 0 } +}, + +{ /* ARM_VUHTOD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VUHTOH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VUHTOS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VUITOD, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VUITOH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VUITOS, ARM_INS_VCVT: vcvt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_VULTOD, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VULTOH, ARM_INS_VCVT: vcvt */ + { 0 } +}, + +{ /* ARM_VULTOS, ARM_INS_VCVT: vcvt */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_VUZPd16, ARM_INS_VUZP: vuzp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VUZPd8, ARM_INS_VUZP: vuzp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VUZPq16, ARM_INS_VUZP: vuzp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VUZPq32, ARM_INS_VUZP: vuzp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VUZPq8, ARM_INS_VUZP: vuzp */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VZIPd16, ARM_INS_VZIP: vzip */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VZIPd8, ARM_INS_VZIP: vzip */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VZIPq16, ARM_INS_VZIP: vzip */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VZIPq32, ARM_INS_VZIP: vzip */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_VZIPq8, ARM_INS_VZIP: vzip */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_sysLDMDA, ARM_INS_LDMDA: ldmda */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_sysLDMDA_UPD, ARM_INS_LDMDA: ldmda */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_sysLDMDB, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_sysLDMDB_UPD, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_sysLDMIA, ARM_INS_LDM: ldm */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_sysLDMIA_UPD, ARM_INS_LDM: ldm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_sysLDMIB, ARM_INS_LDMIB: ldmib */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_sysLDMIB_UPD, ARM_INS_LDMIB: ldmib */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_sysSTMDA, ARM_INS_STMDA: stmda */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_sysSTMDA_UPD, ARM_INS_STMDA: stmda */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_sysSTMDB, ARM_INS_STMDB: stmdb */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_sysSTMDB_UPD, ARM_INS_STMDB: stmdb */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_sysSTMIA, ARM_INS_STM: stm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_sysSTMIA_UPD, ARM_INS_STM: stm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_sysSTMIB, ARM_INS_STMIB: stmib */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_sysSTMIB_UPD, ARM_INS_STMIB: stmib */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ADCri, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ADCrr, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ADCrs, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ADDri, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ADDri12, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ADDrr, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ADDrs, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ADR, ARM_INS_ADD: add */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2ANDri, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ANDrr, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ANDrs, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ASRri, ARM_INS_ASR: asr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ASRrr, ARM_INS_ASR: asr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2B, ARM_INS_B: b */ + { 0 } +}, + +{ /* ARM_t2BFC, ARM_INS_BFC: bfc */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2BFI, ARM_INS_BFI: bfi */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2BICri, ARM_INS_AND: and */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2BICrr, ARM_INS_BIC: bic */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2BICrs, ARM_INS_BIC: bic */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2BXJ, ARM_INS_BXJ: bxj */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2Bcc, ARM_INS_B: b */ + { 0 } +}, + +{ /* ARM_t2CDP, ARM_INS_CDP: cdp */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_t2CDP2, ARM_INS_CDP2: cdp2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_t2CLREX, ARM_INS_CLREX: clrex */ + { 0 } +}, + +{ /* ARM_t2CLZ, ARM_INS_CLZ: clz */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2CMNri, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2CMNzrr, ARM_INS_CMN: cmn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2CMNzrs, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2CMPri, ARM_INS_CMN: cmn */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2CMPrr, ARM_INS_CMP: cmp */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2CMPrs, ARM_INS_CMP: cmp */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2CPS1p, ARM_INS_CPS: cps */ + { 0 } +}, + +{ /* ARM_t2CPS2p, ARM_INS_CPS: cps */ + { 0 } +}, + +{ /* ARM_t2CPS3p, ARM_INS_CPS: cps */ + { 0 } +}, + +{ /* ARM_t2CRC32B, ARM_INS_CRC32B: crc32b */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2CRC32CB, ARM_INS_CRC32CB: crc32cb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2CRC32CH, ARM_INS_CRC32CH: crc32ch */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2CRC32CW, ARM_INS_CRC32CW: crc32cw */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2CRC32H, ARM_INS_CRC32H: crc32h */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2CRC32W, ARM_INS_CRC32W: crc32w */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2DBG, ARM_INS_DBG: dbg */ + { 0 } +}, + +{ /* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1 */ + { 0 } +}, + +{ /* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2 */ + { 0 } +}, + +{ /* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3 */ + { 0 } +}, + +{ /* ARM_t2DMB, ARM_INS_DMB: dmb */ + { 0 } +}, + +{ /* ARM_t2DSB, ARM_INS_DFB: dfb */ + { 0 } +}, + +{ /* ARM_t2EORri, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2EORrr, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2EORrs, ARM_INS_EOR: eor */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2HINT, ARM_INS_CSDB: csdb */ + { 0 } +}, + +{ /* ARM_t2HVC, ARM_INS_HVC: hvc */ + { 0 } +}, + +{ /* ARM_t2ISB, ARM_INS_ISB: isb */ + { 0 } +}, + +{ /* ARM_t2IT, ARM_INS_IT: it */ + { 0 } +}, + +{ /* ARM_t2LDA, ARM_INS_LDA: lda */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDAB, ARM_INS_LDAB: ldab */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDAEX, ARM_INS_LDAEX: ldaex */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDAEXB, ARM_INS_LDAEXB: ldaexb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDAEXD, ARM_INS_LDAEXD: ldaexd */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDAEXH, ARM_INS_LDAEXH: ldaexh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDAH, ARM_INS_LDAH: ldah */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC_POST, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDC_PRE, ARM_INS_LDC: ldc */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDMDB, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDMIA, ARM_INS_LDM: ldm */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDMIA_UPD, ARM_INS_LDM: ldm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRBT, ARM_INS_LDRBT: ldrbt */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRB_POST, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRB_PRE, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRBi12, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRBi8, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRBpci, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRBs, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRD_POST, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRD_PRE, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRDi8, ARM_INS_LDRD: ldrd */ + { CS_AC_WRITE, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDREX, ARM_INS_LDREX: ldrex */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDREXB, ARM_INS_LDREXB: ldrexb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDREXD, ARM_INS_LDREXD: ldrexd */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDREXH, ARM_INS_LDREXH: ldrexh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRHT, ARM_INS_LDRHT: ldrht */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRH_POST, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRH_PRE, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRHi12, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRHi8, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRHpci, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRHs, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSBT, ARM_INS_LDRSBT: ldrsbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSB_POST, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSBi12, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSBi8, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSBpci, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSBs, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSHT, ARM_INS_LDRSHT: ldrsht */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSH_POST, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSHi12, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSHi8, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSHpci, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRSHs, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LDRT, ARM_INS_LDRT: ldrt */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDR_POST, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDR_PRE, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRi12, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRi8, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRpci, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2LDRs, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LSLri, ARM_INS_LSL: lsl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LSLrr, ARM_INS_LSL: lsl */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LSRri, ARM_INS_LSR: lsr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2LSRrr, ARM_INS_LSR: lsr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MCR, ARM_INS_MCR: mcr */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_t2MCR2, ARM_INS_MCR2: mcr2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_t2MCRR, ARM_INS_MCRR: mcrr */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MCRR2, ARM_INS_MCRR2: mcrr2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MLA, ARM_INS_MLA: mla */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MLS, ARM_INS_MLS: mls */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MOVTi16, ARM_INS_MOVT: movt */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2MOVi, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2MOVi16, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2MOVr, ARM_INS_LSL: lsl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MOVsra_flag, ARM_INS_ASR: asrs${p}.w $rd $rm #1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MOVsrl_flag, ARM_INS_LSR: lsrs${p}.w $rd $rm #1 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MRC, ARM_INS_MRC: mrc */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_t2MRC2, ARM_INS_MRC2: mrc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } +}, + +{ /* ARM_t2MRRC, ARM_INS_MRRC: mrrc */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MRRC2, ARM_INS_MRRC2: mrrc2 */ + { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MRS_AR, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2MRS_M, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2MRSbanked, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2MRSsys_AR, ARM_INS_MRS: mrs */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2MSR_AR, ARM_INS_MSR: msr */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2MSR_M, ARM_INS_MSR: msr */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2MSRbanked, ARM_INS_MSR: msr */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2MUL, ARM_INS_MUL: mul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MVNi, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2MVNr, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2MVNs, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2ORNri, ARM_INS_ORN: orn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ORNrr, ARM_INS_ORN: orn */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ORNrs, ARM_INS_ORN: orn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ORRri, ARM_INS_ORN: orn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ORRrr, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2ORRrs, ARM_INS_ORR: orr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2PKHBT, ARM_INS_PKHBT: pkhbt */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2PKHTB, ARM_INS_PKHTB: pkhtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLDWi12, ARM_INS_PLDW: pldw */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLDWi8, ARM_INS_PLDW: pldw */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLDWs, ARM_INS_PLDW: pldw */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLDi12, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLDi8, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLDpci, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLDs, ARM_INS_PLD: pld */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLIi12, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLIi8, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLIpci, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2PLIs, ARM_INS_PLI: pli */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2QADD, ARM_INS_QADD: qadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2QADD16, ARM_INS_QADD16: qadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2QADD8, ARM_INS_QADD8: qadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2QASX, ARM_INS_QASX: qasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2QDADD, ARM_INS_QDADD: qdadd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2QSAX, ARM_INS_QSAX: qsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2QSUB, ARM_INS_QSUB: qsub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2QSUB16, ARM_INS_QSUB16: qsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2RBIT, ARM_INS_RBIT: rbit */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2REV, ARM_INS_REV: rev */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2REV16, ARM_INS_REV16: rev16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2REVSH, ARM_INS_REVSH: revsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2RFEDB, ARM_INS_RFEDB: rfedb */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2RFEDBW, ARM_INS_RFEDB: rfedb */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2RFEIA, ARM_INS_RFEIA: rfeia */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2RFEIAW, ARM_INS_RFEIA: rfeia */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2RORri, ARM_INS_ROR: ror */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2RORrr, ARM_INS_ROR: ror */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2RRX, ARM_INS_RRX: rrx */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2RSBri, ARM_INS_NEG: neg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2RSBrr, ARM_INS_RSB: rsb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2RSBrs, ARM_INS_RSB: rsb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SADD16, ARM_INS_SADD16: sadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SADD8, ARM_INS_SADD8: sadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SASX, ARM_INS_SASX: sasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SBCri, ARM_INS_ADC: adc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SBCrr, ARM_INS_SBC: sbc */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SBCrs, ARM_INS_SBC: sbc */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SBFX, ARM_INS_SBFX: sbfx */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SDIV, ARM_INS_SDIV: sdiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SEL, ARM_INS_SEL: sel */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SETPAN, ARM_INS_SETPAN: setpan */ + { 0 } +}, + +{ /* ARM_t2SG, ARM_INS_SG: sg */ + { 0 } +}, + +{ /* ARM_t2SHADD16, ARM_INS_SHADD16: shadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SHASX, ARM_INS_SHASX: shasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SHSAX, ARM_INS_SHSAX: shsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SHSUB8, ARM_INS_SHSUB8: shsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMC, ARM_INS_SMC: smc */ + { 0 } +}, + +{ /* ARM_t2SMLABB, ARM_INS_SMLABB: smlabb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLABT, ARM_INS_SMLABT: smlabt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLAD, ARM_INS_SMLAD: smlad */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLADX, ARM_INS_SMLADX: smladx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLAL, ARM_INS_SMLAL: smlal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLALBB, ARM_INS_SMLALBB: smlalbb */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLALBT, ARM_INS_SMLALBT: smlalbt */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLALD, ARM_INS_SMLALD: smlald */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLALDX, ARM_INS_SMLALDX: smlaldx */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLALTB, ARM_INS_SMLALTB: smlaltb */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLALTT, ARM_INS_SMLALTT: smlaltt */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLATB, ARM_INS_SMLATB: smlatb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLATT, ARM_INS_SMLATT: smlatt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLSD, ARM_INS_SMLSD: smlsd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMMLA, ARM_INS_SMMLA: smmla */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMMLAR, ARM_INS_SMMLAR: smmlar */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMMLS, ARM_INS_SMMLS: smmls */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMMLSR, ARM_INS_SMMLSR: smmlsr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMMUL, ARM_INS_SMMUL: smmul */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMMULR, ARM_INS_SMMULR: smmulr */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMUADX, ARM_INS_SMUADX: smuadx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMULBB, ARM_INS_SMULBB: smulbb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMULBT, ARM_INS_SMULBT: smulbt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMULL, ARM_INS_SMULL: smull */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMULTB, ARM_INS_SMULTB: smultb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMULTT, ARM_INS_SMULTT: smultt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMULWB, ARM_INS_SMULWB: smulwb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMULWT, ARM_INS_SMULWT: smulwt */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMUSD, ARM_INS_SMUSD: smusd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SRSDB, ARM_INS_SRSDB: srsdb */ + { 0 } +}, + +{ /* ARM_t2SRSDB_UPD, ARM_INS_SRSDB: srsdb */ + { 0 } +}, + +{ /* ARM_t2SRSIA, ARM_INS_SRSIA: srsia */ + { 0 } +}, + +{ /* ARM_t2SRSIA_UPD, ARM_INS_SRSIA: srsia */ + { 0 } +}, + +{ /* ARM_t2SSAT, ARM_INS_SSAT: ssat */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2SSAT16, ARM_INS_SSAT16: ssat16 */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SSAX, ARM_INS_SSAX: ssax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SSUB16, ARM_INS_SSUB16: ssub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC2_POST, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC2_PRE, ARM_INS_STC2: stc2 */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STCL_POST, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC_OFFSET, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC_OPTION, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC_POST, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STC_PRE, ARM_INS_STC: stc */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STL, ARM_INS_STL: stl */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STLB, ARM_INS_STLB: stlb */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STLEX, ARM_INS_STLEX: stlex */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STLEXD, ARM_INS_STLEXD: stlexd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STLH, ARM_INS_STLH: stlh */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STMDB, ARM_INS_STMDB: stmdb */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STMDB_UPD, ARM_INS_PUSH: push */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STMIA, ARM_INS_STM: stm */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STMIA_UPD, ARM_INS_STM: stm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STRBT, ARM_INS_STRBT: strbt */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRB_POST, ARM_INS_STRB: strb */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2STRB_PRE, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRBi12, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRBi8, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRBs, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRD_POST, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STRD_PRE, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STRDi8, ARM_INS_STRD: strd */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STREX, ARM_INS_STREX: strex */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STREXB, ARM_INS_STREXB: strexb */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STREXD, ARM_INS_STREXD: strexd */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STREXH, ARM_INS_STREXH: strexh */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2STRHT, ARM_INS_STRHT: strht */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRH_POST, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRH_PRE, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRHi12, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRHi8, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRHs, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRT, ARM_INS_STRT: strt */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STR_POST, ARM_INS_STR: str */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2STR_PRE, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRi12, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRi8, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2STRs, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2SUBS_PC_LR, ARM_INS_ERET: eret */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SUBri, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SUBri12, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SUBrr, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SUBrs, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SXTAB, ARM_INS_SXTAB: sxtab */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SXTAB16, ARM_INS_SXTAB16: sxtab16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SXTAH, ARM_INS_SXTAH: sxtah */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SXTB, ARM_INS_SXTB: sxtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SXTB16, ARM_INS_SXTB16: sxtb16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2SXTH, ARM_INS_SXTH: sxth */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2TBB, ARM_INS_TBB: tbb */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2TBH, ARM_INS_TBH: tbh */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2TEQri, ARM_INS_TEQ: teq */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2TEQrr, ARM_INS_TEQ: teq */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2TEQrs, ARM_INS_TEQ: teq */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2TSB, ARM_INS_TSB: tsb */ + { 0 } +}, + +{ /* ARM_t2TSTri, ARM_INS_TST: tst */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2TSTrr, ARM_INS_TST: tst */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2TSTrs, ARM_INS_TST: tst */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_t2TT, ARM_INS_TT: tt */ + { 0 } +}, + +{ /* ARM_t2TTA, ARM_INS_TTA: tta */ + { 0 } +}, + +{ /* ARM_t2TTAT, ARM_INS_TTAT: ttat */ + { 0 } +}, + +{ /* ARM_t2TTT, ARM_INS_TTT: ttt */ + { 0 } +}, + +{ /* ARM_t2UADD16, ARM_INS_UADD16: uadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UADD8, ARM_INS_UADD8: uadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UASX, ARM_INS_UASX: uasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UBFX, ARM_INS_UBFX: ubfx */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UDF, ARM_INS_UDF: udf */ + { 0 } +}, + +{ /* ARM_t2UDIV, ARM_INS_UDIV: udiv */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UHADD16, ARM_INS_UHADD16: uhadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UHADD8, ARM_INS_UHADD8: uhadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UHASX, ARM_INS_UHASX: uhasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UHSAX, ARM_INS_UHSAX: uhsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UHSUB16, ARM_INS_UHSUB16: uhsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UHSUB8, ARM_INS_UHSUB8: uhsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UMAAL, ARM_INS_UMAAL: umaal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UMLAL, ARM_INS_UMLAL: umlal */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UMULL, ARM_INS_UMULL: umull */ + { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UQADD16, ARM_INS_UQADD16: uqadd16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UQADD8, ARM_INS_UQADD8: uqadd8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UQASX, ARM_INS_UQASX: uqasx */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UQSAX, ARM_INS_UQSAX: uqsax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UQSUB16, ARM_INS_UQSUB16: uqsub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UQSUB8, ARM_INS_UQSUB8: uqsub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2USAD8, ARM_INS_USAD8: usad8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2USADA8, ARM_INS_USADA8: usada8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2USAT, ARM_INS_USAT: usat */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2USAT16, ARM_INS_USAT16: usat16 */ + { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2USAX, ARM_INS_USAX: usax */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2USUB16, ARM_INS_USUB16: usub16 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2USUB8, ARM_INS_USUB8: usub8 */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UXTAB, ARM_INS_UXTAB: uxtab */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UXTAB16, ARM_INS_UXTAB16: uxtab16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UXTAH, ARM_INS_UXTAH: uxtah */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_t2UXTB, ARM_INS_UXTB: uxtb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2UXTB16, ARM_INS_UXTB16: uxtb16 */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_t2UXTH, ARM_INS_UXTH: uxth */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tADC, ARM_INS_ADC: adc */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tADDhirr, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tADDi3, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tADDi8, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_tADDrSP, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_tADDrSPi, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tADDrr, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_tADDspi, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_tADDspr, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tADR, ARM_INS_ADR: adr */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tAND, ARM_INS_AND: and */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tASRri, ARM_INS_ASR: asr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tASRrr, ARM_INS_ASR: asr */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tB, ARM_INS_B: b */ + { 0 } +}, + +{ /* ARM_tBIC, ARM_INS_BIC: bic */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tBKPT, ARM_INS_BKPT: bkpt */ + { 0 } +}, + +{ /* ARM_tBL, ARM_INS_BL: bl */ + { 0 } +}, + +{ /* ARM_tBLXNSr, ARM_INS_BLXNS: blxns */ + { 0 } +}, + +{ /* ARM_tBLXi, ARM_INS_BLX: blx */ + { 0 } +}, + +{ /* ARM_tBLXr, ARM_INS_BLX: blx */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_tBX, ARM_INS_BX: bx */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_tBXNS, ARM_INS_BXNS: bxns */ + { 0 } +}, + +{ /* ARM_tBcc, ARM_INS_B: b */ + { 0 } +}, + +{ /* ARM_tCBNZ, ARM_INS_CBNZ: cbnz */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_tCBZ, ARM_INS_CBZ: cbz */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_tCMNz, ARM_INS_CMN: cmn */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_tCMPhir, ARM_INS_CMP: cmp */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_tCMPi8, ARM_INS_CMP: cmp */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_tCMPr, ARM_INS_CMP: cmp */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_tCPS, ARM_INS_CPS: cps */ + { 0 } +}, + +{ /* ARM_tEOR, ARM_INS_EOR: eor */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tHINT, ARM_INS_HINT: hint */ + { 0 } +}, + +{ /* ARM_tHLT, ARM_INS_HLT: hlt */ + { 0 } +}, + +{ /* ARM_tLDMIA, ARM_INS_LDM: ldm */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tLDRBi, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tLDRBr, ARM_INS_LDRB: ldrb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tLDRHi, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tLDRHr, ARM_INS_LDRH: ldrh */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tLDRSB, ARM_INS_LDRSB: ldrsb */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tLDRSH, ARM_INS_LDRSH: ldrsh */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tLDRi, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tLDRpci, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tLDRr, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tLDRspi, ARM_INS_LDR: ldr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tLSLri, ARM_INS_LSL: lsl */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tLSLrr, ARM_INS_LSL: lsl */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tLSRri, ARM_INS_LSR: lsr */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tLSRrr, ARM_INS_LSR: lsr */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tMOVSr, ARM_INS_MOVS: movs */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tMOVi8, ARM_INS_MOV: mov */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tMOVr, ARM_INS_MOV: mov */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tMUL, ARM_INS_MUL: mul */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_tMVN, ARM_INS_MVN: mvn */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tORR, ARM_INS_ORR: orr */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tPOP, ARM_INS_POP: pop */ + { CS_AC_WRITE, 0 } +}, + +{ /* ARM_tPUSH, ARM_INS_PUSH: push */ + { CS_AC_READ, 0 } +}, + +{ /* ARM_tREV, ARM_INS_REV: rev */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tREV16, ARM_INS_REV16: rev16 */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tREVSH, ARM_INS_REVSH: revsh */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tROR, ARM_INS_ROR: ror */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tRSB, ARM_INS_NEG: neg */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tSBC, ARM_INS_SBC: sbc */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tSETEND, ARM_INS_SETEND: setend */ + { 0 } +}, + +{ /* ARM_tSTMIA_UPD, ARM_INS_STM: stm */ + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tSTRBi, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_tSTRBr, ARM_INS_STRB: strb */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_tSTRHi, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_tSTRHr, ARM_INS_STRH: strh */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_tSTRi, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_tSTRr, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_tSTRspi, ARM_INS_STR: str */ + { CS_AC_READ, CS_AC_WRITE, 0 } +}, + +{ /* ARM_tSUBi3, ARM_INS_ADD: add */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tSUBi8, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_tSUBrr, ARM_INS_SUB: sub */ + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_tSUBspi, ARM_INS_ADD: add */ + { CS_AC_READ | CS_AC_WRITE, 0 } +}, + +{ /* ARM_tSVC, ARM_INS_SVC: svc */ + { 0 } +}, + +{ /* ARM_tSXTB, ARM_INS_SXTB: sxtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tSXTH, ARM_INS_SXTH: sxth */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tTRAP, ARM_INS_TRAP: trap */ + { 0 } +}, + +{ /* ARM_tTST, ARM_INS_TST: tst */ + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* ARM_tUDF, ARM_INS_UDF: udf */ + { 0 } +}, + +{ /* ARM_tUXTB, ARM_INS_UXTB: uxtb */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* ARM_tUXTH, ARM_INS_UXTH: uxth */ + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + diff --git a/capstone/arch/ARM/ARMModule.c b/capstone/arch/ARM/ARMModule.c new file mode 100644 index 000000000..0ecadd802 --- /dev/null +++ b/capstone/arch/ARM/ARMModule.c @@ -0,0 +1,63 @@ +/* Capstone Disassembly Engine */ +/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */ + +#ifdef CAPSTONE_HAS_ARM + +#include "../../cs_priv.h" +#include "../../MCRegisterInfo.h" +#include "ARMDisassembler.h" +#include "ARMInstPrinter.h" +#include "ARMMapping.h" +#include "ARMModule.h" + +cs_err ARM_global_init(cs_struct *ud) +{ + MCRegisterInfo *mri; + mri = cs_mem_malloc(sizeof(*mri)); + + ARM_init(mri); + ARM_getRegName(ud, 0); // use default get_regname + + ud->printer = ARM_printInst; + ud->printer_info = mri; + ud->reg_name = ARM_reg_name; + ud->insn_id = ARM_get_insn_id; + ud->insn_name = ARM_insn_name; + ud->group_name = ARM_group_name; + ud->post_printer = ARM_post_printer; +#ifndef CAPSTONE_DIET + ud->reg_access = ARM_reg_access; +#endif + + if (ud->mode & CS_MODE_THUMB) + ud->disasm = Thumb_getInstruction; + else + ud->disasm = ARM_getInstruction; + + return CS_ERR_OK; +} + +cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + switch(type) { + case CS_OPT_MODE: + if (value & CS_MODE_THUMB) + handle->disasm = Thumb_getInstruction; + else + handle->disasm = ARM_getInstruction; + + handle->mode = (cs_mode)value; + + break; + case CS_OPT_SYNTAX: + ARM_getRegName(handle, (int)value); + handle->syntax = (int)value; + break; + default: + break; + } + + return CS_ERR_OK; +} + +#endif diff --git a/capstone/arch/ARM/ARMModule.h b/capstone/arch/ARM/ARMModule.h new file mode 100644 index 000000000..f84497212 --- /dev/null +++ b/capstone/arch/ARM/ARMModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */ + +#ifndef CS_ARM_MODULE_H +#define CS_ARM_MODULE_H + +#include "../../utils.h" + +cs_err ARM_global_init(cs_struct *ud); +cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif |