diff options
Diffstat (limited to 'roms/edk2/ArmPkg/Include')
33 files changed, 3996 insertions, 0 deletions
diff --git a/roms/edk2/ArmPkg/Include/AsmMacroExport.inc b/roms/edk2/ArmPkg/Include/AsmMacroExport.inc new file mode 100644 index 000000000..615feee54 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/AsmMacroExport.inc @@ -0,0 +1,23 @@ +;%HEADER%
+;/** @file
+; Macros to centralize the EXPORT, AREA, and definition of an assembly
+; function. The AREA prefix is required to put the function in its own
+; section so that removal of unused functions in the final link is performed.
+; This provides equivalent functionality to the compiler's --split-sections
+; option.
+;
+; Copyright (c) 2015 HP Development Company, L.P.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;**/
+
+
+ MACRO
+ RVCT_ASM_EXPORT $func
+ EXPORT $func
+ AREA s_$func, CODE, READONLY
+$func
+ MEND
+
+ END
diff --git a/roms/edk2/ArmPkg/Include/AsmMacroIoLib.h b/roms/edk2/ArmPkg/Include/AsmMacroIoLib.h new file mode 100644 index 000000000..e3576c8be --- /dev/null +++ b/roms/edk2/ArmPkg/Include/AsmMacroIoLib.h @@ -0,0 +1,39 @@ +/** @file
+ Macros to work around lack of Apple support for LDR register, =expr
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#ifndef __MACRO_IO_LIB_H__
+#define __MACRO_IO_LIB_H__
+
+#define _ASM_FUNC(Name, Section) \
+ .global Name ; \
+ .section #Section, "ax" ; \
+ .type Name, %function ; \
+ .p2align 2 ; \
+ Name:
+
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+
+#define MOV32(Reg, Val) \
+ movw Reg, #(Val) & 0xffff ; \
+ movt Reg, #(Val) >> 16
+
+#define ADRL(Reg, Sym) \
+ movw Reg, #:lower16:(Sym) - (. + 16) ; \
+ movt Reg, #:upper16:(Sym) - (. + 12) ; \
+ add Reg, Reg, pc
+
+#define LDRL(Reg, Sym) \
+ movw Reg, #:lower16:(Sym) - (. + 16) ; \
+ movt Reg, #:upper16:(Sym) - (. + 12) ; \
+ ldr Reg, [pc, Reg]
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/AsmMacroIoLib.inc b/roms/edk2/ArmPkg/Include/AsmMacroIoLib.inc new file mode 100644 index 000000000..66b8d3d33 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/AsmMacroIoLib.inc @@ -0,0 +1,33 @@ +;%HEADER%
+;/** @file
+; Macros to work around lack of Apple support for LDR register, =expr
+;
+; Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
+; Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;**/
+
+
+ MACRO
+ adrll $Reg, $Symbol
+ add $Reg, pc, #-8
+ RELOC R_ARM_ALU_PC_G0_NC, $Symbol
+ add $Reg, $Reg, #-4
+ RELOC R_ARM_ALU_PC_G1_NC, $Symbol
+ add $Reg, $Reg, #0
+ RELOC R_ARM_ALU_PC_G2, $Symbol
+ MEND
+
+ MACRO
+ ldrl $Reg, $Symbol
+ add $Reg, pc, #-8
+ RELOC R_ARM_ALU_PC_G0_NC, $Symbol
+ add $Reg, $Reg, #-4
+ RELOC R_ARM_ALU_PC_G1_NC, $Symbol
+ ldr $Reg, [$Reg, #0]
+ RELOC R_ARM_LDR_PC_G2, $Symbol
+ MEND
+
+ END
diff --git a/roms/edk2/ArmPkg/Include/AsmMacroIoLibV8.h b/roms/edk2/ArmPkg/Include/AsmMacroIoLibV8.h new file mode 100644 index 000000000..bcc0d8daf --- /dev/null +++ b/roms/edk2/ArmPkg/Include/AsmMacroIoLibV8.h @@ -0,0 +1,57 @@ +/** @file
+ Macros to work around lack of Clang support for LDR register, =expr
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#ifndef __MACRO_IO_LIBV8_H__
+#define __MACRO_IO_LIBV8_H__
+
+// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
+// This only selects between EL1 and EL2, else we die.
+// Provide the Macro with a safe temp xreg to use.
+#define EL1_OR_EL2(SAFE_XREG) \
+ mrs SAFE_XREG, CurrentEL ;\
+ cmp SAFE_XREG, #0x8 ;\
+ b.gt . ;\
+ b.eq 2f ;\
+ cbnz SAFE_XREG, 1f ;\
+ b . ;// We should never get here
+
+
+// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
+// This only selects between EL1 and EL2 and EL3, else we die.
+// Provide the Macro with a safe temp xreg to use.
+#define EL1_OR_EL2_OR_EL3(SAFE_XREG) \
+ mrs SAFE_XREG, CurrentEL ;\
+ cmp SAFE_XREG, #0x8 ;\
+ b.gt 3f ;\
+ b.eq 2f ;\
+ cbnz SAFE_XREG, 1f ;\
+ b . ;// We should never get here
+
+#define _ASM_FUNC(Name, Section) \
+ .global Name ; \
+ .section #Section, "ax" ; \
+ .type Name, %function ; \
+ Name:
+
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+
+#define MOV32(Reg, Val) \
+ movz Reg, (Val) >> 16, lsl #16 ; \
+ movk Reg, (Val) & 0xffff
+
+#define MOV64(Reg, Val) \
+ movz Reg, (Val) >> 48, lsl #48 ; \
+ movk Reg, ((Val) >> 32) & 0xffff, lsl #32 ; \
+ movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \
+ movk Reg, (Val) & 0xffff
+
+#endif // __MACRO_IO_LIBV8_H__
diff --git a/roms/edk2/ArmPkg/Include/Chipset/AArch64.h b/roms/edk2/ArmPkg/Include/Chipset/AArch64.h new file mode 100644 index 000000000..0ade5cce9 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Chipset/AArch64.h @@ -0,0 +1,237 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __AARCH64_H__
+#define __AARCH64_H__
+
+#include <Chipset/AArch64Mmu.h>
+
+// ARM Interrupt ID in Exception Table
+#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
+
+// CPACR - Coprocessor Access Control Register definitions
+#define CPACR_TTA_EN (1UL << 28)
+#define CPACR_FPEN_EL1 (1UL << 20)
+#define CPACR_FPEN_FULL (3UL << 20)
+#define CPACR_CP_FULL_ACCESS 0x300000
+
+// Coprocessor Trap Register (CPTR)
+#define AARCH64_CPTR_TFP (1 << 10)
+
+// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
+#define AARCH64_PFR0_FP (0xF << 16)
+#define AARCH64_PFR0_GIC (0xF << 24)
+
+// SCR - Secure Configuration Register definitions
+#define SCR_NS (1 << 0)
+#define SCR_IRQ (1 << 1)
+#define SCR_FIQ (1 << 2)
+#define SCR_EA (1 << 3)
+#define SCR_FW (1 << 4)
+#define SCR_AW (1 << 5)
+
+// MIDR - Main ID Register definitions
+#define ARM_CPU_TYPE_SHIFT 4
+#define ARM_CPU_TYPE_MASK 0xFFF
+#define ARM_CPU_TYPE_AEMv8 0xD0F
+#define ARM_CPU_TYPE_A53 0xD03
+#define ARM_CPU_TYPE_A57 0xD07
+#define ARM_CPU_TYPE_A72 0xD08
+#define ARM_CPU_TYPE_A15 0xC0F
+#define ARM_CPU_TYPE_A9 0xC09
+#define ARM_CPU_TYPE_A7 0xC07
+#define ARM_CPU_TYPE_A5 0xC05
+
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
+
+// Hypervisor Configuration Register
+#define ARM_HCR_FMO BIT3
+#define ARM_HCR_IMO BIT4
+#define ARM_HCR_AMO BIT5
+#define ARM_HCR_TSC BIT19
+#define ARM_HCR_TGE BIT27
+
+// Exception Syndrome Register
+#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
+#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
+
+#define AARCH64_ESR_EC_SMC32 (0x13 << 26)
+#define AARCH64_ESR_EC_SMC64 (0x17 << 26)
+
+// AArch64 Exception Level
+#define AARCH64_EL3 0xC
+#define AARCH64_EL2 0x8
+#define AARCH64_EL1 0x4
+
+// Saved Program Status Register definitions
+#define SPSR_A BIT8
+#define SPSR_I BIT7
+#define SPSR_F BIT6
+
+#define SPSR_AARCH32 BIT4
+
+#define SPSR_AARCH32_MODE_USER 0x0
+#define SPSR_AARCH32_MODE_FIQ 0x1
+#define SPSR_AARCH32_MODE_IRQ 0x2
+#define SPSR_AARCH32_MODE_SVC 0x3
+#define SPSR_AARCH32_MODE_ABORT 0x7
+#define SPSR_AARCH32_MODE_UNDEF 0xB
+#define SPSR_AARCH32_MODE_SYS 0xF
+
+// Counter-timer Hypervisor Control register definitions
+#define CNTHCTL_EL2_EL1PCTEN BIT0
+#define CNTHCTL_EL2_EL1PCEN BIT1
+
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
+
+// Vector table offset definitions
+#define ARM_VECTOR_CUR_SP0_SYNC 0x000
+#define ARM_VECTOR_CUR_SP0_IRQ 0x080
+#define ARM_VECTOR_CUR_SP0_FIQ 0x100
+#define ARM_VECTOR_CUR_SP0_SERR 0x180
+
+#define ARM_VECTOR_CUR_SPx_SYNC 0x200
+#define ARM_VECTOR_CUR_SPx_IRQ 0x280
+#define ARM_VECTOR_CUR_SPx_FIQ 0x300
+#define ARM_VECTOR_CUR_SPx_SERR 0x380
+
+#define ARM_VECTOR_LOW_A64_SYNC 0x400
+#define ARM_VECTOR_LOW_A64_IRQ 0x480
+#define ARM_VECTOR_LOW_A64_FIQ 0x500
+#define ARM_VECTOR_LOW_A64_SERR 0x580
+
+#define ARM_VECTOR_LOW_A32_SYNC 0x600
+#define ARM_VECTOR_LOW_A32_IRQ 0x680
+#define ARM_VECTOR_LOW_A32_FIQ 0x700
+#define ARM_VECTOR_LOW_A32_SERR 0x780
+
+#define VECTOR_BASE(tbl) \
+ .section .text.##tbl##,"ax"; \
+ .align 11; \
+ .org 0x0; \
+ GCC_ASM_EXPORT(tbl); \
+ ASM_PFX(tbl): \
+
+#define VECTOR_ENTRY(tbl, off) \
+ .org off
+
+#define VECTOR_END(tbl) \
+ .org 0x800; \
+ .previous
+
+VOID
+EFIAPI
+ArmEnableSWPInstruction (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadCbar (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadTpidrurw (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteTpidrurw (
+ UINTN Value
+ );
+
+UINTN
+EFIAPI
+ArmGetTCR (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmSetTCR (
+ UINTN Value
+ );
+
+UINTN
+EFIAPI
+ArmGetMAIR (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmSetMAIR (
+ UINTN Value
+ );
+
+VOID
+EFIAPI
+ArmDisableAlignmentCheck (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableAlignmentCheck (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableStackAlignmentCheck (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableStackAlignmentCheck (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableAllExceptions (
+ VOID
+ );
+
+VOID
+ArmWriteHcr (
+ IN UINTN Hcr
+ );
+
+UINTN
+ArmReadHcr (
+ VOID
+ );
+
+UINTN
+ArmReadCurrentEL (
+ VOID
+ );
+
+UINTN
+ArmWriteCptr (
+ IN UINT64 Cptr
+ );
+
+UINT32
+ArmReadCntHctl (
+ VOID
+ );
+
+VOID
+ArmWriteCntHctl (
+ IN UINT32 CntHctl
+ );
+
+#endif // __AARCH64_H__
diff --git a/roms/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h b/roms/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h new file mode 100644 index 000000000..606fe7420 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -0,0 +1,198 @@ +/** @file
+*
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __AARCH64_MMU_H_
+#define __AARCH64_MMU_H_
+
+//
+// Memory Attribute Indirection register Definitions
+//
+#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL
+#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL
+#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL
+#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL
+
+#define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8))
+
+//
+// Long-descriptor Translation Table format
+//
+
+// Return the smallest offset from the table level.
+// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
+#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))
+
+#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
+
+// Get the associated entry in the given Translation Table
+#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \
+ ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))
+
+// Return the smallest address granularity from the table level.
+// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
+#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
+
+#define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \
+ ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))
+
+// There are 512 entries per table when 4K Granularity
+#define TT_ENTRY_COUNT 512
+#define TT_ALIGNMENT_BLOCK_ENTRY BIT12
+#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12
+
+#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)
+#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)
+
+#define TT_TYPE_MASK 0x3
+#define TT_TYPE_TABLE_ENTRY 0x3
+#define TT_TYPE_BLOCK_ENTRY 0x1
+#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3
+
+#define TT_ATTR_INDX_MASK (0x7 << 2)
+#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)
+#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)
+#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)
+#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)
+
+#define TT_AP_MASK (0x3UL << 6)
+#define TT_AP_NO_RW (0x0UL << 6)
+#define TT_AP_RW_RW (0x1UL << 6)
+#define TT_AP_NO_RO (0x2UL << 6)
+#define TT_AP_RO_RO (0x3UL << 6)
+
+#define TT_NS BIT5
+#define TT_AF BIT10
+
+#define TT_SH_NON_SHAREABLE (0x0 << 8)
+#define TT_SH_OUTER_SHAREABLE (0x2 << 8)
+#define TT_SH_INNER_SHAREABLE (0x3 << 8)
+#define TT_SH_MASK (0x3 << 8)
+
+#define TT_PXN_MASK BIT53
+#define TT_UXN_MASK BIT54 // EL1&0
+#define TT_XN_MASK BIT54 // EL2 / EL3
+
+#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))
+
+#define TT_TABLE_PXN BIT59
+#define TT_TABLE_UXN BIT60 // EL1&0
+#define TT_TABLE_XN BIT60 // EL2 / EL3
+#define TT_TABLE_NS BIT63
+
+#define TT_TABLE_AP_MASK (BIT62 | BIT61)
+#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)
+#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)
+#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)
+
+//
+// Translation Control Register
+//
+#define TCR_T0SZ_MASK 0x3FUL
+
+#define TCR_PS_4GB (0UL << 16)
+#define TCR_PS_64GB (1UL << 16)
+#define TCR_PS_1TB (2UL << 16)
+#define TCR_PS_4TB (3UL << 16)
+#define TCR_PS_16TB (4UL << 16)
+#define TCR_PS_256TB (5UL << 16)
+
+#define TCR_TG0_4KB (0UL << 14)
+#define TCR_TG1_4KB (2UL << 30)
+
+#define TCR_IPS_4GB (0ULL << 32)
+#define TCR_IPS_64GB (1ULL << 32)
+#define TCR_IPS_1TB (2ULL << 32)
+#define TCR_IPS_4TB (3ULL << 32)
+#define TCR_IPS_16TB (4ULL << 32)
+#define TCR_IPS_256TB (5ULL << 32)
+
+#define TCR_EPD1 (1UL << 23)
+
+#define TTBR_ASID_FIELD (48)
+#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
+#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits
+
+#define TCR_EL1_T0SZ_FIELD (0)
+#define TCR_EL1_EPD0_FIELD (7)
+#define TCR_EL1_IRGN0_FIELD (8)
+#define TCR_EL1_ORGN0_FIELD (10)
+#define TCR_EL1_SH0_FIELD (12)
+#define TCR_EL1_TG0_FIELD (14)
+#define TCR_EL1_T1SZ_FIELD (16)
+#define TCR_EL1_A1_FIELD (22)
+#define TCR_EL1_EPD1_FIELD (23)
+#define TCR_EL1_IRGN1_FIELD (24)
+#define TCR_EL1_ORGN1_FIELD (26)
+#define TCR_EL1_SH1_FIELD (28)
+#define TCR_EL1_TG1_FIELD (30)
+#define TCR_EL1_IPS_FIELD (32)
+#define TCR_EL1_AS_FIELD (36)
+#define TCR_EL1_TBI0_FIELD (37)
+#define TCR_EL1_TBI1_FIELD (38)
+#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)
+#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)
+#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)
+#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)
+#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)
+#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)
+#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)
+#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)
+#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)
+#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)
+#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)
+#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)
+#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)
+#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)
+#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)
+#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)
+#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)
+
+
+#define TCR_EL23_T0SZ_FIELD (0)
+#define TCR_EL23_IRGN0_FIELD (8)
+#define TCR_EL23_ORGN0_FIELD (10)
+#define TCR_EL23_SH0_FIELD (12)
+#define TCR_EL23_TG0_FIELD (14)
+#define TCR_EL23_PS_FIELD (16)
+#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)
+#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)
+#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)
+#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)
+#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)
+#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)
+
+
+#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)
+#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)
+#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)
+#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)
+
+#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)
+#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)
+#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)
+#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)
+
+#define TCR_SH_NON_SHAREABLE (0x0UL << 12)
+#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)
+#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)
+
+#define TCR_PASZ_32BITS_4GB (0x0UL)
+#define TCR_PASZ_36BITS_64GB (0x1UL)
+#define TCR_PASZ_40BITS_1TB (0x2UL)
+#define TCR_PASZ_42BITS_4TB (0x3UL)
+#define TCR_PASZ_44BITS_16TB (0x4UL)
+#define TCR_PASZ_48BITS_256TB (0x5UL)
+
+// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
+// Virtual address range for 512GB of virtual space sets T*SZ to 25
+#define INPUT_ADDRESS_SIZE_TO_TxSZ(a) (64 - a)
+
+// Uses LPAE Page Table format
+
+#endif // __AARCH64_MMU_H_
+
diff --git a/roms/edk2/ArmPkg/Include/Chipset/ArmCortexA5x.h b/roms/edk2/ArmPkg/Include/Chipset/ArmCortexA5x.h new file mode 100644 index 000000000..847a6e004 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Chipset/ArmCortexA5x.h @@ -0,0 +1,44 @@ +/** @file
+
+ Copyright (c) 2012-2014, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARM_CORTEX_A5x_H__
+#define __ARM_CORTEX_A5x_H__
+
+//
+// Cortex A5x feature bit definitions
+//
+#define A5X_FEATURE_SMP (1 << 6)
+
+//
+// Helper functions to access CPU Extended Control Register
+//
+UINT64
+EFIAPI
+ArmReadCpuExCr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCpuExCr (
+ IN UINT64 Val
+ );
+
+VOID
+EFIAPI
+ArmSetCpuExCrBit (
+ IN UINT64 Bits
+ );
+
+VOID
+EFIAPI
+ArmUnsetCpuExCrBit (
+ IN UINT64 Bits
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Chipset/ArmCortexA9.h b/roms/edk2/ArmPkg/Include/Chipset/ArmCortexA9.h new file mode 100644 index 000000000..13d18e589 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Chipset/ArmCortexA9.h @@ -0,0 +1,59 @@ +/** @file
+
+ Copyright (c) 2011, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARM_CORTEX_A9_H__
+#define __ARM_CORTEX_A9_H__
+
+#include <Chipset/ArmV7.h>
+
+//
+// Cortex A9 feature bit definitions
+//
+#define A9_FEATURE_PARITY (1<<9)
+#define A9_FEATURE_AOW (1<<8)
+#define A9_FEATURE_EXCL (1<<7)
+#define A9_FEATURE_SMP (1<<6)
+#define A9_FEATURE_FOZ (1<<3)
+#define A9_FEATURE_DPREF (1<<2)
+#define A9_FEATURE_HINT (1<<1)
+#define A9_FEATURE_FWD (1<<0)
+
+//
+// Cortex A9 Watchdog
+//
+#define ARM_A9_WATCHDOG_REGION 0x600
+
+#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20
+#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28
+
+#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)
+#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)
+#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)
+#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)
+#define ARM_A9_WATCHDOG_ENABLE 1
+
+//
+// SCU register offsets & masks
+//
+#define A9_SCU_CONTROL_OFFSET 0x0
+#define A9_SCU_CONFIG_OFFSET 0x4
+#define A9_SCU_INVALL_OFFSET 0xC
+#define A9_SCU_FILT_START_OFFSET 0x40
+#define A9_SCU_FILT_END_OFFSET 0x44
+#define A9_SCU_SACR_OFFSET 0x50
+#define A9_SCU_SSACR_OFFSET 0x54
+
+
+UINTN
+EFIAPI
+ArmGetScuBaseAddress (
+ VOID
+ );
+
+#endif
+
diff --git a/roms/edk2/ArmPkg/Include/Chipset/ArmV7.h b/roms/edk2/ArmPkg/Include/Chipset/ArmV7.h new file mode 100644 index 000000000..fe91031ef --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Chipset/ArmV7.h @@ -0,0 +1,123 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARM_V7_H__
+#define __ARM_V7_H__
+
+#include <Chipset/ArmV7Mmu.h>
+
+// ARM Interrupt ID in Exception Table
+#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
+
+// ID_PFR1 - ARM Processor Feature Register 1 definitions
+#define ARM_PFR1_SEC (0xFUL << 4)
+#define ARM_PFR1_TIMER (0xFUL << 16)
+#define ARM_PFR1_GIC (0xFUL << 28)
+
+// Domain Access Control Register
+#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
+
+// CPSR - Coprocessor Status Register definitions
+#define CPSR_MODE_USER 0x10
+#define CPSR_MODE_FIQ 0x11
+#define CPSR_MODE_IRQ 0x12
+#define CPSR_MODE_SVC 0x13
+#define CPSR_MODE_ABORT 0x17
+#define CPSR_MODE_HYP 0x1A
+#define CPSR_MODE_UNDEFINED 0x1B
+#define CPSR_MODE_SYSTEM 0x1F
+#define CPSR_MODE_MASK 0x1F
+#define CPSR_ASYNC_ABORT (1 << 8)
+#define CPSR_IRQ (1 << 7)
+#define CPSR_FIQ (1 << 6)
+
+
+// CPACR - Coprocessor Access Control Register definitions
+#define CPACR_CP_DENIED(cp) 0x00
+#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
+#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
+#define CPACR_ASEDIS (1 << 31)
+#define CPACR_D32DIS (1 << 30)
+#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
+
+// NSACR - Non-Secure Access Control Register definitions
+#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
+#define NSACR_NSD32DIS (1 << 14)
+#define NSACR_NSASEDIS (1 << 15)
+#define NSACR_PLE (1 << 16)
+#define NSACR_TL (1 << 17)
+#define NSACR_NS_SMP (1 << 18)
+#define NSACR_RFR (1 << 19)
+
+// SCR - Secure Configuration Register definitions
+#define SCR_NS (1 << 0)
+#define SCR_IRQ (1 << 1)
+#define SCR_FIQ (1 << 2)
+#define SCR_EA (1 << 3)
+#define SCR_FW (1 << 4)
+#define SCR_AW (1 << 5)
+
+// MIDR - Main ID Register definitions
+#define ARM_CPU_TYPE_SHIFT 4
+#define ARM_CPU_TYPE_MASK 0xFFF
+#define ARM_CPU_TYPE_AEMv8 0xD0F
+#define ARM_CPU_TYPE_A53 0xD03
+#define ARM_CPU_TYPE_A57 0xD07
+#define ARM_CPU_TYPE_A15 0xC0F
+#define ARM_CPU_TYPE_A12 0xC0D
+#define ARM_CPU_TYPE_A9 0xC09
+#define ARM_CPU_TYPE_A7 0xC07
+#define ARM_CPU_TYPE_A5 0xC05
+
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
+
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
+
+VOID
+EFIAPI
+ArmEnableSWPInstruction (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadCbar (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadTpidrurw (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteTpidrurw (
+ UINTN Value
+ );
+
+UINT32
+EFIAPI
+ArmReadNsacr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteNsacr (
+ IN UINT32 Nsacr
+ );
+
+#endif // __ARM_V7_H__
diff --git a/roms/edk2/ArmPkg/Include/Chipset/ArmV7Mmu.h b/roms/edk2/ArmPkg/Include/Chipset/ArmV7Mmu.h new file mode 100644 index 000000000..25d82d029 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -0,0 +1,238 @@ +/** @file
+*
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ARMV7_MMU_H_
+#define __ARMV7_MMU_H_
+
+#define TTBR_NOT_OUTER_SHAREABLE BIT5
+#define TTBR_RGN_OUTER_NON_CACHEABLE 0
+#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
+#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
+#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
+#define TTBR_SHAREABLE BIT1
+#define TTBR_NON_SHAREABLE 0
+#define TTBR_INNER_CACHEABLE BIT0
+#define TTBR_INNER_NON_CACHEABLE 0
+#define TTBR_RGN_INNER_NON_CACHEABLE 0
+#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
+#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
+#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
+
+#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )
+#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+
+#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
+#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
+#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
+#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
+
+
+#define TRANSLATION_TABLE_SECTION_COUNT 4096
+#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
+#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
+#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
+
+#define TRANSLATION_TABLE_PAGE_COUNT 256
+#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
+#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
+#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
+
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
+
+// Translation table descriptor types
+#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
+#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
+#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
+#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
+#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
+#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
+
+// Translation table descriptor types
+#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
+
+// Section descriptor definitions
+#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
+
+#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
+#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
+
+#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
+#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
+#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
+
+#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
+#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
+#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
+
+#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
+#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
+#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
+
+#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
+#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
+#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
+
+#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
+
+#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
+
+#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
+#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
+#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)
+
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
+
+#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)
+
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3)
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
+
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
+
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc,IsLargePage) ((IsLargePage)? \
+ ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \
+ ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK))
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
+ (((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \
+ (((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))))
+
+#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
+
+#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
+ (((Desc) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK): \
+ (((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))))
+
+#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
+ TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \
+ TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK)
+
+#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
+ TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK)
+
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
+
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
+#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
+#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
+
+#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
+#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
+#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
+#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
+
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
+#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_XN_MASK | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
+#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+ ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
+
+#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
+ TT_DESCRIPTOR_PAGE_S_SHARED | \
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)
+#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
+ TT_DESCRIPTOR_PAGE_S_SHARED | \
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
+#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \
+ TT_DESCRIPTOR_PAGE_XN_MASK | \
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)
+#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+ TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
+ TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
+ TT_DESCRIPTOR_PAGE_AP_RW_RW | \
+ TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)
+
+// First Level Descriptors
+typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
+
+// Second Level Descriptors
+typedef UINT32 ARM_PAGE_TABLE_ENTRY;
+
+UINT32
+ConvertSectionAttributesToPageAttributes (
+ IN UINT32 SectionAttributes,
+ IN BOOLEAN IsLargePage
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Guid/ArmMpCoreInfo.h b/roms/edk2/ArmPkg/Include/Guid/ArmMpCoreInfo.h new file mode 100644 index 000000000..3f9d17bb7 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Guid/ArmMpCoreInfo.h @@ -0,0 +1,60 @@ +/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ARM_MP_CORE_INFO_GUID_H_
+#define __ARM_MP_CORE_INFO_GUID_H_
+
+#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
+#define SCU_CONFIG_REG_OFFSET 0x04
+#define MPIDR_U_BIT_MASK 0x40000000
+
+typedef struct {
+ UINT32 ClusterId;
+ UINT32 CoreId;
+
+ // MP Core Mailbox
+ EFI_PHYSICAL_ADDRESS MailboxSetAddress;
+ EFI_PHYSICAL_ADDRESS MailboxGetAddress;
+ EFI_PHYSICAL_ADDRESS MailboxClearAddress;
+ UINT64 MailboxClearValue;
+} ARM_CORE_INFO;
+
+typedef struct{
+ UINT64 Signature;
+ UINT32 Length;
+ UINT32 Revision;
+ UINT64 OemId;
+ UINT64 OemTableId;
+ UINTN OemRevision;
+ UINTN CreatorId;
+ UINTN CreatorRevision;
+ EFI_GUID Identifier;
+ UINTN DataLen;
+} ARM_PROCESSOR_TABLE_HEADER;
+
+typedef struct {
+ ARM_PROCESSOR_TABLE_HEADER Header;
+ UINTN NumberOfEntries;
+ ARM_CORE_INFO *ArmCpus;
+} ARM_PROCESSOR_TABLE;
+
+
+#define ARM_MP_CORE_INFO_GUID \
+ { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
+
+#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')
+#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000 //1.0
+#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')
+#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')
+#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001
+
+extern EFI_GUID gArmMpCoreInfoGuid;
+
+#endif /* MPCOREINFO_H_ */
diff --git a/roms/edk2/ArmPkg/Include/IndustryStandard/ArmMmSvc.h b/roms/edk2/ArmPkg/Include/IndustryStandard/ArmMmSvc.h new file mode 100644 index 000000000..ee29c2fec --- /dev/null +++ b/roms/edk2/ArmPkg/Include/IndustryStandard/ArmMmSvc.h @@ -0,0 +1,44 @@ +/** @file
+*
+* Copyright (c) 2012-2017, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ARM_MM_SVC_H__
+#define __ARM_MM_SVC_H__
+
+/*
+ * SVC IDs to allow the MM secure partition to initialise itself, handle
+ * delegated events and request the Secure partition manager to perform
+ * privileged operations on its behalf.
+ */
+#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
+
+#define SET_MEM_ATTR_DATA_PERM_MASK 0x3
+#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
+#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
+#define SET_MEM_ATTR_DATA_PERM_RW 1
+#define SET_MEM_ATTR_DATA_PERM_RO 3
+
+#define SET_MEM_ATTR_CODE_PERM_MASK 0x1
+#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
+#define SET_MEM_ATTR_CODE_PERM_X 0
+#define SET_MEM_ATTR_CODE_PERM_XN 1
+
+#define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm) \
+ ((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \
+ (( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT))
+
+/* MM SVC Return error codes */
+#define ARM_SVC_SPM_RET_SUCCESS 0
+#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
+#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
+#define ARM_SVC_SPM_RET_DENIED -3
+#define ARM_SVC_SPM_RET_NO_MEMORY -5
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/roms/edk2/ArmPkg/Include/IndustryStandard/ArmStdSmc.h new file mode 100644 index 000000000..3509eb680 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/IndustryStandard/ArmStdSmc.h @@ -0,0 +1,116 @@ +/** @file
+*
+* Copyright (c) 2012-2017, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ARM_STD_SMC_H__
+#define __ARM_STD_SMC_H__
+
+/*
+ * SMC function IDs for Standard Service queries
+ */
+
+#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
+#define ARM_SMC_ID_STD_UID 0x8400ff01
+/* 0x8400ff02 is reserved */
+#define ARM_SMC_ID_STD_REVISION 0x8400ff03
+
+/*
+ * The 'Standard Service Call UID' is supposed to return the Standard
+ * Service UUID. This is a 128-bit value.
+ */
+#define ARM_SMC_STD_UUID0 0x108d905b
+#define ARM_SMC_STD_UUID1 0x47e8f863
+#define ARM_SMC_STD_UUID2 0xfbc02dae
+#define ARM_SMC_STD_UUID3 0xe2f64156
+
+/*
+ * ARM Standard Service Calls revision numbers
+ * The current revision is: 0.1
+ */
+#define ARM_SMC_STD_REVISION_MAJOR 0x0
+#define ARM_SMC_STD_REVISION_MINOR 0x1
+
+/*
+ * Management Mode (MM) calls cover a subset of the Standard Service Call range.
+ * The list below is not exhaustive.
+ */
+#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
+#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
+
+// Request service from secure standalone MM environment
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
+
+/* MM return error codes */
+#define ARM_SMC_MM_RET_SUCCESS 0
+#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
+#define ARM_SMC_MM_RET_INVALID_PARAMS -2
+#define ARM_SMC_MM_RET_DENIED -3
+#define ARM_SMC_MM_RET_NO_MEMORY -4
+
+/*
+ * Power State Coordination Interface (PSCI) calls cover a subset of the
+ * Standard Service Call range.
+ * The list below is not exhaustive.
+ */
+#define ARM_SMC_ID_PSCI_VERSION 0x84000000
+#define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64 0xc4000001
+#define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH32 0x84000001
+#define ARM_SMC_ID_PSCI_CPU_OFF 0x84000002
+#define ARM_SMC_ID_PSCI_CPU_ON_AARCH64 0xc4000003
+#define ARM_SMC_ID_PSCI_CPU_ON_AARCH32 0x84000003
+#define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH64 0xc4000004
+#define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH32 0x84000004
+#define ARM_SMC_ID_PSCI_MIGRATE_AARCH64 0xc4000005
+#define ARM_SMC_ID_PSCI_MIGRATE_AARCH32 0x84000005
+#define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x84000008
+#define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x84000009
+
+/* The current PSCI version is: 0.2 */
+#define ARM_SMC_PSCI_VERSION_MAJOR 0
+#define ARM_SMC_PSCI_VERSION_MINOR 2
+#define ARM_SMC_PSCI_VERSION \
+ ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)
+
+/* PSCI return error codes */
+#define ARM_SMC_PSCI_RET_SUCCESS 0
+#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
+#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
+#define ARM_SMC_PSCI_RET_DENIED -3
+#define ARM_SMC_PSCI_RET_ALREADY_ON -4
+#define ARM_SMC_PSCI_RET_ON_PENDING -5
+#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
+#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
+#define ARM_SMC_PSCI_RET_DISABLED -8
+
+#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \
+ ((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
+
+#define ARM_SMC_PSCI_TARGET_CPU64(Aff3, Aff2, Aff1, Aff0) \
+ ((((Aff3) & 0xFFULL) << 32) | (((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
+
+#define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)
+#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)
+
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
+
+#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0
+#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1
+#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON_PENDING 2
+
+/*
+ * SMC function IDs for Trusted OS Service queries
+ */
+#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
+#define ARM_SMC_ID_TOS_UID 0xbf00ff01
+/* 0xbf00ff02 is reserved */
+#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/ArmDisassemblerLib.h b/roms/edk2/ArmPkg/Include/Library/ArmDisassemblerLib.h new file mode 100644 index 000000000..c103b72e8 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/ArmDisassemblerLib.h @@ -0,0 +1,37 @@ +/** @file
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARM_DISASSEBLER_LIB_H__
+#define __ARM_DISASSEBLER_LIB_H__
+
+/**
+ Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
+ point to next instruction.
+
+ We cheat and only decode instructions that access
+ memory. If the instruction is not found we dump the instruction in hex.
+
+ @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
+ @param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
+ @param Extended TRUE dump hex for instruction too.
+ @param ItBlock Size of IT Block
+ @param Buf Buffer to sprintf disassembly into.
+ @param Size Size of Buf in bytes.
+
+**/
+VOID
+DisassembleInstruction (
+ IN UINT8 **OpCodePtr,
+ IN BOOLEAN Thumb,
+ IN BOOLEAN Extended,
+ IN OUT UINT32 *ItBlock,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h b/roms/edk2/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h new file mode 100644 index 000000000..d3051be30 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h @@ -0,0 +1,85 @@ +/** @file
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARM_GENERIC_TIMER_COUNTER_LIB_H__
+#define __ARM_GENERIC_TIMER_COUNTER_LIB_H__
+
+VOID
+EFIAPI
+ArmGenericTimerEnableTimer (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmGenericTimerReenableTimer (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmGenericTimerDisableTimer (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmGenericTimerSetTimerFreq (
+ IN UINTN FreqInHz
+ );
+
+UINTN
+EFIAPI
+ArmGenericTimerGetTimerFreq (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmGenericTimerSetTimerVal (
+ IN UINTN Value
+ );
+
+UINTN
+EFIAPI
+ArmGenericTimerGetTimerVal (
+ VOID
+ );
+
+UINT64
+EFIAPI
+ArmGenericTimerGetSystemCount (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmGenericTimerGetTimerCtrlReg (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmGenericTimerSetTimerCtrlReg (
+ UINTN Value
+ );
+
+UINT64
+EFIAPI
+ArmGenericTimerGetCompareVal (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmGenericTimerSetCompareVal (
+ IN UINT64 Value
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/ArmGicArchLib.h b/roms/edk2/ArmPkg/Include/Library/ArmGicArchLib.h new file mode 100644 index 000000000..264322f1d --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/ArmGicArchLib.h @@ -0,0 +1,27 @@ +/** @file
+*
+* Copyright (c) 2015, Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ARM_GIC_ARCH_LIB_H__
+#define __ARM_GIC_ARCH_LIB_H__
+
+//
+// GIC definitions
+//
+typedef enum {
+ ARM_GIC_ARCH_REVISION_2,
+ ARM_GIC_ARCH_REVISION_3
+} ARM_GIC_ARCH_REVISION;
+
+
+ARM_GIC_ARCH_REVISION
+EFIAPI
+ArmGicGetSupportedArchRevision (
+ VOID
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/ArmGicLib.h b/roms/edk2/ArmPkg/Include/Library/ArmGicLib.h new file mode 100644 index 000000000..550931896 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/ArmGicLib.h @@ -0,0 +1,327 @@ +/** @file
+*
+* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ARMGIC_H
+#define __ARMGIC_H
+
+#include <Library/ArmGicArchLib.h>
+
+// GIC Distributor
+#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
+#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
+#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
+
+// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
+#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
+#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
+#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
+#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
+#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
+#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
+
+// Each reg base below repeats for Number of interrupts / 4
+#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
+
+// Each reg base below repeats for Number of interrupts
+#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
+#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
+
+#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
+
+// just one of these
+#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
+
+// GICv3 specific registers
+#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
+
+// GICD_CTLR bits
+#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
+#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
+
+// GICD_ICDICFR bits
+#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register
+#define ARM_GIC_ICDICFR_BYTES (ARM_GIC_ICDICFR_WIDTH / 8)
+#define ARM_GIC_ICDICFR_F_WIDTH 2 // Each F field is 2 bits
+#define ARM_GIC_ICDICFR_F_STRIDE 16 // (32/2) F fields per register
+#define ARM_GIC_ICDICFR_F_CONFIG1_BIT 1 // Bit number within F field
+#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt
+#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt
+
+
+// GIC Redistributor
+#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
+
+// GIC Redistributor Control frame
+#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
+
+// GIC Redistributor TYPER bit assignments
+#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
+#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
+#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
+#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
+#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
+ // Selection Support
+#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
+#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
+#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
+
+#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \
+ ARM_GICR_TYPER_AFFINITY) >> 32)
+
+// GIC SGI & PPI Redistributor frame
+#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
+#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
+
+// GIC Cpu interface
+#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
+#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
+#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
+#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
+#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
+#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
+#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
+#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
+#define ARM_GIC_ICCIIDR 0xFC // Identification Register
+
+#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
+#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
+#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
+
+// Bit-masks to configure the CPU Interface Control register
+#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
+#define ARM_GIC_ICCICR_ENABLE_NS 0x02
+#define ARM_GIC_ICCICR_ACK_CTL 0x04
+#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
+#define ARM_GIC_ICCICR_USE_SBPR 0x10
+
+// Bit Mask for GICC_IIDR
+#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
+#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
+#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
+#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
+
+// Bit Mask for
+#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
+
+UINTN
+EFIAPI
+ArmGicGetInterfaceIdentification (
+ IN INTN GicInterruptInterfaceBase
+ );
+
+// GIC Secure interfaces
+VOID
+EFIAPI
+ArmGicSetupNonSecure (
+ IN UINTN MpId,
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
+ );
+
+VOID
+EFIAPI
+ArmGicSetSecureInterrupts (
+ IN UINTN GicDistributorBase,
+ IN UINTN* GicSecureInterruptMask,
+ IN UINTN GicSecureInterruptMaskSize
+ );
+
+VOID
+EFIAPI
+ArmGicEnableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ );
+
+VOID
+EFIAPI
+ArmGicDisableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ );
+
+VOID
+EFIAPI
+ArmGicEnableDistributor (
+ IN INTN GicDistributorBase
+ );
+
+VOID
+EFIAPI
+ArmGicDisableDistributor (
+ IN INTN GicDistributorBase
+ );
+
+UINTN
+EFIAPI
+ArmGicGetMaxNumInterrupts (
+ IN INTN GicDistributorBase
+ );
+
+VOID
+EFIAPI
+ArmGicSendSgiTo (
+ IN INTN GicDistributorBase,
+ IN INTN TargetListFilter,
+ IN INTN CPUTargetList,
+ IN INTN SgiId
+ );
+
+/*
+ * Acknowledge and return the value of the Interrupt Acknowledge Register
+ *
+ * InterruptId is returned separately from the register value because in
+ * the GICv2 the register value contains the CpuId and InterruptId while
+ * in the GICv3 the register value is only the InterruptId.
+ *
+ * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface
+ * @param InterruptId InterruptId read from the Interrupt
+ * Acknowledge Register
+ *
+ * @retval value returned by the Interrupt Acknowledge Register
+ *
+ */
+UINTN
+EFIAPI
+ArmGicAcknowledgeInterrupt (
+ IN UINTN GicInterruptInterfaceBase,
+ OUT UINTN *InterruptId
+ );
+
+VOID
+EFIAPI
+ArmGicEndOfInterrupt (
+ IN UINTN GicInterruptInterfaceBase,
+ IN UINTN Source
+ );
+
+UINTN
+EFIAPI
+ArmGicSetPriorityMask (
+ IN INTN GicInterruptInterfaceBase,
+ IN INTN PriorityMask
+ );
+
+VOID
+EFIAPI
+ArmGicEnableInterrupt (
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
+ );
+
+VOID
+EFIAPI
+ArmGicDisableInterrupt (
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
+ );
+
+BOOLEAN
+EFIAPI
+ArmGicIsInterruptEnabled (
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
+ );
+
+// GIC revision 2 specific declarations
+
+// Interrupts from 1020 to 1023 are considered as special interrupts
+// (eg: spurious interrupts)
+#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \
+ (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
+
+VOID
+EFIAPI
+ArmGicV2SetupNonSecure (
+ IN UINTN MpId,
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
+ );
+
+VOID
+EFIAPI
+ArmGicV2EnableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ );
+
+VOID
+EFIAPI
+ArmGicV2DisableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ );
+
+UINTN
+EFIAPI
+ArmGicV2AcknowledgeInterrupt (
+ IN UINTN GicInterruptInterfaceBase
+ );
+
+VOID
+EFIAPI
+ArmGicV2EndOfInterrupt (
+ IN UINTN GicInterruptInterfaceBase,
+ IN UINTN Source
+ );
+
+// GIC revision 3 specific declarations
+
+#define ICC_SRE_EL2_SRE (1 << 0)
+
+#define ARM_GICD_IROUTER_IRM BIT31
+
+UINT32
+EFIAPI
+ArmGicV3GetControlSystemRegisterEnable (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmGicV3SetControlSystemRegisterEnable (
+ IN UINT32 ControlSystemRegisterEnable
+ );
+
+VOID
+EFIAPI
+ArmGicV3EnableInterruptInterface (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmGicV3DisableInterruptInterface (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmGicV3AcknowledgeInterrupt (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmGicV3EndOfInterrupt (
+ IN UINTN Source
+ );
+
+VOID
+ArmGicV3SetBinaryPointer (
+ IN UINTN BinaryPoint
+ );
+
+VOID
+ArmGicV3SetPriorityMask (
+ IN UINTN Priority
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/ArmHvcLib.h b/roms/edk2/ArmPkg/Include/Library/ArmHvcLib.h new file mode 100644 index 000000000..d26f0cff3 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/ArmHvcLib.h @@ -0,0 +1,40 @@ +/** @file
+*
+* Copyright (c) 2012-2014, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ARM_HVC_LIB__
+#define __ARM_HVC_LIB__
+
+/**
+ * The size of the HVC arguments are different between AArch64 and AArch32.
+ * The native size is used for the arguments.
+ */
+typedef struct {
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINTN Arg3;
+ UINTN Arg4;
+ UINTN Arg5;
+ UINTN Arg6;
+ UINTN Arg7;
+} ARM_HVC_ARGS;
+
+/**
+ Trigger an HVC call
+
+ HVC calls can take up to 8 arguments and return up to 4 return values.
+ Therefore, the 4 first fields in the ARM_HVC_ARGS structure are used
+ for both input and output values.
+
+**/
+VOID
+ArmCallHvc (
+ IN OUT ARM_HVC_ARGS *Args
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/ArmLib.h b/roms/edk2/ArmPkg/Include/Library/ArmLib.h new file mode 100644 index 000000000..5a27b7c2f --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/ArmLib.h @@ -0,0 +1,718 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARM_LIB__
+#define __ARM_LIB__
+
+#include <Uefi/UefiBaseType.h>
+
+#ifdef MDE_CPU_ARM
+ #include <Chipset/ArmV7.h>
+#elif defined(MDE_CPU_AARCH64)
+ #include <Chipset/AArch64.h>
+#else
+ #error "Unknown chipset."
+#endif
+
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
+ EFI_MEMORY_WT | EFI_MEMORY_WB | \
+ EFI_MEMORY_UCE)
+
+/**
+ * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
+ *
+ * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
+ * be used in Secure World to distinguished Secure to Non-Secure memory.
+ */
+typedef enum {
+ ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
+
+ // On some platforms, memory mapped flash region is designed as not supporting
+ // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
+ // need.
+ // Do NOT use below two attributes if you are not sure.
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
+
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
+ ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
+} ARM_MEMORY_REGION_ATTRIBUTES;
+
+#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESS PhysicalBase;
+ EFI_VIRTUAL_ADDRESS VirtualBase;
+ UINT64 Length;
+ ARM_MEMORY_REGION_ATTRIBUTES Attributes;
+} ARM_MEMORY_REGION_DESCRIPTOR;
+
+typedef VOID (*CACHE_OPERATION)(VOID);
+typedef VOID (*LINE_OPERATION)(UINTN);
+
+//
+// ARM Processor Mode
+//
+typedef enum {
+ ARM_PROCESSOR_MODE_USER = 0x10,
+ ARM_PROCESSOR_MODE_FIQ = 0x11,
+ ARM_PROCESSOR_MODE_IRQ = 0x12,
+ ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
+ ARM_PROCESSOR_MODE_ABORT = 0x17,
+ ARM_PROCESSOR_MODE_HYP = 0x1A,
+ ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,
+ ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
+ ARM_PROCESSOR_MODE_MASK = 0x1F
+} ARM_PROCESSOR_MODE;
+
+//
+// ARM Cpu IDs
+//
+#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
+#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
+#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
+#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
+#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
+#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
+
+#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
+
+//
+// ARM MP Core IDs
+//
+#define ARM_CORE_AFF0 0xFF
+#define ARM_CORE_AFF1 (0xFF << 8)
+#define ARM_CORE_AFF2 (0xFF << 16)
+#define ARM_CORE_AFF3 (0xFFULL << 32)
+
+#define ARM_CORE_MASK ARM_CORE_AFF0
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1
+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
+#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
+
+UINTN
+EFIAPI
+ArmDataCacheLineLength (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmInstructionCacheLineLength (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmCacheWritebackGranule (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmIsArchTimerImplemented (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadIdPfr0 (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadIdPfr1 (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmCacheInfo (
+ VOID
+ );
+
+BOOLEAN
+EFIAPI
+ArmIsMpCore (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmInvalidateDataCache (
+ VOID
+ );
+
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmCleanDataCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmInvalidateInstructionCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmInvalidateDataCacheEntryByMVA (
+ IN UINTN Address
+ );
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryToPoUByMVA (
+ IN UINTN Address
+ );
+
+VOID
+EFIAPI
+ArmInvalidateInstructionCacheEntryToPoUByMVA (
+ IN UINTN Address
+ );
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryByMVA (
+IN UINTN Address
+);
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCacheEntryByMVA (
+ IN UINTN Address
+ );
+
+VOID
+EFIAPI
+ArmEnableDataCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableDataCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableInstructionCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableInstructionCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableMmu (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableMmu (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableCachesAndMmu (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableCachesAndMmu (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableInterrupts (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmDisableInterrupts (
+ VOID
+ );
+
+BOOLEAN
+EFIAPI
+ArmGetInterruptState (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableAsynchronousAbort (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmDisableAsynchronousAbort (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableIrq (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmDisableIrq (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableFiq (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmDisableFiq (
+ VOID
+ );
+
+BOOLEAN
+EFIAPI
+ArmGetFiqState (
+ VOID
+ );
+
+/**
+ * Invalidate Data and Instruction TLBs
+ */
+VOID
+EFIAPI
+ArmInvalidateTlb (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmUpdateTranslationTableEntry (
+ IN VOID *TranslationTableEntry,
+ IN VOID *Mva
+ );
+
+VOID
+EFIAPI
+ArmSetDomainAccessControl (
+ IN UINT32 Domain
+ );
+
+VOID
+EFIAPI
+ArmSetTTBR0 (
+ IN VOID *TranslationTableBase
+ );
+
+VOID
+EFIAPI
+ArmSetTTBCR (
+ IN UINT32 Bits
+ );
+
+VOID *
+EFIAPI
+ArmGetTTBR0BaseAddress (
+ VOID
+ );
+
+BOOLEAN
+EFIAPI
+ArmMmuEnabled (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableBranchPrediction (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableBranchPrediction (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmSetLowVectors (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmSetHighVectors (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDataMemoryBarrier (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDataSynchronizationBarrier (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmInstructionSynchronizationBarrier (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteVBar (
+ IN UINTN VectorBase
+ );
+
+UINTN
+EFIAPI
+ArmReadVBar (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteAuxCr (
+ IN UINT32 Bit
+ );
+
+UINT32
+EFIAPI
+ArmReadAuxCr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmSetAuxCrBit (
+ IN UINT32 Bits
+ );
+
+VOID
+EFIAPI
+ArmUnsetAuxCrBit (
+ IN UINT32 Bits
+ );
+
+VOID
+EFIAPI
+ArmCallSEV (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmCallWFE (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmCallWFI (
+
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadMpidr (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadMidr (
+ VOID
+ );
+
+UINT32
+EFIAPI
+ArmReadCpacr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCpacr (
+ IN UINT32 Access
+ );
+
+VOID
+EFIAPI
+ArmEnableVFP (
+ VOID
+ );
+
+/**
+ Get the Secure Configuration Register value
+
+ @return Value read from the Secure Configuration Register
+
+**/
+UINT32
+EFIAPI
+ArmReadScr (
+ VOID
+ );
+
+/**
+ Set the Secure Configuration Register
+
+ @param Value Value to write to the Secure Configuration Register
+
+**/
+VOID
+EFIAPI
+ArmWriteScr (
+ IN UINT32 Value
+ );
+
+UINT32
+EFIAPI
+ArmReadMVBar (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteMVBar (
+ IN UINT32 VectorMonitorBase
+ );
+
+UINT32
+EFIAPI
+ArmReadSctlr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteSctlr (
+ IN UINT32 Value
+ );
+
+UINTN
+EFIAPI
+ArmReadHVBar (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteHVBar (
+ IN UINTN HypModeVectorBase
+ );
+
+
+//
+// Helper functions for accessing CPU ACTLR
+//
+
+UINTN
+EFIAPI
+ArmReadCpuActlr (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCpuActlr (
+ IN UINTN Val
+ );
+
+VOID
+EFIAPI
+ArmSetCpuActlrBit (
+ IN UINTN Bits
+ );
+
+VOID
+EFIAPI
+ArmUnsetCpuActlrBit (
+ IN UINTN Bits
+ );
+
+//
+// Accessors for the architected generic timer registers
+//
+
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)
+#define ARM_ARCH_TIMER_IMASK (1 << 1)
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
+
+UINTN
+EFIAPI
+ArmReadCntFrq (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntFrq (
+ UINTN FreqInHz
+ );
+
+UINT64
+EFIAPI
+ArmReadCntPct (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmReadCntkCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntkCtl (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntpTval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpTval (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntpCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpCtl (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntvTval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvTval (
+ UINTN Val
+ );
+
+UINTN
+EFIAPI
+ArmReadCntvCtl (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvCtl (
+ UINTN Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvCt (
+ VOID
+ );
+
+UINT64
+EFIAPI
+ArmReadCntpCval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntpCval (
+ UINT64 Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvCval (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvCval (
+ UINT64 Val
+ );
+
+UINT64
+EFIAPI
+ArmReadCntvOff (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmWriteCntvOff (
+ UINT64 Val
+ );
+
+UINTN
+EFIAPI
+ArmGetPhysicalAddressBits (
+ VOID
+ );
+
+#endif // __ARM_LIB__
diff --git a/roms/edk2/ArmPkg/Include/Library/ArmMmuLib.h b/roms/edk2/ArmPkg/Include/Library/ArmMmuLib.h new file mode 100644 index 000000000..23e89a0c6 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/ArmMmuLib.h @@ -0,0 +1,67 @@ +/** @file
+
+ Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARM_MMU_LIB__
+#define __ARM_MMU_LIB__
+
+#include <Uefi/UefiBaseType.h>
+
+#include <Library/ArmLib.h>
+
+EFI_STATUS
+EFIAPI
+ArmConfigureMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
+ OUT VOID **TranslationTableBase OPTIONAL,
+ OUT UINTN *TranslationTableSize OPTIONAL
+ );
+
+EFI_STATUS
+EFIAPI
+ArmSetMemoryRegionNoExec (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+EFI_STATUS
+EFIAPI
+ArmClearMemoryRegionNoExec (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+EFI_STATUS
+EFIAPI
+ArmSetMemoryRegionReadOnly (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+EFI_STATUS
+EFIAPI
+ArmClearMemoryRegionReadOnly (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+VOID
+EFIAPI
+ArmReplaceLiveTranslationEntry (
+ IN UINT64 *Entry,
+ IN UINT64 Value,
+ IN UINT64 RegionStart
+ );
+
+EFI_STATUS
+ArmSetMemoryAttributes (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/ArmMtlLib.h b/roms/edk2/ArmPkg/Include/Library/ArmMtlLib.h new file mode 100644 index 000000000..35059bf78 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/ArmMtlLib.h @@ -0,0 +1,131 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#ifndef ARM_MTL_LIB_H_
+#define ARM_MTL_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+
+// Ideally we don't need packed struct. However we can't rely on compilers.
+#pragma pack(1)
+
+typedef struct {
+ UINT32 Reserved1;
+ UINT32 ChannelStatus;
+ UINT64 Reserved2;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 MessageHeader;
+
+ // NOTE: Since EDK2 does not allow flexible array member [] we declare
+ // here array of 1 element length. However below is used as a variable
+ // length array.
+ UINT32 Payload[1]; // size less object gives offset to payload.
+} MTL_MAILBOX;
+
+#pragma pack()
+
+// Channel Type, Low-priority, and High-priority
+typedef enum {
+ MTL_CHANNEL_TYPE_LOW = 0,
+ MTL_CHANNEL_TYPE_HIGH = 1
+} MTL_CHANNEL_TYPE;
+
+typedef struct {
+ UINT64 PhysicalAddress;
+ UINT32 ModifyMask;
+ UINT32 PreserveMask;
+} MTL_DOORBELL;
+
+typedef struct {
+ MTL_CHANNEL_TYPE ChannelType;
+ MTL_MAILBOX * CONST MailBox;
+ MTL_DOORBELL DoorBell;
+} MTL_CHANNEL;
+
+/** Wait until channel is free.
+
+ @param[in] Channel Pointer to a channel.
+ @param[in] TimeOutInMicroSeconds Time out in micro seconds.
+
+ @retval EFI_SUCCESS Channel is free.
+ @retval EFI_TIMEOUT Time out error.
+**/
+EFI_STATUS
+MtlWaitUntilChannelFree (
+ IN MTL_CHANNEL *Channel,
+ IN UINTN TimeOutInMicroSeconds
+ );
+
+/** Return the address of the message payload.
+
+ @param[in] Channel Pointer to a channel.
+
+ @retval UINT32* Pointer to the payload.
+**/
+UINT32*
+MtlGetChannelPayload (
+ IN MTL_CHANNEL *Channel
+ );
+
+/** Return pointer to a channel for the requested channel type.
+
+ @param[in] ChannelType ChannelType, Low or High priority channel.
+ MTL_CHANNEL_TYPE_LOW or
+ MTL_CHANNEL_TYPE_HIGH
+
+ @param[out] Channel Holds pointer to the channel.
+
+ @retval EFI_SUCCESS Pointer to channel is returned.
+ @retval EFI_UNSUPPORTED Requested channel type not supported.
+**/
+EFI_STATUS
+MtlGetChannel (
+ IN MTL_CHANNEL_TYPE ChannelType,
+ OUT MTL_CHANNEL **Channel
+ );
+
+/** Mark the channel busy and ring the doorbell.
+
+ @param[in] Channel Pointer to a channel.
+ @param[in] MessageHeader Message header.
+
+ @param[out] PayloadLength Message length.
+
+ @retval EFI_SUCCESS Message sent successfully.
+ @retval EFI_DEVICE_ERROR Channel is busy.
+**/
+EFI_STATUS
+MtlSendMessage (
+ IN MTL_CHANNEL *Channel,
+ IN UINT32 MessageHeader,
+ OUT UINT32 PayloadLength
+ );
+
+/** Wait for a response on a channel.
+
+ If channel is free after sending message, it implies SCP responded
+ with a response on the channel.
+
+ @param[in] Channel Pointer to a channel.
+
+ @retval EFI_SUCCESS Message received successfully.
+ @retval EFI_TIMEOUT Time out error.
+**/
+EFI_STATUS
+MtlReceiveMessage (
+ IN MTL_CHANNEL *Channel,
+ OUT UINT32 *MessageHeader,
+ OUT UINT32 *PayloadLength
+ );
+
+#endif /* ARM_MTL_LIB_H_ */
+
diff --git a/roms/edk2/ArmPkg/Include/Library/ArmSmcLib.h b/roms/edk2/ArmPkg/Include/Library/ArmSmcLib.h new file mode 100644 index 000000000..835d6788e --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/ArmSmcLib.h @@ -0,0 +1,40 @@ +/** @file
+*
+* Copyright (c) 2012-2014, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ARM_SMC_LIB__
+#define __ARM_SMC_LIB__
+
+/**
+ * The size of the SMC arguments are different between AArch64 and AArch32.
+ * The native size is used for the arguments.
+ */
+typedef struct {
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINTN Arg3;
+ UINTN Arg4;
+ UINTN Arg5;
+ UINTN Arg6;
+ UINTN Arg7;
+} ARM_SMC_ARGS;
+
+/**
+ Trigger an SMC call
+
+ SMC calls can take up to 7 arguments and return up to 4 return values.
+ Therefore, the 4 first fields in the ARM_SMC_ARGS structure are used
+ for both input and output values.
+
+**/
+VOID
+ArmCallSmc (
+ IN OUT ARM_SMC_ARGS *Args
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/ArmSvcLib.h b/roms/edk2/ArmPkg/Include/Library/ArmSvcLib.h new file mode 100644 index 000000000..a94ead196 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/ArmSvcLib.h @@ -0,0 +1,40 @@ +/** @file
+*
+* Copyright (c) 2016 - 2017, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ARM_SVC_LIB__
+#define __ARM_SVC_LIB__
+
+/**
+ * The size of the SVC arguments are different between AArch64 and AArch32.
+ * The native size is used for the arguments.
+ */
+typedef struct {
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINTN Arg3;
+ UINTN Arg4;
+ UINTN Arg5;
+ UINTN Arg6;
+ UINTN Arg7;
+} ARM_SVC_ARGS;
+
+/**
+ Trigger an SVC call
+
+ SVC calls can take up to 7 arguments and return up to 4 return values.
+ Therefore, the 4 first fields in the ARM_SVC_ARGS structure are used
+ for both input and output values.
+
+**/
+VOID
+ArmCallSvc (
+ IN OUT ARM_SVC_ARGS *Args
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h b/roms/edk2/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h new file mode 100644 index 000000000..bbcf30f85 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h @@ -0,0 +1,25 @@ +/** @file
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEFAULT_EXCEPTION_HANDLER_LIB_H__
+#define __DEFAULT_EXCEPTION_HANDLER_LIB_H__
+
+/**
+ This is the default action to take on an unexpected exception
+
+ @param ExceptionType Type of the exception
+ @param SystemContext Register state at the time of the Exception
+
+**/
+VOID
+DefaultExceptionHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/OpteeLib.h b/roms/edk2/ArmPkg/Include/Library/OpteeLib.h new file mode 100644 index 000000000..d71636143 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/OpteeLib.h @@ -0,0 +1,117 @@ +/** @file
+ OP-TEE specific header file.
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _OPTEE_H_
+#define _OPTEE_H_
+
+/*
+ * The 'Trusted OS Call UID' is supposed to return the following UUID for
+ * OP-TEE OS. This is a 128-bit value.
+ */
+#define OPTEE_OS_UID0 0x384fb3e0
+#define OPTEE_OS_UID1 0xe7f811e3
+#define OPTEE_OS_UID2 0xaf630002
+#define OPTEE_OS_UID3 0xa5d5c51b
+
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb
+
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff
+
+#define OPTEE_SUCCESS 0x00000000
+#define OPTEE_ORIGIN_COMMUNICATION 0x00000002
+#define OPTEE_ERROR_COMMUNICATION 0xFFFF000E
+
+typedef struct {
+ UINT64 BufferAddress;
+ UINT64 Size;
+ UINT64 SharedMemoryReference;
+} OPTEE_MESSAGE_PARAM_MEMORY;
+
+typedef struct {
+ UINT64 A;
+ UINT64 B;
+ UINT64 C;
+} OPTEE_MESSAGE_PARAM_VALUE;
+
+typedef struct {
+ UINT64 Attribute;
+ union {
+ OPTEE_MESSAGE_PARAM_MEMORY Memory;
+ OPTEE_MESSAGE_PARAM_VALUE Value;
+ } Union;
+} OPTEE_MESSAGE_PARAM;
+
+#define OPTEE_MAX_CALL_PARAMS 4
+
+typedef struct {
+ UINT32 Command;
+ UINT32 Function;
+ UINT32 Session;
+ UINT32 CancelId;
+ UINT32 Pad;
+ UINT32 Return;
+ UINT32 ReturnOrigin;
+ UINT32 NumParams;
+
+ // NumParams tells the actual number of element in Params
+ OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS];
+} OPTEE_MESSAGE_ARG;
+
+typedef struct {
+ EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application
+ UINT32 Session; // [out] Session id
+ UINT32 Return; // [out] Return value
+ UINT32 ReturnOrigin; // [out] Origin of the return value
+} OPTEE_OPEN_SESSION_ARG;
+
+typedef struct {
+ UINT32 Function; // [in] Trusted Application function, specific to the TA
+ UINT32 Session; // [in] Session id
+ UINT32 Return; // [out] Return value
+ UINT32 ReturnOrigin; // [out] Origin of the return value
+ OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked
+} OPTEE_INVOKE_FUNCTION_ARG;
+
+BOOLEAN
+EFIAPI
+IsOpteePresent (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+OpteeInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+OpteeOpenSession (
+ IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
+ );
+
+EFI_STATUS
+EFIAPI
+OpteeCloseSession (
+ IN UINT32 Session
+ );
+
+EFI_STATUS
+EFIAPI
+OpteeInvokeFunction (
+ IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Library/SemihostLib.h b/roms/edk2/ArmPkg/Include/Library/SemihostLib.h new file mode 100644 index 000000000..ce08b2778 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/SemihostLib.h @@ -0,0 +1,132 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Portions copyright (c) 2011, 2012, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SEMIHOSTING_H__
+#define __SEMIHOSTING_H__
+
+/*
+ *
+ * Please refer to ARM RVDS 3.0 Compiler and Libraries Guide for more information
+ * about the semihosting interface.
+ *
+ */
+
+#define SEMIHOST_FILE_MODE_READ (0 << 2)
+#define SEMIHOST_FILE_MODE_WRITE (1 << 2)
+#define SEMIHOST_FILE_MODE_APPEND (2 << 2)
+#define SEMIHOST_FILE_MODE_UPDATE (1 << 1)
+#define SEMIHOST_FILE_MODE_BINARY (1 << 0)
+#define SEMIHOST_FILE_MODE_ASCII (0 << 0)
+
+BOOLEAN
+SemihostConnectionSupported (
+ VOID
+ );
+
+RETURN_STATUS
+SemihostFileOpen (
+ IN CHAR8 *FileName,
+ IN UINT32 Mode,
+ OUT UINTN *FileHandle
+ );
+
+RETURN_STATUS
+SemihostFileSeek (
+ IN UINTN FileHandle,
+ IN UINTN Offset
+ );
+
+RETURN_STATUS
+SemihostFileRead (
+ IN UINTN FileHandle,
+ IN OUT UINTN *Length,
+ OUT VOID *Buffer
+ );
+
+RETURN_STATUS
+SemihostFileWrite (
+ IN UINTN FileHandle,
+ IN OUT UINTN *Length,
+ IN VOID *Buffer
+ );
+
+RETURN_STATUS
+SemihostFileClose (
+ IN UINTN FileHandle
+ );
+
+RETURN_STATUS
+SemihostFileLength (
+ IN UINTN FileHandle,
+ OUT UINTN *Length
+ );
+
+/**
+ Get a temporary name for a file from the host running the debug agent.
+
+ @param[out] Buffer Pointer to the buffer where the temporary name has to
+ be stored
+ @param[in] Identifier File name identifier (integer in the range 0 to 255)
+ @param[in] Length Length of the buffer to store the temporary name
+
+ @retval RETURN_SUCCESS Temporary name returned
+ @retval RETURN_INVALID_PARAMETER Invalid buffer address
+ @retval RETURN_ABORTED Temporary name not returned
+
+**/
+RETURN_STATUS
+SemihostFileTmpName(
+ OUT VOID *Buffer,
+ IN UINT8 Identifier,
+ IN UINTN Length
+ );
+
+RETURN_STATUS
+SemihostFileRemove (
+ IN CHAR8 *FileName
+ );
+
+/**
+ Rename a specified file.
+
+ @param[in] FileName Name of the file to rename.
+ @param[in] NewFileName The new name of the file.
+
+ @retval RETURN_SUCCESS File Renamed
+ @retval RETURN_INVALID_PARAMETER Either the current or the new name is not specified
+ @retval RETURN_ABORTED Rename failed
+
+**/
+RETURN_STATUS
+SemihostFileRename(
+ IN CHAR8 *FileName,
+ IN CHAR8 *NewFileName
+ );
+
+CHAR8
+SemihostReadCharacter (
+ VOID
+ );
+
+VOID
+SemihostWriteCharacter (
+ IN CHAR8 Character
+ );
+
+VOID
+SemihostWriteString (
+ IN CHAR8 *String
+ );
+
+UINT32
+SemihostSystem (
+ IN CHAR8 *CommandLine
+ );
+
+#endif // __SEMIHOSTING_H__
diff --git a/roms/edk2/ArmPkg/Include/Library/StandaloneMmMmuLib.h b/roms/edk2/ArmPkg/Include/Library/StandaloneMmMmuLib.h new file mode 100644 index 000000000..1d2a0e0c2 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Library/StandaloneMmMmuLib.h @@ -0,0 +1,36 @@ +/** @file
+
+ Copyright (c) 2018, ARM Ltd. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __STANDALONEMM_MMU_LIB__
+#define __STANDALONEMM_MMU_LIB__
+
+EFI_STATUS
+ArmSetMemoryRegionNoExec (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+EFI_STATUS
+ArmClearMemoryRegionNoExec (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+EFI_STATUS
+ArmSetMemoryRegionReadOnly (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+EFI_STATUS
+ArmClearMemoryRegionReadOnly (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+#endif /* __STANDALONEMM_MMU_LIB__ */
diff --git a/roms/edk2/ArmPkg/Include/Ppi/ArmMpCoreInfo.h b/roms/edk2/ArmPkg/Include/Ppi/ArmMpCoreInfo.h new file mode 100644 index 000000000..871119bde --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Ppi/ArmMpCoreInfo.h @@ -0,0 +1,52 @@ +/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __ARM_MP_CORE_INFO_PPI_H__
+#define __ARM_MP_CORE_INFO_PPI_H__
+
+#include <Guid/ArmMpCoreInfo.h>
+
+#define ARM_MP_CORE_INFO_PPI_GUID \
+ { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
+
+/**
+ This service of the EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into
+ permanent memory.
+
+ @param PeiServices Pointer to the PEI Services Table.
+ @param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the
+ Temporary RAM contents.
+ @param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the
+ Temporary RAM contents.
+ @param CopySize Amount of memory to migrate from temporary to permanent memory.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when
+ TemporaryMemoryBase > PermanentMemoryBase.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI * ARM_MP_CORE_INFO_GET) (
+ OUT UINTN *ArmCoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+);
+
+///
+/// This service abstracts the ability to migrate contents of the platform early memory store.
+/// Note: The name EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI is different from the current PI 1.2 spec.
+/// This PPI was optional.
+///
+typedef struct {
+ ARM_MP_CORE_INFO_GET GetMpCoreInfo;
+} ARM_MP_CORE_INFO_PPI;
+
+extern EFI_GUID gArmMpCoreInfoPpiGuid;
+extern EFI_GUID gArmMpCoreInfoGuid;
+
+#endif
diff --git a/roms/edk2/ArmPkg/Include/Protocol/ArmScmi.h b/roms/edk2/ArmPkg/Include/Protocol/ArmScmi.h new file mode 100644 index 000000000..aedea8f61 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Protocol/ArmScmi.h @@ -0,0 +1,21 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#ifndef ARM_SCMI_H_
+#define ARM_SCMI_H_
+
+/* As per SCMI specification, maximum allowed ASCII string length
+ for various return values/parameters of a SCMI message.
+*/
+#define SCMI_MAX_STR_LEN 16
+
+#endif /* ARM_SCMI_H_ */
+
diff --git a/roms/edk2/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h b/roms/edk2/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h new file mode 100644 index 000000000..2f93ec923 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h @@ -0,0 +1,168 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#ifndef ARM_SCMI_BASE_PROTOCOL_H_
+#define ARM_SCMI_BASE_PROTOCOL_H_
+
+#include <Protocol/ArmScmi.h>
+
+#define BASE_PROTOCOL_VERSION 0x10000
+
+#define NUM_PROTOCOL_MASK 0xFFU
+#define NUM_AGENT_MASK 0xFFU
+
+#define NUM_AGENT_SHIFT 0x8
+
+/** Returns total number of protocols that are
+ implemented (excluding the Base protocol)
+*/
+#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK)
+
+// Returns total number of agents in the system.
+#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK)
+
+#define ARM_SCMI_BASE_PROTOCOL_GUID { \
+ 0xd7e5abe9, 0x33ab, 0x418e, {0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f} \
+ }
+
+extern EFI_GUID gArmScmiBaseProtocolGuid;
+
+typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL;
+
+/** Return version of the Base protocol supported by SCP firmware.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] Version Version of the supported SCMI Base protocol.
+
+ @retval EFI_SUCCESS The version of the protocol is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_BASE_GET_VERSION) (
+ IN SCMI_BASE_PROTOCOL *This,
+ OUT UINT32 *Version
+ );
+
+/** Return total number of SCMI protocols supported by the SCP firmware.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] TotalProtocols Total number of SCMI protocols supported.
+
+ @retval EFI_SUCCESS Total number of protocols supported are returned.
+ @retval EFI_DEVICE_ERROR SCP returns a SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS) (
+ IN SCMI_BASE_PROTOCOL *This,
+ OUT UINT32 *TotalProtocols
+ );
+
+/** Return vendor name.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] VendorIdentifier Null terminated ASCII string of up to
+ 16 bytes with a vendor name.
+
+ @retval EFI_SUCCESS VendorIdentifier is returned.
+ @retval EFI_DEVICE_ERROR SCP returns a SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_BASE_DISCOVER_VENDOR) (
+ IN SCMI_BASE_PROTOCOL *This,
+ OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
+ );
+
+/** Return sub vendor name.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] VendorIdentifier Null terminated ASCII string of up to
+ 16 bytes with a vendor name.
+
+ @retval EFI_SUCCESS VendorIdentifier is returned.
+ @retval EFI_DEVICE_ERROR SCP returns a SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR) (
+ IN SCMI_BASE_PROTOCOL *This,
+ OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
+ );
+
+/** Return implementation version.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] ImplementationVersion Vendor specific implementation version.
+
+ @retval EFI_SUCCESS Implementation version is returned.
+ @retval EFI_DEVICE_ERROR SCP returns a SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION) (
+ IN SCMI_BASE_PROTOCOL *This,
+ OUT UINT32 *ImplementationVersion
+ );
+
+/** Return list of protocols.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] ProtocolListSize Size of the ProtocolList.
+
+ @param[out] ProtocolList Protocol list.
+
+ @retval EFI_SUCCESS List of protocols is returned.
+ @retval EFI_BUFFER_TOO_SMALL ProtocolListSize is too small for the result.
+ It has been updated to the size needed.
+ @retval EFI_DEVICE_ERROR SCP returns a SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS) (
+ IN SCMI_BASE_PROTOCOL *This,
+ IN OUT UINT32 *ProtocolListSize,
+ OUT UINT8 *ProtocolList
+ );
+
+// Base protocol.
+typedef struct _SCMI_BASE_PROTOCOL {
+ SCMI_BASE_GET_VERSION GetVersion;
+ SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols;
+ SCMI_BASE_DISCOVER_VENDOR DiscoverVendor;
+ SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor;
+ SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion;
+ SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols;
+} SCMI_BASE_PROTOCOL;
+
+// SCMI Message IDs for Base protocol.
+typedef enum {
+ SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR = 0x3,
+ SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR = 0x4,
+ SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION = 0x5,
+ SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS = 0x6
+} SCMI_MESSAGE_ID_BASE;
+
+#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */
+
diff --git a/roms/edk2/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h b/roms/edk2/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h new file mode 100644 index 000000000..950141cbd --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h @@ -0,0 +1,191 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#ifndef ARM_SCMI_CLOCK2_PROTOCOL_H_
+#define ARM_SCMI_CLOCK2_PROTOCOL_H_
+
+#include <Protocol/ArmScmi.h>
+#include <Protocol/ArmScmiClockProtocol.h>
+
+#define ARM_SCMI_CLOCK2_PROTOCOL_GUID { \
+ 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } \
+ }
+
+extern EFI_GUID gArmScmiClock2ProtocolGuid;
+
+#define SCMI_CLOCK2_PROTOCOL_VERSION 1
+
+typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL;
+
+// Protocol Interface functions.
+
+/** Return version of the clock management protocol supported by SCP firmware.
+
+ @param[in] This A Pointer to SCMI_CLOCK2_PROTOCOL Instance.
+
+ @param[out] Version Version of the supported SCMI Clock management protocol.
+
+ @retval EFI_SUCCESS The version is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK2_GET_VERSION) (
+ IN SCMI_CLOCK2_PROTOCOL *This,
+ OUT UINT32 *Version
+ );
+
+/** Return total number of clock devices supported by the clock management
+ protocol.
+
+ @param[in] This A Pointer to SCMI_CLOCK2_PROTOCOL Instance.
+
+ @param[out] TotalClocks Total number of clocks supported.
+
+ @retval EFI_SUCCESS Total number of clocks supported is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS) (
+ IN SCMI_CLOCK2_PROTOCOL *This,
+ OUT UINT32 *TotalClocks
+ );
+
+/** Return attributes of a clock device.
+
+ @param[in] This A Pointer to SCMI_CLOCK2_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+
+ @param[out] Enabled If TRUE, the clock device is enabled.
+ @param[out] ClockAsciiName A NULL terminated ASCII string with the clock
+ name, of up to 16 bytes.
+
+ @retval EFI_SUCCESS Clock device attributes are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES) (
+ IN SCMI_CLOCK2_PROTOCOL *This,
+ IN UINT32 ClockId,
+ OUT BOOLEAN *Enabled,
+ OUT CHAR8 *ClockAsciiName
+ );
+
+/** Return list of rates supported by a given clock device.
+
+ @param[in] This A pointer to SCMI_CLOCK2_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+
+ @param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
+ supports range of clock rates which are non-linear.
+
+ SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
+ range of linear clock rates from Min to Max in steps.
+
+ @param[out] TotalRates Total number of rates.
+
+ @param[in,out] RateArraySize Size of the RateArray.
+
+ @param[out] RateArray List of clock rates.
+
+ @retval EFI_SUCCESS List of clock rates are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval EFI_BUFFER_TOO_SMALL RateArraySize is too small for the result.
+ It has been updated to the size needed.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES) (
+ IN SCMI_CLOCK2_PROTOCOL *This,
+ IN UINT32 ClockId,
+ OUT SCMI_CLOCK_RATE_FORMAT *Format,
+ OUT UINT32 *TotalRates,
+ IN OUT UINT32 *RateArraySize,
+ OUT SCMI_CLOCK_RATE *RateArray
+ );
+
+/** Get clock rate.
+
+ @param[in] This A Pointer to SCMI_CLOCK2_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+
+ @param[out] Rate Clock rate.
+
+ @retval EFI_SUCCESS Clock rate is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK2_RATE_GET) (
+ IN SCMI_CLOCK2_PROTOCOL *This,
+ IN UINT32 ClockId,
+ OUT UINT64 *Rate
+ );
+
+/** Set clock rate.
+
+ @param[in] This A Pointer to SCMI_CLOCK2_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+ @param[in] Rate Clock rate.
+
+ @retval EFI_SUCCESS Clock rate set success.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK2_RATE_SET) (
+ IN SCMI_CLOCK2_PROTOCOL *This,
+ IN UINT32 ClockId,
+ IN UINT64 Rate
+ );
+
+/** Enable/Disable specified clock.
+ Function is only available under gArmScmiClock2ProtocolGuid
+
+ @param[in] This A Pointer to SCMI_CLOCK2_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+ @param[in] Enable TRUE to enable, FALSE to disable.
+
+ @retval EFI_SUCCESS Clock enable/disable successful.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK2_ENABLE) (
+ IN SCMI_CLOCK2_PROTOCOL *This,
+ IN UINT32 ClockId,
+ IN BOOLEAN Enable
+ );
+
+typedef struct _SCMI_CLOCK2_PROTOCOL {
+ SCMI_CLOCK2_GET_VERSION GetVersion;
+ SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks;
+ SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes;
+ SCMI_CLOCK2_DESCRIBE_RATES DescribeRates;
+ SCMI_CLOCK2_RATE_GET RateGet;
+ SCMI_CLOCK2_RATE_SET RateSet;
+
+ // Extension to original ClockProtocol, added here so SCMI_CLOCK2_PROTOCOL
+ // can be cast to SCMI_CLOCK_PROTOCOL
+ UINTN Version; // For future expandability
+ SCMI_CLOCK2_ENABLE Enable;
+} SCMI_CLOCK2_PROTOCOL;
+
+#endif /* ARM_SCMI_CLOCK2_PROTOCOL_H_ */
diff --git a/roms/edk2/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h b/roms/edk2/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h new file mode 100644 index 000000000..b4d970dee --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h @@ -0,0 +1,212 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#ifndef ARM_SCMI_CLOCK_PROTOCOL_H_
+#define ARM_SCMI_CLOCK_PROTOCOL_H_
+
+#include <Protocol/ArmScmi.h>
+
+#define ARM_SCMI_CLOCK_PROTOCOL_GUID { \
+ 0x91ce67a8, 0xe0aa, 0x4012, {0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa} \
+ }
+
+extern EFI_GUID gArmScmiClockProtocolGuid;
+
+// Message Type for clock management protocol.
+typedef enum {
+ SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES = 0x3,
+ SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES = 0x4,
+ SCMI_MESSAGE_ID_CLOCK_RATE_SET = 0x5,
+ SCMI_MESSAGE_ID_CLOCK_RATE_GET = 0x6,
+ SCMI_MESSAGE_ID_CLOCK_CONFIG_SET = 0x7
+} SCMI_MESSAGE_ID_CLOCK;
+
+typedef enum {
+ SCMI_CLOCK_RATE_FORMAT_DISCRETE, // Non-linear range.
+ SCMI_CLOCK_RATE_FORMAT_LINEAR // Linear range.
+} SCMI_CLOCK_RATE_FORMAT;
+
+// Clock management protocol version.
+#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000
+
+#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU
+#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16
+#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU
+
+/** Total number of pending asynchronous clock rates changes
+ supported by the SCP, Attr Bits[23:16]
+*/
+#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \
+ (Attr >> SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT) && \
+ SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK)
+
+// Total of clock devices supported by the SCP, Attr Bits[15:0]
+#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK)
+
+#pragma pack(1)
+
+/* Depending on the format (linear/non-linear) supported by a clock device
+ either Rate or Min/Max/Step triplet is valid.
+*/
+typedef struct {
+ union {
+ UINT64 Min;
+ UINT64 Rate;
+ };
+ UINT64 Max;
+ UINT64 Step;
+} SCMI_CLOCK_RATE;
+
+#pragma pack()
+
+typedef struct _SCMI_CLOCK_PROTOCOL SCMI_CLOCK_PROTOCOL;
+
+// Protocol Interface functions.
+
+/** Return version of the clock management protocol supported by SCP firmware.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+
+ @param[out] Version Version of the supported SCMI Clock management protocol.
+
+ @retval EFI_SUCCESS The version is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK_GET_VERSION) (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ OUT UINT32 *Version
+ );
+
+/** Return total number of clock devices supported by the clock management
+ protocol.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+
+ @param[out] TotalClocks Total number of clocks supported.
+
+ @retval EFI_SUCCESS Total number of clocks supported is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS) (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ OUT UINT32 *TotalClocks
+ );
+
+/** Return attributes of a clock device.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+
+ @param[out] Enabled If TRUE, the clock device is enabled.
+ @param[out] ClockAsciiName A NULL terminated ASCII string with the clock
+ name, of up to 16 bytes.
+
+ @retval EFI_SUCCESS Clock device attributes are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES) (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ IN UINT32 ClockId,
+ OUT BOOLEAN *Enabled,
+ OUT CHAR8 *ClockAsciiName
+ );
+
+/** Return list of rates supported by a given clock device.
+
+ @param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+
+ @param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
+ supports range of clock rates which are non-linear.
+
+ SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
+ range of linear clock rates from Min to Max in steps.
+
+ @param[out] TotalRates Total number of rates.
+
+ @param[in,out] RateArraySize Size of the RateArray.
+
+ @param[out] RateArray List of clock rates.
+
+ @retval EFI_SUCCESS List of clock rates are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval EFI_BUFFER_TOO_SMALL RateArraySize is too small for the result.
+ It has been updated to the size needed.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES) (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ IN UINT32 ClockId,
+ OUT SCMI_CLOCK_RATE_FORMAT *Format,
+ OUT UINT32 *TotalRates,
+ IN OUT UINT32 *RateArraySize,
+ OUT SCMI_CLOCK_RATE *RateArray
+ );
+
+/** Get clock rate.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+
+ @param[out] Rate Clock rate.
+
+ @retval EFI_SUCCESS Clock rate is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK_RATE_GET) (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ IN UINT32 ClockId,
+ OUT UINT64 *Rate
+ );
+
+/** Set clock rate.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+ @param[in] Rate Clock rate.
+
+ @retval EFI_SUCCESS Clock rate set success.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_CLOCK_RATE_SET) (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ IN UINT32 ClockId,
+ IN UINT64 Rate
+ );
+
+typedef struct _SCMI_CLOCK_PROTOCOL {
+ SCMI_CLOCK_GET_VERSION GetVersion;
+ SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks;
+ SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes;
+ SCMI_CLOCK_DESCRIBE_RATES DescribeRates;
+ SCMI_CLOCK_RATE_GET RateGet;
+ SCMI_CLOCK_RATE_SET RateSet;
+} SCMI_CLOCK_PROTOCOL;
+
+#endif /* ARM_SCMI_CLOCK_PROTOCOL_H_ */
+
diff --git a/roms/edk2/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h b/roms/edk2/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h new file mode 100644 index 000000000..96a4d6673 --- /dev/null +++ b/roms/edk2/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h @@ -0,0 +1,259 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#ifndef ARM_SCMI_PERFORMANCE_PROTOCOL_H_
+#define ARM_SCMI_PERFORMANCE_PROTOCOL_H_
+
+#include <Protocol/ArmScmi.h>
+
+#define PERFORMANCE_PROTOCOL_VERSION 0x10000
+
+#define ARM_SCMI_PERFORMANCE_PROTOCOL_GUID { \
+ 0x9b8ba84, 0x3dd3, 0x49a6, {0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad} \
+ }
+
+extern EFI_GUID gArmScmiPerformanceProtocolGuid;
+
+typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL;
+
+#pragma pack(1)
+
+#define POWER_IN_MW_SHIFT 16
+#define POWER_IN_MW_MASK 0x1
+#define NUM_PERF_DOMAINS_MASK 0xFFFF
+
+// Total number of performance domains, Attr Bits [15:0]
+#define SCMI_PERF_TOTAL_DOMAINS(Attr) (Attr & NUM_PERF_DOMAINS_MASK)
+
+// A flag to express power values in mW or platform specific way, Attr Bit [16]
+#define SCMI_PERF_POWER_IN_MW(Attr) ((Attr >> POWER_IN_MW_SHIFT) & \
+ POWER_IN_MW_MASK)
+
+// Performance protocol attributes return values.
+typedef struct {
+ UINT32 Attributes;
+ UINT64 StatisticsAddress;
+ UINT32 StatisticsLen;
+} SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES;
+
+#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1)
+#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1)
+#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1)
+#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1)
+#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF)
+
+// Performance protocol domain attributes.
+typedef struct {
+ UINT32 Attributes;
+ UINT32 RateLimit;
+ UINT32 SustainedFreq;
+ UINT32 SustainedPerfLevel;
+ UINT8 Name[SCMI_MAX_STR_LEN];
+} SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES;
+
+// Worst case latency in microseconds, Bits[15:0]
+#define PERF_LATENCY_MASK 0xFFFF
+#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK)
+
+// Performance protocol performance level.
+typedef struct {
+ UINT32 Level;
+ UINT32 PowerCost;
+ UINT32 Latency;
+} SCMI_PERFORMANCE_LEVEL;
+
+// Performance protocol performance limit.
+typedef struct {
+ UINT32 RangeMax;
+ UINT32 RangeMin;
+} SCMI_PERFORMANCE_LIMITS;
+
+#pragma pack()
+
+/** Return version of the performance management protocol supported by SCP.
+ firmware.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+
+ @param[out] Version Version of the supported SCMI performance management
+ protocol.
+
+ @retval EFI_SUCCESS The version is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_PERFORMANCE_GET_VERSION) (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ OUT UINT32 *Version
+ );
+
+/** Return protocol attributes of the performance management protocol.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+
+ @param[out] Attributes Protocol attributes.
+
+ @retval EFI_SUCCESS Protocol attributes are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES) (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
+
+ );
+
+/** Return performance domain attributes.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+
+ @param[out] Attributes Performance domain attributes.
+
+ @retval EFI_SUCCESS Domain attributes are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES) (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes
+ );
+
+/** Return list of performance domain levels of a given domain.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+
+ @param[out] NumLevels Total number of levels a domain can support.
+
+ @param[in,out] LevelArraySize Size of the performance level array.
+
+ @param[out] LevelArray Array of the performance levels.
+
+ @retval EFI_SUCCESS Domain levels are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval EFI_BUFFER_TOO_SMALL LevelArraySize is too small for the result.
+ It has been updated to the size needed.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS) (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ OUT UINT32 *NumLevels,
+ IN OUT UINT32 *LevelArraySize,
+ OUT SCMI_PERFORMANCE_LEVEL *LevelArray
+ );
+
+/** Set performance limits of a domain.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+ @param[in] Limit Performance limit to set.
+
+ @retval EFI_SUCCESS Performance limits set successfully.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET) (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ IN SCMI_PERFORMANCE_LIMITS *Limits
+ );
+
+/** Get performance limits of a domain.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+
+ @param[out] Limit Performance Limits of the domain.
+
+ @retval EFI_SUCCESS Performance limits are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET) (
+ SCMI_PERFORMANCE_PROTOCOL *This,
+ UINT32 DomainId,
+ SCMI_PERFORMANCE_LIMITS *Limits
+ );
+
+/** Set performance level of a domain.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+ @param[in] Level Performance level of the domain.
+
+ @retval EFI_SUCCESS Performance level set successfully.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET) (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ IN UINT32 Level
+ );
+
+/** Get performance level of a domain.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+
+ @param[out] Level Performance level of the domain.
+
+ @retval EFI_SUCCESS Performance level got successfully.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET) (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ OUT UINT32 *Level
+ );
+
+typedef struct _SCMI_PERFORMANCE_PROTOCOL {
+ SCMI_PERFORMANCE_GET_VERSION GetVersion;
+ SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes;
+ SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes;
+ SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels;
+ SCMI_PERFORMANCE_LIMITS_SET LimitsSet;
+ SCMI_PERFORMANCE_LIMITS_GET LimitsGet;
+ SCMI_PERFORMANCE_LEVEL_SET LevelSet;
+ SCMI_PERFORMANCE_LEVEL_GET LevelGet;
+} SCMI_PERFORMANCE_PROTOCOL;
+
+typedef enum {
+ SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES = 0x3,
+ SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS = 0x4,
+ SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET = 0x5,
+ SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET = 0x6,
+ SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET = 0x7,
+ SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET = 0x8,
+} SCMI_MESSAGE_ID_PERFORMANCE;
+
+#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */
+
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