diff options
Diffstat (limited to 'roms/u-boot/arch/mips/dts')
69 files changed, 9642 insertions, 0 deletions
diff --git a/roms/u-boot/arch/mips/dts/Makefile b/roms/u-boot/arch/mips/dts/Makefile new file mode 100644 index 000000000..215283cfa --- /dev/null +++ b/roms/u-boot/arch/mips/dts/Makefile @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0+ + +dtb-$(CONFIG_TARGET_AP121) += ap121.dtb +dtb-$(CONFIG_TARGET_AP143) += ap143.dtb +dtb-$(CONFIG_TARGET_AP152) += ap152.dtb +dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb +dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb +dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb +dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb +dtb-$(CONFIG_BOARD_BROADCOM_BCM968380GERG) += brcm,bcm968380gerg.dtb +dtb-$(CONFIG_BOARD_COMTREND_AR5315U) += comtrend,ar-5315u.dtb +dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb +dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb +dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb +dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb +dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb +dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb +dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb +dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb +dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb +dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb +dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb +dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb +dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb +dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb +dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb +dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb +dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb +dtb-$(CONFIG_BOARD_VOCORE2) += vocore_vocore2.dtb +dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb +dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb +dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb +dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb +dtb-$(CONFIG_SOC_SERVALT) += servalt_pcb116.dtb +dtb-$(CONFIG_SOC_SERVAL) += serval_pcb105.dtb serval_pcb106.dtb + +targets += $(dtb-y) + +# Add any required device tree compiler flags here +DTC_FLAGS += + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/roms/u-boot/arch/mips/dts/ap121.dts b/roms/u-boot/arch/mips/dts/ap121.dts new file mode 100644 index 000000000..f30af5021 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/ap121.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + */ + +/dts-v1/; +#include "ar933x.dtsi" + +/ { + model = "AP121 Reference Board"; + compatible = "qca,ap121", "qca,ar933x"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&xtal { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + memory-map = <0x9f000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +&gmac0 { + phy-mode = "rmii"; + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/ap143.dts b/roms/u-boot/arch/mips/dts/ap143.dts new file mode 100644 index 000000000..93a098052 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/ap143.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + */ + +/dts-v1/; +#include "qca953x.dtsi" + +/ { + model = "AP143 Reference Board"; + compatible = "qca,ap143", "qca,qca953x"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&xtal { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + memory-map = <0x9f000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; +}; diff --git a/roms/u-boot/arch/mips/dts/ap152.dts b/roms/u-boot/arch/mips/dts/ap152.dts new file mode 100644 index 000000000..1722290c7 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/ap152.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Rosy Song <rosysong@rosinson.com> + */ + +/dts-v1/; +#include "qca956x.dtsi" + +/ { + model = "AP152 Reference Board"; + compatible = "qca,ap152", "qca,qca956x"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&gmac0 { + phy-mode = "sgmii"; + status = "okay"; +}; + +&xtal { + clock-frequency = <25000000>; +}; + +&uart0 { + clock-frequency = <25000000>; + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + memory-map = <0x9f000000 0x01000000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/ar933x.dtsi b/roms/u-boot/arch/mips/dts/ar933x.dtsi new file mode 100644 index 000000000..37354324f --- /dev/null +++ b/roms/u-boot/arch/mips/dts/ar933x.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + */ + +#include "skeleton.dtsi" + +/ { + compatible = "qca,ar933x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + pinctrl { + u-boot,dm-pre-reloc; + compatible = "qca,ar933x-pinctrl"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18040000 0x100>; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + ehci0: ehci@1b000100 { + compatible = "generic-ehci"; + reg = <0x1b000100 0x100>; + + status = "disabled"; + }; + + uart0: uart@18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x20>; + + status = "disabled"; + }; + + gmac0: eth@0x19000000 { + compatible = "qca,ag933x-mac"; + reg = <0x19000000 0x200>; + phy = <&phy0>; + phy-mode = "rmii"; + + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + + gmac1: eth@0x1a000000 { + compatible = "qca,ag933x-mac"; + reg = <0x1a000000 0x200>; + phy = <&phy0>; + phy-mode = "rgmii"; + + status = "disabled"; + }; + }; + + spi0: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/ar934x.dtsi b/roms/u-boot/arch/mips/dts/ar934x.dtsi new file mode 100644 index 000000000..9bc2da112 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/ar934x.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Marek Vasut <marex@denx.de> + */ + +#include "skeleton.dtsi" + +/ { + compatible = "qca,ar934x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips74Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + ehci0: ehci@1b000100 { + compatible = "generic-ehci"; + reg = <0x1b000100 0x100>; + + status = "disabled"; + }; + + uart0: uart@18020000 { + compatible = "ns16550"; + reg = <0x18020000 0x20>; + reg-shift = <2>; + + status = "disabled"; + }; + + gmac0: eth@0x19000000 { + compatible = "qca,ag934x-mac"; + reg = <0x19000000 0x200>; + phy = <&phy0>; + phy-mode = "rgmii"; + + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + + gmac1: eth@0x1a000000 { + compatible = "qca,ag934x-mac"; + reg = <0x1a000000 0x200>; + phy = <&phy1>; + phy-mode = "rgmii"; + + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + }; + + spi0: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm3380.dtsi b/roms/u-boot/arch/mips/dts/brcm,bcm3380.dtsi new file mode 100644 index 000000000..7cccec5da --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm3380.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +#include <dt-bindings/clock/bcm3380-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/bcm3380-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm3380"; + + aliases { + spi0 = &spi; + }; + + cpus { + reg = <0x14e00000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm3380-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm3380-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk0: periph-clk@14e00004 { + compatible = "brcm,bcm6345-clk"; + reg = <0x14e00004 0x4>; + #clock-cells = <1>; + }; + + periph_clk1: periph-clk@14e00008 { + compatible = "brcm,bcm6345-clk"; + reg = <0x14e00008 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + memory-controller@12000000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x12000000 0x1000>; + u-boot,dm-pre-reloc; + }; + + periph_rst0: reset-controller@14e0008c { + compatible = "brcm,bcm6345-reset"; + reg = <0x14e0008c 0x4>; + #reset-cells = <1>; + }; + + periph_rst1: reset-controller@14e00090 { + compatible = "brcm,bcm6345-reset"; + reg = <0x14e00090 0x4>; + #reset-cells = <1>; + }; + + pll_cntl: syscon@14e00094 { + compatible = "syscon"; + reg = <0x14e00094 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + wdt: watchdog@14e000dc { + compatible = "brcm,bcm6345-wdt"; + reg = <0x14e000dc 0xc>; + + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio0: gpio-controller@14e00100 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x14e00100 0x4>, <0x14e00108 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio1: gpio-controller@14e00104 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x14e00104 0x4>, <0x14e0010c 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <3>; + + status = "disabled"; + }; + + uart0: serial@14e00200 { + compatible = "brcm,bcm6345-uart"; + reg = <0x14e00200 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@14e00220 { + compatible = "brcm,bcm6345-uart"; + reg = <0x14e00220 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + spi: spi@14e02000 { + compatible = "brcm,bcm6358-spi"; + reg = <0x14e02000 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk0 BCM3380_CLK0_SPI>; + resets = <&periph_rst0 BCM3380_RST0_SPI>; + spi-max-frequency = <25000000>; + num-cs = <6>; + + status = "disabled"; + }; + + leds: led-controller@14e00f00 { + compatible = "brcm,bcm6328-leds"; + reg = <0x14e00f00 0x1c>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm6318.dtsi b/roms/u-boot/arch/mips/dts/brcm,bcm6318.dtsi new file mode 100644 index 000000000..d678dab24 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm6318.dtsi @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +#include <dt-bindings/clock/bcm6318-clock.h> +#include <dt-bindings/dma/bcm6318-dma.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power-domain/bcm6318-power-domain.h> +#include <dt-bindings/reset/bcm6318-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6318"; + + aliases { + spi0 = &spi; + }; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6318-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + + ubus_clk: ubus-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000008 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@10000068 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x10000068 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + pll_cntl: syscon@10000074 { + compatible = "syscon"; + reg = <0x10000074 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + gpio1: gpio-controller@10000080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000080 0x4>, <0x10000088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <18>; + + status = "disabled"; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 0x4>, <0x1000008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + leds: led-controller@10000200 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10000200 0x28>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + periph_pwr: power-controller@100008e8 { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x100008e8 0x4>; + #power-domain-cells = <1>; + }; + + spi: spi@10003000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10003000 0x600>; + clocks = <&periph_clk BCM6318_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM6318_RST_SPI>; + spi-max-frequency = <33333334>; + num-cs = <3>; + + status = "disabled"; + }; + + memory-controller@10004000 { + compatible = "brcm,bcm6318-mc"; + reg = <0x10004000 0x38>; + u-boot,dm-pre-reloc; + }; + + ehci: usb-controller@10005000 { + compatible = "brcm,bcm6318-ehci", "generic-ehci"; + reg = <0x10005000 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10005100 { + compatible = "brcm,bcm6318-ohci", "generic-ohci"; + reg = <0x10005100 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10005200 { + compatible = "brcm,bcm6318-usbh"; + reg = <0x10005200 0x30>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6318_CLK_USB>; + clock-names = "usbh"; + power-domains = <&periph_pwr BCM6318_PWR_USB>; + resets = <&periph_rst BCM6318_RST_USBH>; + + status = "disabled"; + }; + + enet: ethernet@10080000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10080000 0x8000>; + clocks = <&periph_clk BCM6318_CLK_ROBOSW250>, + <&periph_clk BCM6318_CLK_ROBOSW025>, + <&ubus_clk BCM6318_UCLK_ROBOSW>; + resets = <&periph_rst BCM6318_RST_ENETSW>, + <&periph_rst BCM6318_RST_EPHY>; + dmas = <&iudma BCM6318_DMA_ENETSW_RX>, + <&iudma BCM6318_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <5>; + + status = "disabled"; + }; + + iudma: dma-controller@10088000 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x10088000 0x80>, + <0x10088200 0x80>, + <0x10088400 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm63268.dtsi b/roms/u-boot/arch/mips/dts/brcm,bcm63268.dtsi new file mode 100644 index 000000000..529424252 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm63268.dtsi @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +#include <dt-bindings/clock/bcm63268-clock.h> +#include <dt-bindings/dma/bcm63268-dma.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power-domain/bcm63268-power-domain.h> +#include <dt-bindings/reset/bcm63268-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm63268"; + + aliases { + spi0 = &lsspi; + spi1 = &hsspi; + }; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + + timer_clk: timer-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x100000ac 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000008 { + compatible = "syscon"; + reg = <0x10000008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@1000009c { + compatible = "brcm,bcm6345-wdt"; + reg = <0x1000009c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio1: gpio-controller@100000c0 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100000c0 0x4>, <0x100000c8 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <20>; + + status = "disabled"; + }; + + gpio0: gpio-controller@100000c4 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100000c4 0x4>, <0x100000cc 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + uart0: serial@10000180 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000180 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@100001a0 { + compatible = "brcm,bcm6345-uart"; + reg = <0x100001a0 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + nand: nand-controller@10000200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6368", + "brcm,brcmnand-v4.0", + "brcm,brcmnand"; + reg-names = "nand", + "nand-cache", + "nand-int-base"; + reg = <0x10000200 0x180>, + <0x10000600 0x200>, + <0x100000b0 0x10>; + clocks = <&periph_clk BCM63268_CLK_NAND>; + clock-names = "nand"; + + status = "disabled"; + }; + + periph_pwr: power-controller@1000184c { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x1000184c 0x4>; + #power-domain-cells = <1>; + }; + + lsspi: spi@10000800 { + compatible = "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM63268_CLK_SPI>; + resets = <&periph_rst BCM63268_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <8>; + + status = "disabled"; + }; + + hsspi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM63268_RST_SPI>; + spi-max-frequency = <50000000>; + num-cs = <8>; + + status = "disabled"; + }; + + leds: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10001900 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + ehci: usb-controller@10002500 { + compatible = "brcm,bcm63268-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10002600 { + compatible = "brcm,bcm63268-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10002700 { + compatible = "brcm,bcm63268-usbh"; + reg = <0x10002700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>; + clock-names = "usbh", "usb_ref"; + power-domains = <&periph_pwr BCM63268_PWR_USBH>; + resets = <&periph_rst BCM63268_RST_USBH>; + + status = "disabled"; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x894>; + u-boot,dm-pre-reloc; + }; + + iudma: dma-controller@1000d800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10700000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10700000 0x10000>; + clocks = <&periph_clk BCM63268_CLK_GMAC>, + <&periph_clk BCM63268_CLK_ROBOSW>, + <&periph_clk BCM63268_CLK_ROBOSW250>, + <&timer_clk BCM63268_TCLK_EPHY1>, + <&timer_clk BCM63268_TCLK_EPHY2>, + <&timer_clk BCM63268_TCLK_EPHY3>, + <&timer_clk BCM63268_TCLK_GPHY>; + resets = <&periph_rst BCM63268_RST_ENETSW>, + <&periph_rst BCM63268_RST_EPHY>, + <&periph_rst BCM63268_RST_GPHY>; + dmas = <&iudma BCM63268_DMA_ENETSW_RX>, + <&iudma BCM63268_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,rgmii-override; + brcm,rgmii-timing; + + status = "disabled"; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm6328.dtsi b/roms/u-boot/arch/mips/dts/brcm,bcm6328.dtsi new file mode 100644 index 000000000..350c0e903 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm6328.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +#include <dt-bindings/clock/bcm6328-clock.h> +#include <dt-bindings/dma/bcm6328-dma.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power-domain/bcm6328-power-domain.h> +#include <dt-bindings/reset/bcm6328-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6328"; + + aliases { + spi0 = &spi; + }; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6328-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6328-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + }; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + pll_cntl: syscon@10000068 { + compatible = "syscon"; + reg = <0x10000068 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + wdt: watchdog@1000005c { + compatible = "brcm,bcm6345-wdt"; + reg = <0x1000005c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 0x4>, <0x1000008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + nand: nand-controller@10000200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6368", + "brcm,brcmnand-v2.2", + "brcm,brcmnand"; + reg-names = "nand", + "nand-cache", + "nand-int-base"; + reg = <0x10000200 0x180>, + <0x10000400 0x200>, + <0x100000b0 0x10>; + + status = "disabled"; + }; + + leds: led-controller@10000800 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10000800 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM6328_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM6328_RST_SPI>; + spi-max-frequency = <33333334>; + num-cs = <3>; + + status = "disabled"; + }; + + periph_pwr: power-controller@10001848 { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x10001848 0x4>; + #power-domain-cells = <1>; + }; + + ehci: usb-controller@10002500 { + compatible = "brcm,bcm6328-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10002600 { + compatible = "brcm,bcm6328-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10002700 { + compatible = "brcm,bcm6328-usbh"; + reg = <0x10002700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6328_CLK_USBH>; + clock-names = "usbh"; + power-domains = <&periph_pwr BCM6328_PWR_USBH>; + resets = <&periph_rst BCM6328_RST_USBH>; + + status = "disabled"; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x864>; + u-boot,dm-pre-reloc; + }; + + iudma: dma-controller@1000d800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10e00000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10e00000 0x10000>; + clocks = <&periph_clk BCM6328_CLK_ROBOSW>; + resets = <&periph_rst BCM6328_RST_ENETSW>, + <&periph_rst BCM6328_RST_EPHY>; + dmas = <&iudma BCM6328_DMA_ENETSW_RX>, + <&iudma BCM6328_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <5>; + + status = "disabled"; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm6338.dtsi b/roms/u-boot/arch/mips/dts/brcm,bcm6338.dtsi new file mode 100644 index 000000000..c547e949d --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm6338.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +#include <dt-bindings/clock/bcm6338-clock.h> +#include <dt-bindings/dma/bcm6338-dma.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/bcm6338-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6338"; + + aliases { + spi0 = &spi; + }; + + cpus { + reg = <0xfffe0000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6338-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0xfffe0004 0x4>; + #clock-cells = <1>; + }; + }; + + pflash: nor@1fc00000 { + compatible = "cfi-flash"; + reg = <0x1fc00000 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@fffe0008 { + compatible = "syscon"; + reg = <0xfffe0008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@fffe0028 { + compatible = "brcm,bcm6345-reset"; + reg = <0xfffe0028 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@fffe021c { + compatible = "brcm,bcm6345-wdt"; + reg = <0xfffe021c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + uart0: serial@fffe0300 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0300 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + gpio: gpio-controller@fffe0404 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + + status = "disabled"; + }; + + spi: spi@fffe0c00 { + compatible = "brcm,bcm6348-spi"; + reg = <0xfffe0c00 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6338_CLK_SPI>; + resets = <&periph_rst BCM6338_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + + memory-controller@fffe3100 { + compatible = "brcm,bcm6338-mc"; + reg = <0xfffe3100 0x38>; + u-boot,dm-pre-reloc; + }; + + iudma: dma-controller@fffe2400 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe2400 0x1c>, + <0xfffe2500 0x60>, + <0xfffe2600 0x60>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <6>; + resets = <&periph_rst BCM6338_RST_DMAMEM>; + }; + + enet: ethernet@fffe2800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe2800 0x2dc>; + clocks = <&periph_clk BCM6338_CLK_ENET>; + resets = <&periph_rst BCM6338_RST_ENET>; + dmas = <&iudma BCM6338_DMA_ENET_RX>, + <&iudma BCM6338_DMA_ENET_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm6348.dtsi b/roms/u-boot/arch/mips/dts/brcm,bcm6348.dtsi new file mode 100644 index 000000000..79e7bd892 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm6348.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +#include <dt-bindings/clock/bcm6348-clock.h> +#include <dt-bindings/dma/bcm6348-dma.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/bcm6348-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6348"; + + aliases { + spi0 = &spi; + }; + + cpus { + reg = <0xfffe0000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6348-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0xfffe0004 0x4>; + #clock-cells = <1>; + }; + }; + + pflash: nor@1fc00000 { + compatible = "cfi-flash"; + reg = <0x1fc00000 0x2000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@fffe0008 { + compatible = "syscon"; + reg = <0xfffe0008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@fffe0028 { + compatible = "brcm,bcm6345-reset"; + reg = <0xfffe0028 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@fffe021c { + compatible = "brcm,bcm6345-wdt"; + reg = <0xfffe021c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + uart0: serial@fffe0300 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0300 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + gpio1: gpio-controller@fffe0400 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + + status = "disabled"; + }; + + gpio0: gpio-controller@fffe0404 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + spi: spi@fffe0c00 { + compatible = "brcm,bcm6348-spi"; + reg = <0xfffe0c00 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6348_CLK_SPI>; + resets = <&periph_rst BCM6348_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + + ohci: usb-controller@fffe1b00 { + compatible = "brcm,bcm6348-ohci", "generic-ohci"; + reg = <0xfffe1b00 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@fffe1c00 { + compatible = "brcm,bcm6348-usbh"; + reg = <0xfffe1c00 0x4>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6348_CLK_USBH>; + clock-names = "usbh"; + resets = <&periph_rst BCM6348_RST_USBH>; + + status = "disabled"; + }; + + memory-controller@fffe2300 { + compatible = "brcm,bcm6338-mc"; + reg = <0xfffe2300 0x38>; + u-boot,dm-pre-reloc; + }; + + enet0: ethernet@fffe6000 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe6000 0x2dc>; + dmas = <&iudma BCM6348_DMA_ENET0_RX>, + <&iudma BCM6348_DMA_ENET0_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + enet1: ethernet@fffe6800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe6800 0x2dc>; + dmas = <&iudma BCM6348_DMA_ENET1_RX>, + <&iudma BCM6348_DMA_ENET1_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + iudma: dma-controller@fffe7000 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe7000 0x1c>, + <0xfffe7100 0x40>, + <0xfffe7200 0x40>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&periph_clk BCM6348_CLK_ENET>; + resets = <&periph_rst BCM6348_RST_ENET>, + <&periph_rst BCM6348_RST_DMAMEM>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm6358.dtsi b/roms/u-boot/arch/mips/dts/brcm,bcm6358.dtsi new file mode 100644 index 000000000..5e9c9ad76 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm6358.dtsi @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +#include <dt-bindings/clock/bcm6358-clock.h> +#include <dt-bindings/dma/bcm6358-dma.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/bcm6358-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6358"; + + aliases { + spi0 = &spi; + }; + + cpus { + reg = <0xfffe0000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0xfffe0004 0x4>; + #clock-cells = <1>; + }; + }; + + pflash: nor@1e000000 { + compatible = "cfi-flash"; + reg = <0x1e000000 0x2000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@fffe0008 { + compatible = "syscon"; + reg = <0xfffe0008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@fffe0034 { + compatible = "brcm,bcm6345-reset"; + reg = <0xfffe0034 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@fffe005c { + compatible = "brcm,bcm6345-wdt"; + reg = <0xfffe005c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio1: gpio-controller@fffe0080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + + status = "disabled"; + }; + + gpio0: gpio-controller@fffe0084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + leds: led-controller@fffe00d0 { + compatible = "brcm,bcm6358-leds"; + reg = <0xfffe00d0 0x8>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart0: serial@fffe0100 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@fffe0120 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + spi: spi@fffe0800 { + compatible = "brcm,bcm6358-spi"; + reg = <0xfffe0800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6358_CLK_SPI>; + resets = <&periph_rst BCM6358_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + + memory-controller@fffe1200 { + compatible = "brcm,bcm6358-mc"; + reg = <0xfffe1200 0x4c>; + u-boot,dm-pre-reloc; + }; + + ehci: usb-controller@fffe1300 { + compatible = "brcm,bcm6358-ehci", "generic-ehci"; + reg = <0xfffe1300 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@fffe1400 { + compatible = "brcm,bcm6358-ohci", "generic-ohci"; + reg = <0xfffe1400 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@fffe1500 { + compatible = "brcm,bcm6358-usbh"; + reg = <0xfffe1500 0x28>; + #phy-cells = <0>; + resets = <&periph_rst BCM6358_RST_USBH>; + + status = "disabled"; + }; + + enet0: ethernet@fffe4000 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe4000 0x2dc>; + clocks = <&periph_clk BCM6358_CLK_ENET0>; + dmas = <&iudma BCM6358_DMA_ENET0_RX>, + <&iudma BCM6358_DMA_ENET0_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + enet1: ethernet@fffe4800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe4800 0x2dc>; + clocks = <&periph_clk BCM6358_CLK_ENET1>; + dmas = <&iudma BCM6358_DMA_ENET1_RX>, + <&iudma BCM6358_DMA_ENET1_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + iudma: dma-controller@fffe5000 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe5000 0x24>, + <0xfffe5100 0x80>, + <0xfffe5200 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + clocks = <&periph_clk BCM6358_CLK_EMUSB>, + <&periph_clk BCM6358_CLK_USBSU>, + <&periph_clk BCM6358_CLK_EPHY>; + resets = <&periph_rst BCM6358_RST_ENET>, + <&periph_rst BCM6358_RST_EPHY>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm6362.dtsi b/roms/u-boot/arch/mips/dts/brcm,bcm6362.dtsi new file mode 100644 index 000000000..71598f97b --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm6362.dtsi @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +#include <dt-bindings/clock/bcm6362-clock.h> +#include <dt-bindings/dma/bcm6362-dma.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power-domain/bcm6362-power-domain.h> +#include <dt-bindings/reset/bcm6362-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6362"; + + aliases { + spi0 = &lsspi; + spi1 = &hsspi; + }; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6362-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6362-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + }; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000008 { + compatible = "syscon"; + reg = <0x10000008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@1000005c { + compatible = "brcm,bcm6345-wdt"; + reg = <0x1000005c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio1: gpio-controller@10000080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000080 0x4>, <0x10000088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + + status = "disabled"; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 0x4>, <0x1000008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + nand: nand-controller@10000200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6368", + "brcm,brcmnand-v2.2", + "brcm,brcmnand"; + reg-names = "nand", + "nand-cache", + "nand-int-base"; + reg = <0x10000200 0x180>, + <0x10000600 0x200>, + <0x100000b0 0x10>; + clocks = <&periph_clk BCM6362_CLK_NAND>; + clock-names = "nand"; + + status = "disabled"; + }; + + lsspi: spi@10000800 { + compatible = "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6362_CLK_SPI>; + resets = <&periph_rst BCM6362_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <8>; + + status = "disabled"; + }; + + hsspi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM6362_RST_SPI>; + spi-max-frequency = <50000000>; + num-cs = <8>; + + status = "disabled"; + }; + + leds: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10001900 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + periph_pwr: power-controller@10001848 { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x10001848 0x4>; + #power-domain-cells = <1>; + }; + + ehci: usb-controller@10002500 { + compatible = "brcm,bcm6362-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10002600 { + compatible = "brcm,bcm6362-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10002700 { + compatible = "brcm,bcm6368-usbh"; + reg = <0x10002700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6362_CLK_USBH>; + clock-names = "usbh"; + power-domains = <&periph_pwr BCM6362_PWR_USBH>; + resets = <&periph_rst BCM6362_RST_USBH>; + + status = "disabled"; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x864>; + u-boot,dm-pre-reloc; + }; + + iudma: dma-controller@1000d800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10e00000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10e00000 0x10000>; + clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>, + <&periph_clk BCM6362_CLK_SWPKT_SAR>, + <&periph_clk BCM6362_CLK_ROBOSW>; + resets = <&periph_rst BCM6362_RST_ENETSW>, + <&periph_rst BCM6362_RST_EPHY>; + dmas = <&iudma BCM6362_DMA_ENETSW_RX>, + <&iudma BCM6362_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <6>; + + status = "disabled"; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm6368.dtsi b/roms/u-boot/arch/mips/dts/brcm,bcm6368.dtsi new file mode 100644 index 000000000..69be65056 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm6368.dtsi @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +#include <dt-bindings/clock/bcm6368-clock.h> +#include <dt-bindings/dma/bcm6368-dma.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/bcm6368-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6368"; + + aliases { + spi0 = &spi; + }; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6368-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6368-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + }; + + pflash: nor@18000000 { + compatible = "cfi-flash"; + reg = <0x18000000 0x2000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000008 { + compatible = "syscon"; + reg = <0x10000008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@1000005c { + compatible = "brcm,bcm6345-wdt"; + reg = <0x1000005c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio1: gpio-controller@10000080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000080 0x4>, <0x10000088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <6>; + + status = "disabled"; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 0x4>, <0x1000008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + leds: led-controller@100000d0 { + compatible = "brcm,bcm6358-leds"; + reg = <0x100000d0 0x8>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + nand: nand-controller@10000200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6368", + "brcm,brcmnand-v2.1", + "brcm,brcmnand"; + reg-names = "nand", + "nand-cache", + "nand-int-base"; + reg = <0x10000200 0x180>, + <0x10000600 0x200>, + <0x100000b0 0x10>; + clocks = <&periph_clk BCM6368_CLK_NAND>; + clock-names = "nand"; + + status = "disabled"; + }; + + spi: spi@10000800 { + compatible = "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6368_CLK_SPI>; + resets = <&periph_rst BCM6368_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <6>; + + status = "disabled"; + }; + + memory-controller@10001200 { + compatible = "brcm,bcm6358-mc"; + reg = <0x10001200 0x4c>; + u-boot,dm-pre-reloc; + }; + + ehci: usb-controller@10001500 { + compatible = "brcm,bcm6368-ehci", "generic-ehci"; + reg = <0x10001500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10001600 { + compatible = "brcm,bcm6368-ohci", "generic-ohci"; + reg = <0x10001600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10001700 { + compatible = "brcm,bcm6368-usbh"; + reg = <0x10001700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6368_CLK_USBH>; + clock-names = "usbh"; + resets = <&periph_rst BCM6368_RST_USBH>; + + status = "disabled"; + }; + + iudma: dma-controller@10006800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x10006800 0x80>, + <0x10006a00 0x80>, + <0x10006c00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10f00000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10f00000 0x10000>; + clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>, + <&periph_clk BCM6368_CLK_SWPKT_SAR>, + <&periph_clk BCM6368_CLK_ROBOSW>; + resets = <&periph_rst BCM6368_RST_SWITCH>, + <&periph_rst BCM6368_RST_EPHY>; + dmas = <&iudma BCM6368_DMA_ENETSW_RX>, + <&iudma BCM6368_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <6>; + + status = "disabled"; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm6838.dtsi b/roms/u-boot/arch/mips/dts/brcm,bcm6838.dtsi new file mode 100644 index 000000000..6676f83b2 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm6838.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> + */ + +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6838"; + + cpus { + reg = <0x14e00000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6838-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6838-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + memory: memory-controller@12000000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x12000000 0x1000>; + u-boot,dm-pre-reloc; + }; + + gpio_test_port: syscon@14e00294 { + compatible = "syscon"; + reg = <0x14e00294 0x1c>; + }; + + pinctrl: pinctrl { + compatible = "brcm,bcm6838-pinctrl"; + regmap = <&gpio_test_port>; + brcm,pins-count = <74>; + brcm,functions-count = <8>; + }; + + uart0: serial@14e00500 { + compatible = "brcm,bcm6345-uart"; + reg = <0x14e00500 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + wdt0: watchdog@14e002d0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x14e002d0 0xc>; + clocks = <&periph_osc>; + }; + + wdt1: watchdog@14e002dc { + compatible = "brcm,bcm6345-wdt"; + reg = <0x14e002dc 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt0>; + }; + + leds: led-controller@14e00f00 { + compatible = "brcm,bcm6328-leds"; + reg = <0x14e00f00 0x28>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + gpio_lo: gpio-controller@14e00100 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x14e00100 0x4>, <0x14e0012c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio_mid0: gpio-controller@14e00104 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x14e00104 0x4>, <0x14e00130 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio_mid1: gpio-controller@14e00108 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x14e00108 0x4>, <0x14e00134 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + nand: nand-controller@14e02200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6838", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x14e02200 0x180>, + <0x14e000f0 0x10>, + <0x14e02600 0x180>; + status = "disabled"; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/brcm,bcm968380gerg.dts b/roms/u-boot/arch/mips/dts/brcm,bcm968380gerg.dts new file mode 100644 index 000000000..5a5ac0ea7 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/brcm,bcm968380gerg.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> + */ + +/dts-v1/; + +#include "brcm,bcm6838.dtsi" + +/ { + model = "Broadcom bcm68380gerg"; + compatible = "broadcom,bcm68380gerg", "brcm,bcm6838"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&memory { + force-size = <0x10000000>; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&leds { + status = "okay"; + + led@0 { + reg = <0>; + active-low; + label = "bcm968380gerg:green:usb"; + }; +}; + +&gpio_lo { + status = "okay"; +}; + +&gpio_mid0 { + status = "okay"; +}; + +&gpio_mid1 { + status = "okay"; +}; + +&nand { + status = "okay"; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/ci20.dts b/roms/u-boot/arch/mips/dts/ci20.dts new file mode 100644 index 000000000..8d6417af7 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/ci20.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include "jz4780.dtsi" + +/ { + compatible = "img,ci20", "ingenic,jz4780"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial4:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000 + 0x30000000 0x30000000>; + }; +}; + +&ext { + clock-frequency = <48000000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&nemc { + status = "okay"; + + nandc: nand-controller@1 { + compatible = "ingenic,jz4780-nand"; + reg = <1 0 0x1000000>; + + #address-cells = <1>; + #size-cells = <0>; + + ingenic,bch-controller = <&bch>; + + ingenic,nemc-tAS = <10>; + ingenic,nemc-tAH = <5>; + ingenic,nemc-tBP = <10>; + ingenic,nemc-tAW = <15>; + ingenic,nemc-tSTRV = <100>; + + nand@1 { + reg = <1>; + + nand-ecc-step-size = <1024>; + nand-ecc-strength = <24>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x0 0x0 0x800000>; + }; + + partition@0x800000 { + label = "u-boot"; + reg = <0x0 0x800000 0x0 0x200000>; + }; + + partition@0xa00000 { + label = "u-boot-env"; + reg = <0x0 0xa00000 0x0 0x200000>; + }; + + partition@0xc00000 { + label = "boot"; + reg = <0x0 0xc00000 0x0 0x4000000>; + }; + + partition@0x8c00000 { + label = "system"; + reg = <0x0 0x4c00000 0x1 0xfb400000>; + }; + }; + }; + }; +}; + +&bch { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/comtrend,ar-5315u.dts b/roms/u-boot/arch/mips/dts/comtrend,ar-5315u.dts new file mode 100644 index 000000000..28443b3b0 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/comtrend,ar-5315u.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +/dts-v1/; + +#include "brcm,bcm6318.dtsi" + +/ { + model = "Comtrend AR-5315u"; + compatible = "comtrend,ar5315-un", "brcm,bcm6318"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci { + status = "okay"; +}; + +&enet { + status = "okay"; + + port@0 { + compatible = "brcm,enetsw-port"; + reg = <0>; + label = "fe4"; + brcm,phy-id = <1>; + }; + + port@1 { + compatible = "brcm,enetsw-port"; + reg = <1>; + label = "fe3"; + brcm,phy-id = <2>; + }; + + port@2 { + compatible = "brcm,enetsw-port"; + reg = <2>; + label = "fe2"; + brcm,phy-id = <3>; + }; + + port@3 { + compatible = "brcm,enetsw-port"; + reg = <3>; + label = "fe1"; + brcm,phy-id = <4>; + }; +}; + +&leds { + status = "okay"; + + led@0 { + reg = <0>; + active-low; + label = "AR-5315u:green:wps"; + }; + + led@1 { + reg = <1>; + active-low; + label = "AR-5315u:green:power"; + }; + + led@2 { + reg = <2>; + active-low; + label = "AR-5315u:green:usb"; + }; + + led@8 { + reg = <8>; + active-low; + label = "AR-5315u:green:inet"; + }; + + led@9 { + reg = <9>; + active-low; + label = "AR-5315u:red:inet"; + }; + + led@10 { + reg = <10>; + active-low; + label = "AR-5315u:green:dsl"; + }; + + led@11 { + reg = <11>; + active-low; + label = "AR-5315u:red:power"; + }; +}; + +&ohci { + status = "okay"; +}; + +&spi { + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <62500000>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/comtrend,ar-5387un.dts b/roms/u-boot/arch/mips/dts/comtrend,ar-5387un.dts new file mode 100644 index 000000000..12ace6462 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/comtrend,ar-5387un.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +/dts-v1/; + +#include "brcm,bcm6328.dtsi" + +/ { + model = "Comtrend AR-5387un"; + compatible = "comtrend,ar5387-un", "brcm,bcm6328"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci { + status = "okay"; +}; + +&enet { + status = "okay"; + + port@0 { + compatible = "brcm,enetsw-port"; + reg = <0>; + label = "fe1"; + brcm,phy-id = <1>; + }; + + port@1 { + compatible = "brcm,enetsw-port"; + reg = <1>; + label = "fe2"; + brcm,phy-id = <2>; + }; + + port@2 { + compatible = "brcm,enetsw-port"; + reg = <2>; + label = "fe3"; + brcm,phy-id = <3>; + }; + + port@3 { + compatible = "brcm,enetsw-port"; + reg = <3>; + label = "fe4"; + brcm,phy-id = <4>; + }; +}; + +&leds { + status = "okay"; + + led@1 { + reg = <1>; + label = "AR-5387un:red:inet"; + }; + + led@4 { + reg = <4>; + label = "AR-5387un:red:power"; + }; + + led@7 { + reg = <7>; + label = "AR-5387un:green:inet"; + }; + + led@8 { + reg = <8>; + label = "AR-5387un:green:power"; + }; + + led@11 { + reg = <11>; + active-low; + label = "AR-5387un:green:dsl"; + }; +}; + +&ohci { + status = "okay"; +}; + +&spi { + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <33333334>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/comtrend,ct-5361.dts b/roms/u-boot/arch/mips/dts/comtrend,ct-5361.dts new file mode 100644 index 000000000..f6b8a94e2 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/comtrend,ct-5361.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +/dts-v1/; + +#include "brcm,bcm6348.dtsi" + +/ { + model = "Comtrend CT-5361"; + compatible = "comtrend,ct-5361", "brcm,bcm6348"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "CT-5361:green:power"; + gpios = <&gpio0 0 1>; + }; + + alarm_red { + label = "CT-5361:red:alarm"; + gpios = <&gpio0 2 1>; + }; + }; +}; + +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/comtrend,vr-3032u.dts b/roms/u-boot/arch/mips/dts/comtrend,vr-3032u.dts new file mode 100644 index 000000000..110119b50 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/comtrend,vr-3032u.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +/dts-v1/; + +#include "brcm,bcm63268.dtsi" + +/ { + model = "Comtrend VR-3032u"; + compatible = "comtrend,vr-3032u", "brcm,bcm63268"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci { + status = "okay"; +}; + +&enet { + status = "okay"; + + port@0 { + compatible = "brcm,enetsw-port"; + reg = <0>; + label = "fe2"; + brcm,phy-id = <1>; + }; + + port@1 { + compatible = "brcm,enetsw-port"; + reg = <1>; + label = "fe3"; + brcm,phy-id = <2>; + }; + + port@2 { + compatible = "brcm,enetsw-port"; + reg = <2>; + label = "fe4"; + brcm,phy-id = <3>; + }; + + port@3 { + compatible = "brcm,enetsw-port"; + reg = <3>; + label = "fe1"; + brcm,phy-id = <4>; + }; +}; + +&leds { + status = "okay"; + brcm,serial-leds; + brcm,serial-dat-low; + brcm,serial-shift-inv; + + led@2 { + reg = <2>; + active-low; + label = "VR-3032u:red:inet"; + }; + + led@3 { + reg = <3>; + active-low; + label = "VR-3032u:green:dsl"; + }; + + led@4 { + reg = <4>; + active-low; + label = "VR-3032u:green:usb"; + }; + + led@7 { + reg = <7>; + active-low; + label = "VR-3032u:green:wps"; + }; + + led@8 { + reg = <8>; + active-low; + label = "VR-3032u:green:inet"; + }; + + led@20 { + reg = <20>; + active-low; + label = "VR-3032u:green:power"; + }; +}; + +&nand { + status = "okay"; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <15>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + brcm,nand-oob-sector-size = <64>; + }; +}; + +&ohci { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/comtrend,wap-5813n.dts b/roms/u-boot/arch/mips/dts/comtrend,wap-5813n.dts new file mode 100644 index 000000000..7e835b28d --- /dev/null +++ b/roms/u-boot/arch/mips/dts/comtrend,wap-5813n.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +/dts-v1/; + +#include "brcm,bcm6368.dtsi" + +/ { + model = "Comtrend WAP-5813n"; + compatible = "comtrend,wap-5813n", "brcm,bcm6368"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "WAP-5813n:green:inet"; + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + }; + + power_green { + label = "WAP-5813n:green:power"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + wps_green { + label = "WAP-5813n:green:wps"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + power_red { + label = "WAP-5813n:red:power"; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; + + inet_red { + label = "WAP-5813n:red:inet"; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&enet { + status = "okay"; + + port@4 { + compatible = "brcm,enetsw-port"; + reg = <4>; + label = "rgmii"; + brcm,phy-id = <0xff>; + speed = <1000>; + full-duplex; + bypass-link; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/roms/u-boot/arch/mips/dts/gardena-smart-gateway-mt7688.dts new file mode 100644 index 000000000..b7b5a2405 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/gardena-smart-gateway-mt7688.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Stefan Roese <sr@denx.de> + */ + +/dts-v1/; + +#include "mt7628a.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc"; + model = "GARDENA smart Gateway (MT7688)"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + power_blue { + label = "smartgw:power:blue"; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + power_green { + label = "smartgw:power:green"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + power_red { + label = "smartgw:power:red"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_blue { + label = "smartgw:radio:blue"; + gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_green { + label = "smartgw:radio:green"; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_red { + label = "smartgw:radio:red"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_blue { + label = "smartgw:internet:blue"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_green { + label = "smartgw:internet:green"; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_red { + label = "smartgw:internet:red"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&pinctrl { + state_default: pin_state { + p0led { + groups = "p0led_a"; + function = "led"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_dual_pins>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + + spi-nand@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <40000000>; + reg = <1>; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_iot_mode>; + mediatek,poll-link-phy = <0>; +}; diff --git a/roms/u-boot/arch/mips/dts/huawei,hg556a.dts b/roms/u-boot/arch/mips/dts/huawei,hg556a.dts new file mode 100644 index 000000000..6a7fc1df4 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/huawei,hg556a.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +/dts-v1/; + +#include "brcm,bcm6358.dtsi" + +/ { + model = "Huawei EchoLife HG556a"; + compatible = "huawei,hg556a", "brcm,bcm6358"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + message_red { + label = "HG556a:red:message"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + hspa_red { + label = "HG556a:red:hspa"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + dsl_red { + label = "HG556a:red:dsl"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + power_red { + label = "HG556a:red:power"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + + all_red { + label = "HG556a:red:all"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + }; + + lan1_green { + label = "HG556a:green:lan1"; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + + lan1_red { + label = "HG556a:red:lan1"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + + lan2_green { + label = "HG556a:green:lan2"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + lan2_red { + label = "HG556a:red:lan2"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + lan3_green { + label = "HG556a:green:lan3"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + lan3_red { + label = "HG556a:red:lan3"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + + lan4_green { + label = "HG556a:green:lan4"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + + lan4_red { + label = "HG556a:red:lan4"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/img,boston.dts b/roms/u-boot/arch/mips/dts/img,boston.dts new file mode 100644 index 000000000..1d4eeda4e --- /dev/null +++ b/roms/u-boot/arch/mips/dts/img,boston.dts @@ -0,0 +1,222 @@ +/dts-v1/; + +#include <dt-bindings/clock/boston-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/mips-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "img,boston"; + + chosen { + stdout-path = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "img,mips"; + reg = <0>; + clocks = <&clk_boston BOSTON_CLK_CPU>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + gic: interrupt-controller { + compatible = "mti,gic"; + + interrupt-controller; + #interrupt-cells = <3>; + + timer { + compatible = "mti,gic-timer"; + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; + clocks = <&clk_boston BOSTON_CLK_CPU>; + }; + }; + + pci0: pci@10000000 { + status = "disabled"; + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + reg = <0x10000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; + + ranges = <0x02000000 0 0x40000000 + 0x40000000 0 0x40000000>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci0_intc 0>, + <0 0 0 2 &pci0_intc 1>, + <0 0 0 3 &pci0_intc 2>, + <0 0 0 4 &pci0_intc 3>; + + pci0_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pci1: pci@12000000 { + status = "disabled"; + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + reg = <0x12000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>; + + ranges = <0x02000000 0 0x20000000 + 0x20000000 0 0x20000000>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci1_intc 0>, + <0 0 0 2 &pci1_intc 1>, + <0 0 0 3 &pci1_intc 2>, + <0 0 0 4 &pci1_intc 3>; + + pci1_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pci2: pci@14000000 { + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + reg = <0x14000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; + + ranges = <0x02000000 0 0x16000000 + 0x16000000 0 0x100000>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci2_intc 0>, + <0 0 0 2 &pci2_intc 1>, + <0 0 0 3 &pci2_intc 2>, + <0 0 0 4 &pci2_intc 3>; + + pci2_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + pci2_root@0,0,0 { + compatible = "pci10ee,7021"; + reg = <0x00000000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + eg20t_bridge@1,0,0 { + compatible = "pci8086,8800"; + reg = <0x00010000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + eg20t_mac@2,0,1 { + compatible = "pci8086,8802"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>; + }; + + eg20t_gpio: eg20t_gpio@2,0,2 { + compatible = "pci8086,8803"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + }; + + eg20t_i2c@2,12,2 { + compatible = "pci8086,8817"; + reg = <0x00026200 0 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + rtc@0x68 { + compatible = "st,m41t81s"; + reg = <0x68>; + }; + }; + }; + }; + }; + + plat_regs: system-controller@17ffd000 { + compatible = "img,boston-platform-regs", "syscon"; + reg = <0x17ffd000 0x1000>; + u-boot,dm-pre-reloc; + }; + + clk_boston: clock { + compatible = "img,boston-clock"; + #clock-cells = <1>; + regmap = <&plat_regs>; + u-boot,dm-pre-reloc; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&plat_regs>; + offset = <0x10>; + mask = <0x10>; + }; + + uart0: uart@17ffe000 { + compatible = "ns16550a"; + reg = <0x17ffe000 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&clk_boston BOSTON_CLK_SYS>; + + u-boot,dm-pre-reloc; + }; + + lcd: lcd@17fff000 { + compatible = "img,boston-lcd"; + reg = <0x17fff000 0x8>; + }; + + flash@18000000 { + compatible = "cfi-flash"; + reg = <0x18000000 0x8000000>; + bank-width = <2>; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/include/dt-bindings b/roms/u-boot/arch/mips/dts/include/dt-bindings new file mode 120000 index 000000000..0cecb3d08 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings
\ No newline at end of file diff --git a/roms/u-boot/arch/mips/dts/jr2_pcb110.dts b/roms/u-boot/arch/mips/dts/jr2_pcb110.dts new file mode 100644 index 000000000..656222179 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/jr2_pcb110.dts @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,jr2.dtsi" +#include <dt-bindings/mscc/jr2_data.h> + +/ { + model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board"; + compatible = "mscc,jr2-pcb110", "mscc,jr2"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_green { + label = "pcb110:green:status"; + gpios = <&gpio 12 0>; + default-state = "on"; + }; + + status_red { + label = "pcb110:red:status"; + gpios = <&gpio 13 0>; + default-state = "off"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + }; +}; + +&gpio { + /* SPIO only use DO, CLK, no inputs */ + sgpio1_pins: sgpio1-pins { + pins = "GPIO_4", "GPIO_5"; + function = "sg1"; + }; +}; + +&sgpio { + status = "okay"; + sgpio-ports = <0x00ffffff>; +}; + +&sgpio1 { + status = "okay"; + sgpio-ports = <0x00ff0000>; +}; + +&sgpio2 { + status = "okay"; + sgpio-ports = <0x3f00ffff>; + gpio-ranges = <&sgpio2 0 0 96>; +}; + +&mdio1 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + }; + phy6: ethernet-phy@6 { + reg = <6>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + }; +}; + +&switch { + ethernet-ports { + + port0: port@0 { + reg = <0>; + phy-handle = <&phy0>; + phys = <&serdes_hsio 0 SERDES1G(1) PHY_MODE_SGMII>; + }; + port1: port@1 { + reg = <1>; + phy-handle = <&phy1>; + phys = <&serdes_hsio 1 SERDES1G(2) PHY_MODE_SGMII>; + }; + port2: port@2 { + reg = <2>; + phy-handle = <&phy2>; + phys = <&serdes_hsio 2 SERDES1G(3) PHY_MODE_SGMII>; + }; + port3: port@3 { + reg = <3>; + phy-handle = <&phy3>; + phys = <&serdes_hsio 3 SERDES1G(4) PHY_MODE_SGMII>; + }; + port4: port@4 { + reg = <4>; + phy-handle = <&phy4>; + phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>; + }; + port5: port@5 { + reg = <5>; + phy-handle = <&phy5>; + phys = <&serdes_hsio 5 SERDES1G(6) PHY_MODE_SGMII>; + }; + port6: port@6 { + reg = <6>; + phy-handle = <&phy6>; + phys = <&serdes_hsio 6 SERDES1G(7) PHY_MODE_SGMII>; + }; + port7: port@7 { + reg = <7>; + phy-handle = <&phy7>; + phys = <&serdes_hsio 7 SERDES1G(8) PHY_MODE_SGMII>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/jr2_pcb111.dts b/roms/u-boot/arch/mips/dts/jr2_pcb111.dts new file mode 100644 index 000000000..74305a8f3 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/jr2_pcb111.dts @@ -0,0 +1,474 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,jr2.dtsi" +#include <dt-bindings/mscc/jr2_data.h> + +/ { + model = "Jaguar2 Cu48 PCB111 Reference Board"; + compatible = "mscc,jr2-pcb111", "mscc,jr2"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_green { + label = "pcb111:green:status"; + gpios = <&gpio 12 0>; + default-state = "on"; + }; + + status_red { + label = "pcb111:red:status"; + gpios = <&gpio 13 0>; + default-state = "off"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + }; +}; + +&gpio { + /* SPIO only use DO, CLK, no inputs */ + sgpio1_pins: sgpio1-pins { + pins = "GPIO_4", "GPIO_5"; + function = "sg1"; + }; +}; + +&sgpio { + status = "okay"; + sgpio-ports = <0xffffffff>; +}; + +&sgpio1 { + status = "okay"; + sgpio-ports = <0x001effff>; +}; + +&sgpio2 { + status = "okay"; + sgpio-ports = <0xff000000>; + gpio-ranges = <&sgpio2 0 0 96>; +}; + +&mdio1 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + }; + phy6: ethernet-phy@6 { + reg = <6>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + }; + phy10: ethernet-phy@10 { + reg = <10>; + }; + phy11: ethernet-phy@11 { + reg = <11>; + }; + phy12: ethernet-phy@12 { + reg = <12>; + }; + phy13: ethernet-phy@13 { + reg = <13>; + }; + phy14: ethernet-phy@14 { + reg = <14>; + }; + phy15: ethernet-phy@15 { + reg = <15>; + }; + phy16: ethernet-phy@16 { + reg = <16>; + }; + phy17: ethernet-phy@17 { + reg = <17>; + }; + phy18: ethernet-phy@18 { + reg = <18>; + }; + phy19: ethernet-phy@19 { + reg = <19>; + }; + phy20: ethernet-phy@20 { + reg = <20>; + }; + phy21: ethernet-phy@21 { + reg = <21>; + }; + phy22: ethernet-phy@22 { + reg = <22>; + }; + phy23: ethernet-phy@23 { + reg = <23>; + }; +}; + +&mdio2 { + status = "okay"; + + phy24: ethernet-phy@24 { + reg = <0>; + }; + phy25: ethernet-phy@25 { + reg = <1>; + }; + phy26: ethernet-phy@26 { + reg = <2>; + }; + phy27: ethernet-phy@27 { + reg = <3>; + }; + phy28: ethernet-phy@28 { + reg = <4>; + }; + phy29: ethernet-phy@29 { + reg = <5>; + }; + phy30: ethernet-phy@30 { + reg = <6>; + }; + phy31: ethernet-phy@31 { + reg = <7>; + }; + phy32: ethernet-phy@32 { + reg = <8>; + }; + phy33: ethernet-phy@33 { + reg = <9>; + }; + phy34: ethernet-phy@34 { + reg = <10>; + }; + phy35: ethernet-phy@35 { + reg = <11>; + }; + phy36: ethernet-phy@36 { + reg = <12>; + }; + phy37: ethernet-phy@37 { + reg = <13>; + }; + phy38: ethernet-phy@38 { + reg = <14>; + }; + phy39: ethernet-phy@39 { + reg = <15>; + }; + phy40: ethernet-phy@40 { + reg = <16>; + }; + phy41: ethernet-phy@41 { + reg = <17>; + }; + phy42: ethernet-phy@42 { + reg = <18>; + }; + phy43: ethernet-phy@43 { + reg = <19>; + }; + phy44: ethernet-phy@44 { + reg = <20>; + }; + phy45: ethernet-phy@45 { + reg = <21>; + }; + phy46: ethernet-phy@46 { + reg = <22>; + }; + phy47: ethernet-phy@47 { + reg = <23>; + }; +}; + +&switch { + ethernet-ports { + port0: port@0 { + reg = <0>; + phy-handle = <&phy0>; + phys = <&serdes_hsio 0 SERDES6G(4) PHY_MODE_QSGMII>; + }; + port1: port@1 { + reg = <1>; + phy-handle = <&phy1>; + phys = <&serdes_hsio 1 0xff PHY_MODE_QSGMII>; + }; + port2: port@2 { + reg = <2>; + phy-handle = <&phy2>; + phys = <&serdes_hsio 2 0xff PHY_MODE_QSGMII>; + }; + port3: port@3 { + reg = <3>; + phy-handle = <&phy3>; + phys = <&serdes_hsio 3 0xff PHY_MODE_QSGMII>; + }; + port4: port@4 { + reg = <4>; + phy-handle = <&phy4>; + phys = <&serdes_hsio 4 SERDES6G(5) PHY_MODE_QSGMII>; + }; + port5: port@5 { + reg = <5>; + phy-handle = <&phy5>; + phys = <&serdes_hsio 5 0xff PHY_MODE_QSGMII>; + }; + port6: port@6 { + reg = <6>; + phy-handle = <&phy6>; + phys = <&serdes_hsio 6 0xff PHY_MODE_QSGMII>; + }; + port7: port@7 { + reg = <7>; + phy-handle = <&phy7>; + phys = <&serdes_hsio 7 0xff PHY_MODE_QSGMII>; + }; + port8: port@8 { + reg = <8>; + phy-handle = <&phy8>; + phys = <&serdes_hsio 8 SERDES6G(6) PHY_MODE_QSGMII>; + }; + port9: port@9 { + reg = <9>; + phy-handle = <&phy9>; + phys = <&serdes_hsio 9 0xff PHY_MODE_QSGMII>; + }; + port10: port@10 { + reg = <10>; + phy-handle = <&phy10>; + phys = <&serdes_hsio 10 0xff PHY_MODE_QSGMII>; + }; + port11: port@11 { + reg = <11>; + phy-handle = <&phy11>; + phys = <&serdes_hsio 11 0xff PHY_MODE_QSGMII>; + }; + port12: port@12 { + reg = <12>; + phy-handle = <&phy12>; + phys = <&serdes_hsio 12 SERDES6G(7) PHY_MODE_QSGMII>; + }; + port13: port@13 { + reg = <13>; + phy-handle = <&phy13>; + phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>; + }; + port14: port@14 { + reg = <14>; + phy-handle = <&phy14>; + phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>; + }; + port15: port@15 { + reg = <15>; + phy-handle = <&phy15>; + phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>; + }; + port16: port@16 { + reg = <16>; + phy-handle = <&phy16>; + phys = <&serdes_hsio 16 SERDES6G(8) PHY_MODE_QSGMII>; + }; + port17: port@17 { + reg = <17>; + phy-handle = <&phy17>; + phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>; + }; + port18: port@18 { + reg = <18>; + phy-handle = <&phy18>; + phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>; + }; + port19: port@19 { + reg = <19>; + phy-handle = <&phy19>; + phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>; + }; + port20: port@20 { + reg = <20>; + phy-handle = <&phy20>; + phys = <&serdes_hsio 20 SERDES6G(9) PHY_MODE_QSGMII>; + }; + port21: port@21 { + reg = <21>; + phy-handle = <&phy21>; + phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>; + }; + port22: port@22 { + reg = <22>; + phy-handle = <&phy22>; + phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>; + }; + port23: port@23 { + reg = <23>; + phy-handle = <&phy23>; + phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>; + }; + port24: port@24 { + reg = <24>; + phy-handle = <&phy24>; + phys = <&serdes_hsio 24 SERDES6G(10) PHY_MODE_QSGMII>; + }; + port25: port@25 { + reg = <25>; + phy-handle = <&phy25>; + phys = <&serdes_hsio 25 0xff PHY_MODE_QSGMII>; + }; + port26: port@26 { + reg = <26>; + phy-handle = <&phy26>; + phys = <&serdes_hsio 26 0xff PHY_MODE_QSGMII>; + }; + port27: port@27 { + reg = <27>; + phy-handle = <&phy27>; + phys = <&serdes_hsio 27 0xff PHY_MODE_QSGMII>; + }; + port28: port@28 { + reg = <28>; + phy-handle = <&phy28>; + phys = <&serdes_hsio 28 SERDES6G(11) PHY_MODE_QSGMII>; + }; + port29: port@29 { + reg = <29>; + phy-handle = <&phy29>; + phys = <&serdes_hsio 29 0xff PHY_MODE_QSGMII>; + }; + port30: port@30 { + reg = <30>; + phy-handle = <&phy30>; + phys = <&serdes_hsio 30 0xff PHY_MODE_QSGMII>; + }; + port31: port@31 { + reg = <31>; + phy-handle = <&phy31>; + phys = <&serdes_hsio 31 0xff PHY_MODE_QSGMII>; + }; + port32: port@32 { + reg = <32>; + phy-handle = <&phy32>; + phys = <&serdes_hsio 32 SERDES6G(12) PHY_MODE_QSGMII>; + }; + port33: port@33 { + reg = <33>; + phy-handle = <&phy33>; + phys = <&serdes_hsio 33 0xff PHY_MODE_QSGMII>; + }; + port34: port@34 { + reg = <34>; + phy-handle = <&phy34>; + phys = <&serdes_hsio 34 0xff PHY_MODE_QSGMII>; + }; + port35: port@35 { + reg = <35>; + phy-handle = <&phy35>; + phys = <&serdes_hsio 35 0xff PHY_MODE_QSGMII>; + }; + port36: port@36 { + reg = <36>; + phy-handle = <&phy36>; + phys = <&serdes_hsio 36 SERDES6G(13) PHY_MODE_QSGMII>; + }; + port37: port@37 { + reg = <37>; + phy-handle = <&phy37>; + phys = <&serdes_hsio 37 0xff PHY_MODE_QSGMII>; + }; + port38: port@38 { + reg = <38>; + phy-handle = <&phy38>; + phys = <&serdes_hsio 38 0xff PHY_MODE_QSGMII>; + }; + port39: port@39 { + reg = <39>; + phy-handle = <&phy39>; + phys = <&serdes_hsio 39 0xff PHY_MODE_QSGMII>; + }; + port40: port@40 { + reg = <40>; + phy-handle = <&phy40>; + phys = <&serdes_hsio 40 SERDES6G(14) PHY_MODE_QSGMII>; + }; + port41: port@41 { + reg = <41>; + phy-handle = <&phy41>; + phys = <&serdes_hsio 41 0xff PHY_MODE_QSGMII>; + }; + port42: port@42 { + reg = <42>; + phy-handle = <&phy42>; + phys = <&serdes_hsio 42 0xff PHY_MODE_QSGMII>; + }; + port43: port@43 { + reg = <43>; + phy-handle = <&phy43>; + phys = <&serdes_hsio 43 0xff PHY_MODE_QSGMII>; + }; + port44: port@44 { + reg = <44>; + phy-handle = <&phy44>; + phys = <&serdes_hsio 44 SERDES6G(15) PHY_MODE_QSGMII>; + }; + port45: port@45 { + reg = <45>; + phy-handle = <&phy45>; + phys = <&serdes_hsio 45 0xff PHY_MODE_QSGMII>; + }; + port46: port@46 { + reg = <46>; + phy-handle = <&phy46>; + phys = <&serdes_hsio 46 0xff PHY_MODE_QSGMII>; + }; + port47: port@47 { + reg = <47>; + phy-handle = <&phy47>; + phys = <&serdes_hsio 47 0xff PHY_MODE_QSGMII>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/jz4780.dtsi b/roms/u-boot/arch/mips/dts/jz4780.dtsi new file mode 100644 index 000000000..f62a7a95f --- /dev/null +++ b/roms/u-boot/arch/mips/dts/jz4780.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <dt-bindings/clock/jz4780-cgu.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ingenic,jz4780"; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4780-intc"; + reg = <0x10001000 0x50>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + ext: ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + rtc: rtc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + cgu: jz4780-cgu@10000000 { + compatible = "ingenic,jz4780-cgu"; + reg = <0x10000000 0x100>; + + clocks = <&ext>, <&rtc>; + clock-names = "ext", "rtc"; + + #clock-cells = <1>; + }; + + mmc0: mmc@13450000 { + compatible = "ingenic,jz4780-mmc"; + reg = <0x13450000 0x1000>; + + status = "disabled"; + + clocks = <&cgu JZ4780_CLK_MSC0>; + clock-names = "mmc"; + }; + + mmc1: mmc@13460000 { + compatible = "ingenic,jz4780-mmc"; + reg = <0x13460000 0x1000>; + + clocks = <&cgu JZ4780_CLK_MSC1>; + clock-names = "mmc"; + + status = "disabled"; + }; + + uart0: serial@10030000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10030000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <51>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART0>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart1: serial@10031000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10031000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <50>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART1>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart2: serial@10032000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10032000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <49>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART2>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart3: serial@10033000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10033000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <48>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART3>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart4: serial@10034000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10034000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <34>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART4>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + nemc: nemc@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000 + 2 0 0x1a000000 0x1000000 + 3 0 0x19000000 0x1000000 + 4 0 0x18000000 0x1000000 + 5 0 0x17000000 0x1000000 + 6 0 0x16000000 0x1000000>; + + clocks = <&cgu JZ4780_CLK_NEMC>; + + status = "disabled"; + }; + + bch: bch@134d0000 { + compatible = "ingenic,jz4780-bch"; + reg = <0x134d0000 0x10000>; + + clocks = <&cgu JZ4780_CLK_BCH>; + + status = "disabled"; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/linkit-smart-7688.dts b/roms/u-boot/arch/mips/dts/linkit-smart-7688.dts new file mode 100644 index 000000000..f154aae19 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/linkit-smart-7688.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Stefan Roese <sr@denx.de> + */ + +/dts-v1/; + +#include "mt7628a.dtsi" + +/ { + compatible = "seeed,linkit-smart-7688", "ralink,mt7628a-soc"; + model = "LinkIt-Smart-7688"; + + aliases { + serial0 = &uart2; + spi0 = &spi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + chosen { + stdout-path = &uart2; + }; +}; + +&pinctrl { + state_default: pin_state { + p0led { + groups = "p0led_a"; + function = "led"; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_iot_mode>; + mediatek,poll-link-phy = <0>; +}; diff --git a/roms/u-boot/arch/mips/dts/luton_pcb090.dts b/roms/u-boot/arch/mips/dts/luton_pcb090.dts new file mode 100644 index 000000000..ea3e3b7fb --- /dev/null +++ b/roms/u-boot/arch/mips/dts/luton_pcb090.dts @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,luton.dtsi" +#include <dt-bindings/mscc/luton_data.h> + +/ { + model = "Luton26 PCB090 Reference Board"; + compatible = "mscc,luton-pcb090", "mscc,luton"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_green { + label = "pcb090:green:status"; + gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */ + default-state = "on"; + }; + + status_red { + label = "pcb090:red:status"; + gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */ + default-state = "off"; + }; + }; +}; + +&sgpio { + status = "okay"; + gpio-ranges = <&sgpio 0 0 96>; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + spi-cs-high; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + }; + phy6: ethernet-phy@6 { + reg = <6>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + }; + phy10: ethernet-phy@10 { + reg = <10>; + }; + phy11: ethernet-phy@11 { + reg = <11>; + }; +}; + +&mdio1 { + status = "okay"; + + phy12: ethernet-phy@12 { + reg = <0>; + }; + phy13: ethernet-phy@13 { + reg = <1>; + }; + phy14: ethernet-phy@14 { + reg = <2>; + }; + phy15: ethernet-phy@15 { + reg = <3>; + }; + phy16: ethernet-phy@16 { + reg = <4>; + }; + phy17: ethernet-phy@17 { + reg = <5>; + }; + phy18: ethernet-phy@18 { + reg = <6>; + }; + phy19: ethernet-phy@19 { + reg = <7>; + }; + phy20: ethernet-phy@20 { + reg = <8>; + }; + phy21: ethernet-phy@21 { + reg = <9>; + }; + phy22: ethernet-phy@22 { + reg = <10>; + }; + phy23: ethernet-phy@23 { + reg = <11>; + }; +}; + +&switch { + ethernet-ports { + port0: port@0 { + reg = <0>; + phy-handle = <&phy0>; + }; + port1: port@1 { + reg = <1>; + phy-handle = <&phy1>; + }; + port2: port@2 { + reg = <2>; + phy-handle = <&phy2>; + }; + port3: port@3 { + reg = <3>; + phy-handle = <&phy3>; + }; + port4: port@4 { + reg = <4>; + phy-handle = <&phy4>; + }; + port5: port@5 { + reg = <5>; + phy-handle = <&phy5>; + }; + port6: port@6 { + reg = <6>; + phy-handle = <&phy6>; + }; + port7: port@7 { + reg = <7>; + phy-handle = <&phy7>; + }; + port8: port@8 { + reg = <8>; + phy-handle = <&phy8>; + }; + port9: port@9 { + reg = <9>; + phy-handle = <&phy9>; + }; + port10: port@10 { + reg = <10>; + phy-handle = <&phy10>; + }; + port11: port@11 { + reg = <11>; + phy-handle = <&phy11>; + }; + port12: port@12 { + reg = <12>; + phy-handle = <&phy12>; + phys = <&serdes_hsio 12 SERDES6G(1) PHY_MODE_QSGMII>; + }; + port13: port@13 { + reg = <13>; + phy-handle = <&phy13>; + phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>; + }; + port14: port@14 { + reg = <14>; + phy-handle = <&phy14>; + phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>; + }; + port15: port@15 { + reg = <15>; + phy-handle = <&phy15>; + phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>; + }; + port16: port@16 { + reg = <16>; + phy-handle = <&phy16>; + phys = <&serdes_hsio 16 SERDES6G(2) PHY_MODE_QSGMII>; + }; + port17: port@17 { + reg = <17>; + phy-handle = <&phy17>; + phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>; + }; + port18: port@18 { + reg = <18>; + phy-handle = <&phy18>; + phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>; + }; + port19: port@19 { + reg = <19>; + phy-handle = <&phy19>; + phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>; + }; + port20: port@20 { + reg = <20>; + phy-handle = <&phy20>; + phys = <&serdes_hsio 20 SERDES6G(3) PHY_MODE_QSGMII>; + }; + port21: port@21 { + reg = <21>; + phy-handle = <&phy21>; + phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>; + }; + port22: port@22 { + reg = <22>; + phy-handle = <&phy22>; + phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>; + }; + port23: port@23 { + reg = <23>; + phy-handle = <&phy23>; + phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/luton_pcb091.dts b/roms/u-boot/arch/mips/dts/luton_pcb091.dts new file mode 100644 index 000000000..cb78c5751 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/luton_pcb091.dts @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,luton.dtsi" + +/ { + model = "Luton10 PCB091 Reference Board"; + compatible = "mscc,luton-pcb091", "mscc,luton"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + top_dimmer { + label = "pcb091:top:dimmer"; + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + status_green { + label = "pcb091:green:status"; + gpios = <&sgpio 26 GPIO_ACTIVE_HIGH>; /* p26.0 */ + default-state = "on"; + }; + + status_red { + label = "pcb091:red:status"; + gpios = <&sgpio 58 GPIO_ACTIVE_HIGH>; /* p26.1 */ + default-state = "off"; + }; + }; +}; + +&sgpio { + status = "okay"; + mscc,sgpio-ports = <0xFFF000FF>; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + spi-cs-high; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + }; + phy6: ethernet-phy@6 { + reg = <6>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + }; + phy10: ethernet-phy@10 { + reg = <10>; + }; + phy11: ethernet-phy@11 { + reg = <11>; + }; +}; + +&switch { + ethernet-ports { + port0: port@0 { + reg = <0>; + phy-handle = <&phy0>; + }; + port1: port@1 { + reg = <1>; + phy-handle = <&phy1>; + }; + port2: port@2 { + reg = <2>; + phy-handle = <&phy2>; + }; + port3: port@3 { + reg = <3>; + phy-handle = <&phy3>; + }; + port4: port@4 { + reg = <4>; + phy-handle = <&phy4>; + }; + port5: port@5 { + reg = <5>; + phy-handle = <&phy5>; + }; + port6: port@6 { + reg = <6>; + phy-handle = <&phy6>; + }; + port7: port@7 { + reg = <7>; + phy-handle = <&phy7>; + }; + port8: port@8 { + reg = <8>; + phy-handle = <&phy8>; + }; + port9: port@9 { + reg = <9>; + phy-handle = <&phy9>; + }; + port10: port@10 { + reg = <10>; + phy-handle = <&phy10>; + }; + port11: port@11 { + reg = <11>; + phy-handle = <&phy11>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts b/roms/u-boot/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts new file mode 100644 index 000000000..8bc3b1673 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "mt7620.dtsi" + +/ { + compatible = "mediatek,mt7620-mt7530-rfb", "mediatek,mt7620-soc"; + model = "MediaTek MT7620-MT7530 RFB (MTKC712)"; + + aliases { + serial0 = &uartlite; + spi0 = &spi0; + }; + + chosen { + stdout-path = &uartlite; + }; +}; + +&uartlite { + status = "okay"; +}; + +&pinctrl { + state_default: pin_state { + pleds { + groups = "ephy led", "wled"; + function = "led"; + }; + + gpios { + groups = "pa", "uartf"; + function = "gpio"; + }; + }; + + gsw_pins: gsw_pins { + mdio { + groups = "mdio"; + function = "mdio"; + }; + + rgmii1 { + groups = "rgmii1"; + function = "rgmii1"; + }; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +&gpio0 { + pa0_pull_low { + gpio-hog; + output-low; + gpios = <20 GPIO_ACTIVE_HIGH>; + }; + + pa1_pull_low { + gpio-hog; + output-low; + gpios = <21 GPIO_ACTIVE_HIGH>; + }; +}; + +ð { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&gsw_pins>; + + port5 { + phy-mode = "rgmii"; + phy-addr = <5>; + fixed-link { + full-duplex; + speed = <1000>; + mediatek,mt7530; + mediatek,mt7530-reset = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mediatek,mt7620-rfb.dts b/roms/u-boot/arch/mips/dts/mediatek,mt7620-rfb.dts new file mode 100644 index 000000000..616903e55 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mediatek,mt7620-rfb.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "mt7620.dtsi" + +/ { + compatible = "mediatek,mt7620-rfb", "mediatek,mt7620-soc"; + model = "MediaTek MT7620 RFB (WS2120)"; + + aliases { + serial0 = &uartlite; + spi0 = &spi0; + }; + + chosen { + stdout-path = &uartlite; + }; +}; + +&uartlite { + status = "okay"; +}; + +&pinctrl { + state_default: pin_state { + pleds { + groups = "ephy led", "wled"; + function = "led"; + }; + + gpios { + groups = "uartf"; + function = "gpio"; + }; + }; + + gsw_pins: gsw_pins { + mdio { + groups = "mdio"; + function = "mdio"; + }; + + rgmii1 { + groups = "rgmii1"; + function = "rgmii1"; + }; + + rgmii2 { + groups = "rgmii2"; + function = "rgmii2"; + }; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +ð { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&gsw_pins>; + + port4 { + phy-mode = "rgmii"; + phy-addr = <4>; + }; + + port5 { + phy-mode = "rgmii"; + phy-addr = <5>; + }; +}; + +&mmc { + bus-width = <4>; + cap-sd-highspeed; + + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/mediatek,mt7628-rfb.dts b/roms/u-boot/arch/mips/dts/mediatek,mt7628-rfb.dts new file mode 100644 index 000000000..6ff36daa6 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mediatek,mt7628-rfb.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +/dts-v1/; + +#include "mt7628a.dtsi" + +/ { + compatible = "mediatek,mt7628-rfb", "ralink,mt7628a-soc"; + model = "MediaTek MT7628 RFB"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&pinctrl { + state_default: pin_state { + pleds { + groups = "p0led", "p1led", "p2led", "p3led", "p4led"; + function = "led"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + num-cs = <2>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +ð { + mediatek,wan-port = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&ephy_router_mode>; +}; + +&mmc { + bus-width = <4>; + cap-sd-highspeed; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_router_mode>; + + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/microAptiv.dtsi b/roms/u-boot/arch/mips/dts/microAptiv.dtsi new file mode 100644 index 000000000..81d518e75 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/microAptiv.dtsi @@ -0,0 +1,21 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "img,xilfpga"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "mips,m14Kc"; + clocks = <&ext>; + reg = <0>; + }; + }; + + ext: ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mrvl,cn73xx.dtsi b/roms/u-boot/arch/mips/dts/mrvl,cn73xx.dtsi new file mode 100644 index 000000000..2a17f7a6a --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mrvl,cn73xx.dtsi @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Marvell / Cavium Inc. CN73xx + */ + +/dts-v1/; + +#include <dt-bindings/clock/octeon-clock.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + soc0: soc@0 { + interrupt-parent = <&ciu3>; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu3: interrupt-controller@1010000000000 { + compatible = "cavium,octeon-7890-ciu3"; + interrupt-controller; + /* + * Interrupts are specified by two parts: + * 1) Source number (20 significant bits) + * 2) Trigger type: (4 == level, 1 == edge) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10100 0x00000000 0x0 0xb0000000>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus","simple-bus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + }; + + clk: clock { + compatible = "mrvl,octeon-clk"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-7890-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + nr-gpios = <32>; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pins connect to 16 consecutive CUI bits */ + interrupts = <0x03000 4>, <0x03001 4>, + <0x03002 4>, <0x03003 4>, + <0x03004 4>, <0x03005 4>, + <0x03006 4>, <0x03007 4>, + <0x03008 4>, <0x03009 4>, + <0x0300a 4>, <0x0300b 4>, + <0x0300c 4>, <0x0300d 4>, + <0x0300e 4>, <0x0300f 4>; + }; + + l2c: l2c@1180080000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7xxx-l2c"; + reg = <0x11800 0x80000000 0x0 0x01000000>; + u-boot,dm-pre-reloc; + }; + + lmc: lmc@1180088000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7xxx-ddr4"; + reg = <0x11800 0x88000000 0x0 0x02000000>; // 2 IFs + u-boot,dm-pre-reloc; + l2c-handle = <&l2c>; + }; + + reset: reset@1180006001600 { + compatible = "mrvl,cn7xxx-rst"; + reg = <0x11800 0x06001600 0x0 0x200>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clocks = <&clk OCTEON_CLK_IO>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0x08000 4>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clocks = <&clk OCTEON_CLK_IO>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0x08040 4>; + }; + + i2c0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7890-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + /* INT_ST, INT_TS, INT_CORE */ + interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>; + clock-frequency = <100000>; + clocks = <&clk OCTEON_CLK_IO>; + }; + + i2c1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7890-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + /* INT_ST, INT_TS, INT_CORE */ + interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>; + clock-frequency = <100000>; + clocks = <&clk OCTEON_CLK_IO>; + }; + + mmc: mmc@1180000002000 { + compatible = "cavium,octeon-7890-mmc", + "cavium,octeon-7360-mmc"; + reg = <0x11800 0x00000000 0x0 0x2100>; + #address-cells = <1>; + #size-cells = <0>; + /* EMM_INT_BUF_DONE, + EMM_INT_CMD_DONE, + EMM_INT_DMA_DONE, + EMM_INT_CMD_ERR, + EMM_INT_DMA_ERR, + EMM_INT_SWITCH_DONE, + EMM_INT_SWITCH_ERR, + EMM_DMA_DONE, + EMM_DMA_FIFO*/ + interrupts = <0x09040 1>, + <0x09041 1>, + <0x09042 1>, + <0x09043 1>, + <0x09044 1>, + <0x09045 1>, + <0x09046 1>, + <0x09000 1>, + <0x09001 1>; + clocks = <&clk OCTEON_CLK_IO>; + }; + + spi: spi@1070000001000 { + compatible = "cavium,octeon-3010-spi"; + reg = <0x10700 0x00001000 0x0 0x100>; + interrupts = <0x05001 1>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <25000000>; + clocks = <&clk OCTEON_CLK_IO>; + }; + + /* USB 0 */ + usb0: uctl@1180068000000 { + compatible = "cavium,octeon-7130-usb-uctl"; + reg = <0x11800 0x68000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* Only 100MHz allowed */ + refclk-frequency = <100000000>; + /* Only "dlmc_ref_clk0" is supported for 73xx */ + refclk-type-ss = "dlmc_ref_clk0"; + /* Only "dlmc_ref_clk0" is supported for 73xx */ + refclk-type-hs = "dlmc_ref_clk0"; + + /* + * Power is specified by three parts: + * 1) GPIO handle (must be &gpio) + * 2) GPIO pin number + * 3) Active high (0) or active low (1) + */ + xhci@1680000000000 { + compatible = "cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3"; + reg = <0x16800 0x00000000 0x10 0x0>; + interrupts = <0x68080 4>; /* UAHC_IMAN, level */ + maximum-speed = "super-speed"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + }; + }; + + /* USB 1 */ + usb1: uctl@1180069000000 { + compatible = "cavium,octeon-7130-usb-uctl"; + reg = <0x11800 0x69000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 50MHz, 100MHz and 125MHz allowed */ + refclk-frequency = <100000000>; + /* Either "dlmc_ref_clk0" or "dlmc_ref_clk0" */ + refclk-type-ss = "dlmc_ref_clk0"; + /* Either "dlmc_ref_clk0" "dlmc_ref_clk1" or "pll_ref_clk" */ + refclk-type-hs = "dlmc_ref_clk0"; + + /* + * Power is specified by three parts: + * 1) GPIO handle (must be &gpio) + * 2) GPIO pin number + * 3) Active high (0) or active low (1) + */ + xhci@1690000000000 { + compatible = "cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3"; + reg = <0x16900 0x00000000 0x10 0x0>; + interrupts = <0x69080 4>; /* UAHC_IMAN, level */ + dr_mode = "host"; + }; + }; + + /* PCIe 0 */ + pcie0: pcie@1180069000000 { + compatible = "marvell,pcie-host-octeon"; + reg = <0 0xf2600000 0 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + + bus-range = <0 0xff>; + marvell,pcie-port = <0>; + ranges = <0x81000000 0x00000000 0xd0000000 0x00011a00 0xd0000000 0x00000000 0x01000000 /* IO */ + 0x02000000 0x00000000 0xe0000000 0x00011b00 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ + 0x43000000 0x00011c00 0x00000000 0x00011c00 0x00000000 0x00000010 0x00000000>;/* prefetchable memory */ + }; + + uctl@118006c000000 { + compatible = "cavium,octeon-7130-sata-uctl", "simple-bus"; + reg = <0x11800 0x6c000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + portmap = <0x3>; + staggered-spinup; + cavium,qlm-trim = "4,sata"; + + sata: sata@16c0000000000 { + compatible = "cavium,octeon-7130-ahci"; + reg = <0x16c00 0x00000000 0x0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = <0x6c010 4>; + }; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mrvl,octeon-ebb7304.dts b/roms/u-boot/arch/mips/dts/mrvl,octeon-ebb7304.dts new file mode 100644 index 000000000..fda559d86 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mrvl,octeon-ebb7304.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Marvell / Cavium Inc. EVB CN7300 + */ + +/dts-v1/; + +#include "mrvl,cn73xx.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "cavium,ebb7304"; + compatible = "cavium,ebb7304"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; + spi0 = &spi; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + /* Power on GPIO 8, active high */ + reg_mmc_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "mmc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&bootbus { + /* + * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000) + * as the initial size is too small for the 8MiB flash device + */ + ranges = <0 0 0 0x1f400000 0xc00000>, + <1 0 0x10000 0x10000000 0>, + <2 0 0x10000 0x20000000 0>, + <3 0 0x10000 0x30000000 0>, + <4 0 0 0x1d020000 0x10000>, + <5 0 0x10000 0x50000000 0>, + <6 0 0x10000 0x60000000 0>, + <7 0 0x10000 0x70000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <10>; + cavium,t-ce = <50>; + cavium,t-oe = <50>; + cavium,t-we = <35>; + cavium,t-rd-hld = <25>; + cavium,t-wr-hld = <35>; + cavium,t-pause = <0>; + cavium,t-wait = <50>; + cavium,t-page = <30>; + cavium,t-rd-dly = <0>; + cavium,page-mode = <1>; + cavium,pages = <8>; + cavium,bus-width = <8>; + }; + + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <10>; + cavium,t-ce = <10>; + cavium,t-oe = <160>; + cavium,t-we = <100>; + cavium,t-rd-hld = <10>; + cavium,t-wr-hld = <0>; + cavium,t-pause = <50>; + cavium,t-wait = <50>; + cavium,t-page = <10>; + cavium,t-rd-dly = <10>; + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "bootloader"; + reg = <0 0x340000>; + read-only; + }; + partition@300000 { + label = "storage"; + reg = <0x340000 0x4be000>; + }; + partition@7fe000 { + label = "environment"; + reg = <0x7fe000 0x2000>; + read-only; + }; + }; +}; + +&i2c0 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + + tlv-eeprom@56 { + compatible = "atmel,24c256", "microchip,24lc256"; + reg = <0x56>; + pagesize = <64>; + }; +}; + +&i2c1 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&spi { + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <2000000>; + reg = <0>; + }; +}; + +/* USB 0 */ +&usb0 { + status = "okay"; + /* + * Power is specified by three parts: + * 1) GPIO handle (must be &gpio) + * 2) GPIO pin number + * 3) Active high (0) or active low (1) + */ + power = <&gpio 20 0>; +}; + +/* USB 1 */ +&usb1 { + status = "okay"; + /* + * Power is specified by three parts: + * 1) GPIO handle (must be &gpio) + * 2) GPIO pin number + * 3) Active high (0) or active low (1) + */ + power = <&gpio 21 0>; +}; + +&mmc { + status = "okay"; + + /* The board has two MMC slots + * If both are occupied, the speed must be reduced, + * as extra data-line load increases slew time, + * and dat-skew adjustment does not help significantly. + */ + mmc0: mmc-slot@0 { + compatible = "cavium,octeon-6130-mmc-slot", "mmc-slot"; + reg = <0>; + vqmmc-supply = <®_mmc_3v3>; + voltage-ranges = <3300 3300>; + //spi-max-frequency = <52000000>; // just one + spi-max-frequency = <37000000>; // both slots + /* bus width can be 1, 4 or 8 */ + bus-width = <8>; /* new std property */ + cavium,bus-max-width = <8>; /* custom property */ + wp-gpios = <&gpio 22 0>; /* active high */ + cd-gpios = <&gpio 23 1>; /* active low */ + }; + + mmc1: mmc-slot@1 { + compatible = "cavium,octeon-6130-mmc-slot", "mmc-slot"; + reg = <1>; + vqmmc-supply = <®_mmc_3v3>; + voltage-ranges = <3300 3300>; + //spi-max-frequency = <52000000>; // just one + spi-max-frequency = <37000000>; // both slots + /* bus width can be 1, 4 or 8 */ + bus-width = <8>; /* new std property */ + cavium,bus-max-width = <8>; /* custom property */ + wp-gpios = <&gpio 24 0>; /* active high */ + cd-gpios = <&gpio 25 1>; /* active low */ + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mrvl,octeon-nic23.dts b/roms/u-boot/arch/mips/dts/mrvl,octeon-nic23.dts new file mode 100644 index 000000000..72ef56d83 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mrvl,octeon-nic23.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Marvell / Cavium Inc. NIC23 + */ + +/dts-v1/; + +#include "mrvl,cn73xx.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "cavium,nic23"; + compatible = "cavium,nic23"; + + aliases { + mmc0 = &mmc0; + serial0 = &uart0; + spi0 = &spi; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + /* Power on GPIO 8, active high */ + reg_mmc_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "mmc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&bootbus { + /* + * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000) + * as the initial size is too small for the 8MiB flash device + */ + ranges = <0 0 0 0x1f400000 0xc00000>, + <1 0 0x10000 0x10000000 0>, + <2 0 0x10000 0x20000000 0>, + <3 0 0x10000 0x30000000 0>, + <4 0 0 0x1d020000 0x10000>, + <5 0 0x10000 0x50000000 0>, + <6 0 0x10000 0x60000000 0>, + <7 0 0x10000 0x70000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <10>; + cavium,t-ce = <50>; + cavium,t-oe = <50>; + cavium,t-we = <35>; + cavium,t-rd-hld = <25>; + cavium,t-wr-hld = <35>; + cavium,t-pause = <0>; + cavium,t-wait = <50>; + cavium,t-page = <30>; + cavium,t-rd-dly = <0>; + cavium,page-mode = <1>; + cavium,pages = <8>; + cavium,bus-width = <8>; + }; + + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <10>; + cavium,t-ce = <10>; + cavium,t-oe = <160>; + cavium,t-we = <100>; + cavium,t-rd-hld = <10>; + cavium,t-wr-hld = <0>; + cavium,t-pause = <50>; + cavium,t-wait = <50>; + cavium,t-page = <10>; + cavium,t-rd-dly = <10>; + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "bootloader"; + reg = <0 0x340000>; + read-only; + }; + partition@300000 { + label = "storage"; + reg = <0x340000 0x4be000>; + }; + partition@7fe000 { + label = "environment"; + reg = <0x7fe000 0x2000>; + read-only; + }; + }; +}; + +&uart0 { + clock-frequency = <800000000>; +}; + +&i2c0 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&i2c1 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&mmc { + status = "okay"; + + mmc0: mmc-slot@0 { + compatible = "cavium,octeon-6130-mmc-slot", "mmc-slot"; + reg = <0>; + vqmmc-supply = <®_mmc_3v3>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <52000000>; + /* bus width can be 1, 4 or 8 */ + bus-width = <8>; /* new std property */ + cavium,bus-max-width = <8>; /* custom property */ + non-removable; + }; +}; + +&soc0 { + pci-console@0 { + compatible = "marvell,pci-console"; + status = "okay"; + }; + + pci-bootcmd@0 { + compatible = "marvell,pci-bootcmd"; + status = "okay"; + }; +}; + +&spi { + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <2000000>; + reg = <0>; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mscc,jr2.dtsi b/roms/u-boot/arch/mips/dts/mscc,jr2.dtsi new file mode 100644 index 000000000..87db7cae9 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mscc,jr2.dtsi @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,jr2"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + clocks = <&cpu_clk>; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + cpuintc: interrupt-controller@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + cpu_clk: cpu-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x70000000 0x2000000>; + + interrupt-parent = <&intc>; + + cpu_ctrl: syscon@0 { + compatible = "mscc,jr2-cpu-syscon", "syscon"; + reg = <0x0 0x2c>; + }; + + intc: interrupt-controller@70 { + compatible = "mscc,jr2-icpu-intr"; + reg = <0x70 0x94>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + uart0: serial@100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100000 0x20>; + interrupts = <6>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + uart2: serial@100800 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100800 0x20>; + interrupts = <7>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + spi0: spi-master@101000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,jaguar2-spi", "snps,dw-apb-ssi"; + reg = <0x101000 0x40>; + num-chipselect = <4>; + bus-num = <0>; + reg-io-width = <4>; + reg-shift = <2>; + spi-max-frequency = <18000000>; /* input clock */ + clocks = <&ahb_clk>; + + status = "disabled"; + }; + + reset@1010008 { + compatible = "mscc,jr2-chip-reset"; + reg = <0x1010008 0x4>; + }; + + gpio: pinctrl@1070034 { + compatible = "mscc,jaguar2-pinctrl"; + reg = <0x1010038 0x90>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 64>; + + sgpio_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + sgpio1_pins: sgpio1-pins { + pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; + function = "sg1"; + }; + + sgpio2_pins: sgpio2-pins { + pins = "GPIO_30", "GPIO_31", + "GPIO_32", "GPIO_33"; + function = "sg2"; + }; + + uart_pins: uart-pins { + pins = "GPIO_10", "GPIO_11"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_24", "GPIO_25"; + function = "uart2"; + }; + }; + + sgpio: gpio@1010150 { + compatible = "mscc,ocelot-sgpio"; + status = "disabled"; + pinctrl-0 = <&sgpio_pins>; + pinctrl-names = "default"; + reg = <0x1010150 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&sgpio 0 0 64>; + gpio-bank-name = "sgpio0_"; + sgpio-clock = <0x14>; + }; + + sgpio1: gpio@101025c { + compatible = "mscc,ocelot-sgpio"; + status = "disabled"; + pinctrl-0 = <&sgpio1_pins>; + pinctrl-names = "default"; + reg = <0x101025c 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&sgpio1 0 0 64>; + gpio-bank-name = "sgpio1_"; + sgpio-clock = <0x14>; + }; + + sgpio2: gpio@1010368 { + compatible = "mscc,ocelot-sgpio"; + status = "disabled"; + pinctrl-0 = <&sgpio2_pins>; + pinctrl-names = "default"; + reg = <0x1010368 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&sgpio2 0 0 64>; + gpio-bank-name = "sgpio2_"; + sgpio-clock = <0x14>; + }; + + switch: switch@1010000 { + compatible = "mscc,vsc7454-switch"; + reg = <0x01040000 0x0100>, // VTSS_TO_DEV_0 + <0x01050000 0x0100>, // VTSS_TO_DEV_1 + <0x01060000 0x0100>, // VTSS_TO_DEV_2 + <0x01070000 0x0100>, // VTSS_TO_DEV_3 + <0x01080000 0x0100>, // VTSS_TO_DEV_4 + <0x01090000 0x0100>, // VTSS_TO_DEV_5 + <0x010a0000 0x0100>, // VTSS_TO_DEV_6 + <0x010b0000 0x0100>, // VTSS_TO_DEV_7 + <0x010c0000 0x0100>, // VTSS_TO_DEV_8 + <0x010d0000 0x0100>, // VTSS_TO_DEV_9 + <0x010e0000 0x0100>, // VTSS_TO_DEV_10 + <0x010f0000 0x0100>, // VTSS_TO_DEV_11 + <0x01100000 0x0100>, // VTSS_TO_DEV_12 + <0x01110000 0x0100>, // VTSS_TO_DEV_13 + <0x01120000 0x0100>, // VTSS_TO_DEV_14 + <0x01130000 0x0100>, // VTSS_TO_DEV_15 + <0x01140000 0x0100>, // VTSS_TO_DEV_16 + <0x01150000 0x0100>, // VTSS_TO_DEV_17 + <0x01160000 0x0100>, // VTSS_TO_DEV_18 + <0x01170000 0x0100>, // VTSS_TO_DEV_19 + <0x01180000 0x0100>, // VTSS_TO_DEV_20 + <0x01190000 0x0100>, // VTSS_TO_DEV_21 + <0x011a0000 0x0100>, // VTSS_TO_DEV_22 + <0x011b0000 0x0100>, // VTSS_TO_DEV_23 + <0x011c0000 0x0100>, // VTSS_TO_DEV_24 + <0x011d0000 0x0100>, // VTSS_TO_DEV_25 + <0x011e0000 0x0100>, // VTSS_TO_DEV_26 + <0x011f0000 0x0100>, // VTSS_TO_DEV_27 + <0x01200000 0x0100>, // VTSS_TO_DEV_28 + <0x01210000 0x0100>, // VTSS_TO_DEV_29 + <0x01220000 0x0100>, // VTSS_TO_DEV_30 + <0x01230000 0x0100>, // VTSS_TO_DEV_31 + <0x01240000 0x0100>, // VTSS_TO_DEV_32 + <0x01250000 0x0100>, // VTSS_TO_DEV_33 + <0x01260000 0x0100>, // VTSS_TO_DEV_34 + <0x01270000 0x0100>, // VTSS_TO_DEV_35 + <0x01280000 0x0100>, // VTSS_TO_DEV_36 + <0x01290000 0x0100>, // VTSS_TO_DEV_37 + <0x012a0000 0x0100>, // VTSS_TO_DEV_38 + <0x012b0000 0x0100>, // VTSS_TO_DEV_39 + <0x012c0000 0x0100>, // VTSS_TO_DEV_40 + <0x012d0000 0x0100>, // VTSS_TO_DEV_41 + <0x012e0000 0x0100>, // VTSS_TO_DEV_42 + <0x012f0000 0x0100>, // VTSS_TO_DEV_43 + <0x01300000 0x0100>, // VTSS_TO_DEV_44 + <0x01310000 0x0100>, // VTSS_TO_DEV_45 + <0x01320000 0x0100>, // VTSS_TO_DEV_46 + <0x01330000 0x0100>, // VTSS_TO_DEV_47 + <0x01f00000 0x100000>, // ANA_AC + <0x01d00000 0x100000>, // ANA_CL + <0x01e00000 0x100000>, // ANA_L2 + <0x01410000 0x10000>, // ASM + <0x01460000 0x10000>, // HSIO + <0x01420000 0x00000>, // LRN + <0x017d0000 0x10000>, // QFWD + <0x01020000 0x20000>, // QS + <0x017e0000 0x10000>, // QSYS + <0x01b00000 0x80000>, // REW + <0x01010000 0x100>, // GCB + <0x00000000 0x100>; // ICPU + reg-names = "port0", "port1", "port2", "port3", "port4", + "port5", "port6", "port7", "port8", "port9", + "port10", "port11", "port12", "port13", + "port14", "port15", "port16", "port17", + "port18", "port19", "port20", "port21", + "port22", "port23", "port24", "port25", + "port26", "port27", "port28", "port29", + "port30", "port31", "port32", "port33", + "port34", "port35", "port36", "port37", + "port38", "port39", "port40", "port41", + "port42", "port43", "port44", "port45", + "port46", "port47", "ana_ac", "ana_cl", + "ana_l2", "asm", "hsio", "lrn", "qfwd", + "qs", "qsys", "rew", "gcb", "icpu"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio0: mdio@010100c8 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,jr2-miim"; + reg = <0x010100c8 0x24>; + status = "disabled"; + }; + + mdio1: mdio@010100ec { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,jr2-miim"; + reg = <0x010100ec 0x24>; + status = "disabled"; + }; + + mdio2: mdio@01010110 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,jr2-miim"; + reg = <0x01010110 0x24>; + status = "disabled"; + }; + + hsio: syscon@10d0000 { + compatible = "mscc,jr2-hsio", "syscon", "simple-mfd"; + reg = <0x10d0000 0x10000>; + + serdes_hsio: serdes_hsio { + compatible = "mscc,vsc7454-serdes"; + #phy-cells = <3>; + }; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mscc,luton.dtsi b/roms/u-boot/arch/mips/dts/mscc,luton.dtsi new file mode 100644 index 000000000..c8231018f --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mscc,luton.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,luton"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <208333333>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x60000000 0x10200000>; + + uart0: serial@10100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + + compatible = "ns16550a"; + reg = <0x10100000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + gpio: pinctrl@70068 { + compatible = "mscc,luton-pinctrl"; + reg = <0x70068 0x68>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 32>; + + sgpio_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sio"; + }; + uart_pins: uart-pins { + pins = "GPIO_30", "GPIO_31"; + function = "uart"; + }; + }; + + sgpio: gpio@70130 { + compatible = "mscc,luton-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio_pins>; + pinctrl-names = "default"; + reg = <0x0070130 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&sgpio 0 0 64>; + }; + + spi0: spi-bitbang { + compatible = "mscc,luton-bb-spi"; + status = "okay"; + reg = <0x10000064 0x4>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + switch: switch@1010000 { + compatible = "mscc,vsc7527-switch"; + reg = <0x1e0000 0x0100>, // VTSS_TO_DEV_0 + <0x1f0000 0x0100>, // VTSS_TO_DEV_1 + <0x200000 0x0100>, // VTSS_TO_DEV_2 + <0x210000 0x0100>, // VTSS_TO_DEV_3 + <0x220000 0x0100>, // VTSS_TO_DEV_4 + <0x230000 0x0100>, // VTSS_TO_DEV_5 + <0x240000 0x0100>, // VTSS_TO_DEV_6 + <0x250000 0x0100>, // VTSS_TO_DEV_7 + <0x260000 0x0100>, // VTSS_TO_DEV_8 + <0x270000 0x0100>, // VTSS_TO_DEV_9 + <0x280000 0x0100>, // VTSS_TO_DEV_10 + <0x290000 0x0100>, // VTSS_TO_DEV_11 + <0x2a0000 0x0100>, // VTSS_TO_DEV_12 + <0x2b0000 0x0100>, // VTSS_TO_DEV_13 + <0x2c0000 0x0100>, // VTSS_TO_DEV_14 + <0x2d0000 0x0100>, // VTSS_TO_DEV_15 + <0x2e0000 0x0100>, // VTSS_TO_DEV_16 + <0x2f0000 0x0100>, // VTSS_TO_DEV_17 + <0x300000 0x0100>, // VTSS_TO_DEV_18 + <0x310000 0x0100>, // VTSS_TO_DEV_19 + <0x320000 0x0100>, // VTSS_TO_DEV_20 + <0x330000 0x0100>, // VTSS_TO_DEV_21 + <0x340000 0x0100>, // VTSS_TO_DEV_22 + <0x350000 0x0100>, // VTSS_TO_DEV_23 + <0x010000 0x1000>, // VTSS_TO_SYS + <0x020000 0x1000>, // VTSS_TO_ANA + <0x030000 0x1000>, // VTSS_TO_REW + <0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB + <0x080000 0x0100>, // VTSS_TO_DEVCPU_QS + <0x0a0000 0x10000>; // VTSS_TO_HSIO + reg-names = "port0", "port1", "port2", "port3", + "port4", "port5", "port6", "port7", + "port8", "port9", "port10", "port11", + "port12", "port13", "port14", "port15", + "port16", "port17", "port18", "port19", + "port20", "port21", "port22", "port23", + "sys", "ana", "rew", "gcb", "qs", "hsio"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio0: mdio@700a0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,luton-miim"; + reg = <0x700a0 0x24>; + status = "disabled"; + }; + + mdio1: mdio@700c4 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,luton-miim"; + reg = <0x700c4 0x24>; + status = "disabled"; + }; + + hsio: syscon@10d0000 { + compatible = "mscc,luton-hsio", "syscon", "simple-mfd"; + reg = <0xa0000 0x10000>; + + serdes_hsio: serdes_hsio { + compatible = "mscc,vsc7527-serdes"; + #phy-cells = <3>; + }; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mscc,ocelot.dtsi b/roms/u-boot/arch/mips/dts/mscc,ocelot.dtsi new file mode 100644 index 000000000..aeb4bf8f4 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mscc,ocelot.dtsi @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,ocelot"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + clocks = <&cpu_clk>; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + cpuintc: interrupt-controller@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + cpu_clk: cpu-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + }; + + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x70000000 0x2000000>; + + interrupt-parent = <&intc>; + + cpu_ctrl: syscon@0 { + compatible = "mscc,ocelot-cpu-syscon", "syscon"; + reg = <0x0 0x2c>; + }; + + intc: interrupt-controller@70 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + uart0: serial@100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100000 0x20>; + interrupts = <6>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + uart2: serial@100800 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100800 0x20>; + interrupts = <7>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + spi0: spi-master@101000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi"; + reg = <0x101000 0x40>; + num-chipselect = <4>; + bus-num = <0>; + reg-io-width = <4>; + reg-shift = <2>; + spi-max-frequency = <18000000>; /* input clock */ + clocks = <&ahb_clk>; + + status = "disabled"; + }; + + switch: switch@1010000 { + pinctrl-0 = <&miim1_pins>; + pinctrl-names = "default"; + + compatible = "mscc,vsc7514-switch"; + + reg = <0x11e0000 0x100>, // VTSS_TO_DEV_0 + <0x11f0000 0x100>, // VTSS_TO_DEV_1 + <0x1200000 0x100>, // VTSS_TO_DEV_2 + <0x1210000 0x100>, // VTSS_TO_DEV_3 + <0x1220000 0x100>, // VTSS_TO_DEV_4 + <0x1230000 0x100>, // VTSS_TO_DEV_5 + <0x1240000 0x100>, // VTSS_TO_DEV_6 + <0x1250000 0x100>, // VTSS_TO_DEV_7 + <0x1260000 0x100>, // VTSS_TO_DEV_8 + <0x1270000 0x100>, // VTSS_TO_DEV_9 + <0x1280000 0x100>, // VTSS_TO_DEV_10 + <0x1010000 0x10000>, // VTSS_TO_SYS + <0x1030000 0x10000>, // VTSS_TO_REW + <0x1080000 0x100>, // VTSS_TO_DEVCPU_QS + <0x10d0000 0x10000>, // VTSS_TO_HSIO + <0x1800000 0x80000>,// VTSS_TO_QSYS + <0x1880000 0x10000>;// VTSS_TO_ANA + reg-names = "port0", "port1", "port2", "port3", "port4", + "port5", "port6", "port7", "port8", "port9", + "port10", + "sys", "rew", "qs", "hsio", "qsys", "ana"; + interrupts = <21 22>; + interrupt-names = "xtr", "inj"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio0: mdio@107009c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,ocelot-miim"; + reg = <0x107009c 0x24>; + interrupts = <14>; + status = "disabled"; + }; + + mdio1: mdio@10700f0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,ocelot-miim"; + reg = <0x10700c0 0x24>; + interrupts = <14>; + status = "disabled"; + }; + + hsio: syscon@10d0000 { + compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd"; + reg = <0x10d0000 0x10000>; + + serdes_hsio: serdes_hsio { + compatible = "mscc,vsc7514-serdes"; + #phy-cells = <3>; + }; + }; + + reset@1070008 { + compatible = "mscc,ocelot-chip-reset"; + reg = <0x1070008 0x4>; + }; + + gpio: pinctrl@1070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x1070034 0x68>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + sgpio_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + + spi_cs1_pin: spi-cs1-pin { + pins = "GPIO_8"; + function = "si"; + }; + + miim1_pins: miim1-pins { + pins = "GPIO_14", "GPIO_15"; + function = "miim1"; + }; + + spi_cs2_pin: spi-cs2-pin { + pins = "GPIO_9"; + function = "si"; + }; + + spi_cs3_pin: spi-cs3-pin { + pins = "GPIO_16"; + function = "si"; + }; + + spi_cs4_pin: spi-cs4-pin { + pins = "GPIO_17"; + function = "si"; + }; + }; + + sgpio: gpio@10700f8 { + compatible = "mscc,ocelot-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio_pins>; + pinctrl-names = "default"; + reg = <0x10700f8 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&sgpio 0 0 64>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mscc,ocelot_pcb.dtsi b/roms/u-boot/arch/mips/dts/mscc,ocelot_pcb.dtsi new file mode 100644 index 000000000..885b5643f --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mscc,ocelot_pcb.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,ocelot.dtsi" + +/ { + compatible = "mscc,ocelot"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi_cs1_pin>; + pinctrl-names = "default"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + }; + + spi-nand@1 { + compatible = "spi-nand"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <1>; /* CS1 */ + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mscc,serval.dtsi b/roms/u-boot/arch/mips/dts/mscc,serval.dtsi new file mode 100644 index 000000000..90eeebd3a --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mscc,serval.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,serval"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + clocks = <&cpu_clk>; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + cpuintc: interrupt-controller@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + cpu_clk: cpu-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <416666666>; + }; + + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <208333333>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <208333333>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x70000000 0x2000000>; + + interrupt-parent = <&intc>; + + cpu_ctrl: syscon@0 { + compatible = "mscc,serval-cpu-syscon", "syscon"; + reg = <0x0 0x2c>; + }; + + intc: interrupt-controller@70 { + compatible = "mscc,serval-icpu-intr"; + reg = <0x70 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + uart0: serial@100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100000 0x20>; + interrupts = <6>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + uart2: serial@100800 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100800 0x20>; + interrupts = <7>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + reset@1070008 { + compatible = "mscc,serval-chip-reset"; + reg = <0x1070008 0x4>; + }; + + gpio: pinctrl@1070034 { + compatible = "mscc,serval-pinctrl"; + reg = <0x1070034 0x68>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + sgpio_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1"; + function = "sio"; + }; + + uart_pins: uart-pins { + pins = "GPIO_26", "GPIO_27"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_13", "GPIO_14"; + function = "uart2"; + }; + }; + + spi0: spi-bitbang { + compatible = "mscc,luton-bb-spi"; + status = "okay"; + reg = <0x50 0x4>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sgpio: gpio@10700b4 { + compatible = "mscc,luton-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio_pins>; + pinctrl-names = "default"; + reg = <0x10700b4 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&sgpio 0 0 64>; + }; + + switch: switch@011e0000 { + compatible = "mscc,vsc7418-switch"; + reg = <0x011e0000 0x0100>, // VTSS_TO_DEV0 + <0x011f0000 0x0100>, // VTSS_TO_DEV1 + <0x01200000 0x0100>, // VTSS_TO_DEV2 + <0x01210000 0x0100>, // VTSS_TO_DEV3 + <0x01220000 0x0100>, // VTSS_TO_DEV4 + <0x01230000 0x0100>, // VTSS_TO_DEV5 + <0x01240000 0x0100>, // VTSS_TO_DEV6 + <0x01250000 0x0100>, // VTSS_TO_DEV7 + <0x01260000 0x0100>, // VTSS_TO_DEV8 + <0x01270000 0x0100>, // VTSS_TO_DEV9 + <0x01280000 0x0100>, // VTSS_TO_DEV10 + <0x01900000 0x100000>, // ANA + <0x01080000 0x20000>, // QS + <0x01800000 0x100000>, // QSYS + <0x01030000 0x10000>, // REW + <0x01010000 0x20000>, // SYS + <0x010a0000 0x10000>; // HSIO + reg-names = "port0", "port1", "port2", "port3", + "port4", "port5", "port6", "port7", + "port8", "port9", "port10", + "ana", "qs", "qsys", "rew", "sys", + "hsio"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio0: mdio@0107005c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,serval-miim"; + reg = <0x0107005c 0x24>; + status = "disabled"; + }; + + mdio1: mdio@01070080 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,serval-miim"; + reg = <0x01070080 0x24>; + status = "disabled"; + }; + + hsio: syscon@10d0000 { + compatible = "mscc,serval-hsio", "syscon", "simple-mfd"; + reg = <0x10a0000 0x10000>; + + serdes_hsio: serdes_hsio { + compatible = "mscc,vsc7418-serdes"; + #phy-cells = <3>; + }; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mscc,servalt.dtsi b/roms/u-boot/arch/mips/dts/mscc,servalt.dtsi new file mode 100644 index 000000000..45ae2de5e --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mscc,servalt.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,servalt"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + clocks = <&cpu_clk>; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + cpuintc: interrupt-controller@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + cpu_clk: cpu-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + }; + + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x70000000 0x2000000>; + + interrupt-parent = <&intc>; + + cpu_ctrl: syscon@0 { + compatible = "mscc,servalt-cpu-syscon", "syscon"; + reg = <0x0 0x2c>; + }; + + intc: interrupt-controller@70 { + compatible = "mscc,servalt-icpu-intr"; + reg = <0x70 0x74>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + uart0: serial@100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100000 0x20>; + interrupts = <6>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + uart2: serial@100800 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100800 0x20>; + interrupts = <7>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + reset@1010008 { + compatible = "mscc,servalt-chip-reset"; + reg = <0x1010008 0x4>; + }; + + gpio: pinctrl@1010034 { + compatible = "mscc,servalt-pinctrl"; + reg = <0x1010034 0x90>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 36>; + + sgpio_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sio"; + }; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_20", "GPIO_21"; + function = "uart2"; + }; + }; + + spi0: spi-bitbang { + compatible = "mscc,luton-bb-spi"; + status = "okay"; + reg = <0x50 0x4>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sgpio: gpio@1010120 { + compatible = "mscc,ocelot-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio_pins>; + pinctrl-names = "default"; + reg = <0x1010120 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&sgpio 0 0 128>; + }; + + switch: switch@1010000 { + compatible = "mscc,vsc7437-switch"; + reg = <0x01030000 0x0100>, // VTSS_TO_DEV_0 + <0x01040000 0x0100>, // VTSS_TO_DEV_1 + <0x01f00000 0x100000>, // ANA_AC + <0x01d00000 0x100000>, // ANA_CL + <0x01e00000 0x100000>, // ANA_L2 + <0x01120000 0x10000>, // ASM + <0x01130000 0x00000>, // LRN + <0x017d0000 0x10000>, // QFWD + <0x01020000 0x20000>, // QS + <0x017e0000 0x10000>, // QSYS + <0x01b00000 0x80000>; // REW + reg-names = "port0", "port1", + "ana_ac", "ana_cl", "ana_l2", "asm", "lrn", + "qfwd", "qs", "qsys", "rew"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio0: mdio@010100c4 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,jr2-miim"; + reg = <0x010100c4 0x24>; + status = "disabled"; + }; + + mdio1: mdio@010100e8 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,jr2-miim"; + reg = <0x010100e8 0x24>; + status = "disabled"; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mt7620-u-boot.dtsi b/roms/u-boot/arch/mips/dts/mt7620-u-boot.dtsi new file mode 100644 index 000000000..ed8425719 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mt7620-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +&uartlite { + u-boot,dm-pre-reloc; +}; + +&uartfull { + u-boot,dm-pre-reloc; +}; diff --git a/roms/u-boot/arch/mips/dts/mt7620.dtsi b/roms/u-boot/arch/mips/dts/mt7620.dtsi new file mode 100644 index 000000000..03a80b7a7 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mt7620.dtsi @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/clock/mt7620-clk.h> +#include <dt-bindings/reset/mt7620-reset.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7620-soc"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mti,mips24KEc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + clk48m: clk48m@0 { + compatible = "fixed-clock"; + + clock-frequency = <48000000>; + + #clock-cells = <0>; + }; + + sysc: sysc@10000000 { + compatible = "mediatek,mt7620-sysc"; + reg = <0x10000000 0x100>; + }; + + clkctrl: clkctrl@10000030 { + compatible = "mediatek,mt7620-clk"; + mediatek,sysc = <&sysc>; + + #clock-cells = <1>; + }; + + rstctrl: rstctrl@10000034 { + compatible = "mediatek,mtmips-reset"; + reg = <0x10000034 0x4>; + #reset-cells = <1>; + }; + + reboot: resetctl-reboot { + compatible = "resetctl-reboot"; + + resets = <&rstctrl SYS_RST>; + reset-names = "sysreset"; + }; + + uartfull: uartfull@10000500 { + compatible = "mediatek,mt7620-uart"; + reg = <10000500 0x100>; + + pinctrl-names = "default"; + pinctrl-0 = <&uartf_gpio_pins>; + + clocks = <&clkctrl CLK_UARTF>; + + resets = <&rstctrl UARTF_RST>; + reset-names = "uartf"; + + clock-frequency = <40000000>; + + status = "disabled"; + }; + + uartlite: uartlite@10000c00 { + compatible = "mediatek,mt7620-uart"; + reg = <0x10000c00 0x100>; + + pinctrl-names = "default"; + pinctrl-0 = <&uartl_pins>; + + clocks = <&clkctrl CLK_UARTL>; + + resets = <&rstctrl UARTL_RST>; + reset-names = "uartl"; + + clock-frequency = <40000000>; + }; + + pinctrl: pinctrl@10000060 { + compatible = "mediatek,mt7620-pinctrl"; + reg = <0x10000060 0x4>; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pin_state { + sutif_pins { + groups = "sutif"; + function = "none"; + }; + }; + + nand_pins: nand_pins { + groups = "nand"; + function = "nand"; + }; + + sd_pins: sd_pins { + groups = "nand"; + function = "sd"; + }; + + spi_single_pins: spi_single_pins { + groups = "spi"; + function = "spi"; + }; + + spi_dual_pins: spi_dual_pins { + spi_master_pins { + groups = "spi"; + function = "spi"; + }; + + spi_cs1_pin { + groups = "spi cs1"; + function = "spi cs1"; + }; + }; + + uartl_pins: uartl_pins { + groups = "uartl"; + function = "uartl"; + }; + + uartf_pins: uartf_pins { + groups = "uartf"; + function = "uartf"; + }; + + uartf_pcm_pins: uartf_pcm_pins { + groups = "uartf"; + function = "uartf pcm"; + }; + + uartf_i2s_pins: uartf_i2s_pins { + groups = "uartf"; + function = "i2s uartf"; + }; + + uartf_gpio_pins: uartf_gpio_pins { + groups = "uartf"; + function = "uartf gpio"; + }; + }; + + watchdog: watchdog@10000120 { + compatible = "mediatek,mt7620-wdt"; + reg = <0x10000120 0x10>; + + resets = <&rstctrl TIMER_RST>; + reset-names = "wdt"; + }; + + gpio0: gpio0@10000600 { + compatible = "mediatek,mt7620-gpio"; + reg = <0x10000600 0x34>; + + resets = <&rstctrl PIO_RST>; + reset-names = "pio"; + + mediatek,bank-name = "PIOA"; + mediatek,gpio-num = <24>; + mediatek,register-map = <0x20 0x24 0x2c 0x30>; + + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: gpio1@10000638 { + compatible = "mediatek,mt7620-gpio"; + reg = <0x10000638 0x24>; + + resets = <&rstctrl PIO_RST>; + reset-names = "pio"; + + mediatek,bank-name = "PIOB"; + mediatek,gpio-num = <16>; + mediatek,register-map = <0x10 0x14 0x1c 0x20>; + + gpio-controller; + #gpio-cells = <2>; + }; + + gpio2: gpio2@10000660 { + compatible = "mediatek,mt7620-gpio"; + reg = <0x10000660 0x24>; + + resets = <&rstctrl PIO_RST>; + reset-names = "pio"; + + mediatek,bank-name = "PIOC"; + mediatek,gpio-num = <32>; + mediatek,register-map = <0x10 0x14 0x1c 0x20>; + + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio3@10000688 { + compatible = "mediatek,mt7620-gpio"; + reg = <0x10000688 0x24>; + + resets = <&rstctrl PIO_RST>; + reset-names = "pio"; + + mediatek,bank-name = "PIOD"; + mediatek,gpio-num = <1>; + mediatek,register-map = <0x10 0x14 0x1c 0x20>; + + gpio-controller; + #gpio-cells = <2>; + }; + + spi0: spi@10000b00 { + compatible = "mediatek,mt7620-spi"; + reg = <0x10000b00 0x100>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_single_pins>; + + resets = <&rstctrl SPI_RST>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clkctrl CLK_SPI>; + }; + + eth: eth@10100000 { + compatible = "mediatek,mt7620-eth"; + reg = <0x10100000 0x10000 + 0x10110000 0x8000>; + reg-names = "fe", "esw"; + + mediatek,sysc = <&sysc>; + + resets = <&rstctrl EPHY_RST>, + <&rstctrl ESW_RST>, + <&rstctrl FE_RST>; + reset-names = "ephy", "esw", "fe"; + + clocks = <&clkctrl CLK_EPHY>, + <&clkctrl CLK_ESW>, + <&clkctrl CLK_FE>; + clock-names = "ephy", "esw", "fe"; + + status = "disabled"; + }; + + usb_phy: mt7620-usb-phy { + compatible = "mediatek,mt7620-usbphy"; + + #phy-cells = <0>; + + mediatek,sysc = <&sysc>; + + clocks = <&clkctrl CLK_UPHY_48M>, <&clkctrl CLK_UPHY_12M>; + clock-names = "uphy48m", "uphy12m"; + + resets = <&rstctrl UHST_RST>, <&rstctrl UDEV_RST>; + reset-names = "uhst", "udev"; + }; + + ehci@101c0000 { + compatible = "generic-ehci"; + reg = <0x101c0000 0x1000>; + + phys = <&usb_phy>; + phy-names = "usb"; + }; + + mmc: mmc@10130000 { + compatible = "mediatek,mt7620-mmc"; + reg = <0x10130000 0x4000>; + builtin-cd = <1>; + r_smpl = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins>; + + clocks = <&clk48m>, <&clkctrl CLK_SDHC>; + clock-names = "source", "hclk"; + + resets = <&rstctrl SDHC_RST>; + + status = "disabled"; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mt7628-u-boot.dtsi b/roms/u-boot/arch/mips/dts/mt7628-u-boot.dtsi new file mode 100644 index 000000000..eea5dc64b --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mt7628-u-boot.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +&palmbus { + u-boot,dm-pre-reloc; +}; + +&reboot { + u-boot,dm-pre-reloc; +}; + +&clkctrl { + u-boot,dm-pre-reloc; +}; + +&rstctrl { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/roms/u-boot/arch/mips/dts/mt7628a.dtsi b/roms/u-boot/arch/mips/dts/mt7628a.dtsi new file mode 100644 index 000000000..6baa63add --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mt7628a.dtsi @@ -0,0 +1,412 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/clock/mt7628-clk.h> +#include <dt-bindings/reset/mt7628-reset.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ralink,mt7628a-soc"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mti,mips24KEc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + clk48m: clk48m@0 { + compatible = "fixed-clock"; + + clock-frequency = <48000000>; + + #clock-cells = <0>; + }; + + palmbus: palmbus@10000000 { + compatible = "palmbus", "simple-bus"; + reg = <0x10000000 0x200000>; + ranges = <0x0 0x10000000 0x1FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc: system-controller@0 { + compatible = "ralink,mt7620a-sysc", "syscon"; + reg = <0x0 0x100>; + }; + + reboot: resetctl-reboot { + compatible = "resetctl-reboot"; + + resets = <&rstctrl MT7628_SYS_RST>; + reset-names = "sysreset"; + }; + + clkctrl: clkctrl@0x2c { + reg = <0x2c 0x8>, <0x10 0x4>; + reg-names = "syscfg0", "clkcfg"; + compatible = "mediatek,mt7628-clk"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + rstctrl: rstctrl@0x34 { + reg = <0x34 0x4>; + compatible = "mediatek,mtmips-reset"; + #reset-cells = <1>; + }; + + pinctrl: pinctrl@60 { + compatible = "mediatek,mt7628-pinctrl"; + reg = <0x3c 0x2c>, <0x1300 0x100>; + reg-names = "gpiomode", "padconf"; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pin_state { + }; + + spi_single_pins: spi_single_pins { + groups = "spi"; + function = "spi"; + }; + + spi_dual_pins: spi_dual_pins { + spi_master_pins { + groups = "spi"; + function = "spi"; + }; + + spi_cs1_pin { + groups = "spi cs1"; + function = "spi cs1"; + }; + }; + + uart0_pins: uart0_pins { + groups = "uart0"; + function = "uart0"; + }; + + uart1_pins: uart1_pins { + groups = "uart1"; + function = "uart1"; + }; + + uart2_pins: uart2_pins { + groups = "uart2"; + function = "uart2"; + }; + + uart2_pwm_pins: uart2_pwm_pins { + groups = "spis"; + function = "pwm_uart2"; + }; + + i2c_pins: i2c_pins { + groups = "i2c"; + function = "i2c"; + }; + + ephy_iot_mode: ephy_iot_mode { + ephy4_1_dis { + groups = "ephy4_1_pad"; + function = "digital"; + }; + + ephy0_en { + groups = "ephy0"; + function = "enable"; + }; + }; + + ephy_router_mode: ephy_router_mode { + ephy4_1_en { + groups = "ephy4_1_pad"; + function = "analog"; + }; + + ephy0_en { + groups = "ephy0"; + function = "enable"; + }; + }; + + sd_iot_mode: sd_iot_mode { + ephy4_1_dis { + groups = "ephy4_1_pad"; + function = "digital"; + }; + + sdxc_en { + groups = "sdmode"; + function = "sdxc"; + }; + + sdxc_iot_mode { + groups = "sd router"; + function = "iot"; + }; + + sd_clk_pad { + pins = "sd_clk"; + drive-strength-4g = <8>; + }; + }; + + sd_router_mode: sd_router_mode { + sdxc_router_mode { + groups = "sd router"; + function = "router"; + }; + + sdxc_map_pins { + groups = "gpio0", "i2s", "sdmode", \ + "i2c", "uart1"; + function = "gpio"; + }; + + sd_clk_pad { + pins = "gpio0"; + drive-strength-28 = <8>; + }; + }; + + emmc_iot_8bit_mode: emmc_iot_8bit_mode { + ephy4_1_dis { + groups = "ephy4_1_pad"; + function = "digital"; + }; + + emmc_en { + groups = "sdmode"; + function = "sdxc"; + }; + + emmc_iot_mode { + groups = "sd router"; + function = "iot"; + }; + + emmc_d4_d5 { + groups = "uart2"; + function = "sdxc d5 d4"; + }; + + emmc_d6 { + groups = "pwm1"; + function = "sdxc d6"; + }; + + emmc_d7 { + groups = "pwm0"; + function = "sdxc d7"; + }; + + sd_clk_pad { + pins = "sd_clk"; + drive-strength-4g = <8>; + }; + }; + }; + + watchdog: watchdog@100 { + compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt"; + reg = <0x100 0x30>; + + resets = <&rstctrl MT7628_TIMER_RST>; + reset-names = "wdt"; + + interrupt-parent = <&intc>; + interrupts = <24>; + }; + + intc: interrupt-controller@200 { + compatible = "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + resets = <&rstctrl MT7628_INT_RST>; + reset-names = "intc"; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + ralink,intc-registers = <0x9c 0xa0 + 0x6c 0xa4 + 0x80 0x78>; + }; + + memory-controller@300 { + compatible = "ralink,mt7620a-memc"; + reg = <0x300 0x100>; + }; + + gpio@600 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; + reg = <0x600 0x100>; + + resets = <&rstctrl MT7628_PIO_RST>; + reset-names = "pio"; + + interrupt-parent = <&intc>; + interrupts = <6>; + + gpio0: bank@0 { + reg = <0>; + compatible = "mtk,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: bank@1 { + reg = <1>; + compatible = "mtk,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio2: bank@2 { + reg = <2>; + compatible = "mtk,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + spi0: spi@b00 { + compatible = "ralink,mt7621-spi"; + reg = <0xb00 0x40>; + + resets = <&rstctrl MT7628_SPI_RST>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clkctrl CLK_SPI>; + }; + + uart0: uartlite@c00 { + compatible = "mediatek,hsuart", "ns16550a"; + reg = <0xc00 0x100>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + clocks = <&clkctrl CLK_UART0>; + + resets = <&rstctrl MT7628_UART0_RST>; + reset-names = "uart0"; + + interrupt-parent = <&intc>; + interrupts = <20>; + + reg-shift = <2>; + }; + + uart1: uart1@d00 { + compatible = "mediatek,hsuart", "ns16550a"; + reg = <0xd00 0x100>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + clocks = <&clkctrl CLK_UART1>; + + resets = <&rstctrl MT7628_UART1_RST>; + reset-names = "uart1"; + + interrupt-parent = <&intc>; + interrupts = <21>; + + reg-shift = <2>; + }; + + uart2: uart2@e00 { + compatible = "mediatek,hsuart", "ns16550a"; + reg = <0xe00 0x100>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + clocks = <&clkctrl CLK_UART2>; + + resets = <&rstctrl MT7628_UART2_RST>; + reset-names = "uart2"; + + interrupt-parent = <&intc>; + interrupts = <22>; + + reg-shift = <2>; + }; + }; + + eth: eth@10110000 { + compatible = "mediatek,mt7628-eth"; + reg = <0x10100000 0x10000 + 0x10110000 0x8000>; + + resets = <&rstctrl MT7628_EPHY_RST>; + reset-names = "ephy"; + + syscon = <&sysc>; + }; + + usb_phy: usb-phy@10120000 { + compatible = "mediatek,mt7628-usbphy"; + reg = <0x10120000 0x1000>; + + #phy-cells = <0>; + + ralink,sysctl = <&sysc>; + + resets = <&rstctrl MT7628_UPHY_RST>; + reset-names = "phy"; + + clocks = <&clkctrl CLK_UPHY>; + clock-names = "cg"; + }; + + ehci@101c0000 { + compatible = "generic-ehci"; + reg = <0x101c0000 0x1000>; + + phys = <&usb_phy>; + phy-names = "usb"; + + interrupt-parent = <&intc>; + interrupts = <18>; + }; + + mmc: mmc@10130000 { + compatible = "mediatek,mt7620-mmc"; + reg = <0x10130000 0x4000>; + builtin-cd = <1>; + r_smpl = <1>; + + clocks = <&clk48m>, <&clkctrl CLK_SDXC>; + clock-names = "source", "hclk"; + + resets = <&rstctrl MT7628_SDXC_RST>; + + status = "disabled"; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/mti,malta.dts b/roms/u-boot/arch/mips/dts/mti,malta.dts new file mode 100644 index 000000000..d339229c2 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/mti,malta.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +/memreserve/ 0x00000000 0x00001000; /* Exception vectors */ +/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mti,malta"; + + chosen { + stdout-path = &uart0; + }; + + isa@0 { + compatible = "isa"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0 0x1000>; + + uart0: serial@3f8 { + compatible = "ns16550a"; + + reg = <1 0x3f8 0x40>; + reg-shift = <0>; + + clock-frequency = <1843200>; + + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/netgear,cg3100d.dts b/roms/u-boot/arch/mips/dts/netgear,cg3100d.dts new file mode 100644 index 000000000..a42a0da2d --- /dev/null +++ b/roms/u-boot/arch/mips/dts/netgear,cg3100d.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +/dts-v1/; + +#include "brcm,bcm3380.dtsi" + +/ { + model = "Netgear CG3100D"; + compatible = "netgear,cg3100d", "brcm,bcm3380"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + wifi_green { + label = "CG3100D:green:wifi"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + }; + + wps_green { + label = "CG3100D:green:wps"; + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + power_red { + label = "CG3100D:red:power"; + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&leds { + status = "okay"; + + led@0 { + reg = <0>; + active-low; + label = "CG3100D:green:power"; + }; + + led@1 { + reg = <1>; + active-low; + label = "CG3100D:green:downlink"; + }; + + led@2 { + reg = <2>; + active-low; + label = "CG3100D:orange:downlink"; + }; + + led@3 { + reg = <3>; + active-low; + label = "CG3100D:green:uplink"; + }; + + led@4 { + reg = <4>; + active-low; + label = "CG3100D:orange:uplink"; + }; + + led@6 { + reg = <6>; + active-low; + label = "CG3100D:green:inet"; + }; + + led@7 { + reg = <7>; + active-low; + label = "CG3100D:green:stby"; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&spi { + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <25000000>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/netgear,dgnd3700v2.dts b/roms/u-boot/arch/mips/dts/netgear,dgnd3700v2.dts new file mode 100644 index 000000000..88fca647c --- /dev/null +++ b/roms/u-boot/arch/mips/dts/netgear,dgnd3700v2.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +/dts-v1/; + +#include "brcm,bcm6362.dtsi" + +/ { + model = "Netgear DGND3700v2"; + compatible = "netgear,dgnd3700v2", "brcm,bcm6362"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "DGND3700v2:green:inet"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + dsl_green { + label = "DGND3700v2:green:dsl"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + power_amber { + label = "DGND3700v2:red:power"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&enet { + status = "okay"; + + port@4 { + compatible = "brcm,enetsw-port"; + reg = <4>; + label = "rgmii"; + brcm,phy-id = <0xff>; + speed = <1000>; + full-duplex; + bypass-link; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&leds { + status = "okay"; + brcm,serial-leds; + brcm,serial-dat-low; + brcm,serial-shift-inv; + brcm,serial-mux; + + led@8 { + reg = <8>; + label = "DGND3700v2:green:power"; + }; + + led@9 { + reg = <9>; + active-low; + label = "DGND3700v2:green:wps"; + }; + + led@10 { + reg = <10>; + active-low; + label = "DGND3700v2:green:usb1"; + }; + + led@11 { + reg = <11>; + active-low; + label = "DGND3700v2:green:usb2"; + }; + + led@12 { + reg = <12>; + active-low; + label = "DGND3700v2:amber:inet"; + }; + + led@13 { + reg = <13>; + active-low; + label = "DGND3700v2:green:ethernet"; + }; + + led@14 { + reg = <14>; + active-low; + label = "DGND3700v2:amber:dsl"; + }; + + led@16 { + reg = <16>; + active-low; + label = "DGND3700v2:amber:usb1"; + }; + + led@17 { + reg = <17>; + active-low; + label = "DGND3700v2:amber:usb2"; + }; + + led@18 { + reg = <18>; + active-low; + label = "DGND3700v2:amber:ethernet"; + }; +}; + +&ohci { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/nexys4ddr.dts b/roms/u-boot/arch/mips/dts/nexys4ddr.dts new file mode 100644 index 000000000..6de8584ea --- /dev/null +++ b/roms/u-boot/arch/mips/dts/nexys4ddr.dts @@ -0,0 +1,61 @@ +/dts-v1/; + +#include "microAptiv.dtsi" + +/ { + compatible = "digilent,nexys4ddr"; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + cpuintc: interrupt-controller@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + aliases { + console = &axi_uart16550; + }; + + axi_ethernetlite: ethernet@10e00000 { + compatible = "xlnx,xps-ethernetlite-1.00.a"; + device_type = "network"; + local-mac-address = [08 86 4C 0D F7 09]; + phy-handle = <&phy0>; + reg = <0x10e00000 0x10000>; + xlnx,duplex = <0x1>; + xlnx,include-global-buffers = <0x1>; + xlnx,include-internal-loopback = <0x0>; + xlnx,include-mdio = <0x1>; + xlnx,instance = "axi_ethernetlite_inst"; + xlnx,rx-ping-pong = <0x1>; + xlnx,s-axi-id-width = <0x1>; + xlnx,tx-ping-pong = <0x1>; + xlnx,use-internal = <0x0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@1 { + device_type = "ethernet-phy"; + reg = <1>; + } ; + } ; + } ; + + + axi_uart16550: serial@10400000 { + compatible = "ns16550a"; + reg = <0x10400000 0x10000>; + + reg-shift = <2>; + reg-offset = <0x1000>; + + clock-frequency = <50000000>; + + }; +}; + diff --git a/roms/u-boot/arch/mips/dts/ocelot_pcb120.dts b/roms/u-boot/arch/mips/dts/ocelot_pcb120.dts new file mode 100644 index 000000000..e608029a3 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/ocelot_pcb120.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,ocelot_pcb.dtsi" +#include <dt-bindings/mscc/ocelot_data.h> + +/ { + model = "Ocelot PCB120 Reference Board"; + compatible = "mscc,ocelot-pcb120", "mscc,ocelot"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + poe_green { + label = "pcb120:green:poe"; + gpios = <&sgpio 44 1>; /* p12.1 */ + default-state = "off"; + }; + + poe_red { + label = "pcb120:red:poe"; + gpios = <&sgpio 12 1>; /* p12.0 */ + default-state = "off"; + }; + + alarm_green { + label = "pcb120:green:alarm"; + gpios = <&sgpio 45 1>; /* p13.1 */ + default-state = "off"; + }; + + alarm_red { + label = "pcb120:red:alarm"; + gpios = <&sgpio 13 1>; /* p13.0 */ + default-state = "off"; + }; + + dc_a_green { + label = "pcb120:green:dc_a"; + gpios = <&sgpio 46 1>; /* p14.1 */ + default-state = "off"; + }; + + dc_a_red { + label = "pcb120:red:dc_a"; + gpios = <&sgpio 14 1>; /* p14.0 */ + default-state = "off"; + }; + + dc_b_green { + label = "pcb120:green:dc_b"; + gpios = <&sgpio 47 1>; /* p15.1 */ + default-state = "off"; + }; + + dc_b_red { + label = "pcb120:red:dc_b"; + gpios = <&sgpio 15 1>; /* p15.0 */ + default-state = "off"; + }; + + status_green { + label = "pcb120:green:status"; + gpios = <&sgpio 48 1>; /* p16.1 */ + default-state = "on"; + }; + + status_red { + label = "pcb120:red:alarm"; + gpios = <&sgpio 16 1>; /* p16.0 */ + default-state = "off"; + }; + + }; + +}; + +&sgpio { + status = "okay"; + mscc,sgpio-ports = <0x000FFFFF>; +}; + +&mdio0 { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <3>; + }; + phy5: ethernet-phy@5 { + reg = <2>; + }; + phy6: ethernet-phy@6 { + reg = <1>; + }; + phy7: ethernet-phy@7 { + reg = <0>; + }; +}; + +&mdio1 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <3>; + }; + phy1: ethernet-phy@1 { + reg = <2>; + }; + phy2: ethernet-phy@2 { + reg = <1>; + }; + phy3: ethernet-phy@3 { + reg = <0>; + }; +}; + +&switch { + ethernet-ports { + port0: port@0 { + reg = <5>; + phy-handle = <&phy0>; + phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>; + }; + port1: port@1 { + reg = <9>; + phy-handle = <&phy1>; + phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>; + }; + port2: port@2 { + reg = <6>; + phy-handle = <&phy2>; + phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>; + }; + port3: port@3 { + reg = <4>; + phy-handle = <&phy3>; + phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>; + }; + port4: port@4 { + reg = <3>; + phy-handle = <&phy4>; + }; + port5: port@5 { + reg = <2>; + phy-handle = <&phy5>; + }; + port6: port@6 { + reg = <1>; + phy-handle = <&phy6>; + }; + port7: port@7 { + reg = <0>; + phy-handle = <&phy7>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/ocelot_pcb123.dts b/roms/u-boot/arch/mips/dts/ocelot_pcb123.dts new file mode 100644 index 000000000..1b0156e50 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/ocelot_pcb123.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,ocelot_pcb.dtsi" + +/ { + model = "Ocelot PCB123 Reference Board"; + compatible = "mscc,ocelot-pcb123", "mscc,ocelot"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_green { + label = "pcb123:green:status"; + gpios = <&sgpio 43 1>; /* p11.1 */ + default-state = "on"; + }; + + status_red { + label = "pcb123:red:status"; + gpios = <&sgpio 11 1>; /* p11.0 */ + default-state = "off"; + }; + }; +}; + +&sgpio { + status = "okay"; + mscc,sgpio-ports = <0x00FFFFFF>; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; +}; + +&switch { + ethernet-ports { + port0: port@0 { + reg = <2>; + phy-handle = <&phy2>; + }; + port1: port@1 { + reg = <3>; + phy-handle = <&phy3>; + }; + port2: port@2 { + reg = <0>; + phy-handle = <&phy0>; + }; + port3: port@3 { + reg = <1>; + phy-handle = <&phy1>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/pic32mzda.dtsi b/roms/u-boot/arch/mips/dts/pic32mzda.dtsi new file mode 100644 index 000000000..43cd7cf30 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/pic32mzda.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Microchip Technology, Inc. + * Purna Chandra Mandal, <purna.mandal@microchip.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/microchip,clock.h> +#include <dt-bindings/gpio/gpio.h> +#include "skeleton.dtsi" + +/ { + compatible = "microchip,pic32mzda", "microchip,pic32mz"; + + aliases { + gpio0 = &gpioA; + gpio1 = &gpioB; + gpio2 = &gpioC; + gpio3 = &gpioD; + gpio4 = &gpioE; + gpio5 = &gpioF; + gpio6 = &gpioG; + gpio7 = &gpioH; + gpio8 = &gpioJ; + gpio9 = &gpioK; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips14kc"; + device-type = "cpu"; + reg = <0>; + }; + }; + + clock: clk@1f801200 { + compatible = "microchip,pic32mzda-clk"; + reg = <0x1f801200 0x1000>; + #clock-cells = <1>; + }; + + uart1: serial@1f822000 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822000 0x50>; + interrupt-parent = <&evic>; + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clock PB2CLK>; + }; + + uart2: serial@1f822200 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822200 0x50>; + interrupt-parent = <&evic>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB2CLK>; + status = "disabled"; + }; + + uart6: serial@1f822a00 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822a00 0x50>; + interrupt-parent = <&evic>; + interrupts = <188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB2CLK>; + status = "disabled"; + }; + + evic: interrupt-controller@1f810000 { + compatible = "microchip,pic32mzda-evic"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1f810000 0x1000>; + }; + + pinctrl: pinctrl@1f801400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "microchip,pic32mzda-pinctrl"; + reg = <0x1f801400 0x100>, /* in */ + <0x1f801500 0x200>, /* out */ + <0x1f860000 0xa00>; /* port */ + reg-names = "ppsin","ppsout","port"; + status = "disabled"; + + gpioA: gpio0@1f860000 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x1f860000 0xe0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioB: gpio1@1f860100 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x1f860100 0xe0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioC: gpio2@1f860200 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x1f860200 0xe0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioD: gpio3@1f860300 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x1f860300 0xe0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioE: gpio4@1f860400 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x1f860400 0xe0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioF: gpio5@1f860500 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x1f860500 0xe0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioG: gpio6@1f860600 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x1f860600 0xe0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioH: gpio7@1f860700 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x1f860700 0xe0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioJ: gpio9@1f860800 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x1f860800 0xe0>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioK: gpio10@1f860900 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x1f860900 0xe0>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + sdhci: sdhci@1f8ec000 { + compatible = "microchip,pic32mzda-sdhci"; + reg = <0x1f8ec000 0x100>; + interrupt-parent = <&evic>; + interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock REF4CLK>, <&clock PB5CLK>; + clock-names = "base_clk", "sys_clk"; + clock-freq-min-max = <25000000>,<25000000>; + bus-width = <4>; + status = "disabled"; + }; + + ethernet: ethernet@1f882000 { + compatible = "microchip,pic32mzda-eth"; + reg = <0x1f882000 0x1000>; + interrupt-parent = <&evic>; + interrupts = <153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB5CLK>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb: musb@1f8e3000 { + compatible = "microchip,pic32mzda-usb"; + reg = <0x1f8e3000 0x1000>, + <0x1f884000 0x1000>; + reg-names = "mc", "control"; + interrupt-parent = <&evic>; + interrupts = <132 IRQ_TYPE_EDGE_RISING>, + <133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB5CLK>; + clock-names = "usb_clk"; + status = "disabled"; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/pic32mzda_sk.dts b/roms/u-boot/arch/mips/dts/pic32mzda_sk.dts new file mode 100644 index 000000000..fc86154e0 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/pic32mzda_sk.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Purna Chandra Mandal, purna.mandal@microchip.com + */ + +/dts-v1/; + +#include "pic32mzda.dtsi" + +/ { + model = "Microchip PIC32MZDASK"; + compatible = "microchip,pic32mzdask", "microchip,pic32mzda"; + + aliases { + console = &uart2; + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&clock { + microchip,refo2-frequency = <50000000>; + microchip,refo4-frequency = <25000000>; + microchip,refo5-frequency = <40000000>; + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&uart2 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&sdhci { + microchip,use-sdcd; + status = "okay"; +}; + +ðernet { + reset-gpios = <&gpioJ 15 0>; + status = "okay"; + phy-mode = "rmii"; + phy-handle = <ðernet_phy>; + ethernet_phy: lan8740_phy@0 { + reg = <0>; + }; +}; + +&usb { + status = "okay"; +};
\ No newline at end of file diff --git a/roms/u-boot/arch/mips/dts/qca953x.dtsi b/roms/u-boot/arch/mips/dts/qca953x.dtsi new file mode 100644 index 000000000..90d34ddbb --- /dev/null +++ b/roms/u-boot/arch/mips/dts/qca953x.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + */ + +#include "skeleton.dtsi" + +/ { + compatible = "qca,qca953x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + pinctrl { + u-boot,dm-pre-reloc; + compatible = "qca,qca953x-pinctrl"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18040000 0x100>; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@18020000 { + compatible = "ns16550"; + reg = <0x18020000 0x20>; + reg-shift = <2>; + clock-frequency = <25000000>; + + status = "disabled"; + }; + + gmac0: eth0@0x19000000 { + compatible = "qca,ag953x-mac"; + reg = <0x19000000 0x200>; + phy = <&phy4>; + phy-mode = "rmii"; + + status = "disabled"; + }; + + gmac1: eth1@0x1a000000 { + compatible = "qca,ag953x-mac"; + reg = <0x1a000000 0x200>; + phy = <&phy0>; + phy-mode = "rgmii"; + + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "rmii"; + }; + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rmii"; + }; + }; + }; + }; + + spi0: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/qca956x.dtsi b/roms/u-boot/arch/mips/dts/qca956x.dtsi new file mode 100644 index 000000000..6cb360b3f --- /dev/null +++ b/roms/u-boot/arch/mips/dts/qca956x.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Rosy Song <rosysong@rosinson.com> + */ + +#include "skeleton.dtsi" + +/ { + compatible = "qca,qca956x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips74Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@18020000 { + compatible = "ns16550"; + reg = <0x18020000 0x20>; + reg-shift = <2>; + + status = "disabled"; + }; + + gmac0: eth@0x19000000 { + compatible = "qca,ag956x-mac"; + reg = <0x19000000 0x200>; + phy = <&phy0>; + phy-mode = "sgmii"; + + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + }; + + spi0: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/sagem,f@st1704.dts b/roms/u-boot/arch/mips/dts/sagem,f@st1704.dts new file mode 100644 index 000000000..98ed353f2 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/sagem,f@st1704.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +/dts-v1/; + +#include "brcm,bcm6338.dtsi" + +/ { + model = "Sagem F@ST1704"; + compatible = "sagem,f@st1704", "brcm,bcm6338"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "F@ST1704:green:inet"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + + power_green { + label = "F@ST1704:green:power"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + + inet_red { + label = "F@ST1704:red:inet"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&enet { + status = "okay"; + phy = <&enetphy>; + phy-mode = "mii"; + + enetphy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + +&gpio { + status = "okay"; +}; + +&spi { + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/serval2_pcb112.dts b/roms/u-boot/arch/mips/dts/serval2_pcb112.dts new file mode 100644 index 000000000..5777a773b --- /dev/null +++ b/roms/u-boot/arch/mips/dts/serval2_pcb112.dts @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,jr2.dtsi" +#include <dt-bindings/mscc/jr2_data.h> + +/ { + model = "Serval2 NID PCB112 Reference Board"; + compatible = "mscc,serval2-pcb110", "mscc,jr2"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_green { + label = "pcb110:green:status"; + gpios = <&gpio 12 0>; + default-state = "on"; + }; + + status_red { + label = "pcb110:red:status"; + gpios = <&gpio 13 0>; + default-state = "off"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + }; +}; + +&sgpio { + status = "okay"; + sgpio-ports = <0x0000ffff>; +}; + +&sgpio2 { + status = "okay"; + sgpio-ports = <0x3fe0ffff>; +}; + +&mdio0 { + status = "okay"; + + phy16: ethernet-phy@16 { + reg = <16>; + }; + phy17: ethernet-phy@17 { + reg = <17>; + }; + phy18: ethernet-phy@18 { + reg = <18>; + }; + phy19: ethernet-phy@19 { + reg = <19>; + }; +}; + +&switch { + ethernet-ports { + + port0: port@0 { + reg = <24>; + phy-handle = <&phy16>; + phys = <&serdes_hsio 24 SERDES6G(0) PHY_MODE_SGMII>; + }; + port1: port@1 { + reg = <25>; + phy-handle = <&phy17>; + phys = <&serdes_hsio 25 SERDES6G(1) PHY_MODE_SGMII>; + }; + port2: port@2 { + reg = <26>; + phy-handle = <&phy18>; + phys = <&serdes_hsio 26 SERDES6G(2) PHY_MODE_SGMII>; + }; + port3: port@3 { + reg = <27>; + phy-handle = <&phy19>; + phys = <&serdes_hsio 27 SERDES6G(3) PHY_MODE_SGMII>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/serval_pcb105.dts b/roms/u-boot/arch/mips/dts/serval_pcb105.dts new file mode 100644 index 000000000..667277080 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/serval_pcb105.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,serval.dtsi" +#include <dt-bindings/mscc/serval_data.h> + +/ { + model = "Serval PCB105 Reference Board"; + compatible = "mscc,serval-pcb105", "mscc,serval"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_green { + label = "pcb105:green:status"; + gpios = <&sgpio 43 1>; /* p11.1 */ + default-state = "on"; + }; + + status_red { + label = "pcb105:red:status"; + gpios = <&sgpio 11 1>; /* p11.0 */ + default-state = "off"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + spi-cs-high; + }; +}; + +&sgpio { + status = "okay"; + sgpio-ports = <0x00FFFFFF>; +}; + +&mdio1 { + status = "okay"; + + phy16: ethernet-phy@16 { + reg = <16>; + }; + phy17: ethernet-phy@17 { + reg = <17>; + }; + phy18: ethernet-phy@18 { + reg = <18>; + }; + phy19: ethernet-phy@19 { + reg = <19>; + }; +}; + +&switch { + ethernet-ports { + + port0: port@0 { + reg = <7>; + phy-handle = <&phy16>; + phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>; + }; + port1: port@1 { + reg = <6>; + phy-handle = <&phy17>; + phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>; + }; + port2: port@2 { + reg = <5>; + phy-handle = <&phy18>; + phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>; + }; + port3: port@3 { + reg = <4>; + phy-handle = <&phy19>; + phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/serval_pcb106.dts b/roms/u-boot/arch/mips/dts/serval_pcb106.dts new file mode 100644 index 000000000..e77c35786 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/serval_pcb106.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,serval.dtsi" +#include <dt-bindings/mscc/serval_data.h> + +/ { + model = "Serval PCB106 Reference Board"; + compatible = "mscc,serval-pcb106", "mscc,serval"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_green { + label = "pcb106:green:status"; + gpios = <&sgpio 43 1>; /* p11.1 */ + default-state = "on"; + }; + + status_red { + label = "pcb106:red:status"; + gpios = <&sgpio 11 1>; /* p11.0 */ + default-state = "off"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + spi-cs-high; + }; +}; + +&sgpio { + status = "okay"; + sgpio-ports = <0x00FFFFFF>; +}; + +&mdio1 { + status = "okay"; + + phy16: ethernet-phy@16 { + reg = <16>; + }; + phy17: ethernet-phy@17 { + reg = <17>; + }; + phy18: ethernet-phy@18 { + reg = <18>; + }; + phy19: ethernet-phy@19 { + reg = <19>; + }; +}; + +&switch { + ethernet-ports { + + port0: port@0 { + reg = <7>; + phy-handle = <&phy16>; + phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>; + }; + port1: port@1 { + reg = <6>; + phy-handle = <&phy17>; + phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>; + }; + port2: port@2 { + reg = <5>; + phy-handle = <&phy18>; + phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>; + }; + port3: port@3 { + reg = <4>; + phy-handle = <&phy19>; + phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/servalt_pcb116.dts b/roms/u-boot/arch/mips/dts/servalt_pcb116.dts new file mode 100644 index 000000000..313b0998e --- /dev/null +++ b/roms/u-boot/arch/mips/dts/servalt_pcb116.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,servalt.dtsi" + +/ { + model = "ServalT PCB116 Reference Board"; + compatible = "mscc,servalt-pcb116", "mscc,servalt"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status_green { + label = "pcb116:green:status"; + gpios = <&sgpio 70 0>; /* p6.2 */ + default-state = "on"; + }; + + status_red { + label = "pcb116:red:status"; + gpios = <&sgpio 102 0>; /* p6.3 */ + default-state = "off"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + spi-cs-high; + }; +}; + +&sgpio { + status = "okay"; + sgpio-ports = <0x0000fe7f>; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&switch { + ethernet-ports { + + port0: port@0 { + reg = <0>; + phy-handle = <&phy0>; + }; + port1: port@1 { + reg = <1>; + phy-handle = <&phy1>; + }; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/sfr,nb4-ser.dts b/roms/u-boot/arch/mips/dts/sfr,nb4-ser.dts new file mode 100644 index 000000000..dfbc4148d --- /dev/null +++ b/roms/u-boot/arch/mips/dts/sfr,nb4-ser.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +/dts-v1/; + +#include "brcm,bcm6358.dtsi" + +/ { + model = "SFR NeufBox 4 (Sercomm) Board"; + compatible = "sfr,nb4-ser", "brcm,bcm6358"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + traffic_white { + label = "NB4-SER:white:traffic"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + service_blue { + label = "NB4-SER:blue:service"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + }; + + wifi_white { + label = "NB4-SER:white:wifi"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + service_red { + label = "NB4-SER:red:service"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + + service_green { + label = "NB4-SER:green:service"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&enet0 { + status = "okay"; + phy = <&enet0phy>; + phy-mode = "internal"; + + enet0phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&leds { + status = "okay"; + brcm,clk-div = <1>; + + led@0 { + reg = <0>; + active-low; + label = "NB4-SER:white:alarm"; + }; + + led@2 { + reg = <2>; + active-low; + label = "NB4-SER:white:tv"; + }; + + led@3 { + reg = <3>; + active-low; + label = "NB4-SER:white:tel"; + }; + + led@4 { + reg = <4>; + active-low; + label = "NB4-SER:white:adsl"; + }; +}; + +&ohci { + status = "okay"; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; diff --git a/roms/u-boot/arch/mips/dts/skeleton.dtsi b/roms/u-boot/arch/mips/dts/skeleton.dtsi new file mode 100644 index 000000000..422fcdb17 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/skeleton.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + + chosen { + }; + + aliases { + }; + + memory { + device_type = "memory"; + reg = <0 0>; + }; +}; diff --git a/roms/u-boot/arch/mips/dts/tplink_wdr4300.dts b/roms/u-boot/arch/mips/dts/tplink_wdr4300.dts new file mode 100644 index 000000000..2bcad6d20 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/tplink_wdr4300.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Marek Vasut <marex@denx.de> + */ + +/dts-v1/; +#include "ar934x.dtsi" + +/ { + model = "TP-Link WDR4300 Board"; + compatible = "tplink,wdr4300", "qca,ar934x"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + memory-map = <0x1e000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +&uart0 { + clock-frequency = <40000000>; + status = "okay"; +}; + +&xtal { + clock-frequency = <40000000>; +}; diff --git a/roms/u-boot/arch/mips/dts/vocore_vocore2.dts b/roms/u-boot/arch/mips/dts/vocore_vocore2.dts new file mode 100644 index 000000000..9adf39652 --- /dev/null +++ b/roms/u-boot/arch/mips/dts/vocore_vocore2.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Mauro Condarelli <mc5686@mclink.it> + */ + +/dts-v1/; + +#include "mt7628a.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "vocore,vocore2", "ralink,mt7628a-soc"; + model = "VoCore2"; + + aliases { + serial0 = &uart2; + spi0 = &spi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + leds { + compatible = "gpio-leds"; + + power { + label = "vocore:power"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + chosen { + bootargs = "console=ttyS2,115200"; + stdout-path = &uart2; + }; +}; + +&pinctrl { + state_default: pin_state { + p0led { + groups = "p0led_a"; + function = "led"; + }; + }; +}; + +&uart2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pwm_pins>; +}; + +&spi0 { + status = "okay"; + nor0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + }; +}; + +ð { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&ephy_iot_mode>; + mediatek,poll-link-phy = <0>; +}; + +&mmc { + status = "okay"; + + bus-width = <4>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_iot_mode>; +}; |