aboutsummaryrefslogtreecommitdiffstats
path: root/roms/u-boot/arch/x86/include/asm/arch-queensbay
diff options
context:
space:
mode:
Diffstat (limited to 'roms/u-boot/arch/x86/include/asm/arch-queensbay')
-rw-r--r--roms/u-boot/arch/x86/include/asm/arch-queensbay/device.h93
-rw-r--r--roms/u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h18
-rw-r--r--roms/u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h52
-rw-r--r--roms/u-boot/arch/x86/include/asm/arch-queensbay/tnc.h52
4 files changed, 215 insertions, 0 deletions
diff --git a/roms/u-boot/arch/x86/include/asm/arch-queensbay/device.h b/roms/u-boot/arch/x86/include/asm/arch-queensbay/device.h
new file mode 100644
index 000000000..15857bfba
--- /dev/null
+++ b/roms/u-boot/arch/x86/include/asm/arch-queensbay/device.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _QUEENSBAY_DEVICE_H_
+#define _QUEENSBAY_DEVICE_H_
+
+#include <pci.h>
+
+/* TunnelCreek PCI Devices */
+#define TNC_HOST_BRIDGE_DEV 0
+#define TNC_HOST_BRIDGE_FUNC 0
+#define TNC_IGD_DEV 2
+#define TNC_IGD_FUNC 0
+#define TNC_SDVO_DEV 3
+#define TNC_SDVO_FUNC 0
+#define TNC_PCIE0_DEV 23
+#define TNC_PCIE0_FUNC 0
+#define TNC_PCIE1_DEV 24
+#define TNC_PCIE1_FUNC 0
+#define TNC_PCIE2_DEV 25
+#define TNC_PCIE2_FUNC 0
+#define TNC_PCIE3_DEV 26
+#define TNC_PCIE3_FUNC 0
+#define TNC_HDA_DEV 27
+#define TNC_HDA_FUNC 0
+#define TNC_LPC_DEV 31
+#define TNC_LPC_FUNC 0
+
+#define TNC_HOST_BRIDGE \
+ PCI_BDF(0, TNC_HOST_BRIDGE_DEV, TNC_HOST_BRIDGE_FUNC)
+#define TNC_IGD \
+ PCI_BDF(0, TNC_IGD_DEV, TNC_IGD_FUNC)
+#define TNC_SDVO \
+ PCI_BDF(0, TNC_SDVO_DEV, TNC_SDVO_FUNC)
+#define TNC_PCIE0 \
+ PCI_BDF(0, TNC_PCIE0_DEV, TNC_PCIE0_FUNC)
+#define TNC_PCIE1 \
+ PCI_BDF(0, TNC_PCIE1_DEV, TNC_PCIE1_FUNC)
+#define TNC_PCIE2 \
+ PCI_BDF(0, TNC_PCIE2_DEV, TNC_PCIE2_FUNC)
+#define TNC_PCIE3 \
+ PCI_BDF(0, TNC_PCIE3_DEV, TNC_PCIE3_FUNC)
+#define TNC_HDA \
+ PCI_BDF(0, TNC_HDA_DEV, TNC_HDA_FUNC)
+#define TNC_LPC \
+ PCI_BDF(0, TNC_LPC_DEV, TNC_LPC_FUNC)
+
+/* Topcliff IOH PCI Devices */
+#define TCF_PCIE_PORT_DEV 0
+#define TCF_PCIE_PORT_FUNC 0
+
+#define TCF_DEV_0 0
+#define TCF_PKT_HUB_FUNC 0
+#define TCF_GBE_FUNC 1
+#define TCF_GPIO_FUNC 2
+
+#define TCF_DEV_2 2
+#define TCF_USB1_OHCI0_FUNC 0
+#define TCF_USB1_OHCI1_FUNC 1
+#define TCF_USB1_OHCI2_FUNC 2
+#define TCF_USB1_EHCI_FUNC 3
+#define TCF_USB_DEVICE_FUNC 4
+
+#define TCF_DEV_4 4
+#define TCF_SDIO0_FUNC 0
+#define TCF_SDIO1_FUNC 1
+
+#define TCF_DEV_6 6
+#define TCF_SATA_FUNC 0
+
+#define TCF_DEV_8 8
+#define TCF_USB2_OHCI0_FUNC 0
+#define TCF_USB2_OHCI1_FUNC 1
+#define TCF_USB2_OHCI2_FUNC 2
+#define TCF_USB2_EHCI_FUNC 3
+
+#define TCF_DEV_10 10
+#define TCF_DMA1_FUNC 0
+#define TCF_UART0_FUNC 1
+#define TCF_UART1_FUNC 2
+#define TCF_UART2_FUNC 3
+#define TCF_UART3_FUNC 4
+
+#define TCF_DEV_12 12
+#define TCF_DMA2_FUNC 0
+#define TCF_SPI_FUNC 1
+#define TCF_I2C_FUNC 2
+#define TCF_CAN_FUNC 3
+#define TCF_1588_FUNC 4
+
+#endif /* _QUEENSBAY_DEVICE_H_ */
diff --git a/roms/u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h b/roms/u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h
new file mode 100644
index 000000000..979121cde
--- /dev/null
+++ b/roms/u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct fsp_config_data {
+ struct fsp_cfg_common common;
+ struct upd_region fsp_upd;
+};
+
+struct fspinit_rtbuf {
+ struct common_buf common; /* FSP common runtime data structure */
+};
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/roms/u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h b/roms/u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
new file mode 100644
index 000000000..7572fc7e4
--- /dev/null
+++ b/roms/u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * This file is automatically generated. Please do NOT modify !!!
+ */
+
+#ifndef __VPDHEADER_H__
+#define __VPDHEADER_H__
+
+struct __packed upd_region {
+ u64 sign; /* Offset 0x0000 */
+ u64 reserved; /* Offset 0x0008 */
+ u8 dummy[240]; /* Offset 0x0010 */
+ u8 hda_verb_header[12]; /* Offset 0x0100 */
+ u32 hda_verb_length; /* Offset 0x010C */
+ u8 hda_verb_data0[16]; /* Offset 0x0110 */
+ u8 hda_verb_data1[16]; /* Offset 0x0120 */
+ u8 hda_verb_data2[16]; /* Offset 0x0130 */
+ u8 hda_verb_data3[16]; /* Offset 0x0140 */
+ u8 hda_verb_data4[16]; /* Offset 0x0150 */
+ u8 hda_verb_data5[16]; /* Offset 0x0160 */
+ u8 hda_verb_data6[16]; /* Offset 0x0170 */
+ u8 hda_verb_data7[16]; /* Offset 0x0180 */
+ u8 hda_verb_data8[16]; /* Offset 0x0190 */
+ u8 hda_verb_data9[16]; /* Offset 0x01A0 */
+ u8 hda_verb_data10[16]; /* Offset 0x01B0 */
+ u8 hda_verb_data11[16]; /* Offset 0x01C0 */
+ u8 hda_verb_data12[16]; /* Offset 0x01D0 */
+ u8 hda_verb_data13[16]; /* Offset 0x01E0 */
+ u8 hda_verb_pad[47]; /* Offset 0x01F0 */
+ u16 terminator; /* Offset 0x021F */
+};
+
+#define VPD_IMAGE_ID 0x445056574F4E4E4D /* 'MNNOWVPD' */
+
+struct __packed vpd_region {
+ u64 sign; /* Offset 0x0000 */
+ u32 img_rev; /* Offset 0x0008 */
+ u32 upd_offset; /* Offset 0x000C */
+ u8 unused[16]; /* Offset 0x0010 */
+ u32 fsp_res_memlen; /* Offset 0x0020 */
+ u8 disable_pcie1; /* Offset 0x0024 */
+ u8 disable_pcie2; /* Offset 0x0025 */
+ u8 disable_pcie3; /* Offset 0x0026 */
+ u8 enable_azalia; /* Offset 0x0027 */
+ u8 legacy_seg_decode; /* Offset 0x0028 */
+ u8 pcie_port_ioh; /* Offset 0x0029 */
+};
+
+#endif
diff --git a/roms/u-boot/arch/x86/include/asm/arch-queensbay/tnc.h b/roms/u-boot/arch/x86/include/asm/arch-queensbay/tnc.h
new file mode 100644
index 000000000..8d151509a
--- /dev/null
+++ b/roms/u-boot/arch/x86/include/asm/arch-queensbay/tnc.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _X86_ARCH_TNC_H_
+#define _X86_ARCH_TNC_H_
+
+/* IGD Function Disable Register */
+#define IGD_FD 0xc4
+#define FUNC_DISABLE 0x00000001
+
+/* Memory BAR Enable */
+#define MEM_BAR_EN 0x00000001
+
+/* LPC PCI Configuration Registers */
+#define LPC_RCBA 0xf0
+
+/* Root Complex Register Block */
+struct tnc_rcba {
+ u32 rctl;
+ u32 esd;
+ u32 rsvd1[2];
+ u32 hdd;
+ u32 rsvd2;
+ u32 hdba;
+ u32 rsvd3[3129];
+ u32 d31ip;
+ u32 rsvd4[3];
+ u32 d27ip;
+ u32 rsvd5;
+ u32 d02ip;
+ u32 rsvd6;
+ u32 d26ip;
+ u32 d25ip;
+ u32 d24ip;
+ u32 d23ip;
+ u32 d03ip;
+ u32 rsvd7[3];
+ u16 d31ir;
+ u16 rsvd8[3];
+ u16 d27ir;
+ u16 d26ir;
+ u16 d25ir;
+ u16 d24ir;
+ u16 d23ir;
+ u16 rsvd9[7];
+ u16 d02ir;
+ u16 d03ir;
+};
+
+#endif /* _X86_ARCH_TNC_H_ */