diff options
Diffstat (limited to 'roms/u-boot/board/compulab')
53 files changed, 12362 insertions, 0 deletions
diff --git a/roms/u-boot/board/compulab/cl-som-imx7/Kconfig b/roms/u-boot/board/compulab/cl-som-imx7/Kconfig new file mode 100644 index 000000000..6d69cf31f --- /dev/null +++ b/roms/u-boot/board/compulab/cl-som-imx7/Kconfig @@ -0,0 +1,28 @@ +if TARGET_CL_SOM_IMX7 + +config SYS_BOARD + default "cl-som-imx7" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "cl-som-imx7" + +config SYS_MMC_DEV + int + default 0 + +config SYS_USB_DEV + int + default 0 + +config SYS_MMC_IMG_LOAD_PART + int + default 1 + +config SYS_USB_IMG_LOAD_PART + int + default 1 + +endif diff --git a/roms/u-boot/board/compulab/cl-som-imx7/MAINTAINERS b/roms/u-boot/board/compulab/cl-som-imx7/MAINTAINERS new file mode 100644 index 000000000..2b917a5c8 --- /dev/null +++ b/roms/u-boot/board/compulab/cl-som-imx7/MAINTAINERS @@ -0,0 +1,6 @@ +CL-SOM-IMX7 BOARD +M: Uri Mashiach <uri.mashiach@compulab.co.il> +S: Maintained +F: board/compulab/cl-som-imx7 +F: include/configs/cl-som-imx7.h +F: configs/cl-som-imx7_defconfig diff --git a/roms/u-boot/board/compulab/cl-som-imx7/Makefile b/roms/u-boot/board/compulab/cl-som-imx7/Makefile new file mode 100644 index 000000000..8f0e068b7 --- /dev/null +++ b/roms/u-boot/board/compulab/cl-som-imx7/Makefile @@ -0,0 +1,17 @@ +# +# Makefile +# +# (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com +# +# Author: Uri Mashiach <uri.mashiach@compulab.co.il> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mux.o common.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += cl-som-imx7.o +endif diff --git a/roms/u-boot/board/compulab/cl-som-imx7/cl-som-imx7.c b/roms/u-boot/board/compulab/cl-som-imx7/cl-som-imx7.c new file mode 100644 index 000000000..454c93a57 --- /dev/null +++ b/roms/u-boot/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot board functions for CompuLab CL-SOM-iMX7 module + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach <uri.mashiach@compulab.co.il> + */ + +#include <common.h> +#include <env.h> +#include <init.h> +#include <mmc.h> +#include <net.h> +#include <phy.h> +#include <netdev.h> +#include <fsl_esdhc_imx.h> +#include <asm/global_data.h> +#include <linux/delay.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch-mx7/mx7-pins.h> +#include <asm/arch-mx7/sys_proto.h> +#include <asm/arch-mx7/clock.h> +#include "../common/eeprom.h" +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SYS_I2C_MXC + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS) + +#define CL_SOM_IMX7_GPIO_I2C2_SCL IMX_GPIO_NR(1, 6) +#define CL_SOM_IMX7_GPIO_I2C2_SDA IMX_GPIO_NR(1, 7) + +static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = { + .scl = { + .i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL | + MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | + MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = CL_SOM_IMX7_GPIO_I2C2_SCL, + }, + .sda = { + .i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA | + MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 | + MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = CL_SOM_IMX7_GPIO_I2C2_SDA, + }, +}; + +/* + * cl_som_imx7_setup_i2c() - I2C pinmux configuration. + */ +static void cl_som_imx7_setup_i2c(void) +{ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2); +} +#else /* !CONFIG_SYS_I2C_MXC */ +static void cl_som_imx7_setup_i2c(void) {} +#endif /* CONFIG_SYS_I2C_MXC */ + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC_IMX + +#define CL_SOM_IMX7_GPIO_USDHC3_PWR IMX_GPIO_NR(6, 11) + +static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = { + {USDHC1_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc2 USDHC3 (eMMC) + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + cl_som_imx7_usdhc1_pads_set(); + gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd"); + cl_som_imx7_usdhc_cfg[0].sdhc_clk = + mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + cl_som_imx7_usdhc3_emmc_pads_set(); + gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr"); + gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0); + udelay(500); + gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1); + cl_som_imx7_usdhc_cfg[1].sdhc_clk = + mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers " + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif /* CONFIG_FSL_ESDHC_IMX */ + +#ifdef CONFIG_FEC_MXC + +#define CL_SOM_IMX7_ETH1_PHY_NRST IMX_GPIO_NR(1, 4) + +/* + * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration. + */ +static void cl_som_imx7_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* Ar8031 phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= ~(0x1 << 8); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); +} + +int board_phy_config(struct phy_device *phydev) +{ + cl_som_imx7_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +/* + * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment. + * + * @env_var: MAC address environment variable + * @eeprom_bus: I2C bus of the environment EEPROM + * + * @return: 0 on success, < 0 on failure + */ +static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus) +{ + int ret; + unsigned char enetaddr[6]; + + ret = eth_env_get_enetaddr(env_var, enetaddr); + if (ret) + return 0; + + ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus); + if (ret) + return ret; + + ret = is_valid_ethaddr(enetaddr); + if (!ret) + return -1; + + return eth_env_set_enetaddr(env_var, enetaddr); +} + +#define CL_SOM_IMX7_FEC_DEV_ID_PRI 0 + +int board_eth_init(struct bd_info *bis) +{ + /* set Ethernet MAC address environment */ + cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS); + /* Ethernet interface pinmux configuration */ + cl_som_imx7_phy1_rst_pads_set(); + cl_som_imx7_fec1_pads_set(); + /* PHY reset */ + gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst"); + gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0); + mdelay(10); + gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1); + /* MAC initialization */ + return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); +} + +/* + * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration. + * - ENET1 reference clock mode select. + * - ENET1_TX_CLK output driver is disabled when configured for ALT1. + */ +static void cl_som_imx7_setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + set_clk_enet(ENET_125MHZ); +} +#else /* !CONFIG_FEC_MXC */ +static void cl_som_imx7_setup_fec(void) {} +#endif /* CONFIG_FEC_MXC */ + +#ifdef CONFIG_SPI + +static void cl_som_imx7_spi_init(void) +{ + cl_som_imx7_espi1_pads_set(); +} +#else /* !CONFIG_SPI */ +static void cl_som_imx7_spi_init(void) {} +#endif /* CONFIG_SPI */ + +int board_early_init_f(void) +{ + cl_som_imx7_uart1_pads_set(); + cl_som_imx7_usb_otg1_pads_set(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + cl_som_imx7_setup_i2c(); + cl_som_imx7_setup_fec(); + cl_som_imx7_spi_init(); + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE3000"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE3000_DEVICEID, ®); + pmic_reg_read(p, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1); + + return 0; +} +#endif /* CONFIG_POWER */ + +/* + * cl_som_imx7_setup_wdog() - watchdog configuration. + * - Output WDOG_B signal to reset external pmic. + * - Suspend the watchdog timer during low-power modes. + */ +void cl_som_imx7_setup_wdog(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + cl_som_imx7_wdog_pads_set(); + set_wdog_reset(wdog); + /* + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), + * since we use PMIC_PWRON to reset the board. + */ + clrsetbits_le16(&wdog->wcr, 0, 0x10); +} + +int board_late_init(void) +{ + env_set("board_name", "CL-SOM-iMX7"); + cl_som_imx7_setup_wdog(); + return 0; +} + +int checkboard(void) +{ + char *mode; + + if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) + mode = "secure"; + else + mode = "non-secure"; + + printf("Board: CL-SOM-iMX7 in %s mode\n", mode); + + return 0; +} diff --git a/roms/u-boot/board/compulab/cl-som-imx7/common.c b/roms/u-boot/board/compulab/cl-som-imx7/common.c new file mode 100644 index 000000000..40ba0f7a9 --- /dev/null +++ b/roms/u-boot/board/compulab/cl-som-imx7/common.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SPL/U-Boot common functions for CompuLab CL-SOM-iMX7 module + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach <uri.mashiach@compulab.co.il> + */ + +#include <common.h> +#include <fsl_esdhc_imx.h> +#include <asm-generic/gpio.h> +#include "common.h" + +#ifdef CONFIG_SPI + +#define CL_SOM_IMX7_GPIO_SPI_CS IMX_GPIO_NR(4, 19) + +int board_spi_cs_gpio(unsigned int bus, unsigned int cs) +{ + return CL_SOM_IMX7_GPIO_SPI_CS; +} + +#endif /* CONFIG_SPI */ + +#ifdef CONFIG_FSL_ESDHC_IMX + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(CL_SOM_IMX7_GPIO_USDHC1_CD); + break; + case USDHC3_BASE_ADDR: + ret = 1; /* Assume uSDHC3 emmc is always present */ + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ diff --git a/roms/u-boot/board/compulab/cl-som-imx7/common.h b/roms/u-boot/board/compulab/cl-som-imx7/common.h new file mode 100644 index 000000000..bc19867f8 --- /dev/null +++ b/roms/u-boot/board/compulab/cl-som-imx7/common.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * SPL/U-Boot common header file for CompuLab CL-SOM-iMX7 module + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach <uri.mashiach@compulab.co.il> + */ + +#define PADS_SET_PROT(pads_array) void cl_som_imx7_##pads_array##_set(void) + +#ifdef CONFIG_FSL_ESDHC_IMX +#define CL_SOM_IMX7_GPIO_USDHC1_CD IMX_GPIO_NR(5, 0) +PADS_SET_PROT(usdhc1_pads); +#endif /* CONFIG_FSL_ESDHC_IMX */ +PADS_SET_PROT(uart1_pads); +#ifdef CONFIG_SPI +PADS_SET_PROT(espi1_pads); +#endif /* CONFIG_SPI */ + +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_FSL_ESDHC_IMX +PADS_SET_PROT(usdhc3_emmc_pads); +#endif /* CONFIG_FSL_ESDHC_IMX */ +#ifdef CONFIG_FEC_MXC +PADS_SET_PROT(phy1_rst_pads); +PADS_SET_PROT(fec1_pads); +#endif /* CONFIG_FEC_MXC */ +PADS_SET_PROT(usb_otg1_pads); +PADS_SET_PROT(wdog_pads); +#endif /* !CONFIG_SPL_BUILD */ diff --git a/roms/u-boot/board/compulab/cl-som-imx7/mux.c b/roms/u-boot/board/compulab/cl-som-imx7/mux.c new file mode 100644 index 000000000..18f16a487 --- /dev/null +++ b/roms/u-boot/board/compulab/cl-som-imx7/mux.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach <uri.mashiach@compulab.co.il> + */ + +#include <common.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch-mx7/mx7-pins.h> + +#define PADS_SET(pads_array) \ +void cl_som_imx7_##pads_array##_set(void) \ +{ \ + imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array)); \ +} + +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_PUS_PU47KOHM) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +PADS_SET(usdhc1_pads) + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +PADS_SET(uart1_pads) + +#ifdef CONFIG_SPI + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \ + PAD_CTL_DSE_3P3V_32OHM) + +#define GPIO_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \ + PAD_CTL_SRE_SLOW) + +static iomux_v3_cfg_t const espi1_pads[] = { + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +PADS_SET(espi1_pads) + +#endif /* CONFIG_SPI */ + +#ifndef CONFIG_SPL_BUILD + +#ifdef CONFIG_FSL_ESDHC_IMX + +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +PADS_SET(usdhc3_emmc_pads) + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +#ifdef CONFIG_FEC_MXC + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU5KOHM) + +static iomux_v3_cfg_t const phy1_rst_pads[] = { + /* PHY1 RST */ + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +PADS_SET(phy1_rst_pads) + +static iomux_v3_cfg_t const fec1_pads[] = { + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), +}; + +PADS_SET(fec1_pads) + +#endif /* CONFIG_FEC_MXC */ + +static iomux_v3_cfg_t const usb_otg1_pads[] = { + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +PADS_SET(usb_otg1_pads) + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +PADS_SET(wdog_pads) + +#endif /* !CONFIG_SPL_BUILD */ diff --git a/roms/u-boot/board/compulab/cl-som-imx7/spl.c b/roms/u-boot/board/compulab/cl-som-imx7/spl.c new file mode 100644 index 000000000..9c7332b43 --- /dev/null +++ b/roms/u-boot/board/compulab/cl-som-imx7/spl.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SPL board functions for CompuLab CL-SOM-iMX7 module + * + * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com + * + * Author: Uri Mashiach <uri.mashiach@compulab.co.il> + */ + +#include <common.h> +#include <hang.h> +#include <init.h> +#include <spl.h> +#include <fsl_esdhc_imx.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch-mx7/mx7-pins.h> +#include <asm/arch-mx7/clock.h> +#include <asm/arch-mx7/mx7-ddr.h> +#include "common.h" + +#ifdef CONFIG_FSL_ESDHC_IMX + +static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = { + USDHC1_BASE_ADDR, 0, 4}; + +int board_mmc_init(struct bd_info *bis) +{ + cl_som_imx7_usdhc1_pads_set(); + cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg); +} +#endif /* CONFIG_FSL_ESDHC_IMX */ + +static iomux_v3_cfg_t const led_pads[] = { + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM | + PAD_CTL_PUE | PAD_CTL_SRE_SLOW) +}; + +static struct ddrc cl_som_imx7_spl_ddrc_regs_val = { + .init1 = 0x00690000, + .init0 = 0x00020083, + .init3 = 0x09300004, + .init4 = 0x04080000, + .init5 = 0x00100004, + .rankctl = 0x0000033F, + .dramtmg1 = 0x0007020E, + .dramtmg2 = 0x03040407, + .dramtmg3 = 0x00002006, + .dramtmg4 = 0x04020305, + .dramtmg5 = 0x03030202, + .dramtmg8 = 0x00000803, + .zqctl0 = 0x00810021, + .dfitmg0 = 0x02098204, + .dfitmg1 = 0x00030303, + .dfiupd0 = 0x80400003, + .dfiupd1 = 0x00100020, + .dfiupd2 = 0x80100004, + .addrmap4 = 0x00000F0F, + .odtcfg = 0x06000604, + .odtmap = 0x00000001, +}; + +static struct ddrc_mp cl_som_imx7_spl_ddrc_mp_val = { + .pctrl_0 = 0x00000001, +}; + +static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = { + .phy_con0 = 0x17420F40, + .phy_con1 = 0x10210100, + .phy_con4 = 0x00060807, + .mdll_con0 = 0x1010007E, + .drvds_con0 = 0x00000D6E, + .cmd_sdll_con0 = 0x00000010, + .offset_lp_con0 = 0x0000000F, +}; + +struct mx7_calibration cl_som_imx7_spl_calib_param = { + .num_val = 5, + .values = { + 0x0E407304, + 0x0E447304, + 0x0E447306, + 0x0E447304, + 0x0E407304, + }, +}; + +static void cl_som_imx7_spl_dram_cfg_size(u32 ram_size) +{ + switch (ram_size) { + case SZ_256M: + cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01041001; + cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046; + cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; + cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000014; + cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00151515; + cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x03030303; + cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0303; + cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C; + cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404; + break; + case SZ_512M: + cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; + cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046; + cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; + cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000015; + cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00161616; + cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404; + cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0404; + cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C; + cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404; + break; + case SZ_1G: + cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; + cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046; + cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; + cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000016; + cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00171717; + cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404; + cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F040404; + cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A; + cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x02020202; + break; + case SZ_2G: + cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; + cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x0040005E; + cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E110A; + cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000018; + cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00181818; + cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404; + cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x04040404; + cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A; + cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404; + break; + } + + mx7_dram_cfg(&cl_som_imx7_spl_ddrc_regs_val, + &cl_som_imx7_spl_ddrc_mp_val, + &cl_som_imx7_spl_ddr_phy_regs_val, + &cl_som_imx7_spl_calib_param); +} + +static void cl_som_imx7_spl_dram_cfg(void) +{ + ulong ram_size_test, ram_size = 0; + + for (ram_size = SZ_2G; ram_size >= SZ_256M; ram_size >>= 1) { + cl_som_imx7_spl_dram_cfg_size(ram_size); + ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size); + if (ram_size_test == ram_size) + break; + } + + if (ram_size < SZ_256M) { + puts("!!!ERROR!!! DRAM detection failed!!!\n"); + hang(); + } +} + +#ifdef CONFIG_SPL_SPI_SUPPORT + +static void cl_som_imx7_spl_spi_init(void) +{ + cl_som_imx7_espi1_pads_set(); +} +#else /* !CONFIG_SPL_SPI_SUPPORT */ +static void cl_som_imx7_spl_spi_init(void) {} +#endif /* CONFIG_SPL_SPI_SUPPORT */ + +void board_init_f(ulong dummy) +{ + imx_iomux_v3_setup_multiple_pads(led_pads, 1); + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + /* setup GP timer */ + timer_init(); + cl_som_imx7_spl_spi_init(); + cl_som_imx7_uart1_pads_set(); + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + /* DRAM detection */ + cl_som_imx7_spl_dram_cfg(); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void spl_board_init(void) +{ + u32 boot_device = spl_boot_device(); + + if (boot_device == BOOT_DEVICE_SPI) + puts("Booting from SPI flash\n"); + else if (boot_device == BOOT_DEVICE_MMC1) + puts("Booting from SD card\n"); + else + puts("Unknown boot device\n"); +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + switch (spl_boot_list[0]) { + case BOOT_DEVICE_SPI: + spl_boot_list[1] = BOOT_DEVICE_MMC1; + break; + case BOOT_DEVICE_MMC1: + spl_boot_list[1] = BOOT_DEVICE_SPI; + break; + } +} diff --git a/roms/u-boot/board/compulab/cm_fx6/Kconfig b/roms/u-boot/board/compulab/cm_fx6/Kconfig new file mode 100644 index 000000000..59070c5f7 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_fx6/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CM_FX6 + +config SYS_BOARD + default "cm_fx6" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "cm_fx6" + +endif diff --git a/roms/u-boot/board/compulab/cm_fx6/MAINTAINERS b/roms/u-boot/board/compulab/cm_fx6/MAINTAINERS new file mode 100644 index 000000000..5b2623a66 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_fx6/MAINTAINERS @@ -0,0 +1,6 @@ +CM_FX6 BOARD +M: Nikita Kiryanov <nikita@compulab.co.il> +S: Maintained +F: board/compulab/cm_fx6/ +F: include/configs/cm_fx6.h +F: configs/cm_fx6_defconfig diff --git a/roms/u-boot/board/compulab/cm_fx6/Makefile b/roms/u-boot/board/compulab/cm_fx6/Makefile new file mode 100644 index 000000000..e648db26a --- /dev/null +++ b/roms/u-boot/board/compulab/cm_fx6/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> +# +# Authors: Nikita Kiryanov <nikita@compulab.co.il> +ifdef CONFIG_SPL_BUILD +obj-y = common.o spl.o +else +obj-y = common.o cm_fx6.o +endif diff --git a/roms/u-boot/board/compulab/cm_fx6/cm_fx6.c b/roms/u-boot/board/compulab/cm_fx6/cm_fx6.c new file mode 100644 index 000000000..f29b08247 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_fx6/cm_fx6.c @@ -0,0 +1,798 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for Compulab CM-FX6 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov <nikita@compulab.co.il> + */ + +#include <common.h> +#include <ahci.h> +#include <dm.h> +#include <dwc_ahsata.h> +#include <env.h> +#include <fsl_esdhc_imx.h> +#include <init.h> +#include <miiphy.h> +#include <mtd_node.h> +#include <net.h> +#include <netdev.h> +#include <errno.h> +#include <usb.h> +#include <fdt_support.h> +#include <sata.h> +#include <splash.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/global_data.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/mach-imx/sata.h> +#include <asm/mach-imx/video.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <dm/platform_data/serial_mxc.h> +#include <dm/device-internal.h> +#include <jffs2/load_kernel.h> +#include <linux/delay.h> +#include "common.h" +#include "../common/eeprom.h" +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPLASH_SCREEN +static struct splash_location cm_fx6_splash_locations[] = { + { + .name = "sf", + .storage = SPLASH_STORAGE_SF, + .flags = SPLASH_STORAGE_RAW, + .offset = 0x100000, + }, + { + .name = "mmc_fs", + .storage = SPLASH_STORAGE_MMC, + .flags = SPLASH_STORAGE_FS, + .devpart = "2:1", + }, + { + .name = "usb_fs", + .storage = SPLASH_STORAGE_USB, + .flags = SPLASH_STORAGE_FS, + .devpart = "0:1", + }, + { + .name = "sata_fs", + .storage = SPLASH_STORAGE_SATA, + .flags = SPLASH_STORAGE_FS, + .devpart = "0:1", + }, +}; + +int splash_screen_prepare(void) +{ + return splash_source_load(cm_fx6_splash_locations, + ARRAY_SIZE(cm_fx6_splash_locations)); +} +#endif + +#ifdef CONFIG_IMX_HDMI +static void cm_fx6_enable_hdmi(struct display_info_t const *dev) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + imx_setup_hdmi(); + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); + imx_enable_hdmi_phy(); +} + +static struct display_info_t preset_hdmi_1024X768 = { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .enable = cm_fx6_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 40385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED, + } +}; + +static void cm_fx6_setup_display(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + enable_ipu_clock(); + clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); +} + +int board_video_skip(void) +{ + int ret; + struct display_info_t *preset; + char const *panel = env_get("displaytype"); + + if (!panel) /* Also accept panel for backward compatibility */ + panel = env_get("panel"); + + if (!panel) + return -ENOENT; + + if (!strcmp(panel, "HDMI")) + preset = &preset_hdmi_1024X768; + else + return -EINVAL; + + ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt); + if (ret) { + printf("Can't init display %s: %d\n", preset->mode.name, ret); + return ret; + } + + preset->enable(preset); + printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres, + preset->mode.yres); + + return 0; +} +#else +static inline void cm_fx6_setup_display(void) {} +#endif /* CONFIG_VIDEO_IPUV3 */ + +int ipu_displays_init(void) +{ + return board_video_skip(); +} + +#ifdef CONFIG_DWC_AHSATA +static int cm_fx6_issd_gpios[] = { + /* The order of the GPIOs in the array is important! */ + CM_FX6_SATA_LDO_EN, + CM_FX6_SATA_PHY_SLP, + CM_FX6_SATA_NRSTDLY, + CM_FX6_SATA_PWREN, + CM_FX6_SATA_NSTANDBY1, + CM_FX6_SATA_NSTANDBY2, +}; + +static void cm_fx6_sata_power(int on) +{ + int i; + + if (!on) { /* tell the iSSD that the power will be removed */ + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1); + mdelay(10); + } + + for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { + gpio_direction_output(cm_fx6_issd_gpios[i], on); + udelay(100); + } + + if (!on) /* for compatibility lower the power loss interrupt */ + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); +} + +static iomux_v3_cfg_t const sata_pads[] = { + /* SATA PWR */ + IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* SATA CTRL */ + IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static int cm_fx6_setup_issd(void) +{ + int ret, i; + + SETUP_IOMUX_PADS(sata_pads); + + for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { + ret = gpio_request(cm_fx6_issd_gpios[i], "sata"); + if (ret) + return ret; + } + + ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int"); + if (ret) + return ret; + + return 0; +} + +#define CM_FX6_SATA_INIT_RETRIES 10 + +#else +static int cm_fx6_setup_issd(void) { return 0; } +#endif + +#ifdef CONFIG_SYS_I2C_MXC +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +I2C_PADS(i2c0_pads, + PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(3, 21), + PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(3, 28)); + +I2C_PADS(i2c1_pads, + PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(4, 12), + PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(4, 13)); + +I2C_PADS(i2c2_pads, + PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(1, 3), + PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), + PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX_GPIO_NR(1, 6)); + + +static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads) +{ + int ret; + + ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads); + if (ret) + printf("Warning: I2C%d setup failed: %d\n", busnum, ret); + + return ret; +} + +static int cm_fx6_setup_i2c(void) +{ + int ret = 0, err; + + /* i2c<x>_pads are wierd macro variables; we can't use an array */ + err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads)); + if (err) + ret = err; + err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads)); + if (err) + ret = err; + err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads)); + if (err) + ret = err; + + return ret; +} +#else +static int cm_fx6_setup_i2c(void) { return 0; } +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS | PAD_CTL_SRE_SLOW) +#define MX6_USBNC_BASEADDR 0x2184800 +#define USBNC_USB_H1_PWR_POL (1 << 9) + +static int cm_fx6_setup_usb_host(void) +{ + int err; + + err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); + if (err) + return err; + + SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)); + SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); + + return 0; +} + +static int cm_fx6_setup_usb_otg(void) +{ + int err; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); + if (err) { + printf("USB OTG pwr gpio request failed: %d\n", err); + return err; + } + + SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)); + SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID | + MUX_PAD_CTRL(WEAK_PULLDOWN)); + clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK); + /* disable ext. charger detect, or it'll affect signal quality at dp. */ + return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); +} + +int board_usb_phy_mode(int port) +{ + return USB_INIT_HOST; +} + +int board_ehci_hcd_init(int port) +{ + int ret; + u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4); + + /* Only 1 host controller in use. port 0 is OTG & needs no attention */ + if (port != 1) + return 0; + + /* Set PWR polarity to match power switch's enable polarity */ + setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL); + ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0); + if (ret) + return ret; + + udelay(10); + ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1); + if (ret) + return ret; + + mdelay(1); + + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port == 0) + return gpio_direction_output(SB_FX6_USB_OTG_PWR, on); + + return 0; +} +#else +static int cm_fx6_setup_usb_otg(void) { return 0; } +static int cm_fx6_setup_usb_host(void) { return 0; } +#endif + +#ifdef CONFIG_FEC_MXC +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +static int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* Ar8031 phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= ~(0x1 << 8); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} + +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), +}; + +static int handle_mac_address(char *env_var, uint eeprom_bus) +{ + unsigned char enetaddr[6]; + int rc; + + rc = eth_env_get_enetaddr(env_var, enetaddr); + if (rc) + return 0; + + rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus); + if (rc) + return rc; + + if (!is_valid_ethaddr(enetaddr)) + return -1; + + return eth_env_set_enetaddr(env_var, enetaddr); +} + +#define SB_FX6_I2C_EEPROM_BUS 0 +#define NO_MAC_ADDR "No MAC address found for %s\n" +int board_eth_init(struct bd_info *bis) +{ + int err; + + if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS)) + printf(NO_MAC_ADDR, "primary NIC"); + + if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS)) + printf(NO_MAC_ADDR, "secondary NIC"); + + SETUP_IOMUX_PADS(enet_pads); + /* phy reset */ + err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst"); + if (err) + printf("Etnernet NRST gpio request failed: %d\n", err); + gpio_direction_output(CM_FX6_ENET_NRST, 0); + udelay(500); + gpio_set_value(CM_FX6_ENET_NRST, 1); + enable_enet_clk(1); + return cpu_eth_init(bis); +} +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void cm_fx6_setup_gpmi_nand(void) +{ + SETUP_IOMUX_PADS(nand_pads); + /* Enable clock roots */ + enable_usdhc_clk(1, 3); + enable_usdhc_clk(1, 4); + + setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(0)); +} +#else +static void cm_fx6_setup_gpmi_nand(void) {} +#endif + +#ifdef CONFIG_MXC_SPI +int cm_fx6_setup_ecspi(void) +{ + cm_fx6_set_ecspi_iomux(); + return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0"); +} +#else +int cm_fx6_setup_ecspi(void) { return 0; } +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +#define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/" + +static const struct node_info nodes[] = { + /* + * Both entries target the same flash chip. The st,m25p compatible + * is used in the vendor device trees, while upstream uses (the + * documented) jedec,spi-nor compatible. + */ + { "st,m25p", MTD_DEV_TYPE_NOR, }, + { "jedec,spi-nor", MTD_DEV_TYPE_NOR, }, +}; + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u32 baseboard_rev; + int nodeoffset; + uint8_t enetaddr[6]; + char baseboard_name[16]; + int err; + + fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */ + + /* MAC addr */ + if (eth_env_get_enetaddr("ethaddr", enetaddr)) { + fdt_find_and_setprop(blob, + "/soc/aips-bus@02100000/ethernet@02188000", + "local-mac-address", enetaddr, 6, 1); + } + + if (eth_env_get_enetaddr("eth1addr", enetaddr)) { + fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address", + enetaddr, 6, 1); + } + + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + + baseboard_rev = cl_eeprom_get_board_rev(0); + err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0); + if (err || baseboard_rev == 0) + return 0; /* Assume not an early revision SB-FX6m baseboard */ + + if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) { + nodeoffset = fdt_path_offset(blob, USDHC3_PATH); + fdt_delprop(blob, nodeoffset, "cd-gpios"); + fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd", + NULL, 0, 1); + fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend", + NULL, 0, 1); + } + + return 0; +} +#endif + +int board_init(void) +{ + int ret; + + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + cm_fx6_setup_gpmi_nand(); + + ret = cm_fx6_setup_ecspi(); + if (ret) + printf("Warning: ECSPI setup failed: %d\n", ret); + + ret = cm_fx6_setup_usb_otg(); + if (ret) + printf("Warning: USB OTG setup failed: %d\n", ret); + + ret = cm_fx6_setup_usb_host(); + if (ret) + printf("Warning: USB host setup failed: %d\n", ret); + + /* + * cm-fx6 may have iSSD not assembled and in this case it has + * bypasses for a (m)SATA socket on the baseboard. The socketed + * device is not controlled by those GPIOs. So just print a warning + * if the setup fails. + */ + ret = cm_fx6_setup_issd(); + if (ret) + printf("Warning: iSSD setup failed: %d\n", ret); + + /* Warn on failure but do not abort boot */ + ret = cm_fx6_setup_i2c(); + if (ret) + printf("Warning: I2C setup failed: %d\n", ret); + + cm_fx6_setup_display(); + + /* This should be done in the MMC driver when MX6 has a clock driver */ +#ifdef CONFIG_FSL_ESDHC_IMX + if (IS_ENABLED(CONFIG_BLK)) { + int i; + + cm_fx6_set_usdhc_iomux(); + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) + enable_usdhc_clk(1, i); + } +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + char baseboard_name[16]; + int err; + + if (is_mx6dq()) + env_set("board_rev", "MX6Q"); + else if (is_mx6dl()) + env_set("board_rev", "MX6DL"); + + err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0); + if (err) + return 0; + + if (!strncmp("SB-FX6m", baseboard_name, 7)) + env_set("board_name", "Utilite"); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: CM-FX6\n"); + return 0; +} + +int misc_init_r(void) +{ + cl_print_pcb_info(); + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + + switch (gd->ram_size) { + case 0x10000000: /* DDR_16BIT_256MB */ + gd->bd->bi_dram[0].size = 0x10000000; + gd->bd->bi_dram[1].size = 0; + break; + case 0x20000000: /* DDR_32BIT_512MB */ + gd->bd->bi_dram[0].size = 0x20000000; + gd->bd->bi_dram[1].size = 0; + break; + case 0x40000000: + if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ + gd->bd->bi_dram[0].size = 0x20000000; + gd->bd->bi_dram[1].size = 0x20000000; + } else { /* DDR_64BIT_1GB */ + gd->bd->bi_dram[0].size = 0x40000000; + gd->bd->bi_dram[1].size = 0; + } + break; + case 0x80000000: /* DDR_64BIT_2GB */ + gd->bd->bi_dram[0].size = 0x40000000; + gd->bd->bi_dram[1].size = 0x40000000; + break; + case 0xEFF00000: /* DDR_64BIT_4GB */ + gd->bd->bi_dram[0].size = 0x70000000; + gd->bd->bi_dram[1].size = 0x7FF00000; + break; + } + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + switch (gd->ram_size) { + case 0x10000000: + case 0x20000000: + case 0x40000000: + case 0x80000000: + break; + case 0xF0000000: + gd->ram_size -= 0x100000; + break; + default: + printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size); + return -1; + } + + return 0; +} + +u32 get_board_rev(void) +{ + return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS); +} + +static struct mxc_serial_plat cm_fx6_mxc_serial_plat = { + .reg = (struct mxc_uart *)UART4_BASE, +}; + +U_BOOT_DRVINFO(cm_fx6_serial) = { + .name = "serial_mxc", + .plat = &cm_fx6_mxc_serial_plat, +}; + +#if CONFIG_IS_ENABLED(AHCI) +static int sata_imx_probe(struct udevice *dev) +{ + int i, err; + + /* Make sure this gpio has logical 0 value */ + gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); + udelay(100); + cm_fx6_sata_power(1); + + for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) { + err = setup_sata(); + if (err) { + printf("SATA setup failed: %d\n", err); + return err; + } + + udelay(100); + + err = dwc_ahsata_probe(dev); + if (!err) + break; + + /* There is no device on the SATA port */ + if (sata_dm_port_status(0, 0) == 0) + break; + + /* There's a device, but link not established. Retry */ + device_remove(dev, DM_REMOVE_NORMAL); + } + + return 0; +} + +static int sata_imx_remove(struct udevice *dev) +{ + cm_fx6_sata_power(0); + mdelay(250); + + return 0; +} + +struct ahci_ops sata_imx_ops = { + .port_status = dwc_ahsata_port_status, + .reset = dwc_ahsata_bus_reset, + .scan = dwc_ahsata_scan, +}; + +static const struct udevice_id sata_imx_ids[] = { + { .compatible = "fsl,imx6q-ahci" }, + { } +}; + +U_BOOT_DRIVER(sata_imx) = { + .name = "dwc_ahci", + .id = UCLASS_AHCI, + .of_match = sata_imx_ids, + .ops = &sata_imx_ops, + .probe = sata_imx_probe, + .remove = sata_imx_remove, /* reset bus to stop it */ +}; +#endif /* AHCI */ diff --git a/roms/u-boot/board/compulab/cm_fx6/common.c b/roms/u-boot/board/compulab/cm_fx6/common.c new file mode 100644 index 000000000..ed8c7a3bf --- /dev/null +++ b/roms/u-boot/board/compulab/cm_fx6/common.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Code used by both U-Boot and SPL for Compulab CM-FX6 + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov <nikita@compulab.co.il> + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-imx/spi.h> +#include <fsl_esdhc_imx.h> +#include "common.h" + +#ifdef CONFIG_FSL_ESDHC_IMX +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc_pads[] = { + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +void cm_fx6_set_usdhc_iomux(void) +{ + SETUP_IOMUX_PADS(usdhc_pads); +} + +/* CINS bit doesn't work, so always try to access the MMC card */ +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} +#endif + +#ifdef CONFIG_MXC_SPI +#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +static iomux_v3_cfg_t const ecspi_pads[] = { + IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)), +}; + +void cm_fx6_set_ecspi_iomux(void) +{ + SETUP_IOMUX_PADS(ecspi_pads); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1; +} +#endif diff --git a/roms/u-boot/board/compulab/cm_fx6/common.h b/roms/u-boot/board/compulab/cm_fx6/common.h new file mode 100644 index 000000000..debef1588 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_fx6/common.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov <nikita@compulab.co.il> + */ + +#include <asm/arch/mx6-pins.h> +#include <asm/arch/clock.h> + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define CM_FX6_ECSPI_BUS0_CS0 IMX_GPIO_NR(2, 30) +#define CM_FX6_GREEN_LED IMX_GPIO_NR(2, 31) +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) +#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8) +#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8) +#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8) +#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define CM_FX6_SATA_PWREN IMX_GPIO_NR(1, 28) +#define CM_FX6_SATA_VDDC_CTRL IMX_GPIO_NR(1, 30) +#define CM_FX6_SATA_LDO_EN IMX_GPIO_NR(2, 16) +#define CM_FX6_SATA_NSTANDBY1 IMX_GPIO_NR(3, 20) +#define CM_FX6_SATA_PHY_SLP IMX_GPIO_NR(3, 23) +#define CM_FX6_SATA_STBY_REQ IMX_GPIO_NR(3, 29) +#define CM_FX6_SATA_NSTANDBY2 IMX_GPIO_NR(5, 2) +#define CM_FX6_SATA_NRSTDLY IMX_GPIO_NR(6, 6) +#define CM_FX6_SATA_PWLOSS_INT IMX_GPIO_NR(6, 31) + + +void cm_fx6_set_usdhc_iomux(void); +void cm_fx6_set_ecspi_iomux(void); diff --git a/roms/u-boot/board/compulab/cm_fx6/spl.c b/roms/u-boot/board/compulab/cm_fx6/spl.c new file mode 100644 index 000000000..c3c816181 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_fx6/spl.c @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SPL specific code for Compulab CM-FX6 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Nikita Kiryanov <nikita@compulab.co.il> + */ + +#include <common.h> +#include <clock_legacy.h> +#include <hang.h> +#include <init.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/mach-imx/iomux-v3.h> +#include <fsl_esdhc_imx.h> +#include <linux/delay.h> +#include "common.h" + +enum ddr_config { + DDR_16BIT_256MB, + DDR_32BIT_512MB, + DDR_32BIT_1GB, + DDR_64BIT_1GB, + DDR_64BIT_2GB, + DDR_64BIT_4GB, + DDR_UNKNOWN, +}; + +/* + * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to + * Freescale QRM, but this is exactly the value used by the automatic + * calibration script and it works also in all our tests, so we leave + * it as is at this point. + */ +#define CM_FX6_DDR_IOMUX_CFG \ + .dram_sdqs0 = 0x00000038, \ + .dram_sdqs1 = 0x00000038, \ + .dram_sdqs2 = 0x00000038, \ + .dram_sdqs3 = 0x00000038, \ + .dram_sdqs4 = 0x00000038, \ + .dram_sdqs5 = 0x00000038, \ + .dram_sdqs6 = 0x00000038, \ + .dram_sdqs7 = 0x00000038, \ + .dram_dqm0 = 0x00000038, \ + .dram_dqm1 = 0x00000038, \ + .dram_dqm2 = 0x00000038, \ + .dram_dqm3 = 0x00000038, \ + .dram_dqm4 = 0x00000038, \ + .dram_dqm5 = 0x00000038, \ + .dram_dqm6 = 0x00000038, \ + .dram_dqm7 = 0x00000038, \ + .dram_cas = 0x00000038, \ + .dram_ras = 0x00000038, \ + .dram_sdclk_0 = 0x00000038, \ + .dram_sdclk_1 = 0x00000038, \ + .dram_sdcke0 = 0x00003000, \ + .dram_sdcke1 = 0x00003000, \ + .dram_reset = 0x00000038, \ + .dram_sdba2 = 0x00000000, \ + .dram_sdodt0 = 0x00000038, \ + .dram_sdodt1 = 0x00000038, + +#define CM_FX6_GPR_IOMUX_CFG \ + .grp_b0ds = 0x00000038, \ + .grp_b1ds = 0x00000038, \ + .grp_b2ds = 0x00000038, \ + .grp_b3ds = 0x00000038, \ + .grp_b4ds = 0x00000038, \ + .grp_b5ds = 0x00000038, \ + .grp_b6ds = 0x00000038, \ + .grp_b7ds = 0x00000038, \ + .grp_addds = 0x00000038, \ + .grp_ddrmode_ctl = 0x00020000, \ + .grp_ddrpke = 0x00000000, \ + .grp_ddrmode = 0x00020000, \ + .grp_ctlds = 0x00000038, \ + .grp_ddr_type = 0x000C0000, + +static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG }; +static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG }; +static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG }; +static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG }; + +static struct mx6_mmdc_calibration cm_fx6_calib_s = { + .p0_mpwldectrl0 = 0x005B0061, + .p0_mpwldectrl1 = 0x004F0055, + .p0_mpdgctrl0 = 0x0314030C, + .p0_mpdgctrl1 = 0x025C0268, + .p0_mprddlctl = 0x42464646, + .p0_mpwrdlctl = 0x36322C34, +}; + +static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = { + .cs1_mirror = 1, + .cs_density = 16, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 1, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = { + .mem_speed = 800, + .density = 4, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1800, + .trcmin = 5200, + .trasmin = 3600, + .SRT = 0, +}; + +static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset) +{ + if (reset) + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; + + switch (dram_config) { + case DDR_16BIT_256MB: + cm_fx6_sysinfo_s.dsize = 0; + cm_fx6_sysinfo_s.ncs = 1; + break; + case DDR_32BIT_512MB: + cm_fx6_sysinfo_s.dsize = 1; + cm_fx6_sysinfo_s.ncs = 1; + break; + case DDR_32BIT_1GB: + cm_fx6_sysinfo_s.dsize = 1; + cm_fx6_sysinfo_s.ncs = 2; + break; + default: + puts("Tried to setup invalid DDR configuration\n"); + hang(); + } + + mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s); + udelay(100); +} + +static struct mx6_mmdc_calibration cm_fx6_calib_q = { + .p0_mpwldectrl0 = 0x00630068, + .p0_mpwldectrl1 = 0x0068005D, + .p0_mpdgctrl0 = 0x04140428, + .p0_mpdgctrl1 = 0x037C037C, + .p0_mprddlctl = 0x3C30303A, + .p0_mpwrdlctl = 0x3A344038, + .p1_mpwldectrl0 = 0x0035004C, + .p1_mpwldectrl1 = 0x00170026, + .p1_mpdgctrl0 = 0x0374037C, + .p1_mpdgctrl1 = 0x0350032C, + .p1_mprddlctl = 0x30322A3C, + .p1_mpwrdlctl = 0x48304A3E, +}; + +static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = { + .cs_density = 16, + .cs1_mirror = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 1, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ +}; + +static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = { + .mem_speed = 1066, + .density = 4, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1324, + .trcmin = 59500, + .trasmin = 9750, + .SRT = 0, +}; + +static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset) +{ + if (reset) + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; + + cm_fx6_ddr3_cfg_q.rowaddr = 14; + switch (dram_config) { + case DDR_16BIT_256MB: + cm_fx6_sysinfo_q.dsize = 0; + cm_fx6_sysinfo_q.ncs = 1; + break; + case DDR_32BIT_512MB: + cm_fx6_sysinfo_q.dsize = 1; + cm_fx6_sysinfo_q.ncs = 1; + break; + case DDR_64BIT_1GB: + cm_fx6_sysinfo_q.dsize = 2; + cm_fx6_sysinfo_q.ncs = 1; + break; + case DDR_64BIT_2GB: + cm_fx6_sysinfo_q.dsize = 2; + cm_fx6_sysinfo_q.ncs = 2; + break; + case DDR_64BIT_4GB: + cm_fx6_sysinfo_q.dsize = 2; + cm_fx6_sysinfo_q.ncs = 2; + cm_fx6_ddr3_cfg_q.rowaddr = 15; + break; + default: + puts("Tried to setup invalid DDR configuration\n"); + hang(); + } + + mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q); + udelay(100); +} + +static int cm_fx6_spl_dram_init(void) +{ + unsigned long bank1_size, bank2_size; + + switch (get_cpu_type()) { + case MXC_CPU_MX6SOLO: + mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s); + + spl_mx6s_dram_init(DDR_32BIT_1GB, false); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000); + if (bank1_size == 0x20000000) { + if (bank2_size == 0x20000000) + return 0; + + spl_mx6s_dram_init(DDR_32BIT_512MB, true); + return 0; + } + + spl_mx6s_dram_init(DDR_16BIT_256MB, true); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x10000000) + return 0; + + break; + case MXC_CPU_MX6D: + case MXC_CPU_MX6Q: + mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q); + + spl_mx6q_dram_init(DDR_64BIT_4GB, false); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x80000000) + return 0; + + if (bank1_size == 0x40000000) { + bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, + 0x80000000); + if (bank2_size == 0x40000000) { + /* Don't do a full reset here */ + spl_mx6q_dram_init(DDR_64BIT_2GB, false); + } else { + spl_mx6q_dram_init(DDR_64BIT_1GB, true); + } + + return 0; + } + + spl_mx6q_dram_init(DDR_32BIT_512MB, true); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x20000000) + return 0; + + spl_mx6q_dram_init(DDR_16BIT_256MB, true); + bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); + if (bank1_size == 0x10000000) + return 0; + + break; + } + + return -1; +} + +static iomux_v3_cfg_t const uart4_pads[] = { + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static void cm_fx6_setup_uart(void) +{ + SETUP_IOMUX_PADS(uart4_pads); + enable_uart_clk(1); +} + +#ifdef CONFIG_SPL_SPI_SUPPORT +static void cm_fx6_setup_ecspi(void) +{ + cm_fx6_set_ecspi_iomux(); + enable_spi_clk(1, 0); +} +#else +static void cm_fx6_setup_ecspi(void) { } +#endif + +void board_init_f(ulong dummy) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* + * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot + * initializes DMA very early (before all board code), so the only + * opportunity we have to initialize APBHDMA clocks is in SPL. + */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); + enable_usdhc_clk(1, 2); + + arch_cpu_init(); + timer_init(); + cm_fx6_setup_ecspi(); + cm_fx6_setup_uart(); + get_clocks(); + preloader_console_init(); + gpio_direction_output(CM_FX6_GREEN_LED, 1); + if (cm_fx6_spl_dram_init()) { + puts("!!!ERROR!!! DRAM detection failed!!!\n"); + hang(); + } +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + switch (spl_boot_list[0]) { + case BOOT_DEVICE_SPI: + spl_boot_list[1] = BOOT_DEVICE_MMC1; + break; + case BOOT_DEVICE_MMC1: + spl_boot_list[1] = BOOT_DEVICE_SPI; + break; + } +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +static struct fsl_esdhc_cfg usdhc_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 4, +}; + +int board_mmc_init(struct bd_info *bis) +{ + cm_fx6_set_usdhc_iomux(); + + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} +#endif diff --git a/roms/u-boot/board/compulab/cm_t335/Kconfig b/roms/u-boot/board/compulab/cm_t335/Kconfig new file mode 100644 index 000000000..683efde76 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t335/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CM_T335 + +config SYS_BOARD + default "cm_t335" + +config SYS_VENDOR + default "compulab" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "cm_t335" + +endif diff --git a/roms/u-boot/board/compulab/cm_t335/MAINTAINERS b/roms/u-boot/board/compulab/cm_t335/MAINTAINERS new file mode 100644 index 000000000..5fb922c68 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t335/MAINTAINERS @@ -0,0 +1,6 @@ +CM_T335 BOARD +M: Igor Grinberg <grinberg@compulab.co.il> +S: Maintained +F: board/compulab/cm_t335/ +F: include/configs/cm_t335.h +F: configs/cm_t335_defconfig diff --git a/roms/u-boot/board/compulab/cm_t335/Makefile b/roms/u-boot/board/compulab/cm_t335/Makefile new file mode 100644 index 000000000..34f671311 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t335/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/ +# +# Author: Ilya Ledvich <ilya@compulab.co.il> + +obj-y += cm_t335.o +obj-$(CONFIG_SPL_BUILD) += mux.o spl.o diff --git a/roms/u-boot/board/compulab/cm_t335/cm_t335.c b/roms/u-boot/board/compulab/cm_t335/cm_t335.c new file mode 100644 index 000000000..1d4a3acee --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t335/cm_t335.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for Compulab CM-T335 board + * + * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ + * + * Author: Ilya Ledvich <ilya@compulab.co.il> + */ + +#include <common.h> +#include <env.h> +#include <errno.h> +#include <miiphy.h> +#include <net.h> +#include <status_led.h> +#include <cpsw.h> +#include <asm/global_data.h> +#include <linux/delay.h> + +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware_am33xx.h> +#include <asm/io.h> +#include <asm/gpio.h> + +#include "../common/eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + gpmc_init(); + +#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) + status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF); +#endif + return 0; +} + +#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slave = { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RGMII, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = &cpsw_slave, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +/* PHY reset GPIO */ +#define GPIO_PHY_RST GPIO_PIN(3, 7) + +static void board_phy_init(void) +{ + gpio_request(GPIO_PHY_RST, "phy_rst"); + gpio_direction_output(GPIO_PHY_RST, 0); + mdelay(2); + gpio_set_value(GPIO_PHY_RST, 1); + mdelay(2); +} + +static void get_efuse_mac_addr(uchar *enetaddr) +{ + uint32_t mac_hi, mac_lo; + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + enetaddr[0] = mac_hi & 0xFF; + enetaddr[1] = (mac_hi & 0xFF00) >> 8; + enetaddr[2] = (mac_hi & 0xFF0000) >> 16; + enetaddr[3] = (mac_hi & 0xFF000000) >> 24; + enetaddr[4] = mac_lo & 0xFF; + enetaddr[5] = (mac_lo & 0xFF00) >> 8; +} + +/* + * Routine: handle_mac_address + * Description: prepare MAC address for on-board Ethernet. + */ +static int handle_mac_address(void) +{ + uchar enetaddr[6]; + int rv; + + rv = eth_env_get_enetaddr("ethaddr", enetaddr); + if (rv) + return 0; + + rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); + if (rv) + get_efuse_mac_addr(enetaddr); + + if (!is_valid_ethaddr(enetaddr)) + return -1; + + return eth_env_set_enetaddr("ethaddr", enetaddr); +} + +#define AR8051_PHY_DEBUG_ADDR_REG 0x1d +#define AR8051_PHY_DEBUG_DATA_REG 0x1e +#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 +#define AR8051_RGMII_TX_CLK_DLY 0x100 + +int board_eth_init(struct bd_info *bis) +{ + int rv, n = 0; + const char *devname; + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + + rv = handle_mac_address(); + if (rv) + printf("No MAC address found!\n"); + + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); + + board_phy_init(); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + + /* + * CPSW RGMII Internal Delay Mode is not supported in all PVT + * operating points. So we must set the TX clock delay feature + * in the AR8051 PHY. Since we only support a single ethernet + * device, we only do this for the first instance. + */ + devname = miiphy_get_current_dev(); + + miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, + AR8051_DEBUG_RGMII_CLK_DLY_REG); + miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, + AR8051_RGMII_TX_CLK_DLY); + return n; +} +#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */ diff --git a/roms/u-boot/board/compulab/cm_t335/mux.c b/roms/u-boot/board/compulab/cm_t335/mux.c new file mode 100644 index 000000000..1c326bd1b --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t335/mux.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Pinmux configuration for Compulab CM-T335 board + * + * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ + * + * Author: Ilya Ledvich <ilya@compulab.co.il> + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, + {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +static struct module_pin_mux eth_phy_rst_pin_mux[] = { + {OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */ + {-1}, +}; + +static struct module_pin_mux status_led_pin_mux[] = { + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */ + {-1}, +}; + +void set_uart_mux_conf(void) +{ + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(uart1_pin_mux); +} + +void set_mux_conf_regs(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(eth_phy_rst_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(status_led_pin_mux); +} diff --git a/roms/u-boot/board/compulab/cm_t335/spl.c b/roms/u-boot/board/compulab/cm_t335/spl.c new file mode 100644 index 000000000..33264dfa7 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t335/spl.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SPL specific code for Compulab CM-T335 board + * + * Board functions for Compulab CM-T335 board + * + * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ + * + * Author: Ilya Ledvich <ilya@compulab.co.il> + */ + +#include <common.h> +#include <cpu_func.h> +#include <errno.h> +#include <init.h> +#include <log.h> + +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/clocks_am33xx.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware_am33xx.h> +#include <linux/sizes.h> + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, +}; + +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41J128MJT125_RD_DQS, + .datawdsratio0 = MT41J128MJT125_WR_DQS, + .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, + .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41J128MJT125_RATIO, + .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, + + .cmd1csratio = MT41J128MJT125_RATIO, + .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, + + .cmd2csratio = MT41J128MJT125_RATIO, + .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41J128MJT125_EMIF_SDCFG, + .ref_ctrl = MT41J128MJT125_EMIF_SDREF, + .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, + .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, + .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, + .zq_config = MT41J128MJT125_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +const struct dpll_params dpll_ddr = { +/* M N M2 M3 M4 M5 M6 */ + 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +static void probe_sdram_size(long size) +{ + switch (size) { + case SZ_512M: + ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG; + break; + case SZ_256M: + ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG; + break; + case SZ_128M: + ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG; + break; + default: + puts("Failed configuring DRAM, resetting...\n\n"); + reset_cpu(); + } + debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); + config_ddr(303, &ioregs, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} + +void sdram_init(void) +{ + long size = SZ_1G; + + do { + size = size / 2; + probe_sdram_size(size); + } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size); + + return; +} diff --git a/roms/u-boot/board/compulab/cm_t335/u-boot.lds b/roms/u-boot/board/compulab/cm_t335/u-boot.lds new file mode 100644 index 000000000..b00e466d5 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t335/u-boot.lds @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + CPUDIR/start.o (.text*) + board/compulab/cm_t335/built-in.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .hash : { *(.hash*) } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } +} diff --git a/roms/u-boot/board/compulab/cm_t43/Kconfig b/roms/u-boot/board/compulab/cm_t43/Kconfig new file mode 100644 index 000000000..a19188975 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t43/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CM_T43 + +config SYS_BOARD + default "cm_t43" + +config SYS_VENDOR + default "compulab" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "cm_t43" + +endif diff --git a/roms/u-boot/board/compulab/cm_t43/MAINTAINERS b/roms/u-boot/board/compulab/cm_t43/MAINTAINERS new file mode 100644 index 000000000..951c370dd --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t43/MAINTAINERS @@ -0,0 +1,6 @@ +CM_T43 BOARD +M: Nikita Kiryanov <nikita@compulab.co.il> +S: Maintained +F: board/compulab/cm_t43/ +F: include/configs/cm_t43.h +F: configs/cm_t43_defconfig diff --git a/roms/u-boot/board/compulab/cm_t43/Makefile b/roms/u-boot/board/compulab/cm_t43/Makefile new file mode 100644 index 000000000..6fa231a04 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t43/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile +# +# Copyright (C) 2015 Compulab, Ltd. + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o mux.o +else +obj-y += cm_t43.o mux.o +endif diff --git a/roms/u-boot/board/compulab/cm_t43/board.h b/roms/u-boot/board/compulab/cm_t43/board.h new file mode 100644 index 000000000..fcacd2bc0 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t43/board.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Compulab, Ltd. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +void set_i2c_pin_mux(void); +void set_mdio_pin_mux(void); +void set_rgmii_pin_mux(void); +#endif diff --git a/roms/u-boot/board/compulab/cm_t43/cm_t43.c b/roms/u-boot/board/compulab/cm_t43/cm_t43.c new file mode 100644 index 000000000..efdade155 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t43/cm_t43.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Compulab, Ltd. + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <net.h> +#include <asm/global_data.h> +#include <asm/gpio.h> +#include <asm/arch/sys_proto.h> +#include <asm/emif.h> +#include <linux/delay.h> +#include <power/pmic.h> +#include <power/tps65218.h> +#include "board.h" +#include <usb.h> +#include <asm/omap_common.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + uchar tps_status = 0; + + power_tps65218_init(I2C_PMIC); + p = pmic_get("TPS65218_PMIC"); + if (p && !pmic_probe(p)) { + puts("PMIC: TPS65218\n"); + /* We don't care if fseal is locked, but we do need it set */ + tps65218_lock_fseal(); + tps65218_reg_read(TPS65218_STATUS, &tps_status); + if (!(tps_status & TPS65218_FSEAL)) + printf("WARNING: RTC not backed by battery!\n"); + } + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + set_i2c_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_probe(TPS65218_CHIP_PM); + + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + enable_usb_clocks(index); + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + disable_usb_clocks(index); + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW + +static void cpsw_control(int enabled) +{ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#define GPIO_PHY1_RST 170 +#define GPIO_PHY2_RST 168 + +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} + +static void board_phy_init(void) +{ + set_mdio_pin_mux(); + writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */ + writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */ + writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */ + + /* For revision A */ + writel(0x2000009, 0x44df2e6c); + writel(0x38a, 0x44df2e70); + + mdelay(10); + + gpio_request(GPIO_PHY1_RST, "phy1_rst"); + gpio_request(GPIO_PHY2_RST, "phy2_rst"); + gpio_direction_output(GPIO_PHY1_RST, 0); + gpio_direction_output(GPIO_PHY2_RST, 0); + mdelay(2); + + gpio_set_value(GPIO_PHY1_RST, 1); + gpio_set_value(GPIO_PHY2_RST, 1); + mdelay(2); +} + +int board_eth_init(struct bd_info *bis) +{ + int rv; + + set_rgmii_pin_mux(); + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); + board_phy_init(); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + + return rv; +} +#endif diff --git a/roms/u-boot/board/compulab/cm_t43/mux.c b/roms/u-boot/board/compulab/cm_t43/mux.c new file mode 100644 index 000000000..778ea05e8 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t43/mux.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Compulab, Ltd. + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include "board.h" + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, + {OFFSET(mii1_txd3), MODE(2)}, + {OFFSET(mii1_txd2), MODE(2)}, + {OFFSET(mii1_txd1), MODE(2)}, + {OFFSET(mii1_txd0), MODE(2)}, + {OFFSET(mii1_txclk), MODE(2)}, + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* txen */ + {OFFSET(gpmc_a2), MODE(2)}, /* txd3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* txd2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* txd1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* txd0 */ + {OFFSET(gpmc_a6), MODE(2)}, /* txclk */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxvd */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxclk */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd3 */ + {OFFSET(gpmc_a9), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd1 */ + {OFFSET(gpmc_a11), MODE(2) | RXACTIVE | PULLUP_EN}, /* rxd0 */ + {-1}, +}; + +static struct module_pin_mux mdio_pin_mux[] = { + {OFFSET(mdio_data), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux i2c_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(spi2_sclk), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(spi2_cs0), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(gpmc_wpn), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, + {-1}, +}; + +static struct module_pin_mux emmc_pin_mux[] = { + {OFFSET(gpmc_csn1), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* EMMC_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_CMD */ + {OFFSET(gpmc_ad8), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT0 */ + {OFFSET(gpmc_ad9), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT1 */ + {OFFSET(gpmc_ad10), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT2 */ + {OFFSET(gpmc_ad11), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT3 */ + {OFFSET(gpmc_ad12), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT4 */ + {OFFSET(gpmc_ad13), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT5 */ + {OFFSET(gpmc_ad14), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT6 */ + {OFFSET(gpmc_ad15), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT7 */ + {-1}, +}; + +static struct module_pin_mux spi_flash_pin_mux[] = { + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN)}, + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN)}, + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, + {-1}, +}; + +void set_uart_mux_conf(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void set_mdio_pin_mux(void) +{ + configure_module_pin_mux(mdio_pin_mux); +} + +void set_rgmii_pin_mux(void) +{ + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); +} + +void set_mux_conf_regs(void) +{ + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(emmc_pin_mux); + configure_module_pin_mux(i2c_pin_mux); + configure_module_pin_mux(spi_flash_pin_mux); + configure_module_pin_mux(nand_pin_mux); +} + +void set_i2c_pin_mux(void) +{ + configure_module_pin_mux(i2c_pin_mux); +} diff --git a/roms/u-boot/board/compulab/cm_t43/spl.c b/roms/u-boot/board/compulab/cm_t43/spl.c new file mode 100644 index 000000000..016c63a50 --- /dev/null +++ b/roms/u-boot/board/compulab/cm_t43/spl.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Compulab, Ltd. + */ + +#include <common.h> +#include <hang.h> +#include <init.h> +#include <spl.h> +#include <i2c.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr_defs.h> +#include <asm/gpio.h> +#include <power/pmic.h> +#include <power/tps65218.h> +#include "board.h" + +const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; +const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; +const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; +const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 }; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x0143, +}; + +/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ +struct emif_regs ddr3_emif_regs = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000066, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +const u32 ext_phy_ctrl_const_base_ddr3[] = { + 0x00000000, + 0x00000044, + 0x00000044, + 0x00000046, + 0x00000046, + 0x00000000, + 0x00000059, + 0x00000077, + 0x00000093, + 0x000000A8, + 0x00000000, + 0x00000019, + 0x00000037, + 0x00000053, + 0x00000068, + 0x00000000, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + *regs = ext_phy_ctrl_const_base_ddr3; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + return &dpll_mpu; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + return &dpll_core; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + return &dpll_per; +} + +void scale_vcores(void) +{ + set_i2c_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (i2c_probe(TPS65218_CHIP_PM)) + return; + + tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV); + tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV); +} + +void sdram_init(void) +{ + unsigned long ram_size; + + config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); + ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (ram_size == 0x80000000 || + ram_size == 0x40000000 || + ram_size == 0x20000000) + return; + + ddr3_emif_regs.sdram_config = 0x638453B2; + config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); + ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (ram_size == 0x08000000) + return; + + hang(); +} + diff --git a/roms/u-boot/board/compulab/common/Makefile b/roms/u-boot/board/compulab/common/Makefile new file mode 100644 index 000000000..7ba92f5db --- /dev/null +++ b/roms/u-boot/board/compulab/common/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il> +# +# Author: Igor Grinberg <grinberg@compulab.co.il> + +obj-y += common.o +obj-$(CONFIG_SYS_I2C) += eeprom.o +obj-$(CONFIG_LCD) += omap3_display.o +obj-$(CONFIG_SMC911X) += omap3_smc911x.o diff --git a/roms/u-boot/board/compulab/common/common.c b/roms/u-boot/board/compulab/common/common.c new file mode 100644 index 000000000..528c97df1 --- /dev/null +++ b/roms/u-boot/board/compulab/common/common.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + */ + +#include <common.h> +#include <malloc.h> +#include <asm/bootm.h> +#include <asm/gpio.h> +#include <asm/setup.h> +#include <linux/delay.h> + +#include "common.h" +#include "eeprom.h" + +void cl_print_pcb_info(void) +{ + u32 board_rev = get_board_rev(); + u32 rev_major = board_rev / 100; + u32 rev_minor = board_rev - (rev_major * 100); + + if ((rev_minor / 10) * 10 == rev_minor) + rev_minor = rev_minor / 10; + + printf("PCB: %u.%u\n", rev_major, rev_minor); +} + +#ifdef CONFIG_SERIAL_TAG +void __weak get_board_serial(struct tag_serialnr *serialnr) +{ + /* + * This corresponds to what happens when we can communicate with the + * eeprom but don't get a valid board serial value. + */ + serialnr->low = 0; + serialnr->high = 0; +}; +#endif + +#ifdef CONFIG_CMD_USB +int cl_usb_hub_init(int gpio, const char *label) +{ + if (gpio_request(gpio, label)) { + printf("Error: can't obtain GPIO%d for %s", gpio, label); + return -1; + } + + gpio_direction_output(gpio, 0); + udelay(10); + gpio_set_value(gpio, 1); + udelay(1000); + return 0; +} + +void cl_usb_hub_deinit(int gpio) +{ + gpio_free(gpio); +} +#endif diff --git a/roms/u-boot/board/compulab/common/common.h b/roms/u-boot/board/compulab/common/common.h new file mode 100644 index 000000000..17cfbb6f2 --- /dev/null +++ b/roms/u-boot/board/compulab/common/common.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + */ + +#ifndef _CL_COMMON_ +#define _CL_COMMON_ + +#include <linux/errno.h> + +void cl_print_pcb_info(void); + +#ifdef CONFIG_CMD_USB +int cl_usb_hub_init(int gpio, const char *label); +void cl_usb_hub_deinit(int gpio); +#else /* !CONFIG_CMD_USB */ +static inline int cl_usb_hub_init(int gpio, const char *label) +{ + return -ENOSYS; +} +static inline void cl_usb_hub_deinit(int gpio) {} +#endif /* CONFIG_CMD_USB */ + +#ifdef CONFIG_SMC911X +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio); +#else /* !CONFIG_SMC911X */ +static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio) +{ + return -ENOSYS; +} +#endif /* CONFIG_SMC911X */ + +#endif /* _CL_COMMON_ */ diff --git a/roms/u-boot/board/compulab/common/eeprom.c b/roms/u-boot/board/compulab/common/eeprom.c new file mode 100644 index 000000000..5206cf5c0 --- /dev/null +++ b/roms/u-boot/board/compulab/common/eeprom.c @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Nikita Kiryanov <nikita@compulab.co.il> + * Igor Grinberg <grinberg@compulab.co.il> + */ + +#include <common.h> +#include <eeprom.h> +#include <i2c.h> +#include <eeprom_layout.h> +#include <eeprom_field.h> +#include <asm/setup.h> +#include <linux/kernel.h> +#include "eeprom.h" + +#ifndef CONFIG_SYS_I2C_EEPROM_ADDR +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#endif + +#ifndef CONFIG_SYS_I2C_EEPROM_BUS +#define CONFIG_SYS_I2C_EEPROM_BUS 0 +#endif + +#define EEPROM_LAYOUT_VER_OFFSET 44 +#define BOARD_SERIAL_OFFSET 20 +#define BOARD_SERIAL_OFFSET_LEGACY 8 +#define BOARD_REV_OFFSET 0 +#define BOARD_REV_OFFSET_LEGACY 6 +#define BOARD_REV_SIZE 2 +#define PRODUCT_NAME_OFFSET 128 +#define PRODUCT_NAME_SIZE 16 +#define MAC_ADDR_OFFSET 4 +#define MAC_ADDR_OFFSET_LEGACY 0 + +#define LAYOUT_INVALID 0 +#define LAYOUT_LEGACY 0xff + +static int cl_eeprom_bus; +static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */ + +static int cl_eeprom_read(uint offset, uchar *buf, int len) +{ + int res; + unsigned int current_i2c_bus = i2c_get_bus_num(); + + res = i2c_set_bus_num(cl_eeprom_bus); + if (res < 0) + return res; + + res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len); + + i2c_set_bus_num(current_i2c_bus); + + return res; +} + +static int cl_eeprom_setup(uint eeprom_bus) +{ + int res; + + /* + * We know the setup was already done when the layout is set to a valid + * value and we're using the same bus as before. + */ + if (cl_eeprom_layout != LAYOUT_INVALID && eeprom_bus == cl_eeprom_bus) + return 0; + + cl_eeprom_bus = eeprom_bus; + res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, + (uchar *)&cl_eeprom_layout, 1); + if (res) { + cl_eeprom_layout = LAYOUT_INVALID; + return res; + } + + if (cl_eeprom_layout == 0 || cl_eeprom_layout >= 0x20) + cl_eeprom_layout = LAYOUT_LEGACY; + + return 0; +} + +void get_board_serial(struct tag_serialnr *serialnr) +{ + u32 serial[2]; + uint offset; + + memset(serialnr, 0, sizeof(*serialnr)); + + if (cl_eeprom_setup(CONFIG_SYS_I2C_EEPROM_BUS)) + return; + + offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? + BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY; + + if (cl_eeprom_read(offset, (uchar *)serial, 8)) + return; + + if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) { + serialnr->low = serial[0]; + serialnr->high = serial[1]; + } +} + +/* + * Routine: cl_eeprom_read_mac_addr + * Description: read mac address and store it in buf. + */ +int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus) +{ + uint offset; + int err; + + err = cl_eeprom_setup(eeprom_bus); + if (err) + return err; + + offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? + MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY; + + return cl_eeprom_read(offset, buf, 6); +} + +static u32 board_rev; + +/* + * Routine: cl_eeprom_get_board_rev + * Description: read system revision from eeprom + */ +u32 cl_eeprom_get_board_rev(uint eeprom_bus) +{ + char str[5]; /* Legacy representation can contain at most 4 digits */ + uint offset = BOARD_REV_OFFSET_LEGACY; + + if (board_rev) + return board_rev; + + if (cl_eeprom_setup(eeprom_bus)) + return 0; + + if (cl_eeprom_layout != LAYOUT_LEGACY) + offset = BOARD_REV_OFFSET; + + if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE)) + return 0; + + /* + * Convert legacy syntactic representation to semantic + * representation. i.e. for rev 1.00: 0x100 --> 0x64 + */ + if (cl_eeprom_layout == LAYOUT_LEGACY) { + sprintf(str, "%x", board_rev); + board_rev = simple_strtoul(str, NULL, 10); + } + + return board_rev; +}; + +/* + * Routine: cl_eeprom_get_board_rev + * Description: read system revision from eeprom + * + * @buf: buffer to store the product name + * @eeprom_bus: i2c bus num of the eeprom + * + * @return: 0 on success, < 0 on failure + */ +int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus) +{ + int err; + + if (buf == NULL) + return -EINVAL; + + err = cl_eeprom_setup(eeprom_bus); + if (err) + return err; + + err = cl_eeprom_read(PRODUCT_NAME_OFFSET, buf, PRODUCT_NAME_SIZE); + if (!err) /* Protect ourselves from invalid data (unterminated str) */ + buf[PRODUCT_NAME_SIZE - 1] = '\0'; + + return err; +} + +#ifdef CONFIG_CMD_EEPROM_LAYOUT +/** + * eeprom_field_print_bin_ver() - print a "version field" which contains binary + * data + * + * Treat the field data as simple binary data, and print it formatted as a + * version number (2 digits after decimal point). + * The field size must be exactly 2 bytes. + * + * Sample output: + * Field Name 123.45 + * + * @field: an initialized field to print + */ +void eeprom_field_print_bin_ver(const struct eeprom_field *field) +{ + if ((field->buf[0] == 0xff) && (field->buf[1] == 0xff)) { + field->buf[0] = 0; + field->buf[1] = 0; + } + + printf(PRINT_FIELD_SEGMENT, field->name); + int major = (field->buf[1] << 8 | field->buf[0]) / 100; + int minor = (field->buf[1] << 8 | field->buf[0]) - major * 100; + printf("%d.%02d\n", major, minor); +} + +/** + * eeprom_field_update_bin_ver() - update a "version field" which contains + * binary data + * + * This function takes a version string in the form of x.y (x and y are both + * decimal values, y is limited to two digits), translates it to the binary + * form, then writes it to the field. The field size must be exactly 2 bytes. + * + * This function strictly enforces the data syntax, and will not update the + * field if there's any deviation from it. It also protects from overflow. + * + * @field: an initialized field + * @value: a version string + * + * Returns 0 on success, -1 on failure. + */ +int eeprom_field_update_bin_ver(struct eeprom_field *field, char *value) +{ + char *endptr; + char *tok = strtok(value, "."); + if (tok == NULL) + return -1; + + int num = simple_strtol(tok, &endptr, 0); + if (*endptr != '\0') + return -1; + + tok = strtok(NULL, ""); + if (tok == NULL) + return -1; + + int remainder = simple_strtol(tok, &endptr, 0); + if (*endptr != '\0') + return -1; + + num = num * 100 + remainder; + if (num >> 16) + return -1; + + field->buf[0] = (unsigned char)num; + field->buf[1] = num >> 8; + + return 0; +} + +char *months[12] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", + "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"}; + +/** + * eeprom_field_print_date() - print a field which contains date data + * + * Treat the field data as simple binary data, and print it formatted as a date. + * Sample output: + * Field Name 07/Feb/2014 + * Field Name 56/BAD/9999 + * + * @field: an initialized field to print + */ +void eeprom_field_print_date(const struct eeprom_field *field) +{ + printf(PRINT_FIELD_SEGMENT, field->name); + printf("%02d/", field->buf[0]); + if (field->buf[1] >= 1 && field->buf[1] <= 12) + printf("%s", months[field->buf[1] - 1]); + else + printf("BAD"); + + printf("/%d\n", field->buf[3] << 8 | field->buf[2]); +} + +static int validate_date(unsigned char day, unsigned char month, + unsigned int year) +{ + int days_in_february; + + switch (month) { + case 0: + case 2: + case 4: + case 6: + case 7: + case 9: + case 11: + if (day > 31) + return -1; + break; + case 3: + case 5: + case 8: + case 10: + if (day > 30) + return -1; + break; + case 1: + days_in_february = 28; + if (year % 4 == 0) { + if (year % 100 != 0) + days_in_february = 29; + else if (year % 400 == 0) + days_in_february = 29; + } + + if (day > days_in_february) + return -1; + + break; + default: + return -1; + } + + return 0; +} + +/** + * eeprom_field_update_date() - update a date field which contains binary data + * + * This function takes a date string in the form of x/Mon/y (x and y are both + * decimal values), translates it to the binary representation, then writes it + * to the field. + * + * This function strictly enforces the data syntax, and will not update the + * field if there's any deviation from it. It also protects from overflow in the + * year value, and checks the validity of the date. + * + * @field: an initialized field + * @value: a date string + * + * Returns 0 on success, -1 on failure. + */ +int eeprom_field_update_date(struct eeprom_field *field, char *value) +{ + char *endptr; + char *tok1 = strtok(value, "/"); + char *tok2 = strtok(NULL, "/"); + char *tok3 = strtok(NULL, "/"); + + if (tok1 == NULL || tok2 == NULL || tok3 == NULL) { + printf("%s: syntax error\n", field->name); + return -1; + } + + unsigned char day = (unsigned char)simple_strtol(tok1, &endptr, 0); + if (*endptr != '\0' || day == 0) { + printf("%s: invalid day\n", field->name); + return -1; + } + + unsigned char month; + for (month = 1; month <= 12; month++) + if (!strcmp(tok2, months[month - 1])) + break; + + unsigned int year = simple_strtol(tok3, &endptr, 0); + if (*endptr != '\0') { + printf("%s: invalid year\n", field->name); + return -1; + } + + if (validate_date(day, month - 1, year)) { + printf("%s: invalid date\n", field->name); + return -1; + } + + if (year >> 16) { + printf("%s: year overflow\n", field->name); + return -1; + } + + field->buf[0] = day; + field->buf[1] = month; + field->buf[2] = (unsigned char)year; + field->buf[3] = (unsigned char)(year >> 8); + + return 0; +} + +#define LAYOUT_VERSION_LEGACY 1 +#define LAYOUT_VERSION_VER1 2 +#define LAYOUT_VERSION_VER2 3 +#define LAYOUT_VERSION_VER3 4 + +extern struct eeprom_field layout_unknown[1]; + +#define DEFINE_PRINT_UPDATE(x) eeprom_field_print_##x, eeprom_field_update_##x + +#ifdef CONFIG_CM_T3X +struct eeprom_field layout_legacy[5] = { + { "MAC address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "Board Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin) }, + { "Serial Number", 8, NULL, DEFINE_PRINT_UPDATE(bin) }, + { "Board Configuration", 64, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { RESERVED_FIELDS, 176, NULL, eeprom_field_print_reserved, + eeprom_field_update_ascii }, +}; +#else +#define layout_legacy layout_unknown +#endif + +#if defined(CONFIG_CM_T3X) +struct eeprom_field layout_v1[12] = { + { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, + { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, + { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) }, + { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) }, + { RESERVED_FIELDS, 96, NULL, DEFINE_PRINT_UPDATE(reserved) }, + { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved, + eeprom_field_update_ascii }, +}; +#else +#define layout_v1 layout_unknown +#endif + +struct eeprom_field layout_v2[15] = { + { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, + { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, + { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) }, + { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) }, + { "3rd MAC Address (WIFI)", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "Layout Version", 1, NULL, DEFINE_PRINT_UPDATE(bin) }, + { RESERVED_FIELDS, 83, NULL, DEFINE_PRINT_UPDATE(reserved) }, + { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved, + eeprom_field_update_ascii }, +}; + +struct eeprom_field layout_v3[16] = { + { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, + { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, + { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) }, + { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) }, + { "3rd MAC Address (WIFI)", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, + { "Layout Version", 1, NULL, DEFINE_PRINT_UPDATE(bin) }, + { "CompuLab EEPROM ID", 3, NULL, DEFINE_PRINT_UPDATE(bin) }, + { RESERVED_FIELDS, 80, NULL, DEFINE_PRINT_UPDATE(reserved) }, + { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, + { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved, + eeprom_field_update_ascii }, +}; + +void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version) +{ + switch (layout->layout_version) { + case LAYOUT_VERSION_LEGACY: + layout->fields = layout_legacy; + layout->num_of_fields = ARRAY_SIZE(layout_legacy); + break; + case LAYOUT_VERSION_VER1: + layout->fields = layout_v1; + layout->num_of_fields = ARRAY_SIZE(layout_v1); + break; + case LAYOUT_VERSION_VER2: + layout->fields = layout_v2; + layout->num_of_fields = ARRAY_SIZE(layout_v2); + break; + case LAYOUT_VERSION_VER3: + layout->fields = layout_v3; + layout->num_of_fields = ARRAY_SIZE(layout_v3); + break; + default: + __eeprom_layout_assign(layout, layout_version); + } +} + +int eeprom_parse_layout_version(char *str) +{ + if (!strcmp(str, "legacy")) + return LAYOUT_VERSION_LEGACY; + else if (!strcmp(str, "v1")) + return LAYOUT_VERSION_VER1; + else if (!strcmp(str, "v2")) + return LAYOUT_VERSION_VER2; + else if (!strcmp(str, "v3")) + return LAYOUT_VERSION_VER3; + else + return LAYOUT_VERSION_UNRECOGNIZED; +} + +int eeprom_layout_detect(unsigned char *data) +{ + switch (data[EEPROM_LAYOUT_VER_OFFSET]) { + case 0xff: + case 0: + return LAYOUT_VERSION_VER1; + case 2: + return LAYOUT_VERSION_VER2; + case 3: + return LAYOUT_VERSION_VER3; + } + + if (data[EEPROM_LAYOUT_VER_OFFSET] >= 0x20) + return LAYOUT_VERSION_LEGACY; + + return LAYOUT_VERSION_UNRECOGNIZED; +} +#endif diff --git a/roms/u-boot/board/compulab/common/eeprom.h b/roms/u-boot/board/compulab/common/eeprom.h new file mode 100644 index 000000000..a9c0203b8 --- /dev/null +++ b/roms/u-boot/board/compulab/common/eeprom.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Nikita Kiryanov <nikita@compulab.co.il> + * Igor Grinberg <grinberg@compulab.co.il> + */ + +#ifndef _EEPROM_ +#define _EEPROM_ +#include <errno.h> + +#ifdef CONFIG_SYS_I2C +int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus); +u32 cl_eeprom_get_board_rev(uint eeprom_bus); +int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus); +#else +static inline int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus) +{ + return 1; +} +static inline u32 cl_eeprom_get_board_rev(uint eeprom_bus) +{ + return 0; +} +static inline int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus) +{ + return -ENOSYS; +} +#endif + +#endif diff --git a/roms/u-boot/board/compulab/common/omap3_display.c b/roms/u-boot/board/compulab/common/omap3_display.c new file mode 100644 index 000000000..cb9ebae7f --- /dev/null +++ b/roms/u-boot/board/compulab/common/omap3_display.c @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Nikita Kiryanov <nikita@compulab.co.il> + * + * Parsing code based on linux/drivers/video/pxafb.c + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <env.h> +#include <stdio_dev.h> +#include <asm/arch/dss.h> +#include <lcd.h> +#include <scf0403_lcd.h> +#include <asm/arch-omap3/dss.h> + +enum display_type { + NONE, + DVI, + DVI_CUSTOM, + DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */ +}; + +#define CMAP_ADDR 0x80100000 + +/* + * The frame buffer is allocated before we have the chance to parse user input. + * To make sure enough memory is allocated for all resolutions, we define + * vl_{col | row} to the maximal resolution supported by OMAP3. + */ +vidinfo_t panel_info = { + .vl_col = 1400, + .vl_row = 1050, + .vl_bpix = LCD_BPP, + .cmap = (ushort *)CMAP_ADDR, +}; + +static struct panel_config panel_cfg; +static enum display_type lcd_def; + +/* + * A note on DVI presets; + * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can + * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to + * support two BMP types with one setting. + */ +static const struct panel_config preset_dvi_640X480 = { + .lcd_size = PANEL_LCD_SIZE(640, 480), + .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96), + .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 12 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_800X600 = { + .lcd_size = PANEL_LCD_SIZE(800, 600), + .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128), + .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 8 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1024X768 = { + .lcd_size = PANEL_LCD_SIZE(1024, 768), + .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136), + .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 5 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1152X864 = { + .lcd_size = PANEL_LCD_SIZE(1152, 864), + .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128), + .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 4 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1280X960 = { + .lcd_size = PANEL_LCD_SIZE(1280, 960), + .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112), + .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1280X1024 = { + .lcd_size = PANEL_LCD_SIZE(1280, 1024), + .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112), + .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dataimage_480X800 = { + .lcd_size = PANEL_LCD_SIZE(480, 800), + .timing_h = DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2), + .timing_v = DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3), + .pol_freq = DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF, + .divisor = 10 | (1 << 10), + .data_lines = LCD_INTERFACE_18_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +/* + * set_resolution_params() + * + * Due to usage of multiple display related APIs resolution data is located in + * more than one place. This function updates them all. + */ +static void set_resolution_params(int x, int y) +{ + panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y); + panel_info.vl_col = x; + panel_info.vl_row = y; + lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; +} + +static void set_preset(const struct panel_config preset, int x_res, int y_res) +{ + panel_cfg = preset; + set_resolution_params(x_res, y_res); +} + +static enum display_type set_dvi_preset(const struct panel_config preset, + int x_res, int y_res) +{ + set_preset(preset, x_res, y_res); + return DVI; +} + +static enum display_type set_dataimage_preset(const struct panel_config preset, + int x_res, int y_res) +{ + set_preset(preset, x_res, y_res); + return DATA_IMAGE; +} + +/* + * parse_mode() - parse the mode parameter of custom lcd settings + * + * @mode: <res_x>x<res_y> + * + * Returns -1 on error, 0 on success. + */ +static int parse_mode(const char *mode) +{ + unsigned int modelen = strlen(mode); + int res_specified = 0; + unsigned int xres = 0, yres = 0; + int yres_specified = 0; + int i; + + for (i = modelen - 1; i >= 0; i--) { + switch (mode[i]) { + case 'x': + if (!yres_specified) { + yres = simple_strtoul(&mode[i + 1], NULL, 0); + yres_specified = 1; + } else { + goto done_parsing; + } + + break; + case '0' ... '9': + break; + default: + goto done_parsing; + } + } + + if (i < 0 && yres_specified) { + xres = simple_strtoul(mode, NULL, 0); + res_specified = 1; + } + +done_parsing: + if (res_specified) { + set_resolution_params(xres, yres); + } else { + printf("LCD: invalid mode: %s\n", mode); + return -1; + } + + return 0; +} + +#define PIXEL_CLK_NUMERATOR (26 * 432 / 39) +/* + * parse_pixclock() - Parse the pixclock parameter of custom lcd settings + * + * @pixclock: the desired pixel clock + * + * Returns -1 on error, 0 on success. + * + * Handling the pixel_clock: + * + * Pixel clock is defined in the OMAP35x TRM as follows: + * pixel_clock = + * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) / + * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] * + * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1)) + * + * In practice, this means that in order to set the + * divisor for the desired pixel clock one needs to + * solve the following equation: + * + * 26 * 432 / (39 * <pixel_clock>) = DSS.DISPC_DIVISOR[6:0] + * + * NOTE: the explicit equation above is reduced. Do not + * try to infer anything from these numbers. + */ +static int parse_pixclock(char *pixclock) +{ + int divisor, pixclock_val; + char *pixclk_start = pixclock; + + pixclock_val = simple_strtoul(pixclock, &pixclock, 10); + divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val); + /* 0 and 1 are illegal values for PCD */ + if (divisor <= 1) + divisor = 2; + + panel_cfg.divisor = divisor | (1 << 16); + if (pixclock[0] != '\0') { + printf("LCD: invalid value for pixclock:%s\n", pixclk_start); + return -1; + } + + return 0; +} + +/* + * parse_setting() - parse a single setting of custom lcd parameters + * + * @setting: The custom lcd setting <name>:<value> + * + * Returns -1 on failure, 0 on success. + */ +static int parse_setting(char *setting) +{ + int num_val; + char *setting_start = setting; + + if (!strncmp(setting, "mode:", 5)) { + return parse_mode(setting + 5); + } else if (!strncmp(setting, "pixclock:", 9)) { + return parse_pixclock(setting + 9); + } else if (!strncmp(setting, "left:", 5)) { + num_val = simple_strtoul(setting + 5, &setting, 0); + panel_cfg.timing_h |= DSS_HBP(num_val); + } else if (!strncmp(setting, "right:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_h |= DSS_HFP(num_val); + } else if (!strncmp(setting, "upper:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_v |= DSS_VBP(num_val); + } else if (!strncmp(setting, "lower:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_v |= DSS_VFP(num_val); + } else if (!strncmp(setting, "hsynclen:", 9)) { + num_val = simple_strtoul(setting + 9, &setting, 0); + panel_cfg.timing_h |= DSS_HSW(num_val); + } else if (!strncmp(setting, "vsynclen:", 9)) { + num_val = simple_strtoul(setting + 9, &setting, 0); + panel_cfg.timing_v |= DSS_VSW(num_val); + } else if (!strncmp(setting, "hsync:", 6)) { + if (simple_strtoul(setting + 6, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IHS; + else + panel_cfg.pol_freq &= ~DSS_IHS; + } else if (!strncmp(setting, "vsync:", 6)) { + if (simple_strtoul(setting + 6, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IVS; + else + panel_cfg.pol_freq &= ~DSS_IVS; + } else if (!strncmp(setting, "outputen:", 9)) { + if (simple_strtoul(setting + 9, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IEO; + else + panel_cfg.pol_freq &= ~DSS_IEO; + } else if (!strncmp(setting, "pixclockpol:", 12)) { + if (simple_strtoul(setting + 12, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IPC; + else + panel_cfg.pol_freq &= ~DSS_IPC; + } else if (!strncmp(setting, "active", 6)) { + panel_cfg.panel_type = ACTIVE_DISPLAY; + return 0; /* Avoid sanity check below */ + } else if (!strncmp(setting, "passive", 7)) { + panel_cfg.panel_type = PASSIVE_DISPLAY; + return 0; /* Avoid sanity check below */ + } else if (!strncmp(setting, "display:", 8)) { + if (!strncmp(setting + 8, "dvi", 3)) { + lcd_def = DVI_CUSTOM; + return 0; /* Avoid sanity check below */ + } + } else { + printf("LCD: unknown option %s\n", setting_start); + return -1; + } + + if (setting[0] != '\0') { + printf("LCD: invalid value for %s\n", setting_start); + return -1; + } + + return 0; +} + +/* + * env_parse_customlcd() - parse custom lcd params from an environment variable. + * + * @custom_lcd_params: The environment variable containing the lcd params. + * + * Returns -1 on failure, 0 on success. + */ +static int parse_customlcd(char *custom_lcd_params) +{ + char params_cpy[160]; + char *setting; + + strncpy(params_cpy, custom_lcd_params, 160); + setting = strtok(params_cpy, ","); + while (setting) { + if (parse_setting(setting) < 0) + return -1; + + setting = strtok(NULL, ","); + } + + /* Currently we don't support changing this via custom lcd params */ + panel_cfg.data_lines = LCD_INTERFACE_24_BIT; + panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */ + + return 0; +} + +/* + * env_parse_displaytype() - parse display type. + * + * Parses the environment variable "displaytype", which contains the + * name of the display type or preset, in which case it applies its + * configurations. + * + * Returns the type of display that was specified. + */ +static enum display_type env_parse_displaytype(char *displaytype) +{ + if (!strncmp(displaytype, "dvi640x480", 10)) + return set_dvi_preset(preset_dvi_640X480, 640, 480); + else if (!strncmp(displaytype, "dvi800x600", 10)) + return set_dvi_preset(preset_dvi_800X600, 800, 600); + else if (!strncmp(displaytype, "dvi1024x768", 11)) + return set_dvi_preset(preset_dvi_1024X768, 1024, 768); + else if (!strncmp(displaytype, "dvi1152x864", 11)) + return set_dvi_preset(preset_dvi_1152X864, 1152, 864); + else if (!strncmp(displaytype, "dvi1280x960", 11)) + return set_dvi_preset(preset_dvi_1280X960, 1280, 960); + else if (!strncmp(displaytype, "dvi1280x1024", 12)) + return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024); + else if (!strncmp(displaytype, "dataimage480x800", 16)) + return set_dataimage_preset(preset_dataimage_480X800, 480, 800); + + return NONE; +} + +void lcd_ctrl_init(void *lcdbase) +{ + struct prcm *prcm = (struct prcm *)PRCM_BASE; + char *custom_lcd; + char *displaytype = env_get("displaytype"); + + if (displaytype == NULL) + return; + + lcd_def = env_parse_displaytype(displaytype); + /* If we did not recognize the preset, check if it's an env variable */ + if (lcd_def == NONE) { + custom_lcd = env_get(displaytype); + if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0) + return; + } + + panel_cfg.frame_buffer = lcdbase; + omap3_dss_panel_config(&panel_cfg); + /* + * Pixel clock is defined with many divisions and only few + * multiplications of the system clock. Since DSS FCLK divisor is set + * to 16 by default, we need to set it to a smaller value, like 3 + * (chosen via trial and error). + */ + clrsetbits_le32(&prcm->clksel_dss, 0xF, 3); +} + +#ifdef CONFIG_SCF0403_LCD +static void scf0403_enable(void) +{ + gpio_direction_output(58, 1); + scf0403_init(157); +} +#else +static inline void scf0403_enable(void) {} +#endif + +void lcd_enable(void) +{ + switch (lcd_def) { + case NONE: + return; + case DVI: + case DVI_CUSTOM: + gpio_direction_output(54, 0); /* Turn on DVI */ + break; + case DATA_IMAGE: + scf0403_enable(); + break; + } + + omap3_dss_enable(); +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {} diff --git a/roms/u-boot/board/compulab/common/omap3_smc911x.c b/roms/u-boot/board/compulab/common/omap3_smc911x.c new file mode 100644 index 000000000..f0d365272 --- /dev/null +++ b/roms/u-boot/board/compulab/common/omap3_smc911x.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + */ + +#include <common.h> +#include <netdev.h> +#include <linux/delay.h> + +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/cpu.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> + +#include "common.h" + +static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = { + NET_GPMC_CONFIG1, + NET_GPMC_CONFIG2, + NET_GPMC_CONFIG3, + NET_GPMC_CONFIG4, + NET_GPMC_CONFIG5, + NET_GPMC_CONFIG6, + 0 +}; + +static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config, + &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); +} + +#ifdef CONFIG_OMAP_GPIO +static int cl_omap3_smc911x_reset_net_chip(int gpio) +{ + int err; + + if (!gpio_is_valid(gpio)) + return -EINVAL; + + err = gpio_request(gpio, "eth rst"); + if (err) + return err; + + /* Set gpio as output and send a pulse */ + gpio_direction_output(gpio, 1); + udelay(1); + gpio_set_value(gpio, 0); + mdelay(40); + gpio_set_value(gpio, 1); + mdelay(1); + + return 0; +} +#else /* !CONFIG_OMAP_GPIO */ +static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; } +#endif /* CONFIG_OMAP_GPIO */ + +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio) +{ + int ret; + + cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr); + + if (reset) + reset(rst_gpio); + else + cl_omap3_smc911x_reset_net_chip(rst_gpio); + + ret = smc911x_initialize(id, base_addr); + if (ret > 0) + return ret; + + printf("Failed initializing SMC911x! "); + return 0; +} diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Kconfig b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Kconfig new file mode 100644 index 000000000..7f5c794bf --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8MM_CL_IOT_GATE + +config SYS_BOARD + default "imx8mm-cl-iot-gate" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "imx8mm-cl-iot-gate" + +endif diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS new file mode 100644 index 000000000..9c6b17095 --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS @@ -0,0 +1,6 @@ +Compulab IOT-GATE-iMX8 BOARD +M: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> +S: Maintained +F: board/compulab/imx8mm-cl-iot-gate/ +F: include/configs/imx8mm-cl-iot-gate.h +F: configs/imx8mm-cl-iot-gate_defconfig diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Makefile b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Makefile new file mode 100644 index 000000000..3a2bfc4dc --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2018 NXP +# Copyright 2020 Linaro +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mm-cl-iot-gate.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += ddr/ +endif diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile new file mode 100644 index 000000000..591479662 --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile @@ -0,0 +1,8 @@ +obj-y += ddr.o +obj-y += lpddr4_timing_ff020008.o +obj-y += lpddr4_timing_ff000110.o +ifdef CONFIG_TARGET_MCM_IMX8M_MINI +obj-y += lpddr4_timing_01061010.o +else +obj-y += lpddr4_timing_01061010.1_2.o +endif diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c new file mode 100644 index 000000000..42dd0dbf1 --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + * Copyright 2020 Linaro + * + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <errno.h> +#include <command.h> +#include <asm/io.h> +#include <asm/arch/lpddr4_define.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/gpio.h> +#include <asm-generic/gpio.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/mach-imx/gpio.h> +#include "ddr.h" + +static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) +{ + unsigned int tmp; + + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); + } while ((tmp & 0x8) == 0); + tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); + while (tmp) { //try to find a significant byte in the word + if (tmp & 0xff) { + tmp &= 0xff; + break; + } + tmp >>= 8; + } + return tmp; +} + +struct lpddr4_desc { + char name[16]; + unsigned int id; + unsigned int size; + unsigned int count; + /* an optional field + * use it if default is not the + * 1-st array entry + */ + unsigned int _default; + /* An optional field to distiguish DRAM chips that + * have different geometry, though return the same MRR. + * Default value 0xff + */ + u8 subind; + struct dram_timing_info *timing; + char *desc[4]; +}; + +#define DEFAULT (('D' << 24) + ('E' << 16) + ('F' << 8) + 'A') +static const struct lpddr4_desc lpddr4_array[] = { + { .name = "Nanya", .id = 0x05000010, .subind = 0xff, + .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, + { .name = "Samsung", .id = 0x01061010, .subind = 0xff, + .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, + { .name = "Kingston", .id = 0xff000010, .subind = 0x04, + .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110}, + { .name = "Kingston", .id = 0xff000010, .subind = 0x02, + .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, + { .name = "Micron", .id = 0xff020008, .subind = 0xff, + .size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008}, + { .name = "Micron", .id = 0xff000110, .subind = 0xff, + .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110}, +}; + +static unsigned int lpddr4_get_mr(void) +{ + int i = 0, attempts = 5; + unsigned int ddr_info = 0; + unsigned int regs[] = { 5, 6, 7, 8 }; + + do { + for (i = 0 ; i < ARRAY_SIZE(regs) ; i++) { + unsigned int data = 0; + + data = lpddr4_mr_read(0xF, regs[i]); + ddr_info <<= 8; + ddr_info += (data & 0xFF); + } + if (ddr_info != 0xFFFFFFFF && ddr_info != 0) + break; // The attempt was successful + } while (--attempts); + return ddr_info; +} + +static void spl_tcm_init(struct lpddr4_tcm_desc *lpddr4_tcm_desc) +{ + if (lpddr4_tcm_desc->sign == DEFAULT) + return; + + lpddr4_tcm_desc->sign = DEFAULT; + lpddr4_tcm_desc->index = 0; +} + +static void spl_tcm_fini(struct lpddr4_tcm_desc *lpddr4_tcm_desc) +{ + if (lpddr4_tcm_desc->sign != DEFAULT) + return; + + lpddr4_tcm_desc->sign = ~DEFAULT; + lpddr4_tcm_desc->index = 0; +} + +#define SPL_TCM_DATA 0x7e0000 +#define SPL_TCM_INIT spl_tcm_init(lpddr4_tcm_desc) +#define SPL_TCM_FINI spl_tcm_fini(lpddr4_tcm_desc) + +void spl_dram_init_compulab(void) +{ + unsigned int ddr_info = 0xdeadbeef; + unsigned int ddr_info_mrr = 0xdeadbeef; + unsigned int ddr_found = 0; + int i = 0; + + struct lpddr4_tcm_desc *lpddr4_tcm_desc = + (struct lpddr4_tcm_desc *)SPL_TCM_DATA; + + if (lpddr4_tcm_desc->sign != DEFAULT) { + /* if not in tcm scan mode */ + for (i = 0; i < ARRAY_SIZE(lpddr4_array); i++) { + if (lpddr4_array[i].id == ddr_info && + lpddr4_array[i].subind == 0xff) { + ddr_found = 1; + break; + } + } + } + + /* Walk trought all available ddr ids and apply + * one by one. Save the index at the tcm memory that + * persists after the reset. + */ + if (ddr_found == 0) { + SPL_TCM_INIT; + + if (lpddr4_tcm_desc->index < ARRAY_SIZE(lpddr4_array)) { + printf("DDRINFO: Cfg attempt: [ %d/%lu ]\n", + lpddr4_tcm_desc->index + 1, + ARRAY_SIZE(lpddr4_array)); + i = lpddr4_tcm_desc->index; + lpddr4_tcm_desc->index += 1; + } else { + /* Ran out all available ddr setings */ + printf("DDRINFO: Ran out all [ %lu ] cfg attempts. A non supported configuration.\n", + ARRAY_SIZE(lpddr4_array)); + while (1) + ; + } + ddr_info = lpddr4_array[i].id; + } else { + printf("DDRINFO(%s): %s %dG\n", (ddr_found ? "D" : "?"), + lpddr4_array[i].name, + lpddr4_array[i].size); + } + + if (ddr_init(lpddr4_array[i].timing)) { + SPL_TCM_INIT; + do_reset(NULL, 0, 0, NULL); + } + + ddr_info_mrr = lpddr4_get_mr(); + if (ddr_info_mrr == 0xFFFFFFFF) { + printf("DDRINFO(M): mr5-8 [ 0x%x ] is invalid; reset\n", + ddr_info_mrr); + SPL_TCM_INIT; + do_reset(NULL, 0, 0, NULL); + } + + printf("DDRINFO(M): mr5-8 [ 0x%x ]\n", ddr_info_mrr); + printf("DDRINFO(%s): mr5-8 [ 0x%x ]\n", (ddr_found ? "E" : "T"), + ddr_info); + + if (ddr_info_mrr != ddr_info) { + SPL_TCM_INIT; + do_reset(NULL, 0, 0, NULL); + } + + SPL_TCM_FINI; + + /* Pass the dram size to th U-Boot through the tcm memory */ + { /* To figure out what to store into the TCM buffer */ + /* For debug purpouse only. To override the real memsize */ + unsigned int ddr_tcm_size = 0; + + if (ddr_tcm_size == 0 || ddr_tcm_size == -1) + ddr_tcm_size = lpddr4_array[i].size; + + lpddr4_tcm_desc->size = ddr_tcm_size; + } +} diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h new file mode 100644 index 000000000..59c189115 --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + * Copyright 2020 Linaro + * + */ + +#ifndef __COMPULAB_DDR_H__ +#define __COMPULAB_DDR_H__ + +extern struct dram_timing_info ucm_dram_timing_ff020008; +extern struct dram_timing_info ucm_dram_timing_ff000110; +extern struct dram_timing_info ucm_dram_timing_01061010; + +void spl_dram_init_compulab(void); + +#define TCM_DATA_CFG 0x7e0000 + +struct lpddr4_tcm_desc { + unsigned int size; + unsigned int sign; + unsigned int index; + unsigned int count; +}; + +#endif diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c new file mode 100644 index 000000000..870a94aec --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c @@ -0,0 +1,1848 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <common.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304, 0x1}, + {0x3d400030, 0x1}, + {0x3d400000, 0xa1080020}, + {0x3d400020, 0x223}, + {0x3d400024, 0x2ee00}, + {0x3d400064, 0x4900a8}, + {0x3d4000d0, 0xc0030495}, + {0x3d4000d4, 0x770000}, + {0x3d4000dc, 0xc40024}, + {0x3d4000e0, 0x310000}, + {0x3d4000e8, 0x66004d}, + {0x3d4000ec, 0x16004d}, + {0x3d400100, 0x1618141a}, + {0x3d400104, 0x504a6}, + {0x3d40010c, 0x909000}, + {0x3d400110, 0xb04060b}, + {0x3d400114, 0x2030909}, + {0x3d400118, 0x1010006}, + {0x3d40011c, 0x301}, + {0x3d400130, 0x20500}, + {0x3d400134, 0xb100002}, + {0x3d400138, 0xad}, + {0x3d400144, 0x78003c}, + {0x3d400180, 0x2580012}, + {0x3d400184, 0x1e0493e}, + {0x3d400188, 0x0}, + {0x3d400190, 0x4938208}, + {0x3d400194, 0x80303}, + {0x3d4001b4, 0x1308}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0xdf00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x11}, + {0x3d4001c0, 0x1}, + {0x3d4001c4, 0x0}, + {0x3d4000f4, 0xc99}, + {0x3d400108, 0x60c1514}, + {0x3d400200, 0x1f}, + {0x3d40020c, 0x0}, + {0x3d400210, 0x1f1f}, + {0x3d400204, 0x80808}, + {0x3d400214, 0x7070707}, + {0x3d400218, 0x7070707}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x2c}, + {0x3d40025c, 0x4000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x2005574}, + {0x3d400400, 0x111}, + {0x3d400408, 0x72ff}, + {0x3d400494, 0x2100e07}, + {0x3d400498, 0x620096}, + {0x3d40049c, 0x1100e07}, + {0x3d4004a0, 0xc8012c}, + {0x3d402020, 0x21}, + {0x3d402024, 0x7d00}, + {0x3d402050, 0x20d040}, + {0x3d402064, 0xc001c}, + {0x3d4020dc, 0x840000}, + {0x3d4020e0, 0x310000}, + {0x3d4020e8, 0x66004d}, + {0x3d4020ec, 0x16004d}, + {0x3d402100, 0xa040305}, + {0x3d402104, 0x30407}, + {0x3d402108, 0x203060b}, + {0x3d40210c, 0x505000}, + {0x3d402110, 0x2040202}, + {0x3d402114, 0x2030202}, + {0x3d402118, 0x1010004}, + {0x3d40211c, 0x301}, + {0x3d402130, 0x20300}, + {0x3d402134, 0xa100002}, + {0x3d402138, 0x1d}, + {0x3d402144, 0x14000a}, + {0x3d402180, 0x640004}, + {0x3d402190, 0x3818200}, + {0x3d402194, 0x80303}, + {0x3d4021b4, 0x100}, + {0x3d403020, 0x21}, + {0x3d403024, 0x1f40}, + {0x3d403050, 0x20d040}, + {0x3d403064, 0x30007}, + {0x3d4030dc, 0x840000}, + {0x3d4030e0, 0x310000}, + {0x3d4030e8, 0x66004d}, + {0x3d4030ec, 0x16004d}, + {0x3d403100, 0xa010102}, + {0x3d403104, 0x30404}, + {0x3d403108, 0x203060b}, + {0x3d40310c, 0x505000}, + {0x3d403110, 0x2040202}, + {0x3d403114, 0x2030202}, + {0x3d403118, 0x1010004}, + {0x3d40311c, 0x301}, + {0x3d403130, 0x20300}, + {0x3d403134, 0xa100002}, + {0x3d403138, 0x8}, + {0x3d403144, 0x50003}, + {0x3d403180, 0x190004}, + {0x3d403190, 0x3818200}, + {0x3d403194, 0x80303}, + {0x3d4031b4, 0x100}, + {0x3d400028, 0x0}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x3}, + {0x110a3, 0x4}, + {0x110a4, 0x5}, + {0x110a5, 0x2}, + {0x110a6, 0x7}, + {0x110a7, 0x6}, + {0x120a0, 0x0}, + {0x120a1, 0x1}, + {0x120a2, 0x3}, + {0x120a3, 0x2}, + {0x120a4, 0x5}, + {0x120a5, 0x4}, + {0x120a6, 0x7}, + {0x120a7, 0x6}, + {0x130a0, 0x0}, + {0x130a1, 0x1}, + {0x130a2, 0x2}, + {0x130a3, 0x3}, + {0x130a4, 0x4}, + {0x130a5, 0x5}, + {0x130a6, 0x6}, + {0x130a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x1205f, 0x1ff}, + {0x1215f, 0x1ff}, + {0x1305f, 0x1ff}, + {0x1315f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x11205f, 0x1ff}, + {0x11215f, 0x1ff}, + {0x11305f, 0x1ff}, + {0x11315f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x21205f, 0x1ff}, + {0x21215f, 0x1ff}, + {0x21305f, 0x1ff}, + {0x21315f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x3055, 0x1ff}, + {0x4055, 0x1ff}, + {0x5055, 0x1ff}, + {0x6055, 0x1ff}, + {0x7055, 0x1ff}, + {0x8055, 0x1ff}, + {0x9055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x7}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1ab}, + {0x2003a, 0x0}, + {0x120024, 0x1ab}, + {0x2003a, 0x0}, + {0x220024, 0x1ab}, + {0x2003a, 0x0}, + {0x20056, 0x2}, + {0x120056, 0xa}, + {0x220056, 0xa}, + {0x1004d, 0xe00}, + {0x1014d, 0xe00}, + {0x1104d, 0xe00}, + {0x1114d, 0xe00}, + {0x1204d, 0xe00}, + {0x1214d, 0xe00}, + {0x1304d, 0xe00}, + {0x1314d, 0xe00}, + {0x11004d, 0xe00}, + {0x11014d, 0xe00}, + {0x11104d, 0xe00}, + {0x11114d, 0xe00}, + {0x11204d, 0xe00}, + {0x11214d, 0xe00}, + {0x11304d, 0xe00}, + {0x11314d, 0xe00}, + {0x21004d, 0xe00}, + {0x21014d, 0xe00}, + {0x21104d, 0xe00}, + {0x21114d, 0xe00}, + {0x21204d, 0xe00}, + {0x21214d, 0xe00}, + {0x21304d, 0xe00}, + {0x21314d, 0xe00}, + {0x10049, 0xeba}, + {0x10149, 0xeba}, + {0x11049, 0xeba}, + {0x11149, 0xeba}, + {0x12049, 0xeba}, + {0x12149, 0xeba}, + {0x13049, 0xeba}, + {0x13149, 0xeba}, + {0x110049, 0xeba}, + {0x110149, 0xeba}, + {0x111049, 0xeba}, + {0x111149, 0xeba}, + {0x112049, 0xeba}, + {0x112149, 0xeba}, + {0x113049, 0xeba}, + {0x113149, 0xeba}, + {0x210049, 0xeba}, + {0x210149, 0xeba}, + {0x211049, 0xeba}, + {0x211149, 0xeba}, + {0x212049, 0xeba}, + {0x212149, 0xeba}, + {0x213049, 0xeba}, + {0x213149, 0xeba}, + {0x43, 0x63}, + {0x1043, 0x63}, + {0x2043, 0x63}, + {0x3043, 0x63}, + {0x4043, 0x63}, + {0x5043, 0x63}, + {0x6043, 0x63}, + {0x7043, 0x63}, + {0x8043, 0x63}, + {0x9043, 0x63}, + {0x20018, 0x3}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x20008, 0x258}, + {0x120008, 0x64}, + {0x220008, 0x19}, + {0x20088, 0x9}, + {0x200b2, 0xdc}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x12043, 0x5a1}, + {0x12143, 0x5a1}, + {0x13043, 0x5a1}, + {0x13143, 0x5a1}, + {0x1200b2, 0xdc}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x112043, 0x5a1}, + {0x112143, 0x5a1}, + {0x113043, 0x5a1}, + {0x113143, 0x5a1}, + {0x2200b2, 0xdc}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x212043, 0x5a1}, + {0x212143, 0x5a1}, + {0x213043, 0x5a1}, + {0x213143, 0x5a1}, + {0x200fa, 0x1}, + {0x1200fa, 0x1}, + {0x2200fa, 0x1}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x660}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5665}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x2200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, + {0x2200ca, 0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0}, + { 0x1200b2, 0x0}, + { 0x2200b2, 0x0}, + { 0x200cb, 0x0}, + { 0x10043, 0x0}, + { 0x110043, 0x0}, + { 0x210043, 0x0}, + { 0x10143, 0x0}, + { 0x110143, 0x0}, + { 0x210143, 0x0}, + { 0x11043, 0x0}, + { 0x111043, 0x0}, + { 0x211043, 0x0}, + { 0x11143, 0x0}, + { 0x111143, 0x0}, + { 0x211143, 0x0}, + { 0x12043, 0x0}, + { 0x112043, 0x0}, + { 0x212043, 0x0}, + { 0x12143, 0x0}, + { 0x112143, 0x0}, + { 0x212143, 0x0}, + { 0x13043, 0x0}, + { 0x113043, 0x0}, + { 0x213043, 0x0}, + { 0x13143, 0x0}, + { 0x113143, 0x0}, + { 0x213143, 0x0}, + { 0x80, 0x0}, + { 0x100080, 0x0}, + { 0x200080, 0x0}, + { 0x1080, 0x0}, + { 0x101080, 0x0}, + { 0x201080, 0x0}, + { 0x2080, 0x0}, + { 0x102080, 0x0}, + { 0x202080, 0x0}, + { 0x3080, 0x0}, + { 0x103080, 0x0}, + { 0x203080, 0x0}, + { 0x4080, 0x0}, + { 0x104080, 0x0}, + { 0x204080, 0x0}, + { 0x5080, 0x0}, + { 0x105080, 0x0}, + { 0x205080, 0x0}, + { 0x6080, 0x0}, + { 0x106080, 0x0}, + { 0x206080, 0x0}, + { 0x7080, 0x0}, + { 0x107080, 0x0}, + { 0x207080, 0x0}, + { 0x8080, 0x0}, + { 0x108080, 0x0}, + { 0x208080, 0x0}, + { 0x9080, 0x0}, + { 0x109080, 0x0}, + { 0x209080, 0x0}, + { 0x10080, 0x0}, + { 0x110080, 0x0}, + { 0x210080, 0x0}, + { 0x10180, 0x0}, + { 0x110180, 0x0}, + { 0x210180, 0x0}, + { 0x11080, 0x0}, + { 0x111080, 0x0}, + { 0x211080, 0x0}, + { 0x11180, 0x0}, + { 0x111180, 0x0}, + { 0x211180, 0x0}, + { 0x12080, 0x0}, + { 0x112080, 0x0}, + { 0x212080, 0x0}, + { 0x12180, 0x0}, + { 0x112180, 0x0}, + { 0x212180, 0x0}, + { 0x13080, 0x0}, + { 0x113080, 0x0}, + { 0x213080, 0x0}, + { 0x13180, 0x0}, + { 0x113180, 0x0}, + { 0x213180, 0x0}, + { 0x10081, 0x0}, + { 0x110081, 0x0}, + { 0x210081, 0x0}, + { 0x10181, 0x0}, + { 0x110181, 0x0}, + { 0x210181, 0x0}, + { 0x11081, 0x0}, + { 0x111081, 0x0}, + { 0x211081, 0x0}, + { 0x11181, 0x0}, + { 0x111181, 0x0}, + { 0x211181, 0x0}, + { 0x12081, 0x0}, + { 0x112081, 0x0}, + { 0x212081, 0x0}, + { 0x12181, 0x0}, + { 0x112181, 0x0}, + { 0x212181, 0x0}, + { 0x13081, 0x0}, + { 0x113081, 0x0}, + { 0x213081, 0x0}, + { 0x13181, 0x0}, + { 0x113181, 0x0}, + { 0x213181, 0x0}, + { 0x100d0, 0x0}, + { 0x1100d0, 0x0}, + { 0x2100d0, 0x0}, + { 0x101d0, 0x0}, + { 0x1101d0, 0x0}, + { 0x2101d0, 0x0}, + { 0x110d0, 0x0}, + { 0x1110d0, 0x0}, + { 0x2110d0, 0x0}, + { 0x111d0, 0x0}, + { 0x1111d0, 0x0}, + { 0x2111d0, 0x0}, + { 0x120d0, 0x0}, + { 0x1120d0, 0x0}, + { 0x2120d0, 0x0}, + { 0x121d0, 0x0}, + { 0x1121d0, 0x0}, + { 0x2121d0, 0x0}, + { 0x130d0, 0x0}, + { 0x1130d0, 0x0}, + { 0x2130d0, 0x0}, + { 0x131d0, 0x0}, + { 0x1131d0, 0x0}, + { 0x2131d0, 0x0}, + { 0x100d1, 0x0}, + { 0x1100d1, 0x0}, + { 0x2100d1, 0x0}, + { 0x101d1, 0x0}, + { 0x1101d1, 0x0}, + { 0x2101d1, 0x0}, + { 0x110d1, 0x0}, + { 0x1110d1, 0x0}, + { 0x2110d1, 0x0}, + { 0x111d1, 0x0}, + { 0x1111d1, 0x0}, + { 0x2111d1, 0x0}, + { 0x120d1, 0x0}, + { 0x1120d1, 0x0}, + { 0x2120d1, 0x0}, + { 0x121d1, 0x0}, + { 0x1121d1, 0x0}, + { 0x2121d1, 0x0}, + { 0x130d1, 0x0}, + { 0x1130d1, 0x0}, + { 0x2130d1, 0x0}, + { 0x131d1, 0x0}, + { 0x1131d1, 0x0}, + { 0x2131d1, 0x0}, + { 0x10068, 0x0}, + { 0x10168, 0x0}, + { 0x10268, 0x0}, + { 0x10368, 0x0}, + { 0x10468, 0x0}, + { 0x10568, 0x0}, + { 0x10668, 0x0}, + { 0x10768, 0x0}, + { 0x10868, 0x0}, + { 0x11068, 0x0}, + { 0x11168, 0x0}, + { 0x11268, 0x0}, + { 0x11368, 0x0}, + { 0x11468, 0x0}, + { 0x11568, 0x0}, + { 0x11668, 0x0}, + { 0x11768, 0x0}, + { 0x11868, 0x0}, + { 0x12068, 0x0}, + { 0x12168, 0x0}, + { 0x12268, 0x0}, + { 0x12368, 0x0}, + { 0x12468, 0x0}, + { 0x12568, 0x0}, + { 0x12668, 0x0}, + { 0x12768, 0x0}, + { 0x12868, 0x0}, + { 0x13068, 0x0}, + { 0x13168, 0x0}, + { 0x13268, 0x0}, + { 0x13368, 0x0}, + { 0x13468, 0x0}, + { 0x13568, 0x0}, + { 0x13668, 0x0}, + { 0x13768, 0x0}, + { 0x13868, 0x0}, + { 0x10069, 0x0}, + { 0x10169, 0x0}, + { 0x10269, 0x0}, + { 0x10369, 0x0}, + { 0x10469, 0x0}, + { 0x10569, 0x0}, + { 0x10669, 0x0}, + { 0x10769, 0x0}, + { 0x10869, 0x0}, + { 0x11069, 0x0}, + { 0x11169, 0x0}, + { 0x11269, 0x0}, + { 0x11369, 0x0}, + { 0x11469, 0x0}, + { 0x11569, 0x0}, + { 0x11669, 0x0}, + { 0x11769, 0x0}, + { 0x11869, 0x0}, + { 0x12069, 0x0}, + { 0x12169, 0x0}, + { 0x12269, 0x0}, + { 0x12369, 0x0}, + { 0x12469, 0x0}, + { 0x12569, 0x0}, + { 0x12669, 0x0}, + { 0x12769, 0x0}, + { 0x12869, 0x0}, + { 0x13069, 0x0}, + { 0x13169, 0x0}, + { 0x13269, 0x0}, + { 0x13369, 0x0}, + { 0x13469, 0x0}, + { 0x13569, 0x0}, + { 0x13669, 0x0}, + { 0x13769, 0x0}, + { 0x13869, 0x0}, + { 0x1008c, 0x0}, + { 0x11008c, 0x0}, + { 0x21008c, 0x0}, + { 0x1018c, 0x0}, + { 0x11018c, 0x0}, + { 0x21018c, 0x0}, + { 0x1108c, 0x0}, + { 0x11108c, 0x0}, + { 0x21108c, 0x0}, + { 0x1118c, 0x0}, + { 0x11118c, 0x0}, + { 0x21118c, 0x0}, + { 0x1208c, 0x0}, + { 0x11208c, 0x0}, + { 0x21208c, 0x0}, + { 0x1218c, 0x0}, + { 0x11218c, 0x0}, + { 0x21218c, 0x0}, + { 0x1308c, 0x0}, + { 0x11308c, 0x0}, + { 0x21308c, 0x0}, + { 0x1318c, 0x0}, + { 0x11318c, 0x0}, + { 0x21318c, 0x0}, + { 0x1008d, 0x0}, + { 0x11008d, 0x0}, + { 0x21008d, 0x0}, + { 0x1018d, 0x0}, + { 0x11018d, 0x0}, + { 0x21018d, 0x0}, + { 0x1108d, 0x0}, + { 0x11108d, 0x0}, + { 0x21108d, 0x0}, + { 0x1118d, 0x0}, + { 0x11118d, 0x0}, + { 0x21118d, 0x0}, + { 0x1208d, 0x0}, + { 0x11208d, 0x0}, + { 0x21208d, 0x0}, + { 0x1218d, 0x0}, + { 0x11218d, 0x0}, + { 0x21218d, 0x0}, + { 0x1308d, 0x0}, + { 0x11308d, 0x0}, + { 0x21308d, 0x0}, + { 0x1318d, 0x0}, + { 0x11318d, 0x0}, + { 0x21318d, 0x0}, + { 0x100c0, 0x0}, + { 0x1100c0, 0x0}, + { 0x2100c0, 0x0}, + { 0x101c0, 0x0}, + { 0x1101c0, 0x0}, + { 0x2101c0, 0x0}, + { 0x102c0, 0x0}, + { 0x1102c0, 0x0}, + { 0x2102c0, 0x0}, + { 0x103c0, 0x0}, + { 0x1103c0, 0x0}, + { 0x2103c0, 0x0}, + { 0x104c0, 0x0}, + { 0x1104c0, 0x0}, + { 0x2104c0, 0x0}, + { 0x105c0, 0x0}, + { 0x1105c0, 0x0}, + { 0x2105c0, 0x0}, + { 0x106c0, 0x0}, + { 0x1106c0, 0x0}, + { 0x2106c0, 0x0}, + { 0x107c0, 0x0}, + { 0x1107c0, 0x0}, + { 0x2107c0, 0x0}, + { 0x108c0, 0x0}, + { 0x1108c0, 0x0}, + { 0x2108c0, 0x0}, + { 0x110c0, 0x0}, + { 0x1110c0, 0x0}, + { 0x2110c0, 0x0}, + { 0x111c0, 0x0}, + { 0x1111c0, 0x0}, + { 0x2111c0, 0x0}, + { 0x112c0, 0x0}, + { 0x1112c0, 0x0}, + { 0x2112c0, 0x0}, + { 0x113c0, 0x0}, + { 0x1113c0, 0x0}, + { 0x2113c0, 0x0}, + { 0x114c0, 0x0}, + { 0x1114c0, 0x0}, + { 0x2114c0, 0x0}, + { 0x115c0, 0x0}, + { 0x1115c0, 0x0}, + { 0x2115c0, 0x0}, + { 0x116c0, 0x0}, + { 0x1116c0, 0x0}, + { 0x2116c0, 0x0}, + { 0x117c0, 0x0}, + { 0x1117c0, 0x0}, + { 0x2117c0, 0x0}, + { 0x118c0, 0x0}, + { 0x1118c0, 0x0}, + { 0x2118c0, 0x0}, + { 0x120c0, 0x0}, + { 0x1120c0, 0x0}, + { 0x2120c0, 0x0}, + { 0x121c0, 0x0}, + { 0x1121c0, 0x0}, + { 0x2121c0, 0x0}, + { 0x122c0, 0x0}, + { 0x1122c0, 0x0}, + { 0x2122c0, 0x0}, + { 0x123c0, 0x0}, + { 0x1123c0, 0x0}, + { 0x2123c0, 0x0}, + { 0x124c0, 0x0}, + { 0x1124c0, 0x0}, + { 0x2124c0, 0x0}, + { 0x125c0, 0x0}, + { 0x1125c0, 0x0}, + { 0x2125c0, 0x0}, + { 0x126c0, 0x0}, + { 0x1126c0, 0x0}, + { 0x2126c0, 0x0}, + { 0x127c0, 0x0}, + { 0x1127c0, 0x0}, + { 0x2127c0, 0x0}, + { 0x128c0, 0x0}, + { 0x1128c0, 0x0}, + { 0x2128c0, 0x0}, + { 0x130c0, 0x0}, + { 0x1130c0, 0x0}, + { 0x2130c0, 0x0}, + { 0x131c0, 0x0}, + { 0x1131c0, 0x0}, + { 0x2131c0, 0x0}, + { 0x132c0, 0x0}, + { 0x1132c0, 0x0}, + { 0x2132c0, 0x0}, + { 0x133c0, 0x0}, + { 0x1133c0, 0x0}, + { 0x2133c0, 0x0}, + { 0x134c0, 0x0}, + { 0x1134c0, 0x0}, + { 0x2134c0, 0x0}, + { 0x135c0, 0x0}, + { 0x1135c0, 0x0}, + { 0x2135c0, 0x0}, + { 0x136c0, 0x0}, + { 0x1136c0, 0x0}, + { 0x2136c0, 0x0}, + { 0x137c0, 0x0}, + { 0x1137c0, 0x0}, + { 0x2137c0, 0x0}, + { 0x138c0, 0x0}, + { 0x1138c0, 0x0}, + { 0x2138c0, 0x0}, + { 0x100c1, 0x0}, + { 0x1100c1, 0x0}, + { 0x2100c1, 0x0}, + { 0x101c1, 0x0}, + { 0x1101c1, 0x0}, + { 0x2101c1, 0x0}, + { 0x102c1, 0x0}, + { 0x1102c1, 0x0}, + { 0x2102c1, 0x0}, + { 0x103c1, 0x0}, + { 0x1103c1, 0x0}, + { 0x2103c1, 0x0}, + { 0x104c1, 0x0}, + { 0x1104c1, 0x0}, + { 0x2104c1, 0x0}, + { 0x105c1, 0x0}, + { 0x1105c1, 0x0}, + { 0x2105c1, 0x0}, + { 0x106c1, 0x0}, + { 0x1106c1, 0x0}, + { 0x2106c1, 0x0}, + { 0x107c1, 0x0}, + { 0x1107c1, 0x0}, + { 0x2107c1, 0x0}, + { 0x108c1, 0x0}, + { 0x1108c1, 0x0}, + { 0x2108c1, 0x0}, + { 0x110c1, 0x0}, + { 0x1110c1, 0x0}, + { 0x2110c1, 0x0}, + { 0x111c1, 0x0}, + { 0x1111c1, 0x0}, + { 0x2111c1, 0x0}, + { 0x112c1, 0x0}, + { 0x1112c1, 0x0}, + { 0x2112c1, 0x0}, + { 0x113c1, 0x0}, + { 0x1113c1, 0x0}, + { 0x2113c1, 0x0}, + { 0x114c1, 0x0}, + { 0x1114c1, 0x0}, + { 0x2114c1, 0x0}, + { 0x115c1, 0x0}, + { 0x1115c1, 0x0}, + { 0x2115c1, 0x0}, + { 0x116c1, 0x0}, + { 0x1116c1, 0x0}, + { 0x2116c1, 0x0}, + { 0x117c1, 0x0}, + { 0x1117c1, 0x0}, + { 0x2117c1, 0x0}, + { 0x118c1, 0x0}, + { 0x1118c1, 0x0}, + { 0x2118c1, 0x0}, + { 0x120c1, 0x0}, + { 0x1120c1, 0x0}, + { 0x2120c1, 0x0}, + { 0x121c1, 0x0}, + { 0x1121c1, 0x0}, + { 0x2121c1, 0x0}, + { 0x122c1, 0x0}, + { 0x1122c1, 0x0}, + { 0x2122c1, 0x0}, + { 0x123c1, 0x0}, + { 0x1123c1, 0x0}, + { 0x2123c1, 0x0}, + { 0x124c1, 0x0}, + { 0x1124c1, 0x0}, + { 0x2124c1, 0x0}, + { 0x125c1, 0x0}, + { 0x1125c1, 0x0}, + { 0x2125c1, 0x0}, + { 0x126c1, 0x0}, + { 0x1126c1, 0x0}, + { 0x2126c1, 0x0}, + { 0x127c1, 0x0}, + { 0x1127c1, 0x0}, + { 0x2127c1, 0x0}, + { 0x128c1, 0x0}, + { 0x1128c1, 0x0}, + { 0x2128c1, 0x0}, + { 0x130c1, 0x0}, + { 0x1130c1, 0x0}, + { 0x2130c1, 0x0}, + { 0x131c1, 0x0}, + { 0x1131c1, 0x0}, + { 0x2131c1, 0x0}, + { 0x132c1, 0x0}, + { 0x1132c1, 0x0}, + { 0x2132c1, 0x0}, + { 0x133c1, 0x0}, + { 0x1133c1, 0x0}, + { 0x2133c1, 0x0}, + { 0x134c1, 0x0}, + { 0x1134c1, 0x0}, + { 0x2134c1, 0x0}, + { 0x135c1, 0x0}, + { 0x1135c1, 0x0}, + { 0x2135c1, 0x0}, + { 0x136c1, 0x0}, + { 0x1136c1, 0x0}, + { 0x2136c1, 0x0}, + { 0x137c1, 0x0}, + { 0x1137c1, 0x0}, + { 0x2137c1, 0x0}, + { 0x138c1, 0x0}, + { 0x1138c1, 0x0}, + { 0x2138c1, 0x0}, + { 0x10020, 0x0}, + { 0x110020, 0x0}, + { 0x210020, 0x0}, + { 0x11020, 0x0}, + { 0x111020, 0x0}, + { 0x211020, 0x0}, + { 0x12020, 0x0}, + { 0x112020, 0x0}, + { 0x212020, 0x0}, + { 0x13020, 0x0}, + { 0x113020, 0x0}, + { 0x213020, 0x0}, + { 0x20072, 0x0}, + { 0x20073, 0x0}, + { 0x20074, 0x0}, + { 0x100aa, 0x0}, + { 0x110aa, 0x0}, + { 0x120aa, 0x0}, + { 0x130aa, 0x0}, + { 0x20010, 0x0}, + { 0x120010, 0x0}, + { 0x220010, 0x0}, + { 0x20011, 0x0}, + { 0x120011, 0x0}, + { 0x220011, 0x0}, + { 0x100ae, 0x0}, + { 0x1100ae, 0x0}, + { 0x2100ae, 0x0}, + { 0x100af, 0x0}, + { 0x1100af, 0x0}, + { 0x2100af, 0x0}, + { 0x110ae, 0x0}, + { 0x1110ae, 0x0}, + { 0x2110ae, 0x0}, + { 0x110af, 0x0}, + { 0x1110af, 0x0}, + { 0x2110af, 0x0}, + { 0x120ae, 0x0}, + { 0x1120ae, 0x0}, + { 0x2120ae, 0x0}, + { 0x120af, 0x0}, + { 0x1120af, 0x0}, + { 0x2120af, 0x0}, + { 0x130ae, 0x0}, + { 0x1130ae, 0x0}, + { 0x2130ae, 0x0}, + { 0x130af, 0x0}, + { 0x1130af, 0x0}, + { 0x2130af, 0x0}, + { 0x20020, 0x0}, + { 0x120020, 0x0}, + { 0x220020, 0x0}, + { 0x100a0, 0x0}, + { 0x100a1, 0x0}, + { 0x100a2, 0x0}, + { 0x100a3, 0x0}, + { 0x100a4, 0x0}, + { 0x100a5, 0x0}, + { 0x100a6, 0x0}, + { 0x100a7, 0x0}, + { 0x110a0, 0x0}, + { 0x110a1, 0x0}, + { 0x110a2, 0x0}, + { 0x110a3, 0x0}, + { 0x110a4, 0x0}, + { 0x110a5, 0x0}, + { 0x110a6, 0x0}, + { 0x110a7, 0x0}, + { 0x120a0, 0x0}, + { 0x120a1, 0x0}, + { 0x120a2, 0x0}, + { 0x120a3, 0x0}, + { 0x120a4, 0x0}, + { 0x120a5, 0x0}, + { 0x120a6, 0x0}, + { 0x120a7, 0x0}, + { 0x130a0, 0x0}, + { 0x130a1, 0x0}, + { 0x130a2, 0x0}, + { 0x130a3, 0x0}, + { 0x130a4, 0x0}, + { 0x130a5, 0x0}, + { 0x130a6, 0x0}, + { 0x130a7, 0x0}, + { 0x2007c, 0x0}, + { 0x12007c, 0x0}, + { 0x22007c, 0x0}, + { 0x2007d, 0x0}, + { 0x12007d, 0x0}, + { 0x22007d, 0x0}, + { 0x400fd, 0x0}, + { 0x400c0, 0x0}, + { 0x90201, 0x0}, + { 0x190201, 0x0}, + { 0x290201, 0x0}, + { 0x90202, 0x0}, + { 0x190202, 0x0}, + { 0x290202, 0x0}, + { 0x90203, 0x0}, + { 0x190203, 0x0}, + { 0x290203, 0x0}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x90205, 0x0}, + { 0x190205, 0x0}, + { 0x290205, 0x0}, + { 0x90206, 0x0}, + { 0x190206, 0x0}, + { 0x290206, 0x0}, + { 0x90207, 0x0}, + { 0x190207, 0x0}, + { 0x290207, 0x0}, + { 0x90208, 0x0}, + { 0x190208, 0x0}, + { 0x290208, 0x0}, + { 0x10062, 0x0}, + { 0x10162, 0x0}, + { 0x10262, 0x0}, + { 0x10362, 0x0}, + { 0x10462, 0x0}, + { 0x10562, 0x0}, + { 0x10662, 0x0}, + { 0x10762, 0x0}, + { 0x10862, 0x0}, + { 0x11062, 0x0}, + { 0x11162, 0x0}, + { 0x11262, 0x0}, + { 0x11362, 0x0}, + { 0x11462, 0x0}, + { 0x11562, 0x0}, + { 0x11662, 0x0}, + { 0x11762, 0x0}, + { 0x11862, 0x0}, + { 0x12062, 0x0}, + { 0x12162, 0x0}, + { 0x12262, 0x0}, + { 0x12362, 0x0}, + { 0x12462, 0x0}, + { 0x12562, 0x0}, + { 0x12662, 0x0}, + { 0x12762, 0x0}, + { 0x12862, 0x0}, + { 0x13062, 0x0}, + { 0x13162, 0x0}, + { 0x13262, 0x0}, + { 0x13362, 0x0}, + { 0x13462, 0x0}, + { 0x13562, 0x0}, + { 0x13662, 0x0}, + { 0x13762, 0x0}, + { 0x13862, 0x0}, + { 0x20077, 0x0}, + { 0x10001, 0x0}, + { 0x11001, 0x0}, + { 0x12001, 0x0}, + { 0x13001, 0x0}, + { 0x10040, 0x0}, + { 0x10140, 0x0}, + { 0x10240, 0x0}, + { 0x10340, 0x0}, + { 0x10440, 0x0}, + { 0x10540, 0x0}, + { 0x10640, 0x0}, + { 0x10740, 0x0}, + { 0x10840, 0x0}, + { 0x10030, 0x0}, + { 0x10130, 0x0}, + { 0x10230, 0x0}, + { 0x10330, 0x0}, + { 0x10430, 0x0}, + { 0x10530, 0x0}, + { 0x10630, 0x0}, + { 0x10730, 0x0}, + { 0x10830, 0x0}, + { 0x11040, 0x0}, + { 0x11140, 0x0}, + { 0x11240, 0x0}, + { 0x11340, 0x0}, + { 0x11440, 0x0}, + { 0x11540, 0x0}, + { 0x11640, 0x0}, + { 0x11740, 0x0}, + { 0x11840, 0x0}, + { 0x11030, 0x0}, + { 0x11130, 0x0}, + { 0x11230, 0x0}, + { 0x11330, 0x0}, + { 0x11430, 0x0}, + { 0x11530, 0x0}, + { 0x11630, 0x0}, + { 0x11730, 0x0}, + { 0x11830, 0x0}, + { 0x12040, 0x0}, + { 0x12140, 0x0}, + { 0x12240, 0x0}, + { 0x12340, 0x0}, + { 0x12440, 0x0}, + { 0x12540, 0x0}, + { 0x12640, 0x0}, + { 0x12740, 0x0}, + { 0x12840, 0x0}, + { 0x12030, 0x0}, + { 0x12130, 0x0}, + { 0x12230, 0x0}, + { 0x12330, 0x0}, + { 0x12430, 0x0}, + { 0x12530, 0x0}, + { 0x12630, 0x0}, + { 0x12730, 0x0}, + { 0x12830, 0x0}, + { 0x13040, 0x0}, + { 0x13140, 0x0}, + { 0x13240, 0x0}, + { 0x13340, 0x0}, + { 0x13440, 0x0}, + { 0x13540, 0x0}, + { 0x13640, 0x0}, + { 0x13740, 0x0}, + { 0x13840, 0x0}, + { 0x13030, 0x0}, + { 0x13130, 0x0}, + { 0x13230, 0x0}, + { 0x13330, 0x0}, + { 0x13430, 0x0}, + { 0x13530, 0x0}, + { 0x13630, 0x0}, + { 0x13730, 0x0}, + { 0x13830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x24c4}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xc400}, + {0x54033, 0x3124}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0xc400}, + {0x54039, 0x3124}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x101}, + {0x54003, 0x190}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x84}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x84}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0x8400}, + {0x54033, 0x3100}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0x8400}, + {0x54039, 0x3100}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x64}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x84}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x84}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0x8400}, + {0x54033, 0x3100}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0x8400}, + {0x54039, 0x3100}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54010, 0x1f7f}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x24c4}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xc400}, + {0x54033, 0x3124}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0xc400}, + {0x54039, 0x3124}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xf}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x630}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x630}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x630}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x630}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x630}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x630}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x630}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x630}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x630}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x630}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x630}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x630}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x630}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xa}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x2}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x900a4, 0x10}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x623}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x623}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x790}, + {0x900a9, 0x11a}, + {0x900aa, 0x8}, + {0x900ab, 0x7aa}, + {0x900ac, 0x2a}, + {0x900ad, 0x10}, + {0x900ae, 0x7b2}, + {0x900af, 0x2a}, + {0x900b0, 0x0}, + {0x900b1, 0x7c8}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x0}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xc}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x0}, + {0x90169, 0x8}, + {0x9016a, 0x8}, + {0x9016b, 0x448}, + {0x9016c, 0x109}, + {0x9016d, 0xf}, + {0x9016e, 0x7c0}, + {0x9016f, 0x109}, + {0x90170, 0x0}, + {0x90171, 0xe8}, + {0x90172, 0x109}, + {0x90173, 0x47}, + {0x90174, 0x630}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0x618}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0xe0}, + {0x9017b, 0x109}, + {0x9017c, 0x0}, + {0x9017d, 0x7c8}, + {0x9017e, 0x109}, + {0x9017f, 0x8}, + {0x90180, 0x8140}, + {0x90181, 0x10c}, + {0x90182, 0x0}, + {0x90183, 0x1}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x4}, + {0x90187, 0x8}, + {0x90188, 0x8}, + {0x90189, 0x7c8}, + {0x9018a, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2a}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x4b}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x60}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x220010, 0x5a}, + {0x220011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x12011, 0x1}, + {0x12012, 0x1}, + {0x12013, 0x180}, + {0x12018, 0x1}, + {0x12002, 0x6209}, + {0x120b2, 0x1}, + {0x121b4, 0x1}, + {0x122b4, 0x1}, + {0x123b4, 0x1}, + {0x124b4, 0x1}, + {0x125b4, 0x1}, + {0x126b4, 0x1}, + {0x127b4, 0x1}, + {0x128b4, 0x1}, + {0x13011, 0x1}, + {0x13012, 0x1}, + {0x13013, 0x180}, + {0x13018, 0x1}, + {0x13002, 0x6209}, + {0x130b2, 0x1}, + {0x131b4, 0x1}, + {0x132b4, 0x1}, + {0x133b4, 0x1}, + {0x134b4, 0x1}, + {0x135b4, 0x1}, + {0x136b4, 0x1}, + {0x137b4, 0x1}, + {0x138b4, 0x1}, + {0x2003a, 0x2}, + {0xc0080, 0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_01061010 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 400, 100, }, +}; + diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c new file mode 100644 index 000000000..5141c04f1 --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c @@ -0,0 +1,1847 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <common.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304, 0x1}, + {0x3d400030, 0x1}, + {0x3d400000, 0xa1080020}, + {0x3d400020, 0x223}, + {0x3d400024, 0x3a980}, + {0x3d400064, 0x5b00d2}, + {0x3d4000d0, 0xc00305ba}, + {0x3d4000d4, 0x940000}, + {0x3d4000dc, 0xd4002d}, + {0x3d4000e0, 0x310000}, + {0x3d4000e8, 0x66004d}, + {0x3d4000ec, 0x16004d}, + {0x3d400100, 0x191e1920}, + {0x3d400104, 0x60630}, + {0x3d40010c, 0xb0b000}, + {0x3d400110, 0xe04080e}, + {0x3d400114, 0x2040c0c}, + {0x3d400118, 0x1010007}, + {0x3d40011c, 0x401}, + {0x3d400130, 0x20600}, + {0x3d400134, 0xc100002}, + {0x3d400138, 0xd8}, + {0x3d400144, 0x96004b}, + {0x3d400180, 0x2ee0017}, + {0x3d400184, 0x2605b8e}, + {0x3d400188, 0x0}, + {0x3d400190, 0x497820a}, + {0x3d400194, 0x80303}, + {0x3d4001b4, 0x170a}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0xdf00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x11}, + {0x3d4001c0, 0x1}, + {0x3d4001c4, 0x0}, + {0x3d4000f4, 0xc99}, + {0x3d400108, 0x70e1617}, + {0x3d400200, 0x1f}, + {0x3d40020c, 0x0}, + {0x3d400210, 0x1f1f}, + {0x3d400204, 0x80808}, + {0x3d400214, 0x7070707}, + {0x3d400218, 0x7070707}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x2c}, + {0x3d40025c, 0x4000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x2005574}, + {0x3d400400, 0x111}, + {0x3d400408, 0x72ff}, + {0x3d400494, 0x2100e07}, + {0x3d400498, 0x620096}, + {0x3d40049c, 0x1100e07}, + {0x3d4004a0, 0xc8012c}, + {0x3d402020, 0x21}, + {0x3d402024, 0x7d00}, + {0x3d402050, 0x20d040}, + {0x3d402064, 0xc001c}, + {0x3d4020dc, 0x840000}, + {0x3d4020e0, 0x310000}, + {0x3d4020e8, 0x66004d}, + {0x3d4020ec, 0x16004d}, + {0x3d402100, 0xa040305}, + {0x3d402104, 0x30407}, + {0x3d402108, 0x203060b}, + {0x3d40210c, 0x505000}, + {0x3d402110, 0x2040202}, + {0x3d402114, 0x2030202}, + {0x3d402118, 0x1010004}, + {0x3d40211c, 0x301}, + {0x3d402130, 0x20300}, + {0x3d402134, 0xa100002}, + {0x3d402138, 0x1d}, + {0x3d402144, 0x14000a}, + {0x3d402180, 0x640004}, + {0x3d402190, 0x3818200}, + {0x3d402194, 0x80303}, + {0x3d4021b4, 0x100}, + {0x3d403020, 0x21}, + {0x3d403024, 0x1f40}, + {0x3d403050, 0x20d040}, + {0x3d403064, 0x30007}, + {0x3d4030dc, 0x840000}, + {0x3d4030e0, 0x310000}, + {0x3d4030e8, 0x66004d}, + {0x3d4030ec, 0x16004d}, + {0x3d403100, 0xa010102}, + {0x3d403104, 0x30404}, + {0x3d403108, 0x203060b}, + {0x3d40310c, 0x505000}, + {0x3d403110, 0x2040202}, + {0x3d403114, 0x2030202}, + {0x3d403118, 0x1010004}, + {0x3d40311c, 0x301}, + {0x3d403130, 0x20300}, + {0x3d403134, 0xa100002}, + {0x3d403138, 0x8}, + {0x3d403144, 0x50003}, + {0x3d403180, 0x190004}, + {0x3d403190, 0x3818200}, + {0x3d403194, 0x80303}, + {0x3d4031b4, 0x100}, + {0x3d400028, 0x0}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x3}, + {0x110a3, 0x4}, + {0x110a4, 0x5}, + {0x110a5, 0x2}, + {0x110a6, 0x7}, + {0x110a7, 0x6}, + {0x120a0, 0x0}, + {0x120a1, 0x1}, + {0x120a2, 0x3}, + {0x120a3, 0x2}, + {0x120a4, 0x5}, + {0x120a5, 0x4}, + {0x120a6, 0x7}, + {0x120a7, 0x6}, + {0x130a0, 0x0}, + {0x130a1, 0x1}, + {0x130a2, 0x2}, + {0x130a3, 0x3}, + {0x130a4, 0x4}, + {0x130a5, 0x5}, + {0x130a6, 0x6}, + {0x130a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x1205f, 0x1ff}, + {0x1215f, 0x1ff}, + {0x1305f, 0x1ff}, + {0x1315f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x11205f, 0x1ff}, + {0x11215f, 0x1ff}, + {0x11305f, 0x1ff}, + {0x11315f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x21205f, 0x1ff}, + {0x21215f, 0x1ff}, + {0x21305f, 0x1ff}, + {0x21315f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x3055, 0x1ff}, + {0x4055, 0x1ff}, + {0x5055, 0x1ff}, + {0x6055, 0x1ff}, + {0x7055, 0x1ff}, + {0x8055, 0x1ff}, + {0x9055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0x7}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1ab}, + {0x2003a, 0x0}, + {0x120024, 0x1ab}, + {0x2003a, 0x0}, + {0x220024, 0x1ab}, + {0x2003a, 0x0}, + {0x20056, 0x3}, + {0x120056, 0xa}, + {0x220056, 0xa}, + {0x1004d, 0xe00}, + {0x1014d, 0xe00}, + {0x1104d, 0xe00}, + {0x1114d, 0xe00}, + {0x1204d, 0xe00}, + {0x1214d, 0xe00}, + {0x1304d, 0xe00}, + {0x1314d, 0xe00}, + {0x11004d, 0xe00}, + {0x11014d, 0xe00}, + {0x11104d, 0xe00}, + {0x11114d, 0xe00}, + {0x11204d, 0xe00}, + {0x11214d, 0xe00}, + {0x11304d, 0xe00}, + {0x11314d, 0xe00}, + {0x21004d, 0xe00}, + {0x21014d, 0xe00}, + {0x21104d, 0xe00}, + {0x21114d, 0xe00}, + {0x21204d, 0xe00}, + {0x21214d, 0xe00}, + {0x21304d, 0xe00}, + {0x21314d, 0xe00}, + {0x10049, 0xeba}, + {0x10149, 0xeba}, + {0x11049, 0xeba}, + {0x11149, 0xeba}, + {0x12049, 0xeba}, + {0x12149, 0xeba}, + {0x13049, 0xeba}, + {0x13149, 0xeba}, + {0x110049, 0xeba}, + {0x110149, 0xeba}, + {0x111049, 0xeba}, + {0x111149, 0xeba}, + {0x112049, 0xeba}, + {0x112149, 0xeba}, + {0x113049, 0xeba}, + {0x113149, 0xeba}, + {0x210049, 0xeba}, + {0x210149, 0xeba}, + {0x211049, 0xeba}, + {0x211149, 0xeba}, + {0x212049, 0xeba}, + {0x212149, 0xeba}, + {0x213049, 0xeba}, + {0x213149, 0xeba}, + {0x43, 0x63}, + {0x1043, 0x63}, + {0x2043, 0x63}, + {0x3043, 0x63}, + {0x4043, 0x63}, + {0x5043, 0x63}, + {0x6043, 0x63}, + {0x7043, 0x63}, + {0x8043, 0x63}, + {0x9043, 0x63}, + {0x20018, 0x3}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x20008, 0x2ee}, + {0x120008, 0x64}, + {0x220008, 0x19}, + {0x20088, 0x9}, + {0x200b2, 0xdc}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x12043, 0x5a1}, + {0x12143, 0x5a1}, + {0x13043, 0x5a1}, + {0x13143, 0x5a1}, + {0x1200b2, 0xdc}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x112043, 0x5a1}, + {0x112143, 0x5a1}, + {0x113043, 0x5a1}, + {0x113143, 0x5a1}, + {0x2200b2, 0xdc}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x212043, 0x5a1}, + {0x212143, 0x5a1}, + {0x213043, 0x5a1}, + {0x213143, 0x5a1}, + {0x200fa, 0x1}, + {0x1200fa, 0x1}, + {0x2200fa, 0x1}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x660}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5665}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x2200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, + {0x2200ca, 0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0}, + { 0x1200b2, 0x0}, + { 0x2200b2, 0x0}, + { 0x200cb, 0x0}, + { 0x10043, 0x0}, + { 0x110043, 0x0}, + { 0x210043, 0x0}, + { 0x10143, 0x0}, + { 0x110143, 0x0}, + { 0x210143, 0x0}, + { 0x11043, 0x0}, + { 0x111043, 0x0}, + { 0x211043, 0x0}, + { 0x11143, 0x0}, + { 0x111143, 0x0}, + { 0x211143, 0x0}, + { 0x12043, 0x0}, + { 0x112043, 0x0}, + { 0x212043, 0x0}, + { 0x12143, 0x0}, + { 0x112143, 0x0}, + { 0x212143, 0x0}, + { 0x13043, 0x0}, + { 0x113043, 0x0}, + { 0x213043, 0x0}, + { 0x13143, 0x0}, + { 0x113143, 0x0}, + { 0x213143, 0x0}, + { 0x80, 0x0}, + { 0x100080, 0x0}, + { 0x200080, 0x0}, + { 0x1080, 0x0}, + { 0x101080, 0x0}, + { 0x201080, 0x0}, + { 0x2080, 0x0}, + { 0x102080, 0x0}, + { 0x202080, 0x0}, + { 0x3080, 0x0}, + { 0x103080, 0x0}, + { 0x203080, 0x0}, + { 0x4080, 0x0}, + { 0x104080, 0x0}, + { 0x204080, 0x0}, + { 0x5080, 0x0}, + { 0x105080, 0x0}, + { 0x205080, 0x0}, + { 0x6080, 0x0}, + { 0x106080, 0x0}, + { 0x206080, 0x0}, + { 0x7080, 0x0}, + { 0x107080, 0x0}, + { 0x207080, 0x0}, + { 0x8080, 0x0}, + { 0x108080, 0x0}, + { 0x208080, 0x0}, + { 0x9080, 0x0}, + { 0x109080, 0x0}, + { 0x209080, 0x0}, + { 0x10080, 0x0}, + { 0x110080, 0x0}, + { 0x210080, 0x0}, + { 0x10180, 0x0}, + { 0x110180, 0x0}, + { 0x210180, 0x0}, + { 0x11080, 0x0}, + { 0x111080, 0x0}, + { 0x211080, 0x0}, + { 0x11180, 0x0}, + { 0x111180, 0x0}, + { 0x211180, 0x0}, + { 0x12080, 0x0}, + { 0x112080, 0x0}, + { 0x212080, 0x0}, + { 0x12180, 0x0}, + { 0x112180, 0x0}, + { 0x212180, 0x0}, + { 0x13080, 0x0}, + { 0x113080, 0x0}, + { 0x213080, 0x0}, + { 0x13180, 0x0}, + { 0x113180, 0x0}, + { 0x213180, 0x0}, + { 0x10081, 0x0}, + { 0x110081, 0x0}, + { 0x210081, 0x0}, + { 0x10181, 0x0}, + { 0x110181, 0x0}, + { 0x210181, 0x0}, + { 0x11081, 0x0}, + { 0x111081, 0x0}, + { 0x211081, 0x0}, + { 0x11181, 0x0}, + { 0x111181, 0x0}, + { 0x211181, 0x0}, + { 0x12081, 0x0}, + { 0x112081, 0x0}, + { 0x212081, 0x0}, + { 0x12181, 0x0}, + { 0x112181, 0x0}, + { 0x212181, 0x0}, + { 0x13081, 0x0}, + { 0x113081, 0x0}, + { 0x213081, 0x0}, + { 0x13181, 0x0}, + { 0x113181, 0x0}, + { 0x213181, 0x0}, + { 0x100d0, 0x0}, + { 0x1100d0, 0x0}, + { 0x2100d0, 0x0}, + { 0x101d0, 0x0}, + { 0x1101d0, 0x0}, + { 0x2101d0, 0x0}, + { 0x110d0, 0x0}, + { 0x1110d0, 0x0}, + { 0x2110d0, 0x0}, + { 0x111d0, 0x0}, + { 0x1111d0, 0x0}, + { 0x2111d0, 0x0}, + { 0x120d0, 0x0}, + { 0x1120d0, 0x0}, + { 0x2120d0, 0x0}, + { 0x121d0, 0x0}, + { 0x1121d0, 0x0}, + { 0x2121d0, 0x0}, + { 0x130d0, 0x0}, + { 0x1130d0, 0x0}, + { 0x2130d0, 0x0}, + { 0x131d0, 0x0}, + { 0x1131d0, 0x0}, + { 0x2131d0, 0x0}, + { 0x100d1, 0x0}, + { 0x1100d1, 0x0}, + { 0x2100d1, 0x0}, + { 0x101d1, 0x0}, + { 0x1101d1, 0x0}, + { 0x2101d1, 0x0}, + { 0x110d1, 0x0}, + { 0x1110d1, 0x0}, + { 0x2110d1, 0x0}, + { 0x111d1, 0x0}, + { 0x1111d1, 0x0}, + { 0x2111d1, 0x0}, + { 0x120d1, 0x0}, + { 0x1120d1, 0x0}, + { 0x2120d1, 0x0}, + { 0x121d1, 0x0}, + { 0x1121d1, 0x0}, + { 0x2121d1, 0x0}, + { 0x130d1, 0x0}, + { 0x1130d1, 0x0}, + { 0x2130d1, 0x0}, + { 0x131d1, 0x0}, + { 0x1131d1, 0x0}, + { 0x2131d1, 0x0}, + { 0x10068, 0x0}, + { 0x10168, 0x0}, + { 0x10268, 0x0}, + { 0x10368, 0x0}, + { 0x10468, 0x0}, + { 0x10568, 0x0}, + { 0x10668, 0x0}, + { 0x10768, 0x0}, + { 0x10868, 0x0}, + { 0x11068, 0x0}, + { 0x11168, 0x0}, + { 0x11268, 0x0}, + { 0x11368, 0x0}, + { 0x11468, 0x0}, + { 0x11568, 0x0}, + { 0x11668, 0x0}, + { 0x11768, 0x0}, + { 0x11868, 0x0}, + { 0x12068, 0x0}, + { 0x12168, 0x0}, + { 0x12268, 0x0}, + { 0x12368, 0x0}, + { 0x12468, 0x0}, + { 0x12568, 0x0}, + { 0x12668, 0x0}, + { 0x12768, 0x0}, + { 0x12868, 0x0}, + { 0x13068, 0x0}, + { 0x13168, 0x0}, + { 0x13268, 0x0}, + { 0x13368, 0x0}, + { 0x13468, 0x0}, + { 0x13568, 0x0}, + { 0x13668, 0x0}, + { 0x13768, 0x0}, + { 0x13868, 0x0}, + { 0x10069, 0x0}, + { 0x10169, 0x0}, + { 0x10269, 0x0}, + { 0x10369, 0x0}, + { 0x10469, 0x0}, + { 0x10569, 0x0}, + { 0x10669, 0x0}, + { 0x10769, 0x0}, + { 0x10869, 0x0}, + { 0x11069, 0x0}, + { 0x11169, 0x0}, + { 0x11269, 0x0}, + { 0x11369, 0x0}, + { 0x11469, 0x0}, + { 0x11569, 0x0}, + { 0x11669, 0x0}, + { 0x11769, 0x0}, + { 0x11869, 0x0}, + { 0x12069, 0x0}, + { 0x12169, 0x0}, + { 0x12269, 0x0}, + { 0x12369, 0x0}, + { 0x12469, 0x0}, + { 0x12569, 0x0}, + { 0x12669, 0x0}, + { 0x12769, 0x0}, + { 0x12869, 0x0}, + { 0x13069, 0x0}, + { 0x13169, 0x0}, + { 0x13269, 0x0}, + { 0x13369, 0x0}, + { 0x13469, 0x0}, + { 0x13569, 0x0}, + { 0x13669, 0x0}, + { 0x13769, 0x0}, + { 0x13869, 0x0}, + { 0x1008c, 0x0}, + { 0x11008c, 0x0}, + { 0x21008c, 0x0}, + { 0x1018c, 0x0}, + { 0x11018c, 0x0}, + { 0x21018c, 0x0}, + { 0x1108c, 0x0}, + { 0x11108c, 0x0}, + { 0x21108c, 0x0}, + { 0x1118c, 0x0}, + { 0x11118c, 0x0}, + { 0x21118c, 0x0}, + { 0x1208c, 0x0}, + { 0x11208c, 0x0}, + { 0x21208c, 0x0}, + { 0x1218c, 0x0}, + { 0x11218c, 0x0}, + { 0x21218c, 0x0}, + { 0x1308c, 0x0}, + { 0x11308c, 0x0}, + { 0x21308c, 0x0}, + { 0x1318c, 0x0}, + { 0x11318c, 0x0}, + { 0x21318c, 0x0}, + { 0x1008d, 0x0}, + { 0x11008d, 0x0}, + { 0x21008d, 0x0}, + { 0x1018d, 0x0}, + { 0x11018d, 0x0}, + { 0x21018d, 0x0}, + { 0x1108d, 0x0}, + { 0x11108d, 0x0}, + { 0x21108d, 0x0}, + { 0x1118d, 0x0}, + { 0x11118d, 0x0}, + { 0x21118d, 0x0}, + { 0x1208d, 0x0}, + { 0x11208d, 0x0}, + { 0x21208d, 0x0}, + { 0x1218d, 0x0}, + { 0x11218d, 0x0}, + { 0x21218d, 0x0}, + { 0x1308d, 0x0}, + { 0x11308d, 0x0}, + { 0x21308d, 0x0}, + { 0x1318d, 0x0}, + { 0x11318d, 0x0}, + { 0x21318d, 0x0}, + { 0x100c0, 0x0}, + { 0x1100c0, 0x0}, + { 0x2100c0, 0x0}, + { 0x101c0, 0x0}, + { 0x1101c0, 0x0}, + { 0x2101c0, 0x0}, + { 0x102c0, 0x0}, + { 0x1102c0, 0x0}, + { 0x2102c0, 0x0}, + { 0x103c0, 0x0}, + { 0x1103c0, 0x0}, + { 0x2103c0, 0x0}, + { 0x104c0, 0x0}, + { 0x1104c0, 0x0}, + { 0x2104c0, 0x0}, + { 0x105c0, 0x0}, + { 0x1105c0, 0x0}, + { 0x2105c0, 0x0}, + { 0x106c0, 0x0}, + { 0x1106c0, 0x0}, + { 0x2106c0, 0x0}, + { 0x107c0, 0x0}, + { 0x1107c0, 0x0}, + { 0x2107c0, 0x0}, + { 0x108c0, 0x0}, + { 0x1108c0, 0x0}, + { 0x2108c0, 0x0}, + { 0x110c0, 0x0}, + { 0x1110c0, 0x0}, + { 0x2110c0, 0x0}, + { 0x111c0, 0x0}, + { 0x1111c0, 0x0}, + { 0x2111c0, 0x0}, + { 0x112c0, 0x0}, + { 0x1112c0, 0x0}, + { 0x2112c0, 0x0}, + { 0x113c0, 0x0}, + { 0x1113c0, 0x0}, + { 0x2113c0, 0x0}, + { 0x114c0, 0x0}, + { 0x1114c0, 0x0}, + { 0x2114c0, 0x0}, + { 0x115c0, 0x0}, + { 0x1115c0, 0x0}, + { 0x2115c0, 0x0}, + { 0x116c0, 0x0}, + { 0x1116c0, 0x0}, + { 0x2116c0, 0x0}, + { 0x117c0, 0x0}, + { 0x1117c0, 0x0}, + { 0x2117c0, 0x0}, + { 0x118c0, 0x0}, + { 0x1118c0, 0x0}, + { 0x2118c0, 0x0}, + { 0x120c0, 0x0}, + { 0x1120c0, 0x0}, + { 0x2120c0, 0x0}, + { 0x121c0, 0x0}, + { 0x1121c0, 0x0}, + { 0x2121c0, 0x0}, + { 0x122c0, 0x0}, + { 0x1122c0, 0x0}, + { 0x2122c0, 0x0}, + { 0x123c0, 0x0}, + { 0x1123c0, 0x0}, + { 0x2123c0, 0x0}, + { 0x124c0, 0x0}, + { 0x1124c0, 0x0}, + { 0x2124c0, 0x0}, + { 0x125c0, 0x0}, + { 0x1125c0, 0x0}, + { 0x2125c0, 0x0}, + { 0x126c0, 0x0}, + { 0x1126c0, 0x0}, + { 0x2126c0, 0x0}, + { 0x127c0, 0x0}, + { 0x1127c0, 0x0}, + { 0x2127c0, 0x0}, + { 0x128c0, 0x0}, + { 0x1128c0, 0x0}, + { 0x2128c0, 0x0}, + { 0x130c0, 0x0}, + { 0x1130c0, 0x0}, + { 0x2130c0, 0x0}, + { 0x131c0, 0x0}, + { 0x1131c0, 0x0}, + { 0x2131c0, 0x0}, + { 0x132c0, 0x0}, + { 0x1132c0, 0x0}, + { 0x2132c0, 0x0}, + { 0x133c0, 0x0}, + { 0x1133c0, 0x0}, + { 0x2133c0, 0x0}, + { 0x134c0, 0x0}, + { 0x1134c0, 0x0}, + { 0x2134c0, 0x0}, + { 0x135c0, 0x0}, + { 0x1135c0, 0x0}, + { 0x2135c0, 0x0}, + { 0x136c0, 0x0}, + { 0x1136c0, 0x0}, + { 0x2136c0, 0x0}, + { 0x137c0, 0x0}, + { 0x1137c0, 0x0}, + { 0x2137c0, 0x0}, + { 0x138c0, 0x0}, + { 0x1138c0, 0x0}, + { 0x2138c0, 0x0}, + { 0x100c1, 0x0}, + { 0x1100c1, 0x0}, + { 0x2100c1, 0x0}, + { 0x101c1, 0x0}, + { 0x1101c1, 0x0}, + { 0x2101c1, 0x0}, + { 0x102c1, 0x0}, + { 0x1102c1, 0x0}, + { 0x2102c1, 0x0}, + { 0x103c1, 0x0}, + { 0x1103c1, 0x0}, + { 0x2103c1, 0x0}, + { 0x104c1, 0x0}, + { 0x1104c1, 0x0}, + { 0x2104c1, 0x0}, + { 0x105c1, 0x0}, + { 0x1105c1, 0x0}, + { 0x2105c1, 0x0}, + { 0x106c1, 0x0}, + { 0x1106c1, 0x0}, + { 0x2106c1, 0x0}, + { 0x107c1, 0x0}, + { 0x1107c1, 0x0}, + { 0x2107c1, 0x0}, + { 0x108c1, 0x0}, + { 0x1108c1, 0x0}, + { 0x2108c1, 0x0}, + { 0x110c1, 0x0}, + { 0x1110c1, 0x0}, + { 0x2110c1, 0x0}, + { 0x111c1, 0x0}, + { 0x1111c1, 0x0}, + { 0x2111c1, 0x0}, + { 0x112c1, 0x0}, + { 0x1112c1, 0x0}, + { 0x2112c1, 0x0}, + { 0x113c1, 0x0}, + { 0x1113c1, 0x0}, + { 0x2113c1, 0x0}, + { 0x114c1, 0x0}, + { 0x1114c1, 0x0}, + { 0x2114c1, 0x0}, + { 0x115c1, 0x0}, + { 0x1115c1, 0x0}, + { 0x2115c1, 0x0}, + { 0x116c1, 0x0}, + { 0x1116c1, 0x0}, + { 0x2116c1, 0x0}, + { 0x117c1, 0x0}, + { 0x1117c1, 0x0}, + { 0x2117c1, 0x0}, + { 0x118c1, 0x0}, + { 0x1118c1, 0x0}, + { 0x2118c1, 0x0}, + { 0x120c1, 0x0}, + { 0x1120c1, 0x0}, + { 0x2120c1, 0x0}, + { 0x121c1, 0x0}, + { 0x1121c1, 0x0}, + { 0x2121c1, 0x0}, + { 0x122c1, 0x0}, + { 0x1122c1, 0x0}, + { 0x2122c1, 0x0}, + { 0x123c1, 0x0}, + { 0x1123c1, 0x0}, + { 0x2123c1, 0x0}, + { 0x124c1, 0x0}, + { 0x1124c1, 0x0}, + { 0x2124c1, 0x0}, + { 0x125c1, 0x0}, + { 0x1125c1, 0x0}, + { 0x2125c1, 0x0}, + { 0x126c1, 0x0}, + { 0x1126c1, 0x0}, + { 0x2126c1, 0x0}, + { 0x127c1, 0x0}, + { 0x1127c1, 0x0}, + { 0x2127c1, 0x0}, + { 0x128c1, 0x0}, + { 0x1128c1, 0x0}, + { 0x2128c1, 0x0}, + { 0x130c1, 0x0}, + { 0x1130c1, 0x0}, + { 0x2130c1, 0x0}, + { 0x131c1, 0x0}, + { 0x1131c1, 0x0}, + { 0x2131c1, 0x0}, + { 0x132c1, 0x0}, + { 0x1132c1, 0x0}, + { 0x2132c1, 0x0}, + { 0x133c1, 0x0}, + { 0x1133c1, 0x0}, + { 0x2133c1, 0x0}, + { 0x134c1, 0x0}, + { 0x1134c1, 0x0}, + { 0x2134c1, 0x0}, + { 0x135c1, 0x0}, + { 0x1135c1, 0x0}, + { 0x2135c1, 0x0}, + { 0x136c1, 0x0}, + { 0x1136c1, 0x0}, + { 0x2136c1, 0x0}, + { 0x137c1, 0x0}, + { 0x1137c1, 0x0}, + { 0x2137c1, 0x0}, + { 0x138c1, 0x0}, + { 0x1138c1, 0x0}, + { 0x2138c1, 0x0}, + { 0x10020, 0x0}, + { 0x110020, 0x0}, + { 0x210020, 0x0}, + { 0x11020, 0x0}, + { 0x111020, 0x0}, + { 0x211020, 0x0}, + { 0x12020, 0x0}, + { 0x112020, 0x0}, + { 0x212020, 0x0}, + { 0x13020, 0x0}, + { 0x113020, 0x0}, + { 0x213020, 0x0}, + { 0x20072, 0x0}, + { 0x20073, 0x0}, + { 0x20074, 0x0}, + { 0x100aa, 0x0}, + { 0x110aa, 0x0}, + { 0x120aa, 0x0}, + { 0x130aa, 0x0}, + { 0x20010, 0x0}, + { 0x120010, 0x0}, + { 0x220010, 0x0}, + { 0x20011, 0x0}, + { 0x120011, 0x0}, + { 0x220011, 0x0}, + { 0x100ae, 0x0}, + { 0x1100ae, 0x0}, + { 0x2100ae, 0x0}, + { 0x100af, 0x0}, + { 0x1100af, 0x0}, + { 0x2100af, 0x0}, + { 0x110ae, 0x0}, + { 0x1110ae, 0x0}, + { 0x2110ae, 0x0}, + { 0x110af, 0x0}, + { 0x1110af, 0x0}, + { 0x2110af, 0x0}, + { 0x120ae, 0x0}, + { 0x1120ae, 0x0}, + { 0x2120ae, 0x0}, + { 0x120af, 0x0}, + { 0x1120af, 0x0}, + { 0x2120af, 0x0}, + { 0x130ae, 0x0}, + { 0x1130ae, 0x0}, + { 0x2130ae, 0x0}, + { 0x130af, 0x0}, + { 0x1130af, 0x0}, + { 0x2130af, 0x0}, + { 0x20020, 0x0}, + { 0x120020, 0x0}, + { 0x220020, 0x0}, + { 0x100a0, 0x0}, + { 0x100a1, 0x0}, + { 0x100a2, 0x0}, + { 0x100a3, 0x0}, + { 0x100a4, 0x0}, + { 0x100a5, 0x0}, + { 0x100a6, 0x0}, + { 0x100a7, 0x0}, + { 0x110a0, 0x0}, + { 0x110a1, 0x0}, + { 0x110a2, 0x0}, + { 0x110a3, 0x0}, + { 0x110a4, 0x0}, + { 0x110a5, 0x0}, + { 0x110a6, 0x0}, + { 0x110a7, 0x0}, + { 0x120a0, 0x0}, + { 0x120a1, 0x0}, + { 0x120a2, 0x0}, + { 0x120a3, 0x0}, + { 0x120a4, 0x0}, + { 0x120a5, 0x0}, + { 0x120a6, 0x0}, + { 0x120a7, 0x0}, + { 0x130a0, 0x0}, + { 0x130a1, 0x0}, + { 0x130a2, 0x0}, + { 0x130a3, 0x0}, + { 0x130a4, 0x0}, + { 0x130a5, 0x0}, + { 0x130a6, 0x0}, + { 0x130a7, 0x0}, + { 0x2007c, 0x0}, + { 0x12007c, 0x0}, + { 0x22007c, 0x0}, + { 0x2007d, 0x0}, + { 0x12007d, 0x0}, + { 0x22007d, 0x0}, + { 0x400fd, 0x0}, + { 0x400c0, 0x0}, + { 0x90201, 0x0}, + { 0x190201, 0x0}, + { 0x290201, 0x0}, + { 0x90202, 0x0}, + { 0x190202, 0x0}, + { 0x290202, 0x0}, + { 0x90203, 0x0}, + { 0x190203, 0x0}, + { 0x290203, 0x0}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x90205, 0x0}, + { 0x190205, 0x0}, + { 0x290205, 0x0}, + { 0x90206, 0x0}, + { 0x190206, 0x0}, + { 0x290206, 0x0}, + { 0x90207, 0x0}, + { 0x190207, 0x0}, + { 0x290207, 0x0}, + { 0x90208, 0x0}, + { 0x190208, 0x0}, + { 0x290208, 0x0}, + { 0x10062, 0x0}, + { 0x10162, 0x0}, + { 0x10262, 0x0}, + { 0x10362, 0x0}, + { 0x10462, 0x0}, + { 0x10562, 0x0}, + { 0x10662, 0x0}, + { 0x10762, 0x0}, + { 0x10862, 0x0}, + { 0x11062, 0x0}, + { 0x11162, 0x0}, + { 0x11262, 0x0}, + { 0x11362, 0x0}, + { 0x11462, 0x0}, + { 0x11562, 0x0}, + { 0x11662, 0x0}, + { 0x11762, 0x0}, + { 0x11862, 0x0}, + { 0x12062, 0x0}, + { 0x12162, 0x0}, + { 0x12262, 0x0}, + { 0x12362, 0x0}, + { 0x12462, 0x0}, + { 0x12562, 0x0}, + { 0x12662, 0x0}, + { 0x12762, 0x0}, + { 0x12862, 0x0}, + { 0x13062, 0x0}, + { 0x13162, 0x0}, + { 0x13262, 0x0}, + { 0x13362, 0x0}, + { 0x13462, 0x0}, + { 0x13562, 0x0}, + { 0x13662, 0x0}, + { 0x13762, 0x0}, + { 0x13862, 0x0}, + { 0x20077, 0x0}, + { 0x10001, 0x0}, + { 0x11001, 0x0}, + { 0x12001, 0x0}, + { 0x13001, 0x0}, + { 0x10040, 0x0}, + { 0x10140, 0x0}, + { 0x10240, 0x0}, + { 0x10340, 0x0}, + { 0x10440, 0x0}, + { 0x10540, 0x0}, + { 0x10640, 0x0}, + { 0x10740, 0x0}, + { 0x10840, 0x0}, + { 0x10030, 0x0}, + { 0x10130, 0x0}, + { 0x10230, 0x0}, + { 0x10330, 0x0}, + { 0x10430, 0x0}, + { 0x10530, 0x0}, + { 0x10630, 0x0}, + { 0x10730, 0x0}, + { 0x10830, 0x0}, + { 0x11040, 0x0}, + { 0x11140, 0x0}, + { 0x11240, 0x0}, + { 0x11340, 0x0}, + { 0x11440, 0x0}, + { 0x11540, 0x0}, + { 0x11640, 0x0}, + { 0x11740, 0x0}, + { 0x11840, 0x0}, + { 0x11030, 0x0}, + { 0x11130, 0x0}, + { 0x11230, 0x0}, + { 0x11330, 0x0}, + { 0x11430, 0x0}, + { 0x11530, 0x0}, + { 0x11630, 0x0}, + { 0x11730, 0x0}, + { 0x11830, 0x0}, + { 0x12040, 0x0}, + { 0x12140, 0x0}, + { 0x12240, 0x0}, + { 0x12340, 0x0}, + { 0x12440, 0x0}, + { 0x12540, 0x0}, + { 0x12640, 0x0}, + { 0x12740, 0x0}, + { 0x12840, 0x0}, + { 0x12030, 0x0}, + { 0x12130, 0x0}, + { 0x12230, 0x0}, + { 0x12330, 0x0}, + { 0x12430, 0x0}, + { 0x12530, 0x0}, + { 0x12630, 0x0}, + { 0x12730, 0x0}, + { 0x12830, 0x0}, + { 0x13040, 0x0}, + { 0x13140, 0x0}, + { 0x13240, 0x0}, + { 0x13340, 0x0}, + { 0x13440, 0x0}, + { 0x13540, 0x0}, + { 0x13640, 0x0}, + { 0x13740, 0x0}, + { 0x13840, 0x0}, + { 0x13030, 0x0}, + { 0x13130, 0x0}, + { 0x13230, 0x0}, + { 0x13330, 0x0}, + { 0x13430, 0x0}, + { 0x13530, 0x0}, + { 0x13630, 0x0}, + { 0x13730, 0x0}, + { 0x13830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xbb8}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x2dd4}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x2dd4}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xd400}, + {0x54033, 0x312d}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0xd400}, + {0x54039, 0x312d}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x101}, + {0x54003, 0x190}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x84}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x84}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0x8400}, + {0x54033, 0x3100}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0x8400}, + {0x54039, 0x3100}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x64}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x84}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x84}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0x8400}, + {0x54033, 0x3100}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0x8400}, + {0x54039, 0x3100}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xbb8}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54010, 0x1f7f}, + {0x54012, 0x110}, + {0x54019, 0x2dd4}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x2dd4}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x1}, + {0x54032, 0xd400}, + {0x54033, 0x312d}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0xd400}, + {0x54039, 0x312d}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xf}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x630}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x630}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x630}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x630}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x630}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x630}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x630}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x630}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x630}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x630}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x630}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x630}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x630}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xa}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x2}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x900a4, 0x10}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x623}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x623}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x790}, + {0x900a9, 0x11a}, + {0x900aa, 0x8}, + {0x900ab, 0x7aa}, + {0x900ac, 0x2a}, + {0x900ad, 0x10}, + {0x900ae, 0x7b2}, + {0x900af, 0x2a}, + {0x900b0, 0x0}, + {0x900b1, 0x7c8}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x0}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xc}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x0}, + {0x90169, 0x8}, + {0x9016a, 0x8}, + {0x9016b, 0x448}, + {0x9016c, 0x109}, + {0x9016d, 0xf}, + {0x9016e, 0x7c0}, + {0x9016f, 0x109}, + {0x90170, 0x0}, + {0x90171, 0xe8}, + {0x90172, 0x109}, + {0x90173, 0x47}, + {0x90174, 0x630}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0x618}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0xe0}, + {0x9017b, 0x109}, + {0x9017c, 0x0}, + {0x9017d, 0x7c8}, + {0x9017e, 0x109}, + {0x9017f, 0x8}, + {0x90180, 0x8140}, + {0x90181, 0x10c}, + {0x90182, 0x0}, + {0x90183, 0x1}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x4}, + {0x90187, 0x8}, + {0x90188, 0x8}, + {0x90189, 0x7c8}, + {0x9018a, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2a}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x5d}, + {0x2000c, 0xbb}, + {0x2000d, 0x753}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x60}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x220010, 0x5a}, + {0x220011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x12011, 0x1}, + {0x12012, 0x1}, + {0x12013, 0x180}, + {0x12018, 0x1}, + {0x12002, 0x6209}, + {0x120b2, 0x1}, + {0x121b4, 0x1}, + {0x122b4, 0x1}, + {0x123b4, 0x1}, + {0x124b4, 0x1}, + {0x125b4, 0x1}, + {0x126b4, 0x1}, + {0x127b4, 0x1}, + {0x128b4, 0x1}, + {0x13011, 0x1}, + {0x13012, 0x1}, + {0x13013, 0x180}, + {0x13018, 0x1}, + {0x13002, 0x6209}, + {0x130b2, 0x1}, + {0x131b4, 0x1}, + {0x132b4, 0x1}, + {0x133b4, 0x1}, + {0x134b4, 0x1}, + {0x135b4, 0x1}, + {0x136b4, 0x1}, + {0x137b4, 0x1}, + {0x138b4, 0x1}, + {0x2003a, 0x2}, + {0xc0080, 0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_01061010 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c new file mode 100644 index 000000000..233472249 --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c @@ -0,0 +1,1847 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <common.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304, 0x1}, + {0x3d400030, 0x1}, + {0x3d400000, 0xa3080020}, + {0x3d400020, 0x223}, + {0x3d400024, 0x3a980}, + {0x3d400064, 0x5b00d2}, + {0x3d4000d0, 0xc00305ba}, + {0x3d4000d4, 0x940000}, + {0x3d4000dc, 0xd4002d}, + {0x3d4000e0, 0x310000}, + {0x3d4000e8, 0x66004d}, + {0x3d4000ec, 0x16004d}, + {0x3d400100, 0x191e1920}, + {0x3d400104, 0x60630}, + {0x3d40010c, 0xb0b000}, + {0x3d400110, 0xe04080e}, + {0x3d400114, 0x2040c0c}, + {0x3d400118, 0x1010007}, + {0x3d40011c, 0x401}, + {0x3d400130, 0x20600}, + {0x3d400134, 0xc100002}, + {0x3d400138, 0xd8}, + {0x3d400144, 0x96004b}, + {0x3d400180, 0x2ee0017}, + {0x3d400184, 0x2605b8e}, + {0x3d400188, 0x0}, + {0x3d400190, 0x497820a}, + {0x3d400194, 0x80303}, + {0x3d4001b4, 0x170a}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0xdf00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x11}, + {0x3d4001c0, 0x1}, + {0x3d4001c4, 0x0}, + {0x3d4000f4, 0xc99}, + {0x3d400108, 0x70e1617}, + {0x3d400200, 0x17}, + {0x3d40020c, 0x0}, + {0x3d400210, 0x1f1f}, + {0x3d400204, 0x80808}, + {0x3d400214, 0x7070707}, + {0x3d400218, 0x7070707}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x2c}, + {0x3d40025c, 0x4000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x2005574}, + {0x3d400400, 0x111}, + {0x3d400408, 0x72ff}, + {0x3d400494, 0x2100e07}, + {0x3d400498, 0x620096}, + {0x3d40049c, 0x1100e07}, + {0x3d4004a0, 0xc8012c}, + {0x3d402020, 0x21}, + {0x3d402024, 0x7d00}, + {0x3d402050, 0x20d040}, + {0x3d402064, 0xc001c}, + {0x3d4020dc, 0x840000}, + {0x3d4020e0, 0x310000}, + {0x3d4020e8, 0x66004d}, + {0x3d4020ec, 0x16004d}, + {0x3d402100, 0xa040305}, + {0x3d402104, 0x30407}, + {0x3d402108, 0x203060b}, + {0x3d40210c, 0x505000}, + {0x3d402110, 0x2040202}, + {0x3d402114, 0x2030202}, + {0x3d402118, 0x1010004}, + {0x3d40211c, 0x301}, + {0x3d402130, 0x20300}, + {0x3d402134, 0xa100002}, + {0x3d402138, 0x1d}, + {0x3d402144, 0x14000a}, + {0x3d402180, 0x640004}, + {0x3d402190, 0x3818200}, + {0x3d402194, 0x80303}, + {0x3d4021b4, 0x100}, + {0x3d403020, 0x21}, + {0x3d403024, 0x1f40}, + {0x3d403050, 0x20d040}, + {0x3d403064, 0x30007}, + {0x3d4030dc, 0x840000}, + {0x3d4030e0, 0x310000}, + {0x3d4030e8, 0x66004d}, + {0x3d4030ec, 0x16004d}, + {0x3d403100, 0xa010102}, + {0x3d403104, 0x30404}, + {0x3d403108, 0x203060b}, + {0x3d40310c, 0x505000}, + {0x3d403110, 0x2040202}, + {0x3d403114, 0x2030202}, + {0x3d403118, 0x1010004}, + {0x3d40311c, 0x301}, + {0x3d403130, 0x20300}, + {0x3d403134, 0xa100002}, + {0x3d403138, 0x8}, + {0x3d403144, 0x50003}, + {0x3d403180, 0x190004}, + {0x3d403190, 0x3818200}, + {0x3d403194, 0x80303}, + {0x3d4031b4, 0x100}, + {0x3d400028, 0x0}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x3}, + {0x110a3, 0x4}, + {0x110a4, 0x5}, + {0x110a5, 0x2}, + {0x110a6, 0x7}, + {0x110a7, 0x6}, + {0x120a0, 0x0}, + {0x120a1, 0x1}, + {0x120a2, 0x3}, + {0x120a3, 0x2}, + {0x120a4, 0x5}, + {0x120a5, 0x4}, + {0x120a6, 0x7}, + {0x120a7, 0x6}, + {0x130a0, 0x0}, + {0x130a1, 0x1}, + {0x130a2, 0x2}, + {0x130a3, 0x3}, + {0x130a4, 0x4}, + {0x130a5, 0x5}, + {0x130a6, 0x6}, + {0x130a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x1205f, 0x1ff}, + {0x1215f, 0x1ff}, + {0x1305f, 0x1ff}, + {0x1315f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x11205f, 0x1ff}, + {0x11215f, 0x1ff}, + {0x11305f, 0x1ff}, + {0x11315f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x21205f, 0x1ff}, + {0x21215f, 0x1ff}, + {0x21305f, 0x1ff}, + {0x21315f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x3055, 0x1ff}, + {0x4055, 0x1ff}, + {0x5055, 0x1ff}, + {0x6055, 0x1ff}, + {0x7055, 0x1ff}, + {0x8055, 0x1ff}, + {0x9055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0x7}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1ab}, + {0x2003a, 0x0}, + {0x120024, 0x1ab}, + {0x2003a, 0x0}, + {0x220024, 0x1ab}, + {0x2003a, 0x0}, + {0x20056, 0x3}, + {0x120056, 0xa}, + {0x220056, 0xa}, + {0x1004d, 0xe00}, + {0x1014d, 0xe00}, + {0x1104d, 0xe00}, + {0x1114d, 0xe00}, + {0x1204d, 0xe00}, + {0x1214d, 0xe00}, + {0x1304d, 0xe00}, + {0x1314d, 0xe00}, + {0x11004d, 0xe00}, + {0x11014d, 0xe00}, + {0x11104d, 0xe00}, + {0x11114d, 0xe00}, + {0x11204d, 0xe00}, + {0x11214d, 0xe00}, + {0x11304d, 0xe00}, + {0x11314d, 0xe00}, + {0x21004d, 0xe00}, + {0x21014d, 0xe00}, + {0x21104d, 0xe00}, + {0x21114d, 0xe00}, + {0x21204d, 0xe00}, + {0x21214d, 0xe00}, + {0x21304d, 0xe00}, + {0x21314d, 0xe00}, + {0x10049, 0xeba}, + {0x10149, 0xeba}, + {0x11049, 0xeba}, + {0x11149, 0xeba}, + {0x12049, 0xeba}, + {0x12149, 0xeba}, + {0x13049, 0xeba}, + {0x13149, 0xeba}, + {0x110049, 0xeba}, + {0x110149, 0xeba}, + {0x111049, 0xeba}, + {0x111149, 0xeba}, + {0x112049, 0xeba}, + {0x112149, 0xeba}, + {0x113049, 0xeba}, + {0x113149, 0xeba}, + {0x210049, 0xeba}, + {0x210149, 0xeba}, + {0x211049, 0xeba}, + {0x211149, 0xeba}, + {0x212049, 0xeba}, + {0x212149, 0xeba}, + {0x213049, 0xeba}, + {0x213149, 0xeba}, + {0x43, 0x63}, + {0x1043, 0x63}, + {0x2043, 0x63}, + {0x3043, 0x63}, + {0x4043, 0x63}, + {0x5043, 0x63}, + {0x6043, 0x63}, + {0x7043, 0x63}, + {0x8043, 0x63}, + {0x9043, 0x63}, + {0x20018, 0x3}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x20008, 0x2ee}, + {0x120008, 0x64}, + {0x220008, 0x19}, + {0x20088, 0x9}, + {0x200b2, 0xdc}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x12043, 0x5a1}, + {0x12143, 0x5a1}, + {0x13043, 0x5a1}, + {0x13143, 0x5a1}, + {0x1200b2, 0xdc}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x112043, 0x5a1}, + {0x112143, 0x5a1}, + {0x113043, 0x5a1}, + {0x113143, 0x5a1}, + {0x2200b2, 0xdc}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x212043, 0x5a1}, + {0x212143, 0x5a1}, + {0x213043, 0x5a1}, + {0x213143, 0x5a1}, + {0x200fa, 0x1}, + {0x1200fa, 0x1}, + {0x2200fa, 0x1}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x660}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5665}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x2200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, + {0x2200ca, 0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0}, + { 0x1200b2, 0x0}, + { 0x2200b2, 0x0}, + { 0x200cb, 0x0}, + { 0x10043, 0x0}, + { 0x110043, 0x0}, + { 0x210043, 0x0}, + { 0x10143, 0x0}, + { 0x110143, 0x0}, + { 0x210143, 0x0}, + { 0x11043, 0x0}, + { 0x111043, 0x0}, + { 0x211043, 0x0}, + { 0x11143, 0x0}, + { 0x111143, 0x0}, + { 0x211143, 0x0}, + { 0x12043, 0x0}, + { 0x112043, 0x0}, + { 0x212043, 0x0}, + { 0x12143, 0x0}, + { 0x112143, 0x0}, + { 0x212143, 0x0}, + { 0x13043, 0x0}, + { 0x113043, 0x0}, + { 0x213043, 0x0}, + { 0x13143, 0x0}, + { 0x113143, 0x0}, + { 0x213143, 0x0}, + { 0x80, 0x0}, + { 0x100080, 0x0}, + { 0x200080, 0x0}, + { 0x1080, 0x0}, + { 0x101080, 0x0}, + { 0x201080, 0x0}, + { 0x2080, 0x0}, + { 0x102080, 0x0}, + { 0x202080, 0x0}, + { 0x3080, 0x0}, + { 0x103080, 0x0}, + { 0x203080, 0x0}, + { 0x4080, 0x0}, + { 0x104080, 0x0}, + { 0x204080, 0x0}, + { 0x5080, 0x0}, + { 0x105080, 0x0}, + { 0x205080, 0x0}, + { 0x6080, 0x0}, + { 0x106080, 0x0}, + { 0x206080, 0x0}, + { 0x7080, 0x0}, + { 0x107080, 0x0}, + { 0x207080, 0x0}, + { 0x8080, 0x0}, + { 0x108080, 0x0}, + { 0x208080, 0x0}, + { 0x9080, 0x0}, + { 0x109080, 0x0}, + { 0x209080, 0x0}, + { 0x10080, 0x0}, + { 0x110080, 0x0}, + { 0x210080, 0x0}, + { 0x10180, 0x0}, + { 0x110180, 0x0}, + { 0x210180, 0x0}, + { 0x11080, 0x0}, + { 0x111080, 0x0}, + { 0x211080, 0x0}, + { 0x11180, 0x0}, + { 0x111180, 0x0}, + { 0x211180, 0x0}, + { 0x12080, 0x0}, + { 0x112080, 0x0}, + { 0x212080, 0x0}, + { 0x12180, 0x0}, + { 0x112180, 0x0}, + { 0x212180, 0x0}, + { 0x13080, 0x0}, + { 0x113080, 0x0}, + { 0x213080, 0x0}, + { 0x13180, 0x0}, + { 0x113180, 0x0}, + { 0x213180, 0x0}, + { 0x10081, 0x0}, + { 0x110081, 0x0}, + { 0x210081, 0x0}, + { 0x10181, 0x0}, + { 0x110181, 0x0}, + { 0x210181, 0x0}, + { 0x11081, 0x0}, + { 0x111081, 0x0}, + { 0x211081, 0x0}, + { 0x11181, 0x0}, + { 0x111181, 0x0}, + { 0x211181, 0x0}, + { 0x12081, 0x0}, + { 0x112081, 0x0}, + { 0x212081, 0x0}, + { 0x12181, 0x0}, + { 0x112181, 0x0}, + { 0x212181, 0x0}, + { 0x13081, 0x0}, + { 0x113081, 0x0}, + { 0x213081, 0x0}, + { 0x13181, 0x0}, + { 0x113181, 0x0}, + { 0x213181, 0x0}, + { 0x100d0, 0x0}, + { 0x1100d0, 0x0}, + { 0x2100d0, 0x0}, + { 0x101d0, 0x0}, + { 0x1101d0, 0x0}, + { 0x2101d0, 0x0}, + { 0x110d0, 0x0}, + { 0x1110d0, 0x0}, + { 0x2110d0, 0x0}, + { 0x111d0, 0x0}, + { 0x1111d0, 0x0}, + { 0x2111d0, 0x0}, + { 0x120d0, 0x0}, + { 0x1120d0, 0x0}, + { 0x2120d0, 0x0}, + { 0x121d0, 0x0}, + { 0x1121d0, 0x0}, + { 0x2121d0, 0x0}, + { 0x130d0, 0x0}, + { 0x1130d0, 0x0}, + { 0x2130d0, 0x0}, + { 0x131d0, 0x0}, + { 0x1131d0, 0x0}, + { 0x2131d0, 0x0}, + { 0x100d1, 0x0}, + { 0x1100d1, 0x0}, + { 0x2100d1, 0x0}, + { 0x101d1, 0x0}, + { 0x1101d1, 0x0}, + { 0x2101d1, 0x0}, + { 0x110d1, 0x0}, + { 0x1110d1, 0x0}, + { 0x2110d1, 0x0}, + { 0x111d1, 0x0}, + { 0x1111d1, 0x0}, + { 0x2111d1, 0x0}, + { 0x120d1, 0x0}, + { 0x1120d1, 0x0}, + { 0x2120d1, 0x0}, + { 0x121d1, 0x0}, + { 0x1121d1, 0x0}, + { 0x2121d1, 0x0}, + { 0x130d1, 0x0}, + { 0x1130d1, 0x0}, + { 0x2130d1, 0x0}, + { 0x131d1, 0x0}, + { 0x1131d1, 0x0}, + { 0x2131d1, 0x0}, + { 0x10068, 0x0}, + { 0x10168, 0x0}, + { 0x10268, 0x0}, + { 0x10368, 0x0}, + { 0x10468, 0x0}, + { 0x10568, 0x0}, + { 0x10668, 0x0}, + { 0x10768, 0x0}, + { 0x10868, 0x0}, + { 0x11068, 0x0}, + { 0x11168, 0x0}, + { 0x11268, 0x0}, + { 0x11368, 0x0}, + { 0x11468, 0x0}, + { 0x11568, 0x0}, + { 0x11668, 0x0}, + { 0x11768, 0x0}, + { 0x11868, 0x0}, + { 0x12068, 0x0}, + { 0x12168, 0x0}, + { 0x12268, 0x0}, + { 0x12368, 0x0}, + { 0x12468, 0x0}, + { 0x12568, 0x0}, + { 0x12668, 0x0}, + { 0x12768, 0x0}, + { 0x12868, 0x0}, + { 0x13068, 0x0}, + { 0x13168, 0x0}, + { 0x13268, 0x0}, + { 0x13368, 0x0}, + { 0x13468, 0x0}, + { 0x13568, 0x0}, + { 0x13668, 0x0}, + { 0x13768, 0x0}, + { 0x13868, 0x0}, + { 0x10069, 0x0}, + { 0x10169, 0x0}, + { 0x10269, 0x0}, + { 0x10369, 0x0}, + { 0x10469, 0x0}, + { 0x10569, 0x0}, + { 0x10669, 0x0}, + { 0x10769, 0x0}, + { 0x10869, 0x0}, + { 0x11069, 0x0}, + { 0x11169, 0x0}, + { 0x11269, 0x0}, + { 0x11369, 0x0}, + { 0x11469, 0x0}, + { 0x11569, 0x0}, + { 0x11669, 0x0}, + { 0x11769, 0x0}, + { 0x11869, 0x0}, + { 0x12069, 0x0}, + { 0x12169, 0x0}, + { 0x12269, 0x0}, + { 0x12369, 0x0}, + { 0x12469, 0x0}, + { 0x12569, 0x0}, + { 0x12669, 0x0}, + { 0x12769, 0x0}, + { 0x12869, 0x0}, + { 0x13069, 0x0}, + { 0x13169, 0x0}, + { 0x13269, 0x0}, + { 0x13369, 0x0}, + { 0x13469, 0x0}, + { 0x13569, 0x0}, + { 0x13669, 0x0}, + { 0x13769, 0x0}, + { 0x13869, 0x0}, + { 0x1008c, 0x0}, + { 0x11008c, 0x0}, + { 0x21008c, 0x0}, + { 0x1018c, 0x0}, + { 0x11018c, 0x0}, + { 0x21018c, 0x0}, + { 0x1108c, 0x0}, + { 0x11108c, 0x0}, + { 0x21108c, 0x0}, + { 0x1118c, 0x0}, + { 0x11118c, 0x0}, + { 0x21118c, 0x0}, + { 0x1208c, 0x0}, + { 0x11208c, 0x0}, + { 0x21208c, 0x0}, + { 0x1218c, 0x0}, + { 0x11218c, 0x0}, + { 0x21218c, 0x0}, + { 0x1308c, 0x0}, + { 0x11308c, 0x0}, + { 0x21308c, 0x0}, + { 0x1318c, 0x0}, + { 0x11318c, 0x0}, + { 0x21318c, 0x0}, + { 0x1008d, 0x0}, + { 0x11008d, 0x0}, + { 0x21008d, 0x0}, + { 0x1018d, 0x0}, + { 0x11018d, 0x0}, + { 0x21018d, 0x0}, + { 0x1108d, 0x0}, + { 0x11108d, 0x0}, + { 0x21108d, 0x0}, + { 0x1118d, 0x0}, + { 0x11118d, 0x0}, + { 0x21118d, 0x0}, + { 0x1208d, 0x0}, + { 0x11208d, 0x0}, + { 0x21208d, 0x0}, + { 0x1218d, 0x0}, + { 0x11218d, 0x0}, + { 0x21218d, 0x0}, + { 0x1308d, 0x0}, + { 0x11308d, 0x0}, + { 0x21308d, 0x0}, + { 0x1318d, 0x0}, + { 0x11318d, 0x0}, + { 0x21318d, 0x0}, + { 0x100c0, 0x0}, + { 0x1100c0, 0x0}, + { 0x2100c0, 0x0}, + { 0x101c0, 0x0}, + { 0x1101c0, 0x0}, + { 0x2101c0, 0x0}, + { 0x102c0, 0x0}, + { 0x1102c0, 0x0}, + { 0x2102c0, 0x0}, + { 0x103c0, 0x0}, + { 0x1103c0, 0x0}, + { 0x2103c0, 0x0}, + { 0x104c0, 0x0}, + { 0x1104c0, 0x0}, + { 0x2104c0, 0x0}, + { 0x105c0, 0x0}, + { 0x1105c0, 0x0}, + { 0x2105c0, 0x0}, + { 0x106c0, 0x0}, + { 0x1106c0, 0x0}, + { 0x2106c0, 0x0}, + { 0x107c0, 0x0}, + { 0x1107c0, 0x0}, + { 0x2107c0, 0x0}, + { 0x108c0, 0x0}, + { 0x1108c0, 0x0}, + { 0x2108c0, 0x0}, + { 0x110c0, 0x0}, + { 0x1110c0, 0x0}, + { 0x2110c0, 0x0}, + { 0x111c0, 0x0}, + { 0x1111c0, 0x0}, + { 0x2111c0, 0x0}, + { 0x112c0, 0x0}, + { 0x1112c0, 0x0}, + { 0x2112c0, 0x0}, + { 0x113c0, 0x0}, + { 0x1113c0, 0x0}, + { 0x2113c0, 0x0}, + { 0x114c0, 0x0}, + { 0x1114c0, 0x0}, + { 0x2114c0, 0x0}, + { 0x115c0, 0x0}, + { 0x1115c0, 0x0}, + { 0x2115c0, 0x0}, + { 0x116c0, 0x0}, + { 0x1116c0, 0x0}, + { 0x2116c0, 0x0}, + { 0x117c0, 0x0}, + { 0x1117c0, 0x0}, + { 0x2117c0, 0x0}, + { 0x118c0, 0x0}, + { 0x1118c0, 0x0}, + { 0x2118c0, 0x0}, + { 0x120c0, 0x0}, + { 0x1120c0, 0x0}, + { 0x2120c0, 0x0}, + { 0x121c0, 0x0}, + { 0x1121c0, 0x0}, + { 0x2121c0, 0x0}, + { 0x122c0, 0x0}, + { 0x1122c0, 0x0}, + { 0x2122c0, 0x0}, + { 0x123c0, 0x0}, + { 0x1123c0, 0x0}, + { 0x2123c0, 0x0}, + { 0x124c0, 0x0}, + { 0x1124c0, 0x0}, + { 0x2124c0, 0x0}, + { 0x125c0, 0x0}, + { 0x1125c0, 0x0}, + { 0x2125c0, 0x0}, + { 0x126c0, 0x0}, + { 0x1126c0, 0x0}, + { 0x2126c0, 0x0}, + { 0x127c0, 0x0}, + { 0x1127c0, 0x0}, + { 0x2127c0, 0x0}, + { 0x128c0, 0x0}, + { 0x1128c0, 0x0}, + { 0x2128c0, 0x0}, + { 0x130c0, 0x0}, + { 0x1130c0, 0x0}, + { 0x2130c0, 0x0}, + { 0x131c0, 0x0}, + { 0x1131c0, 0x0}, + { 0x2131c0, 0x0}, + { 0x132c0, 0x0}, + { 0x1132c0, 0x0}, + { 0x2132c0, 0x0}, + { 0x133c0, 0x0}, + { 0x1133c0, 0x0}, + { 0x2133c0, 0x0}, + { 0x134c0, 0x0}, + { 0x1134c0, 0x0}, + { 0x2134c0, 0x0}, + { 0x135c0, 0x0}, + { 0x1135c0, 0x0}, + { 0x2135c0, 0x0}, + { 0x136c0, 0x0}, + { 0x1136c0, 0x0}, + { 0x2136c0, 0x0}, + { 0x137c0, 0x0}, + { 0x1137c0, 0x0}, + { 0x2137c0, 0x0}, + { 0x138c0, 0x0}, + { 0x1138c0, 0x0}, + { 0x2138c0, 0x0}, + { 0x100c1, 0x0}, + { 0x1100c1, 0x0}, + { 0x2100c1, 0x0}, + { 0x101c1, 0x0}, + { 0x1101c1, 0x0}, + { 0x2101c1, 0x0}, + { 0x102c1, 0x0}, + { 0x1102c1, 0x0}, + { 0x2102c1, 0x0}, + { 0x103c1, 0x0}, + { 0x1103c1, 0x0}, + { 0x2103c1, 0x0}, + { 0x104c1, 0x0}, + { 0x1104c1, 0x0}, + { 0x2104c1, 0x0}, + { 0x105c1, 0x0}, + { 0x1105c1, 0x0}, + { 0x2105c1, 0x0}, + { 0x106c1, 0x0}, + { 0x1106c1, 0x0}, + { 0x2106c1, 0x0}, + { 0x107c1, 0x0}, + { 0x1107c1, 0x0}, + { 0x2107c1, 0x0}, + { 0x108c1, 0x0}, + { 0x1108c1, 0x0}, + { 0x2108c1, 0x0}, + { 0x110c1, 0x0}, + { 0x1110c1, 0x0}, + { 0x2110c1, 0x0}, + { 0x111c1, 0x0}, + { 0x1111c1, 0x0}, + { 0x2111c1, 0x0}, + { 0x112c1, 0x0}, + { 0x1112c1, 0x0}, + { 0x2112c1, 0x0}, + { 0x113c1, 0x0}, + { 0x1113c1, 0x0}, + { 0x2113c1, 0x0}, + { 0x114c1, 0x0}, + { 0x1114c1, 0x0}, + { 0x2114c1, 0x0}, + { 0x115c1, 0x0}, + { 0x1115c1, 0x0}, + { 0x2115c1, 0x0}, + { 0x116c1, 0x0}, + { 0x1116c1, 0x0}, + { 0x2116c1, 0x0}, + { 0x117c1, 0x0}, + { 0x1117c1, 0x0}, + { 0x2117c1, 0x0}, + { 0x118c1, 0x0}, + { 0x1118c1, 0x0}, + { 0x2118c1, 0x0}, + { 0x120c1, 0x0}, + { 0x1120c1, 0x0}, + { 0x2120c1, 0x0}, + { 0x121c1, 0x0}, + { 0x1121c1, 0x0}, + { 0x2121c1, 0x0}, + { 0x122c1, 0x0}, + { 0x1122c1, 0x0}, + { 0x2122c1, 0x0}, + { 0x123c1, 0x0}, + { 0x1123c1, 0x0}, + { 0x2123c1, 0x0}, + { 0x124c1, 0x0}, + { 0x1124c1, 0x0}, + { 0x2124c1, 0x0}, + { 0x125c1, 0x0}, + { 0x1125c1, 0x0}, + { 0x2125c1, 0x0}, + { 0x126c1, 0x0}, + { 0x1126c1, 0x0}, + { 0x2126c1, 0x0}, + { 0x127c1, 0x0}, + { 0x1127c1, 0x0}, + { 0x2127c1, 0x0}, + { 0x128c1, 0x0}, + { 0x1128c1, 0x0}, + { 0x2128c1, 0x0}, + { 0x130c1, 0x0}, + { 0x1130c1, 0x0}, + { 0x2130c1, 0x0}, + { 0x131c1, 0x0}, + { 0x1131c1, 0x0}, + { 0x2131c1, 0x0}, + { 0x132c1, 0x0}, + { 0x1132c1, 0x0}, + { 0x2132c1, 0x0}, + { 0x133c1, 0x0}, + { 0x1133c1, 0x0}, + { 0x2133c1, 0x0}, + { 0x134c1, 0x0}, + { 0x1134c1, 0x0}, + { 0x2134c1, 0x0}, + { 0x135c1, 0x0}, + { 0x1135c1, 0x0}, + { 0x2135c1, 0x0}, + { 0x136c1, 0x0}, + { 0x1136c1, 0x0}, + { 0x2136c1, 0x0}, + { 0x137c1, 0x0}, + { 0x1137c1, 0x0}, + { 0x2137c1, 0x0}, + { 0x138c1, 0x0}, + { 0x1138c1, 0x0}, + { 0x2138c1, 0x0}, + { 0x10020, 0x0}, + { 0x110020, 0x0}, + { 0x210020, 0x0}, + { 0x11020, 0x0}, + { 0x111020, 0x0}, + { 0x211020, 0x0}, + { 0x12020, 0x0}, + { 0x112020, 0x0}, + { 0x212020, 0x0}, + { 0x13020, 0x0}, + { 0x113020, 0x0}, + { 0x213020, 0x0}, + { 0x20072, 0x0}, + { 0x20073, 0x0}, + { 0x20074, 0x0}, + { 0x100aa, 0x0}, + { 0x110aa, 0x0}, + { 0x120aa, 0x0}, + { 0x130aa, 0x0}, + { 0x20010, 0x0}, + { 0x120010, 0x0}, + { 0x220010, 0x0}, + { 0x20011, 0x0}, + { 0x120011, 0x0}, + { 0x220011, 0x0}, + { 0x100ae, 0x0}, + { 0x1100ae, 0x0}, + { 0x2100ae, 0x0}, + { 0x100af, 0x0}, + { 0x1100af, 0x0}, + { 0x2100af, 0x0}, + { 0x110ae, 0x0}, + { 0x1110ae, 0x0}, + { 0x2110ae, 0x0}, + { 0x110af, 0x0}, + { 0x1110af, 0x0}, + { 0x2110af, 0x0}, + { 0x120ae, 0x0}, + { 0x1120ae, 0x0}, + { 0x2120ae, 0x0}, + { 0x120af, 0x0}, + { 0x1120af, 0x0}, + { 0x2120af, 0x0}, + { 0x130ae, 0x0}, + { 0x1130ae, 0x0}, + { 0x2130ae, 0x0}, + { 0x130af, 0x0}, + { 0x1130af, 0x0}, + { 0x2130af, 0x0}, + { 0x20020, 0x0}, + { 0x120020, 0x0}, + { 0x220020, 0x0}, + { 0x100a0, 0x0}, + { 0x100a1, 0x0}, + { 0x100a2, 0x0}, + { 0x100a3, 0x0}, + { 0x100a4, 0x0}, + { 0x100a5, 0x0}, + { 0x100a6, 0x0}, + { 0x100a7, 0x0}, + { 0x110a0, 0x0}, + { 0x110a1, 0x0}, + { 0x110a2, 0x0}, + { 0x110a3, 0x0}, + { 0x110a4, 0x0}, + { 0x110a5, 0x0}, + { 0x110a6, 0x0}, + { 0x110a7, 0x0}, + { 0x120a0, 0x0}, + { 0x120a1, 0x0}, + { 0x120a2, 0x0}, + { 0x120a3, 0x0}, + { 0x120a4, 0x0}, + { 0x120a5, 0x0}, + { 0x120a6, 0x0}, + { 0x120a7, 0x0}, + { 0x130a0, 0x0}, + { 0x130a1, 0x0}, + { 0x130a2, 0x0}, + { 0x130a3, 0x0}, + { 0x130a4, 0x0}, + { 0x130a5, 0x0}, + { 0x130a6, 0x0}, + { 0x130a7, 0x0}, + { 0x2007c, 0x0}, + { 0x12007c, 0x0}, + { 0x22007c, 0x0}, + { 0x2007d, 0x0}, + { 0x12007d, 0x0}, + { 0x22007d, 0x0}, + { 0x400fd, 0x0}, + { 0x400c0, 0x0}, + { 0x90201, 0x0}, + { 0x190201, 0x0}, + { 0x290201, 0x0}, + { 0x90202, 0x0}, + { 0x190202, 0x0}, + { 0x290202, 0x0}, + { 0x90203, 0x0}, + { 0x190203, 0x0}, + { 0x290203, 0x0}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x90205, 0x0}, + { 0x190205, 0x0}, + { 0x290205, 0x0}, + { 0x90206, 0x0}, + { 0x190206, 0x0}, + { 0x290206, 0x0}, + { 0x90207, 0x0}, + { 0x190207, 0x0}, + { 0x290207, 0x0}, + { 0x90208, 0x0}, + { 0x190208, 0x0}, + { 0x290208, 0x0}, + { 0x10062, 0x0}, + { 0x10162, 0x0}, + { 0x10262, 0x0}, + { 0x10362, 0x0}, + { 0x10462, 0x0}, + { 0x10562, 0x0}, + { 0x10662, 0x0}, + { 0x10762, 0x0}, + { 0x10862, 0x0}, + { 0x11062, 0x0}, + { 0x11162, 0x0}, + { 0x11262, 0x0}, + { 0x11362, 0x0}, + { 0x11462, 0x0}, + { 0x11562, 0x0}, + { 0x11662, 0x0}, + { 0x11762, 0x0}, + { 0x11862, 0x0}, + { 0x12062, 0x0}, + { 0x12162, 0x0}, + { 0x12262, 0x0}, + { 0x12362, 0x0}, + { 0x12462, 0x0}, + { 0x12562, 0x0}, + { 0x12662, 0x0}, + { 0x12762, 0x0}, + { 0x12862, 0x0}, + { 0x13062, 0x0}, + { 0x13162, 0x0}, + { 0x13262, 0x0}, + { 0x13362, 0x0}, + { 0x13462, 0x0}, + { 0x13562, 0x0}, + { 0x13662, 0x0}, + { 0x13762, 0x0}, + { 0x13862, 0x0}, + { 0x20077, 0x0}, + { 0x10001, 0x0}, + { 0x11001, 0x0}, + { 0x12001, 0x0}, + { 0x13001, 0x0}, + { 0x10040, 0x0}, + { 0x10140, 0x0}, + { 0x10240, 0x0}, + { 0x10340, 0x0}, + { 0x10440, 0x0}, + { 0x10540, 0x0}, + { 0x10640, 0x0}, + { 0x10740, 0x0}, + { 0x10840, 0x0}, + { 0x10030, 0x0}, + { 0x10130, 0x0}, + { 0x10230, 0x0}, + { 0x10330, 0x0}, + { 0x10430, 0x0}, + { 0x10530, 0x0}, + { 0x10630, 0x0}, + { 0x10730, 0x0}, + { 0x10830, 0x0}, + { 0x11040, 0x0}, + { 0x11140, 0x0}, + { 0x11240, 0x0}, + { 0x11340, 0x0}, + { 0x11440, 0x0}, + { 0x11540, 0x0}, + { 0x11640, 0x0}, + { 0x11740, 0x0}, + { 0x11840, 0x0}, + { 0x11030, 0x0}, + { 0x11130, 0x0}, + { 0x11230, 0x0}, + { 0x11330, 0x0}, + { 0x11430, 0x0}, + { 0x11530, 0x0}, + { 0x11630, 0x0}, + { 0x11730, 0x0}, + { 0x11830, 0x0}, + { 0x12040, 0x0}, + { 0x12140, 0x0}, + { 0x12240, 0x0}, + { 0x12340, 0x0}, + { 0x12440, 0x0}, + { 0x12540, 0x0}, + { 0x12640, 0x0}, + { 0x12740, 0x0}, + { 0x12840, 0x0}, + { 0x12030, 0x0}, + { 0x12130, 0x0}, + { 0x12230, 0x0}, + { 0x12330, 0x0}, + { 0x12430, 0x0}, + { 0x12530, 0x0}, + { 0x12630, 0x0}, + { 0x12730, 0x0}, + { 0x12830, 0x0}, + { 0x13040, 0x0}, + { 0x13140, 0x0}, + { 0x13240, 0x0}, + { 0x13340, 0x0}, + { 0x13440, 0x0}, + { 0x13540, 0x0}, + { 0x13640, 0x0}, + { 0x13740, 0x0}, + { 0x13840, 0x0}, + { 0x13030, 0x0}, + { 0x13130, 0x0}, + { 0x13230, 0x0}, + { 0x13330, 0x0}, + { 0x13430, 0x0}, + { 0x13530, 0x0}, + { 0x13630, 0x0}, + { 0x13730, 0x0}, + { 0x13830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xbb8}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x310}, + {0x54019, 0x2dd4}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x2dd4}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0xd400}, + {0x54033, 0x312d}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0xd400}, + {0x54039, 0x312d}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x101}, + {0x54003, 0x190}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x310}, + {0x54019, 0x84}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x84}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0x8400}, + {0x54033, 0x3100}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0x8400}, + {0x54039, 0x3100}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x64}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x310}, + {0x54019, 0x84}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x84}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0x8400}, + {0x54033, 0x3100}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0x8400}, + {0x54039, 0x3100}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xbb8}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54010, 0x1f7f}, + {0x54012, 0x310}, + {0x54019, 0x2dd4}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x2dd4}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0xd400}, + {0x54033, 0x312d}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0xd400}, + {0x54039, 0x312d}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xf}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x630}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x630}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x630}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x630}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x630}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x630}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x630}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x630}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x630}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x630}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x630}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x630}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x630}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xa}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x2}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x900a4, 0x10}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x623}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x623}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x790}, + {0x900a9, 0x11a}, + {0x900aa, 0x8}, + {0x900ab, 0x7aa}, + {0x900ac, 0x2a}, + {0x900ad, 0x10}, + {0x900ae, 0x7b2}, + {0x900af, 0x2a}, + {0x900b0, 0x0}, + {0x900b1, 0x7c8}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x0}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xc}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x0}, + {0x90169, 0x8}, + {0x9016a, 0x8}, + {0x9016b, 0x448}, + {0x9016c, 0x109}, + {0x9016d, 0xf}, + {0x9016e, 0x7c0}, + {0x9016f, 0x109}, + {0x90170, 0x0}, + {0x90171, 0xe8}, + {0x90172, 0x109}, + {0x90173, 0x47}, + {0x90174, 0x630}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0x618}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0xe0}, + {0x9017b, 0x109}, + {0x9017c, 0x0}, + {0x9017d, 0x7c8}, + {0x9017e, 0x109}, + {0x9017f, 0x8}, + {0x90180, 0x8140}, + {0x90181, 0x10c}, + {0x90182, 0x0}, + {0x90183, 0x1}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x4}, + {0x90187, 0x8}, + {0x90188, 0x8}, + {0x90189, 0x7c8}, + {0x9018a, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2a}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x5d}, + {0x2000c, 0xbb}, + {0x2000d, 0x753}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x60}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x220010, 0x5a}, + {0x220011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x12011, 0x1}, + {0x12012, 0x1}, + {0x12013, 0x180}, + {0x12018, 0x1}, + {0x12002, 0x6209}, + {0x120b2, 0x1}, + {0x121b4, 0x1}, + {0x122b4, 0x1}, + {0x123b4, 0x1}, + {0x124b4, 0x1}, + {0x125b4, 0x1}, + {0x126b4, 0x1}, + {0x127b4, 0x1}, + {0x128b4, 0x1}, + {0x13011, 0x1}, + {0x13012, 0x1}, + {0x13013, 0x180}, + {0x13018, 0x1}, + {0x13002, 0x6209}, + {0x130b2, 0x1}, + {0x131b4, 0x1}, + {0x132b4, 0x1}, + {0x133b4, 0x1}, + {0x134b4, 0x1}, + {0x135b4, 0x1}, + {0x136b4, 0x1}, + {0x137b4, 0x1}, + {0x138b4, 0x1}, + {0x2003a, 0x2}, + {0xc0080, 0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_ff000110 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c new file mode 100644 index 000000000..e65445e01 --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c @@ -0,0 +1,1847 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include <linux/kernel.h> +#include <common.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304, 0x1}, + {0x3d400030, 0x1}, + {0x3d400000, 0xa3080020}, + {0x3d400020, 0x223}, + {0x3d400024, 0x3a980}, + {0x3d400064, 0x5b00d2}, + {0x3d4000d0, 0xc00305ba}, + {0x3d4000d4, 0x940000}, + {0x3d4000dc, 0xd4002d}, + {0x3d4000e0, 0x310000}, + {0x3d4000e8, 0x66004d}, + {0x3d4000ec, 0x16004d}, + {0x3d400100, 0x191e1920}, + {0x3d400104, 0x60630}, + {0x3d40010c, 0xb0b000}, + {0x3d400110, 0xe04080e}, + {0x3d400114, 0x2040c0c}, + {0x3d400118, 0x1010007}, + {0x3d40011c, 0x401}, + {0x3d400130, 0x20600}, + {0x3d400134, 0xc100002}, + {0x3d400138, 0xd8}, + {0x3d400144, 0x96004b}, + {0x3d400180, 0x2ee0017}, + {0x3d400184, 0x2605b8e}, + {0x3d400188, 0x0}, + {0x3d400190, 0x497820a}, + {0x3d400194, 0x80303}, + {0x3d4001b4, 0x170a}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0xdf00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x11}, + {0x3d4001c0, 0x1}, + {0x3d4001c4, 0x0}, + {0x3d4000f4, 0xc99}, + {0x3d400108, 0x70e1617}, + {0x3d400200, 0x16}, + {0x3d40020c, 0x0}, + {0x3d400210, 0x1f1f}, + {0x3d400204, 0x80808}, + {0x3d400214, 0x7070707}, + {0x3d400218, 0xf070707}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x2c}, + {0x3d40025c, 0x4000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x2005574}, + {0x3d400400, 0x111}, + {0x3d400408, 0x72ff}, + {0x3d400494, 0x2100e07}, + {0x3d400498, 0x620096}, + {0x3d40049c, 0x1100e07}, + {0x3d4004a0, 0xc8012c}, + {0x3d402020, 0x21}, + {0x3d402024, 0x7d00}, + {0x3d402050, 0x20d040}, + {0x3d402064, 0xc001c}, + {0x3d4020dc, 0x840000}, + {0x3d4020e0, 0x310000}, + {0x3d4020e8, 0x66004d}, + {0x3d4020ec, 0x16004d}, + {0x3d402100, 0xa040305}, + {0x3d402104, 0x30407}, + {0x3d402108, 0x203060b}, + {0x3d40210c, 0x505000}, + {0x3d402110, 0x2040202}, + {0x3d402114, 0x2030202}, + {0x3d402118, 0x1010004}, + {0x3d40211c, 0x301}, + {0x3d402130, 0x20300}, + {0x3d402134, 0xa100002}, + {0x3d402138, 0x1d}, + {0x3d402144, 0x14000a}, + {0x3d402180, 0x640004}, + {0x3d402190, 0x3818200}, + {0x3d402194, 0x80303}, + {0x3d4021b4, 0x100}, + {0x3d403020, 0x21}, + {0x3d403024, 0x1f40}, + {0x3d403050, 0x20d040}, + {0x3d403064, 0x30007}, + {0x3d4030dc, 0x840000}, + {0x3d4030e0, 0x310000}, + {0x3d4030e8, 0x66004d}, + {0x3d4030ec, 0x16004d}, + {0x3d403100, 0xa010102}, + {0x3d403104, 0x30404}, + {0x3d403108, 0x203060b}, + {0x3d40310c, 0x505000}, + {0x3d403110, 0x2040202}, + {0x3d403114, 0x2030202}, + {0x3d403118, 0x1010004}, + {0x3d40311c, 0x301}, + {0x3d403130, 0x20300}, + {0x3d403134, 0xa100002}, + {0x3d403138, 0x8}, + {0x3d403144, 0x50003}, + {0x3d403180, 0x190004}, + {0x3d403190, 0x3818200}, + {0x3d403194, 0x80303}, + {0x3d4031b4, 0x100}, + {0x3d400028, 0x0}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x3}, + {0x110a3, 0x4}, + {0x110a4, 0x5}, + {0x110a5, 0x2}, + {0x110a6, 0x7}, + {0x110a7, 0x6}, + {0x120a0, 0x0}, + {0x120a1, 0x1}, + {0x120a2, 0x3}, + {0x120a3, 0x2}, + {0x120a4, 0x5}, + {0x120a5, 0x4}, + {0x120a6, 0x7}, + {0x120a7, 0x6}, + {0x130a0, 0x0}, + {0x130a1, 0x1}, + {0x130a2, 0x2}, + {0x130a3, 0x3}, + {0x130a4, 0x4}, + {0x130a5, 0x5}, + {0x130a6, 0x6}, + {0x130a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x1205f, 0x1ff}, + {0x1215f, 0x1ff}, + {0x1305f, 0x1ff}, + {0x1315f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x11205f, 0x1ff}, + {0x11215f, 0x1ff}, + {0x11305f, 0x1ff}, + {0x11315f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x21205f, 0x1ff}, + {0x21215f, 0x1ff}, + {0x21305f, 0x1ff}, + {0x21315f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x3055, 0x1ff}, + {0x4055, 0x1ff}, + {0x5055, 0x1ff}, + {0x6055, 0x1ff}, + {0x7055, 0x1ff}, + {0x8055, 0x1ff}, + {0x9055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0x7}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1ab}, + {0x2003a, 0x0}, + {0x120024, 0x1ab}, + {0x2003a, 0x0}, + {0x220024, 0x1ab}, + {0x2003a, 0x0}, + {0x20056, 0x3}, + {0x120056, 0xa}, + {0x220056, 0xa}, + {0x1004d, 0xe00}, + {0x1014d, 0xe00}, + {0x1104d, 0xe00}, + {0x1114d, 0xe00}, + {0x1204d, 0xe00}, + {0x1214d, 0xe00}, + {0x1304d, 0xe00}, + {0x1314d, 0xe00}, + {0x11004d, 0xe00}, + {0x11014d, 0xe00}, + {0x11104d, 0xe00}, + {0x11114d, 0xe00}, + {0x11204d, 0xe00}, + {0x11214d, 0xe00}, + {0x11304d, 0xe00}, + {0x11314d, 0xe00}, + {0x21004d, 0xe00}, + {0x21014d, 0xe00}, + {0x21104d, 0xe00}, + {0x21114d, 0xe00}, + {0x21204d, 0xe00}, + {0x21214d, 0xe00}, + {0x21304d, 0xe00}, + {0x21314d, 0xe00}, + {0x10049, 0xeba}, + {0x10149, 0xeba}, + {0x11049, 0xeba}, + {0x11149, 0xeba}, + {0x12049, 0xeba}, + {0x12149, 0xeba}, + {0x13049, 0xeba}, + {0x13149, 0xeba}, + {0x110049, 0xeba}, + {0x110149, 0xeba}, + {0x111049, 0xeba}, + {0x111149, 0xeba}, + {0x112049, 0xeba}, + {0x112149, 0xeba}, + {0x113049, 0xeba}, + {0x113149, 0xeba}, + {0x210049, 0xeba}, + {0x210149, 0xeba}, + {0x211049, 0xeba}, + {0x211149, 0xeba}, + {0x212049, 0xeba}, + {0x212149, 0xeba}, + {0x213049, 0xeba}, + {0x213149, 0xeba}, + {0x43, 0x63}, + {0x1043, 0x63}, + {0x2043, 0x63}, + {0x3043, 0x63}, + {0x4043, 0x63}, + {0x5043, 0x63}, + {0x6043, 0x63}, + {0x7043, 0x63}, + {0x8043, 0x63}, + {0x9043, 0x63}, + {0x20018, 0x3}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x20008, 0x2ee}, + {0x120008, 0x64}, + {0x220008, 0x19}, + {0x20088, 0x9}, + {0x200b2, 0xdc}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x12043, 0x5a1}, + {0x12143, 0x5a1}, + {0x13043, 0x5a1}, + {0x13143, 0x5a1}, + {0x1200b2, 0xdc}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x112043, 0x5a1}, + {0x112143, 0x5a1}, + {0x113043, 0x5a1}, + {0x113143, 0x5a1}, + {0x2200b2, 0xdc}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x212043, 0x5a1}, + {0x212143, 0x5a1}, + {0x213043, 0x5a1}, + {0x213143, 0x5a1}, + {0x200fa, 0x1}, + {0x1200fa, 0x1}, + {0x2200fa, 0x1}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x660}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5665}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x2200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, + {0x2200ca, 0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0}, + { 0x1200b2, 0x0}, + { 0x2200b2, 0x0}, + { 0x200cb, 0x0}, + { 0x10043, 0x0}, + { 0x110043, 0x0}, + { 0x210043, 0x0}, + { 0x10143, 0x0}, + { 0x110143, 0x0}, + { 0x210143, 0x0}, + { 0x11043, 0x0}, + { 0x111043, 0x0}, + { 0x211043, 0x0}, + { 0x11143, 0x0}, + { 0x111143, 0x0}, + { 0x211143, 0x0}, + { 0x12043, 0x0}, + { 0x112043, 0x0}, + { 0x212043, 0x0}, + { 0x12143, 0x0}, + { 0x112143, 0x0}, + { 0x212143, 0x0}, + { 0x13043, 0x0}, + { 0x113043, 0x0}, + { 0x213043, 0x0}, + { 0x13143, 0x0}, + { 0x113143, 0x0}, + { 0x213143, 0x0}, + { 0x80, 0x0}, + { 0x100080, 0x0}, + { 0x200080, 0x0}, + { 0x1080, 0x0}, + { 0x101080, 0x0}, + { 0x201080, 0x0}, + { 0x2080, 0x0}, + { 0x102080, 0x0}, + { 0x202080, 0x0}, + { 0x3080, 0x0}, + { 0x103080, 0x0}, + { 0x203080, 0x0}, + { 0x4080, 0x0}, + { 0x104080, 0x0}, + { 0x204080, 0x0}, + { 0x5080, 0x0}, + { 0x105080, 0x0}, + { 0x205080, 0x0}, + { 0x6080, 0x0}, + { 0x106080, 0x0}, + { 0x206080, 0x0}, + { 0x7080, 0x0}, + { 0x107080, 0x0}, + { 0x207080, 0x0}, + { 0x8080, 0x0}, + { 0x108080, 0x0}, + { 0x208080, 0x0}, + { 0x9080, 0x0}, + { 0x109080, 0x0}, + { 0x209080, 0x0}, + { 0x10080, 0x0}, + { 0x110080, 0x0}, + { 0x210080, 0x0}, + { 0x10180, 0x0}, + { 0x110180, 0x0}, + { 0x210180, 0x0}, + { 0x11080, 0x0}, + { 0x111080, 0x0}, + { 0x211080, 0x0}, + { 0x11180, 0x0}, + { 0x111180, 0x0}, + { 0x211180, 0x0}, + { 0x12080, 0x0}, + { 0x112080, 0x0}, + { 0x212080, 0x0}, + { 0x12180, 0x0}, + { 0x112180, 0x0}, + { 0x212180, 0x0}, + { 0x13080, 0x0}, + { 0x113080, 0x0}, + { 0x213080, 0x0}, + { 0x13180, 0x0}, + { 0x113180, 0x0}, + { 0x213180, 0x0}, + { 0x10081, 0x0}, + { 0x110081, 0x0}, + { 0x210081, 0x0}, + { 0x10181, 0x0}, + { 0x110181, 0x0}, + { 0x210181, 0x0}, + { 0x11081, 0x0}, + { 0x111081, 0x0}, + { 0x211081, 0x0}, + { 0x11181, 0x0}, + { 0x111181, 0x0}, + { 0x211181, 0x0}, + { 0x12081, 0x0}, + { 0x112081, 0x0}, + { 0x212081, 0x0}, + { 0x12181, 0x0}, + { 0x112181, 0x0}, + { 0x212181, 0x0}, + { 0x13081, 0x0}, + { 0x113081, 0x0}, + { 0x213081, 0x0}, + { 0x13181, 0x0}, + { 0x113181, 0x0}, + { 0x213181, 0x0}, + { 0x100d0, 0x0}, + { 0x1100d0, 0x0}, + { 0x2100d0, 0x0}, + { 0x101d0, 0x0}, + { 0x1101d0, 0x0}, + { 0x2101d0, 0x0}, + { 0x110d0, 0x0}, + { 0x1110d0, 0x0}, + { 0x2110d0, 0x0}, + { 0x111d0, 0x0}, + { 0x1111d0, 0x0}, + { 0x2111d0, 0x0}, + { 0x120d0, 0x0}, + { 0x1120d0, 0x0}, + { 0x2120d0, 0x0}, + { 0x121d0, 0x0}, + { 0x1121d0, 0x0}, + { 0x2121d0, 0x0}, + { 0x130d0, 0x0}, + { 0x1130d0, 0x0}, + { 0x2130d0, 0x0}, + { 0x131d0, 0x0}, + { 0x1131d0, 0x0}, + { 0x2131d0, 0x0}, + { 0x100d1, 0x0}, + { 0x1100d1, 0x0}, + { 0x2100d1, 0x0}, + { 0x101d1, 0x0}, + { 0x1101d1, 0x0}, + { 0x2101d1, 0x0}, + { 0x110d1, 0x0}, + { 0x1110d1, 0x0}, + { 0x2110d1, 0x0}, + { 0x111d1, 0x0}, + { 0x1111d1, 0x0}, + { 0x2111d1, 0x0}, + { 0x120d1, 0x0}, + { 0x1120d1, 0x0}, + { 0x2120d1, 0x0}, + { 0x121d1, 0x0}, + { 0x1121d1, 0x0}, + { 0x2121d1, 0x0}, + { 0x130d1, 0x0}, + { 0x1130d1, 0x0}, + { 0x2130d1, 0x0}, + { 0x131d1, 0x0}, + { 0x1131d1, 0x0}, + { 0x2131d1, 0x0}, + { 0x10068, 0x0}, + { 0x10168, 0x0}, + { 0x10268, 0x0}, + { 0x10368, 0x0}, + { 0x10468, 0x0}, + { 0x10568, 0x0}, + { 0x10668, 0x0}, + { 0x10768, 0x0}, + { 0x10868, 0x0}, + { 0x11068, 0x0}, + { 0x11168, 0x0}, + { 0x11268, 0x0}, + { 0x11368, 0x0}, + { 0x11468, 0x0}, + { 0x11568, 0x0}, + { 0x11668, 0x0}, + { 0x11768, 0x0}, + { 0x11868, 0x0}, + { 0x12068, 0x0}, + { 0x12168, 0x0}, + { 0x12268, 0x0}, + { 0x12368, 0x0}, + { 0x12468, 0x0}, + { 0x12568, 0x0}, + { 0x12668, 0x0}, + { 0x12768, 0x0}, + { 0x12868, 0x0}, + { 0x13068, 0x0}, + { 0x13168, 0x0}, + { 0x13268, 0x0}, + { 0x13368, 0x0}, + { 0x13468, 0x0}, + { 0x13568, 0x0}, + { 0x13668, 0x0}, + { 0x13768, 0x0}, + { 0x13868, 0x0}, + { 0x10069, 0x0}, + { 0x10169, 0x0}, + { 0x10269, 0x0}, + { 0x10369, 0x0}, + { 0x10469, 0x0}, + { 0x10569, 0x0}, + { 0x10669, 0x0}, + { 0x10769, 0x0}, + { 0x10869, 0x0}, + { 0x11069, 0x0}, + { 0x11169, 0x0}, + { 0x11269, 0x0}, + { 0x11369, 0x0}, + { 0x11469, 0x0}, + { 0x11569, 0x0}, + { 0x11669, 0x0}, + { 0x11769, 0x0}, + { 0x11869, 0x0}, + { 0x12069, 0x0}, + { 0x12169, 0x0}, + { 0x12269, 0x0}, + { 0x12369, 0x0}, + { 0x12469, 0x0}, + { 0x12569, 0x0}, + { 0x12669, 0x0}, + { 0x12769, 0x0}, + { 0x12869, 0x0}, + { 0x13069, 0x0}, + { 0x13169, 0x0}, + { 0x13269, 0x0}, + { 0x13369, 0x0}, + { 0x13469, 0x0}, + { 0x13569, 0x0}, + { 0x13669, 0x0}, + { 0x13769, 0x0}, + { 0x13869, 0x0}, + { 0x1008c, 0x0}, + { 0x11008c, 0x0}, + { 0x21008c, 0x0}, + { 0x1018c, 0x0}, + { 0x11018c, 0x0}, + { 0x21018c, 0x0}, + { 0x1108c, 0x0}, + { 0x11108c, 0x0}, + { 0x21108c, 0x0}, + { 0x1118c, 0x0}, + { 0x11118c, 0x0}, + { 0x21118c, 0x0}, + { 0x1208c, 0x0}, + { 0x11208c, 0x0}, + { 0x21208c, 0x0}, + { 0x1218c, 0x0}, + { 0x11218c, 0x0}, + { 0x21218c, 0x0}, + { 0x1308c, 0x0}, + { 0x11308c, 0x0}, + { 0x21308c, 0x0}, + { 0x1318c, 0x0}, + { 0x11318c, 0x0}, + { 0x21318c, 0x0}, + { 0x1008d, 0x0}, + { 0x11008d, 0x0}, + { 0x21008d, 0x0}, + { 0x1018d, 0x0}, + { 0x11018d, 0x0}, + { 0x21018d, 0x0}, + { 0x1108d, 0x0}, + { 0x11108d, 0x0}, + { 0x21108d, 0x0}, + { 0x1118d, 0x0}, + { 0x11118d, 0x0}, + { 0x21118d, 0x0}, + { 0x1208d, 0x0}, + { 0x11208d, 0x0}, + { 0x21208d, 0x0}, + { 0x1218d, 0x0}, + { 0x11218d, 0x0}, + { 0x21218d, 0x0}, + { 0x1308d, 0x0}, + { 0x11308d, 0x0}, + { 0x21308d, 0x0}, + { 0x1318d, 0x0}, + { 0x11318d, 0x0}, + { 0x21318d, 0x0}, + { 0x100c0, 0x0}, + { 0x1100c0, 0x0}, + { 0x2100c0, 0x0}, + { 0x101c0, 0x0}, + { 0x1101c0, 0x0}, + { 0x2101c0, 0x0}, + { 0x102c0, 0x0}, + { 0x1102c0, 0x0}, + { 0x2102c0, 0x0}, + { 0x103c0, 0x0}, + { 0x1103c0, 0x0}, + { 0x2103c0, 0x0}, + { 0x104c0, 0x0}, + { 0x1104c0, 0x0}, + { 0x2104c0, 0x0}, + { 0x105c0, 0x0}, + { 0x1105c0, 0x0}, + { 0x2105c0, 0x0}, + { 0x106c0, 0x0}, + { 0x1106c0, 0x0}, + { 0x2106c0, 0x0}, + { 0x107c0, 0x0}, + { 0x1107c0, 0x0}, + { 0x2107c0, 0x0}, + { 0x108c0, 0x0}, + { 0x1108c0, 0x0}, + { 0x2108c0, 0x0}, + { 0x110c0, 0x0}, + { 0x1110c0, 0x0}, + { 0x2110c0, 0x0}, + { 0x111c0, 0x0}, + { 0x1111c0, 0x0}, + { 0x2111c0, 0x0}, + { 0x112c0, 0x0}, + { 0x1112c0, 0x0}, + { 0x2112c0, 0x0}, + { 0x113c0, 0x0}, + { 0x1113c0, 0x0}, + { 0x2113c0, 0x0}, + { 0x114c0, 0x0}, + { 0x1114c0, 0x0}, + { 0x2114c0, 0x0}, + { 0x115c0, 0x0}, + { 0x1115c0, 0x0}, + { 0x2115c0, 0x0}, + { 0x116c0, 0x0}, + { 0x1116c0, 0x0}, + { 0x2116c0, 0x0}, + { 0x117c0, 0x0}, + { 0x1117c0, 0x0}, + { 0x2117c0, 0x0}, + { 0x118c0, 0x0}, + { 0x1118c0, 0x0}, + { 0x2118c0, 0x0}, + { 0x120c0, 0x0}, + { 0x1120c0, 0x0}, + { 0x2120c0, 0x0}, + { 0x121c0, 0x0}, + { 0x1121c0, 0x0}, + { 0x2121c0, 0x0}, + { 0x122c0, 0x0}, + { 0x1122c0, 0x0}, + { 0x2122c0, 0x0}, + { 0x123c0, 0x0}, + { 0x1123c0, 0x0}, + { 0x2123c0, 0x0}, + { 0x124c0, 0x0}, + { 0x1124c0, 0x0}, + { 0x2124c0, 0x0}, + { 0x125c0, 0x0}, + { 0x1125c0, 0x0}, + { 0x2125c0, 0x0}, + { 0x126c0, 0x0}, + { 0x1126c0, 0x0}, + { 0x2126c0, 0x0}, + { 0x127c0, 0x0}, + { 0x1127c0, 0x0}, + { 0x2127c0, 0x0}, + { 0x128c0, 0x0}, + { 0x1128c0, 0x0}, + { 0x2128c0, 0x0}, + { 0x130c0, 0x0}, + { 0x1130c0, 0x0}, + { 0x2130c0, 0x0}, + { 0x131c0, 0x0}, + { 0x1131c0, 0x0}, + { 0x2131c0, 0x0}, + { 0x132c0, 0x0}, + { 0x1132c0, 0x0}, + { 0x2132c0, 0x0}, + { 0x133c0, 0x0}, + { 0x1133c0, 0x0}, + { 0x2133c0, 0x0}, + { 0x134c0, 0x0}, + { 0x1134c0, 0x0}, + { 0x2134c0, 0x0}, + { 0x135c0, 0x0}, + { 0x1135c0, 0x0}, + { 0x2135c0, 0x0}, + { 0x136c0, 0x0}, + { 0x1136c0, 0x0}, + { 0x2136c0, 0x0}, + { 0x137c0, 0x0}, + { 0x1137c0, 0x0}, + { 0x2137c0, 0x0}, + { 0x138c0, 0x0}, + { 0x1138c0, 0x0}, + { 0x2138c0, 0x0}, + { 0x100c1, 0x0}, + { 0x1100c1, 0x0}, + { 0x2100c1, 0x0}, + { 0x101c1, 0x0}, + { 0x1101c1, 0x0}, + { 0x2101c1, 0x0}, + { 0x102c1, 0x0}, + { 0x1102c1, 0x0}, + { 0x2102c1, 0x0}, + { 0x103c1, 0x0}, + { 0x1103c1, 0x0}, + { 0x2103c1, 0x0}, + { 0x104c1, 0x0}, + { 0x1104c1, 0x0}, + { 0x2104c1, 0x0}, + { 0x105c1, 0x0}, + { 0x1105c1, 0x0}, + { 0x2105c1, 0x0}, + { 0x106c1, 0x0}, + { 0x1106c1, 0x0}, + { 0x2106c1, 0x0}, + { 0x107c1, 0x0}, + { 0x1107c1, 0x0}, + { 0x2107c1, 0x0}, + { 0x108c1, 0x0}, + { 0x1108c1, 0x0}, + { 0x2108c1, 0x0}, + { 0x110c1, 0x0}, + { 0x1110c1, 0x0}, + { 0x2110c1, 0x0}, + { 0x111c1, 0x0}, + { 0x1111c1, 0x0}, + { 0x2111c1, 0x0}, + { 0x112c1, 0x0}, + { 0x1112c1, 0x0}, + { 0x2112c1, 0x0}, + { 0x113c1, 0x0}, + { 0x1113c1, 0x0}, + { 0x2113c1, 0x0}, + { 0x114c1, 0x0}, + { 0x1114c1, 0x0}, + { 0x2114c1, 0x0}, + { 0x115c1, 0x0}, + { 0x1115c1, 0x0}, + { 0x2115c1, 0x0}, + { 0x116c1, 0x0}, + { 0x1116c1, 0x0}, + { 0x2116c1, 0x0}, + { 0x117c1, 0x0}, + { 0x1117c1, 0x0}, + { 0x2117c1, 0x0}, + { 0x118c1, 0x0}, + { 0x1118c1, 0x0}, + { 0x2118c1, 0x0}, + { 0x120c1, 0x0}, + { 0x1120c1, 0x0}, + { 0x2120c1, 0x0}, + { 0x121c1, 0x0}, + { 0x1121c1, 0x0}, + { 0x2121c1, 0x0}, + { 0x122c1, 0x0}, + { 0x1122c1, 0x0}, + { 0x2122c1, 0x0}, + { 0x123c1, 0x0}, + { 0x1123c1, 0x0}, + { 0x2123c1, 0x0}, + { 0x124c1, 0x0}, + { 0x1124c1, 0x0}, + { 0x2124c1, 0x0}, + { 0x125c1, 0x0}, + { 0x1125c1, 0x0}, + { 0x2125c1, 0x0}, + { 0x126c1, 0x0}, + { 0x1126c1, 0x0}, + { 0x2126c1, 0x0}, + { 0x127c1, 0x0}, + { 0x1127c1, 0x0}, + { 0x2127c1, 0x0}, + { 0x128c1, 0x0}, + { 0x1128c1, 0x0}, + { 0x2128c1, 0x0}, + { 0x130c1, 0x0}, + { 0x1130c1, 0x0}, + { 0x2130c1, 0x0}, + { 0x131c1, 0x0}, + { 0x1131c1, 0x0}, + { 0x2131c1, 0x0}, + { 0x132c1, 0x0}, + { 0x1132c1, 0x0}, + { 0x2132c1, 0x0}, + { 0x133c1, 0x0}, + { 0x1133c1, 0x0}, + { 0x2133c1, 0x0}, + { 0x134c1, 0x0}, + { 0x1134c1, 0x0}, + { 0x2134c1, 0x0}, + { 0x135c1, 0x0}, + { 0x1135c1, 0x0}, + { 0x2135c1, 0x0}, + { 0x136c1, 0x0}, + { 0x1136c1, 0x0}, + { 0x2136c1, 0x0}, + { 0x137c1, 0x0}, + { 0x1137c1, 0x0}, + { 0x2137c1, 0x0}, + { 0x138c1, 0x0}, + { 0x1138c1, 0x0}, + { 0x2138c1, 0x0}, + { 0x10020, 0x0}, + { 0x110020, 0x0}, + { 0x210020, 0x0}, + { 0x11020, 0x0}, + { 0x111020, 0x0}, + { 0x211020, 0x0}, + { 0x12020, 0x0}, + { 0x112020, 0x0}, + { 0x212020, 0x0}, + { 0x13020, 0x0}, + { 0x113020, 0x0}, + { 0x213020, 0x0}, + { 0x20072, 0x0}, + { 0x20073, 0x0}, + { 0x20074, 0x0}, + { 0x100aa, 0x0}, + { 0x110aa, 0x0}, + { 0x120aa, 0x0}, + { 0x130aa, 0x0}, + { 0x20010, 0x0}, + { 0x120010, 0x0}, + { 0x220010, 0x0}, + { 0x20011, 0x0}, + { 0x120011, 0x0}, + { 0x220011, 0x0}, + { 0x100ae, 0x0}, + { 0x1100ae, 0x0}, + { 0x2100ae, 0x0}, + { 0x100af, 0x0}, + { 0x1100af, 0x0}, + { 0x2100af, 0x0}, + { 0x110ae, 0x0}, + { 0x1110ae, 0x0}, + { 0x2110ae, 0x0}, + { 0x110af, 0x0}, + { 0x1110af, 0x0}, + { 0x2110af, 0x0}, + { 0x120ae, 0x0}, + { 0x1120ae, 0x0}, + { 0x2120ae, 0x0}, + { 0x120af, 0x0}, + { 0x1120af, 0x0}, + { 0x2120af, 0x0}, + { 0x130ae, 0x0}, + { 0x1130ae, 0x0}, + { 0x2130ae, 0x0}, + { 0x130af, 0x0}, + { 0x1130af, 0x0}, + { 0x2130af, 0x0}, + { 0x20020, 0x0}, + { 0x120020, 0x0}, + { 0x220020, 0x0}, + { 0x100a0, 0x0}, + { 0x100a1, 0x0}, + { 0x100a2, 0x0}, + { 0x100a3, 0x0}, + { 0x100a4, 0x0}, + { 0x100a5, 0x0}, + { 0x100a6, 0x0}, + { 0x100a7, 0x0}, + { 0x110a0, 0x0}, + { 0x110a1, 0x0}, + { 0x110a2, 0x0}, + { 0x110a3, 0x0}, + { 0x110a4, 0x0}, + { 0x110a5, 0x0}, + { 0x110a6, 0x0}, + { 0x110a7, 0x0}, + { 0x120a0, 0x0}, + { 0x120a1, 0x0}, + { 0x120a2, 0x0}, + { 0x120a3, 0x0}, + { 0x120a4, 0x0}, + { 0x120a5, 0x0}, + { 0x120a6, 0x0}, + { 0x120a7, 0x0}, + { 0x130a0, 0x0}, + { 0x130a1, 0x0}, + { 0x130a2, 0x0}, + { 0x130a3, 0x0}, + { 0x130a4, 0x0}, + { 0x130a5, 0x0}, + { 0x130a6, 0x0}, + { 0x130a7, 0x0}, + { 0x2007c, 0x0}, + { 0x12007c, 0x0}, + { 0x22007c, 0x0}, + { 0x2007d, 0x0}, + { 0x12007d, 0x0}, + { 0x22007d, 0x0}, + { 0x400fd, 0x0}, + { 0x400c0, 0x0}, + { 0x90201, 0x0}, + { 0x190201, 0x0}, + { 0x290201, 0x0}, + { 0x90202, 0x0}, + { 0x190202, 0x0}, + { 0x290202, 0x0}, + { 0x90203, 0x0}, + { 0x190203, 0x0}, + { 0x290203, 0x0}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x90205, 0x0}, + { 0x190205, 0x0}, + { 0x290205, 0x0}, + { 0x90206, 0x0}, + { 0x190206, 0x0}, + { 0x290206, 0x0}, + { 0x90207, 0x0}, + { 0x190207, 0x0}, + { 0x290207, 0x0}, + { 0x90208, 0x0}, + { 0x190208, 0x0}, + { 0x290208, 0x0}, + { 0x10062, 0x0}, + { 0x10162, 0x0}, + { 0x10262, 0x0}, + { 0x10362, 0x0}, + { 0x10462, 0x0}, + { 0x10562, 0x0}, + { 0x10662, 0x0}, + { 0x10762, 0x0}, + { 0x10862, 0x0}, + { 0x11062, 0x0}, + { 0x11162, 0x0}, + { 0x11262, 0x0}, + { 0x11362, 0x0}, + { 0x11462, 0x0}, + { 0x11562, 0x0}, + { 0x11662, 0x0}, + { 0x11762, 0x0}, + { 0x11862, 0x0}, + { 0x12062, 0x0}, + { 0x12162, 0x0}, + { 0x12262, 0x0}, + { 0x12362, 0x0}, + { 0x12462, 0x0}, + { 0x12562, 0x0}, + { 0x12662, 0x0}, + { 0x12762, 0x0}, + { 0x12862, 0x0}, + { 0x13062, 0x0}, + { 0x13162, 0x0}, + { 0x13262, 0x0}, + { 0x13362, 0x0}, + { 0x13462, 0x0}, + { 0x13562, 0x0}, + { 0x13662, 0x0}, + { 0x13762, 0x0}, + { 0x13862, 0x0}, + { 0x20077, 0x0}, + { 0x10001, 0x0}, + { 0x11001, 0x0}, + { 0x12001, 0x0}, + { 0x13001, 0x0}, + { 0x10040, 0x0}, + { 0x10140, 0x0}, + { 0x10240, 0x0}, + { 0x10340, 0x0}, + { 0x10440, 0x0}, + { 0x10540, 0x0}, + { 0x10640, 0x0}, + { 0x10740, 0x0}, + { 0x10840, 0x0}, + { 0x10030, 0x0}, + { 0x10130, 0x0}, + { 0x10230, 0x0}, + { 0x10330, 0x0}, + { 0x10430, 0x0}, + { 0x10530, 0x0}, + { 0x10630, 0x0}, + { 0x10730, 0x0}, + { 0x10830, 0x0}, + { 0x11040, 0x0}, + { 0x11140, 0x0}, + { 0x11240, 0x0}, + { 0x11340, 0x0}, + { 0x11440, 0x0}, + { 0x11540, 0x0}, + { 0x11640, 0x0}, + { 0x11740, 0x0}, + { 0x11840, 0x0}, + { 0x11030, 0x0}, + { 0x11130, 0x0}, + { 0x11230, 0x0}, + { 0x11330, 0x0}, + { 0x11430, 0x0}, + { 0x11530, 0x0}, + { 0x11630, 0x0}, + { 0x11730, 0x0}, + { 0x11830, 0x0}, + { 0x12040, 0x0}, + { 0x12140, 0x0}, + { 0x12240, 0x0}, + { 0x12340, 0x0}, + { 0x12440, 0x0}, + { 0x12540, 0x0}, + { 0x12640, 0x0}, + { 0x12740, 0x0}, + { 0x12840, 0x0}, + { 0x12030, 0x0}, + { 0x12130, 0x0}, + { 0x12230, 0x0}, + { 0x12330, 0x0}, + { 0x12430, 0x0}, + { 0x12530, 0x0}, + { 0x12630, 0x0}, + { 0x12730, 0x0}, + { 0x12830, 0x0}, + { 0x13040, 0x0}, + { 0x13140, 0x0}, + { 0x13240, 0x0}, + { 0x13340, 0x0}, + { 0x13440, 0x0}, + { 0x13540, 0x0}, + { 0x13640, 0x0}, + { 0x13740, 0x0}, + { 0x13840, 0x0}, + { 0x13030, 0x0}, + { 0x13130, 0x0}, + { 0x13230, 0x0}, + { 0x13330, 0x0}, + { 0x13430, 0x0}, + { 0x13530, 0x0}, + { 0x13630, 0x0}, + { 0x13730, 0x0}, + { 0x13830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xbb8}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x310}, + {0x54019, 0x2dd4}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x2dd4}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0xd400}, + {0x54033, 0x312d}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0xd400}, + {0x54039, 0x312d}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x101}, + {0x54003, 0x190}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x310}, + {0x54019, 0x84}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x84}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0x8400}, + {0x54033, 0x3100}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0x8400}, + {0x54039, 0x3100}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x64}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x310}, + {0x54019, 0x84}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x84}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0x8400}, + {0x54033, 0x3100}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0x8400}, + {0x54039, 0x3100}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xbb8}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54010, 0x1f7f}, + {0x54012, 0x310}, + {0x54019, 0x2dd4}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x2dd4}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0xd400}, + {0x54033, 0x312d}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0xd400}, + {0x54039, 0x312d}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xf}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x630}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x630}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x630}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x630}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x630}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x630}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x630}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x630}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x630}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x630}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x630}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x630}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x630}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xa}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x2}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x900a4, 0x10}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x623}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x623}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x790}, + {0x900a9, 0x11a}, + {0x900aa, 0x8}, + {0x900ab, 0x7aa}, + {0x900ac, 0x2a}, + {0x900ad, 0x10}, + {0x900ae, 0x7b2}, + {0x900af, 0x2a}, + {0x900b0, 0x0}, + {0x900b1, 0x7c8}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x0}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xc}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x0}, + {0x90169, 0x8}, + {0x9016a, 0x8}, + {0x9016b, 0x448}, + {0x9016c, 0x109}, + {0x9016d, 0xf}, + {0x9016e, 0x7c0}, + {0x9016f, 0x109}, + {0x90170, 0x0}, + {0x90171, 0xe8}, + {0x90172, 0x109}, + {0x90173, 0x47}, + {0x90174, 0x630}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0x618}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0xe0}, + {0x9017b, 0x109}, + {0x9017c, 0x0}, + {0x9017d, 0x7c8}, + {0x9017e, 0x109}, + {0x9017f, 0x8}, + {0x90180, 0x8140}, + {0x90181, 0x10c}, + {0x90182, 0x0}, + {0x90183, 0x1}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x4}, + {0x90187, 0x8}, + {0x90188, 0x8}, + {0x90189, 0x7c8}, + {0x9018a, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2a}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x5d}, + {0x2000c, 0xbb}, + {0x2000d, 0x753}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x60}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x220010, 0x5a}, + {0x220011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x12011, 0x1}, + {0x12012, 0x1}, + {0x12013, 0x180}, + {0x12018, 0x1}, + {0x12002, 0x6209}, + {0x120b2, 0x1}, + {0x121b4, 0x1}, + {0x122b4, 0x1}, + {0x123b4, 0x1}, + {0x124b4, 0x1}, + {0x125b4, 0x1}, + {0x126b4, 0x1}, + {0x127b4, 0x1}, + {0x128b4, 0x1}, + {0x13011, 0x1}, + {0x13012, 0x1}, + {0x13013, 0x180}, + {0x13018, 0x1}, + {0x13002, 0x6209}, + {0x130b2, 0x1}, + {0x131b4, 0x1}, + {0x132b4, 0x1}, + {0x133b4, 0x1}, + {0x134b4, 0x1}, + {0x135b4, 0x1}, + {0x136b4, 0x1}, + {0x137b4, 0x1}, + {0x138b4, 0x1}, + {0x2003a, 0x2}, + {0xc0080, 0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_ff020008 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c new file mode 100644 index 000000000..eabcc842a --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Copyright 2020 Linaro + */ + +#include <common.h> +#include <env.h> +#include <init.h> +#include <miiphy.h> +#include <netdev.h> + +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int setup_fec(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) { + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); + } + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) { + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + } + return 0; +} + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", "IOT-GATE-IMX8"); + env_set("board_rev", "SBC-IOTMX8"); + } + + return 0; +} diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg new file mode 100644 index 000000000..b89092a55 --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#define __ASSEMBLY__ + +BOOT_FROM sd +LOADER mkimage.flash.mkimage 0x7E1000 diff --git a/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/spl.c b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/spl.c new file mode 100644 index 000000000..8f592457d --- /dev/null +++ b/roms/u-boot/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2020 Linaro + */ + +#include <common.h> +#include <command.h> +#include <cpu_func.h> +#include <hang.h> +#include <image.h> +#include <init.h> +#include <log.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx8mm_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/mach-imx/gpio.h> +#include <asm/arch/ddr.h> + +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> + +#include <power/pmic.h> +#include <power/bd71837.h> + +#include "ddr/ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + default: + return BOOT_DEVICE_NONE; + } +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MM_PAD_I2C2_SCL_I2C2_SCL | PC, + .gpio_mode = IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 | PC, + .gp = IMX_GPIO_NR(5, 16), + }, + .sda = { + .i2c_mode = IMX8MM_PAD_I2C2_SDA_I2C2_SDA | PC, + .gpio_mode = IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 | PC, + .gp = IMX_GPIO_NR(5, 17), + }, +}; + +static void spl_dram_init(void) +{ + spl_dram_init_compulab(); +} + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +static int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@4b", &dev); + if (ret == -ENODEV) { + puts("No pmic\n"); + return 0; + } + if (ret != 0) + return ret; + + /* decrease RESET key long push time from the default 10s to 10ms */ + pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); + + /* unlock the PMIC regs */ + pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); + + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); + + /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ + pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); + + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); + + /* lock the PMIC regs */ + pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); + + return 0; +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + arch_cpu_init(); + + board_early_init_f(); + + init_uart_clk(2); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); + hang(); + } + + enable_tzc380(); + + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/roms/u-boot/board/compulab/trimslice/Kconfig b/roms/u-boot/board/compulab/trimslice/Kconfig new file mode 100644 index 000000000..357691403 --- /dev/null +++ b/roms/u-boot/board/compulab/trimslice/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TRIMSLICE + +config SYS_BOARD + default "trimslice" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "trimslice" + +endif diff --git a/roms/u-boot/board/compulab/trimslice/MAINTAINERS b/roms/u-boot/board/compulab/trimslice/MAINTAINERS new file mode 100644 index 000000000..85b120017 --- /dev/null +++ b/roms/u-boot/board/compulab/trimslice/MAINTAINERS @@ -0,0 +1,7 @@ +TRIMSLICE BOARD +M: Tom Warren <twarren@nvidia.com> +M: Stephen Warren <swarren@nvidia.com> +S: Maintained +F: board/compulab/trimslice/ +F: include/configs/trimslice.h +F: configs/trimslice_defconfig diff --git a/roms/u-boot/board/compulab/trimslice/Makefile b/roms/u-boot/board/compulab/trimslice/Makefile new file mode 100644 index 000000000..abdf47191 --- /dev/null +++ b/roms/u-boot/board/compulab/trimslice/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> + +obj-y := trimslice.o diff --git a/roms/u-boot/board/compulab/trimslice/trimslice.c b/roms/u-boot/board/compulab/trimslice/trimslice.c new file mode 100644 index 000000000..21ff0cda7 --- /dev/null +++ b/roms/u-boot/board/compulab/trimslice/trimslice.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/tegra.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/pinmux.h> +#include <asm/gpio.h> +#include <i2c.h> + +void pin_mux_usb(void) +{ + /* + * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO + * in the current device tree. + */ + pinmux_tristate_disable(PMUX_PINGRP_UAC); +} + +void pin_mux_spi(void) +{ + funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); + + /* For CD GPIO PP1 */ + pinmux_tristate_disable(PMUX_PINGRP_DAP3); +} |