diff options
Diffstat (limited to 'roms/u-boot/board/coreboot')
| -rw-r--r-- | roms/u-boot/board/coreboot/Kconfig | 25 | ||||
| -rw-r--r-- | roms/u-boot/board/coreboot/coreboot/Kconfig | 34 | ||||
| -rw-r--r-- | roms/u-boot/board/coreboot/coreboot/MAINTAINERS | 13 | ||||
| -rw-r--r-- | roms/u-boot/board/coreboot/coreboot/Makefile | 13 | ||||
| -rw-r--r-- | roms/u-boot/board/coreboot/coreboot/coreboot.c | 64 |
5 files changed, 149 insertions, 0 deletions
diff --git a/roms/u-boot/board/coreboot/Kconfig b/roms/u-boot/board/coreboot/Kconfig new file mode 100644 index 000000000..05a72d3c5 --- /dev/null +++ b/roms/u-boot/board/coreboot/Kconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + +if VENDOR_COREBOOT + +choice + prompt "Mainboard model" + optional + +config TARGET_COREBOOT + bool "coreboot" + help + This target is used for running U-Boot on top of coreboot. In + this case coreboot does the early inititalisation, and U-Boot + takes over once the RAM, video and CPU are fully running. + U-Boot is loaded as a fallback payload from coreboot, in + coreboot terminology. This method was used for the Chromebook + Pixel when launched. + +endchoice + +source "board/coreboot/coreboot/Kconfig" + +endif diff --git a/roms/u-boot/board/coreboot/coreboot/Kconfig b/roms/u-boot/board/coreboot/coreboot/Kconfig new file mode 100644 index 000000000..5bd6465d9 --- /dev/null +++ b/roms/u-boot/board/coreboot/coreboot/Kconfig @@ -0,0 +1,34 @@ +if TARGET_COREBOOT + +config SYS_BOARD + default "coreboot" + +config SYS_VENDOR + default "coreboot" + +config SYS_SOC + default "coreboot" + +config SYS_CONFIG_NAME + default "coreboot" + +config SYS_TEXT_BASE + default 0x01110000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_EARLY_INIT_R + +config SYS_CAR_ADDR + hex "Board specific Cache-As-RAM (CAR) address" + default 0x01920000 + help + This option specifies the board specific Cache-As-RAM (CAR) address. + +config SYS_CAR_SIZE + hex "Board specific Cache-As-RAM (CAR) size" + default 0x4000 + help + This option specifies the board specific Cache-As-RAM (CAR) size. + +endif diff --git a/roms/u-boot/board/coreboot/coreboot/MAINTAINERS b/roms/u-boot/board/coreboot/coreboot/MAINTAINERS new file mode 100644 index 000000000..a05673bb0 --- /dev/null +++ b/roms/u-boot/board/coreboot/coreboot/MAINTAINERS @@ -0,0 +1,13 @@ +COREBOOT BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/coreboot/coreboot/ +F: include/configs/chromebook_link.h +F: configs/coreboot_defconfig + +COREBOOT64 BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/coreboot/coreboot/ +F: include/configs/chromebook_link.h +F: configs/coreboot64_defconfig diff --git a/roms/u-boot/board/coreboot/coreboot/Makefile b/roms/u-boot/board/coreboot/coreboot/Makefile new file mode 100644 index 000000000..d292b7032 --- /dev/null +++ b/roms/u-boot/board/coreboot/coreboot/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2011 The Chromium OS Authors. +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + +obj-y += coreboot.o diff --git a/roms/u-boot/board/coreboot/coreboot/coreboot.c b/roms/u-boot/board/coreboot/coreboot/coreboot.c new file mode 100644 index 000000000..175d3ce69 --- /dev/null +++ b/roms/u-boot/board/coreboot/coreboot/coreboot.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <asm/cb_sysinfo.h> +#include <asm/global_data.h> +#include <init.h> +#include <smbios.h> + +int board_early_init_r(void) +{ + /* + * Make sure PCI bus is enumerated so that peripherals on the PCI bus + * can be discovered by their drivers + */ + pci_init(); + + return 0; +} + +#ifdef CONFIG_SMBIOS_PARSER +int show_board_info(void) +{ + const struct smbios_entry *smbios = smbios_entry(lib_sysinfo.smbios_start, lib_sysinfo.smbios_size); + + if (!smbios) + goto fallback; + + const struct smbios_header *bios = smbios_header(smbios, SMBIOS_BIOS_INFORMATION); + const struct smbios_header *system = smbios_header(smbios, SMBIOS_SYSTEM_INFORMATION); + const struct smbios_type0 *t0 = (struct smbios_type0 *)bios; + const struct smbios_type1 *t1 = (struct smbios_type1 *)system; + + if (!t0 || !t1) + goto fallback; + + const char *bios_ver = smbios_string(bios, t0->bios_ver); + const char *model = smbios_string(system, t1->product_name); + const char *manufacturer = smbios_string(system, t1->manufacturer); + + if (!model || !manufacturer || !bios_ver) + goto fallback; + + printf("Vendor: %s\n", manufacturer); + printf("Model: %s\n", model); + printf("BIOS Version: %s\n", bios_ver); + + return 0; + +fallback: +#ifdef CONFIG_OF_CONTROL + DECLARE_GLOBAL_DATA_PTR; + + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + + if (model) + printf("Model: %s\n", model); +#endif + + return checkboard(); +} +#endif |